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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.05 95.42 93.80 95.40 94.64 97.53 99.51


Total test records in report: 2939
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T2763 /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3101842547 Jul 29 08:02:47 PM PDT 24 Jul 29 08:09:43 PM PDT 24 24543624462 ps
T2764 /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.1819332595 Jul 29 08:03:43 PM PDT 24 Jul 29 08:03:48 PM PDT 24 20156195 ps
T2765 /workspace/coverage/cover_reg_top/57.xbar_smoke.2450152636 Jul 29 07:59:29 PM PDT 24 Jul 29 07:59:36 PM PDT 24 56762868 ps
T2766 /workspace/coverage/cover_reg_top/2.chip_tl_errors.3736856769 Jul 29 07:49:50 PM PDT 24 Jul 29 07:53:33 PM PDT 24 3136741932 ps
T2767 /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.3107224970 Jul 29 07:59:03 PM PDT 24 Jul 29 07:59:47 PM PDT 24 1262494900 ps
T2768 /workspace/coverage/cover_reg_top/41.xbar_stress_all.733323874 Jul 29 07:57:02 PM PDT 24 Jul 29 08:05:47 PM PDT 24 12823040943 ps
T2769 /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.1793430806 Jul 29 07:50:15 PM PDT 24 Jul 29 07:50:22 PM PDT 24 54335313 ps
T2770 /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.3964166067 Jul 29 08:05:23 PM PDT 24 Jul 29 08:06:05 PM PDT 24 1070080749 ps
T2771 /workspace/coverage/cover_reg_top/86.xbar_smoke.3529447531 Jul 29 08:04:12 PM PDT 24 Jul 29 08:04:22 PM PDT 24 247199537 ps
T2772 /workspace/coverage/cover_reg_top/22.xbar_smoke.3715626743 Jul 29 07:52:58 PM PDT 24 Jul 29 07:53:06 PM PDT 24 145492996 ps
T2773 /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.2609904725 Jul 29 07:56:54 PM PDT 24 Jul 29 07:58:47 PM PDT 24 11054578048 ps
T2774 /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.3074993284 Jul 29 08:02:28 PM PDT 24 Jul 29 08:03:42 PM PDT 24 6732090702 ps
T2775 /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.1078903792 Jul 29 07:56:22 PM PDT 24 Jul 29 08:08:38 PM PDT 24 69300891312 ps
T2776 /workspace/coverage/cover_reg_top/70.xbar_access_same_device.2738514898 Jul 29 08:01:46 PM PDT 24 Jul 29 08:03:12 PM PDT 24 2361020975 ps
T2777 /workspace/coverage/cover_reg_top/10.xbar_smoke.2420373780 Jul 29 07:50:20 PM PDT 24 Jul 29 07:50:28 PM PDT 24 149124924 ps
T2778 /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.3401379773 Jul 29 08:01:40 PM PDT 24 Jul 29 08:02:24 PM PDT 24 504998461 ps
T2779 /workspace/coverage/cover_reg_top/47.xbar_stress_all.2533102955 Jul 29 07:58:00 PM PDT 24 Jul 29 08:00:46 PM PDT 24 2266230223 ps
T2780 /workspace/coverage/cover_reg_top/33.xbar_random.3769749616 Jul 29 07:55:20 PM PDT 24 Jul 29 07:55:58 PM PDT 24 1158922667 ps
T2781 /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.2870785765 Jul 29 08:04:44 PM PDT 24 Jul 29 08:06:05 PM PDT 24 4866686032 ps
T2782 /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.2838092129 Jul 29 07:57:21 PM PDT 24 Jul 29 08:20:04 PM PDT 24 76666333969 ps
T2783 /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.172685205 Jul 29 08:04:37 PM PDT 24 Jul 29 08:04:43 PM PDT 24 45596295 ps
T2784 /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.3193227852 Jul 29 08:05:18 PM PDT 24 Jul 29 08:17:07 PM PDT 24 19091475000 ps
T2785 /workspace/coverage/cover_reg_top/38.xbar_access_same_device.673849324 Jul 29 07:56:21 PM PDT 24 Jul 29 07:56:44 PM PDT 24 594047686 ps
T2786 /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.526464817 Jul 29 08:00:39 PM PDT 24 Jul 29 08:01:04 PM PDT 24 275287927 ps
T2787 /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.4085144448 Jul 29 08:05:19 PM PDT 24 Jul 29 08:10:36 PM PDT 24 9373470217 ps
T2788 /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.1119846743 Jul 29 08:05:49 PM PDT 24 Jul 29 08:46:33 PM PDT 24 136024401510 ps
T2789 /workspace/coverage/cover_reg_top/69.xbar_smoke.2432948346 Jul 29 08:01:29 PM PDT 24 Jul 29 08:01:36 PM PDT 24 49986136 ps
T2790 /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.1028553920 Jul 29 07:52:34 PM PDT 24 Jul 29 07:54:32 PM PDT 24 10947869231 ps
T2791 /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.2416153119 Jul 29 07:58:10 PM PDT 24 Jul 29 07:59:21 PM PDT 24 6751664097 ps
T2792 /workspace/coverage/cover_reg_top/73.xbar_smoke.1636448021 Jul 29 08:02:04 PM PDT 24 Jul 29 08:02:10 PM PDT 24 37082345 ps
T2793 /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.994746623 Jul 29 07:53:06 PM PDT 24 Jul 29 07:53:13 PM PDT 24 97991639 ps
T2794 /workspace/coverage/cover_reg_top/84.xbar_smoke.1975234237 Jul 29 08:03:54 PM PDT 24 Jul 29 08:04:00 PM PDT 24 46042611 ps
T2795 /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.1976414003 Jul 29 08:05:46 PM PDT 24 Jul 29 08:07:23 PM PDT 24 9864724414 ps
T2796 /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.3329605436 Jul 29 07:54:48 PM PDT 24 Jul 29 07:55:20 PM PDT 24 370774768 ps
T2797 /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.921229595 Jul 29 07:58:36 PM PDT 24 Jul 29 08:18:06 PM PDT 24 70630725762 ps
T2798 /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.8564853 Jul 29 07:58:26 PM PDT 24 Jul 29 07:59:52 PM PDT 24 8309719075 ps
T2799 /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.2047668427 Jul 29 07:59:43 PM PDT 24 Jul 29 08:00:58 PM PDT 24 7270718708 ps
T2800 /workspace/coverage/cover_reg_top/19.chip_csr_rw.2988692276 Jul 29 07:52:34 PM PDT 24 Jul 29 07:58:06 PM PDT 24 3843597950 ps
T2801 /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.2466994133 Jul 29 07:50:21 PM PDT 24 Jul 29 07:50:31 PM PDT 24 64772825 ps
T2802 /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.1245161939 Jul 29 08:02:20 PM PDT 24 Jul 29 08:06:42 PM PDT 24 847847741 ps
T2803 /workspace/coverage/cover_reg_top/32.xbar_same_source.3453869128 Jul 29 07:55:10 PM PDT 24 Jul 29 07:55:33 PM PDT 24 312711678 ps
T2804 /workspace/coverage/cover_reg_top/71.xbar_access_same_device.4086354917 Jul 29 08:01:49 PM PDT 24 Jul 29 08:02:56 PM PDT 24 883531959 ps
T2805 /workspace/coverage/cover_reg_top/8.xbar_stress_all.2858647629 Jul 29 07:50:13 PM PDT 24 Jul 29 07:53:55 PM PDT 24 5890080482 ps
T2806 /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.3956875150 Jul 29 08:02:04 PM PDT 24 Jul 29 08:02:37 PM PDT 24 281925167 ps
T2807 /workspace/coverage/cover_reg_top/9.xbar_smoke.2806981090 Jul 29 07:50:12 PM PDT 24 Jul 29 07:50:18 PM PDT 24 36861699 ps
T2808 /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1063940183 Jul 29 07:55:37 PM PDT 24 Jul 29 07:56:21 PM PDT 24 1060936051 ps
T2809 /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.3125221363 Jul 29 08:02:13 PM PDT 24 Jul 29 08:21:05 PM PDT 24 63642132847 ps
T2810 /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.1498686840 Jul 29 08:04:37 PM PDT 24 Jul 29 08:11:09 PM PDT 24 3615118981 ps
T2811 /workspace/coverage/cover_reg_top/76.xbar_access_same_device.4242080662 Jul 29 08:02:39 PM PDT 24 Jul 29 08:03:51 PM PDT 24 1082317551 ps
T2812 /workspace/coverage/cover_reg_top/51.xbar_smoke.879372324 Jul 29 07:58:32 PM PDT 24 Jul 29 07:58:41 PM PDT 24 192142790 ps
T2813 /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.3594500264 Jul 29 07:50:08 PM PDT 24 Jul 29 08:01:38 PM PDT 24 61777735237 ps
T2814 /workspace/coverage/cover_reg_top/68.xbar_error_random.1136472629 Jul 29 08:01:30 PM PDT 24 Jul 29 08:02:00 PM PDT 24 847233925 ps
T2815 /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.2253795630 Jul 29 07:57:30 PM PDT 24 Jul 29 07:57:39 PM PDT 24 53164355 ps
T2816 /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.2070617816 Jul 29 07:59:42 PM PDT 24 Jul 29 07:59:46 PM PDT 24 6865403 ps
T2817 /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.3559351579 Jul 29 07:58:10 PM PDT 24 Jul 29 08:01:14 PM PDT 24 11406253760 ps
T2818 /workspace/coverage/cover_reg_top/24.xbar_smoke.4281453533 Jul 29 07:53:21 PM PDT 24 Jul 29 07:53:28 PM PDT 24 141050866 ps
T2819 /workspace/coverage/cover_reg_top/12.xbar_same_source.4247206171 Jul 29 07:50:41 PM PDT 24 Jul 29 07:51:01 PM PDT 24 261914788 ps
T2820 /workspace/coverage/cover_reg_top/6.xbar_stress_all.2243127409 Jul 29 07:50:02 PM PDT 24 Jul 29 07:51:52 PM PDT 24 2891764798 ps
T2821 /workspace/coverage/cover_reg_top/20.xbar_smoke.3907785651 Jul 29 07:52:35 PM PDT 24 Jul 29 07:52:42 PM PDT 24 127547695 ps
T2822 /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.1348716858 Jul 29 07:56:36 PM PDT 24 Jul 29 08:14:03 PM PDT 24 103867882544 ps
T2823 /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.836367294 Jul 29 07:57:15 PM PDT 24 Jul 29 08:10:49 PM PDT 24 46615838823 ps
T2824 /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.2757130810 Jul 29 07:53:32 PM PDT 24 Jul 29 08:10:12 PM PDT 24 57853727892 ps
T2825 /workspace/coverage/cover_reg_top/61.xbar_error_random.3437580462 Jul 29 08:00:27 PM PDT 24 Jul 29 08:01:17 PM PDT 24 1448696258 ps
T2826 /workspace/coverage/cover_reg_top/38.xbar_smoke.2803002825 Jul 29 07:56:22 PM PDT 24 Jul 29 07:56:31 PM PDT 24 182866166 ps
T2827 /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.1299552806 Jul 29 08:03:02 PM PDT 24 Jul 29 08:05:36 PM PDT 24 2358576844 ps
T2828 /workspace/coverage/cover_reg_top/38.xbar_random.2164252052 Jul 29 07:56:22 PM PDT 24 Jul 29 07:56:55 PM PDT 24 814112158 ps
T2829 /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.1592535634 Jul 29 07:50:01 PM PDT 24 Jul 29 07:58:03 PM PDT 24 5961874940 ps
T2830 /workspace/coverage/cover_reg_top/51.xbar_error_random.2850211288 Jul 29 07:58:38 PM PDT 24 Jul 29 07:59:18 PM PDT 24 602036424 ps
T2831 /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.1005859016 Jul 29 08:03:03 PM PDT 24 Jul 29 08:13:12 PM PDT 24 3870092303 ps
T2832 /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.228307844 Jul 29 07:57:28 PM PDT 24 Jul 29 08:01:49 PM PDT 24 6727290598 ps
T2833 /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2999844136 Jul 29 07:49:52 PM PDT 24 Jul 29 07:51:23 PM PDT 24 5302020624 ps
T2834 /workspace/coverage/cover_reg_top/54.xbar_error_random.2214923741 Jul 29 07:59:19 PM PDT 24 Jul 29 08:00:15 PM PDT 24 1783959820 ps
T2835 /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.4018467026 Jul 29 08:01:17 PM PDT 24 Jul 29 08:01:38 PM PDT 24 193279224 ps
T2836 /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2120389259 Jul 29 07:50:01 PM PDT 24 Jul 29 08:13:51 PM PDT 24 87523519771 ps
T2837 /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.2731039848 Jul 29 08:02:08 PM PDT 24 Jul 29 08:13:28 PM PDT 24 6346210741 ps
T2838 /workspace/coverage/cover_reg_top/87.xbar_error_random.1544676597 Jul 29 08:04:29 PM PDT 24 Jul 29 08:05:37 PM PDT 24 1845584601 ps
T2839 /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1280041266 Jul 29 07:50:41 PM PDT 24 Jul 29 08:06:14 PM PDT 24 96354326407 ps
T2840 /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.2152646068 Jul 29 08:06:32 PM PDT 24 Jul 29 08:13:49 PM PDT 24 6555719707 ps
T2841 /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.3234166160 Jul 29 08:04:48 PM PDT 24 Jul 29 08:05:23 PM PDT 24 430132071 ps
T2842 /workspace/coverage/cover_reg_top/18.xbar_smoke.837361024 Jul 29 07:52:16 PM PDT 24 Jul 29 07:52:23 PM PDT 24 46692038 ps
T2843 /workspace/coverage/cover_reg_top/40.xbar_smoke.1162482821 Jul 29 07:56:37 PM PDT 24 Jul 29 07:56:45 PM PDT 24 135392898 ps
T2844 /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.1809742887 Jul 29 08:05:35 PM PDT 24 Jul 29 08:06:12 PM PDT 24 338250060 ps
T2845 /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3701206688 Jul 29 07:50:41 PM PDT 24 Jul 29 07:59:34 PM PDT 24 50406023421 ps
T2846 /workspace/coverage/cover_reg_top/17.xbar_random.2738315137 Jul 29 07:52:07 PM PDT 24 Jul 29 07:52:44 PM PDT 24 970955454 ps
T2847 /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3336502502 Jul 29 07:50:46 PM PDT 24 Jul 29 08:53:30 PM PDT 24 29620886892 ps
T457 /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.1718399998 Jul 29 07:50:27 PM PDT 24 Jul 29 08:57:48 PM PDT 24 30526685154 ps
T2848 /workspace/coverage/cover_reg_top/37.xbar_access_same_device.3397195353 Jul 29 07:56:10 PM PDT 24 Jul 29 07:58:23 PM PDT 24 3042799675 ps
T2849 /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.320882342 Jul 29 08:03:58 PM PDT 24 Jul 29 08:25:15 PM PDT 24 73850770798 ps
T2850 /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.2926737841 Jul 29 08:00:22 PM PDT 24 Jul 29 08:00:50 PM PDT 24 297981441 ps
T2851 /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.579221185 Jul 29 08:03:18 PM PDT 24 Jul 29 08:41:36 PM PDT 24 132797493102 ps
T2852 /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.542246785 Jul 29 07:59:23 PM PDT 24 Jul 29 08:01:39 PM PDT 24 11706279926 ps
T2853 /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.3796876357 Jul 29 07:56:48 PM PDT 24 Jul 29 08:00:12 PM PDT 24 18142931437 ps
T2854 /workspace/coverage/cover_reg_top/98.xbar_error_random.2820101953 Jul 29 08:06:15 PM PDT 24 Jul 29 08:07:10 PM PDT 24 1538882005 ps
T2855 /workspace/coverage/cover_reg_top/55.xbar_same_source.4262604000 Jul 29 07:59:09 PM PDT 24 Jul 29 07:59:36 PM PDT 24 904515687 ps
T2856 /workspace/coverage/cover_reg_top/99.xbar_stress_all.951316264 Jul 29 08:06:32 PM PDT 24 Jul 29 08:07:18 PM PDT 24 464219177 ps
T2857 /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.1972453606 Jul 29 08:05:40 PM PDT 24 Jul 29 08:11:54 PM PDT 24 6237682702 ps
T2858 /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.3345645504 Jul 29 08:05:13 PM PDT 24 Jul 29 08:06:33 PM PDT 24 5030913030 ps
T2859 /workspace/coverage/cover_reg_top/44.xbar_smoke.2135626087 Jul 29 07:57:13 PM PDT 24 Jul 29 07:57:19 PM PDT 24 33035862 ps
T2860 /workspace/coverage/cover_reg_top/67.xbar_smoke.689477722 Jul 29 08:01:20 PM PDT 24 Jul 29 08:01:29 PM PDT 24 220431636 ps
T2861 /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.1049216477 Jul 29 07:50:20 PM PDT 24 Jul 29 08:00:25 PM PDT 24 16434466568 ps
T2862 /workspace/coverage/cover_reg_top/79.xbar_random.3681082485 Jul 29 08:03:09 PM PDT 24 Jul 29 08:04:08 PM PDT 24 1537196717 ps
T2863 /workspace/coverage/cover_reg_top/66.xbar_random.41666858 Jul 29 08:01:19 PM PDT 24 Jul 29 08:01:55 PM PDT 24 417742342 ps
T2864 /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.320641642 Jul 29 07:59:54 PM PDT 24 Jul 29 08:01:38 PM PDT 24 10012452839 ps
T2865 /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3001879949 Jul 29 08:01:30 PM PDT 24 Jul 29 08:24:17 PM PDT 24 78695181556 ps
T2866 /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.4233567084 Jul 29 07:56:01 PM PDT 24 Jul 29 07:57:28 PM PDT 24 5107365354 ps
T2867 /workspace/coverage/cover_reg_top/8.xbar_access_same_device.4038259898 Jul 29 07:50:09 PM PDT 24 Jul 29 07:52:19 PM PDT 24 3089790707 ps
T2868 /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.3544679372 Jul 29 07:56:01 PM PDT 24 Jul 29 08:05:13 PM PDT 24 31976855017 ps
T138 /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1631675559 Jul 29 07:49:56 PM PDT 24 Jul 29 07:55:40 PM PDT 24 6217297180 ps
T2869 /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.1125948544 Jul 29 08:00:33 PM PDT 24 Jul 29 08:01:08 PM PDT 24 457792431 ps
T2870 /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2750058004 Jul 29 08:01:58 PM PDT 24 Jul 29 08:02:57 PM PDT 24 1470579630 ps
T2871 /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.4201121851 Jul 29 07:52:26 PM PDT 24 Jul 29 07:54:55 PM PDT 24 3980016556 ps
T2872 /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1295449300 Jul 29 07:49:51 PM PDT 24 Jul 29 07:50:28 PM PDT 24 385700231 ps
T2873 /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.2998071415 Jul 29 07:49:48 PM PDT 24 Jul 29 07:50:15 PM PDT 24 649298511 ps
T2874 /workspace/coverage/cover_reg_top/27.xbar_same_source.1718916434 Jul 29 07:54:07 PM PDT 24 Jul 29 07:54:32 PM PDT 24 321085953 ps
T2875 /workspace/coverage/cover_reg_top/79.xbar_stress_all.3046998475 Jul 29 08:03:10 PM PDT 24 Jul 29 08:03:58 PM PDT 24 579429890 ps
T2876 /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.1015751495 Jul 29 07:50:13 PM PDT 24 Jul 29 07:53:19 PM PDT 24 11418405201 ps
T2877 /workspace/coverage/cover_reg_top/59.xbar_same_source.1043679227 Jul 29 07:59:54 PM PDT 24 Jul 29 08:00:05 PM PDT 24 292659090 ps
T2878 /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.670472839 Jul 29 08:05:10 PM PDT 24 Jul 29 08:05:16 PM PDT 24 49648975 ps
T2879 /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.1100355085 Jul 29 07:54:08 PM PDT 24 Jul 29 07:55:13 PM PDT 24 6280869850 ps
T2880 /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.2837825793 Jul 29 07:56:51 PM PDT 24 Jul 29 07:58:00 PM PDT 24 6678575506 ps
T2881 /workspace/coverage/cover_reg_top/25.xbar_stress_all.240998760 Jul 29 07:53:58 PM PDT 24 Jul 29 07:54:34 PM PDT 24 998557736 ps
T2882 /workspace/coverage/cover_reg_top/43.xbar_stress_all.370171644 Jul 29 07:57:16 PM PDT 24 Jul 29 08:04:28 PM PDT 24 11527840641 ps
T2883 /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.1614164366 Jul 29 08:02:53 PM PDT 24 Jul 29 08:03:03 PM PDT 24 85959764 ps
T2884 /workspace/coverage/cover_reg_top/73.xbar_same_source.3386602706 Jul 29 08:02:10 PM PDT 24 Jul 29 08:02:31 PM PDT 24 277608250 ps
T2885 /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.2757508361 Jul 29 07:50:11 PM PDT 24 Jul 29 08:01:10 PM PDT 24 42659927109 ps
T2886 /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.1159064558 Jul 29 07:54:38 PM PDT 24 Jul 29 08:11:51 PM PDT 24 56708685979 ps
T2887 /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2728805472 Jul 29 07:50:31 PM PDT 24 Jul 29 07:52:17 PM PDT 24 2738602275 ps
T2888 /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.2233391189 Jul 29 08:05:11 PM PDT 24 Jul 29 08:13:51 PM PDT 24 7110096186 ps
T2889 /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.263703943 Jul 29 07:56:53 PM PDT 24 Jul 29 08:35:30 PM PDT 24 127278662145 ps
T2890 /workspace/coverage/cover_reg_top/20.xbar_random.1246907073 Jul 29 07:52:44 PM PDT 24 Jul 29 07:53:19 PM PDT 24 455218342 ps
T2891 /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.1028867539 Jul 29 07:54:01 PM PDT 24 Jul 29 07:54:37 PM PDT 24 884050468 ps
T2892 /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.3460365896 Jul 29 07:57:01 PM PDT 24 Jul 29 07:57:07 PM PDT 24 42102811 ps
T2893 /workspace/coverage/cover_reg_top/44.xbar_same_source.1661755191 Jul 29 07:57:22 PM PDT 24 Jul 29 07:57:45 PM PDT 24 321638232 ps
T2894 /workspace/coverage/cover_reg_top/87.xbar_access_same_device.1019699276 Jul 29 08:04:25 PM PDT 24 Jul 29 08:05:27 PM PDT 24 736779136 ps
T2895 /workspace/coverage/cover_reg_top/38.xbar_stress_all.1417818689 Jul 29 07:56:21 PM PDT 24 Jul 29 08:02:36 PM PDT 24 9207690558 ps
T2896 /workspace/coverage/cover_reg_top/34.xbar_random.2714411481 Jul 29 07:55:30 PM PDT 24 Jul 29 07:56:19 PM PDT 24 573553487 ps
T2897 /workspace/coverage/cover_reg_top/23.xbar_error_random.751690371 Jul 29 07:53:20 PM PDT 24 Jul 29 07:53:48 PM PDT 24 842823364 ps
T2898 /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.2500822402 Jul 29 08:03:36 PM PDT 24 Jul 29 08:05:09 PM PDT 24 5176049164 ps
T2899 /workspace/coverage/cover_reg_top/27.xbar_error_random.3225252458 Jul 29 07:54:10 PM PDT 24 Jul 29 07:54:20 PM PDT 24 105034549 ps
T2900 /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.155982493 Jul 29 07:59:05 PM PDT 24 Jul 29 07:59:28 PM PDT 24 262251693 ps
T2901 /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.3202172969 Jul 29 08:01:50 PM PDT 24 Jul 29 08:06:57 PM PDT 24 5542275376 ps
T2902 /workspace/coverage/cover_reg_top/12.chip_tl_errors.3283958611 Jul 29 07:50:46 PM PDT 24 Jul 29 07:56:20 PM PDT 24 3811203436 ps
T2903 /workspace/coverage/cover_reg_top/50.xbar_same_source.952774269 Jul 29 07:58:32 PM PDT 24 Jul 29 07:59:51 PM PDT 24 2610157991 ps
T2904 /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.4242248071 Jul 29 07:52:01 PM PDT 24 Jul 29 08:23:39 PM PDT 24 16255968523 ps
T2905 /workspace/coverage/cover_reg_top/24.xbar_same_source.4114386142 Jul 29 07:53:31 PM PDT 24 Jul 29 07:53:42 PM PDT 24 118939041 ps
T2906 /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.2451712268 Jul 29 08:01:42 PM PDT 24 Jul 29 08:01:54 PM PDT 24 230776379 ps
T2907 /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.3909738979 Jul 29 07:54:01 PM PDT 24 Jul 29 07:55:32 PM PDT 24 8377249941 ps
T2908 /workspace/coverage/cover_reg_top/96.xbar_error_random.1951779570 Jul 29 08:05:48 PM PDT 24 Jul 29 08:05:57 PM PDT 24 66759879 ps
T2909 /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.3732218911 Jul 29 08:05:41 PM PDT 24 Jul 29 08:18:34 PM PDT 24 43410287323 ps
T2910 /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3876805755 Jul 29 07:50:48 PM PDT 24 Jul 29 07:58:19 PM PDT 24 9730838285 ps
T2911 /workspace/coverage/cover_reg_top/41.xbar_access_same_device.2926143904 Jul 29 07:56:53 PM PDT 24 Jul 29 07:57:12 PM PDT 24 365476240 ps
T2912 /workspace/coverage/cover_reg_top/47.xbar_error_random.1379569940 Jul 29 07:58:00 PM PDT 24 Jul 29 07:58:52 PM PDT 24 1413917908 ps
T2913 /workspace/coverage/cover_reg_top/87.xbar_same_source.3448096263 Jul 29 08:04:25 PM PDT 24 Jul 29 08:05:02 PM PDT 24 530101567 ps
T2914 /workspace/coverage/cover_reg_top/4.xbar_random.1137318826 Jul 29 07:50:08 PM PDT 24 Jul 29 07:51:18 PM PDT 24 2055001982 ps
T2915 /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.1539371492 Jul 29 08:02:05 PM PDT 24 Jul 29 08:08:57 PM PDT 24 23647225740 ps
T2916 /workspace/coverage/cover_reg_top/2.xbar_error_random.3266335342 Jul 29 07:49:56 PM PDT 24 Jul 29 07:50:29 PM PDT 24 1027497807 ps
T2917 /workspace/coverage/cover_reg_top/15.xbar_access_same_device.1229993415 Jul 29 07:51:44 PM PDT 24 Jul 29 07:53:10 PM PDT 24 2029750285 ps
T2918 /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1536928109 Jul 29 07:54:28 PM PDT 24 Jul 29 07:58:51 PM PDT 24 2311722590 ps
T2919 /workspace/coverage/cover_reg_top/84.xbar_access_same_device.418667955 Jul 29 08:03:57 PM PDT 24 Jul 29 08:04:11 PM PDT 24 323524721 ps
T2920 /workspace/coverage/cover_reg_top/45.xbar_access_same_device.670879341 Jul 29 07:57:27 PM PDT 24 Jul 29 07:57:48 PM PDT 24 494775364 ps
T2921 /workspace/coverage/cover_reg_top/45.xbar_same_source.1107573173 Jul 29 07:57:30 PM PDT 24 Jul 29 07:57:44 PM PDT 24 368774113 ps
T2922 /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.3770329880 Jul 29 07:57:12 PM PDT 24 Jul 29 07:57:18 PM PDT 24 45929218 ps
T2923 /workspace/coverage/cover_reg_top/21.xbar_stress_all.2114069690 Jul 29 07:52:54 PM PDT 24 Jul 29 08:01:44 PM PDT 24 13965070316 ps
T2924 /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.2220060588 Jul 29 07:53:59 PM PDT 24 Jul 29 07:54:06 PM PDT 24 51492098 ps
T2925 /workspace/coverage/cover_reg_top/10.xbar_access_same_device.2530036368 Jul 29 07:50:27 PM PDT 24 Jul 29 07:51:38 PM PDT 24 1597746527 ps
T2926 /workspace/coverage/cover_reg_top/42.xbar_error_random.900627628 Jul 29 07:57:19 PM PDT 24 Jul 29 07:57:46 PM PDT 24 356533413 ps
T2927 /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.3114155208 Jul 29 07:53:20 PM PDT 24 Jul 29 07:53:26 PM PDT 24 50226779 ps
T2928 /workspace/coverage/cover_reg_top/32.xbar_access_same_device.895014258 Jul 29 07:55:12 PM PDT 24 Jul 29 07:55:50 PM PDT 24 1013925313 ps
T2929 /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.1610300367 Jul 29 07:50:04 PM PDT 24 Jul 29 07:50:22 PM PDT 24 153736680 ps
T2930 /workspace/coverage/cover_reg_top/56.xbar_stress_all.1168069016 Jul 29 07:59:30 PM PDT 24 Jul 29 08:01:08 PM PDT 24 2677583512 ps
T2931 /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.2754154840 Jul 29 07:57:22 PM PDT 24 Jul 29 07:59:24 PM PDT 24 434943090 ps
T2932 /workspace/coverage/cover_reg_top/10.xbar_same_source.3752337387 Jul 29 07:50:18 PM PDT 24 Jul 29 07:50:43 PM PDT 24 842761591 ps
T2933 /workspace/coverage/cover_reg_top/86.xbar_random.2325614705 Jul 29 08:04:12 PM PDT 24 Jul 29 08:04:41 PM PDT 24 712848536 ps
T2934 /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.602099826 Jul 29 07:50:45 PM PDT 24 Jul 29 07:50:58 PM PDT 24 289851056 ps
T2935 /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2804769949 Jul 29 07:50:32 PM PDT 24 Jul 29 07:58:46 PM PDT 24 6931873022 ps
T2936 /workspace/coverage/cover_reg_top/9.xbar_random.755902342 Jul 29 07:50:21 PM PDT 24 Jul 29 07:51:42 PM PDT 24 2323601833 ps
T2937 /workspace/coverage/cover_reg_top/2.xbar_random.180124890 Jul 29 07:49:56 PM PDT 24 Jul 29 07:51:02 PM PDT 24 1967042992 ps
T2938 /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.4273291390 Jul 29 07:53:23 PM PDT 24 Jul 29 07:54:53 PM PDT 24 5658199047 ps
T2939 /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.3909345692 Jul 29 07:57:51 PM PDT 24 Jul 29 08:02:47 PM PDT 24 4180636300 ps
T29 /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3155774724 Jul 29 08:06:32 PM PDT 24 Jul 29 08:10:18 PM PDT 24 4238158632 ps
T30 /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3078172574 Jul 29 08:06:33 PM PDT 24 Jul 29 08:11:05 PM PDT 24 4563916600 ps
T31 /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3148296577 Jul 29 08:06:34 PM PDT 24 Jul 29 08:09:54 PM PDT 24 4708383250 ps
T196 /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4140628318 Jul 29 08:06:32 PM PDT 24 Jul 29 08:10:30 PM PDT 24 5242627544 ps
T197 /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1082255899 Jul 29 08:06:33 PM PDT 24 Jul 29 08:10:19 PM PDT 24 5391203353 ps
T198 /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.844645455 Jul 29 08:06:38 PM PDT 24 Jul 29 08:09:34 PM PDT 24 4203935520 ps
T199 /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.527295222 Jul 29 08:06:34 PM PDT 24 Jul 29 08:11:31 PM PDT 24 5554854026 ps
T200 /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2800884042 Jul 29 08:06:37 PM PDT 24 Jul 29 08:10:28 PM PDT 24 5530342130 ps
T201 /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1688177626 Jul 29 08:06:33 PM PDT 24 Jul 29 08:10:12 PM PDT 24 4851411261 ps
T202 /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3703515113 Jul 29 08:06:38 PM PDT 24 Jul 29 08:10:18 PM PDT 24 4654653534 ps

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.504766932
Short name T1
Test name
Test status
Simulation time 20187507579 ps
CPU time 2744.48 seconds
Started Jul 29 08:33:47 PM PDT 24
Finished Jul 29 09:19:33 PM PDT 24
Peak memory 611196 kb
Host smart-34543372-d0c0-4564-a841-77dd196dcffb
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=504766932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.504766932
Directory /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.3078413406
Short name T385
Test name
Test status
Simulation time 11662015852 ps
CPU time 904.75 seconds
Started Jul 29 07:50:21 PM PDT 24
Finished Jul 29 08:05:26 PM PDT 24
Peak memory 653000 kb
Host smart-618ff4ea-f453-485a-86bb-1f0246ed24a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078413406 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.3078413406
Directory /workspace/8.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.2760079660
Short name T255
Test name
Test status
Simulation time 8102819657 ps
CPU time 265.55 seconds
Started Jul 29 08:04:44 PM PDT 24
Finished Jul 29 08:09:10 PM PDT 24
Peak memory 576840 kb
Host smart-176db0bc-ab90-4fc3-bbb4-164e8101ba1c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760079660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.2760079660
Directory /workspace/88.xbar_stress_all_with_error/latest

Test location /workspace/coverage/default/1.chip_plic_all_irqs_0.1809154648
Short name T320
Test name
Test status
Simulation time 5586706712 ps
CPU time 1224.99 seconds
Started Jul 29 08:30:52 PM PDT 24
Finished Jul 29 08:51:17 PM PDT 24
Peak memory 610208 kb
Host smart-9707d6f8-540b-42ac-8f25-6f6a6aeddbab
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809154648 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_plic_all_irqs_0.1809154648
Directory /workspace/1.chip_plic_all_irqs_0/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.2849888227
Short name T468
Test name
Test status
Simulation time 126743547548 ps
CPU time 2140.95 seconds
Started Jul 29 07:52:46 PM PDT 24
Finished Jul 29 08:28:28 PM PDT 24
Peak memory 575932 kb
Host smart-d5dcd3f1-9825-4a62-838e-56448f9a6135
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849888227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_
device_slow_rsp.2849888227
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3155774724
Short name T29
Test name
Test status
Simulation time 4238158632 ps
CPU time 225.95 seconds
Started Jul 29 08:06:32 PM PDT 24
Finished Jul 29 08:10:18 PM PDT 24
Peak memory 657384 kb
Host smart-5b7ef62a-345c-4f00-8bb1-029265847f22
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155774724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 4.chip_padctrl_attributes.3155774724
Directory /workspace/4.chip_padctrl_attributes/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1428128826
Short name T434
Test name
Test status
Simulation time 119028238971 ps
CPU time 2048.75 seconds
Started Jul 29 07:51:31 PM PDT 24
Finished Jul 29 08:25:40 PM PDT 24
Peak memory 576144 kb
Host smart-6a0285df-53a6-462a-ac39-012c3e530985
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428128826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_
device_slow_rsp.1428128826
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3162791622
Short name T7
Test name
Test status
Simulation time 14440712185 ps
CPU time 3752.48 seconds
Started Jul 29 08:33:53 PM PDT 24
Finished Jul 29 09:36:26 PM PDT 24
Peak memory 611404 kb
Host smart-32763e02-68fa-4e8e-91d4-24a0439503c4
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne
w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162791622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu
tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_
shutdown_exception_c.3162791622
Directory /workspace/1.rom_e2e_shutdown_exception_c/latest

Test location /workspace/coverage/default/1.chip_sw_power_virus.3692461097
Short name T11
Test name
Test status
Simulation time 5824851592 ps
CPU time 1338.74 seconds
Started Jul 29 08:36:58 PM PDT 24
Finished Jul 29 08:59:17 PM PDT 24
Peak memory 625012 kb
Host smart-476c8c75-7548-4a03-90c0-9c5426f78ec9
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_
power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes
t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3692461097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.3692461097
Directory /workspace/1.chip_sw_power_virus/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.84228797
Short name T225
Test name
Test status
Simulation time 12704541872 ps
CPU time 3070.01 seconds
Started Jul 29 08:36:09 PM PDT 24
Finished Jul 29 09:27:20 PM PDT 24
Peak memory 610932 kb
Host smart-6ffa0a61-b1bc-447b-b29b-cbb0abb2aa41
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84228
797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.84228797
Directory /workspace/2.chip_sw_keymgr_sideload_otbn/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.1943661263
Short name T837
Test name
Test status
Simulation time 70584369125 ps
CPU time 1208.81 seconds
Started Jul 29 07:58:42 PM PDT 24
Finished Jul 29 08:18:51 PM PDT 24
Peak memory 575944 kb
Host smart-7a37a9b5-2aa0-42cf-ad95-2846721f84cd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943661263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_
device_slow_rsp.1943661263
Directory /workspace/51.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1974942739
Short name T843
Test name
Test status
Simulation time 86073177973 ps
CPU time 1541.72 seconds
Started Jul 29 07:50:21 PM PDT 24
Finished Jul 29 08:16:03 PM PDT 24
Peak memory 576116 kb
Host smart-c47e9967-b887-45ca-acf3-2c3c79b97d5b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974942739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_
device_slow_rsp.1974942739
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3185717799
Short name T8
Test name
Test status
Simulation time 2760241873 ps
CPU time 392.94 seconds
Started Jul 29 08:37:36 PM PDT 24
Finished Jul 29 08:44:09 PM PDT 24
Peak memory 610084 kb
Host smart-9f785eae-4b36-4527-b9a8-4b33e7899c08
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185
717799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.3185717799
Directory /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2170759227
Short name T179
Test name
Test status
Simulation time 46990936250 ps
CPU time 5865.12 seconds
Started Jul 29 08:13:48 PM PDT 24
Finished Jul 29 09:51:34 PM PDT 24
Peak memory 620596 kb
Host smart-6da2cb0f-e9eb-4a73-ab61-2803559abc52
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170759227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip
_sw_lc_walkthrough_dev.2170759227
Directory /workspace/0.chip_sw_lc_walkthrough_dev/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1384096935
Short name T17
Test name
Test status
Simulation time 7713639344 ps
CPU time 397.96 seconds
Started Jul 29 08:27:55 PM PDT 24
Finished Jul 29 08:34:33 PM PDT 24
Peak memory 610476 kb
Host smart-0666802f-b3dc-40da-90ea-31b176768572
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384096935 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1384096935
Directory /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3836535546
Short name T93
Test name
Test status
Simulation time 2386207396 ps
CPU time 252.63 seconds
Started Jul 29 08:39:14 PM PDT 24
Finished Jul 29 08:43:27 PM PDT 24
Peak memory 609740 kb
Host smart-930aabbe-e3f5-4919-af44-44a4d8c182c1
User root
Command /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3836535546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.3836535546
Directory /workspace/2.chip_sw_rv_core_ibex_address_translation/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.1059328007
Short name T725
Test name
Test status
Simulation time 80741871348 ps
CPU time 1381.96 seconds
Started Jul 29 08:03:10 PM PDT 24
Finished Jul 29 08:26:13 PM PDT 24
Peak memory 576036 kb
Host smart-0f2d9c69-b623-49cd-9878-aefb77775c81
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059328007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_
device_slow_rsp.1059328007
Directory /workspace/79.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/2.chip_plic_all_irqs_10.18640768
Short name T157
Test name
Test status
Simulation time 3879602888 ps
CPU time 675.24 seconds
Started Jul 29 08:36:21 PM PDT 24
Finished Jul 29 08:47:36 PM PDT 24
Peak memory 609732 kb
Host smart-28b8968d-657b-4da9-8b63-daf2c3a082a9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18640768 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_plic_all_irqs_10.18640768
Directory /workspace/2.chip_plic_all_irqs_10/latest

Test location /workspace/coverage/default/1.chip_plic_all_irqs_20.3166777541
Short name T321
Test name
Test status
Simulation time 4131336196 ps
CPU time 856.47 seconds
Started Jul 29 08:27:38 PM PDT 24
Finished Jul 29 08:41:55 PM PDT 24
Peak memory 609812 kb
Host smart-85d60957-593b-41a2-94c8-bb97129442e0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166777541 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.chip_plic_all_irqs_20.3166777541
Directory /workspace/1.chip_plic_all_irqs_20/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.4261010760
Short name T1805
Test name
Test status
Simulation time 57933805767 ps
CPU time 1007.85 seconds
Started Jul 29 08:05:22 PM PDT 24
Finished Jul 29 08:22:10 PM PDT 24
Peak memory 575968 kb
Host smart-89dab005-86cd-4bc0-ae7e-2656e9d31da4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261010760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_
device_slow_rsp.4261010760
Directory /workspace/92.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3121210837
Short name T75
Test name
Test status
Simulation time 929080029 ps
CPU time 71.3 seconds
Started Jul 29 07:49:51 PM PDT 24
Finished Jul 29 07:51:02 PM PDT 24
Peak memory 575932 kb
Host smart-b2e9751d-eadf-4d40-a000-6530fe72ee0c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121210837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3121210837
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.658681915
Short name T4
Test name
Test status
Simulation time 3819051296 ps
CPU time 378.78 seconds
Started Jul 29 08:45:53 PM PDT 24
Finished Jul 29 08:52:12 PM PDT 24
Peak memory 649144 kb
Host smart-9b97b25a-b75e-4c09-8bea-1f6449a05b22
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658681915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_s
w_alert_handler_lpg_sleep_mode_alerts.658681915
Directory /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.370199959
Short name T845
Test name
Test status
Simulation time 55662012079 ps
CPU time 937.53 seconds
Started Jul 29 07:52:55 PM PDT 24
Finished Jul 29 08:08:32 PM PDT 24
Peak memory 575912 kb
Host smart-c8ba4108-9ad1-42e3-b5c5-836bd1791849
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370199959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_d
evice_slow_rsp.370199959
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/1.chip_sw_alert_test.4179812984
Short name T50
Test name
Test status
Simulation time 2820190160 ps
CPU time 241.4 seconds
Started Jul 29 08:30:59 PM PDT 24
Finished Jul 29 08:35:01 PM PDT 24
Peak memory 609964 kb
Host smart-672e4873-a5a4-4b3c-a97d-9842ba5b1325
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179812984 -assert nopostproc +UVM_TESTNAME=chip_ba
se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.chip_sw_alert_test.4179812984
Directory /workspace/1.chip_sw_alert_test/latest

Test location /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2530407674
Short name T61
Test name
Test status
Simulation time 14364951845 ps
CPU time 944.59 seconds
Started Jul 29 08:46:35 PM PDT 24
Finished Jul 29 09:02:20 PM PDT 24
Peak memory 621464 kb
Host smart-5d8ad01f-e3b5-4325-9a16-42e3ab514213
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530407674 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.2530407674
Directory /workspace/14.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.2430806695
Short name T839
Test name
Test status
Simulation time 12145015833 ps
CPU time 388.92 seconds
Started Jul 29 07:59:27 PM PDT 24
Finished Jul 29 08:05:56 PM PDT 24
Peak memory 576844 kb
Host smart-0139cf15-0dea-4abf-a0a9-26334615ec7d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430806695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.2430806695
Directory /workspace/56.xbar_stress_all_with_error/latest

Test location /workspace/coverage/default/1.chip_sw_gpio.3880568773
Short name T16
Test name
Test status
Simulation time 3740327025 ps
CPU time 485.58 seconds
Started Jul 29 08:27:58 PM PDT 24
Finished Jul 29 08:36:04 PM PDT 24
Peak memory 609292 kb
Host smart-0a5b2101-fcff-43cf-834a-0045e7777122
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880568773 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.chip_sw_gpio.3880568773
Directory /workspace/1.chip_sw_gpio/latest

Test location /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2483224543
Short name T125
Test name
Test status
Simulation time 7640018400 ps
CPU time 1238.57 seconds
Started Jul 29 08:35:52 PM PDT 24
Finished Jul 29 08:56:31 PM PDT 24
Peak memory 610904 kb
Host smart-4da8133b-e97c-4318-8414-1c0ad504a493
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed
n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2483224543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.2483224543
Directory /workspace/2.chip_sw_edn_entropy_reqs/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.222805836
Short name T546
Test name
Test status
Simulation time 4410775516 ps
CPU time 368.28 seconds
Started Jul 29 08:00:15 PM PDT 24
Finished Jul 29 08:06:24 PM PDT 24
Peak memory 576032 kb
Host smart-20cb5b02-dfdd-4757-b9cc-d63087a3cb89
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222805836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.222805836
Directory /workspace/60.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.3867697428
Short name T383
Test name
Test status
Simulation time 27206106877 ps
CPU time 3627.13 seconds
Started Jul 29 07:50:04 PM PDT 24
Finished Jul 29 08:50:32 PM PDT 24
Peak memory 593480 kb
Host smart-af722f02-93c9-47cd-ab86-eeed1a73e3a1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867697428 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.3867697428
Directory /workspace/3.chip_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rom_e2e_shutdown_output.944367098
Short name T42
Test name
Test status
Simulation time 27257462380 ps
CPU time 4253.92 seconds
Started Jul 29 08:30:28 PM PDT 24
Finished Jul 29 09:41:23 PM PDT 24
Peak memory 611716 kb
Host smart-37ef9915-eddb-4877-a6b3-b5b0cf57d0c3
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f
lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944367098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip
_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rom_e2e_shutdown_output.944367098
Directory /workspace/0.rom_e2e_shutdown_output/latest

Test location /workspace/coverage/cover_reg_top/15.chip_tl_errors.1587951379
Short name T563
Test name
Test status
Simulation time 3962906274 ps
CPU time 244.35 seconds
Started Jul 29 07:51:44 PM PDT 24
Finished Jul 29 07:55:49 PM PDT 24
Peak memory 598644 kb
Host smart-4de018a9-03d2-445f-a6c6-9ce6aad964eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587951379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.1587951379
Directory /workspace/15.chip_tl_errors/latest

Test location /workspace/coverage/default/0.chip_jtag_mem_access.106413208
Short name T68
Test name
Test status
Simulation time 14101849396 ps
CPU time 1507.77 seconds
Started Jul 29 08:08:43 PM PDT 24
Finished Jul 29 08:33:51 PM PDT 24
Peak memory 607932 kb
Host smart-9e96cd7d-2af7-427a-bd4c-6c9652b33ebe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106413208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m
em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.106413208
Directory /workspace/0.chip_jtag_mem_access/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.3745736511
Short name T555
Test name
Test status
Simulation time 33180657034 ps
CPU time 570.76 seconds
Started Jul 29 07:54:39 PM PDT 24
Finished Jul 29 08:04:10 PM PDT 24
Peak memory 576152 kb
Host smart-1ab85401-07a7-4d2b-bc6f-1347a0557466
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745736511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_
device_slow_rsp.3745736511
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1604604462
Short name T10
Test name
Test status
Simulation time 3055040344 ps
CPU time 319.22 seconds
Started Jul 29 08:13:38 PM PDT 24
Finished Jul 29 08:18:58 PM PDT 24
Peak memory 609844 kb
Host smart-6d81b67f-5c21-4918-8e75-b6d7c710790f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604
604462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.1604604462
Directory /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1096439921
Short name T130
Test name
Test status
Simulation time 5629791940 ps
CPU time 408.43 seconds
Started Jul 29 08:18:59 PM PDT 24
Finished Jul 29 08:25:48 PM PDT 24
Peak memory 609936 kb
Host smart-b3e0cf30-b270-4051-9d3b-7efd74ee6126
User root
Command /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10964399
21 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1096439921
Directory /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location /workspace/coverage/default/1.chip_jtag_csr_rw.2179773112
Short name T77
Test name
Test status
Simulation time 13954971875 ps
CPU time 1531.66 seconds
Started Jul 29 08:19:17 PM PDT 24
Finished Jul 29 08:44:50 PM PDT 24
Peak memory 608100 kb
Host smart-a7a40c2e-6f67-43bf-927f-37f1c5838a36
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179773112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c
hip_jtag_csr_rw.2179773112
Directory /workspace/1.chip_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.650487688
Short name T463
Test name
Test status
Simulation time 9991674375 ps
CPU time 103.06 seconds
Started Jul 29 08:00:34 PM PDT 24
Finished Jul 29 08:02:17 PM PDT 24
Peak memory 574648 kb
Host smart-26c01ed3-f988-42f0-a0b6-ca42554c2641
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650487688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.650487688
Directory /workspace/63.xbar_smoke_large_delays/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.4275554668
Short name T160
Test name
Test status
Simulation time 4772788952 ps
CPU time 597.78 seconds
Started Jul 29 08:15:39 PM PDT 24
Finished Jul 29 08:25:37 PM PDT 24
Peak memory 610996 kb
Host smart-923ab51d-d594-4662-8802-35e568d19c28
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4275554668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.4275554668
Directory /workspace/0.chip_sw_otp_ctrl_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.4038205711
Short name T82
Test name
Test status
Simulation time 9629433496 ps
CPU time 1056 seconds
Started Jul 29 08:14:55 PM PDT 24
Finished Jul 29 08:32:31 PM PDT 24
Peak memory 610924 kb
Host smart-5fe55750-a971-44fe-af60-d13312548a45
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler
_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038205711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han
dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.chip_sw_alert_handler_lpg_sleep_mode_pings.4038205711
Directory /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.447765364
Short name T178
Test name
Test status
Simulation time 43164228545 ps
CPU time 5231.3 seconds
Started Jul 29 08:31:22 PM PDT 24
Finished Jul 29 09:58:35 PM PDT 24
Peak memory 621236 kb
Host smart-1e37eb70-49b2-4544-adfb-4e96a11b0926
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_
rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=447765364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.447765364
Directory /workspace/2.chip_sw_flash_rma_unlocked/latest

Test location /workspace/coverage/cover_reg_top/18.chip_tl_errors.1984374457
Short name T560
Test name
Test status
Simulation time 4007914656 ps
CPU time 334.85 seconds
Started Jul 29 07:52:04 PM PDT 24
Finished Jul 29 07:57:39 PM PDT 24
Peak memory 598696 kb
Host smart-bf9a350c-0b90-4f36-aad8-63010c9ad6f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984374457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.1984374457
Directory /workspace/18.chip_tl_errors/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3561653312
Short name T9
Test name
Test status
Simulation time 3337474017 ps
CPU time 296.03 seconds
Started Jul 29 08:24:46 PM PDT 24
Finished Jul 29 08:29:42 PM PDT 24
Peak memory 610232 kb
Host smart-b8ad5da6-cc5a-4083-ab3b-812d409cebc1
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561
653312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.3561653312
Directory /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1984255921
Short name T419
Test name
Test status
Simulation time 11617450697 ps
CPU time 627.71 seconds
Started Jul 29 07:54:39 PM PDT 24
Finished Jul 29 08:05:07 PM PDT 24
Peak memory 576004 kb
Host smart-74c462f2-fe97-46f6-b17b-3184663fa0a7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984255921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all
_with_rand_reset.1984255921
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.chip_sw_all_escalation_resets.3327594173
Short name T368
Test name
Test status
Simulation time 4513104350 ps
CPU time 440.7 seconds
Started Jul 29 08:50:26 PM PDT 24
Finished Jul 29 08:57:47 PM PDT 24
Peak memory 650376 kb
Host smart-cb154a87-065d-40d1-95b7-fdbf0b010f56
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3327594173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.3327594173
Directory /workspace/73.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.652360870
Short name T496
Test name
Test status
Simulation time 20255128450 ps
CPU time 1043.25 seconds
Started Jul 29 08:03:12 PM PDT 24
Finished Jul 29 08:20:36 PM PDT 24
Peak memory 576080 kb
Host smart-cf411cc2-8bb4-43d9-a5cd-4ed218afc7d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652360870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_
with_rand_reset.652360870
Directory /workspace/79.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2545356440
Short name T24
Test name
Test status
Simulation time 21770664136 ps
CPU time 1402.64 seconds
Started Jul 29 08:29:34 PM PDT 24
Finished Jul 29 08:52:57 PM PDT 24
Peak memory 613880 kb
Host smart-47d9470c-bddb-40b0-98f2-446be2c478b2
User root
Command /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25453564
40 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.2545356440
Directory /workspace/1.chip_sw_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3511130261
Short name T88
Test name
Test status
Simulation time 9253011656 ps
CPU time 1341.11 seconds
Started Jul 29 08:43:48 PM PDT 24
Finished Jul 29 09:06:11 PM PDT 24
Peak memory 624556 kb
Host smart-553338f0-dd1b-4541-bf52-3308b9c2c4a0
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3511130261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.3511130261
Directory /workspace/17.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.4105462795
Short name T491
Test name
Test status
Simulation time 7205481576 ps
CPU time 914.08 seconds
Started Jul 29 07:59:09 PM PDT 24
Finished Jul 29 08:14:23 PM PDT 24
Peak memory 576092 kb
Host smart-968df7b6-abf3-4b6a-bd92-758af8ce6a69
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105462795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all
_with_rand_reset.4105462795
Directory /workspace/53.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1495179527
Short name T98
Test name
Test status
Simulation time 5198393689 ps
CPU time 621.37 seconds
Started Jul 29 08:30:11 PM PDT 24
Finished Jul 29 08:40:33 PM PDT 24
Peak memory 611100 kb
Host smart-58f26312-bde5-4e76-bc5f-acac4cbe43cf
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s
w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495179527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1495179527
Directory /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.195485443
Short name T56
Test name
Test status
Simulation time 3940776371 ps
CPU time 303.25 seconds
Started Jul 29 08:14:54 PM PDT 24
Finished Jul 29 08:19:58 PM PDT 24
Peak memory 617900 kb
Host smart-bfec4c33-a669-4d05-a3c2-26f99eed72e6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195485443 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.195485443
Directory /workspace/0.chip_sw_spi_device_pinmux_sleep_retention/latest

Test location /workspace/coverage/cover_reg_top/24.chip_tl_errors.4075044442
Short name T573
Test name
Test status
Simulation time 4017049050 ps
CPU time 243.99 seconds
Started Jul 29 07:53:23 PM PDT 24
Finished Jul 29 07:57:27 PM PDT 24
Peak memory 598908 kb
Host smart-11dc8e34-29c8-438f-98ee-2c3b16cce876
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075044442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.4075044442
Directory /workspace/24.chip_tl_errors/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2912527884
Short name T105
Test name
Test status
Simulation time 3939268350 ps
CPU time 460.42 seconds
Started Jul 29 08:26:45 PM PDT 24
Finished Jul 29 08:34:25 PM PDT 24
Peak memory 609596 kb
Host smart-b849b870-839d-4057-a972-e2994ae473f2
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29
12527884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.2912527884
Directory /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest

Test location /workspace/coverage/default/51.chip_sw_all_escalation_resets.3793062802
Short name T254
Test name
Test status
Simulation time 6235681920 ps
CPU time 706.28 seconds
Started Jul 29 08:48:18 PM PDT 24
Finished Jul 29 09:00:05 PM PDT 24
Peak memory 650092 kb
Host smart-ef797687-f20d-4df2-8691-e968c7564281
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3793062802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.3793062802
Directory /workspace/51.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random.1089838228
Short name T73
Test name
Test status
Simulation time 468330840 ps
CPU time 19.28 seconds
Started Jul 29 08:01:18 PM PDT 24
Finished Jul 29 08:01:37 PM PDT 24
Peak memory 575788 kb
Host smart-68251cf7-8bff-4755-9658-f7a84e8fec46
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089838228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.1089838228
Directory /workspace/68.xbar_random/latest

Test location /workspace/coverage/default/3.chip_sw_all_escalation_resets.2356793588
Short name T266
Test name
Test status
Simulation time 4724664924 ps
CPU time 612.74 seconds
Started Jul 29 08:43:19 PM PDT 24
Finished Jul 29 08:53:32 PM PDT 24
Peak memory 650300 kb
Host smart-1eaf2d7c-81fb-4ba4-8a37-9719dde23006
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2356793588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.2356793588
Directory /workspace/3.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/83.chip_sw_all_escalation_resets.2515531249
Short name T79
Test name
Test status
Simulation time 4896461140 ps
CPU time 554.07 seconds
Started Jul 29 08:50:52 PM PDT 24
Finished Jul 29 09:00:06 PM PDT 24
Peak memory 650944 kb
Host smart-e6ba0f5a-ba3c-4c6f-9cd1-2c0b875e3d59
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2515531249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.2515531249
Directory /workspace/83.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3952128153
Short name T126
Test name
Test status
Simulation time 142895581304 ps
CPU time 20754.1 seconds
Started Jul 29 08:16:14 PM PDT 24
Finished Jul 30 02:02:11 AM PDT 24
Peak memory 610180 kb
Host smart-f8080b28-31a2-4351-a5d1-bdb1cc338461
User root
Command /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_
cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3952128153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.3952128153
Directory /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location /workspace/coverage/default/52.chip_sw_all_escalation_resets.275561928
Short name T317
Test name
Test status
Simulation time 4720587848 ps
CPU time 603.69 seconds
Started Jul 29 08:48:36 PM PDT 24
Finished Jul 29 08:58:40 PM PDT 24
Peak memory 650476 kb
Host smart-b9c87e00-111b-43c0-9aed-c700fe3e524f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
275561928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.275561928
Directory /workspace/52.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_pincfg.395822927
Short name T21
Test name
Test status
Simulation time 31425919220 ps
CPU time 6864.94 seconds
Started Jul 29 08:13:07 PM PDT 24
Finished Jul 29 10:07:33 PM PDT 24
Peak memory 610280 kb
Host smart-47036be9-e5f4-480a-80f5-8f62903f10af
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=395822927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.395822927
Directory /workspace/0.chip_sw_usbdev_pincfg/latest

Test location /workspace/coverage/cover_reg_top/8.chip_tl_errors.473301592
Short name T565
Test name
Test status
Simulation time 3028967740 ps
CPU time 240.52 seconds
Started Jul 29 07:50:17 PM PDT 24
Finished Jul 29 07:54:18 PM PDT 24
Peak memory 599656 kb
Host smart-558ea296-ae03-40fc-afb8-58d4e2032c01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473301592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.473301592
Directory /workspace/8.chip_tl_errors/latest

Test location /workspace/coverage/default/1.chip_sw_data_integrity_escalation.605965988
Short name T278
Test name
Test status
Simulation time 6070912792 ps
CPU time 853.99 seconds
Started Jul 29 08:27:59 PM PDT 24
Finished Jul 29 08:42:14 PM PDT 24
Peak memory 611140 kb
Host smart-0ed444a1-dfce-4200-b8a3-22ef0c31627a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=605965988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.605965988
Directory /workspace/1.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.37540819
Short name T132
Test name
Test status
Simulation time 7822453268 ps
CPU time 656.09 seconds
Started Jul 29 08:18:40 PM PDT 24
Finished Jul 29 08:29:36 PM PDT 24
Peak memory 610220 kb
Host smart-d38ab6b0-f56c-4e89-966e-080860c005e6
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37540819
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.37540819
Directory /workspace/0.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2652763957
Short name T48
Test name
Test status
Simulation time 3853679821 ps
CPU time 268.65 seconds
Started Jul 29 08:13:30 PM PDT 24
Finished Jul 29 08:17:59 PM PDT 24
Peak memory 621788 kb
Host smart-1f447152-438c-425c-b437-f7bf5c591c77
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules
,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2652763957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.2652763957
Directory /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.1629780949
Short name T415
Test name
Test status
Simulation time 3719930154 ps
CPU time 475.19 seconds
Started Jul 29 07:56:39 PM PDT 24
Finished Jul 29 08:04:34 PM PDT 24
Peak memory 576800 kb
Host smart-b5815d68-531e-4a28-ba46-206ad07e49b9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629780949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all
_with_rand_reset.1629780949
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.857813465
Short name T190
Test name
Test status
Simulation time 44827956284 ps
CPU time 4798.57 seconds
Started Jul 29 08:26:31 PM PDT 24
Finished Jul 29 09:46:30 PM PDT 24
Peak memory 621116 kb
Host smart-09d7265f-ada6-4a76-965e-77507711888d
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_
rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=857813465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.857813465
Directory /workspace/1.chip_sw_flash_rma_unlocked/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all.585281039
Short name T439
Test name
Test status
Simulation time 20148703190 ps
CPU time 755.26 seconds
Started Jul 29 08:00:23 PM PDT 24
Finished Jul 29 08:12:59 PM PDT 24
Peak memory 576048 kb
Host smart-740b60b6-f5f4-413f-af20-3565f42aa708
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585281039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.585281039
Directory /workspace/61.xbar_stress_all/latest

Test location /workspace/coverage/default/0.chip_tap_straps_testunlock0.81213259
Short name T69
Test name
Test status
Simulation time 2509265054 ps
CPU time 140.01 seconds
Started Jul 29 08:15:24 PM PDT 24
Finished Jul 29 08:17:44 PM PDT 24
Peak memory 624668 kb
Host smart-3a34bae9-91f9-422e-ad4e-867f87f6a4ae
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81213259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.81213259
Directory /workspace/0.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pin_wake.269272942
Short name T58
Test name
Test status
Simulation time 5684300218 ps
CPU time 543.01 seconds
Started Jul 29 08:36:19 PM PDT 24
Finished Jul 29 08:45:22 PM PDT 24
Peak memory 610848 kb
Host smart-28ed000f-414f-4785-8636-17153331d84a
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269272942 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.269272942
Directory /workspace/2.chip_sw_sleep_pin_wake/latest

Test location /workspace/coverage/default/2.chip_plic_all_irqs_0.1883371999
Short name T287
Test name
Test status
Simulation time 6284861600 ps
CPU time 1034.31 seconds
Started Jul 29 08:36:30 PM PDT 24
Finished Jul 29 08:53:45 PM PDT 24
Peak memory 609032 kb
Host smart-0c4d376e-572e-4afc-b08e-e384a5839b88
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883371999 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_plic_all_irqs_0.1883371999
Directory /workspace/2.chip_plic_all_irqs_0/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1107781143
Short name T6
Test name
Test status
Simulation time 78163289089 ps
CPU time 12910.7 seconds
Started Jul 29 08:32:54 PM PDT 24
Finished Jul 30 12:08:06 AM PDT 24
Peak memory 636096 kb
Host smart-d4b5fc88-3bf0-4e8d-8768-7488c6879699
User root
Command /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1107781143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.1107781143
Directory /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.1997231264
Short name T1947
Test name
Test status
Simulation time 16031098374 ps
CPU time 859.55 seconds
Started Jul 29 07:58:39 PM PDT 24
Finished Jul 29 08:12:59 PM PDT 24
Peak memory 576640 kb
Host smart-40015611-4724-4dae-b91d-136455d287eb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997231264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all
_with_rand_reset.1997231264
Directory /workspace/51.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.chip_tl_errors.4114608625
Short name T594
Test name
Test status
Simulation time 3389133280 ps
CPU time 252.75 seconds
Started Jul 29 07:50:14 PM PDT 24
Finished Jul 29 07:54:27 PM PDT 24
Peak memory 598796 kb
Host smart-97830c77-e176-47b3-9efa-42d434f00973
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114608625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.4114608625
Directory /workspace/7.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.4159930268
Short name T136
Test name
Test status
Simulation time 5943478432 ps
CPU time 389.84 seconds
Started Jul 29 07:50:09 PM PDT 24
Finished Jul 29 07:56:39 PM PDT 24
Peak memory 662856 kb
Host smart-e29cc733-034f-4b83-94c6-16500d24362c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159930268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r
eset.4159930268
Directory /workspace/4.chip_csr_hw_reset/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pin_retention.3013573730
Short name T55
Test name
Test status
Simulation time 3915944224 ps
CPU time 269.55 seconds
Started Jul 29 08:14:00 PM PDT 24
Finished Jul 29 08:18:30 PM PDT 24
Peak memory 610072 kb
Host smart-3d9c5452-b8bc-408b-8f0d-f91be4da63d3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013573730 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.3013573730
Directory /workspace/0.chip_sw_sleep_pin_retention/latest

Test location /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3756958022
Short name T192
Test name
Test status
Simulation time 45135174180 ps
CPU time 5364.9 seconds
Started Jul 29 08:13:52 PM PDT 24
Finished Jul 29 09:43:18 PM PDT 24
Peak memory 622956 kb
Host smart-bfbd05f0-bbca-4f9d-9a22-a25c9109794d
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_
rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3756958022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.3756958022
Directory /workspace/0.chip_sw_flash_rma_unlocked/latest

Test location /workspace/coverage/default/2.chip_plic_all_irqs_20.1892703764
Short name T322
Test name
Test status
Simulation time 5460571808 ps
CPU time 940.95 seconds
Started Jul 29 08:36:30 PM PDT 24
Finished Jul 29 08:52:11 PM PDT 24
Peak memory 610060 kb
Host smart-64bca153-5ad7-4c9e-907f-1ab217c4f057
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892703764 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.chip_plic_all_irqs_20.1892703764
Directory /workspace/2.chip_plic_all_irqs_20/latest

Test location /workspace/coverage/cover_reg_top/17.chip_tl_errors.2589966173
Short name T689
Test name
Test status
Simulation time 3863809824 ps
CPU time 285.96 seconds
Started Jul 29 07:52:00 PM PDT 24
Finished Jul 29 07:56:47 PM PDT 24
Peak memory 603736 kb
Host smart-d1a8cf20-61ce-4bb9-8478-3c25aabad44c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589966173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.2589966173
Directory /workspace/17.chip_tl_errors/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1898513699
Short name T67
Test name
Test status
Simulation time 3832328920 ps
CPU time 661.67 seconds
Started Jul 29 08:35:41 PM PDT 24
Finished Jul 29 08:46:43 PM PDT 24
Peak memory 613164 kb
Host smart-f4d4edb9-1803-4966-9eac-917596532bbc
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898513699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1898513699
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_plic_all_irqs_0.36132480
Short name T324
Test name
Test status
Simulation time 5593698864 ps
CPU time 1181.62 seconds
Started Jul 29 08:16:15 PM PDT 24
Finished Jul 29 08:35:57 PM PDT 24
Peak memory 608936 kb
Host smart-089db948-00d0-4f7a-a956-a5cb277bad16
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36132480 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_plic_all_irqs_0.36132480
Directory /workspace/0.chip_plic_all_irqs_0/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.926906148
Short name T501
Test name
Test status
Simulation time 6001507410 ps
CPU time 522.97 seconds
Started Jul 29 07:59:30 PM PDT 24
Finished Jul 29 08:08:13 PM PDT 24
Peak memory 576052 kb
Host smart-03db51ef-70a7-44af-9684-eb5cf31b3a70
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926906148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_
with_rand_reset.926906148
Directory /workspace/56.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.281461248
Short name T453
Test name
Test status
Simulation time 11899760361 ps
CPU time 738.86 seconds
Started Jul 29 07:55:58 PM PDT 24
Finished Jul 29 08:08:17 PM PDT 24
Peak memory 576852 kb
Host smart-76593585-1c65-404e-95db-b2aff242d4f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281461248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_
with_rand_reset.281461248
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.623842904
Short name T488
Test name
Test status
Simulation time 12029136194 ps
CPU time 679.01 seconds
Started Jul 29 07:53:05 PM PDT 24
Finished Jul 29 08:04:24 PM PDT 24
Peak memory 576024 kb
Host smart-04010272-54a4-4533-b847-d364abd8ce8e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623842904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_
with_rand_reset.623842904
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.662756844
Short name T112
Test name
Test status
Simulation time 4902349030 ps
CPU time 492.91 seconds
Started Jul 29 08:16:04 PM PDT 24
Finished Jul 29 08:24:17 PM PDT 24
Peak memory 621076 kb
Host smart-41ef3f94-02b0-4bc8-a34e-d87cd0bbc2f2
User root
Command /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6
62756844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.662756844
Directory /workspace/0.chip_rv_dm_ndm_reset_req/latest

Test location /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1293033010
Short name T139
Test name
Test status
Simulation time 6083357480 ps
CPU time 571.61 seconds
Started Jul 29 08:35:06 PM PDT 24
Finished Jul 29 08:44:38 PM PDT 24
Peak memory 610520 kb
Host smart-106dbf2f-970f-456b-a7b6-950fe67b353f
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12930330
10 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.1293033010
Directory /workspace/2.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.4035713244
Short name T386
Test name
Test status
Simulation time 28175475476 ps
CPU time 3517.54 seconds
Started Jul 29 07:50:02 PM PDT 24
Finished Jul 29 08:48:40 PM PDT 24
Peak memory 593488 kb
Host smart-f6665438-99d8-46ee-837b-b263d3e39985
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035713244 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.4035713244
Directory /workspace/5.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.659298486
Short name T904
Test name
Test status
Simulation time 29895175012 ps
CPU time 1278.26 seconds
Started Jul 29 07:49:51 PM PDT 24
Finished Jul 29 08:11:10 PM PDT 24
Peak memory 582976 kb
Host smart-923db74b-a22e-4c03-9c46-6dbd635c86df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659298486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_
with_reset_error.659298486
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1252010825
Short name T167
Test name
Test status
Simulation time 2975173501 ps
CPU time 252.22 seconds
Started Jul 29 08:32:40 PM PDT 24
Finished Jul 29 08:36:52 PM PDT 24
Peak memory 623884 kb
Host smart-d0c9f651-63c8-498c-add6-37a61f2e03d7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252010825 -assert nopost
proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.1252010825
Directory /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.4025934873
Short name T191
Test name
Test status
Simulation time 7269758728 ps
CPU time 825.19 seconds
Started Jul 29 08:22:23 PM PDT 24
Finished Jul 29 08:36:10 PM PDT 24
Peak memory 611072 kb
Host smart-6bb86df3-8148-41a7-91e0-9499d269e9a8
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima
ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025934873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_
lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr
ng_lc_hw_debug_en_test.4025934873
Directory /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2294268151
Short name T87
Test name
Test status
Simulation time 79070215129 ps
CPU time 13951 seconds
Started Jul 29 08:13:41 PM PDT 24
Finished Jul 30 12:06:14 AM PDT 24
Peak memory 635132 kb
Host smart-aef7678a-2bc7-4e5f-9338-0d51043e548c
User root
Command /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2294268151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.2294268151
Directory /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.928945527
Short name T1109
Test name
Test status
Simulation time 4340455630 ps
CPU time 609.75 seconds
Started Jul 29 08:14:17 PM PDT 24
Finished Jul 29 08:24:27 PM PDT 24
Peak memory 623884 kb
Host smart-b61da222-1260-4700-91fd-de129d987c57
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928945527 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.928945527
Directory /workspace/0.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1452035747
Short name T116
Test name
Test status
Simulation time 5927201616 ps
CPU time 466.94 seconds
Started Jul 29 08:37:00 PM PDT 24
Finished Jul 29 08:44:47 PM PDT 24
Peak memory 610840 kb
Host smart-e7b57a79-93ec-406a-8e3d-ec466675f358
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul
es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1452035747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s
leep_wake_up.1452035747
Directory /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location /workspace/coverage/cover_reg_top/23.chip_tl_errors.1017839739
Short name T561
Test name
Test status
Simulation time 4005487087 ps
CPU time 259.97 seconds
Started Jul 29 07:53:05 PM PDT 24
Finished Jul 29 07:57:25 PM PDT 24
Peak memory 598568 kb
Host smart-f174275e-811b-45ca-b58e-4be19df93915
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017839739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.1017839739
Directory /workspace/23.chip_tl_errors/latest

Test location /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1688177626
Short name T201
Test name
Test status
Simulation time 4851411261 ps
CPU time 218.6 seconds
Started Jul 29 08:06:33 PM PDT 24
Finished Jul 29 08:10:12 PM PDT 24
Peak memory 649108 kb
Host smart-2dfc12af-ab0f-469b-b9d3-b2d01d925ae6
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688177626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 1.chip_padctrl_attributes.1688177626
Directory /workspace/1.chip_padctrl_attributes/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2123727259
Short name T884
Test name
Test status
Simulation time 483294141 ps
CPU time 131.55 seconds
Started Jul 29 08:00:05 PM PDT 24
Finished Jul 29 08:02:17 PM PDT 24
Peak memory 575964 kb
Host smart-be33398a-2601-473d-bc38-11c2bf53818a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123727259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al
l_with_reset_error.2123727259
Directory /workspace/59.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/default/0.chip_plic_all_irqs_10.1619936779
Short name T158
Test name
Test status
Simulation time 3489558824 ps
CPU time 437.42 seconds
Started Jul 29 08:15:10 PM PDT 24
Finished Jul 29 08:22:29 PM PDT 24
Peak memory 609752 kb
Host smart-23dcb259-b50c-4dad-9433-41ace722e15c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619936779 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.chip_plic_all_irqs_10.1619936779
Directory /workspace/0.chip_plic_all_irqs_10/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2738168213
Short name T343
Test name
Test status
Simulation time 4269051973 ps
CPU time 691.1 seconds
Started Jul 29 08:14:46 PM PDT 24
Finished Jul 29 08:26:17 PM PDT 24
Peak memory 609892 kb
Host smart-82714933-1d69-4191-a033-afacf5d2738b
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2738168213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.2738168213
Directory /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.513909038
Short name T32
Test name
Test status
Simulation time 2431636450 ps
CPU time 280.14 seconds
Started Jul 29 08:15:14 PM PDT 24
Finished Jul 29 08:19:55 PM PDT 24
Peak memory 610152 kb
Host smart-e670b95e-49c1-4b95-91a1-2428d17ca8fa
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513909038 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.513909038
Directory /workspace/0.chip_sw_spi_host_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3952445157
Short name T120
Test name
Test status
Simulation time 20313417362 ps
CPU time 744.05 seconds
Started Jul 29 08:33:25 PM PDT 24
Finished Jul 29 08:45:49 PM PDT 24
Peak memory 619412 kb
Host smart-3877b078-87fe-4a98-9a10-9412a39fccd1
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3952445157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3952445157
Directory /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.748444533
Short name T240
Test name
Test status
Simulation time 49484594226 ps
CPU time 5048.48 seconds
Started Jul 29 08:32:12 PM PDT 24
Finished Jul 29 09:56:21 PM PDT 24
Peak memory 619884 kb
Host smart-c35989db-5591-4ae2-96d1-0456d53b666e
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748444533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch
ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_
sw_lc_walkthrough_dev.748444533
Directory /workspace/2.chip_sw_lc_walkthrough_dev/latest

Test location /workspace/coverage/cover_reg_top/14.chip_tl_errors.2366347866
Short name T732
Test name
Test status
Simulation time 4139317910 ps
CPU time 370.9 seconds
Started Jul 29 07:51:31 PM PDT 24
Finished Jul 29 07:57:42 PM PDT 24
Peak memory 598780 kb
Host smart-00989b53-3c48-442b-a4fb-da8745b9e770
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366347866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.2366347866
Directory /workspace/14.chip_tl_errors/latest

Test location /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3337851332
Short name T380
Test name
Test status
Simulation time 3627050280 ps
CPU time 403.95 seconds
Started Jul 29 08:44:24 PM PDT 24
Finished Jul 29 08:51:09 PM PDT 24
Peak memory 649108 kb
Host smart-75cdbee1-51b0-4ce6-b7f5-88c4dd3422ab
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337851332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3337851332
Directory /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.1144399766
Short name T2679
Test name
Test status
Simulation time 670760469 ps
CPU time 165.38 seconds
Started Jul 29 07:53:05 PM PDT 24
Finished Jul 29 07:55:51 PM PDT 24
Peak memory 576816 kb
Host smart-11e66561-49a7-4d2e-aa56-3c5579ebe106
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144399766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al
l_with_reset_error.1144399766
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.940624737
Short name T892
Test name
Test status
Simulation time 838739773 ps
CPU time 190.53 seconds
Started Jul 29 08:04:58 PM PDT 24
Finished Jul 29 08:08:09 PM PDT 24
Peak memory 575960 kb
Host smart-1f2bd1ef-9535-46a7-83e9-4885393f0451
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940624737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all
_with_reset_error.940624737
Directory /workspace/90.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3612348015
Short name T19
Test name
Test status
Simulation time 3701779704 ps
CPU time 464.81 seconds
Started Jul 29 08:13:51 PM PDT 24
Finished Jul 29 08:21:36 PM PDT 24
Peak memory 608552 kb
Host smart-878ce257-21fa-44e2-9362-e825cf03e30d
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361234
8015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3612348015
Directory /workspace/0.chip_sw_usbdev_aon_pullup/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all.3835412666
Short name T500
Test name
Test status
Simulation time 12422944265 ps
CPU time 388.43 seconds
Started Jul 29 08:03:50 PM PDT 24
Finished Jul 29 08:10:19 PM PDT 24
Peak memory 576848 kb
Host smart-d522bee9-b57f-4ad5-b9a0-14ec2b9ff15b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835412666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.3835412666
Directory /workspace/83.xbar_stress_all/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.772373942
Short name T45
Test name
Test status
Simulation time 10141174098 ps
CPU time 2426.81 seconds
Started Jul 29 08:25:47 PM PDT 24
Finished Jul 29 09:06:14 PM PDT 24
Peak memory 624484 kb
Host smart-a350252b-10b4-429b-9ffe-451a7e8c3250
User root
Command /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77237
3942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.772373942
Directory /workspace/0.rom_e2e_jtag_debug_dev/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3317935606
Short name T137
Test name
Test status
Simulation time 5672799555 ps
CPU time 245.25 seconds
Started Jul 29 07:49:48 PM PDT 24
Finished Jul 29 07:53:54 PM PDT 24
Peak memory 660152 kb
Host smart-6641db32-fe13-40d9-8fc0-aa3963bad592
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317935606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r
eset.3317935606
Directory /workspace/2.chip_csr_hw_reset/latest

Test location /workspace/coverage/default/0.chip_plic_all_irqs_20.3179928986
Short name T323
Test name
Test status
Simulation time 5375057760 ps
CPU time 772.94 seconds
Started Jul 29 08:18:16 PM PDT 24
Finished Jul 29 08:31:10 PM PDT 24
Peak memory 610040 kb
Host smart-7f7e3dab-3488-4168-9220-553d50bf1755
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179928986 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.chip_plic_all_irqs_20.3179928986
Directory /workspace/0.chip_plic_all_irqs_20/latest

Test location /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.879818539
Short name T396
Test name
Test status
Simulation time 16824741059 ps
CPU time 1833.2 seconds
Started Jul 29 07:50:40 PM PDT 24
Finished Jul 29 08:21:14 PM PDT 24
Peak memory 593436 kb
Host smart-2114a258-4773-4185-a22a-f3dee05f0279
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879818539 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.chip_same_csr_outstanding.879818539
Directory /workspace/11.chip_same_csr_outstanding/latest

Test location /workspace/coverage/default/72.chip_sw_all_escalation_resets.1000680610
Short name T764
Test name
Test status
Simulation time 6552905128 ps
CPU time 641.5 seconds
Started Jul 29 08:48:37 PM PDT 24
Finished Jul 29 08:59:19 PM PDT 24
Peak memory 650404 kb
Host smart-858d256e-acde-4bd6-a95b-f4fd3ab18114
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1000680610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.1000680610
Directory /workspace/72.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.178919140
Short name T169
Test name
Test status
Simulation time 2572534475 ps
CPU time 116.9 seconds
Started Jul 29 08:16:16 PM PDT 24
Finished Jul 29 08:18:14 PM PDT 24
Peak memory 621668 kb
Host smart-9dc6c6af-7a6e-4748-905a-ee5f65aed580
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178919140 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.178919140
Directory /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all.2095734595
Short name T2360
Test name
Test status
Simulation time 16254120307 ps
CPU time 650.75 seconds
Started Jul 29 07:53:05 PM PDT 24
Finished Jul 29 08:03:56 PM PDT 24
Peak memory 576848 kb
Host smart-00971189-6eeb-466f-9249-d338d52d2e18
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095734595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2095734595
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all.1490909756
Short name T2085
Test name
Test status
Simulation time 9416683810 ps
CPU time 350.64 seconds
Started Jul 29 07:50:01 PM PDT 24
Finished Jul 29 07:55:51 PM PDT 24
Peak memory 576036 kb
Host smart-6875157a-fe9d-47f7-b324-40dfc0883326
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490909756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1490909756
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/default/1.chip_plic_all_irqs_10.44039742
Short name T159
Test name
Test status
Simulation time 3808245384 ps
CPU time 724.99 seconds
Started Jul 29 08:32:00 PM PDT 24
Finished Jul 29 08:44:06 PM PDT 24
Peak memory 609664 kb
Host smart-82c1613d-2e80-4f05-ac8e-1fde29764c29
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44039742 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_plic_all_irqs_10.44039742
Directory /workspace/1.chip_plic_all_irqs_10/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2366380549
Short name T2169
Test name
Test status
Simulation time 787812855 ps
CPU time 335.3 seconds
Started Jul 29 07:52:33 PM PDT 24
Finished Jul 29 07:58:08 PM PDT 24
Peak memory 575968 kb
Host smart-347de21a-9f29-4adf-aba9-e36e77f96bb3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366380549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all
_with_rand_reset.2366380549
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1423968646
Short name T1273
Test name
Test status
Simulation time 3657721298 ps
CPU time 406.18 seconds
Started Jul 29 08:14:41 PM PDT 24
Finished Jul 29 08:21:28 PM PDT 24
Peak memory 649016 kb
Host smart-cf5ea460-a15e-44b4-9c82-6fcc0e6d57c1
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423968646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s
w_alert_handler_lpg_sleep_mode_alerts.1423968646
Directory /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/0.chip_sw_all_escalation_resets.3572622674
Short name T782
Test name
Test status
Simulation time 5432243024 ps
CPU time 764.09 seconds
Started Jul 29 08:13:55 PM PDT 24
Finished Jul 29 08:26:39 PM PDT 24
Peak memory 649996 kb
Host smart-6f6e0005-12d5-409c-b1cf-34a4c91c0e87
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3572622674 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.3572622674
Directory /workspace/0.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2832952162
Short name T316
Test name
Test status
Simulation time 4138348038 ps
CPU time 551.23 seconds
Started Jul 29 08:31:37 PM PDT 24
Finished Jul 29 08:40:49 PM PDT 24
Peak memory 649280 kb
Host smart-c7054a81-205e-4ca9-bce6-ab953018b753
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832952162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s
w_alert_handler_lpg_sleep_mode_alerts.2832952162
Directory /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/1.chip_sw_all_escalation_resets.3364846180
Short name T268
Test name
Test status
Simulation time 6153243884 ps
CPU time 775.3 seconds
Started Jul 29 08:26:14 PM PDT 24
Finished Jul 29 08:39:10 PM PDT 24
Peak memory 650680 kb
Host smart-c028ff08-0793-4fdb-acfe-8ab3ffa179bf
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3364846180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.3364846180
Directory /workspace/1.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/10.chip_sw_all_escalation_resets.560248169
Short name T754
Test name
Test status
Simulation time 4729501678 ps
CPU time 718.49 seconds
Started Jul 29 08:44:58 PM PDT 24
Finished Jul 29 08:56:56 PM PDT 24
Peak memory 650316 kb
Host smart-1f1d62aa-250e-449e-876e-e86cd68c79db
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
560248169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.560248169
Directory /workspace/10.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3468077021
Short name T307
Test name
Test status
Simulation time 4326874072 ps
CPU time 354.65 seconds
Started Jul 29 08:43:13 PM PDT 24
Finished Jul 29 08:49:08 PM PDT 24
Peak memory 649544 kb
Host smart-dd67d235-41eb-4b94-95f2-14c8afb91c9b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468077021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3468077021
Directory /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/11.chip_sw_all_escalation_resets.748919061
Short name T743
Test name
Test status
Simulation time 6278750464 ps
CPU time 712.12 seconds
Started Jul 29 08:44:07 PM PDT 24
Finished Jul 29 08:56:00 PM PDT 24
Peak memory 650292 kb
Host smart-268ca253-07f7-4f53-87db-2ea7dbfde630
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
748919061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.748919061
Directory /workspace/11.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1488036829
Short name T737
Test name
Test status
Simulation time 3734136480 ps
CPU time 561.33 seconds
Started Jul 29 08:44:07 PM PDT 24
Finished Jul 29 08:53:29 PM PDT 24
Peak memory 648804 kb
Host smart-66fd3645-4ba4-4186-b6a1-c653c4fe3538
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488036829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1488036829
Directory /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/12.chip_sw_all_escalation_resets.2656295275
Short name T790
Test name
Test status
Simulation time 5536315532 ps
CPU time 572.41 seconds
Started Jul 29 08:44:00 PM PDT 24
Finished Jul 29 08:53:33 PM PDT 24
Peak memory 650592 kb
Host smart-6992cc58-520c-48ec-81cc-1b500872112b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2656295275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.2656295275
Directory /workspace/12.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2600784783
Short name T90
Test name
Test status
Simulation time 3615584808 ps
CPU time 487.28 seconds
Started Jul 29 08:43:39 PM PDT 24
Finished Jul 29 08:51:46 PM PDT 24
Peak memory 649624 kb
Host smart-ca1208b6-9a6c-46bd-bbbc-acc510e68341
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600784783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2600784783
Directory /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1448303239
Short name T794
Test name
Test status
Simulation time 4016331960 ps
CPU time 414.3 seconds
Started Jul 29 08:45:12 PM PDT 24
Finished Jul 29 08:52:07 PM PDT 24
Peak memory 649372 kb
Host smart-ebd083b8-bb93-45d1-b03d-a8272c031495
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448303239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1448303239
Directory /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/14.chip_sw_all_escalation_resets.4082794774
Short name T739
Test name
Test status
Simulation time 5429129320 ps
CPU time 626.85 seconds
Started Jul 29 08:43:06 PM PDT 24
Finished Jul 29 08:53:34 PM PDT 24
Peak memory 650292 kb
Host smart-63755445-31b8-4676-b2e8-214947209944
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4082794774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.4082794774
Directory /workspace/14.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.937246609
Short name T802
Test name
Test status
Simulation time 3834731992 ps
CPU time 418.91 seconds
Started Jul 29 08:45:02 PM PDT 24
Finished Jul 29 08:52:01 PM PDT 24
Peak memory 649524 kb
Host smart-b1e1ec68-9365-479d-b21e-eb89006515fc
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937246609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_s
w_alert_handler_lpg_sleep_mode_alerts.937246609
Directory /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/15.chip_sw_all_escalation_resets.1929401953
Short name T285
Test name
Test status
Simulation time 5238625352 ps
CPU time 612.22 seconds
Started Jul 29 08:44:45 PM PDT 24
Finished Jul 29 08:54:57 PM PDT 24
Peak memory 650396 kb
Host smart-5611544a-1e17-4885-990d-5fc04a522445
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1929401953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.1929401953
Directory /workspace/15.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1559108488
Short name T364
Test name
Test status
Simulation time 3909259456 ps
CPU time 476.39 seconds
Started Jul 29 08:43:33 PM PDT 24
Finished Jul 29 08:51:29 PM PDT 24
Peak memory 648812 kb
Host smart-9b0e6f83-f4c5-4f76-9296-dc5b6123e519
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559108488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1559108488
Directory /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/17.chip_sw_all_escalation_resets.1223056698
Short name T812
Test name
Test status
Simulation time 5449751744 ps
CPU time 572.31 seconds
Started Jul 29 08:45:50 PM PDT 24
Finished Jul 29 08:55:22 PM PDT 24
Peak memory 650396 kb
Host smart-5044bdcd-8c9d-422e-b4f4-437332b1a012
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1223056698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.1223056698
Directory /workspace/17.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1047449921
Short name T786
Test name
Test status
Simulation time 3796160312 ps
CPU time 381.67 seconds
Started Jul 29 08:45:26 PM PDT 24
Finished Jul 29 08:51:48 PM PDT 24
Peak memory 649364 kb
Host smart-76a9ec3c-d8e6-4a7b-8970-bc41dfeded1d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047449921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1047449921
Directory /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/2.chip_sw_all_escalation_resets.36235145
Short name T779
Test name
Test status
Simulation time 5756823922 ps
CPU time 550.52 seconds
Started Jul 29 08:30:30 PM PDT 24
Finished Jul 29 08:39:42 PM PDT 24
Peak memory 650892 kb
Host smart-d74deedc-27dc-4253-baa1-beab5e41f9b8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
36235145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.36235145
Directory /workspace/2.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2248972566
Short name T809
Test name
Test status
Simulation time 4021121456 ps
CPU time 292.3 seconds
Started Jul 29 08:45:33 PM PDT 24
Finished Jul 29 08:50:25 PM PDT 24
Peak memory 649088 kb
Host smart-018626bf-6af0-4a98-807c-c6bd302b578f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248972566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2248972566
Directory /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/21.chip_sw_all_escalation_resets.513039641
Short name T832
Test name
Test status
Simulation time 5760634328 ps
CPU time 509.24 seconds
Started Jul 29 08:44:34 PM PDT 24
Finished Jul 29 08:53:03 PM PDT 24
Peak memory 650312 kb
Host smart-4dd42f51-6516-4f05-a461-d640d98a7f3d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
513039641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.513039641
Directory /workspace/21.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2462330525
Short name T798
Test name
Test status
Simulation time 3456448320 ps
CPU time 374.74 seconds
Started Jul 29 08:44:20 PM PDT 24
Finished Jul 29 08:50:35 PM PDT 24
Peak memory 648908 kb
Host smart-4a6be8e3-99df-4d31-936a-f772b003841b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462330525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2462330525
Directory /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/22.chip_sw_all_escalation_resets.775262136
Short name T738
Test name
Test status
Simulation time 4234186128 ps
CPU time 530.16 seconds
Started Jul 29 08:45:53 PM PDT 24
Finished Jul 29 08:54:43 PM PDT 24
Peak memory 649708 kb
Host smart-02607618-c7bc-404c-aa14-a5859876f9a5
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
775262136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.775262136
Directory /workspace/22.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1426168947
Short name T427
Test name
Test status
Simulation time 3599887520 ps
CPU time 382.92 seconds
Started Jul 29 08:44:37 PM PDT 24
Finished Jul 29 08:51:00 PM PDT 24
Peak memory 649000 kb
Host smart-c56390e0-769f-4cf8-a4a5-1eab94e86b00
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426168947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1426168947
Directory /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/24.chip_sw_all_escalation_resets.3606164653
Short name T1311
Test name
Test status
Simulation time 5146535836 ps
CPU time 582.77 seconds
Started Jul 29 08:44:58 PM PDT 24
Finished Jul 29 08:54:41 PM PDT 24
Peak memory 650360 kb
Host smart-78c6f497-a637-4a00-b483-81863d1629cb
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3606164653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.3606164653
Directory /workspace/24.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/25.chip_sw_all_escalation_resets.3796485070
Short name T1254
Test name
Test status
Simulation time 5212976474 ps
CPU time 612.16 seconds
Started Jul 29 08:45:24 PM PDT 24
Finished Jul 29 08:55:36 PM PDT 24
Peak memory 650364 kb
Host smart-6d015a69-5d04-4d14-afd7-bed3dde592af
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3796485070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.3796485070
Directory /workspace/25.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/26.chip_sw_all_escalation_resets.537021637
Short name T775
Test name
Test status
Simulation time 6531231066 ps
CPU time 630.9 seconds
Started Jul 29 08:46:28 PM PDT 24
Finished Jul 29 08:57:00 PM PDT 24
Peak memory 650104 kb
Host smart-7e8133d9-153d-45d6-baab-ab87f6860b7d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
537021637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.537021637
Directory /workspace/26.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3420521379
Short name T771
Test name
Test status
Simulation time 4192184700 ps
CPU time 466.88 seconds
Started Jul 29 08:47:30 PM PDT 24
Finished Jul 29 08:55:17 PM PDT 24
Peak memory 648996 kb
Host smart-3158b23a-3165-4ddc-b285-7168aec91013
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420521379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3420521379
Directory /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/28.chip_sw_all_escalation_resets.2059419440
Short name T1191
Test name
Test status
Simulation time 5341201836 ps
CPU time 521.72 seconds
Started Jul 29 08:45:33 PM PDT 24
Finished Jul 29 08:54:15 PM PDT 24
Peak memory 650492 kb
Host smart-c789a52e-1dfd-47c3-8adc-2d249a8d071e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2059419440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.2059419440
Directory /workspace/28.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2102092010
Short name T163
Test name
Test status
Simulation time 3509577460 ps
CPU time 441.31 seconds
Started Jul 29 08:47:39 PM PDT 24
Finished Jul 29 08:55:01 PM PDT 24
Peak memory 648952 kb
Host smart-74d58490-8235-40a5-8abc-03758118279b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102092010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2102092010
Directory /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119619587
Short name T162
Test name
Test status
Simulation time 4155770680 ps
CPU time 386.23 seconds
Started Jul 29 08:40:34 PM PDT 24
Finished Jul 29 08:47:00 PM PDT 24
Peak memory 649136 kb
Host smart-0be97f2d-1a1e-461f-bf68-0595d1b1da3f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119619587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s
w_alert_handler_lpg_sleep_mode_alerts.2119619587
Directory /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1013849373
Short name T752
Test name
Test status
Simulation time 4115687728 ps
CPU time 418.6 seconds
Started Jul 29 08:45:11 PM PDT 24
Finished Jul 29 08:52:10 PM PDT 24
Peak memory 649020 kb
Host smart-710e51b4-bfda-4c2b-b945-a103a9ea39c4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013849373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1013849373
Directory /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/31.chip_sw_all_escalation_resets.4031596312
Short name T781
Test name
Test status
Simulation time 5134407600 ps
CPU time 693.35 seconds
Started Jul 29 08:45:32 PM PDT 24
Finished Jul 29 08:57:05 PM PDT 24
Peak memory 650420 kb
Host smart-88154c83-c712-407b-bf45-81614b0dffa6
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4031596312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.4031596312
Directory /workspace/31.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/32.chip_sw_all_escalation_resets.3044870943
Short name T766
Test name
Test status
Simulation time 6315766388 ps
CPU time 624.59 seconds
Started Jul 29 08:45:17 PM PDT 24
Finished Jul 29 08:55:41 PM PDT 24
Peak memory 650304 kb
Host smart-6b3eef31-0ff2-4654-828f-0c4b83ca2761
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3044870943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.3044870943
Directory /workspace/32.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3230293285
Short name T286
Test name
Test status
Simulation time 4318108230 ps
CPU time 353.77 seconds
Started Jul 29 08:44:53 PM PDT 24
Finished Jul 29 08:50:48 PM PDT 24
Peak memory 649500 kb
Host smart-c6251b63-9705-4ab3-853e-b69b42db9fe0
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230293285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3230293285
Directory /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/34.chip_sw_all_escalation_resets.2491143774
Short name T835
Test name
Test status
Simulation time 5627388860 ps
CPU time 573.93 seconds
Started Jul 29 08:46:52 PM PDT 24
Finished Jul 29 08:56:26 PM PDT 24
Peak memory 650224 kb
Host smart-57a8cfff-225e-4940-be5e-81029bb00402
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2491143774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.2491143774
Directory /workspace/34.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.769145143
Short name T407
Test name
Test status
Simulation time 4081903004 ps
CPU time 442.39 seconds
Started Jul 29 08:47:12 PM PDT 24
Finished Jul 29 08:54:35 PM PDT 24
Peak memory 648968 kb
Host smart-68cf8d66-be8d-4a43-af3e-0ccc44a80446
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769145143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_s
w_alert_handler_lpg_sleep_mode_alerts.769145143
Directory /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/36.chip_sw_all_escalation_resets.3205311989
Short name T711
Test name
Test status
Simulation time 5522404376 ps
CPU time 601.98 seconds
Started Jul 29 08:45:06 PM PDT 24
Finished Jul 29 08:55:08 PM PDT 24
Peak memory 650264 kb
Host smart-8eb66dd6-b582-49e8-9dfb-25046ed9bf32
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3205311989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.3205311989
Directory /workspace/36.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/37.chip_sw_all_escalation_resets.2805606349
Short name T413
Test name
Test status
Simulation time 6287744368 ps
CPU time 925.4 seconds
Started Jul 29 08:46:57 PM PDT 24
Finished Jul 29 09:02:23 PM PDT 24
Peak memory 650052 kb
Host smart-466efce4-fad3-4378-8d9f-dc619951dc78
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2805606349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.2805606349
Directory /workspace/37.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/38.chip_sw_all_escalation_resets.705133462
Short name T769
Test name
Test status
Simulation time 5646105680 ps
CPU time 556.5 seconds
Started Jul 29 08:45:10 PM PDT 24
Finished Jul 29 08:54:27 PM PDT 24
Peak memory 650436 kb
Host smart-bd774bd9-6028-4d6d-9b0e-db264582f6d0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
705133462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.705133462
Directory /workspace/38.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.180186534
Short name T787
Test name
Test status
Simulation time 4170019214 ps
CPU time 430.99 seconds
Started Jul 29 08:46:42 PM PDT 24
Finished Jul 29 08:53:53 PM PDT 24
Peak memory 649364 kb
Host smart-aa666d17-4cca-41e1-b57f-f25facaefc80
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180186534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_s
w_alert_handler_lpg_sleep_mode_alerts.180186534
Directory /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/42.chip_sw_all_escalation_resets.2734880058
Short name T459
Test name
Test status
Simulation time 5441498158 ps
CPU time 496.91 seconds
Started Jul 29 08:46:09 PM PDT 24
Finished Jul 29 08:54:26 PM PDT 24
Peak memory 650652 kb
Host smart-02d018cd-ebc4-4d04-9d62-480216b48ac8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2734880058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.2734880058
Directory /workspace/42.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/43.chip_sw_all_escalation_resets.604162141
Short name T804
Test name
Test status
Simulation time 5541108620 ps
CPU time 642.74 seconds
Started Jul 29 08:46:16 PM PDT 24
Finished Jul 29 08:56:59 PM PDT 24
Peak memory 650440 kb
Host smart-6b18c90f-b0cb-4ef4-a353-fbfcfa60de0c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
604162141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.604162141
Directory /workspace/43.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2645299729
Short name T785
Test name
Test status
Simulation time 3875039800 ps
CPU time 366.85 seconds
Started Jul 29 08:47:07 PM PDT 24
Finished Jul 29 08:53:14 PM PDT 24
Peak memory 649160 kb
Host smart-c66ade10-ce52-44ca-9239-1b318803c88e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645299729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2645299729
Directory /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2655967303
Short name T817
Test name
Test status
Simulation time 3935351536 ps
CPU time 372.06 seconds
Started Jul 29 08:48:09 PM PDT 24
Finished Jul 29 08:54:21 PM PDT 24
Peak memory 649068 kb
Host smart-b56a2bcb-66e2-41d3-9099-f9900c31be23
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655967303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2655967303
Directory /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2718299057
Short name T778
Test name
Test status
Simulation time 3991016362 ps
CPU time 366.23 seconds
Started Jul 29 08:48:01 PM PDT 24
Finished Jul 29 08:54:08 PM PDT 24
Peak memory 648676 kb
Host smart-ddc66fa0-205f-47ad-a102-da08763dc72a
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718299057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2718299057
Directory /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2106885075
Short name T371
Test name
Test status
Simulation time 3335775618 ps
CPU time 307.36 seconds
Started Jul 29 08:48:51 PM PDT 24
Finished Jul 29 08:53:59 PM PDT 24
Peak memory 648780 kb
Host smart-fcc5204e-9524-4316-bc42-bbb2c51c1f6b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106885075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2106885075
Directory /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2875831805
Short name T761
Test name
Test status
Simulation time 4483658050 ps
CPU time 446.87 seconds
Started Jul 29 08:48:44 PM PDT 24
Finished Jul 29 08:56:11 PM PDT 24
Peak memory 649360 kb
Host smart-afc61dfc-8749-46be-873a-e652a15756bd
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875831805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2875831805
Directory /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/55.chip_sw_all_escalation_resets.174194737
Short name T814
Test name
Test status
Simulation time 3998225600 ps
CPU time 737.12 seconds
Started Jul 29 08:46:57 PM PDT 24
Finished Jul 29 08:59:15 PM PDT 24
Peak memory 649656 kb
Host smart-5b9c71aa-f86d-407e-aa09-37afb06a5e52
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
174194737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.174194737
Directory /workspace/55.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/56.chip_sw_all_escalation_resets.3239997585
Short name T756
Test name
Test status
Simulation time 4950324052 ps
CPU time 684.46 seconds
Started Jul 29 08:48:17 PM PDT 24
Finished Jul 29 08:59:42 PM PDT 24
Peak memory 650428 kb
Host smart-0aac790d-1f9b-44ac-bee8-af622b12372e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3239997585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.3239997585
Directory /workspace/56.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/57.chip_sw_all_escalation_resets.2853245153
Short name T784
Test name
Test status
Simulation time 6136312154 ps
CPU time 775.26 seconds
Started Jul 29 08:50:42 PM PDT 24
Finished Jul 29 09:03:38 PM PDT 24
Peak memory 650440 kb
Host smart-415c4ee6-01fa-4eba-a552-835b733c4146
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2853245153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.2853245153
Directory /workspace/57.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/59.chip_sw_all_escalation_resets.3420833551
Short name T744
Test name
Test status
Simulation time 4918117132 ps
CPU time 414.99 seconds
Started Jul 29 08:47:16 PM PDT 24
Finished Jul 29 08:54:11 PM PDT 24
Peak memory 650036 kb
Host smart-401cfb7d-bbc3-411b-adaa-9cb4352e16ec
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3420833551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.3420833551
Directory /workspace/59.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/6.chip_sw_all_escalation_resets.722864174
Short name T755
Test name
Test status
Simulation time 5222304976 ps
CPU time 769.72 seconds
Started Jul 29 08:42:23 PM PDT 24
Finished Jul 29 08:55:13 PM PDT 24
Peak memory 650524 kb
Host smart-9df1308e-43be-4ad2-8c8e-c85f603fb154
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
722864174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.722864174
Directory /workspace/6.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/65.chip_sw_all_escalation_resets.1746233296
Short name T250
Test name
Test status
Simulation time 6093399116 ps
CPU time 623.02 seconds
Started Jul 29 08:48:37 PM PDT 24
Finished Jul 29 08:59:00 PM PDT 24
Peak memory 650468 kb
Host smart-00390082-c7eb-42b8-a123-a20de288d584
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1746233296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.1746233296
Directory /workspace/65.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3953548000
Short name T836
Test name
Test status
Simulation time 3678348560 ps
CPU time 324.05 seconds
Started Jul 29 08:49:43 PM PDT 24
Finished Jul 29 08:55:07 PM PDT 24
Peak memory 649024 kb
Host smart-66aabfdd-79aa-4983-865d-c783e9f811a2
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953548000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3953548000
Directory /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/67.chip_sw_all_escalation_resets.150060616
Short name T223
Test name
Test status
Simulation time 4925192520 ps
CPU time 517.4 seconds
Started Jul 29 08:48:28 PM PDT 24
Finished Jul 29 08:57:06 PM PDT 24
Peak memory 650044 kb
Host smart-bec261f7-68c6-4365-8192-f687712807c9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
150060616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.150060616
Directory /workspace/67.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1834123430
Short name T92
Test name
Test status
Simulation time 4075190304 ps
CPU time 438.02 seconds
Started Jul 29 08:50:26 PM PDT 24
Finished Jul 29 08:57:44 PM PDT 24
Peak memory 649132 kb
Host smart-685933fb-226a-40e3-b12c-6ae5a76c66d2
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834123430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1834123430
Directory /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3489480652
Short name T376
Test name
Test status
Simulation time 3527606934 ps
CPU time 488.14 seconds
Started Jul 29 08:48:34 PM PDT 24
Finished Jul 29 08:56:43 PM PDT 24
Peak memory 649068 kb
Host smart-98a32187-9553-439e-b48c-bc8838f032f7
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489480652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3489480652
Directory /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/76.chip_sw_all_escalation_resets.2697342020
Short name T800
Test name
Test status
Simulation time 4327608550 ps
CPU time 520.55 seconds
Started Jul 29 08:49:25 PM PDT 24
Finished Jul 29 08:58:05 PM PDT 24
Peak memory 650300 kb
Host smart-7d9874cf-0eb3-49c9-b69a-967397b8d3ec
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2697342020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.2697342020
Directory /workspace/76.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2056039516
Short name T2
Test name
Test status
Simulation time 4263753096 ps
CPU time 344.67 seconds
Started Jul 29 08:50:43 PM PDT 24
Finished Jul 29 08:56:28 PM PDT 24
Peak memory 648788 kb
Host smart-0097c0d1-96c6-447b-bd1b-632b06b770f6
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056039516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2056039516
Directory /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/8.chip_sw_all_escalation_resets.4212364338
Short name T797
Test name
Test status
Simulation time 5930817876 ps
CPU time 823.67 seconds
Started Jul 29 08:44:50 PM PDT 24
Finished Jul 29 08:58:34 PM PDT 24
Peak memory 650088 kb
Host smart-e87530c5-6b97-412c-a3ed-7e9147ba0dae
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4212364338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.4212364338
Directory /workspace/8.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/2.chip_sw_flash_init.2302711839
Short name T1355
Test name
Test status
Simulation time 23559288012 ps
CPU time 1978.91 seconds
Started Jul 29 08:33:24 PM PDT 24
Finished Jul 29 09:06:24 PM PDT 24
Peak memory 616500 kb
Host smart-f4cdc091-2d46-4fac-a807-2d1bef8c17de
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302711839 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.2302711839
Directory /workspace/2.chip_sw_flash_init/latest

Test location /workspace/coverage/cover_reg_top/27.chip_tl_errors.3032200439
Short name T558
Test name
Test status
Simulation time 4498829496 ps
CPU time 329.13 seconds
Started Jul 29 07:54:00 PM PDT 24
Finished Jul 29 07:59:29 PM PDT 24
Peak memory 603832 kb
Host smart-cc4254fc-e24e-496c-9491-5283097c56ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032200439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.3032200439
Directory /workspace/27.chip_tl_errors/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_csrng.134541844
Short name T121
Test name
Test status
Simulation time 5591400428 ps
CPU time 1221.42 seconds
Started Jul 29 08:17:59 PM PDT 24
Finished Jul 29 08:38:21 PM PDT 24
Peak memory 609476 kb
Host smart-53eb5a69-094c-45cd-ae80-40ae13d81830
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_
csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=134541844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.134541844
Directory /workspace/0.chip_sw_entropy_src_csrng/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.837391418
Short name T345
Test name
Test status
Simulation time 4296705920 ps
CPU time 633.44 seconds
Started Jul 29 08:13:19 PM PDT 24
Finished Jul 29 08:23:52 PM PDT 24
Peak memory 610132 kb
Host smart-38b9a328-41a9-44ca-bf70-68d0feaeb49f
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837391418 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.837391418
Directory /workspace/0.chip_sw_flash_ctrl_ops/latest

Test location /workspace/coverage/default/0.chip_sw_gpio.1459424129
Short name T27
Test name
Test status
Simulation time 3410057800 ps
CPU time 403.91 seconds
Started Jul 29 08:14:06 PM PDT 24
Finished Jul 29 08:20:50 PM PDT 24
Peak memory 609320 kb
Host smart-f4c7d7f5-8018-45d8-b36e-088596a9c240
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459424129 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.chip_sw_gpio.1459424129
Directory /workspace/0.chip_sw_gpio/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1457657487
Short name T340
Test name
Test status
Simulation time 3175025498 ps
CPU time 302.35 seconds
Started Jul 29 08:15:30 PM PDT 24
Finished Jul 29 08:20:33 PM PDT 24
Peak memory 609716 kb
Host smart-d5d64425-2440-4c9b-a556-2f1491c3c128
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457657487 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.1457657487
Directory /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1761375881
Short name T156
Test name
Test status
Simulation time 13730187920 ps
CPU time 2339.57 seconds
Started Jul 29 08:33:18 PM PDT 24
Finished Jul 29 09:12:18 PM PDT 24
Peak memory 610584 kb
Host smart-696ccdc1-9ad8-4091-8a30-881b67bdbef0
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=1761375881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.1761375881
Directory /workspace/2.chip_sw_rstmgr_alert_info/latest

Test location /workspace/coverage/default/20.chip_sw_all_escalation_resets.1662996137
Short name T264
Test name
Test status
Simulation time 5812332400 ps
CPU time 716.07 seconds
Started Jul 29 08:44:58 PM PDT 24
Finished Jul 29 08:56:54 PM PDT 24
Peak memory 610788 kb
Host smart-1f05646c-8b22-4dc2-813f-9de29dee0571
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1662996137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.1662996137
Directory /workspace/20.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.296488613
Short name T5
Test name
Test status
Simulation time 9125451540 ps
CPU time 605.74 seconds
Started Jul 29 08:15:15 PM PDT 24
Finished Jul 29 08:25:22 PM PDT 24
Peak memory 610724 kb
Host smart-d6ba4e72-3cbb-4e65-a338-814a101cdb44
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296488613 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.296488613
Directory /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2151899896
Short name T102
Test name
Test status
Simulation time 23940548730 ps
CPU time 1690.16 seconds
Started Jul 29 08:19:13 PM PDT 24
Finished Jul 29 08:47:24 PM PDT 24
Peak memory 611176 kb
Host smart-7bedc30d-f904-4b6e-a502-ea2f923e301e
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2151899896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2151899896
Directory /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3694364508
Short name T47
Test name
Test status
Simulation time 5615098970 ps
CPU time 560.14 seconds
Started Jul 29 08:26:22 PM PDT 24
Finished Jul 29 08:35:42 PM PDT 24
Peak memory 624452 kb
Host smart-6e288be1-ed10-4540-9783-504b80554cce
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694364508 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.3694364508
Directory /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location /workspace/coverage/default/0.chip_tap_straps_dev.1516332575
Short name T720
Test name
Test status
Simulation time 15195084831 ps
CPU time 1924.87 seconds
Started Jul 29 08:15:47 PM PDT 24
Finished Jul 29 08:47:53 PM PDT 24
Peak memory 621092 kb
Host smart-c1b20ca9-508a-428e-b7c1-1e8609d84905
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1516332575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.1516332575
Directory /workspace/0.chip_tap_straps_dev/latest

Test location /workspace/coverage/cover_reg_top/1.chip_tl_errors.954012990
Short name T731
Test name
Test status
Simulation time 4889109852 ps
CPU time 337.51 seconds
Started Jul 29 07:49:56 PM PDT 24
Finished Jul 29 07:55:34 PM PDT 24
Peak memory 603812 kb
Host smart-12aecf62-c441-4ddc-9db9-9e334ffb0e87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954012990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.954012990
Directory /workspace/1.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3847282583
Short name T134
Test name
Test status
Simulation time 5624109280 ps
CPU time 247.1 seconds
Started Jul 29 07:49:57 PM PDT 24
Finished Jul 29 07:54:05 PM PDT 24
Peak memory 663092 kb
Host smart-1f7a4079-6a35-421a-b0b7-a0ad781f6d30
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847282583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r
eset.3847282583
Directory /workspace/3.chip_csr_hw_reset/latest

Test location /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.551772071
Short name T141
Test name
Test status
Simulation time 19730723130 ps
CPU time 3239.08 seconds
Started Jul 29 08:16:45 PM PDT 24
Finished Jul 29 09:10:45 PM PDT 24
Peak memory 611088 kb
Host smart-2b23385f-04fd-4b98-b923-94b28ec64ccd
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551772071 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.551772071
Directory /workspace/0.chip_sw_ast_clk_rst_inputs/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2438147294
Short name T228
Test name
Test status
Simulation time 9559259804 ps
CPU time 1986.99 seconds
Started Jul 29 08:37:44 PM PDT 24
Finished Jul 29 09:10:51 PM PDT 24
Peak memory 611148 kb
Host smart-e4267283-24cb-4959-ac65-3188c4a5361c
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243814
7294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.2438147294
Directory /workspace/2.chip_sw_keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.chip_sw_plic_sw_irq.1412652380
Short name T257
Test name
Test status
Simulation time 2396106248 ps
CPU time 262.99 seconds
Started Jul 29 08:15:42 PM PDT 24
Finished Jul 29 08:20:05 PM PDT 24
Peak memory 609720 kb
Host smart-9e469b93-e1c6-4f9a-a0a0-63e9fe5962b7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412652380 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.chip_sw_plic_sw_irq.1412652380
Directory /workspace/0.chip_sw_plic_sw_irq/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1830839024
Short name T461
Test name
Test status
Simulation time 8797396104 ps
CPU time 2269.29 seconds
Started Jul 29 08:16:21 PM PDT 24
Finished Jul 29 08:54:11 PM PDT 24
Peak memory 610280 kb
Host smart-8a4a0e82-1e41-47a0-8dcb-4ddbc0165e79
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1830839024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.1830839024
Directory /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3007840538
Short name T60
Test name
Test status
Simulation time 5093443000 ps
CPU time 529.28 seconds
Started Jul 29 08:17:47 PM PDT 24
Finished Jul 29 08:26:37 PM PDT 24
Peak memory 611068 kb
Host smart-acc8b0d6-4230-4d9b-99d0-386e582c27f4
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3007840538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.3007840538
Directory /workspace/0.chip_sw_lc_ctrl_program_error/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.100015246
Short name T148
Test name
Test status
Simulation time 10469090753 ps
CPU time 788.37 seconds
Started Jul 29 08:14:44 PM PDT 24
Finished Jul 29 08:27:53 PM PDT 24
Peak memory 620684 kb
Host smart-6104f81d-081e-4726-861e-5d27539d71f8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100015246 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.100015246
Directory /workspace/0.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3912291924
Short name T1068
Test name
Test status
Simulation time 7516482120 ps
CPU time 632.53 seconds
Started Jul 29 08:17:35 PM PDT 24
Finished Jul 29 08:28:08 PM PDT 24
Peak memory 616608 kb
Host smart-41e46df5-fa46-431a-80b1-507c8d1482e5
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3912291924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3912291924
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2329326094
Short name T210
Test name
Test status
Simulation time 2891921523 ps
CPU time 272.12 seconds
Started Jul 29 08:14:32 PM PDT 24
Finished Jul 29 08:19:05 PM PDT 24
Peak memory 612708 kb
Host smart-e4ab36a8-5836-46ea-87bf-46223c5d717a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329326094 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.2329326094
Directory /workspace/0.chip_sw_sysrst_ctrl_inputs/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2844649311
Short name T168
Test name
Test status
Simulation time 3256385718 ps
CPU time 280.53 seconds
Started Jul 29 08:27:01 PM PDT 24
Finished Jul 29 08:31:42 PM PDT 24
Peak memory 623896 kb
Host smart-b7a4793f-e621-4843-a438-1a888f506a1a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844649311 -assert nopost
proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.2844649311
Directory /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location /workspace/coverage/cover_reg_top/13.chip_tl_errors.3994077267
Short name T570
Test name
Test status
Simulation time 3701478175 ps
CPU time 194.75 seconds
Started Jul 29 07:51:14 PM PDT 24
Finished Jul 29 07:54:28 PM PDT 24
Peak memory 598712 kb
Host smart-ca22869a-2b30-4037-a381-d6a5e5b14fc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994077267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.3994077267
Directory /workspace/13.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.619356594
Short name T655
Test name
Test status
Simulation time 1418169484 ps
CPU time 107.4 seconds
Started Jul 29 07:51:32 PM PDT 24
Finished Jul 29 07:53:19 PM PDT 24
Peak memory 576116 kb
Host smart-9422c10f-cf15-4133-9f4b-68c583ecbd2a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619356594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.619356594
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/16.chip_tl_errors.4977068
Short name T717
Test name
Test status
Simulation time 4066829436 ps
CPU time 333.64 seconds
Started Jul 29 07:52:01 PM PDT 24
Finished Jul 29 07:57:35 PM PDT 24
Peak memory 603916 kb
Host smart-b3d2071e-cce8-4a26-a1f8-108c0602613d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4977068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.4977068
Directory /workspace/16.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.1556720458
Short name T433
Test name
Test status
Simulation time 31486697000 ps
CPU time 318.46 seconds
Started Jul 29 07:52:44 PM PDT 24
Finished Jul 29 07:58:02 PM PDT 24
Peak memory 575964 kb
Host smart-e9926f8c-c6e4-4132-8f22-91c31d841060
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556720458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1556720458
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.903114721
Short name T663
Test name
Test status
Simulation time 6314256917 ps
CPU time 484.6 seconds
Started Jul 29 07:53:56 PM PDT 24
Finished Jul 29 08:02:01 PM PDT 24
Peak memory 576060 kb
Host smart-0ca6605f-a281-43b9-a391-9ba46aa138ac
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903114721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all
_with_reset_error.903114721
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.1995009274
Short name T727
Test name
Test status
Simulation time 4129248016 ps
CPU time 159.62 seconds
Started Jul 29 07:55:58 PM PDT 24
Finished Jul 29 07:58:38 PM PDT 24
Peak memory 576036 kb
Host smart-ffcd2446-c190-4a33-b7d3-0e4483036c1f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995009274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1995009274
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.640228641
Short name T650
Test name
Test status
Simulation time 16247811692 ps
CPU time 731.44 seconds
Started Jul 29 08:00:32 PM PDT 24
Finished Jul 29 08:12:43 PM PDT 24
Peak memory 576852 kb
Host smart-1a36df1f-9fc3-4038-ad3a-84d7f2bad1eb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640228641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all
_with_reset_error.640228641
Directory /workspace/63.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.3258814498
Short name T728
Test name
Test status
Simulation time 20346409951 ps
CPU time 782.89 seconds
Started Jul 29 08:01:09 PM PDT 24
Finished Jul 29 08:14:13 PM PDT 24
Peak memory 576864 kb
Host smart-44745d63-a0ea-4f92-afe4-34428279a750
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258814498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.3258814498
Directory /workspace/65.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.1631200723
Short name T652
Test name
Test status
Simulation time 5676733380 ps
CPU time 330.88 seconds
Started Jul 29 08:01:59 PM PDT 24
Finished Jul 29 08:07:30 PM PDT 24
Peak memory 576960 kb
Host smart-6cd607af-c031-4abb-b603-c0458123363c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631200723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al
l_with_reset_error.1631200723
Directory /workspace/71.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_error_random.3536858615
Short name T657
Test name
Test status
Simulation time 1654253068 ps
CPU time 56.42 seconds
Started Jul 29 08:02:19 PM PDT 24
Finished Jul 29 08:03:16 PM PDT 24
Peak memory 575952 kb
Host smart-7eb13fe5-8c30-48cd-a58f-a70df55acbd2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536858615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.3536858615
Directory /workspace/74.xbar_error_random/latest

Test location /workspace/coverage/default/0.chip_jtag_csr_rw.1980270906
Short name T49
Test name
Test status
Simulation time 11370079889 ps
CPU time 1057.78 seconds
Started Jul 29 08:08:42 PM PDT 24
Finished Jul 29 08:26:20 PM PDT 24
Peak memory 608056 kb
Host smart-a46f56bc-1314-4df4-9aba-a593c17cc8fa
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980270906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c
hip_jtag_csr_rw.1980270906
Directory /workspace/0.chip_jtag_csr_rw/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_irq.1048145236
Short name T362
Test name
Test status
Simulation time 3556614720 ps
CPU time 407.36 seconds
Started Jul 29 08:14:44 PM PDT 24
Finished Jul 29 08:21:32 PM PDT 24
Peak memory 609760 kb
Host smart-8a26573e-5f29-4bd8-b7a3-df0be6389fee
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048145236 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.1048145236
Directory /workspace/0.chip_sw_aon_timer_irq/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3544699050
Short name T339
Test name
Test status
Simulation time 4076787816 ps
CPU time 547.77 seconds
Started Jul 29 08:15:40 PM PDT 24
Finished Jul 29 08:24:48 PM PDT 24
Peak memory 609492 kb
Host smart-0597c060-2453-415d-8e46-266d24073b35
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544699050 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.3544699050
Directory /workspace/0.chip_sw_i2c_device_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3123776158
Short name T328
Test name
Test status
Simulation time 13109768028 ps
CPU time 2187.28 seconds
Started Jul 29 08:14:10 PM PDT 24
Finished Jul 29 08:50:37 PM PDT 24
Peak memory 610996 kb
Host smart-63bdd1b8-1f12-41ec-90ef-5d898ccc4a2c
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=3123776158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.3123776158
Directory /workspace/0.chip_sw_rstmgr_alert_info/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2179098780
Short name T746
Test name
Test status
Simulation time 4840045924 ps
CPU time 832.13 seconds
Started Jul 29 08:15:46 PM PDT 24
Finished Jul 29 08:29:39 PM PDT 24
Peak memory 610160 kb
Host smart-c6f46e04-fdab-44d3-836c-4bb568af4629
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21790
98780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.2179098780
Directory /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3611252911
Short name T338
Test name
Test status
Simulation time 4382422824 ps
CPU time 564.43 seconds
Started Jul 29 08:26:11 PM PDT 24
Finished Jul 29 08:35:36 PM PDT 24
Peak memory 609784 kb
Host smart-47db5e44-7916-4aa1-977b-ced009e69221
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611252911 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.3611252911
Directory /workspace/1.chip_sw_i2c_device_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2629609584
Short name T342
Test name
Test status
Simulation time 3894331924 ps
CPU time 512.46 seconds
Started Jul 29 08:27:47 PM PDT 24
Finished Jul 29 08:36:21 PM PDT 24
Peak memory 609712 kb
Host smart-8559b8cc-c4d1-41ff-bc3e-699066a05d1b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629609584 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.2629609584
Directory /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest

Test location /workspace/coverage/default/0.chip_tap_straps_rma.1073786890
Short name T1287
Test name
Test status
Simulation time 4271939273 ps
CPU time 331.18 seconds
Started Jul 29 08:14:34 PM PDT 24
Finished Jul 29 08:20:06 PM PDT 24
Peak memory 620948 kb
Host smart-215d5c3b-2922-42b4-904a-e6e6ae29fc5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073786890 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.1073786890
Directory /workspace/0.chip_tap_straps_rma/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1631675559
Short name T138
Test name
Test status
Simulation time 6217297180 ps
CPU time 343.89 seconds
Started Jul 29 07:49:56 PM PDT 24
Finished Jul 29 07:55:40 PM PDT 24
Peak memory 663468 kb
Host smart-4501b718-b869-4e1a-b53f-a16e3edfb84c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631675559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r
eset.1631675559
Directory /workspace/0.chip_csr_hw_reset/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.663545087
Short name T309
Test name
Test status
Simulation time 7913919172 ps
CPU time 1679.54 seconds
Started Jul 29 08:16:59 PM PDT 24
Finished Jul 29 08:44:59 PM PDT 24
Peak memory 610028 kb
Host smart-d6453577-13f7-4b5e-984e-1db1657cf85e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=663545087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.663545087
Directory /workspace/0.chip_sw_alert_handler_ping_ok/latest

Test location /workspace/coverage/default/0.chip_sw_edn_boot_mode.2774195302
Short name T701
Test name
Test status
Simulation time 2781796960 ps
CPU time 502.29 seconds
Started Jul 29 08:16:33 PM PDT 24
Finished Jul 29 08:24:56 PM PDT 24
Peak memory 609780 kb
Host smart-e385218e-80d0-4835-94aa-cd10e96bc2f6
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774195302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_
boot_mode.2774195302
Directory /workspace/0.chip_sw_edn_boot_mode/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.184709606
Short name T1024
Test name
Test status
Simulation time 18973151120 ps
CPU time 3882.19 seconds
Started Jul 29 08:13:58 PM PDT 24
Finished Jul 29 09:18:41 PM PDT 24
Peak memory 610260 kb
Host smart-491df676-b752-4081-a560-96eb7235087c
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne
w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=184709606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.184709606
Directory /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1593524479
Short name T195
Test name
Test status
Simulation time 4629174658 ps
CPU time 499.07 seconds
Started Jul 29 08:14:14 PM PDT 24
Finished Jul 29 08:22:33 PM PDT 24
Peak memory 609744 kb
Host smart-824d7bfb-dba0-4665-9d5f-47c6880dff8e
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15935
24479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.1593524479
Directory /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3391338503
Short name T95
Test name
Test status
Simulation time 23739840360 ps
CPU time 5635.78 seconds
Started Jul 29 08:31:08 PM PDT 24
Finished Jul 29 10:05:05 PM PDT 24
Peak memory 610016 kb
Host smart-84fc5e47-d461-49bc-a232-5db2348d8731
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3391338503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3391338503
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3978050088
Short name T392
Test name
Test status
Simulation time 2196959284 ps
CPU time 144.93 seconds
Started Jul 29 08:30:59 PM PDT 24
Finished Jul 29 08:33:25 PM PDT 24
Peak memory 645684 kb
Host smart-cb4177b6-8b58-4ca0-a447-fe6240d8b931
User root
Command /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978050088 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.3978050088
Directory /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.303605765
Short name T395
Test name
Test status
Simulation time 32257725103 ps
CPU time 5558.59 seconds
Started Jul 29 07:49:41 PM PDT 24
Finished Jul 29 09:22:20 PM PDT 24
Peak memory 593860 kb
Host smart-336a2dab-afef-42df-9e31-3b92c29cbb36
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303605765 -assert nopostproc +UVM_TESTNAME=chip_b
ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.chip_csr_aliasing.303605765
Directory /workspace/0.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2294649792
Short name T1543
Test name
Test status
Simulation time 31997881450 ps
CPU time 3818.43 seconds
Started Jul 29 07:49:30 PM PDT 24
Finished Jul 29 08:53:09 PM PDT 24
Peak memory 592716 kb
Host smart-d7862468-6376-45a7-af39-45c792dd9584
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294649792 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.2294649792
Directory /workspace/0.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.4102579681
Short name T2338
Test name
Test status
Simulation time 6472048008 ps
CPU time 422.06 seconds
Started Jul 29 07:49:52 PM PDT 24
Finished Jul 29 07:56:54 PM PDT 24
Peak memory 640720 kb
Host smart-12e1d200-6b57-4ae7-96dd-c0cda8f79c69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102579681 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.4102579681
Directory /workspace/0.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_rw.1615346281
Short name T418
Test name
Test status
Simulation time 4096407246 ps
CPU time 303.25 seconds
Started Jul 29 07:49:49 PM PDT 24
Finished Jul 29 07:54:52 PM PDT 24
Peak memory 597368 kb
Host smart-a0f225f1-32b8-4e47-b1c2-4db74ba4f4bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615346281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.1615346281
Directory /workspace/0.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1810715771
Short name T907
Test name
Test status
Simulation time 6374362060 ps
CPU time 252.69 seconds
Started Jul 29 07:49:42 PM PDT 24
Finished Jul 29 07:53:55 PM PDT 24
Peak memory 590132 kb
Host smart-c032195a-a1d1-4c65-8a57-fd555d7cda12
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810715771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.chip_prim_tl_access.1810715771
Directory /workspace/0.chip_prim_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.712566782
Short name T1826
Test name
Test status
Simulation time 10704411746 ps
CPU time 443.46 seconds
Started Jul 29 07:49:41 PM PDT 24
Finished Jul 29 07:57:05 PM PDT 24
Peak memory 590464 kb
Host smart-a8b79e6c-5884-45c8-898c-3a2f993995b3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712566782 -assert nopostproc +UVM_TESTNAME=chip_base_te
st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.chip_rv_dm_lc_disabled.712566782
Directory /workspace/0.chip_rv_dm_lc_disabled/latest

Test location /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3280537990
Short name T384
Test name
Test status
Simulation time 15575305736 ps
CPU time 1772.55 seconds
Started Jul 29 07:49:36 PM PDT 24
Finished Jul 29 08:19:08 PM PDT 24
Peak memory 593200 kb
Host smart-52a52d5d-5d81-4e61-b77c-ceca2607831a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280537990 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.3280537990
Directory /workspace/0.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.chip_tl_errors.1895306351
Short name T2373
Test name
Test status
Simulation time 3297692925 ps
CPU time 157.87 seconds
Started Jul 29 07:49:43 PM PDT 24
Finished Jul 29 07:52:21 PM PDT 24
Peak memory 598676 kb
Host smart-fccfe149-c1e3-4006-8754-8f3a55df61c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895306351 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.1895306351
Directory /workspace/0.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_access_same_device.2797981352
Short name T1603
Test name
Test status
Simulation time 872439757 ps
CPU time 58.74 seconds
Started Jul 29 07:50:07 PM PDT 24
Finished Jul 29 07:51:05 PM PDT 24
Peak memory 575732 kb
Host smart-7c9aa5ed-c126-4ac1-aef0-2208e0610fdd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797981352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.
2797981352
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.425170838
Short name T876
Test name
Test status
Simulation time 143759866351 ps
CPU time 2486.29 seconds
Started Jul 29 07:49:49 PM PDT 24
Finished Jul 29 08:31:16 PM PDT 24
Peak memory 576136 kb
Host smart-826a5913-3b87-4189-9420-5eb2e0da5c75
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425170838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_de
vice_slow_rsp.425170838
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2867148164
Short name T2293
Test name
Test status
Simulation time 189072861 ps
CPU time 10.16 seconds
Started Jul 29 07:49:56 PM PDT 24
Finished Jul 29 07:50:06 PM PDT 24
Peak memory 576012 kb
Host smart-13d024ea-39ea-49fb-957c-0f0d022064b1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867148164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr
.2867148164
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_error_random.3981927165
Short name T1458
Test name
Test status
Simulation time 2091660347 ps
CPU time 68.48 seconds
Started Jul 29 07:50:03 PM PDT 24
Finished Jul 29 07:51:12 PM PDT 24
Peak memory 575992 kb
Host smart-c1113145-c0cd-4d82-9238-f9a2937ee39c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981927165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3981927165
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random.4121286336
Short name T1760
Test name
Test status
Simulation time 1350035900 ps
CPU time 38.95 seconds
Started Jul 29 07:50:04 PM PDT 24
Finished Jul 29 07:50:43 PM PDT 24
Peak memory 575968 kb
Host smart-7881e55e-4f62-47c5-894b-be4e01034876
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121286336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.4121286336
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.461325812
Short name T2080
Test name
Test status
Simulation time 89956528047 ps
CPU time 929.43 seconds
Started Jul 29 07:49:50 PM PDT 24
Finished Jul 29 08:05:19 PM PDT 24
Peak memory 575868 kb
Host smart-49c4a787-0785-4e52-a481-e134e717516c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461325812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.461325812
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.827584826
Short name T1538
Test name
Test status
Simulation time 4302276459 ps
CPU time 69.21 seconds
Started Jul 29 07:49:49 PM PDT 24
Finished Jul 29 07:50:58 PM PDT 24
Peak memory 574604 kb
Host smart-5002bb1f-4be6-4633-a489-1a111ab3db24
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827584826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.827584826
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1295449300
Short name T2872
Test name
Test status
Simulation time 385700231 ps
CPU time 36.88 seconds
Started Jul 29 07:49:51 PM PDT 24
Finished Jul 29 07:50:28 PM PDT 24
Peak memory 576096 kb
Host smart-68b2e9e0-669c-4e65-9ac8-7661fb721b82
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295449300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela
ys.1295449300
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_same_source.3288766974
Short name T1765
Test name
Test status
Simulation time 395518814 ps
CPU time 27.99 seconds
Started Jul 29 07:49:52 PM PDT 24
Finished Jul 29 07:50:21 PM PDT 24
Peak memory 575828 kb
Host smart-223145ad-28fc-4408-b7a5-17eb7eb93b88
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288766974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3288766974
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke.1343899973
Short name T2319
Test name
Test status
Simulation time 217447304 ps
CPU time 8.9 seconds
Started Jul 29 07:49:42 PM PDT 24
Finished Jul 29 07:49:51 PM PDT 24
Peak memory 573852 kb
Host smart-ab7000f0-48e1-4aca-a13d-1f0740b80e42
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343899973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1343899973
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3836726339
Short name T1470
Test name
Test status
Simulation time 10267158571 ps
CPU time 103.68 seconds
Started Jul 29 07:49:38 PM PDT 24
Finished Jul 29 07:51:22 PM PDT 24
Peak memory 574652 kb
Host smart-43865a94-2630-4d8f-868b-7898d1de5569
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836726339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3836726339
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2352213312
Short name T2211
Test name
Test status
Simulation time 5068579100 ps
CPU time 85.07 seconds
Started Jul 29 07:49:55 PM PDT 24
Finished Jul 29 07:51:21 PM PDT 24
Peak memory 573992 kb
Host smart-957b3e61-3f7a-4155-bab8-25f5914f4be0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352213312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2352213312
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.4093529063
Short name T2422
Test name
Test status
Simulation time 51541985 ps
CPU time 6.88 seconds
Started Jul 29 07:49:40 PM PDT 24
Finished Jul 29 07:49:47 PM PDT 24
Peak memory 574640 kb
Host smart-7df8afd3-92b6-4e29-b733-75034df209ea
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093529063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays
.4093529063
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all.2777056359
Short name T503
Test name
Test status
Simulation time 3816280640 ps
CPU time 327.66 seconds
Started Jul 29 07:49:53 PM PDT 24
Finished Jul 29 07:55:20 PM PDT 24
Peak memory 576024 kb
Host smart-d9c3c762-9c9a-499c-915b-411d7ade312b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777056359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2777056359
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2792266896
Short name T2690
Test name
Test status
Simulation time 356055683 ps
CPU time 120.61 seconds
Started Jul 29 07:49:52 PM PDT 24
Finished Jul 29 07:51:52 PM PDT 24
Peak memory 576748 kb
Host smart-c6cd6085-1c8f-4ff6-a648-ebe51af4afe9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792266896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_
with_rand_reset.2792266896
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2113901587
Short name T2488
Test name
Test status
Simulation time 1383124554 ps
CPU time 61.62 seconds
Started Jul 29 07:49:46 PM PDT 24
Finished Jul 29 07:50:48 PM PDT 24
Peak memory 575960 kb
Host smart-bfe763fa-c865-4036-b114-abd2c485baa8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113901587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2113901587
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3166020062
Short name T1988
Test name
Test status
Simulation time 41064703454 ps
CPU time 6232.89 seconds
Started Jul 29 07:49:49 PM PDT 24
Finished Jul 29 09:33:43 PM PDT 24
Peak memory 594224 kb
Host smart-a074a142-c7c2-4f06-93c8-011a665a3ee9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166020062 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.chip_csr_aliasing.3166020062
Directory /workspace/1.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2847298876
Short name T1524
Test name
Test status
Simulation time 7574904128 ps
CPU time 869.18 seconds
Started Jul 29 07:50:06 PM PDT 24
Finished Jul 29 08:04:35 PM PDT 24
Peak memory 590464 kb
Host smart-0fd1a4ba-3e1d-4a51-8759-b38057f1a907
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847298876 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.2847298876
Directory /workspace/1.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1105316616
Short name T135
Test name
Test status
Simulation time 5045801682 ps
CPU time 238.58 seconds
Started Jul 29 07:49:50 PM PDT 24
Finished Jul 29 07:53:48 PM PDT 24
Peak memory 663824 kb
Host smart-385ccd22-c0e0-41c9-bc33-a050aa755545
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105316616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r
eset.1105316616
Directory /workspace/1.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1565873531
Short name T2494
Test name
Test status
Simulation time 11297563390 ps
CPU time 714.87 seconds
Started Jul 29 07:49:48 PM PDT 24
Finished Jul 29 08:01:43 PM PDT 24
Peak memory 649864 kb
Host smart-bf29a03b-4307-438d-aee4-c9a2f87fd87d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565873531 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.1565873531
Directory /workspace/1.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_rw.2577704228
Short name T532
Test name
Test status
Simulation time 6516545204 ps
CPU time 541.15 seconds
Started Jul 29 07:50:07 PM PDT 24
Finished Jul 29 07:59:08 PM PDT 24
Peak memory 599300 kb
Host smart-a1cba318-ad2f-4b53-bf42-d9c4a6023e4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577704228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.2577704228
Directory /workspace/1.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.3437357780
Short name T2616
Test name
Test status
Simulation time 12299886685 ps
CPU time 397.51 seconds
Started Jul 29 07:49:47 PM PDT 24
Finished Jul 29 07:56:24 PM PDT 24
Peak memory 590196 kb
Host smart-13fbcc33-c0e4-41ad-aa64-520fc01167dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437357780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.chip_prim_tl_access.3437357780
Directory /workspace/1.chip_prim_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2725359171
Short name T2359
Test name
Test status
Simulation time 9073350084 ps
CPU time 339.06 seconds
Started Jul 29 07:49:45 PM PDT 24
Finished Jul 29 07:55:24 PM PDT 24
Peak memory 591364 kb
Host smart-c9cb0fbc-1dde-4d07-9fb2-f40387b767f1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725359171 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.chip_rv_dm_lc_disabled.2725359171
Directory /workspace/1.chip_rv_dm_lc_disabled/latest

Test location /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2339950163
Short name T2538
Test name
Test status
Simulation time 13586978068 ps
CPU time 1672.72 seconds
Started Jul 29 07:49:48 PM PDT 24
Finished Jul 29 08:17:40 PM PDT 24
Peak memory 593176 kb
Host smart-117f7131-05a9-41f3-a338-2160e7db5c1a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339950163 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.2339950163
Directory /workspace/1.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_access_same_device.3131499970
Short name T840
Test name
Test status
Simulation time 2404452091 ps
CPU time 105.54 seconds
Started Jul 29 07:49:50 PM PDT 24
Finished Jul 29 07:51:36 PM PDT 24
Peak memory 576092 kb
Host smart-2ff0c7ae-c85e-48c6-84fb-5c5911762be1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131499970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.
3131499970
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.4071833388
Short name T2708
Test name
Test status
Simulation time 138491269460 ps
CPU time 2316.8 seconds
Started Jul 29 07:50:03 PM PDT 24
Finished Jul 29 08:28:41 PM PDT 24
Peak memory 576108 kb
Host smart-2284bf8c-2cef-4acc-ba0d-4c379affb3bd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071833388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d
evice_slow_rsp.4071833388
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2139221632
Short name T2354
Test name
Test status
Simulation time 256893286 ps
CPU time 24.31 seconds
Started Jul 29 07:49:47 PM PDT 24
Finished Jul 29 07:50:11 PM PDT 24
Peak memory 576048 kb
Host smart-43643522-c251-4851-a73e-4df568da99a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139221632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr
.2139221632
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_error_random.1056074122
Short name T1617
Test name
Test status
Simulation time 1239826623 ps
CPU time 40.15 seconds
Started Jul 29 07:50:06 PM PDT 24
Finished Jul 29 07:50:46 PM PDT 24
Peak memory 575832 kb
Host smart-4f74e039-282f-4db4-a63b-13cba8504c06
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056074122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1056074122
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random.1852183869
Short name T2163
Test name
Test status
Simulation time 67771638 ps
CPU time 9.02 seconds
Started Jul 29 07:49:56 PM PDT 24
Finished Jul 29 07:50:05 PM PDT 24
Peak memory 575844 kb
Host smart-3e0a281e-8cca-4d35-b420-f72207a9a673
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852183869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.1852183869
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.782456002
Short name T528
Test name
Test status
Simulation time 102211761397 ps
CPU time 1150.76 seconds
Started Jul 29 07:49:51 PM PDT 24
Finished Jul 29 08:09:02 PM PDT 24
Peak memory 575884 kb
Host smart-0311657b-0fe1-45cb-adbd-43e25dfd951f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782456002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.782456002
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2869650944
Short name T1829
Test name
Test status
Simulation time 52299602246 ps
CPU time 898.85 seconds
Started Jul 29 07:49:48 PM PDT 24
Finished Jul 29 08:04:47 PM PDT 24
Peak memory 576032 kb
Host smart-b7f85ba6-ed03-4610-b4e3-8cd062509e4c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869650944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2869650944
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.226795195
Short name T1990
Test name
Test status
Simulation time 100038389 ps
CPU time 11.25 seconds
Started Jul 29 07:49:52 PM PDT 24
Finished Jul 29 07:50:04 PM PDT 24
Peak memory 575936 kb
Host smart-6a6bfab2-6587-4794-b713-c14986d339f3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226795195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delay
s.226795195
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_same_source.1058423167
Short name T2607
Test name
Test status
Simulation time 146744937 ps
CPU time 13.19 seconds
Started Jul 29 07:49:48 PM PDT 24
Finished Jul 29 07:50:01 PM PDT 24
Peak memory 575948 kb
Host smart-10c18ffe-89b7-4935-8c7e-855712cc8cf1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058423167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.1058423167
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke.3293930254
Short name T1964
Test name
Test status
Simulation time 58406258 ps
CPU time 6.75 seconds
Started Jul 29 07:50:01 PM PDT 24
Finished Jul 29 07:50:08 PM PDT 24
Peak memory 573844 kb
Host smart-1b3efa95-4435-40c7-b9fe-1d347de5ce06
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293930254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3293930254
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3529031021
Short name T541
Test name
Test status
Simulation time 8863360802 ps
CPU time 99.17 seconds
Started Jul 29 07:49:47 PM PDT 24
Finished Jul 29 07:51:26 PM PDT 24
Peak memory 574776 kb
Host smart-99db78d2-7015-4fbd-bce6-e3751be0e6cd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529031021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3529031021
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2999844136
Short name T2833
Test name
Test status
Simulation time 5302020624 ps
CPU time 90.67 seconds
Started Jul 29 07:49:52 PM PDT 24
Finished Jul 29 07:51:23 PM PDT 24
Peak memory 574624 kb
Host smart-536420cb-4810-4018-94ee-13623419c700
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999844136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2999844136
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1027145520
Short name T2095
Test name
Test status
Simulation time 48350192 ps
CPU time 5.97 seconds
Started Jul 29 07:50:03 PM PDT 24
Finished Jul 29 07:50:09 PM PDT 24
Peak memory 574580 kb
Host smart-7867445e-6885-4c7c-abdd-44fa60803c31
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027145520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays
.1027145520
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all.3572679677
Short name T2164
Test name
Test status
Simulation time 2794026365 ps
CPU time 209.18 seconds
Started Jul 29 07:49:49 PM PDT 24
Finished Jul 29 07:53:19 PM PDT 24
Peak memory 576024 kb
Host smart-fdd491de-7576-4593-aec1-46861489a51c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572679677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3572679677
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.143380337
Short name T2601
Test name
Test status
Simulation time 8326071500 ps
CPU time 279.72 seconds
Started Jul 29 07:49:56 PM PDT 24
Finished Jul 29 07:54:36 PM PDT 24
Peak memory 576832 kb
Host smart-4496479b-8739-4236-94e5-13cde749a562
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143380337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.143380337
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2783337350
Short name T2544
Test name
Test status
Simulation time 90534370 ps
CPU time 27.88 seconds
Started Jul 29 07:49:50 PM PDT 24
Finished Jul 29 07:50:18 PM PDT 24
Peak memory 576008 kb
Host smart-ba1c8e41-d42f-4a85-8d93-e1138d9cbcfb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783337350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_
with_rand_reset.2783337350
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1434476597
Short name T2143
Test name
Test status
Simulation time 128249378 ps
CPU time 36.33 seconds
Started Jul 29 07:49:49 PM PDT 24
Finished Jul 29 07:50:26 PM PDT 24
Peak memory 576136 kb
Host smart-8ee6fa90-947a-49a8-b9d8-e2cc1d97419e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434476597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all
_with_reset_error.1434476597
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2860346400
Short name T1483
Test name
Test status
Simulation time 366446718 ps
CPU time 17.31 seconds
Started Jul 29 07:49:57 PM PDT 24
Finished Jul 29 07:50:14 PM PDT 24
Peak memory 576032 kb
Host smart-1f5e513a-4603-4174-b9fb-36cfd16ca2e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860346400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2860346400
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3277914742
Short name T2536
Test name
Test status
Simulation time 11169384119 ps
CPU time 907.06 seconds
Started Jul 29 07:50:41 PM PDT 24
Finished Jul 29 08:05:48 PM PDT 24
Peak memory 652916 kb
Host smart-bba9100f-278d-442d-a15d-df2e92b90939
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277914742 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.3277914742
Directory /workspace/10.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.chip_csr_rw.2796361123
Short name T2450
Test name
Test status
Simulation time 5272888244 ps
CPU time 505.32 seconds
Started Jul 29 07:50:22 PM PDT 24
Finished Jul 29 07:58:47 PM PDT 24
Peak memory 598632 kb
Host smart-a2c26226-cc2f-4f14-9978-cc5a11ce6440
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796361123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.2796361123
Directory /workspace/10.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1653422229
Short name T387
Test name
Test status
Simulation time 30894819578 ps
CPU time 4412.53 seconds
Started Jul 29 07:50:19 PM PDT 24
Finished Jul 29 09:03:52 PM PDT 24
Peak memory 593464 kb
Host smart-2fc02b2e-f42d-4dd3-a0ce-8335f8e065d1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653422229 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.1653422229
Directory /workspace/10.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.chip_tl_errors.4150648405
Short name T713
Test name
Test status
Simulation time 3014258450 ps
CPU time 167.47 seconds
Started Jul 29 07:50:21 PM PDT 24
Finished Jul 29 07:53:08 PM PDT 24
Peak memory 598852 kb
Host smart-147eb254-6005-49e3-89a5-82580295cd4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150648405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.4150648405
Directory /workspace/10.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_access_same_device.2530036368
Short name T2925
Test name
Test status
Simulation time 1597746527 ps
CPU time 71.23 seconds
Started Jul 29 07:50:27 PM PDT 24
Finished Jul 29 07:51:38 PM PDT 24
Peak memory 575784 kb
Host smart-371c02d1-a61e-4a92-b662-df396909b0f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530036368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device
.2530036368
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2882553680
Short name T2587
Test name
Test status
Simulation time 228254358 ps
CPU time 26.54 seconds
Started Jul 29 07:50:30 PM PDT 24
Finished Jul 29 07:50:57 PM PDT 24
Peak memory 575968 kb
Host smart-f9f08b7d-0649-4e7c-8855-652d33ac19b3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882553680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add
r.2882553680
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_error_random.135757270
Short name T1921
Test name
Test status
Simulation time 1818762045 ps
CPU time 55.6 seconds
Started Jul 29 07:50:21 PM PDT 24
Finished Jul 29 07:51:17 PM PDT 24
Peak memory 575756 kb
Host smart-f9555403-cf25-4a93-ba47-9eb2cafb9fde
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135757270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.135757270
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random.4282121088
Short name T616
Test name
Test status
Simulation time 2258063707 ps
CPU time 78.68 seconds
Started Jul 29 07:50:25 PM PDT 24
Finished Jul 29 07:51:44 PM PDT 24
Peak memory 575772 kb
Host smart-5dfd9c85-551f-481e-aa5e-b34cb8d6b685
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282121088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.4282121088
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1939999889
Short name T676
Test name
Test status
Simulation time 92519035882 ps
CPU time 1089.57 seconds
Started Jul 29 07:50:20 PM PDT 24
Finished Jul 29 08:08:30 PM PDT 24
Peak memory 576104 kb
Host smart-42861789-1fc3-4d5e-9f83-250e9cd166a2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939999889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1939999889
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2438892047
Short name T1651
Test name
Test status
Simulation time 31455363873 ps
CPU time 534.42 seconds
Started Jul 29 07:50:27 PM PDT 24
Finished Jul 29 07:59:21 PM PDT 24
Peak memory 575952 kb
Host smart-26998788-d1c0-445a-8568-700c05d841ff
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438892047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2438892047
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.531802544
Short name T510
Test name
Test status
Simulation time 175823384 ps
CPU time 15.22 seconds
Started Jul 29 07:50:29 PM PDT 24
Finished Jul 29 07:50:45 PM PDT 24
Peak memory 575848 kb
Host smart-fc50ac32-f0f2-4ebc-b266-cd6a53567014
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531802544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_dela
ys.531802544
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_same_source.3752337387
Short name T2932
Test name
Test status
Simulation time 842761591 ps
CPU time 24.98 seconds
Started Jul 29 07:50:18 PM PDT 24
Finished Jul 29 07:50:43 PM PDT 24
Peak memory 575820 kb
Host smart-b48f687f-b9eb-401e-b48b-5a9365c70b8a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752337387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3752337387
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke.2420373780
Short name T2777
Test name
Test status
Simulation time 149124924 ps
CPU time 7.62 seconds
Started Jul 29 07:50:20 PM PDT 24
Finished Jul 29 07:50:28 PM PDT 24
Peak memory 573832 kb
Host smart-4a8edae8-bbc6-4f8c-a987-7e2be76c725c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420373780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2420373780
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2603538870
Short name T1798
Test name
Test status
Simulation time 7206095046 ps
CPU time 74.76 seconds
Started Jul 29 07:50:22 PM PDT 24
Finished Jul 29 07:51:37 PM PDT 24
Peak memory 574652 kb
Host smart-2598bf9c-f1d9-4e2b-bcb1-5309e6675fbe
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603538870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2603538870
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3817136229
Short name T2594
Test name
Test status
Simulation time 4513633171 ps
CPU time 79.12 seconds
Started Jul 29 07:50:21 PM PDT 24
Finished Jul 29 07:51:40 PM PDT 24
Peak memory 573972 kb
Host smart-3074e190-09ab-4923-8cd1-2dcc58b23274
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817136229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3817136229
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3285374816
Short name T1880
Test name
Test status
Simulation time 56486707 ps
CPU time 6.38 seconds
Started Jul 29 07:50:20 PM PDT 24
Finished Jul 29 07:50:26 PM PDT 24
Peak memory 573896 kb
Host smart-79ecb72a-aba4-49e5-ba19-6f0dc955a8a6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285374816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay
s.3285374816
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all.3661413165
Short name T1877
Test name
Test status
Simulation time 7561679291 ps
CPU time 283.11 seconds
Started Jul 29 07:50:23 PM PDT 24
Finished Jul 29 07:55:07 PM PDT 24
Peak memory 576004 kb
Host smart-18b7d275-bc9e-4081-94d7-2e25c3751c54
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661413165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3661413165
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3317102764
Short name T872
Test name
Test status
Simulation time 2035523386 ps
CPU time 157.41 seconds
Started Jul 29 07:50:23 PM PDT 24
Finished Jul 29 07:53:00 PM PDT 24
Peak memory 576128 kb
Host smart-790408e2-01ce-4add-935a-81146988c341
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317102764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3317102764
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2292444182
Short name T1839
Test name
Test status
Simulation time 7065325010 ps
CPU time 500.55 seconds
Started Jul 29 07:50:30 PM PDT 24
Finished Jul 29 07:58:50 PM PDT 24
Peak memory 576800 kb
Host smart-bda33655-b417-45c6-bea6-4c006f3078be
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292444182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all
_with_rand_reset.2292444182
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2456011982
Short name T1655
Test name
Test status
Simulation time 317661975 ps
CPU time 127.13 seconds
Started Jul 29 07:50:41 PM PDT 24
Finished Jul 29 07:52:48 PM PDT 24
Peak memory 576796 kb
Host smart-58fafd24-93bf-4cd0-ab5f-e09fd7ad4684
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456011982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al
l_with_reset_error.2456011982
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1387409054
Short name T486
Test name
Test status
Simulation time 1205513952 ps
CPU time 49.91 seconds
Started Jul 29 07:50:30 PM PDT 24
Finished Jul 29 07:51:20 PM PDT 24
Peak memory 575988 kb
Host smart-9fa9c5ae-9a05-44e9-9eb9-e0f654557c2d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387409054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1387409054
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2804769949
Short name T2935
Test name
Test status
Simulation time 6931873022 ps
CPU time 494.32 seconds
Started Jul 29 07:50:32 PM PDT 24
Finished Jul 29 07:58:46 PM PDT 24
Peak memory 638640 kb
Host smart-094d4103-a482-4819-9278-d0bd5ff9ae11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804769949 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.2804769949
Directory /workspace/11.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.chip_csr_rw.4007762977
Short name T2386
Test name
Test status
Simulation time 4155130536 ps
CPU time 249.08 seconds
Started Jul 29 07:50:31 PM PDT 24
Finished Jul 29 07:54:40 PM PDT 24
Peak memory 597284 kb
Host smart-2c4fb01e-1061-40d6-9300-94399d7f8f7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007762977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.4007762977
Directory /workspace/11.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.chip_tl_errors.2624357233
Short name T2551
Test name
Test status
Simulation time 3588984746 ps
CPU time 252.78 seconds
Started Jul 29 07:50:19 PM PDT 24
Finished Jul 29 07:54:32 PM PDT 24
Peak memory 599660 kb
Host smart-0319c152-e0d3-4454-9e1c-81575c361ff8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624357233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.2624357233
Directory /workspace/11.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_access_same_device.2361488552
Short name T1741
Test name
Test status
Simulation time 1270862412 ps
CPU time 52.43 seconds
Started Jul 29 07:50:20 PM PDT 24
Finished Jul 29 07:51:12 PM PDT 24
Peak memory 575984 kb
Host smart-b824e374-9e48-437f-aa23-c3bc5e62cda2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361488552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device
.2361488552
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2950783219
Short name T863
Test name
Test status
Simulation time 91441793598 ps
CPU time 1564.99 seconds
Started Jul 29 07:50:21 PM PDT 24
Finished Jul 29 08:16:27 PM PDT 24
Peak memory 575872 kb
Host smart-a4a147b3-baa1-4bc9-b51b-b0b99dec4364
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950783219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_
device_slow_rsp.2950783219
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3166105879
Short name T2052
Test name
Test status
Simulation time 292549058 ps
CPU time 27.58 seconds
Started Jul 29 07:50:25 PM PDT 24
Finished Jul 29 07:50:53 PM PDT 24
Peak memory 575696 kb
Host smart-20527e05-c336-4940-bc8f-39d6063b9939
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166105879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add
r.3166105879
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_error_random.1126499669
Short name T2007
Test name
Test status
Simulation time 2332594325 ps
CPU time 73.67 seconds
Started Jul 29 07:50:24 PM PDT 24
Finished Jul 29 07:51:38 PM PDT 24
Peak memory 576040 kb
Host smart-548a2549-a6f9-4c1b-9670-6417a441c418
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126499669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1126499669
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random.3865139004
Short name T1893
Test name
Test status
Simulation time 444843963 ps
CPU time 18.21 seconds
Started Jul 29 07:50:40 PM PDT 24
Finished Jul 29 07:50:59 PM PDT 24
Peak memory 575824 kb
Host smart-f9cf6600-619c-4119-9b55-e56053c675c7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865139004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.3865139004
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1280041266
Short name T2839
Test name
Test status
Simulation time 96354326407 ps
CPU time 933.41 seconds
Started Jul 29 07:50:41 PM PDT 24
Finished Jul 29 08:06:14 PM PDT 24
Peak memory 576016 kb
Host smart-50260954-a01f-4317-8b09-6717d35c5dfc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280041266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1280041266
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3022017642
Short name T2603
Test name
Test status
Simulation time 53695301717 ps
CPU time 893.27 seconds
Started Jul 29 07:50:18 PM PDT 24
Finished Jul 29 08:05:12 PM PDT 24
Peak memory 576108 kb
Host smart-3d824958-951a-4405-8cf0-f5512a44b05d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022017642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3022017642
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.12249193
Short name T531
Test name
Test status
Simulation time 486238301 ps
CPU time 43.94 seconds
Started Jul 29 07:50:30 PM PDT 24
Finished Jul 29 07:51:14 PM PDT 24
Peak memory 575840 kb
Host smart-aa5895d3-8a56-42c3-81c8-a763d8fb64a8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12249193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delay
s.12249193
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_same_source.1727461904
Short name T2652
Test name
Test status
Simulation time 2744030052 ps
CPU time 80.8 seconds
Started Jul 29 07:50:21 PM PDT 24
Finished Jul 29 07:51:42 PM PDT 24
Peak memory 575984 kb
Host smart-1c518e15-1f7b-4d28-b88c-0d184a45fc02
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727461904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1727461904
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke.934043991
Short name T1984
Test name
Test status
Simulation time 201628917 ps
CPU time 8.81 seconds
Started Jul 29 07:50:26 PM PDT 24
Finished Jul 29 07:50:35 PM PDT 24
Peak memory 574532 kb
Host smart-df006210-3ab5-40be-a101-a8180f9dd9a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934043991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.934043991
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.3758978599
Short name T1833
Test name
Test status
Simulation time 9367855044 ps
CPU time 97.58 seconds
Started Jul 29 07:50:25 PM PDT 24
Finished Jul 29 07:52:03 PM PDT 24
Peak memory 573864 kb
Host smart-37ae58bc-0f26-44d6-a05a-e3ffa719c1fc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758978599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3758978599
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3121932246
Short name T2272
Test name
Test status
Simulation time 5807479693 ps
CPU time 102.11 seconds
Started Jul 29 07:50:40 PM PDT 24
Finished Jul 29 07:52:22 PM PDT 24
Peak memory 573940 kb
Host smart-e0fe1a3d-09c6-422c-8847-8816cdc9548a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121932246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3121932246
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2676522450
Short name T1633
Test name
Test status
Simulation time 45642537 ps
CPU time 5.83 seconds
Started Jul 29 07:50:23 PM PDT 24
Finished Jul 29 07:50:29 PM PDT 24
Peak memory 573880 kb
Host smart-a574697a-1f68-434b-9fb5-1bd38969e55e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676522450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay
s.2676522450
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all.4229944881
Short name T489
Test name
Test status
Simulation time 2929011209 ps
CPU time 270.06 seconds
Started Jul 29 07:50:20 PM PDT 24
Finished Jul 29 07:54:50 PM PDT 24
Peak memory 576872 kb
Host smart-4809dc2e-d5ba-4591-a607-b6fa2c37f250
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229944881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.4229944881
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2728805472
Short name T2887
Test name
Test status
Simulation time 2738602275 ps
CPU time 106.02 seconds
Started Jul 29 07:50:31 PM PDT 24
Finished Jul 29 07:52:17 PM PDT 24
Peak memory 575856 kb
Host smart-43d3f787-1446-4275-bc1a-838804a9feba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728805472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2728805472
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3630299360
Short name T1985
Test name
Test status
Simulation time 3901617581 ps
CPU time 239.43 seconds
Started Jul 29 07:50:26 PM PDT 24
Finished Jul 29 07:54:26 PM PDT 24
Peak memory 576816 kb
Host smart-5b8053af-dd26-4b78-a910-5319e8e5cfed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630299360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all
_with_rand_reset.3630299360
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2097657238
Short name T2109
Test name
Test status
Simulation time 260808267 ps
CPU time 93.47 seconds
Started Jul 29 07:50:46 PM PDT 24
Finished Jul 29 07:52:19 PM PDT 24
Peak memory 576780 kb
Host smart-e0ee439e-2f73-4e7d-93b7-8a06f55b8791
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097657238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al
l_with_reset_error.2097657238
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3178845668
Short name T2289
Test name
Test status
Simulation time 272388948 ps
CPU time 36.32 seconds
Started Jul 29 07:50:22 PM PDT 24
Finished Jul 29 07:50:59 PM PDT 24
Peak memory 575988 kb
Host smart-247c0049-ed91-4bb2-97d6-7f5e5ff68cbe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178845668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3178845668
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3991840210
Short name T1883
Test name
Test status
Simulation time 9398912640 ps
CPU time 765.77 seconds
Started Jul 29 07:50:48 PM PDT 24
Finished Jul 29 08:03:34 PM PDT 24
Peak memory 652348 kb
Host smart-cce0b4da-6019-4887-8bdd-0555ac7263f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991840210 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.3991840210
Directory /workspace/12.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.chip_csr_rw.347486060
Short name T2390
Test name
Test status
Simulation time 5310241284 ps
CPU time 535.52 seconds
Started Jul 29 07:50:45 PM PDT 24
Finished Jul 29 07:59:41 PM PDT 24
Peak memory 599548 kb
Host smart-2fbbce7a-a43c-4ded-8ab1-d228dd1c104d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347486060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.347486060
Directory /workspace/12.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3336502502
Short name T2847
Test name
Test status
Simulation time 29620886892 ps
CPU time 3763.99 seconds
Started Jul 29 07:50:46 PM PDT 24
Finished Jul 29 08:53:30 PM PDT 24
Peak memory 593356 kb
Host smart-eed660f6-3007-4629-85a7-dddc1231dfd8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336502502 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.3336502502
Directory /workspace/12.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.chip_tl_errors.3283958611
Short name T2902
Test name
Test status
Simulation time 3811203436 ps
CPU time 334.81 seconds
Started Jul 29 07:50:46 PM PDT 24
Finished Jul 29 07:56:20 PM PDT 24
Peak memory 603804 kb
Host smart-484ec98d-5af6-4f22-80ec-8d64adb19079
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283958611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.3283958611
Directory /workspace/12.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_access_same_device.30273757
Short name T1791
Test name
Test status
Simulation time 1349678951 ps
CPU time 65.21 seconds
Started Jul 29 07:50:30 PM PDT 24
Finished Jul 29 07:51:35 PM PDT 24
Peak memory 576080 kb
Host smart-350d580f-3ed4-4c90-af9c-d1d18d9fdf0c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30273757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.30273757
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2432070679
Short name T1558
Test name
Test status
Simulation time 3185535609 ps
CPU time 60.73 seconds
Started Jul 29 07:50:32 PM PDT 24
Finished Jul 29 07:51:33 PM PDT 24
Peak memory 573884 kb
Host smart-b9d5da02-25ad-4321-9d50-6bdf1749dde2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432070679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_
device_slow_rsp.2432070679
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.602099826
Short name T2934
Test name
Test status
Simulation time 289851056 ps
CPU time 12.68 seconds
Started Jul 29 07:50:45 PM PDT 24
Finished Jul 29 07:50:58 PM PDT 24
Peak memory 575984 kb
Host smart-70c926fb-ed8e-43b6-8803-aab24e020a26
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602099826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr
.602099826
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_error_random.3416457301
Short name T1924
Test name
Test status
Simulation time 2150249771 ps
CPU time 71.43 seconds
Started Jul 29 07:50:32 PM PDT 24
Finished Jul 29 07:51:44 PM PDT 24
Peak memory 575832 kb
Host smart-52e0e131-f712-429c-ada1-693215d72ec3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416457301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3416457301
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random.177674811
Short name T2546
Test name
Test status
Simulation time 474152898 ps
CPU time 36.32 seconds
Started Jul 29 07:50:29 PM PDT 24
Finished Jul 29 07:51:06 PM PDT 24
Peak memory 576028 kb
Host smart-1b4f151e-604b-47c9-91c8-4fc63cb53ef1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177674811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.177674811
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3701206688
Short name T2845
Test name
Test status
Simulation time 50406023421 ps
CPU time 532.69 seconds
Started Jul 29 07:50:41 PM PDT 24
Finished Jul 29 07:59:34 PM PDT 24
Peak memory 576064 kb
Host smart-58fa4a4d-65af-4b2b-a74a-e28043270648
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701206688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3701206688
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1500948400
Short name T2462
Test name
Test status
Simulation time 53171905950 ps
CPU time 907.4 seconds
Started Jul 29 07:50:46 PM PDT 24
Finished Jul 29 08:05:53 PM PDT 24
Peak memory 575908 kb
Host smart-d218dc2c-a7fc-4d15-8a94-87776609650e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500948400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.1500948400
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1964513996
Short name T645
Test name
Test status
Simulation time 321655321 ps
CPU time 31.56 seconds
Started Jul 29 07:50:29 PM PDT 24
Finished Jul 29 07:51:01 PM PDT 24
Peak memory 575816 kb
Host smart-688ce847-0604-4eea-a41a-cb6a518fb399
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964513996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del
ays.1964513996
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_same_source.4247206171
Short name T2819
Test name
Test status
Simulation time 261914788 ps
CPU time 20.14 seconds
Started Jul 29 07:50:41 PM PDT 24
Finished Jul 29 07:51:01 PM PDT 24
Peak memory 575804 kb
Host smart-0487c399-f482-49ba-a05a-57fe5898bff6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247206171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.4247206171
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke.753405625
Short name T2500
Test name
Test status
Simulation time 220640837 ps
CPU time 8.98 seconds
Started Jul 29 07:50:41 PM PDT 24
Finished Jul 29 07:50:50 PM PDT 24
Peak memory 573896 kb
Host smart-679b6671-8424-4fc2-ad28-c6377aad1a0c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753405625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.753405625
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3624281354
Short name T2219
Test name
Test status
Simulation time 9055056165 ps
CPU time 95.93 seconds
Started Jul 29 07:50:30 PM PDT 24
Finished Jul 29 07:52:06 PM PDT 24
Peak memory 574632 kb
Host smart-f164d105-d063-4d43-b84d-c8baf8cfecd8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624281354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3624281354
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.426761123
Short name T1761
Test name
Test status
Simulation time 3702832998 ps
CPU time 58.53 seconds
Started Jul 29 07:50:46 PM PDT 24
Finished Jul 29 07:51:45 PM PDT 24
Peak memory 573876 kb
Host smart-0e199aa0-c2b6-444a-8084-b238e142ad56
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426761123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.426761123
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3705481339
Short name T2619
Test name
Test status
Simulation time 59193430 ps
CPU time 6.53 seconds
Started Jul 29 07:50:33 PM PDT 24
Finished Jul 29 07:50:39 PM PDT 24
Peak memory 573868 kb
Host smart-8edf6cc2-b5a7-4c36-8f7a-04fb7b4162e2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705481339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay
s.3705481339
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all.124489795
Short name T441
Test name
Test status
Simulation time 3332004167 ps
CPU time 294.48 seconds
Started Jul 29 07:50:30 PM PDT 24
Finished Jul 29 07:55:24 PM PDT 24
Peak memory 576088 kb
Host smart-151e1f36-894b-407e-a394-8187ce3de8e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124489795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.124489795
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.529306065
Short name T1584
Test name
Test status
Simulation time 7676414997 ps
CPU time 259.63 seconds
Started Jul 29 07:50:45 PM PDT 24
Finished Jul 29 07:55:04 PM PDT 24
Peak memory 576004 kb
Host smart-a730f11b-af9b-48fd-a8c3-9f8aca715abb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529306065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.529306065
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3439813461
Short name T475
Test name
Test status
Simulation time 358327047 ps
CPU time 213.79 seconds
Started Jul 29 07:50:31 PM PDT 24
Finished Jul 29 07:54:04 PM PDT 24
Peak memory 576708 kb
Host smart-ab1d97a5-fe1b-4717-ad96-446b7a8aa2cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439813461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all
_with_rand_reset.3439813461
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3876805755
Short name T2910
Test name
Test status
Simulation time 9730838285 ps
CPU time 450.74 seconds
Started Jul 29 07:50:48 PM PDT 24
Finished Jul 29 07:58:19 PM PDT 24
Peak memory 576872 kb
Host smart-c8dec6ac-4f6f-48ca-b180-5ab174ad28cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876805755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al
l_with_reset_error.3876805755
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1484285730
Short name T2560
Test name
Test status
Simulation time 134633265 ps
CPU time 8.85 seconds
Started Jul 29 07:50:31 PM PDT 24
Finished Jul 29 07:50:40 PM PDT 24
Peak memory 574012 kb
Host smart-50497dc9-b5e9-4437-9872-ba406a7e33f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484285730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1484285730
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3772185707
Short name T1563
Test name
Test status
Simulation time 10461259725 ps
CPU time 789.53 seconds
Started Jul 29 07:51:34 PM PDT 24
Finished Jul 29 08:04:44 PM PDT 24
Peak memory 652292 kb
Host smart-59e714df-b028-4b2d-ba2c-e76883acac1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772185707 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.3772185707
Directory /workspace/13.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.chip_csr_rw.414874771
Short name T398
Test name
Test status
Simulation time 4379205912 ps
CPU time 320.17 seconds
Started Jul 29 07:51:32 PM PDT 24
Finished Jul 29 07:56:52 PM PDT 24
Peak memory 598972 kb
Host smart-44589cd4-2b03-4cd7-b14e-e2abee24e365
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414874771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.414874771
Directory /workspace/13.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.197276592
Short name T1717
Test name
Test status
Simulation time 27835465999 ps
CPU time 3707.82 seconds
Started Jul 29 07:50:44 PM PDT 24
Finished Jul 29 08:52:33 PM PDT 24
Peak memory 593376 kb
Host smart-ad3f71fe-fbfb-49e9-801f-0e094e957812
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197276592 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.chip_same_csr_outstanding.197276592
Directory /workspace/13.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_access_same_device.1815578513
Short name T2210
Test name
Test status
Simulation time 2636740239 ps
CPU time 112.09 seconds
Started Jul 29 07:51:32 PM PDT 24
Finished Jul 29 07:53:25 PM PDT 24
Peak memory 575960 kb
Host smart-d5d88880-492d-4227-9882-fe3efc334694
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815578513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device
.1815578513
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3990717150
Short name T2469
Test name
Test status
Simulation time 180435569 ps
CPU time 9.95 seconds
Started Jul 29 07:51:33 PM PDT 24
Finished Jul 29 07:51:43 PM PDT 24
Peak memory 573900 kb
Host smart-e1eaca6e-ae28-4f80-9624-e7390f48c915
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990717150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add
r.3990717150
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_error_random.857155450
Short name T1590
Test name
Test status
Simulation time 2483307463 ps
CPU time 79.18 seconds
Started Jul 29 07:51:30 PM PDT 24
Finished Jul 29 07:52:49 PM PDT 24
Peak memory 576032 kb
Host smart-cb8bbdb6-b9e4-43f7-90c0-7ba38837e231
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857155450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.857155450
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random.1111700124
Short name T2059
Test name
Test status
Simulation time 144814666 ps
CPU time 15.06 seconds
Started Jul 29 07:51:31 PM PDT 24
Finished Jul 29 07:51:46 PM PDT 24
Peak memory 575872 kb
Host smart-7266fe86-5246-4a32-9d5d-f58f6c384253
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111700124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.1111700124
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.837188060
Short name T2389
Test name
Test status
Simulation time 13636619776 ps
CPU time 146.04 seconds
Started Jul 29 07:51:31 PM PDT 24
Finished Jul 29 07:53:57 PM PDT 24
Peak memory 575908 kb
Host smart-5c714ba2-8eaf-4a68-a78a-b5124dd34c86
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837188060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.837188060
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1113761760
Short name T1597
Test name
Test status
Simulation time 62906078656 ps
CPU time 1046.33 seconds
Started Jul 29 07:51:32 PM PDT 24
Finished Jul 29 08:08:58 PM PDT 24
Peak memory 576084 kb
Host smart-40940bc9-be66-4df4-9e35-3e2471b1566e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113761760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1113761760
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.518384687
Short name T2409
Test name
Test status
Simulation time 366599697 ps
CPU time 34.43 seconds
Started Jul 29 07:51:31 PM PDT 24
Finished Jul 29 07:52:06 PM PDT 24
Peak memory 575816 kb
Host smart-f537c285-96c6-4c42-bf7f-a75aaa99c01d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518384687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_dela
ys.518384687
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_same_source.2606188381
Short name T1569
Test name
Test status
Simulation time 1706920207 ps
CPU time 49.17 seconds
Started Jul 29 07:51:35 PM PDT 24
Finished Jul 29 07:52:24 PM PDT 24
Peak memory 575808 kb
Host smart-d355915d-a314-40e1-b6da-8cfe3ca55aa9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606188381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2606188381
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke.2277142160
Short name T1725
Test name
Test status
Simulation time 136175937 ps
CPU time 7.3 seconds
Started Jul 29 07:51:13 PM PDT 24
Finished Jul 29 07:51:20 PM PDT 24
Peak memory 573804 kb
Host smart-dec0631e-0632-46f6-ba61-6d8d554fe2e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277142160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2277142160
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2236607698
Short name T1956
Test name
Test status
Simulation time 10315990965 ps
CPU time 110.36 seconds
Started Jul 29 07:51:17 PM PDT 24
Finished Jul 29 07:53:08 PM PDT 24
Peak memory 574000 kb
Host smart-2c111dfa-e032-4124-b0e6-ea21b6dd937d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236607698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2236607698
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3497406636
Short name T1836
Test name
Test status
Simulation time 5544442881 ps
CPU time 96.78 seconds
Started Jul 29 07:51:13 PM PDT 24
Finished Jul 29 07:52:50 PM PDT 24
Peak memory 573964 kb
Host smart-cdb2ede6-2f98-46ce-8de8-0757a496c415
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497406636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3497406636
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2765230869
Short name T2535
Test name
Test status
Simulation time 39656391 ps
CPU time 6.09 seconds
Started Jul 29 07:51:14 PM PDT 24
Finished Jul 29 07:51:20 PM PDT 24
Peak memory 573888 kb
Host smart-d4b7ca87-a9a2-44f8-a191-67ab26d3064f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765230869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay
s.2765230869
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all.2668468880
Short name T1518
Test name
Test status
Simulation time 505053262 ps
CPU time 46.04 seconds
Started Jul 29 07:51:35 PM PDT 24
Finished Jul 29 07:52:21 PM PDT 24
Peak memory 576028 kb
Host smart-ba965ba5-b713-4f1f-b99d-5dcfa8ad58aa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668468880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2668468880
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2571936315
Short name T2242
Test name
Test status
Simulation time 7684440481 ps
CPU time 418.34 seconds
Started Jul 29 07:51:35 PM PDT 24
Finished Jul 29 07:58:34 PM PDT 24
Peak memory 576804 kb
Host smart-ab3f512a-e0e8-45bf-a033-c50bdc0cd9ef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571936315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all
_with_rand_reset.2571936315
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.607508181
Short name T865
Test name
Test status
Simulation time 218811344 ps
CPU time 69.65 seconds
Started Jul 29 07:51:30 PM PDT 24
Finished Jul 29 07:52:40 PM PDT 24
Peak memory 575956 kb
Host smart-cc8f0b34-2cd4-4b9e-937f-361e17248b95
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607508181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all
_with_reset_error.607508181
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2574892373
Short name T2503
Test name
Test status
Simulation time 647580482 ps
CPU time 28.93 seconds
Started Jul 29 07:51:32 PM PDT 24
Finished Jul 29 07:52:01 PM PDT 24
Peak memory 575984 kb
Host smart-e99b3e3e-4ec9-4329-8baa-3687e607816d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574892373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2574892373
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2312655361
Short name T2105
Test name
Test status
Simulation time 9573223740 ps
CPU time 794.46 seconds
Started Jul 29 07:51:46 PM PDT 24
Finished Jul 29 08:05:00 PM PDT 24
Peak memory 652868 kb
Host smart-109e2fba-b1d9-4dd2-b38c-55cf8f60961b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312655361 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.2312655361
Directory /workspace/14.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.chip_csr_rw.2367216914
Short name T716
Test name
Test status
Simulation time 4430848731 ps
CPU time 322.91 seconds
Started Jul 29 07:51:53 PM PDT 24
Finished Jul 29 07:57:16 PM PDT 24
Peak memory 598680 kb
Host smart-f3bc69c8-31b5-4563-849a-ff3f385b07b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367216914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.2367216914
Directory /workspace/14.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.1885692887
Short name T2320
Test name
Test status
Simulation time 15060712379 ps
CPU time 1627.77 seconds
Started Jul 29 07:51:30 PM PDT 24
Finished Jul 29 08:18:38 PM PDT 24
Peak memory 593352 kb
Host smart-4893585b-901c-4be4-ac23-6aef9e7e91f4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885692887 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.1885692887
Directory /workspace/14.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_access_same_device.3034600188
Short name T2153
Test name
Test status
Simulation time 1731928788 ps
CPU time 77.21 seconds
Started Jul 29 07:51:45 PM PDT 24
Finished Jul 29 07:53:03 PM PDT 24
Peak memory 576028 kb
Host smart-f5afc2d1-d10c-419d-b118-59e4298627a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034600188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device
.3034600188
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.508922837
Short name T1910
Test name
Test status
Simulation time 21242615063 ps
CPU time 370.54 seconds
Started Jul 29 07:51:47 PM PDT 24
Finished Jul 29 07:57:57 PM PDT 24
Peak memory 576104 kb
Host smart-9d4f247a-0472-4eae-87f4-8fcee13588f9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508922837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_d
evice_slow_rsp.508922837
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.472068508
Short name T1598
Test name
Test status
Simulation time 1315783905 ps
CPU time 53.27 seconds
Started Jul 29 07:51:45 PM PDT 24
Finished Jul 29 07:52:38 PM PDT 24
Peak memory 576028 kb
Host smart-e3d7c499-7db7-4cd2-a91b-51ab6ad44928
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472068508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr
.472068508
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_error_random.4118552960
Short name T2715
Test name
Test status
Simulation time 664318509 ps
CPU time 23.27 seconds
Started Jul 29 07:51:47 PM PDT 24
Finished Jul 29 07:52:11 PM PDT 24
Peak memory 575980 kb
Host smart-efbfd716-1165-4004-96c5-5f69afe22d1d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118552960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.4118552960
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random.1754761434
Short name T2486
Test name
Test status
Simulation time 372547247 ps
CPU time 33.35 seconds
Started Jul 29 07:51:30 PM PDT 24
Finished Jul 29 07:52:04 PM PDT 24
Peak memory 575836 kb
Host smart-1d59e201-dbdf-4868-9ed1-3ec6252673b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754761434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.1754761434
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2507577128
Short name T1923
Test name
Test status
Simulation time 42201161913 ps
CPU time 418.72 seconds
Started Jul 29 07:51:35 PM PDT 24
Finished Jul 29 07:58:34 PM PDT 24
Peak memory 575968 kb
Host smart-e0ebaebe-9bbf-4035-b24e-501ea037503f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507577128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2507577128
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.900839236
Short name T2065
Test name
Test status
Simulation time 12345014601 ps
CPU time 194.55 seconds
Started Jul 29 07:51:30 PM PDT 24
Finished Jul 29 07:54:45 PM PDT 24
Peak memory 576024 kb
Host smart-480482ea-ee2d-42e9-b3de-cdb6e40bbf7d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900839236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.900839236
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3322111579
Short name T1827
Test name
Test status
Simulation time 594240234 ps
CPU time 57.47 seconds
Started Jul 29 07:51:30 PM PDT 24
Finished Jul 29 07:52:28 PM PDT 24
Peak memory 575888 kb
Host smart-acc490e6-9538-4e4f-be1c-01a503ed39d1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322111579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del
ays.3322111579
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_same_source.1014743840
Short name T2737
Test name
Test status
Simulation time 593723581 ps
CPU time 36.77 seconds
Started Jul 29 07:51:43 PM PDT 24
Finished Jul 29 07:52:19 PM PDT 24
Peak memory 575820 kb
Host smart-5e920e92-e40c-4e32-a0e9-0f26a3b8696d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014743840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1014743840
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke.2202417478
Short name T1940
Test name
Test status
Simulation time 45859539 ps
CPU time 6 seconds
Started Jul 29 07:51:32 PM PDT 24
Finished Jul 29 07:51:39 PM PDT 24
Peak memory 573924 kb
Host smart-70a6defa-19e3-449f-a7a7-c1e7420fd071
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202417478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2202417478
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.2283651583
Short name T2467
Test name
Test status
Simulation time 10474654278 ps
CPU time 110.26 seconds
Started Jul 29 07:51:30 PM PDT 24
Finished Jul 29 07:53:20 PM PDT 24
Peak memory 574644 kb
Host smart-d9258a98-0921-4f2b-b0c1-37379f574542
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283651583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2283651583
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.3212884869
Short name T2686
Test name
Test status
Simulation time 6209657395 ps
CPU time 100.07 seconds
Started Jul 29 07:51:31 PM PDT 24
Finished Jul 29 07:53:11 PM PDT 24
Peak memory 573960 kb
Host smart-3cae05e5-d0cc-45bb-a268-f53a7babc01d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212884869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.3212884869
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.692198921
Short name T1467
Test name
Test status
Simulation time 36090948 ps
CPU time 5.5 seconds
Started Jul 29 07:51:30 PM PDT 24
Finished Jul 29 07:51:36 PM PDT 24
Peak memory 573864 kb
Host smart-d81333a1-2814-45dc-ab86-33925889d833
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692198921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays
.692198921
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all.2867369882
Short name T2288
Test name
Test status
Simulation time 2353924194 ps
CPU time 69.98 seconds
Started Jul 29 07:51:50 PM PDT 24
Finished Jul 29 07:53:00 PM PDT 24
Peak memory 575980 kb
Host smart-04da280c-59cd-42da-810d-cef7da54ecbc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867369882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2867369882
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.848677679
Short name T2392
Test name
Test status
Simulation time 5092150477 ps
CPU time 187.02 seconds
Started Jul 29 07:51:46 PM PDT 24
Finished Jul 29 07:54:53 PM PDT 24
Peak memory 576636 kb
Host smart-34ba5ab4-f6f6-47d5-9712-c6cf6e501c58
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848677679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.848677679
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3254745871
Short name T1790
Test name
Test status
Simulation time 103238665 ps
CPU time 63 seconds
Started Jul 29 07:51:46 PM PDT 24
Finished Jul 29 07:52:49 PM PDT 24
Peak memory 576752 kb
Host smart-fb4f6601-d10c-4d60-b929-91955b3e4675
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254745871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all
_with_rand_reset.3254745871
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1803129315
Short name T871
Test name
Test status
Simulation time 8829335556 ps
CPU time 837.42 seconds
Started Jul 29 07:51:44 PM PDT 24
Finished Jul 29 08:05:42 PM PDT 24
Peak memory 582964 kb
Host smart-14f730f1-5bd3-4a8a-ac03-62f70f2f22e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803129315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al
l_with_reset_error.1803129315
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.2623099403
Short name T477
Test name
Test status
Simulation time 198349524 ps
CPU time 10.51 seconds
Started Jul 29 07:51:45 PM PDT 24
Finished Jul 29 07:51:56 PM PDT 24
Peak memory 576052 kb
Host smart-620c71d1-2029-4acc-99f1-fc6f5418cede
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623099403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2623099403
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.2472434720
Short name T1895
Test name
Test status
Simulation time 10515055235 ps
CPU time 807.58 seconds
Started Jul 29 07:52:02 PM PDT 24
Finished Jul 29 08:05:29 PM PDT 24
Peak memory 649996 kb
Host smart-2493b279-f748-48f9-a3b9-6681d198986e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472434720 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.2472434720
Directory /workspace/15.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.chip_csr_rw.3557163545
Short name T417
Test name
Test status
Simulation time 5921591282 ps
CPU time 499.01 seconds
Started Jul 29 07:51:43 PM PDT 24
Finished Jul 29 08:00:03 PM PDT 24
Peak memory 599220 kb
Host smart-e994af6c-1d1e-4906-8ac1-a79a21c42889
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557163545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.3557163545
Directory /workspace/15.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3814675956
Short name T2215
Test name
Test status
Simulation time 15934859552 ps
CPU time 2187.68 seconds
Started Jul 29 07:51:45 PM PDT 24
Finished Jul 29 08:28:13 PM PDT 24
Peak memory 593244 kb
Host smart-f5f05eec-1c01-4238-9008-3419ffbf7010
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814675956 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.3814675956
Directory /workspace/15.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_access_same_device.1229993415
Short name T2917
Test name
Test status
Simulation time 2029750285 ps
CPU time 85.37 seconds
Started Jul 29 07:51:44 PM PDT 24
Finished Jul 29 07:53:10 PM PDT 24
Peak memory 575916 kb
Host smart-699a38d2-0a63-4a36-83b4-f2a056336083
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229993415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device
.1229993415
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.45225824
Short name T858
Test name
Test status
Simulation time 64743277315 ps
CPU time 1091.75 seconds
Started Jul 29 07:51:46 PM PDT 24
Finished Jul 29 08:09:58 PM PDT 24
Peak memory 576116 kb
Host smart-56e81966-50f5-4a6b-aece-df25086a8743
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45225824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_de
vice_slow_rsp.45225824
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.4158768734
Short name T2028
Test name
Test status
Simulation time 268887810 ps
CPU time 31.03 seconds
Started Jul 29 07:51:44 PM PDT 24
Finished Jul 29 07:52:15 PM PDT 24
Peak memory 575812 kb
Host smart-858d41e2-00ed-4af9-9626-e223edd0941a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158768734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add
r.4158768734
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_error_random.1429359574
Short name T2276
Test name
Test status
Simulation time 1265566930 ps
CPU time 41.05 seconds
Started Jul 29 07:51:52 PM PDT 24
Finished Jul 29 07:52:33 PM PDT 24
Peak memory 575748 kb
Host smart-ecce66d6-a1a4-4d36-8afa-2de1d8636119
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429359574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1429359574
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random.457054205
Short name T1615
Test name
Test status
Simulation time 1772137309 ps
CPU time 67.85 seconds
Started Jul 29 07:51:52 PM PDT 24
Finished Jul 29 07:52:59 PM PDT 24
Peak memory 575892 kb
Host smart-fc7c94b8-7708-4c05-8d76-8e998401124e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457054205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.457054205
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.935764933
Short name T641
Test name
Test status
Simulation time 26353589057 ps
CPU time 267.86 seconds
Started Jul 29 07:51:47 PM PDT 24
Finished Jul 29 07:56:15 PM PDT 24
Peak memory 576028 kb
Host smart-53a61a0a-a42b-4137-b534-996aa57a8555
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935764933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.935764933
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.3253310150
Short name T2246
Test name
Test status
Simulation time 28553845727 ps
CPU time 458.3 seconds
Started Jul 29 07:51:48 PM PDT 24
Finished Jul 29 07:59:26 PM PDT 24
Peak memory 576068 kb
Host smart-5b43800b-b05a-4da2-be51-e1fba97575cc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253310150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3253310150
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.893467507
Short name T2231
Test name
Test status
Simulation time 436064700 ps
CPU time 41.37 seconds
Started Jul 29 07:51:44 PM PDT 24
Finished Jul 29 07:52:25 PM PDT 24
Peak memory 575644 kb
Host smart-659c5822-6396-4228-90fe-5557a156c7bf
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893467507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_dela
ys.893467507
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_same_source.2904907495
Short name T2187
Test name
Test status
Simulation time 2028651182 ps
CPU time 58.55 seconds
Started Jul 29 07:51:43 PM PDT 24
Finished Jul 29 07:52:42 PM PDT 24
Peak memory 575816 kb
Host smart-82bbebe8-f84a-4b1b-b3d5-6527b85992ef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904907495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2904907495
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke.3401139854
Short name T1847
Test name
Test status
Simulation time 222146530 ps
CPU time 9.12 seconds
Started Jul 29 07:51:46 PM PDT 24
Finished Jul 29 07:51:56 PM PDT 24
Peak memory 573924 kb
Host smart-9c78ae80-8da2-4bc2-b11f-e73ef29a56b7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401139854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3401139854
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.3980562076
Short name T2634
Test name
Test status
Simulation time 8998512722 ps
CPU time 95.36 seconds
Started Jul 29 07:51:34 PM PDT 24
Finished Jul 29 07:53:09 PM PDT 24
Peak memory 573988 kb
Host smart-a74f55a3-b54d-4e19-985a-6f1c71c9cdf8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980562076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3980562076
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.915558606
Short name T2556
Test name
Test status
Simulation time 7314277314 ps
CPU time 120.8 seconds
Started Jul 29 07:51:47 PM PDT 24
Finished Jul 29 07:53:48 PM PDT 24
Peak memory 573924 kb
Host smart-afee8cb9-97f5-451e-a8c1-d66adf736835
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915558606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.915558606
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.3970027504
Short name T2221
Test name
Test status
Simulation time 43544208 ps
CPU time 6.27 seconds
Started Jul 29 07:51:52 PM PDT 24
Finished Jul 29 07:51:58 PM PDT 24
Peak memory 573796 kb
Host smart-1212df88-d601-423d-8bdd-4fb0918c133e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970027504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay
s.3970027504
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all.3780768886
Short name T480
Test name
Test status
Simulation time 9519428260 ps
CPU time 313.89 seconds
Started Jul 29 07:51:52 PM PDT 24
Finished Jul 29 07:57:06 PM PDT 24
Peak memory 576016 kb
Host smart-2ac70a28-e596-4c93-919b-3157de0943ef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780768886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3780768886
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.217447323
Short name T618
Test name
Test status
Simulation time 9738314164 ps
CPU time 343.54 seconds
Started Jul 29 07:51:51 PM PDT 24
Finished Jul 29 07:57:35 PM PDT 24
Peak memory 576208 kb
Host smart-1e999598-49b3-4cba-8ab5-1c2871a5472e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217447323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.217447323
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.325411835
Short name T1869
Test name
Test status
Simulation time 16313241 ps
CPU time 8.44 seconds
Started Jul 29 07:51:48 PM PDT 24
Finished Jul 29 07:51:56 PM PDT 24
Peak memory 575996 kb
Host smart-1cf38398-fb81-4424-bbf5-bd68e2db4c25
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325411835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_
with_rand_reset.325411835
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3014618336
Short name T1606
Test name
Test status
Simulation time 4041907848 ps
CPU time 336.67 seconds
Started Jul 29 07:51:47 PM PDT 24
Finished Jul 29 07:57:24 PM PDT 24
Peak memory 576800 kb
Host smart-8f228e73-3297-41f9-9c2f-a791f516e64e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014618336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al
l_with_reset_error.3014618336
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.3001381185
Short name T1508
Test name
Test status
Simulation time 63725137 ps
CPU time 6.01 seconds
Started Jul 29 07:51:45 PM PDT 24
Finished Jul 29 07:51:52 PM PDT 24
Peak memory 573912 kb
Host smart-3547c24b-5ec7-40de-9910-5256bf9f906e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001381185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3001381185
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.1225947330
Short name T1581
Test name
Test status
Simulation time 7036016240 ps
CPU time 485.56 seconds
Started Jul 29 07:52:00 PM PDT 24
Finished Jul 29 08:00:06 PM PDT 24
Peak memory 640732 kb
Host smart-3c4cb312-2612-44ec-8872-96126ec3e468
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225947330 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.1225947330
Directory /workspace/16.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.chip_csr_rw.1012337896
Short name T2621
Test name
Test status
Simulation time 5589509221 ps
CPU time 552.74 seconds
Started Jul 29 07:51:56 PM PDT 24
Finished Jul 29 08:01:09 PM PDT 24
Peak memory 598708 kb
Host smart-bd837afa-775b-45be-b341-5a41cfcd30df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012337896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.1012337896
Directory /workspace/16.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.4242248071
Short name T2904
Test name
Test status
Simulation time 16255968523 ps
CPU time 1897.67 seconds
Started Jul 29 07:52:01 PM PDT 24
Finished Jul 29 08:23:39 PM PDT 24
Peak memory 593216 kb
Host smart-ada6b838-d1bc-49e2-b448-1640b6b22364
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242248071 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.4242248071
Directory /workspace/16.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_access_same_device.2903666937
Short name T2166
Test name
Test status
Simulation time 1767608331 ps
CPU time 78.19 seconds
Started Jul 29 07:52:02 PM PDT 24
Finished Jul 29 07:53:20 PM PDT 24
Peak memory 575980 kb
Host smart-818f1c90-5fc6-4c67-bec2-57827af256e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903666937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device
.2903666937
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.297066339
Short name T2675
Test name
Test status
Simulation time 126541307062 ps
CPU time 2390.92 seconds
Started Jul 29 07:51:55 PM PDT 24
Finished Jul 29 08:31:46 PM PDT 24
Peak memory 576080 kb
Host smart-ac46f3e5-1d81-46a7-bd4a-014e25461d2a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297066339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_d
evice_slow_rsp.297066339
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.329236487
Short name T2408
Test name
Test status
Simulation time 515252181 ps
CPU time 20.79 seconds
Started Jul 29 07:52:01 PM PDT 24
Finished Jul 29 07:52:22 PM PDT 24
Peak memory 575992 kb
Host smart-4f589a8b-4cc2-438c-81a5-59cd619d85bb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329236487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr
.329236487
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_error_random.404118889
Short name T2400
Test name
Test status
Simulation time 427392824 ps
CPU time 32.05 seconds
Started Jul 29 07:51:59 PM PDT 24
Finished Jul 29 07:52:31 PM PDT 24
Peak memory 575944 kb
Host smart-33e7cb6b-54a0-4532-9f77-11779e82b245
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404118889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.404118889
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random.1962141514
Short name T2576
Test name
Test status
Simulation time 2036251689 ps
CPU time 69.07 seconds
Started Jul 29 07:52:01 PM PDT 24
Finished Jul 29 07:53:10 PM PDT 24
Peak memory 575996 kb
Host smart-2c8384f6-febe-443c-9509-4eab7924e3b7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962141514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.1962141514
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2731770842
Short name T1732
Test name
Test status
Simulation time 43817956092 ps
CPU time 474.21 seconds
Started Jul 29 07:51:59 PM PDT 24
Finished Jul 29 07:59:53 PM PDT 24
Peak memory 576068 kb
Host smart-b6d921a6-5d33-4f0c-a355-ba0e80626fdb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731770842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2731770842
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.4198894839
Short name T2714
Test name
Test status
Simulation time 30522503256 ps
CPU time 504.98 seconds
Started Jul 29 07:51:57 PM PDT 24
Finished Jul 29 08:00:22 PM PDT 24
Peak memory 576088 kb
Host smart-3ad59e8c-4601-487a-ae8f-9946193c3b82
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198894839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.4198894839
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.2583219677
Short name T593
Test name
Test status
Simulation time 503535118 ps
CPU time 47.15 seconds
Started Jul 29 07:51:59 PM PDT 24
Finished Jul 29 07:52:47 PM PDT 24
Peak memory 575796 kb
Host smart-eaed22f8-2e1b-4c42-8b81-3a8440259bc8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583219677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del
ays.2583219677
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_same_source.2658703742
Short name T2564
Test name
Test status
Simulation time 445411227 ps
CPU time 15.03 seconds
Started Jul 29 07:51:55 PM PDT 24
Finished Jul 29 07:52:10 PM PDT 24
Peak memory 575872 kb
Host smart-fab6b9f4-04bc-4645-baa0-f49d8edff16b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658703742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2658703742
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke.1974600724
Short name T644
Test name
Test status
Simulation time 50145888 ps
CPU time 6.12 seconds
Started Jul 29 07:52:00 PM PDT 24
Finished Jul 29 07:52:07 PM PDT 24
Peak memory 574560 kb
Host smart-c1b4ef32-b9d2-46fa-955f-e086ae2cc440
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974600724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1974600724
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.1786665343
Short name T2406
Test name
Test status
Simulation time 7635213552 ps
CPU time 79.45 seconds
Started Jul 29 07:51:55 PM PDT 24
Finished Jul 29 07:53:15 PM PDT 24
Peak memory 573968 kb
Host smart-bb274a46-df1c-47f7-b329-675608d78239
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786665343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1786665343
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.4253830439
Short name T2720
Test name
Test status
Simulation time 4378229882 ps
CPU time 69.36 seconds
Started Jul 29 07:52:00 PM PDT 24
Finished Jul 29 07:53:10 PM PDT 24
Peak memory 573980 kb
Host smart-b793ff46-3169-4365-85d1-622efdf457cc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253830439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.4253830439
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2970271735
Short name T1965
Test name
Test status
Simulation time 37701852 ps
CPU time 5.99 seconds
Started Jul 29 07:51:59 PM PDT 24
Finished Jul 29 07:52:05 PM PDT 24
Peak memory 574008 kb
Host smart-0af6cb11-ceb9-4889-bc49-4272e2a6545c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970271735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay
s.2970271735
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all.2639571953
Short name T2271
Test name
Test status
Simulation time 5828435 ps
CPU time 3.89 seconds
Started Jul 29 07:51:54 PM PDT 24
Finished Jul 29 07:51:58 PM PDT 24
Peak memory 566184 kb
Host smart-9c860923-2ad8-4b19-84eb-a95fbb121439
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639571953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2639571953
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.2314205450
Short name T2420
Test name
Test status
Simulation time 14924822866 ps
CPU time 545.16 seconds
Started Jul 29 07:52:00 PM PDT 24
Finished Jul 29 08:01:05 PM PDT 24
Peak memory 576860 kb
Host smart-cf047fb5-1256-441b-82b8-61ad52a388fa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314205450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2314205450
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.916051286
Short name T895
Test name
Test status
Simulation time 152465597 ps
CPU time 49.45 seconds
Started Jul 29 07:51:55 PM PDT 24
Finished Jul 29 07:52:45 PM PDT 24
Peak memory 575912 kb
Host smart-1fafa180-bdbd-43c0-bb56-02cb711388d7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916051286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_
with_rand_reset.916051286
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.2091136310
Short name T1420
Test name
Test status
Simulation time 158522134 ps
CPU time 31.28 seconds
Started Jul 29 07:51:57 PM PDT 24
Finished Jul 29 07:52:28 PM PDT 24
Peak memory 575828 kb
Host smart-4440105d-dc57-46cd-8674-3f95dfa082c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091136310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al
l_with_reset_error.2091136310
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1894767684
Short name T1899
Test name
Test status
Simulation time 102520351 ps
CPU time 13.8 seconds
Started Jul 29 07:51:55 PM PDT 24
Finished Jul 29 07:52:09 PM PDT 24
Peak memory 575856 kb
Host smart-a4c53628-d4c1-4662-873f-e1c3e3aec779
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894767684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1894767684
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.2741215343
Short name T2370
Test name
Test status
Simulation time 11037950860 ps
CPU time 910.72 seconds
Started Jul 29 07:52:06 PM PDT 24
Finished Jul 29 08:07:17 PM PDT 24
Peak memory 647812 kb
Host smart-8075fdbf-9fa7-4b6e-a1ee-26ef9b830b18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741215343 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.2741215343
Directory /workspace/17.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.chip_csr_rw.2207189316
Short name T1482
Test name
Test status
Simulation time 4816468392 ps
CPU time 454.21 seconds
Started Jul 29 07:52:05 PM PDT 24
Finished Jul 29 07:59:40 PM PDT 24
Peak memory 597616 kb
Host smart-7d75ea6c-bd01-4752-9638-d8311b15f047
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207189316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.2207189316
Directory /workspace/17.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.3353857602
Short name T1750
Test name
Test status
Simulation time 30004264884 ps
CPU time 3366.38 seconds
Started Jul 29 07:52:00 PM PDT 24
Finished Jul 29 08:48:07 PM PDT 24
Peak memory 593756 kb
Host smart-df4752fb-f6ae-437a-8c29-d067981c7d48
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353857602 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.3353857602
Directory /workspace/17.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_access_same_device.2353326276
Short name T1399
Test name
Test status
Simulation time 102632191 ps
CPU time 9.15 seconds
Started Jul 29 07:52:04 PM PDT 24
Finished Jul 29 07:52:13 PM PDT 24
Peak memory 573828 kb
Host smart-01186c97-f416-4cf4-9f56-4bd59309bf32
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353326276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device
.2353326276
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.3298931507
Short name T487
Test name
Test status
Simulation time 67806258240 ps
CPU time 1153.26 seconds
Started Jul 29 07:52:06 PM PDT 24
Finished Jul 29 08:11:20 PM PDT 24
Peak memory 576020 kb
Host smart-03c0faef-bb9d-41c0-919d-7963249730d9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298931507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_
device_slow_rsp.3298931507
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.764444009
Short name T2381
Test name
Test status
Simulation time 543777340 ps
CPU time 23.26 seconds
Started Jul 29 07:52:09 PM PDT 24
Finished Jul 29 07:52:32 PM PDT 24
Peak memory 575908 kb
Host smart-d607fc03-9873-4f64-9f51-c8ed87a2f85b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764444009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr
.764444009
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_error_random.920659380
Short name T1579
Test name
Test status
Simulation time 1595282157 ps
CPU time 48.99 seconds
Started Jul 29 07:52:06 PM PDT 24
Finished Jul 29 07:52:55 PM PDT 24
Peak memory 575932 kb
Host smart-95580ebf-7214-4074-b5f0-d63ce0eacca8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920659380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.920659380
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random.2738315137
Short name T2846
Test name
Test status
Simulation time 970955454 ps
CPU time 37.48 seconds
Started Jul 29 07:52:07 PM PDT 24
Finished Jul 29 07:52:44 PM PDT 24
Peak memory 575880 kb
Host smart-6ea398ba-00ad-47f1-bb70-2ee9b7923e29
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738315137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.2738315137
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.1003163794
Short name T1560
Test name
Test status
Simulation time 92931553932 ps
CPU time 945.03 seconds
Started Jul 29 07:52:04 PM PDT 24
Finished Jul 29 08:07:49 PM PDT 24
Peak memory 576088 kb
Host smart-b7a86c2c-c3e2-4fe0-a5f0-180effe24c29
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003163794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1003163794
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.3112139261
Short name T1583
Test name
Test status
Simulation time 9812354591 ps
CPU time 163.91 seconds
Started Jul 29 07:52:07 PM PDT 24
Finished Jul 29 07:54:51 PM PDT 24
Peak memory 576160 kb
Host smart-baee49c5-7c7b-4605-a067-1c12c90a25a1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112139261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3112139261
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.2198380590
Short name T2553
Test name
Test status
Simulation time 148923011 ps
CPU time 14.12 seconds
Started Jul 29 07:52:08 PM PDT 24
Finished Jul 29 07:52:22 PM PDT 24
Peak memory 576084 kb
Host smart-512e3f72-9b16-4381-90fd-563ccf7cd129
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198380590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del
ays.2198380590
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_same_source.2869931341
Short name T2480
Test name
Test status
Simulation time 1772891704 ps
CPU time 53.09 seconds
Started Jul 29 07:52:05 PM PDT 24
Finished Jul 29 07:52:58 PM PDT 24
Peak memory 575940 kb
Host smart-e3acfd5d-6a4b-4c93-9670-a32f7a43244c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869931341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2869931341
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke.1344008727
Short name T745
Test name
Test status
Simulation time 205684908 ps
CPU time 8.78 seconds
Started Jul 29 07:52:01 PM PDT 24
Finished Jul 29 07:52:10 PM PDT 24
Peak memory 573940 kb
Host smart-2a83c497-489c-4770-a966-83807dba3f72
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344008727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1344008727
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.1477101394
Short name T2291
Test name
Test status
Simulation time 7772945363 ps
CPU time 72.44 seconds
Started Jul 29 07:51:56 PM PDT 24
Finished Jul 29 07:53:08 PM PDT 24
Peak memory 574616 kb
Host smart-c51579d9-630d-459f-b9a4-88f4184c6629
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477101394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1477101394
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.3053996539
Short name T1423
Test name
Test status
Simulation time 5858813993 ps
CPU time 97.09 seconds
Started Jul 29 07:52:01 PM PDT 24
Finished Jul 29 07:53:38 PM PDT 24
Peak memory 574684 kb
Host smart-62c0bb1f-f161-41b3-8f9a-834a6a6fdd92
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053996539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3053996539
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3221775036
Short name T2092
Test name
Test status
Simulation time 57464764 ps
CPU time 6.81 seconds
Started Jul 29 07:51:55 PM PDT 24
Finished Jul 29 07:52:02 PM PDT 24
Peak memory 573872 kb
Host smart-812a8996-b5aa-48e8-8c9a-1c5ffa9b3344
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221775036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay
s.3221775036
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all.1961555171
Short name T1785
Test name
Test status
Simulation time 4165115990 ps
CPU time 150.65 seconds
Started Jul 29 07:52:06 PM PDT 24
Finished Jul 29 07:54:37 PM PDT 24
Peak memory 576060 kb
Host smart-1a739e7a-e2b4-46fa-bcbf-e3d6640e89f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961555171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1961555171
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.3257964519
Short name T1860
Test name
Test status
Simulation time 305669187 ps
CPU time 22.48 seconds
Started Jul 29 07:52:07 PM PDT 24
Finished Jul 29 07:52:29 PM PDT 24
Peak memory 576012 kb
Host smart-ad236fd9-37d9-4b07-a996-724aae748874
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257964519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3257964519
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.3115925916
Short name T502
Test name
Test status
Simulation time 14611293431 ps
CPU time 851.37 seconds
Started Jul 29 07:52:04 PM PDT 24
Finished Jul 29 08:06:15 PM PDT 24
Peak memory 576064 kb
Host smart-6bdbd797-6d59-4e97-9c8a-c35197acbd5a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115925916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all
_with_rand_reset.3115925916
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.3843983963
Short name T694
Test name
Test status
Simulation time 5701947735 ps
CPU time 613.12 seconds
Started Jul 29 07:52:09 PM PDT 24
Finished Jul 29 08:02:23 PM PDT 24
Peak memory 575920 kb
Host smart-b476fdfb-f4c0-43dd-ad27-5b2273311503
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843983963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al
l_with_reset_error.3843983963
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.44014059
Short name T515
Test name
Test status
Simulation time 1415498064 ps
CPU time 54.2 seconds
Started Jul 29 07:52:06 PM PDT 24
Finished Jul 29 07:53:00 PM PDT 24
Peak memory 576060 kb
Host smart-893f4bba-34ca-4130-828c-cb00782ea743
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44014059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.44014059
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.3117360476
Short name T1825
Test name
Test status
Simulation time 6179792163 ps
CPU time 420.67 seconds
Started Jul 29 07:52:25 PM PDT 24
Finished Jul 29 07:59:26 PM PDT 24
Peak memory 642912 kb
Host smart-3d57b363-3a25-467a-b630-474ce8d08321
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117360476 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.3117360476
Directory /workspace/18.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.chip_csr_rw.4165160118
Short name T1627
Test name
Test status
Simulation time 6368389580 ps
CPU time 534.2 seconds
Started Jul 29 07:52:31 PM PDT 24
Finished Jul 29 08:01:26 PM PDT 24
Peak memory 599124 kb
Host smart-553b66eb-b154-447e-a6d8-634acbba5567
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165160118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.4165160118
Directory /workspace/18.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.2775815525
Short name T2724
Test name
Test status
Simulation time 16585497214 ps
CPU time 1924.76 seconds
Started Jul 29 07:52:07 PM PDT 24
Finished Jul 29 08:24:12 PM PDT 24
Peak memory 593452 kb
Host smart-ac126601-4839-4dad-9a33-8242f30304d3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775815525 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.2775815525
Directory /workspace/18.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_access_same_device.766492691
Short name T841
Test name
Test status
Simulation time 1939469167 ps
CPU time 76.67 seconds
Started Jul 29 07:52:15 PM PDT 24
Finished Jul 29 07:53:31 PM PDT 24
Peak memory 575912 kb
Host smart-272bef8a-443d-4d6e-bb44-f8f85c56ebb6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766492691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.
766492691
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3997579243
Short name T1777
Test name
Test status
Simulation time 83570451255 ps
CPU time 1376.57 seconds
Started Jul 29 07:52:15 PM PDT 24
Finished Jul 29 08:15:12 PM PDT 24
Peak memory 576028 kb
Host smart-471f6af4-2837-4fef-9d29-82ac0057874f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997579243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_
device_slow_rsp.3997579243
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2024139756
Short name T1397
Test name
Test status
Simulation time 361160026 ps
CPU time 17.48 seconds
Started Jul 29 07:52:14 PM PDT 24
Finished Jul 29 07:52:31 PM PDT 24
Peak memory 575788 kb
Host smart-47428dc0-1988-47b0-9ae0-3ca009c1e7fd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024139756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add
r.2024139756
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_error_random.2499930105
Short name T2680
Test name
Test status
Simulation time 224297301 ps
CPU time 21.45 seconds
Started Jul 29 07:52:16 PM PDT 24
Finished Jul 29 07:52:37 PM PDT 24
Peak memory 576048 kb
Host smart-51989141-926d-40b0-8f2f-d3c403e4d16f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499930105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2499930105
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random.398013912
Short name T2021
Test name
Test status
Simulation time 497235535 ps
CPU time 42.1 seconds
Started Jul 29 07:52:19 PM PDT 24
Finished Jul 29 07:53:02 PM PDT 24
Peak memory 575900 kb
Host smart-816f0b37-5335-4aa0-9f13-76a50600457c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398013912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.398013912
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.1926875570
Short name T2693
Test name
Test status
Simulation time 103423587319 ps
CPU time 1060.61 seconds
Started Jul 29 07:52:15 PM PDT 24
Finished Jul 29 08:09:56 PM PDT 24
Peak memory 576212 kb
Host smart-5e56aa5c-ef29-4841-8aee-9aab5d74b385
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926875570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1926875570
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.2002253518
Short name T1656
Test name
Test status
Simulation time 13590147654 ps
CPU time 219.59 seconds
Started Jul 29 07:52:14 PM PDT 24
Finished Jul 29 07:55:53 PM PDT 24
Peak memory 575936 kb
Host smart-96770cc4-3bfd-43c2-932b-adb2ccde2d0f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002253518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2002253518
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.1879065440
Short name T2664
Test name
Test status
Simulation time 99610659 ps
CPU time 10.97 seconds
Started Jul 29 07:52:22 PM PDT 24
Finished Jul 29 07:52:33 PM PDT 24
Peak memory 575692 kb
Host smart-cd600d4c-7461-41c9-b8f4-aa508a3b3b2e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879065440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del
ays.1879065440
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_same_source.3713664407
Short name T2444
Test name
Test status
Simulation time 1543564039 ps
CPU time 48.6 seconds
Started Jul 29 07:52:14 PM PDT 24
Finished Jul 29 07:53:03 PM PDT 24
Peak memory 575964 kb
Host smart-a4285412-5a24-4e48-95d5-37ea750f33d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713664407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3713664407
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke.837361024
Short name T2842
Test name
Test status
Simulation time 46692038 ps
CPU time 6.6 seconds
Started Jul 29 07:52:16 PM PDT 24
Finished Jul 29 07:52:23 PM PDT 24
Peak memory 574056 kb
Host smart-3f4de9dd-008b-4af4-a5b6-11d29f32c6d5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837361024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.837361024
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.3976033496
Short name T2591
Test name
Test status
Simulation time 8327383565 ps
CPU time 89.98 seconds
Started Jul 29 07:52:15 PM PDT 24
Finished Jul 29 07:53:45 PM PDT 24
Peak memory 574600 kb
Host smart-45c441cc-0196-4f08-92e7-47cbe24ddc8c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976033496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3976033496
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.867939168
Short name T1801
Test name
Test status
Simulation time 4946738534 ps
CPU time 77.72 seconds
Started Jul 29 07:52:21 PM PDT 24
Finished Jul 29 07:53:39 PM PDT 24
Peak memory 573884 kb
Host smart-c6fe51ad-bdb6-4f55-bc73-52fc5789ac6d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867939168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.867939168
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1611228344
Short name T2617
Test name
Test status
Simulation time 46998914 ps
CPU time 6.47 seconds
Started Jul 29 07:52:15 PM PDT 24
Finished Jul 29 07:52:22 PM PDT 24
Peak memory 573912 kb
Host smart-2f27bfe5-1851-4ea0-8dc1-d6f975084215
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611228344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay
s.1611228344
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all.552038939
Short name T1955
Test name
Test status
Simulation time 11927524153 ps
CPU time 443.58 seconds
Started Jul 29 07:52:14 PM PDT 24
Finished Jul 29 07:59:38 PM PDT 24
Peak memory 576048 kb
Host smart-957e6a53-64e6-4fb3-a75a-e70849e98a8e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552038939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.552038939
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.4201121851
Short name T2871
Test name
Test status
Simulation time 3980016556 ps
CPU time 149.39 seconds
Started Jul 29 07:52:26 PM PDT 24
Finished Jul 29 07:54:55 PM PDT 24
Peak memory 576144 kb
Host smart-b217bf49-c559-42a2-ab1e-d620b249ec66
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201121851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.4201121851
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1251106664
Short name T679
Test name
Test status
Simulation time 219018962 ps
CPU time 173.99 seconds
Started Jul 29 07:52:23 PM PDT 24
Finished Jul 29 07:55:17 PM PDT 24
Peak memory 576788 kb
Host smart-1e59df15-b4a2-428c-9eec-8aeb46398398
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251106664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all
_with_rand_reset.1251106664
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.30604426
Short name T879
Test name
Test status
Simulation time 406240516 ps
CPU time 157.66 seconds
Started Jul 29 07:52:26 PM PDT 24
Finished Jul 29 07:55:04 PM PDT 24
Peak memory 576784 kb
Host smart-e9341ec6-e791-40a0-83b0-e737e929150d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30604426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_
with_reset_error.30604426
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.2441271254
Short name T1728
Test name
Test status
Simulation time 917359900 ps
CPU time 35.65 seconds
Started Jul 29 07:52:15 PM PDT 24
Finished Jul 29 07:52:51 PM PDT 24
Peak memory 576040 kb
Host smart-1d4290c0-e42c-44fc-a1f4-3c5971538c85
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441271254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2441271254
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.1249762495
Short name T1978
Test name
Test status
Simulation time 7581660924 ps
CPU time 507.39 seconds
Started Jul 29 07:52:37 PM PDT 24
Finished Jul 29 08:01:04 PM PDT 24
Peak memory 638220 kb
Host smart-579ec706-d847-45a5-b91f-b91d852a19fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249762495 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.1249762495
Directory /workspace/19.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.chip_csr_rw.2988692276
Short name T2800
Test name
Test status
Simulation time 3843597950 ps
CPU time 331.22 seconds
Started Jul 29 07:52:34 PM PDT 24
Finished Jul 29 07:58:06 PM PDT 24
Peak memory 598176 kb
Host smart-26278507-7eec-457e-9402-d23b240cc11b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988692276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.2988692276
Directory /workspace/19.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.1273498466
Short name T456
Test name
Test status
Simulation time 30211222117 ps
CPU time 2934.98 seconds
Started Jul 29 07:52:27 PM PDT 24
Finished Jul 29 08:41:23 PM PDT 24
Peak memory 593848 kb
Host smart-d1aa3595-ac5b-4c5d-994d-467b72744b25
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273498466 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.1273498466
Directory /workspace/19.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.chip_tl_errors.1799530544
Short name T648
Test name
Test status
Simulation time 3964606010 ps
CPU time 238.08 seconds
Started Jul 29 07:52:31 PM PDT 24
Finished Jul 29 07:56:30 PM PDT 24
Peak memory 603912 kb
Host smart-19d7d85a-129e-4c1a-9d75-f8e44cb879ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799530544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.1799530544
Directory /workspace/19.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_access_same_device.3705326170
Short name T479
Test name
Test status
Simulation time 3318850728 ps
CPU time 132 seconds
Started Jul 29 07:52:27 PM PDT 24
Finished Jul 29 07:54:39 PM PDT 24
Peak memory 575936 kb
Host smart-ed5c172f-6d9f-4b4d-86a8-adaafa89c530
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705326170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device
.3705326170
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.626273282
Short name T866
Test name
Test status
Simulation time 124654767101 ps
CPU time 2118.76 seconds
Started Jul 29 07:52:25 PM PDT 24
Finished Jul 29 08:27:44 PM PDT 24
Peak memory 576096 kb
Host smart-7184e2e5-4941-4a8f-ae2a-1df0406a7a16
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626273282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_d
evice_slow_rsp.626273282
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1257197175
Short name T2100
Test name
Test status
Simulation time 78158424 ps
CPU time 11.7 seconds
Started Jul 29 07:52:26 PM PDT 24
Finished Jul 29 07:52:37 PM PDT 24
Peak memory 575824 kb
Host smart-ec79be7a-97d7-4cac-9da7-1e01088ed496
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257197175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add
r.1257197175
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_error_random.2841915139
Short name T1755
Test name
Test status
Simulation time 2003585767 ps
CPU time 58.4 seconds
Started Jul 29 07:52:26 PM PDT 24
Finished Jul 29 07:53:25 PM PDT 24
Peak memory 575988 kb
Host smart-4f81ec78-c2de-40c5-bffb-49106c39edfe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841915139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2841915139
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random.3991509102
Short name T2559
Test name
Test status
Simulation time 2751512165 ps
CPU time 93.2 seconds
Started Jul 29 07:52:27 PM PDT 24
Finished Jul 29 07:54:01 PM PDT 24
Peak memory 575912 kb
Host smart-f834a157-f041-4bb7-a0d4-3b107ee4e2e8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991509102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.3991509102
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.1227719309
Short name T1707
Test name
Test status
Simulation time 30900328746 ps
CPU time 298.58 seconds
Started Jul 29 07:52:27 PM PDT 24
Finished Jul 29 07:57:26 PM PDT 24
Peak memory 575936 kb
Host smart-b9c2eb72-85b0-4976-bf15-ba4e8e54be8d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227719309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1227719309
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.1230160789
Short name T2421
Test name
Test status
Simulation time 34478586879 ps
CPU time 613.9 seconds
Started Jul 29 07:52:26 PM PDT 24
Finished Jul 29 08:02:40 PM PDT 24
Peak memory 575984 kb
Host smart-aaef359c-43d9-4858-9c00-952814b5cc05
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230160789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1230160789
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.2335415293
Short name T2073
Test name
Test status
Simulation time 517260999 ps
CPU time 49.1 seconds
Started Jul 29 07:52:27 PM PDT 24
Finished Jul 29 07:53:16 PM PDT 24
Peak memory 575748 kb
Host smart-c267b8c3-d657-4b72-8f22-56eb93f06bea
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335415293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del
ays.2335415293
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_same_source.387679934
Short name T1738
Test name
Test status
Simulation time 367125651 ps
CPU time 13.36 seconds
Started Jul 29 07:52:28 PM PDT 24
Finished Jul 29 07:52:42 PM PDT 24
Peak memory 575884 kb
Host smart-a894133a-1220-4abb-870b-0144fc4cb434
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387679934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.387679934
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke.3067526550
Short name T2239
Test name
Test status
Simulation time 51183711 ps
CPU time 6.58 seconds
Started Jul 29 07:52:24 PM PDT 24
Finished Jul 29 07:52:31 PM PDT 24
Peak memory 573840 kb
Host smart-daff565c-5d86-4726-8a06-ffb3dc4618bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067526550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3067526550
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.4024952945
Short name T1494
Test name
Test status
Simulation time 7651916165 ps
CPU time 81.22 seconds
Started Jul 29 07:52:31 PM PDT 24
Finished Jul 29 07:53:53 PM PDT 24
Peak memory 574068 kb
Host smart-aa7015a3-e1e4-4299-8426-05628847d407
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024952945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.4024952945
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.290224320
Short name T2069
Test name
Test status
Simulation time 3368202891 ps
CPU time 56.9 seconds
Started Jul 29 07:52:27 PM PDT 24
Finished Jul 29 07:53:24 PM PDT 24
Peak memory 574552 kb
Host smart-e773f2ad-7502-4a0c-b4f3-a13730198fbb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290224320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.290224320
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.632723010
Short name T2639
Test name
Test status
Simulation time 54994410 ps
CPU time 6.84 seconds
Started Jul 29 07:52:25 PM PDT 24
Finished Jul 29 07:52:32 PM PDT 24
Peak memory 573760 kb
Host smart-49f9dcfb-5d61-4fb9-a312-e61d5b237923
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632723010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays
.632723010
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all.1448080580
Short name T2614
Test name
Test status
Simulation time 9472389933 ps
CPU time 394.42 seconds
Started Jul 29 07:52:36 PM PDT 24
Finished Jul 29 07:59:10 PM PDT 24
Peak memory 576596 kb
Host smart-ab8e8d29-e039-4a47-afea-7e5b390d31f0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448080580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1448080580
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.1685103737
Short name T1915
Test name
Test status
Simulation time 1983344146 ps
CPU time 153.9 seconds
Started Jul 29 07:52:35 PM PDT 24
Finished Jul 29 07:55:09 PM PDT 24
Peak memory 576284 kb
Host smart-1c60cdba-5ca6-4b9e-8375-ee30167b1672
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685103737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1685103737
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3302611707
Short name T2701
Test name
Test status
Simulation time 560276187 ps
CPU time 176.45 seconds
Started Jul 29 07:52:35 PM PDT 24
Finished Jul 29 07:55:32 PM PDT 24
Peak memory 576800 kb
Host smart-b0080d68-da26-4021-9e8e-43a4cb7bc708
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302611707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al
l_with_reset_error.3302611707
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.1638014947
Short name T506
Test name
Test status
Simulation time 84232397 ps
CPU time 13.27 seconds
Started Jul 29 07:52:27 PM PDT 24
Finished Jul 29 07:52:40 PM PDT 24
Peak memory 575828 kb
Host smart-c56c8316-bd46-457d-970e-f9a9c0356232
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638014947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1638014947
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.1887388630
Short name T2403
Test name
Test status
Simulation time 41050580719 ps
CPU time 6474.76 seconds
Started Jul 29 07:49:49 PM PDT 24
Finished Jul 29 09:37:45 PM PDT 24
Peak memory 593692 kb
Host smart-9586fb73-54fc-4cd2-a7f7-301e08227094
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887388630 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.chip_csr_aliasing.1887388630
Directory /workspace/2.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.2062566306
Short name T1528
Test name
Test status
Simulation time 57850116004 ps
CPU time 6168.82 seconds
Started Jul 29 07:49:55 PM PDT 24
Finished Jul 29 09:32:45 PM PDT 24
Peak memory 592564 kb
Host smart-049a21bc-41b1-423b-9843-73929e61e5a4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062566306 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.2062566306
Directory /workspace/2.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.3700465975
Short name T1986
Test name
Test status
Simulation time 9479724260 ps
CPU time 680.54 seconds
Started Jul 29 07:50:04 PM PDT 24
Finished Jul 29 08:01:25 PM PDT 24
Peak memory 645864 kb
Host smart-11f4bd76-431b-4464-8c7f-f0e91e693b87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700465975 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.3700465975
Directory /workspace/2.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_rw.3271333693
Short name T1589
Test name
Test status
Simulation time 5665021728 ps
CPU time 512.53 seconds
Started Jul 29 07:50:05 PM PDT 24
Finished Jul 29 07:58:38 PM PDT 24
Peak memory 599344 kb
Host smart-8e08f91a-4ab1-465a-8917-f84108f8825c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271333693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.3271333693
Directory /workspace/2.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.3341903080
Short name T1708
Test name
Test status
Simulation time 8658151472 ps
CPU time 265.16 seconds
Started Jul 29 07:49:49 PM PDT 24
Finished Jul 29 07:54:14 PM PDT 24
Peak memory 591496 kb
Host smart-c4a4f0e8-9348-4edd-a982-56cc276dd44b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341903080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.chip_prim_tl_access.3341903080
Directory /workspace/2.chip_prim_tl_access/latest

Test location /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.2474758115
Short name T1703
Test name
Test status
Simulation time 9486127596 ps
CPU time 361.83 seconds
Started Jul 29 07:49:50 PM PDT 24
Finished Jul 29 07:55:52 PM PDT 24
Peak memory 590364 kb
Host smart-094c1789-d6ae-4332-87c6-b0418941b6b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474758115 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.chip_rv_dm_lc_disabled.2474758115
Directory /workspace/2.chip_rv_dm_lc_disabled/latest

Test location /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.3381027723
Short name T2176
Test name
Test status
Simulation time 26855965276 ps
CPU time 3677.14 seconds
Started Jul 29 07:49:51 PM PDT 24
Finished Jul 29 08:51:09 PM PDT 24
Peak memory 593724 kb
Host smart-d813f60e-2ad0-4223-b954-c47e5b7978c3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381027723 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.3381027723
Directory /workspace/2.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.chip_tl_errors.3736856769
Short name T2766
Test name
Test status
Simulation time 3136741932 ps
CPU time 222.7 seconds
Started Jul 29 07:49:50 PM PDT 24
Finished Jul 29 07:53:33 PM PDT 24
Peak memory 599660 kb
Host smart-75cce8cc-5d2c-4bda-b082-ff5599627984
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736856769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.3736856769
Directory /workspace/2.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_access_same_device.1332300426
Short name T2063
Test name
Test status
Simulation time 266261983 ps
CPU time 19.69 seconds
Started Jul 29 07:50:04 PM PDT 24
Finished Jul 29 07:50:24 PM PDT 24
Peak memory 575944 kb
Host smart-232f5e20-bb8d-4a08-ac0a-7837ae386573
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332300426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.
1332300426
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2120389259
Short name T2836
Test name
Test status
Simulation time 87523519771 ps
CPU time 1430.19 seconds
Started Jul 29 07:50:01 PM PDT 24
Finished Jul 29 08:13:51 PM PDT 24
Peak memory 575932 kb
Host smart-75cf1afc-afba-4233-b16c-1b65b14c010e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120389259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d
evice_slow_rsp.2120389259
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.2899633645
Short name T1639
Test name
Test status
Simulation time 705861807 ps
CPU time 27.18 seconds
Started Jul 29 07:50:01 PM PDT 24
Finished Jul 29 07:50:28 PM PDT 24
Peak memory 575976 kb
Host smart-5c20c7d0-a0e8-4432-8fc9-2cecdab5b218
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899633645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr
.2899633645
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_error_random.3266335342
Short name T2916
Test name
Test status
Simulation time 1027497807 ps
CPU time 32.68 seconds
Started Jul 29 07:49:56 PM PDT 24
Finished Jul 29 07:50:29 PM PDT 24
Peak memory 575844 kb
Host smart-3f34d29a-bdc5-4b2b-866c-cef64e7857fc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266335342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3266335342
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random.180124890
Short name T2937
Test name
Test status
Simulation time 1967042992 ps
CPU time 65.67 seconds
Started Jul 29 07:49:56 PM PDT 24
Finished Jul 29 07:51:02 PM PDT 24
Peak memory 576008 kb
Host smart-553cd33c-0e86-4ba1-a565-d81868e8f360
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180124890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.180124890
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.3282663032
Short name T1896
Test name
Test status
Simulation time 75787591411 ps
CPU time 716.6 seconds
Started Jul 29 07:49:57 PM PDT 24
Finished Jul 29 08:01:54 PM PDT 24
Peak memory 576172 kb
Host smart-fdb5b3ae-41cc-4251-87a8-9581a07694fb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282663032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3282663032
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.2490734325
Short name T575
Test name
Test status
Simulation time 26466952452 ps
CPU time 435.49 seconds
Started Jul 29 07:50:03 PM PDT 24
Finished Jul 29 07:57:19 PM PDT 24
Peak memory 576136 kb
Host smart-bc2bb2af-c4ea-4618-9a58-0d783d0a4d40
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490734325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2490734325
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.707305855
Short name T1823
Test name
Test status
Simulation time 264505282 ps
CPU time 23.37 seconds
Started Jul 29 07:50:03 PM PDT 24
Finished Jul 29 07:50:27 PM PDT 24
Peak memory 575980 kb
Host smart-fbe78b37-10d7-4d11-b074-d2dfb2d9aa29
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707305855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delay
s.707305855
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_same_source.891460421
Short name T569
Test name
Test status
Simulation time 2223463834 ps
CPU time 62.08 seconds
Started Jul 29 07:49:48 PM PDT 24
Finished Jul 29 07:50:51 PM PDT 24
Peak memory 576016 kb
Host smart-7d27a6f5-052d-4634-9ed1-26a3ac063eb2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891460421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.891460421
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke.933149818
Short name T1406
Test name
Test status
Simulation time 181410787 ps
CPU time 8.55 seconds
Started Jul 29 07:50:01 PM PDT 24
Finished Jul 29 07:50:10 PM PDT 24
Peak memory 573820 kb
Host smart-e30129d8-71f8-45b7-a6e0-ad9dc608631e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933149818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.933149818
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.2157185919
Short name T1510
Test name
Test status
Simulation time 9621117286 ps
CPU time 98.28 seconds
Started Jul 29 07:50:03 PM PDT 24
Finished Jul 29 07:51:42 PM PDT 24
Peak memory 573972 kb
Host smart-50951613-1666-4041-a9e3-904670920d81
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157185919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2157185919
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.3507338028
Short name T615
Test name
Test status
Simulation time 3893020875 ps
CPU time 69.25 seconds
Started Jul 29 07:49:44 PM PDT 24
Finished Jul 29 07:50:53 PM PDT 24
Peak memory 574628 kb
Host smart-9ec35bd1-d4ca-4ea3-8235-9bc998c4d5d5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507338028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3507338028
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2442627613
Short name T544
Test name
Test status
Simulation time 49914986 ps
CPU time 6.21 seconds
Started Jul 29 07:49:50 PM PDT 24
Finished Jul 29 07:49:57 PM PDT 24
Peak memory 574500 kb
Host smart-4db285a1-bb19-4fe7-986b-80e8422b0cef
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442627613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays
.2442627613
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all.305871927
Short name T2586
Test name
Test status
Simulation time 10586064500 ps
CPU time 425.22 seconds
Started Jul 29 07:49:55 PM PDT 24
Finished Jul 29 07:57:00 PM PDT 24
Peak memory 575992 kb
Host smart-beb54b76-18eb-4df1-9889-c0e3d06d8170
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305871927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.305871927
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.2509994701
Short name T1489
Test name
Test status
Simulation time 961930779 ps
CPU time 69.05 seconds
Started Jul 29 07:50:01 PM PDT 24
Finished Jul 29 07:51:11 PM PDT 24
Peak memory 575788 kb
Host smart-a4709be6-a714-4463-823b-660018b5cd61
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509994701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.2509994701
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.1712454042
Short name T572
Test name
Test status
Simulation time 449482635 ps
CPU time 157.09 seconds
Started Jul 29 07:50:01 PM PDT 24
Finished Jul 29 07:52:38 PM PDT 24
Peak memory 576712 kb
Host smart-0733835a-5236-4941-8d1d-839a0086ea44
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712454042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_
with_rand_reset.1712454042
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.1610300367
Short name T2929
Test name
Test status
Simulation time 153736680 ps
CPU time 17.75 seconds
Started Jul 29 07:50:04 PM PDT 24
Finished Jul 29 07:50:22 PM PDT 24
Peak memory 576224 kb
Host smart-b5131078-521c-4c50-90bf-c0952dbd809a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610300367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all
_with_reset_error.1610300367
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.2301832441
Short name T623
Test name
Test status
Simulation time 334436846 ps
CPU time 33.47 seconds
Started Jul 29 07:50:05 PM PDT 24
Finished Jul 29 07:50:38 PM PDT 24
Peak memory 575996 kb
Host smart-a72dc0ca-5eed-445e-bf86-26d27d77c319
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301832441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2301832441
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/20.chip_tl_errors.3985804786
Short name T774
Test name
Test status
Simulation time 2730162840 ps
CPU time 96.91 seconds
Started Jul 29 07:52:37 PM PDT 24
Finished Jul 29 07:54:14 PM PDT 24
Peak memory 598656 kb
Host smart-e7283be6-854c-499c-81cc-d05f13d7ef52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985804786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.3985804786
Directory /workspace/20.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_access_same_device.4294826054
Short name T2330
Test name
Test status
Simulation time 121850396 ps
CPU time 13.56 seconds
Started Jul 29 07:52:46 PM PDT 24
Finished Jul 29 07:52:59 PM PDT 24
Peak memory 575824 kb
Host smart-ab6ac6b9-6a2d-498e-8207-c55ecaf2ad07
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294826054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device
.4294826054
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.98268859
Short name T1813
Test name
Test status
Simulation time 645386045 ps
CPU time 27.24 seconds
Started Jul 29 07:52:47 PM PDT 24
Finished Jul 29 07:53:14 PM PDT 24
Peak memory 575812 kb
Host smart-ae0bd16d-d299-4bbe-a357-7053597dd3bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98268859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.98268859
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_error_random.1273062497
Short name T2070
Test name
Test status
Simulation time 1346707942 ps
CPU time 47.55 seconds
Started Jul 29 07:52:46 PM PDT 24
Finished Jul 29 07:53:34 PM PDT 24
Peak memory 575960 kb
Host smart-c06ab72a-1224-4820-a74a-049833955dbf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273062497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1273062497
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random.1246907073
Short name T2890
Test name
Test status
Simulation time 455218342 ps
CPU time 35.2 seconds
Started Jul 29 07:52:44 PM PDT 24
Finished Jul 29 07:53:19 PM PDT 24
Peak memory 575996 kb
Host smart-05aade27-8488-45b8-9c6e-49d4c2aa04ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246907073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.1246907073
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.3031176151
Short name T2294
Test name
Test status
Simulation time 4291984179 ps
CPU time 67.02 seconds
Started Jul 29 07:52:46 PM PDT 24
Finished Jul 29 07:53:53 PM PDT 24
Peak memory 573952 kb
Host smart-8690e821-8a66-4973-b062-a4b5930c04d9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031176151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3031176151
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.4121957079
Short name T2466
Test name
Test status
Simulation time 333705752 ps
CPU time 30.27 seconds
Started Jul 29 07:52:45 PM PDT 24
Finished Jul 29 07:53:15 PM PDT 24
Peak memory 575988 kb
Host smart-7765221d-1af9-4ca4-9836-a9340e2420d7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121957079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del
ays.4121957079
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_same_source.1691627528
Short name T2678
Test name
Test status
Simulation time 711989102 ps
CPU time 24.75 seconds
Started Jul 29 07:52:44 PM PDT 24
Finished Jul 29 07:53:09 PM PDT 24
Peak memory 575800 kb
Host smart-45bb9672-60c2-4bf9-8a84-f573f3e6a5e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691627528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1691627528
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke.3907785651
Short name T2821
Test name
Test status
Simulation time 127547695 ps
CPU time 7.55 seconds
Started Jul 29 07:52:35 PM PDT 24
Finished Jul 29 07:52:42 PM PDT 24
Peak memory 573832 kb
Host smart-253ac09d-7532-4576-81ed-72d4c1ba0979
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907785651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.3907785651
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.1028553920
Short name T2790
Test name
Test status
Simulation time 10947869231 ps
CPU time 118.05 seconds
Started Jul 29 07:52:34 PM PDT 24
Finished Jul 29 07:54:32 PM PDT 24
Peak memory 573912 kb
Host smart-9e1defb0-9d3d-4189-89d3-59480bac1669
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028553920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1028553920
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.1072081952
Short name T2358
Test name
Test status
Simulation time 5400775794 ps
CPU time 91.92 seconds
Started Jul 29 07:52:35 PM PDT 24
Finished Jul 29 07:54:07 PM PDT 24
Peak memory 573940 kb
Host smart-2ff2f069-ec02-45e2-a85f-a74c1de7f681
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072081952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1072081952
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.1724639775
Short name T1705
Test name
Test status
Simulation time 48706642 ps
CPU time 6.08 seconds
Started Jul 29 07:52:34 PM PDT 24
Finished Jul 29 07:52:40 PM PDT 24
Peak memory 574548 kb
Host smart-f45da456-e6ee-42ae-96f0-6f7c56be0318
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724639775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay
s.1724639775
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all.2244751365
Short name T1634
Test name
Test status
Simulation time 4938243913 ps
CPU time 217.95 seconds
Started Jul 29 07:52:45 PM PDT 24
Finished Jul 29 07:56:23 PM PDT 24
Peak memory 576076 kb
Host smart-cdbe8637-72a3-4677-bfd8-8bb64b4f49d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244751365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2244751365
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.3817871877
Short name T2705
Test name
Test status
Simulation time 1354394049 ps
CPU time 97.31 seconds
Started Jul 29 07:52:45 PM PDT 24
Finished Jul 29 07:54:22 PM PDT 24
Peak memory 576088 kb
Host smart-2884bec7-d641-4525-b5e0-66802fe49c49
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817871877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3817871877
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.4108773011
Short name T485
Test name
Test status
Simulation time 1580824021 ps
CPU time 159.24 seconds
Started Jul 29 07:52:45 PM PDT 24
Finished Jul 29 07:55:25 PM PDT 24
Peak memory 575960 kb
Host smart-9733d81a-2dbd-4a13-872a-0201f251e454
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108773011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all
_with_rand_reset.4108773011
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.1459869201
Short name T2290
Test name
Test status
Simulation time 6153548134 ps
CPU time 369.01 seconds
Started Jul 29 07:52:46 PM PDT 24
Finished Jul 29 07:58:55 PM PDT 24
Peak memory 576756 kb
Host smart-79478c23-339d-4721-a482-f19b22e46c2b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459869201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al
l_with_reset_error.1459869201
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.150389337
Short name T1546
Test name
Test status
Simulation time 587172202 ps
CPU time 29.06 seconds
Started Jul 29 07:52:45 PM PDT 24
Finished Jul 29 07:53:14 PM PDT 24
Peak memory 575800 kb
Host smart-09d8df98-8796-4355-aeb2-f98ce5dba835
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150389337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.150389337
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/21.chip_tl_errors.1630852802
Short name T2688
Test name
Test status
Simulation time 4071962243 ps
CPU time 335.79 seconds
Started Jul 29 07:52:46 PM PDT 24
Finished Jul 29 07:58:22 PM PDT 24
Peak memory 603900 kb
Host smart-c73514ca-2f4a-49db-8406-13c5ca807d3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630852802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.1630852802
Directory /workspace/21.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_access_same_device.339986494
Short name T2377
Test name
Test status
Simulation time 2891714755 ps
CPU time 103.63 seconds
Started Jul 29 07:53:00 PM PDT 24
Finished Jul 29 07:54:43 PM PDT 24
Peak memory 575976 kb
Host smart-873c4bda-8b46-469c-a891-5f059a3faf4d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339986494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.
339986494
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.2199000553
Short name T1442
Test name
Test status
Simulation time 266114183 ps
CPU time 29.68 seconds
Started Jul 29 07:52:59 PM PDT 24
Finished Jul 29 07:53:29 PM PDT 24
Peak memory 575796 kb
Host smart-ec940e0b-b6bc-4fed-a62c-0d23750a0177
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199000553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add
r.2199000553
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_error_random.3339083771
Short name T1417
Test name
Test status
Simulation time 976483939 ps
CPU time 38.91 seconds
Started Jul 29 07:52:56 PM PDT 24
Finished Jul 29 07:53:35 PM PDT 24
Peak memory 575920 kb
Host smart-78a19182-afcd-4244-b4f4-a393f5e3e6c0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339083771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3339083771
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random.2252883490
Short name T1488
Test name
Test status
Simulation time 119579179 ps
CPU time 11.73 seconds
Started Jul 29 07:52:57 PM PDT 24
Finished Jul 29 07:53:08 PM PDT 24
Peak memory 575832 kb
Host smart-1048e6f0-1186-4266-981f-dcfd2a988cd9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252883490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.2252883490
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.1961981195
Short name T1815
Test name
Test status
Simulation time 17245111452 ps
CPU time 177.42 seconds
Started Jul 29 07:52:54 PM PDT 24
Finished Jul 29 07:55:52 PM PDT 24
Peak memory 576076 kb
Host smart-6e0d9ed2-340e-4ac0-9838-857579dba586
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961981195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1961981195
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.2441058924
Short name T603
Test name
Test status
Simulation time 45211886308 ps
CPU time 659.42 seconds
Started Jul 29 07:52:55 PM PDT 24
Finished Jul 29 08:03:54 PM PDT 24
Peak memory 576048 kb
Host smart-0b6cbb6a-baa1-4c97-bb27-b0818275c582
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441058924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2441058924
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.3244174564
Short name T1949
Test name
Test status
Simulation time 132338742 ps
CPU time 13.65 seconds
Started Jul 29 07:52:57 PM PDT 24
Finished Jul 29 07:53:11 PM PDT 24
Peak memory 575936 kb
Host smart-6e8080c1-c5a4-45cf-ad68-f3313af7dd67
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244174564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del
ays.3244174564
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_same_source.172924024
Short name T1859
Test name
Test status
Simulation time 253036121 ps
CPU time 20.63 seconds
Started Jul 29 07:52:59 PM PDT 24
Finished Jul 29 07:53:20 PM PDT 24
Peak memory 575872 kb
Host smart-f64ea213-9055-4498-bc77-6ac0454b4dc4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172924024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.172924024
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke.653063576
Short name T1696
Test name
Test status
Simulation time 250035542 ps
CPU time 9.31 seconds
Started Jul 29 07:52:44 PM PDT 24
Finished Jul 29 07:52:54 PM PDT 24
Peak memory 574548 kb
Host smart-cf43eba5-e130-47c2-bc1b-77099dbdfeef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653063576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.653063576
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.4158921762
Short name T2055
Test name
Test status
Simulation time 7921505265 ps
CPU time 91.65 seconds
Started Jul 29 07:52:44 PM PDT 24
Finished Jul 29 07:54:16 PM PDT 24
Peak memory 574140 kb
Host smart-7802053a-f9e6-4711-ae0c-fa53596b8759
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158921762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.4158921762
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.4220196307
Short name T2592
Test name
Test status
Simulation time 4170980563 ps
CPU time 69.24 seconds
Started Jul 29 07:52:45 PM PDT 24
Finished Jul 29 07:53:55 PM PDT 24
Peak memory 573944 kb
Host smart-17e5393e-6d3d-48d1-bf2f-19f26f3e7b9d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220196307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.4220196307
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.2409389034
Short name T552
Test name
Test status
Simulation time 38992385 ps
CPU time 5.7 seconds
Started Jul 29 07:52:46 PM PDT 24
Finished Jul 29 07:52:52 PM PDT 24
Peak memory 574500 kb
Host smart-6b6595e9-99ed-42f5-9351-6a9ce7d92992
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409389034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay
s.2409389034
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all.2114069690
Short name T2923
Test name
Test status
Simulation time 13965070316 ps
CPU time 530.71 seconds
Started Jul 29 07:52:54 PM PDT 24
Finished Jul 29 08:01:44 PM PDT 24
Peak memory 576060 kb
Host smart-3a41ffd5-2b86-4c96-89b5-8ec1b5e605e4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114069690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.2114069690
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.2760211944
Short name T1980
Test name
Test status
Simulation time 3471106867 ps
CPU time 107.7 seconds
Started Jul 29 07:52:58 PM PDT 24
Finished Jul 29 07:54:46 PM PDT 24
Peak memory 575988 kb
Host smart-7542abd9-834b-449e-9bc7-7234102fd2d4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760211944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2760211944
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.1963058161
Short name T1771
Test name
Test status
Simulation time 174403963 ps
CPU time 96.8 seconds
Started Jul 29 07:52:57 PM PDT 24
Finished Jul 29 07:54:34 PM PDT 24
Peak memory 576104 kb
Host smart-1b72205f-efdd-4863-8e8e-1d9b4644b325
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963058161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all
_with_rand_reset.1963058161
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.4110232586
Short name T675
Test name
Test status
Simulation time 1968143681 ps
CPU time 207.84 seconds
Started Jul 29 07:52:54 PM PDT 24
Finished Jul 29 07:56:22 PM PDT 24
Peak memory 576804 kb
Host smart-cd382649-8af2-4bac-8572-35b06eb26d50
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110232586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al
l_with_reset_error.4110232586
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.2351122313
Short name T2759
Test name
Test status
Simulation time 393551041 ps
CPU time 17.86 seconds
Started Jul 29 07:52:55 PM PDT 24
Finished Jul 29 07:53:13 PM PDT 24
Peak memory 575952 kb
Host smart-e1c09a9b-67bf-4ff8-aa2e-c024580faad4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351122313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2351122313
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/22.chip_tl_errors.3412182255
Short name T684
Test name
Test status
Simulation time 4022186600 ps
CPU time 183.75 seconds
Started Jul 29 07:52:55 PM PDT 24
Finished Jul 29 07:55:59 PM PDT 24
Peak memory 599720 kb
Host smart-2bc40ad8-bae9-4405-8915-a3443d0f1bea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412182255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.3412182255
Directory /workspace/22.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_access_same_device.3969780405
Short name T1574
Test name
Test status
Simulation time 222195301 ps
CPU time 19.6 seconds
Started Jul 29 07:53:08 PM PDT 24
Finished Jul 29 07:53:27 PM PDT 24
Peak memory 575860 kb
Host smart-8e948b13-582c-4f83-8444-e612b8715ea9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969780405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device
.3969780405
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.4066104477
Short name T2064
Test name
Test status
Simulation time 110282149711 ps
CPU time 1991.77 seconds
Started Jul 29 07:53:04 PM PDT 24
Finished Jul 29 08:26:16 PM PDT 24
Peak memory 576112 kb
Host smart-581f7fef-cfa6-4a7d-8ce5-a1131c9d3599
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066104477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_
device_slow_rsp.4066104477
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.994746623
Short name T2793
Test name
Test status
Simulation time 97991639 ps
CPU time 6.71 seconds
Started Jul 29 07:53:06 PM PDT 24
Finished Jul 29 07:53:13 PM PDT 24
Peak memory 573956 kb
Host smart-022c20e2-da04-4d50-9103-f772158358d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994746623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr
.994746623
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_error_random.539144126
Short name T1718
Test name
Test status
Simulation time 1974471979 ps
CPU time 73.58 seconds
Started Jul 29 07:53:08 PM PDT 24
Finished Jul 29 07:54:21 PM PDT 24
Peak memory 575988 kb
Host smart-4407f14a-e748-462a-8e3f-0448cdf42de5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539144126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.539144126
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random.3046683961
Short name T1554
Test name
Test status
Simulation time 891766130 ps
CPU time 33.92 seconds
Started Jul 29 07:53:04 PM PDT 24
Finished Jul 29 07:53:38 PM PDT 24
Peak memory 575992 kb
Host smart-640ae314-187f-4059-af95-5b2da62abd8c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046683961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.3046683961
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.2445417515
Short name T2699
Test name
Test status
Simulation time 40647193608 ps
CPU time 409.46 seconds
Started Jul 29 07:53:08 PM PDT 24
Finished Jul 29 07:59:57 PM PDT 24
Peak memory 576044 kb
Host smart-b5751bd4-a43d-4646-81b2-715ff1fc028d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445417515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2445417515
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.688993216
Short name T1811
Test name
Test status
Simulation time 52705146962 ps
CPU time 842.99 seconds
Started Jul 29 07:53:04 PM PDT 24
Finished Jul 29 08:07:07 PM PDT 24
Peak memory 575976 kb
Host smart-6a95ec82-cddc-4e92-b751-40191d4c7d36
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688993216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.688993216
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.3472663559
Short name T2255
Test name
Test status
Simulation time 158809690 ps
CPU time 17.41 seconds
Started Jul 29 07:53:06 PM PDT 24
Finished Jul 29 07:53:24 PM PDT 24
Peak memory 575956 kb
Host smart-0e6362e0-29e1-4bfa-a1cc-640c1f02f68d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472663559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del
ays.3472663559
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_same_source.556511129
Short name T2220
Test name
Test status
Simulation time 588616952 ps
CPU time 19.13 seconds
Started Jul 29 07:53:05 PM PDT 24
Finished Jul 29 07:53:25 PM PDT 24
Peak memory 575940 kb
Host smart-6b182afe-4f55-4761-acbf-88cea20c6696
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556511129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.556511129
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke.3715626743
Short name T2772
Test name
Test status
Simulation time 145492996 ps
CPU time 7.67 seconds
Started Jul 29 07:52:58 PM PDT 24
Finished Jul 29 07:53:06 PM PDT 24
Peak memory 573892 kb
Host smart-98595da3-c7f0-4883-9e9f-ff9a11ad3a49
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715626743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3715626743
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.2586453174
Short name T2157
Test name
Test status
Simulation time 5930020745 ps
CPU time 58.46 seconds
Started Jul 29 07:53:04 PM PDT 24
Finished Jul 29 07:54:02 PM PDT 24
Peak memory 574712 kb
Host smart-dfb03f71-05bb-4509-96dc-54d037c10f26
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586453174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2586453174
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.2445620052
Short name T1454
Test name
Test status
Simulation time 4473337800 ps
CPU time 71.98 seconds
Started Jul 29 07:53:03 PM PDT 24
Finished Jul 29 07:54:15 PM PDT 24
Peak memory 574736 kb
Host smart-1c6d1a76-5139-464b-9e51-e902cd4dba30
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445620052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2445620052
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.579711616
Short name T2706
Test name
Test status
Simulation time 46481947 ps
CPU time 6.42 seconds
Started Jul 29 07:52:54 PM PDT 24
Finished Jul 29 07:53:01 PM PDT 24
Peak memory 573808 kb
Host smart-6694f6d4-7433-46ed-b450-e13c0a1fe0d2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579711616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays
.579711616
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.756175340
Short name T2307
Test name
Test status
Simulation time 2478061843 ps
CPU time 189.92 seconds
Started Jul 29 07:53:05 PM PDT 24
Finished Jul 29 07:56:15 PM PDT 24
Peak memory 576496 kb
Host smart-1fc2eeb5-3c01-471e-b441-719c24f07d87
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756175340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.756175340
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.1087335869
Short name T1875
Test name
Test status
Simulation time 1384793125 ps
CPU time 56.46 seconds
Started Jul 29 07:53:09 PM PDT 24
Finished Jul 29 07:54:05 PM PDT 24
Peak memory 575868 kb
Host smart-3ac0b140-3d51-40c8-b794-d4f303581648
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087335869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1087335869
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_access_same_device.4092269510
Short name T1822
Test name
Test status
Simulation time 2552039523 ps
CPU time 110.32 seconds
Started Jul 29 07:53:15 PM PDT 24
Finished Jul 29 07:55:05 PM PDT 24
Peak memory 575996 kb
Host smart-fa772e86-8f69-40b4-8445-ec94386c2e33
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092269510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device
.4092269510
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.1217070589
Short name T857
Test name
Test status
Simulation time 127989524752 ps
CPU time 2396.37 seconds
Started Jul 29 07:53:14 PM PDT 24
Finished Jul 29 08:33:11 PM PDT 24
Peak memory 576048 kb
Host smart-2f1a430e-22c7-420d-9226-1b0a512c452b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217070589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_
device_slow_rsp.1217070589
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.2604682884
Short name T2243
Test name
Test status
Simulation time 693345869 ps
CPU time 29.49 seconds
Started Jul 29 07:53:14 PM PDT 24
Finished Jul 29 07:53:44 PM PDT 24
Peak memory 575980 kb
Host smart-eaeb50ae-d8d1-422e-b2e7-c8dbb25e433b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604682884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add
r.2604682884
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_error_random.751690371
Short name T2897
Test name
Test status
Simulation time 842823364 ps
CPU time 28.49 seconds
Started Jul 29 07:53:20 PM PDT 24
Finished Jul 29 07:53:48 PM PDT 24
Peak memory 575720 kb
Host smart-d1ff392f-9aa6-4c28-a83b-c7a7cd454196
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751690371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.751690371
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random.3560185760
Short name T624
Test name
Test status
Simulation time 92942204 ps
CPU time 10.67 seconds
Started Jul 29 07:53:15 PM PDT 24
Finished Jul 29 07:53:26 PM PDT 24
Peak memory 575960 kb
Host smart-50d078f1-0eb9-4f56-83fa-b299c3beb855
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560185760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.3560185760
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.2518204637
Short name T2742
Test name
Test status
Simulation time 92167693156 ps
CPU time 971.93 seconds
Started Jul 29 07:53:14 PM PDT 24
Finished Jul 29 08:09:26 PM PDT 24
Peak memory 576848 kb
Host smart-ef9c484b-cef1-45ef-b5ec-8bb0a456279a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518204637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2518204637
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.2529807663
Short name T512
Test name
Test status
Simulation time 56101188476 ps
CPU time 955.41 seconds
Started Jul 29 07:53:15 PM PDT 24
Finished Jul 29 08:09:11 PM PDT 24
Peak memory 576120 kb
Host smart-e47ceb79-ff54-42a3-9a85-8e6e2bda1bdd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529807663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2529807663
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.1348420014
Short name T692
Test name
Test status
Simulation time 306261246 ps
CPU time 30.18 seconds
Started Jul 29 07:53:14 PM PDT 24
Finished Jul 29 07:53:44 PM PDT 24
Peak memory 575968 kb
Host smart-2787a1b1-8798-473b-9e36-28af3b93209b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348420014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del
ays.1348420014
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_same_source.1631202673
Short name T2331
Test name
Test status
Simulation time 2401522547 ps
CPU time 68.78 seconds
Started Jul 29 07:53:15 PM PDT 24
Finished Jul 29 07:54:23 PM PDT 24
Peak memory 575924 kb
Host smart-ce9af96b-e37c-47e2-a0ab-f287ef4b0515
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631202673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1631202673
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke.818767424
Short name T2259
Test name
Test status
Simulation time 193961222 ps
CPU time 8.55 seconds
Started Jul 29 07:53:23 PM PDT 24
Finished Jul 29 07:53:31 PM PDT 24
Peak memory 573932 kb
Host smart-252baace-f72c-4320-98b1-af80667ed371
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818767424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.818767424
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.2411562621
Short name T2640
Test name
Test status
Simulation time 8705701799 ps
CPU time 86.88 seconds
Started Jul 29 07:53:23 PM PDT 24
Finished Jul 29 07:54:50 PM PDT 24
Peak memory 574032 kb
Host smart-100d9860-527a-4514-beae-c89373cc5538
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411562621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2411562621
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.4273291390
Short name T2938
Test name
Test status
Simulation time 5658199047 ps
CPU time 90.15 seconds
Started Jul 29 07:53:23 PM PDT 24
Finished Jul 29 07:54:53 PM PDT 24
Peak memory 574008 kb
Host smart-6dc0e44a-d456-43c2-9089-2601f64964dd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273291390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.4273291390
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.3114155208
Short name T2927
Test name
Test status
Simulation time 50226779 ps
CPU time 6.28 seconds
Started Jul 29 07:53:20 PM PDT 24
Finished Jul 29 07:53:26 PM PDT 24
Peak memory 573844 kb
Host smart-1cb0e760-1cba-4454-ac68-ee03a25d0942
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114155208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay
s.3114155208
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all.3799412456
Short name T2232
Test name
Test status
Simulation time 1200927168 ps
CPU time 82.4 seconds
Started Jul 29 07:53:23 PM PDT 24
Finished Jul 29 07:54:45 PM PDT 24
Peak memory 576108 kb
Host smart-b1c48a2c-dd00-481a-836e-4825a5e8f089
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799412456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3799412456
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.1557005661
Short name T1774
Test name
Test status
Simulation time 3038283073 ps
CPU time 94.72 seconds
Started Jul 29 07:53:13 PM PDT 24
Finished Jul 29 07:54:48 PM PDT 24
Peak memory 575984 kb
Host smart-c479624c-c2ce-43a7-9528-8eaa3088c54d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557005661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1557005661
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.1817023707
Short name T2567
Test name
Test status
Simulation time 3789260553 ps
CPU time 254.04 seconds
Started Jul 29 07:53:14 PM PDT 24
Finished Jul 29 07:57:28 PM PDT 24
Peak memory 576848 kb
Host smart-b646aff9-8494-4711-bbf6-636d8a9fcb7b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817023707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all
_with_rand_reset.1817023707
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.3886203810
Short name T2040
Test name
Test status
Simulation time 1227464504 ps
CPU time 164.35 seconds
Started Jul 29 07:53:21 PM PDT 24
Finished Jul 29 07:56:05 PM PDT 24
Peak memory 575972 kb
Host smart-1f44e189-81e7-4e08-a10f-ff27b39d1d8c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886203810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al
l_with_reset_error.3886203810
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.2208360888
Short name T2478
Test name
Test status
Simulation time 305987875 ps
CPU time 37.53 seconds
Started Jul 29 07:53:16 PM PDT 24
Finished Jul 29 07:53:54 PM PDT 24
Peak memory 575760 kb
Host smart-b4336c2c-b03b-4e9f-a6e0-00460c523eff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208360888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2208360888
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_access_same_device.720077810
Short name T2131
Test name
Test status
Simulation time 1515760918 ps
CPU time 57.97 seconds
Started Jul 29 07:53:33 PM PDT 24
Finished Jul 29 07:54:31 PM PDT 24
Peak memory 576020 kb
Host smart-5ad3f3a0-dad0-4856-a8a3-50f904c61dee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720077810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.
720077810
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1411857230
Short name T852
Test name
Test status
Simulation time 27725432198 ps
CPU time 515.38 seconds
Started Jul 29 07:53:31 PM PDT 24
Finished Jul 29 08:02:06 PM PDT 24
Peak memory 575828 kb
Host smart-f101db8f-effb-4342-a5e3-8403f803a1ae
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411857230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_
device_slow_rsp.1411857230
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.4155728674
Short name T2574
Test name
Test status
Simulation time 201757309 ps
CPU time 24.16 seconds
Started Jul 29 07:53:31 PM PDT 24
Finished Jul 29 07:53:55 PM PDT 24
Peak memory 575796 kb
Host smart-b0746750-b398-4a13-99b8-350d53d88546
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155728674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add
r.4155728674
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_error_random.2600220297
Short name T2428
Test name
Test status
Simulation time 1402606021 ps
CPU time 42.15 seconds
Started Jul 29 07:53:31 PM PDT 24
Finished Jul 29 07:54:14 PM PDT 24
Peak memory 575884 kb
Host smart-eb19477d-f981-47b6-90d2-79fc9648d72a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600220297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2600220297
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random.2255114495
Short name T1716
Test name
Test status
Simulation time 633338201 ps
CPU time 24.92 seconds
Started Jul 29 07:53:22 PM PDT 24
Finished Jul 29 07:53:47 PM PDT 24
Peak memory 575920 kb
Host smart-8e815117-64dd-4366-bcbc-6a5812521df4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255114495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.2255114495
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.99212013
Short name T1864
Test name
Test status
Simulation time 79104183311 ps
CPU time 792.52 seconds
Started Jul 29 07:53:31 PM PDT 24
Finished Jul 29 08:06:44 PM PDT 24
Peak memory 575972 kb
Host smart-3fdb259b-12a8-4b75-8955-6868b1a22589
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99212013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.99212013
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.2757130810
Short name T2824
Test name
Test status
Simulation time 57853727892 ps
CPU time 999.86 seconds
Started Jul 29 07:53:32 PM PDT 24
Finished Jul 29 08:10:12 PM PDT 24
Peak memory 576832 kb
Host smart-c821bc38-3ed4-4104-84a8-1f6df5025ee1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757130810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2757130810
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.3233802856
Short name T1721
Test name
Test status
Simulation time 557128279 ps
CPU time 45.65 seconds
Started Jul 29 07:53:31 PM PDT 24
Finished Jul 29 07:54:17 PM PDT 24
Peak memory 575948 kb
Host smart-4e46c672-736f-45ec-b236-899b8a02e51a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233802856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del
ays.3233802856
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_same_source.4114386142
Short name T2905
Test name
Test status
Simulation time 118939041 ps
CPU time 11.19 seconds
Started Jul 29 07:53:31 PM PDT 24
Finished Jul 29 07:53:42 PM PDT 24
Peak memory 575896 kb
Host smart-78a31917-270e-4711-ace6-1b3f71bc82d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114386142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.4114386142
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke.4281453533
Short name T2818
Test name
Test status
Simulation time 141050866 ps
CPU time 7.2 seconds
Started Jul 29 07:53:21 PM PDT 24
Finished Jul 29 07:53:28 PM PDT 24
Peak memory 573896 kb
Host smart-9183f2b4-7e55-4707-98ba-16d5bc76c4e5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281453533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.4281453533
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.1975445965
Short name T2194
Test name
Test status
Simulation time 9200510180 ps
CPU time 92.1 seconds
Started Jul 29 07:53:22 PM PDT 24
Finished Jul 29 07:54:54 PM PDT 24
Peak memory 574632 kb
Host smart-dc3104cf-1c50-48e3-92cc-8062d8934a87
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975445965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1975445965
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.1856008860
Short name T669
Test name
Test status
Simulation time 4150666382 ps
CPU time 68.22 seconds
Started Jul 29 07:53:22 PM PDT 24
Finished Jul 29 07:54:31 PM PDT 24
Peak memory 574588 kb
Host smart-b869d486-3596-40a3-9bdc-ca52bbc62342
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856008860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1856008860
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.1493912754
Short name T1749
Test name
Test status
Simulation time 48973368 ps
CPU time 6.2 seconds
Started Jul 29 07:53:21 PM PDT 24
Finished Jul 29 07:53:28 PM PDT 24
Peak memory 574008 kb
Host smart-3dc94dc9-5901-4a47-b195-854ffcb7d7de
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493912754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delay
s.1493912754
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all.3503731998
Short name T498
Test name
Test status
Simulation time 1683465217 ps
CPU time 133.08 seconds
Started Jul 29 07:53:35 PM PDT 24
Finished Jul 29 07:55:48 PM PDT 24
Peak memory 575968 kb
Host smart-88088b5a-5122-40cf-8a5c-ebb7e63d5228
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503731998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3503731998
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.1170053421
Short name T2357
Test name
Test status
Simulation time 3706749832 ps
CPU time 286.27 seconds
Started Jul 29 07:53:35 PM PDT 24
Finished Jul 29 07:58:22 PM PDT 24
Peak memory 576804 kb
Host smart-a65fabe4-cf65-4e47-a472-13cf8867a5e8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170053421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1170053421
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.2029484426
Short name T1722
Test name
Test status
Simulation time 1243712473 ps
CPU time 288.87 seconds
Started Jul 29 07:53:35 PM PDT 24
Finished Jul 29 07:58:24 PM PDT 24
Peak memory 576824 kb
Host smart-c0bbe351-def7-4bf1-beb8-6b0dffa3b184
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029484426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all
_with_rand_reset.2029484426
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.4084444075
Short name T1967
Test name
Test status
Simulation time 13274025086 ps
CPU time 601.43 seconds
Started Jul 29 07:54:01 PM PDT 24
Finished Jul 29 08:04:02 PM PDT 24
Peak memory 576824 kb
Host smart-740ce91e-8d54-4cca-8c49-53e5b0557f13
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084444075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al
l_with_reset_error.4084444075
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.998095012
Short name T2361
Test name
Test status
Simulation time 226441503 ps
CPU time 27.59 seconds
Started Jul 29 07:53:32 PM PDT 24
Finished Jul 29 07:53:59 PM PDT 24
Peak memory 575864 kb
Host smart-edebee07-dd22-4138-bdea-eec56ed9903b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998095012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.998095012
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/25.chip_tl_errors.2937131344
Short name T735
Test name
Test status
Simulation time 4804133328 ps
CPU time 382.13 seconds
Started Jul 29 07:53:58 PM PDT 24
Finished Jul 29 08:00:20 PM PDT 24
Peak memory 598616 kb
Host smart-65856d36-b63b-48c5-84ee-23c7f9346892
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937131344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.2937131344
Directory /workspace/25.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_access_same_device.598080572
Short name T870
Test name
Test status
Simulation time 1140018903 ps
CPU time 45.03 seconds
Started Jul 29 07:53:57 PM PDT 24
Finished Jul 29 07:54:42 PM PDT 24
Peak memory 576040 kb
Host smart-164c226d-391a-4e14-ab65-8f9c5a50a0c4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598080572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.
598080572
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.2496759637
Short name T2452
Test name
Test status
Simulation time 19360441851 ps
CPU time 347.15 seconds
Started Jul 29 07:53:56 PM PDT 24
Finished Jul 29 07:59:43 PM PDT 24
Peak memory 576004 kb
Host smart-eae1d1d5-701f-4acd-9c8e-5f3555950f54
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496759637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_
device_slow_rsp.2496759637
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.2301685684
Short name T1580
Test name
Test status
Simulation time 1389058354 ps
CPU time 54.16 seconds
Started Jul 29 07:54:02 PM PDT 24
Finished Jul 29 07:54:57 PM PDT 24
Peak memory 576148 kb
Host smart-e1c8fd0e-500a-452b-a7ad-4801e1417608
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301685684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add
r.2301685684
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_error_random.314115484
Short name T2247
Test name
Test status
Simulation time 100969520 ps
CPU time 11.69 seconds
Started Jul 29 07:53:57 PM PDT 24
Finished Jul 29 07:54:08 PM PDT 24
Peak memory 576008 kb
Host smart-d03110f7-38ce-49cf-a9c1-18b98c9fc7c5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314115484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.314115484
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random.3076639350
Short name T1959
Test name
Test status
Simulation time 340038239 ps
CPU time 15.05 seconds
Started Jul 29 07:54:01 PM PDT 24
Finished Jul 29 07:54:16 PM PDT 24
Peak memory 575584 kb
Host smart-01da0f47-63c6-4dc0-a488-780e46243c74
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076639350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.3076639350
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.1921737173
Short name T2140
Test name
Test status
Simulation time 23110197767 ps
CPU time 234.64 seconds
Started Jul 29 07:53:55 PM PDT 24
Finished Jul 29 07:57:50 PM PDT 24
Peak memory 575988 kb
Host smart-af49ec4a-f2a8-435e-8461-ec61f7027183
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921737173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1921737173
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.1447485932
Short name T2209
Test name
Test status
Simulation time 7526115419 ps
CPU time 128.91 seconds
Started Jul 29 07:54:01 PM PDT 24
Finished Jul 29 07:56:10 PM PDT 24
Peak memory 575980 kb
Host smart-8a79307b-d5de-4823-8854-56a703058bb6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447485932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1447485932
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.1259690023
Short name T1876
Test name
Test status
Simulation time 142357861 ps
CPU time 14.91 seconds
Started Jul 29 07:53:56 PM PDT 24
Finished Jul 29 07:54:11 PM PDT 24
Peak memory 576008 kb
Host smart-6b8db0df-d11d-4cde-8c67-2dd012cec9e5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259690023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del
ays.1259690023
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_same_source.742768822
Short name T2750
Test name
Test status
Simulation time 153976347 ps
CPU time 13.83 seconds
Started Jul 29 07:53:59 PM PDT 24
Finished Jul 29 07:54:13 PM PDT 24
Peak memory 575816 kb
Host smart-3c25e10e-d1eb-48ea-b836-1cdcf735580b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742768822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.742768822
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke.29995963
Short name T2031
Test name
Test status
Simulation time 182646701 ps
CPU time 8.78 seconds
Started Jul 29 07:53:57 PM PDT 24
Finished Jul 29 07:54:06 PM PDT 24
Peak memory 573720 kb
Host smart-7405a168-8cd5-4b56-a6e5-9c0c6d665c99
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29995963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.29995963
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.3603313967
Short name T1522
Test name
Test status
Simulation time 10399440211 ps
CPU time 107.57 seconds
Started Jul 29 07:53:56 PM PDT 24
Finished Jul 29 07:55:44 PM PDT 24
Peak memory 574676 kb
Host smart-095549aa-e4aa-423d-bb1e-6da8d632327e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603313967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3603313967
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.2343810599
Short name T2416
Test name
Test status
Simulation time 5332455326 ps
CPU time 87.71 seconds
Started Jul 29 07:53:57 PM PDT 24
Finished Jul 29 07:55:25 PM PDT 24
Peak memory 574620 kb
Host smart-e0505474-3db9-4a34-8337-702e3dcb589a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343810599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2343810599
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.2220060588
Short name T2924
Test name
Test status
Simulation time 51492098 ps
CPU time 6.82 seconds
Started Jul 29 07:53:59 PM PDT 24
Finished Jul 29 07:54:06 PM PDT 24
Peak memory 573860 kb
Host smart-fc5a49c9-6945-42ca-b9d3-15d2ffeabf36
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220060588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay
s.2220060588
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all.240998760
Short name T2881
Test name
Test status
Simulation time 998557736 ps
CPU time 35.42 seconds
Started Jul 29 07:53:58 PM PDT 24
Finished Jul 29 07:54:34 PM PDT 24
Peak memory 576044 kb
Host smart-46bff63b-0c19-40b2-b01a-2d010bb9e7a6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240998760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.240998760
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.3735864633
Short name T2047
Test name
Test status
Simulation time 11439986202 ps
CPU time 383.44 seconds
Started Jul 29 07:53:57 PM PDT 24
Finished Jul 29 08:00:20 PM PDT 24
Peak memory 576824 kb
Host smart-17463481-f62f-4586-884f-7013bae97dc4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735864633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3735864633
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1533309987
Short name T1881
Test name
Test status
Simulation time 295540425 ps
CPU time 110.58 seconds
Started Jul 29 07:53:57 PM PDT 24
Finished Jul 29 07:55:47 PM PDT 24
Peak memory 576836 kb
Host smart-436052ed-0149-4d28-8690-79ff1c565ad3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533309987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all
_with_rand_reset.1533309987
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.3078725866
Short name T2537
Test name
Test status
Simulation time 329256072 ps
CPU time 40.33 seconds
Started Jul 29 07:53:59 PM PDT 24
Finished Jul 29 07:54:39 PM PDT 24
Peak memory 576048 kb
Host smart-ecefffae-668c-4b2e-8444-439a5dd89e6f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078725866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3078725866
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/26.chip_tl_errors.2256228077
Short name T557
Test name
Test status
Simulation time 2628881407 ps
CPU time 147.75 seconds
Started Jul 29 07:53:57 PM PDT 24
Finished Jul 29 07:56:25 PM PDT 24
Peak memory 599704 kb
Host smart-b8fcc079-2bc7-4e04-8c0c-edae732ca0a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256228077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.2256228077
Directory /workspace/26.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_access_same_device.3611559338
Short name T1943
Test name
Test status
Simulation time 515850101 ps
CPU time 27.46 seconds
Started Jul 29 07:53:57 PM PDT 24
Finished Jul 29 07:54:24 PM PDT 24
Peak memory 575684 kb
Host smart-86dbf504-e2d9-481c-8a5b-894cc0d5fc53
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611559338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device
.3611559338
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.1986450766
Short name T1649
Test name
Test status
Simulation time 39409393463 ps
CPU time 663.16 seconds
Started Jul 29 07:54:01 PM PDT 24
Finished Jul 29 08:05:05 PM PDT 24
Peak memory 576064 kb
Host smart-ca4fd530-8937-418a-9d78-6d3baed1ef19
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986450766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_
device_slow_rsp.1986450766
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.1028867539
Short name T2891
Test name
Test status
Simulation time 884050468 ps
CPU time 36.62 seconds
Started Jul 29 07:54:01 PM PDT 24
Finished Jul 29 07:54:37 PM PDT 24
Peak memory 575760 kb
Host smart-18aacf55-0912-43e6-b4e3-6914977c37bb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028867539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add
r.1028867539
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_error_random.3589443962
Short name T1403
Test name
Test status
Simulation time 134900409 ps
CPU time 8.13 seconds
Started Jul 29 07:53:58 PM PDT 24
Finished Jul 29 07:54:06 PM PDT 24
Peak memory 573964 kb
Host smart-e6628bbc-735d-40b7-bf53-fedbe554dda1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589443962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3589443962
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random.1342434121
Short name T1613
Test name
Test status
Simulation time 450480297 ps
CPU time 19.17 seconds
Started Jul 29 07:54:01 PM PDT 24
Finished Jul 29 07:54:20 PM PDT 24
Peak memory 575928 kb
Host smart-4d240e84-3f4a-4224-bbc1-43a058ddd447
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342434121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.1342434121
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.3678400828
Short name T1566
Test name
Test status
Simulation time 34791944294 ps
CPU time 355.54 seconds
Started Jul 29 07:53:59 PM PDT 24
Finished Jul 29 07:59:54 PM PDT 24
Peak memory 576120 kb
Host smart-d9ee4dfc-3830-4b91-8395-8417b8c85878
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678400828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3678400828
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.3631659619
Short name T2673
Test name
Test status
Simulation time 52495204239 ps
CPU time 922.21 seconds
Started Jul 29 07:54:01 PM PDT 24
Finished Jul 29 08:09:24 PM PDT 24
Peak memory 576172 kb
Host smart-dbdfc3f6-0657-43e1-ab47-a3fbd1cc31b4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631659619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3631659619
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.662399095
Short name T2057
Test name
Test status
Simulation time 100501743 ps
CPU time 12.72 seconds
Started Jul 29 07:53:57 PM PDT 24
Finished Jul 29 07:54:10 PM PDT 24
Peak memory 575936 kb
Host smart-85d914c8-0ff0-4c96-8d12-3eb94d612f3e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662399095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_dela
ys.662399095
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_same_source.1249478928
Short name T2665
Test name
Test status
Simulation time 72663993 ps
CPU time 8.44 seconds
Started Jul 29 07:53:58 PM PDT 24
Finished Jul 29 07:54:07 PM PDT 24
Peak memory 575992 kb
Host smart-ac2a768f-0ffc-42c5-85cb-b53140755097
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249478928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1249478928
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke.1429499510
Short name T682
Test name
Test status
Simulation time 45785336 ps
CPU time 6.35 seconds
Started Jul 29 07:53:58 PM PDT 24
Finished Jul 29 07:54:04 PM PDT 24
Peak memory 574548 kb
Host smart-3202ed4e-04bd-4bb0-8138-47e5557b9641
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429499510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1429499510
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.3909738979
Short name T2907
Test name
Test status
Simulation time 8377249941 ps
CPU time 90.65 seconds
Started Jul 29 07:54:01 PM PDT 24
Finished Jul 29 07:55:32 PM PDT 24
Peak memory 573672 kb
Host smart-bd07b049-16ee-40a6-87c9-3004f9b5242f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909738979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3909738979
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.2494102078
Short name T1671
Test name
Test status
Simulation time 5108408155 ps
CPU time 87.85 seconds
Started Jul 29 07:54:01 PM PDT 24
Finished Jul 29 07:55:29 PM PDT 24
Peak memory 573956 kb
Host smart-bf2b5a96-9a5e-4dfd-a8d7-ed6e3e9fee24
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494102078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.2494102078
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.2623912847
Short name T2145
Test name
Test status
Simulation time 40836744 ps
CPU time 6.36 seconds
Started Jul 29 07:53:56 PM PDT 24
Finished Jul 29 07:54:02 PM PDT 24
Peak memory 573880 kb
Host smart-4dea3732-4876-41d3-bc8a-47815a99dec2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623912847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay
s.2623912847
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all.3087162882
Short name T1954
Test name
Test status
Simulation time 14988956179 ps
CPU time 587.1 seconds
Started Jul 29 07:53:59 PM PDT 24
Finished Jul 29 08:03:46 PM PDT 24
Peak memory 575980 kb
Host smart-54a18dd5-d01a-4e0b-9a2f-2ef8b269aac6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087162882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3087162882
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.504913076
Short name T718
Test name
Test status
Simulation time 2973283834 ps
CPU time 202.72 seconds
Started Jul 29 07:53:59 PM PDT 24
Finished Jul 29 07:57:21 PM PDT 24
Peak memory 575996 kb
Host smart-3b82be1d-5c5c-4b56-a29d-ec2041639785
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504913076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.504913076
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2383916139
Short name T887
Test name
Test status
Simulation time 304606562 ps
CPU time 89.09 seconds
Started Jul 29 07:54:01 PM PDT 24
Finished Jul 29 07:55:30 PM PDT 24
Peak memory 576772 kb
Host smart-6d1a16e8-7609-468f-a808-bbf66f5cd468
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383916139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all
_with_rand_reset.2383916139
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3825922040
Short name T2670
Test name
Test status
Simulation time 139032564 ps
CPU time 72.68 seconds
Started Jul 29 07:53:59 PM PDT 24
Finished Jul 29 07:55:11 PM PDT 24
Peak memory 576728 kb
Host smart-4d92d098-c775-4f00-8224-532aecf1ad57
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825922040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al
l_with_reset_error.3825922040
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.4156718091
Short name T1616
Test name
Test status
Simulation time 239107177 ps
CPU time 31.36 seconds
Started Jul 29 07:53:59 PM PDT 24
Finished Jul 29 07:54:30 PM PDT 24
Peak memory 576068 kb
Host smart-781383b6-80a6-4654-b401-ee7576a583c0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156718091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.4156718091
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_access_same_device.605045811
Short name T1565
Test name
Test status
Simulation time 559735233 ps
CPU time 45.31 seconds
Started Jul 29 07:54:09 PM PDT 24
Finished Jul 29 07:54:54 PM PDT 24
Peak memory 576012 kb
Host smart-1cf1d69a-1aed-4719-9f45-a6fd9d62a13b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605045811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.
605045811
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.990157354
Short name T1638
Test name
Test status
Simulation time 80517282920 ps
CPU time 1382.19 seconds
Started Jul 29 07:54:12 PM PDT 24
Finished Jul 29 08:17:14 PM PDT 24
Peak memory 576080 kb
Host smart-09e29f19-2ef1-49b1-8c9b-d0ff3d4c52b4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990157354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_d
evice_slow_rsp.990157354
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.1237690593
Short name T2379
Test name
Test status
Simulation time 1309894608 ps
CPU time 48.09 seconds
Started Jul 29 07:54:16 PM PDT 24
Finished Jul 29 07:55:04 PM PDT 24
Peak memory 576032 kb
Host smart-2868f468-12b9-47f1-8eeb-7f4194bf4697
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237690593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add
r.1237690593
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_error_random.3225252458
Short name T2899
Test name
Test status
Simulation time 105034549 ps
CPU time 10.45 seconds
Started Jul 29 07:54:10 PM PDT 24
Finished Jul 29 07:54:20 PM PDT 24
Peak memory 575820 kb
Host smart-ea711e00-fe50-4c78-a5ed-46bed5678a2d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225252458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3225252458
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random.965369619
Short name T2186
Test name
Test status
Simulation time 1972762554 ps
CPU time 66.05 seconds
Started Jul 29 07:54:07 PM PDT 24
Finished Jul 29 07:55:13 PM PDT 24
Peak memory 576016 kb
Host smart-523aa985-0b6d-4d34-96c8-ee765960ce29
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965369619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.965369619
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.2485219595
Short name T610
Test name
Test status
Simulation time 63096482607 ps
CPU time 650.82 seconds
Started Jul 29 07:54:13 PM PDT 24
Finished Jul 29 08:05:04 PM PDT 24
Peak memory 575904 kb
Host smart-02865aaf-9203-4c31-a654-9b0567726fd5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485219595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2485219595
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.170625557
Short name T635
Test name
Test status
Simulation time 19356798404 ps
CPU time 315.5 seconds
Started Jul 29 07:54:13 PM PDT 24
Finished Jul 29 07:59:28 PM PDT 24
Peak memory 576120 kb
Host smart-3dd8128c-0ada-45b4-8c02-b7c0860c6793
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170625557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.170625557
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.2567959017
Short name T1935
Test name
Test status
Simulation time 360233949 ps
CPU time 34.86 seconds
Started Jul 29 07:54:08 PM PDT 24
Finished Jul 29 07:54:44 PM PDT 24
Peak memory 575880 kb
Host smart-a1c47451-7625-4395-a9e0-8c71040dd18d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567959017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del
ays.2567959017
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_same_source.1718916434
Short name T2874
Test name
Test status
Simulation time 321085953 ps
CPU time 24.65 seconds
Started Jul 29 07:54:07 PM PDT 24
Finished Jul 29 07:54:32 PM PDT 24
Peak memory 575948 kb
Host smart-9e6ae543-da31-4db3-858b-89d89b2bfccc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718916434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1718916434
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke.2544956952
Short name T2483
Test name
Test status
Simulation time 40382096 ps
CPU time 5.98 seconds
Started Jul 29 07:54:07 PM PDT 24
Finished Jul 29 07:54:13 PM PDT 24
Peak memory 574552 kb
Host smart-ca6e3602-ea11-437d-bb74-e9d75624267a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544956952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2544956952
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.1100355085
Short name T2879
Test name
Test status
Simulation time 6280869850 ps
CPU time 65.22 seconds
Started Jul 29 07:54:08 PM PDT 24
Finished Jul 29 07:55:13 PM PDT 24
Peak memory 573964 kb
Host smart-ff911a13-1102-4fea-8f01-2f0cc82c0a28
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100355085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1100355085
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.2428699807
Short name T1691
Test name
Test status
Simulation time 3209660228 ps
CPU time 52.43 seconds
Started Jul 29 07:54:14 PM PDT 24
Finished Jul 29 07:55:06 PM PDT 24
Peak memory 574648 kb
Host smart-80383de0-ba95-4118-a12d-71ce4859f1e2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428699807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2428699807
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.1311844383
Short name T1440
Test name
Test status
Simulation time 45949634 ps
CPU time 6.54 seconds
Started Jul 29 07:54:08 PM PDT 24
Finished Jul 29 07:54:15 PM PDT 24
Peak memory 573772 kb
Host smart-1b6efc89-983d-4fe1-9f6e-fcfc02483099
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311844383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay
s.1311844383
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all.2193326293
Short name T2091
Test name
Test status
Simulation time 1607094229 ps
CPU time 139.97 seconds
Started Jul 29 07:54:17 PM PDT 24
Finished Jul 29 07:56:37 PM PDT 24
Peak memory 576772 kb
Host smart-fe81f2db-6f5e-4f3e-9bc6-a58f13279ac2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193326293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2193326293
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.3427655871
Short name T695
Test name
Test status
Simulation time 2013627019 ps
CPU time 146.01 seconds
Started Jul 29 07:54:17 PM PDT 24
Finished Jul 29 07:56:43 PM PDT 24
Peak memory 576044 kb
Host smart-4b82ca37-755a-458c-96f2-ff6a76e96451
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427655871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3427655871
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.2355610681
Short name T1739
Test name
Test status
Simulation time 2280508013 ps
CPU time 316.21 seconds
Started Jul 29 07:54:17 PM PDT 24
Finished Jul 29 07:59:33 PM PDT 24
Peak memory 576024 kb
Host smart-cf7c8996-dccb-483b-9c0b-80e858f6bde4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355610681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all
_with_rand_reset.2355610681
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.1634723202
Short name T2279
Test name
Test status
Simulation time 6212204851 ps
CPU time 622.38 seconds
Started Jul 29 07:54:16 PM PDT 24
Finished Jul 29 08:04:39 PM PDT 24
Peak memory 576040 kb
Host smart-c0e7fa94-4556-4c75-966d-fe2ad6047ee4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634723202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al
l_with_reset_error.1634723202
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.2218198847
Short name T2017
Test name
Test status
Simulation time 284007268 ps
CPU time 38.28 seconds
Started Jul 29 07:54:15 PM PDT 24
Finished Jul 29 07:54:53 PM PDT 24
Peak memory 575892 kb
Host smart-af2ef01f-5850-4487-a3b7-525157daea7c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218198847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2218198847
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/28.chip_tl_errors.2570616511
Short name T712
Test name
Test status
Simulation time 2900759391 ps
CPU time 153.63 seconds
Started Jul 29 07:54:18 PM PDT 24
Finished Jul 29 07:56:52 PM PDT 24
Peak memory 603796 kb
Host smart-cba341a4-2dc8-4d4b-a396-b13ff086cbca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570616511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.2570616511
Directory /workspace/28.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_access_same_device.2776965575
Short name T612
Test name
Test status
Simulation time 2852149406 ps
CPU time 102.05 seconds
Started Jul 29 07:54:17 PM PDT 24
Finished Jul 29 07:55:59 PM PDT 24
Peak memory 576108 kb
Host smart-31216465-7c0b-4929-ad2a-8ce0b5bbccdd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776965575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device
.2776965575
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.1948621733
Short name T2448
Test name
Test status
Simulation time 126843332142 ps
CPU time 2292.32 seconds
Started Jul 29 07:54:15 PM PDT 24
Finished Jul 29 08:32:28 PM PDT 24
Peak memory 576032 kb
Host smart-2cf88f4f-43fe-4eee-93cd-eda9fa5e4f62
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948621733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_
device_slow_rsp.1948621733
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.675647586
Short name T1495
Test name
Test status
Simulation time 80467067 ps
CPU time 11.26 seconds
Started Jul 29 07:54:27 PM PDT 24
Finished Jul 29 07:54:39 PM PDT 24
Peak memory 575752 kb
Host smart-b49cf331-32ab-4121-9b8f-328751261388
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675647586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr
.675647586
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_error_random.1630929956
Short name T1582
Test name
Test status
Simulation time 1526907590 ps
CPU time 53.5 seconds
Started Jul 29 07:54:30 PM PDT 24
Finished Jul 29 07:55:24 PM PDT 24
Peak memory 576020 kb
Host smart-cc1f3d30-bc18-40f9-b33e-a42eff818917
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630929956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1630929956
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random.883986194
Short name T2415
Test name
Test status
Simulation time 549109377 ps
CPU time 49.67 seconds
Started Jul 29 07:54:15 PM PDT 24
Finished Jul 29 07:55:05 PM PDT 24
Peak memory 575832 kb
Host smart-675d6802-095f-4623-9bd1-b116b0210344
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883986194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.883986194
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.1131562683
Short name T2653
Test name
Test status
Simulation time 40096855739 ps
CPU time 413.76 seconds
Started Jul 29 07:54:19 PM PDT 24
Finished Jul 29 08:01:13 PM PDT 24
Peak memory 576112 kb
Host smart-6be60cfe-df72-4308-ad2f-81b51d40ced2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131562683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1131562683
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.4226725832
Short name T2491
Test name
Test status
Simulation time 9804456820 ps
CPU time 160.72 seconds
Started Jul 29 07:54:16 PM PDT 24
Finished Jul 29 07:56:57 PM PDT 24
Peak memory 575996 kb
Host smart-c5db9f27-60b3-49d5-9aa2-87c37a22cb1a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226725832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.4226725832
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.2561427350
Short name T668
Test name
Test status
Simulation time 240935640 ps
CPU time 24.38 seconds
Started Jul 29 07:54:16 PM PDT 24
Finished Jul 29 07:54:40 PM PDT 24
Peak memory 575880 kb
Host smart-7fe61201-2f52-436a-958c-25f4ffe07a4c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561427350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del
ays.2561427350
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_same_source.439325463
Short name T2106
Test name
Test status
Simulation time 1918200595 ps
CPU time 53.84 seconds
Started Jul 29 07:54:18 PM PDT 24
Finished Jul 29 07:55:12 PM PDT 24
Peak memory 575968 kb
Host smart-8469d104-b668-4783-be11-15668c192df1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439325463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.439325463
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke.3448968313
Short name T2382
Test name
Test status
Simulation time 210829422 ps
CPU time 9.04 seconds
Started Jul 29 07:54:17 PM PDT 24
Finished Jul 29 07:54:26 PM PDT 24
Peak memory 574560 kb
Host smart-9674ea01-b20c-4119-aa58-b3dd38b6e6cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448968313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3448968313
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.2607792711
Short name T1838
Test name
Test status
Simulation time 8207168221 ps
CPU time 81.7 seconds
Started Jul 29 07:54:16 PM PDT 24
Finished Jul 29 07:55:38 PM PDT 24
Peak memory 574620 kb
Host smart-6a3bf01b-723a-436c-bc2b-3fdcd1c52655
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607792711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2607792711
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3739166940
Short name T2003
Test name
Test status
Simulation time 4205546452 ps
CPU time 76.19 seconds
Started Jul 29 07:54:18 PM PDT 24
Finished Jul 29 07:55:35 PM PDT 24
Peak memory 573892 kb
Host smart-600641f4-3a11-4981-9870-d7bbe552e625
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739166940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3739166940
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.120538259
Short name T1430
Test name
Test status
Simulation time 46931873 ps
CPU time 6.33 seconds
Started Jul 29 07:54:17 PM PDT 24
Finished Jul 29 07:54:24 PM PDT 24
Peak memory 573872 kb
Host smart-f89bfcb5-f5dc-4a58-bbc4-28024d75e3a8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120538259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays
.120538259
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all.941669251
Short name T595
Test name
Test status
Simulation time 7591101987 ps
CPU time 307.93 seconds
Started Jul 29 07:54:28 PM PDT 24
Finished Jul 29 07:59:36 PM PDT 24
Peak memory 576008 kb
Host smart-a16994ac-8fc0-4952-b85e-abed0f5c0c17
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941669251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.941669251
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.2349808144
Short name T714
Test name
Test status
Simulation time 744610086 ps
CPU time 61.32 seconds
Started Jul 29 07:54:26 PM PDT 24
Finished Jul 29 07:55:28 PM PDT 24
Peak memory 576084 kb
Host smart-ac71e840-88a0-48d8-b051-878530106048
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349808144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2349808144
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1536928109
Short name T2918
Test name
Test status
Simulation time 2311722590 ps
CPU time 263.18 seconds
Started Jul 29 07:54:28 PM PDT 24
Finished Jul 29 07:58:51 PM PDT 24
Peak memory 576024 kb
Host smart-df064f34-85ae-4583-91de-61198ffb24fd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536928109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all
_with_rand_reset.1536928109
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.629801604
Short name T2682
Test name
Test status
Simulation time 4959708106 ps
CPU time 566.73 seconds
Started Jul 29 07:54:28 PM PDT 24
Finished Jul 29 08:03:55 PM PDT 24
Peak memory 576868 kb
Host smart-c1a4140d-b584-43d4-ae71-889a620b1e80
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629801604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all
_with_reset_error.629801604
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.1571899143
Short name T2264
Test name
Test status
Simulation time 145731436 ps
CPU time 16.8 seconds
Started Jul 29 07:54:25 PM PDT 24
Finished Jul 29 07:54:42 PM PDT 24
Peak memory 575988 kb
Host smart-9ed0103b-358f-4947-b41d-a99210ac43ec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571899143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1571899143
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/29.chip_tl_errors.996264164
Short name T734
Test name
Test status
Simulation time 3932952238 ps
CPU time 162.52 seconds
Started Jul 29 07:54:27 PM PDT 24
Finished Jul 29 07:57:10 PM PDT 24
Peak memory 599672 kb
Host smart-1225a0f3-fdf8-46e8-8ef3-3c63aae07228
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996264164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.996264164
Directory /workspace/29.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_access_same_device.3352177908
Short name T2141
Test name
Test status
Simulation time 137753745 ps
CPU time 11.9 seconds
Started Jul 29 07:54:36 PM PDT 24
Finished Jul 29 07:54:48 PM PDT 24
Peak memory 575920 kb
Host smart-e5207f0d-b6d2-4efe-9a8c-59b1ae89fb8c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352177908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device
.3352177908
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.1557093511
Short name T1401
Test name
Test status
Simulation time 1120139441 ps
CPU time 45.55 seconds
Started Jul 29 07:54:39 PM PDT 24
Finished Jul 29 07:55:25 PM PDT 24
Peak memory 576032 kb
Host smart-17e73add-47c3-4c54-89cb-110811660bcf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557093511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add
r.1557093511
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_error_random.3499916249
Short name T1981
Test name
Test status
Simulation time 923750043 ps
CPU time 29.84 seconds
Started Jul 29 07:54:40 PM PDT 24
Finished Jul 29 07:55:09 PM PDT 24
Peak memory 575944 kb
Host smart-272cc91c-4bbc-46ce-8ff3-5fbb6c4bb878
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499916249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3499916249
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random.2031089487
Short name T697
Test name
Test status
Simulation time 2026072588 ps
CPU time 76.46 seconds
Started Jul 29 07:54:29 PM PDT 24
Finished Jul 29 07:55:46 PM PDT 24
Peak memory 575856 kb
Host smart-962e741c-294b-48b5-970b-f0540a9f88db
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031089487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.2031089487
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.1015413509
Short name T2266
Test name
Test status
Simulation time 63162766779 ps
CPU time 644.83 seconds
Started Jul 29 07:54:41 PM PDT 24
Finished Jul 29 08:05:26 PM PDT 24
Peak memory 575920 kb
Host smart-eca28615-a31a-4d39-a549-8961d1b20443
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015413509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1015413509
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.1159064558
Short name T2886
Test name
Test status
Simulation time 56708685979 ps
CPU time 1032.97 seconds
Started Jul 29 07:54:38 PM PDT 24
Finished Jul 29 08:11:51 PM PDT 24
Peak memory 576080 kb
Host smart-53c049e5-bad2-451c-ab2f-a05f9c9069d9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159064558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1159064558
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.2807287095
Short name T2707
Test name
Test status
Simulation time 516427177 ps
CPU time 42.76 seconds
Started Jul 29 07:54:27 PM PDT 24
Finished Jul 29 07:55:10 PM PDT 24
Peak memory 575940 kb
Host smart-f122e725-c5f6-495d-8450-6c85e05c79db
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807287095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del
ays.2807287095
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_same_source.413839773
Short name T1746
Test name
Test status
Simulation time 493375862 ps
CPU time 38.75 seconds
Started Jul 29 07:54:39 PM PDT 24
Finished Jul 29 07:55:18 PM PDT 24
Peak memory 575872 kb
Host smart-507e9cd7-6a4a-46d2-a3f4-fc45ba6ce317
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413839773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.413839773
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke.235033643
Short name T2654
Test name
Test status
Simulation time 42103851 ps
CPU time 6.03 seconds
Started Jul 29 07:54:29 PM PDT 24
Finished Jul 29 07:54:35 PM PDT 24
Peak memory 574436 kb
Host smart-859f1bc4-347b-4bd1-9244-2c01564a1810
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235033643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.235033643
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.2717173012
Short name T2451
Test name
Test status
Simulation time 6615522425 ps
CPU time 66.58 seconds
Started Jul 29 07:54:29 PM PDT 24
Finished Jul 29 07:55:35 PM PDT 24
Peak memory 573988 kb
Host smart-7791a312-e242-44d5-8a53-a94f52f5dc40
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717173012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2717173012
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.1896480319
Short name T1911
Test name
Test status
Simulation time 5026086122 ps
CPU time 82.5 seconds
Started Jul 29 07:54:27 PM PDT 24
Finished Jul 29 07:55:50 PM PDT 24
Peak memory 573764 kb
Host smart-02a9f5c5-44eb-4e8f-a3f6-a91a78af9aeb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896480319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1896480319
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.3679351371
Short name T1446
Test name
Test status
Simulation time 45753941 ps
CPU time 6.14 seconds
Started Jul 29 07:54:28 PM PDT 24
Finished Jul 29 07:54:34 PM PDT 24
Peak memory 574544 kb
Host smart-177069ef-0fc5-446a-853f-023c0a0df846
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679351371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay
s.3679351371
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all.4174617036
Short name T1731
Test name
Test status
Simulation time 8220169415 ps
CPU time 315.61 seconds
Started Jul 29 07:54:38 PM PDT 24
Finished Jul 29 07:59:54 PM PDT 24
Peak memory 576836 kb
Host smart-61a3f046-48e1-46c7-9a6f-04ff854f8798
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174617036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.4174617036
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.1809174779
Short name T1413
Test name
Test status
Simulation time 3569589452 ps
CPU time 272.07 seconds
Started Jul 29 07:54:38 PM PDT 24
Finished Jul 29 07:59:10 PM PDT 24
Peak memory 575964 kb
Host smart-8ff169dd-f8f1-4644-a835-fcd267de95f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809174779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1809174779
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.267732245
Short name T889
Test name
Test status
Simulation time 6485557780 ps
CPU time 303.49 seconds
Started Jul 29 07:54:37 PM PDT 24
Finished Jul 29 07:59:41 PM PDT 24
Peak memory 575968 kb
Host smart-ad2c8d1d-6736-4131-9670-9813ba4fdebe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267732245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all
_with_reset_error.267732245
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.462859694
Short name T1968
Test name
Test status
Simulation time 71403979 ps
CPU time 6.1 seconds
Started Jul 29 07:54:39 PM PDT 24
Finished Jul 29 07:54:45 PM PDT 24
Peak memory 573928 kb
Host smart-f48c7e64-a326-4095-8294-4cea2e40471a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462859694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.462859694
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.1538749760
Short name T2066
Test name
Test status
Simulation time 37221116269 ps
CPU time 7689.32 seconds
Started Jul 29 07:49:51 PM PDT 24
Finished Jul 29 09:58:02 PM PDT 24
Peak memory 594188 kb
Host smart-b3a19050-ceb8-4bbd-8719-95fa30c87ea2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538749760 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.chip_csr_aliasing.1538749760
Directory /workspace/3.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.1082791813
Short name T2170
Test name
Test status
Simulation time 4021320480 ps
CPU time 367.22 seconds
Started Jul 29 07:49:50 PM PDT 24
Finished Jul 29 07:55:57 PM PDT 24
Peak memory 593300 kb
Host smart-0af2b916-8270-45db-a680-8a57924fcd3b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082791813 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.1082791813
Directory /workspace/3.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.3402959371
Short name T2696
Test name
Test status
Simulation time 10606782648 ps
CPU time 837.86 seconds
Started Jul 29 07:50:09 PM PDT 24
Finished Jul 29 08:04:07 PM PDT 24
Peak memory 649728 kb
Host smart-9dc81ba5-c837-459f-9f2e-5b1dca0747a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402959371 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.3402959371
Directory /workspace/3.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_rw.1078042963
Short name T1622
Test name
Test status
Simulation time 4185151308 ps
CPU time 264.28 seconds
Started Jul 29 07:49:59 PM PDT 24
Finished Jul 29 07:54:23 PM PDT 24
Peak memory 596884 kb
Host smart-2ac122d0-e2ba-4967-ac18-3e0fd5ef6729
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078042963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.1078042963
Directory /workspace/3.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.chip_tl_errors.2542740326
Short name T590
Test name
Test status
Simulation time 2874746853 ps
CPU time 148.61 seconds
Started Jul 29 07:50:04 PM PDT 24
Finished Jul 29 07:52:33 PM PDT 24
Peak memory 598716 kb
Host smart-f37568c8-196f-4679-9526-a085730c1cc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542740326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.2542740326
Directory /workspace/3.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_access_same_device.3844352493
Short name T2694
Test name
Test status
Simulation time 877285700 ps
CPU time 65.57 seconds
Started Jul 29 07:50:05 PM PDT 24
Finished Jul 29 07:51:11 PM PDT 24
Peak memory 575888 kb
Host smart-97792480-cfa5-4fc8-b8fb-d3dc468813f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844352493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.
3844352493
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3420494923
Short name T1952
Test name
Test status
Simulation time 83277403697 ps
CPU time 1353.32 seconds
Started Jul 29 07:50:04 PM PDT 24
Finished Jul 29 08:12:38 PM PDT 24
Peak memory 576176 kb
Host smart-1162a461-1313-47fa-8a31-91e6bcbcd1c3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420494923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d
evice_slow_rsp.3420494923
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.2998071415
Short name T2873
Test name
Test status
Simulation time 649298511 ps
CPU time 26.42 seconds
Started Jul 29 07:49:48 PM PDT 24
Finished Jul 29 07:50:15 PM PDT 24
Peak memory 575960 kb
Host smart-e2c72c44-3b51-4729-9a1f-bfaaa497ce78
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998071415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr
.2998071415
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_error_random.2976101850
Short name T2214
Test name
Test status
Simulation time 479808245 ps
CPU time 36.81 seconds
Started Jul 29 07:50:06 PM PDT 24
Finished Jul 29 07:50:43 PM PDT 24
Peak memory 575832 kb
Host smart-0d5b08e7-350c-4e2a-8548-8aba9794791d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976101850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2976101850
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random.2173163883
Short name T1496
Test name
Test status
Simulation time 265182981 ps
CPU time 22.98 seconds
Started Jul 29 07:49:50 PM PDT 24
Finished Jul 29 07:50:13 PM PDT 24
Peak memory 575840 kb
Host smart-0b898b57-0121-4024-9395-b827989044a9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173163883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.2173163883
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.2662775012
Short name T1757
Test name
Test status
Simulation time 106735689430 ps
CPU time 1171.04 seconds
Started Jul 29 07:50:05 PM PDT 24
Finished Jul 29 08:09:36 PM PDT 24
Peak memory 575860 kb
Host smart-bb7e4e9b-6001-4f19-a0ca-b1b4d1af246f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662775012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2662775012
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.4290759597
Short name T1973
Test name
Test status
Simulation time 37613205054 ps
CPU time 658.64 seconds
Started Jul 29 07:49:58 PM PDT 24
Finished Jul 29 08:00:57 PM PDT 24
Peak memory 575888 kb
Host smart-fb2fa31b-2917-4272-8048-46717bb7594d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290759597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.4290759597
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.4101321056
Short name T476
Test name
Test status
Simulation time 513365306 ps
CPU time 42.66 seconds
Started Jul 29 07:50:04 PM PDT 24
Finished Jul 29 07:50:47 PM PDT 24
Peak memory 575968 kb
Host smart-e9221f2f-a0a4-41fe-a2ad-2a54f46ddbe0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101321056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela
ys.4101321056
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_same_source.2134824064
Short name T2438
Test name
Test status
Simulation time 1632764022 ps
CPU time 46.14 seconds
Started Jul 29 07:50:05 PM PDT 24
Finished Jul 29 07:50:52 PM PDT 24
Peak memory 575868 kb
Host smart-943280a0-b28a-458c-bb65-9ad0209a8d34
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134824064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2134824064
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke.2399649572
Short name T1793
Test name
Test status
Simulation time 43534734 ps
CPU time 6.4 seconds
Started Jul 29 07:50:04 PM PDT 24
Finished Jul 29 07:50:11 PM PDT 24
Peak memory 573840 kb
Host smart-14fa222a-c212-4878-b7d8-4d84d10ca8d9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399649572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2399649572
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.4028116010
Short name T2439
Test name
Test status
Simulation time 8852044652 ps
CPU time 89.93 seconds
Started Jul 29 07:50:05 PM PDT 24
Finished Jul 29 07:51:35 PM PDT 24
Peak memory 573980 kb
Host smart-f6711750-0b0d-49bb-b056-4d33eeb24d80
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028116010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.4028116010
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2753913769
Short name T1709
Test name
Test status
Simulation time 6490375880 ps
CPU time 111.42 seconds
Started Jul 29 07:50:04 PM PDT 24
Finished Jul 29 07:51:56 PM PDT 24
Peak memory 573980 kb
Host smart-07bb75c6-1850-4660-a8f0-c3d36c52037d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753913769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2753913769
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.4277281693
Short name T1519
Test name
Test status
Simulation time 39720939 ps
CPU time 6.06 seconds
Started Jul 29 07:50:05 PM PDT 24
Finished Jul 29 07:50:11 PM PDT 24
Peak memory 573820 kb
Host smart-ca5acb49-58ae-4c0e-8bcb-833ed4c18e52
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277281693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays
.4277281693
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all.4255514842
Short name T2595
Test name
Test status
Simulation time 5592127633 ps
CPU time 206.35 seconds
Started Jul 29 07:50:05 PM PDT 24
Finished Jul 29 07:53:31 PM PDT 24
Peak memory 576096 kb
Host smart-08631216-2520-4d82-b589-b290de481723
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255514842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.4255514842
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.30941234
Short name T1844
Test name
Test status
Simulation time 7571594945 ps
CPU time 277.78 seconds
Started Jul 29 07:49:59 PM PDT 24
Finished Jul 29 07:54:37 PM PDT 24
Peak memory 576020 kb
Host smart-11f37a8f-0a54-4fa5-b341-a2108af81036
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30941234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.30941234
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.975102581
Short name T2117
Test name
Test status
Simulation time 10077101369 ps
CPU time 670.08 seconds
Started Jul 29 07:49:56 PM PDT 24
Finished Jul 29 08:01:07 PM PDT 24
Peak memory 576072 kb
Host smart-d7d91b37-3632-4264-8090-68cc19e8e9a8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975102581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_w
ith_rand_reset.975102581
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.3826235817
Short name T1865
Test name
Test status
Simulation time 160484405 ps
CPU time 38.93 seconds
Started Jul 29 07:49:58 PM PDT 24
Finished Jul 29 07:50:37 PM PDT 24
Peak memory 575940 kb
Host smart-a90db602-d9ef-4af6-b2f3-dd55308dac69
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826235817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all
_with_reset_error.3826235817
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.4281813056
Short name T2197
Test name
Test status
Simulation time 1023887832 ps
CPU time 41.45 seconds
Started Jul 29 07:50:05 PM PDT 24
Finished Jul 29 07:50:46 PM PDT 24
Peak memory 575788 kb
Host smart-735913d8-efec-4f8e-a0e6-f62a800ab253
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281813056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.4281813056
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_access_same_device.914589780
Short name T1463
Test name
Test status
Simulation time 69354283 ps
CPU time 7.78 seconds
Started Jul 29 07:54:50 PM PDT 24
Finished Jul 29 07:54:58 PM PDT 24
Peak memory 573720 kb
Host smart-f882c4cf-9cb3-4e15-906f-f8523c32d89f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914589780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.
914589780
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.4170284509
Short name T499
Test name
Test status
Simulation time 111200173080 ps
CPU time 1999.64 seconds
Started Jul 29 07:54:49 PM PDT 24
Finished Jul 29 08:28:09 PM PDT 24
Peak memory 576052 kb
Host smart-51fe546f-dea0-4b86-8950-418706019bc6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170284509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_
device_slow_rsp.4170284509
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.1562823111
Short name T2204
Test name
Test status
Simulation time 227780544 ps
CPU time 24.45 seconds
Started Jul 29 07:54:53 PM PDT 24
Finished Jul 29 07:55:17 PM PDT 24
Peak memory 575984 kb
Host smart-3a8d4a19-af12-417c-8086-4317bc4ed4b3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562823111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add
r.1562823111
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_error_random.3857323049
Short name T1457
Test name
Test status
Simulation time 239610443 ps
CPU time 23.08 seconds
Started Jul 29 07:54:49 PM PDT 24
Finished Jul 29 07:55:12 PM PDT 24
Peak memory 575952 kb
Host smart-ea67bebc-c13e-4949-97c7-625d1fa702ca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857323049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3857323049
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random.2009734279
Short name T1807
Test name
Test status
Simulation time 1547578045 ps
CPU time 53.68 seconds
Started Jul 29 07:54:39 PM PDT 24
Finished Jul 29 07:55:33 PM PDT 24
Peak memory 576088 kb
Host smart-2a9c9e7e-0253-4e7b-ad60-8ee2e6d443f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009734279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.2009734279
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.616965841
Short name T583
Test name
Test status
Simulation time 93807770180 ps
CPU time 1047.18 seconds
Started Jul 29 07:54:38 PM PDT 24
Finished Jul 29 08:12:06 PM PDT 24
Peak memory 576084 kb
Host smart-3a39e2ad-7d73-41d5-9389-a67cd51c0a0b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616965841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.616965841
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.1581706418
Short name T2287
Test name
Test status
Simulation time 62842531520 ps
CPU time 1105.27 seconds
Started Jul 29 07:54:51 PM PDT 24
Finished Jul 29 08:13:17 PM PDT 24
Peak memory 576156 kb
Host smart-4e75c109-9e57-455c-9323-13e20c6cd283
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581706418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1581706418
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.604805953
Short name T1878
Test name
Test status
Simulation time 592458472 ps
CPU time 53.88 seconds
Started Jul 29 07:54:38 PM PDT 24
Finished Jul 29 07:55:32 PM PDT 24
Peak memory 575964 kb
Host smart-4d10ef3c-5c9a-42e9-a35e-0fc0dd968bf9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604805953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_dela
ys.604805953
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_same_source.967905874
Short name T2285
Test name
Test status
Simulation time 1460923045 ps
CPU time 41.56 seconds
Started Jul 29 07:54:54 PM PDT 24
Finished Jul 29 07:55:35 PM PDT 24
Peak memory 575940 kb
Host smart-a403d634-056c-4472-964e-e20ba6fc258f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967905874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.967905874
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke.1678595084
Short name T1884
Test name
Test status
Simulation time 216712175 ps
CPU time 9.51 seconds
Started Jul 29 07:54:40 PM PDT 24
Finished Jul 29 07:54:50 PM PDT 24
Peak memory 573884 kb
Host smart-07593f6e-34bd-41b8-82d2-ae440221765b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678595084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1678595084
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.3040318838
Short name T2497
Test name
Test status
Simulation time 9552760573 ps
CPU time 91.79 seconds
Started Jul 29 07:54:41 PM PDT 24
Finished Jul 29 07:56:13 PM PDT 24
Peak memory 573932 kb
Host smart-693fd57f-b28e-482a-ac13-33ad705d951a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040318838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3040318838
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.2618267106
Short name T2746
Test name
Test status
Simulation time 3820655610 ps
CPU time 62.62 seconds
Started Jul 29 07:54:39 PM PDT 24
Finished Jul 29 07:55:42 PM PDT 24
Peak memory 574572 kb
Host smart-fd5fb74c-32e8-4ad6-9df5-8563b05c03b5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618267106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2618267106
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.1592115510
Short name T1539
Test name
Test status
Simulation time 45401318 ps
CPU time 6.29 seconds
Started Jul 29 07:54:41 PM PDT 24
Finished Jul 29 07:54:47 PM PDT 24
Peak memory 573880 kb
Host smart-5e8269e4-6fb9-4df2-8aee-817e29f40c3f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592115510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay
s.1592115510
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all.3134373316
Short name T2513
Test name
Test status
Simulation time 1289537536 ps
CPU time 55.98 seconds
Started Jul 29 07:54:48 PM PDT 24
Finished Jul 29 07:55:44 PM PDT 24
Peak memory 576172 kb
Host smart-e660b093-4c91-4b4e-8962-d7c14e1d6c65
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134373316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3134373316
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.3630570271
Short name T1743
Test name
Test status
Simulation time 4500149439 ps
CPU time 361.24 seconds
Started Jul 29 07:54:51 PM PDT 24
Finished Jul 29 08:00:52 PM PDT 24
Peak memory 577008 kb
Host smart-d809a10b-4493-4c04-915e-e79ff02b6469
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630570271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3630570271
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.2459695020
Short name T881
Test name
Test status
Simulation time 309233860 ps
CPU time 162.64 seconds
Started Jul 29 07:54:54 PM PDT 24
Finished Jul 29 07:57:36 PM PDT 24
Peak memory 576776 kb
Host smart-ab54501a-ac15-4f20-a8e1-0126d254a423
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459695020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all
_with_rand_reset.2459695020
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.64618007
Short name T2372
Test name
Test status
Simulation time 2106895866 ps
CPU time 243 seconds
Started Jul 29 07:54:54 PM PDT 24
Finished Jul 29 07:58:57 PM PDT 24
Peak memory 576684 kb
Host smart-9bce52d2-675f-4dc4-b6f6-2d1a6feeac4e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64618007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_
with_reset_error.64618007
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.2802338757
Short name T1625
Test name
Test status
Simulation time 1273399515 ps
CPU time 53.31 seconds
Started Jul 29 07:54:53 PM PDT 24
Finished Jul 29 07:55:47 PM PDT 24
Peak memory 576056 kb
Host smart-adec05b1-97eb-4cc5-9c63-bcd37efb7eec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802338757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2802338757
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_access_same_device.1782577892
Short name T2353
Test name
Test status
Simulation time 323374262 ps
CPU time 15.02 seconds
Started Jul 29 07:54:59 PM PDT 24
Finished Jul 29 07:55:14 PM PDT 24
Peak memory 575816 kb
Host smart-98bafabb-67c1-42ae-aa48-40241836093a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782577892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device
.1782577892
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.1204616743
Short name T1817
Test name
Test status
Simulation time 32386158964 ps
CPU time 552.73 seconds
Started Jul 29 07:55:01 PM PDT 24
Finished Jul 29 08:04:14 PM PDT 24
Peak memory 576192 kb
Host smart-78505ea8-ad8c-44dd-a3ee-15088e2b2ed1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204616743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_
device_slow_rsp.1204616743
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.2776248207
Short name T1542
Test name
Test status
Simulation time 262568893 ps
CPU time 29.2 seconds
Started Jul 29 07:55:00 PM PDT 24
Finished Jul 29 07:55:29 PM PDT 24
Peak memory 576008 kb
Host smart-b12da140-144a-45ec-bdb5-05390c809c0e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776248207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add
r.2776248207
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_error_random.2087820384
Short name T2561
Test name
Test status
Simulation time 252545824 ps
CPU time 21.75 seconds
Started Jul 29 07:54:59 PM PDT 24
Finished Jul 29 07:55:21 PM PDT 24
Peak memory 575884 kb
Host smart-5f126e93-91a0-4cac-91a0-d93e94b852a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087820384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2087820384
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random.3358339623
Short name T2234
Test name
Test status
Simulation time 2358741476 ps
CPU time 73.76 seconds
Started Jul 29 07:54:47 PM PDT 24
Finished Jul 29 07:56:01 PM PDT 24
Peak memory 575984 kb
Host smart-b65d1b38-b294-4f83-999a-c2cefcc2c5e9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358339623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.3358339623
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.4133598369
Short name T2299
Test name
Test status
Simulation time 49576867134 ps
CPU time 510.63 seconds
Started Jul 29 07:55:03 PM PDT 24
Finished Jul 29 08:03:34 PM PDT 24
Peak memory 575812 kb
Host smart-91f6bd4f-2490-4571-9de6-3c3b87c70642
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133598369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.4133598369
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.2224777738
Short name T1933
Test name
Test status
Simulation time 55387690985 ps
CPU time 886.44 seconds
Started Jul 29 07:55:02 PM PDT 24
Finished Jul 29 08:09:49 PM PDT 24
Peak memory 576000 kb
Host smart-b1dd98a5-6583-454c-8992-47ae08aecedc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224777738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2224777738
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.3329605436
Short name T2796
Test name
Test status
Simulation time 370774768 ps
CPU time 31.36 seconds
Started Jul 29 07:54:48 PM PDT 24
Finished Jul 29 07:55:20 PM PDT 24
Peak memory 575700 kb
Host smart-587c1ea9-69e1-417e-af72-6edea2df9cd7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329605436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del
ays.3329605436
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_same_source.1939836757
Short name T2541
Test name
Test status
Simulation time 2311725571 ps
CPU time 71.38 seconds
Started Jul 29 07:54:59 PM PDT 24
Finished Jul 29 07:56:11 PM PDT 24
Peak memory 575936 kb
Host smart-4de3acdf-424f-4ebc-abe7-d4c4aa3325a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939836757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1939836757
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke.1546912291
Short name T1690
Test name
Test status
Simulation time 193531749 ps
CPU time 8.92 seconds
Started Jul 29 07:54:55 PM PDT 24
Finished Jul 29 07:55:04 PM PDT 24
Peak memory 574552 kb
Host smart-dd48d99d-6dfa-49af-aa28-3cb76f6eb530
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546912291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1546912291
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.791181861
Short name T521
Test name
Test status
Simulation time 7378907870 ps
CPU time 78.67 seconds
Started Jul 29 07:54:55 PM PDT 24
Finished Jul 29 07:56:13 PM PDT 24
Peak memory 573920 kb
Host smart-31609dc9-2661-479b-b787-d6924df99973
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791181861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.791181861
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.2170513380
Short name T2660
Test name
Test status
Simulation time 4792749337 ps
CPU time 73.96 seconds
Started Jul 29 07:54:54 PM PDT 24
Finished Jul 29 07:56:08 PM PDT 24
Peak memory 573796 kb
Host smart-4b16ad63-cb4c-4eb8-b613-4717634f952f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170513380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2170513380
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.3656855437
Short name T1486
Test name
Test status
Simulation time 49617943 ps
CPU time 6.3 seconds
Started Jul 29 07:54:53 PM PDT 24
Finished Jul 29 07:54:59 PM PDT 24
Peak memory 573892 kb
Host smart-c487a0fd-8137-4857-91b0-e13f55451f59
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656855437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay
s.3656855437
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all.3250472965
Short name T586
Test name
Test status
Simulation time 2423873858 ps
CPU time 179.44 seconds
Started Jul 29 07:55:01 PM PDT 24
Finished Jul 29 07:58:01 PM PDT 24
Peak memory 576828 kb
Host smart-97905c6f-39a7-4ff1-abbc-ebb7d12a403e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250472965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3250472965
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.310422780
Short name T2046
Test name
Test status
Simulation time 2253802212 ps
CPU time 184.74 seconds
Started Jul 29 07:55:00 PM PDT 24
Finished Jul 29 07:58:05 PM PDT 24
Peak memory 576212 kb
Host smart-23a27fcf-b04c-4436-8e81-e51ff1118e74
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310422780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.310422780
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.2852275169
Short name T898
Test name
Test status
Simulation time 547785977 ps
CPU time 225.32 seconds
Started Jul 29 07:55:00 PM PDT 24
Finished Jul 29 07:58:46 PM PDT 24
Peak memory 576776 kb
Host smart-16addf39-a3c6-483f-ac5e-1d043703abc6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852275169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all
_with_rand_reset.2852275169
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.1098092704
Short name T1873
Test name
Test status
Simulation time 12209272661 ps
CPU time 667.19 seconds
Started Jul 29 07:55:01 PM PDT 24
Finished Jul 29 08:06:09 PM PDT 24
Peak memory 576868 kb
Host smart-2d7d8be3-4f22-4d5c-9c64-ec34ef704f3d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098092704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al
l_with_reset_error.1098092704
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.3191550299
Short name T2098
Test name
Test status
Simulation time 127221352 ps
CPU time 18.55 seconds
Started Jul 29 07:55:00 PM PDT 24
Finished Jul 29 07:55:19 PM PDT 24
Peak memory 576004 kb
Host smart-814697ee-854a-416b-8b3d-99acdff42b20
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191550299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3191550299
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_access_same_device.895014258
Short name T2928
Test name
Test status
Simulation time 1013925313 ps
CPU time 38.39 seconds
Started Jul 29 07:55:12 PM PDT 24
Finished Jul 29 07:55:50 PM PDT 24
Peak memory 575972 kb
Host smart-aee2e073-f6f5-4ab0-acf0-d7351265b803
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895014258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.
895014258
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.3690973267
Short name T873
Test name
Test status
Simulation time 57224624472 ps
CPU time 959.48 seconds
Started Jul 29 07:55:10 PM PDT 24
Finished Jul 29 08:11:09 PM PDT 24
Peak memory 576140 kb
Host smart-23189def-6924-45db-884a-c754071f7348
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690973267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_
device_slow_rsp.3690973267
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.2928268340
Short name T1503
Test name
Test status
Simulation time 451601592 ps
CPU time 18.6 seconds
Started Jul 29 07:55:12 PM PDT 24
Finished Jul 29 07:55:31 PM PDT 24
Peak memory 575816 kb
Host smart-b265798d-1f86-4fdd-8009-594151417763
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928268340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add
r.2928268340
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_error_random.449078185
Short name T1783
Test name
Test status
Simulation time 85773589 ps
CPU time 10.57 seconds
Started Jul 29 07:55:11 PM PDT 24
Finished Jul 29 07:55:22 PM PDT 24
Peak memory 575756 kb
Host smart-0c434d51-2d8d-4c75-92af-0873bc733dfe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449078185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.449078185
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random.1496507485
Short name T2122
Test name
Test status
Simulation time 433624104 ps
CPU time 19.43 seconds
Started Jul 29 07:55:13 PM PDT 24
Finished Jul 29 07:55:32 PM PDT 24
Peak memory 575844 kb
Host smart-5f624d1d-ef8d-4d76-b431-a818ecce7370
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496507485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.1496507485
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.557617750
Short name T2318
Test name
Test status
Simulation time 33489846360 ps
CPU time 326.66 seconds
Started Jul 29 07:55:12 PM PDT 24
Finished Jul 29 08:00:38 PM PDT 24
Peak memory 576100 kb
Host smart-59024618-3db1-41dc-b5c2-4a0bcb6ad0b2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557617750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.557617750
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.1884832484
Short name T1680
Test name
Test status
Simulation time 61059209101 ps
CPU time 1011.29 seconds
Started Jul 29 07:55:14 PM PDT 24
Finished Jul 29 08:12:06 PM PDT 24
Peak memory 576104 kb
Host smart-2a16b1cf-c5cf-4565-bb50-bf3bba9ccf9c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884832484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1884832484
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.88813123
Short name T1936
Test name
Test status
Simulation time 230418803 ps
CPU time 22.7 seconds
Started Jul 29 07:55:09 PM PDT 24
Finished Jul 29 07:55:32 PM PDT 24
Peak memory 575892 kb
Host smart-1fd3d397-53d6-41ef-bebe-cdda49aa6dcc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88813123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delay
s.88813123
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_same_source.3453869128
Short name T2803
Test name
Test status
Simulation time 312711678 ps
CPU time 22.89 seconds
Started Jul 29 07:55:10 PM PDT 24
Finished Jul 29 07:55:33 PM PDT 24
Peak memory 575860 kb
Host smart-6c76388a-6437-427d-ade8-2ad820ffe7ea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453869128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3453869128
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke.1174456644
Short name T2334
Test name
Test status
Simulation time 216937355 ps
CPU time 9.45 seconds
Started Jul 29 07:54:59 PM PDT 24
Finished Jul 29 07:55:09 PM PDT 24
Peak memory 573900 kb
Host smart-a938c50d-6330-4ef5-8813-8041684f5cf8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174456644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1174456644
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.2674846201
Short name T1670
Test name
Test status
Simulation time 10262524405 ps
CPU time 114.86 seconds
Started Jul 29 07:54:59 PM PDT 24
Finished Jul 29 07:56:54 PM PDT 24
Peak memory 573912 kb
Host smart-6c785e51-f20a-47c3-86c6-a9bfebce6498
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674846201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2674846201
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.172581909
Short name T2103
Test name
Test status
Simulation time 2585945973 ps
CPU time 44.28 seconds
Started Jul 29 07:55:01 PM PDT 24
Finished Jul 29 07:55:46 PM PDT 24
Peak memory 574604 kb
Host smart-c86417e9-5c1e-4d3d-9f91-33a52fe90d89
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172581909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.172581909
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.259201
Short name T2502
Test name
Test status
Simulation time 39412997 ps
CPU time 5.98 seconds
Started Jul 29 07:54:59 PM PDT 24
Finished Jul 29 07:55:05 PM PDT 24
Peak memory 573848 kb
Host smart-014b9a38-5dc9-4e2f-a92a-7f952a4b4e1c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.259201
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all.2800203784
Short name T432
Test name
Test status
Simulation time 2568133873 ps
CPU time 217.05 seconds
Started Jul 29 07:55:10 PM PDT 24
Finished Jul 29 07:58:47 PM PDT 24
Peak memory 576092 kb
Host smart-ca9cab1c-305b-4fa8-b20d-113c63c74b77
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800203784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2800203784
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.1540225433
Short name T2076
Test name
Test status
Simulation time 9405714382 ps
CPU time 346.58 seconds
Started Jul 29 07:55:09 PM PDT 24
Finished Jul 29 08:00:55 PM PDT 24
Peak memory 575992 kb
Host smart-d85e1ea7-d515-4bda-8182-3a8ea0491b88
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540225433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1540225433
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.841830341
Short name T2010
Test name
Test status
Simulation time 943023525 ps
CPU time 99.12 seconds
Started Jul 29 07:55:09 PM PDT 24
Finished Jul 29 07:56:48 PM PDT 24
Peak memory 576908 kb
Host smart-1642cf8c-0d0c-4270-882a-b6cdccc367b0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841830341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_
with_rand_reset.841830341
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.1594458784
Short name T1492
Test name
Test status
Simulation time 1474711513 ps
CPU time 198.27 seconds
Started Jul 29 07:55:10 PM PDT 24
Finished Jul 29 07:58:28 PM PDT 24
Peak memory 576880 kb
Host smart-4a7a61d3-86b6-4a95-bf68-de68870fbf46
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594458784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al
l_with_reset_error.1594458784
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.1651364575
Short name T1698
Test name
Test status
Simulation time 851531570 ps
CPU time 37.23 seconds
Started Jul 29 07:55:10 PM PDT 24
Finished Jul 29 07:55:48 PM PDT 24
Peak memory 576000 kb
Host smart-42865335-5d69-4bdc-8c4c-47350e2ea0df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651364575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1651364575
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_access_same_device.3220379102
Short name T1812
Test name
Test status
Simulation time 438352802 ps
CPU time 25 seconds
Started Jul 29 07:55:18 PM PDT 24
Finished Jul 29 07:55:43 PM PDT 24
Peak memory 575932 kb
Host smart-352577ff-e9dd-4f31-9b36-5339ad332ea1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220379102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device
.3220379102
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.4011113423
Short name T2631
Test name
Test status
Simulation time 60143812518 ps
CPU time 983.67 seconds
Started Jul 29 07:55:21 PM PDT 24
Finished Jul 29 08:11:45 PM PDT 24
Peak memory 575956 kb
Host smart-8910ed53-c771-46ad-ae0b-39bba0d1da7f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011113423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_
device_slow_rsp.4011113423
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.115038005
Short name T2757
Test name
Test status
Simulation time 58103865 ps
CPU time 9.28 seconds
Started Jul 29 07:55:19 PM PDT 24
Finished Jul 29 07:55:28 PM PDT 24
Peak memory 576016 kb
Host smart-4fc28525-81dc-468e-a3d5-02ab67d0dba1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115038005 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr
.115038005
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_error_random.627404705
Short name T2460
Test name
Test status
Simulation time 366413582 ps
CPU time 33.54 seconds
Started Jul 29 07:55:18 PM PDT 24
Finished Jul 29 07:55:51 PM PDT 24
Peak memory 575752 kb
Host smart-1681f449-9e0c-43b9-9902-0bc13dbcedc4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627404705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.627404705
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random.3769749616
Short name T2780
Test name
Test status
Simulation time 1158922667 ps
CPU time 38.32 seconds
Started Jul 29 07:55:20 PM PDT 24
Finished Jul 29 07:55:58 PM PDT 24
Peak memory 576044 kb
Host smart-99c28496-68d8-441a-8a48-ff62232498c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769749616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.3769749616
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.1078901131
Short name T2343
Test name
Test status
Simulation time 95964996512 ps
CPU time 985.72 seconds
Started Jul 29 07:55:18 PM PDT 24
Finished Jul 29 08:11:45 PM PDT 24
Peak memory 576004 kb
Host smart-30e5a8be-7bf1-4b9d-a19a-37a047eb25ed
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078901131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1078901131
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.2265345144
Short name T1700
Test name
Test status
Simulation time 56576782549 ps
CPU time 909.54 seconds
Started Jul 29 07:55:19 PM PDT 24
Finished Jul 29 08:10:29 PM PDT 24
Peak memory 575800 kb
Host smart-31e527e4-f20c-44bf-a225-dd19898ef527
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265345144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2265345144
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.1643547963
Short name T2178
Test name
Test status
Simulation time 305790467 ps
CPU time 25.99 seconds
Started Jul 29 07:55:19 PM PDT 24
Finished Jul 29 07:55:45 PM PDT 24
Peak memory 575796 kb
Host smart-93d2be85-58da-4964-8532-212472c5dc5d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643547963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del
ays.1643547963
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_same_source.2340556289
Short name T2072
Test name
Test status
Simulation time 374394560 ps
CPU time 26.5 seconds
Started Jul 29 07:55:20 PM PDT 24
Finished Jul 29 07:55:47 PM PDT 24
Peak memory 575920 kb
Host smart-d46f3b63-fd52-4577-bedf-494851c6e670
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340556289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2340556289
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke.1276299030
Short name T2740
Test name
Test status
Simulation time 50987165 ps
CPU time 6.18 seconds
Started Jul 29 07:55:11 PM PDT 24
Finished Jul 29 07:55:18 PM PDT 24
Peak memory 573796 kb
Host smart-a2d3d621-2638-4855-a073-99f2ff24e141
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276299030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1276299030
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.3172683417
Short name T2278
Test name
Test status
Simulation time 8048452978 ps
CPU time 81.13 seconds
Started Jul 29 07:55:20 PM PDT 24
Finished Jul 29 07:56:41 PM PDT 24
Peak memory 573932 kb
Host smart-8ced9fb6-a537-400a-9c18-736dbb84105e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172683417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3172683417
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.1461025129
Short name T2629
Test name
Test status
Simulation time 4770520946 ps
CPU time 84.18 seconds
Started Jul 29 07:55:21 PM PDT 24
Finished Jul 29 07:56:45 PM PDT 24
Peak memory 574004 kb
Host smart-e14e3995-17e4-45cc-843d-7e0881ddca86
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461025129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1461025129
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.1309908569
Short name T1526
Test name
Test status
Simulation time 53407245 ps
CPU time 6.8 seconds
Started Jul 29 07:55:18 PM PDT 24
Finished Jul 29 07:55:25 PM PDT 24
Peak memory 573836 kb
Host smart-4848840b-5b09-4625-b587-313b94c81820
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309908569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay
s.1309908569
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all.1581121579
Short name T452
Test name
Test status
Simulation time 4750238285 ps
CPU time 149.99 seconds
Started Jul 29 07:55:35 PM PDT 24
Finished Jul 29 07:58:05 PM PDT 24
Peak memory 576124 kb
Host smart-f1d46074-1525-4f09-907b-35a8c4674ff6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581121579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1581121579
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.245674540
Short name T1433
Test name
Test status
Simulation time 2249319450 ps
CPU time 65.33 seconds
Started Jul 29 07:55:33 PM PDT 24
Finished Jul 29 07:56:38 PM PDT 24
Peak memory 576024 kb
Host smart-bd43b46c-4baa-4d0f-a98c-33cd489424a9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245674540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.245674540
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3446402277
Short name T1912
Test name
Test status
Simulation time 94809124 ps
CPU time 26.78 seconds
Started Jul 29 07:55:36 PM PDT 24
Finished Jul 29 07:56:03 PM PDT 24
Peak memory 576696 kb
Host smart-e5765ef2-9187-4b5e-84a1-16b89cdc1c16
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446402277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all
_with_rand_reset.3446402277
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1545928079
Short name T853
Test name
Test status
Simulation time 1986750938 ps
CPU time 111.45 seconds
Started Jul 29 07:55:28 PM PDT 24
Finished Jul 29 07:57:20 PM PDT 24
Peak memory 576548 kb
Host smart-76a89da9-d63f-4851-b46b-fcafd8717518
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545928079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al
l_with_reset_error.1545928079
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.3283799015
Short name T524
Test name
Test status
Simulation time 954766888 ps
CPU time 37.25 seconds
Started Jul 29 07:55:18 PM PDT 24
Finished Jul 29 07:55:56 PM PDT 24
Peak memory 576068 kb
Host smart-d555c205-d8f7-4755-8de1-8959f0f43550
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283799015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3283799015
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1063940183
Short name T2808
Test name
Test status
Simulation time 1060936051 ps
CPU time 44.07 seconds
Started Jul 29 07:55:37 PM PDT 24
Finished Jul 29 07:56:21 PM PDT 24
Peak memory 575876 kb
Host smart-04867450-b1d8-4951-8fc1-a0de956b181d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063940183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device
.1063940183
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.2730184421
Short name T1609
Test name
Test status
Simulation time 6201355752 ps
CPU time 108.5 seconds
Started Jul 29 07:55:39 PM PDT 24
Finished Jul 29 07:57:28 PM PDT 24
Peak memory 575868 kb
Host smart-958a00c0-bed9-4ba1-a5e9-c52921ee2778
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730184421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_
device_slow_rsp.2730184421
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.1982300732
Short name T2179
Test name
Test status
Simulation time 103400220 ps
CPU time 13.08 seconds
Started Jul 29 07:55:38 PM PDT 24
Finished Jul 29 07:55:51 PM PDT 24
Peak memory 575964 kb
Host smart-eed6ee5e-1547-46d1-8b2e-fb13860838df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982300732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add
r.1982300732
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_error_random.2282620848
Short name T2000
Test name
Test status
Simulation time 1462829794 ps
CPU time 44.99 seconds
Started Jul 29 07:55:47 PM PDT 24
Finished Jul 29 07:56:32 PM PDT 24
Peak memory 575856 kb
Host smart-875f9271-a924-44e2-9aaa-32eb9838efdd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282620848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2282620848
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random.2714411481
Short name T2896
Test name
Test status
Simulation time 573553487 ps
CPU time 49.25 seconds
Started Jul 29 07:55:30 PM PDT 24
Finished Jul 29 07:56:19 PM PDT 24
Peak memory 575852 kb
Host smart-e4896c9b-6b32-45bf-b798-9977e957e063
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714411481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.2714411481
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.1623624320
Short name T2413
Test name
Test status
Simulation time 69737497134 ps
CPU time 715.41 seconds
Started Jul 29 07:55:36 PM PDT 24
Finished Jul 29 08:07:31 PM PDT 24
Peak memory 576064 kb
Host smart-88bfb623-e866-4873-af08-cefd64e71ed7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623624320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1623624320
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.502559994
Short name T1657
Test name
Test status
Simulation time 58936442701 ps
CPU time 1031.8 seconds
Started Jul 29 07:55:28 PM PDT 24
Finished Jul 29 08:12:40 PM PDT 24
Peak memory 575920 kb
Host smart-737f1639-b630-4517-9f13-c3813a9f26a6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502559994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.502559994
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.2293275447
Short name T2658
Test name
Test status
Simulation time 184748177 ps
CPU time 18.76 seconds
Started Jul 29 07:55:28 PM PDT 24
Finished Jul 29 07:55:46 PM PDT 24
Peak memory 576096 kb
Host smart-63c73902-efbe-4975-81be-0cbc8434271a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293275447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del
ays.2293275447
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_same_source.3553171761
Short name T1568
Test name
Test status
Simulation time 1228483668 ps
CPU time 39.14 seconds
Started Jul 29 07:55:36 PM PDT 24
Finished Jul 29 07:56:15 PM PDT 24
Peak memory 575728 kb
Host smart-39a47a30-f4da-4474-a74e-e6f4531897c1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553171761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3553171761
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke.3014660128
Short name T1572
Test name
Test status
Simulation time 44591894 ps
CPU time 6.75 seconds
Started Jul 29 07:55:35 PM PDT 24
Finished Jul 29 07:55:42 PM PDT 24
Peak memory 573912 kb
Host smart-622a698f-7d4a-4f5b-9856-a06f1df88b71
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014660128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3014660128
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.1071107603
Short name T1443
Test name
Test status
Simulation time 7360322481 ps
CPU time 73.93 seconds
Started Jul 29 07:55:33 PM PDT 24
Finished Jul 29 07:56:47 PM PDT 24
Peak memory 573996 kb
Host smart-59c87623-a015-4848-aa46-26c6dccfba79
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071107603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1071107603
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.1300141914
Short name T1659
Test name
Test status
Simulation time 5177526556 ps
CPU time 86.13 seconds
Started Jul 29 07:55:29 PM PDT 24
Finished Jul 29 07:56:55 PM PDT 24
Peak memory 574644 kb
Host smart-ad430fc5-e2cd-4031-9de0-ee05cec335c8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300141914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1300141914
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.1987976297
Short name T2433
Test name
Test status
Simulation time 38436110 ps
CPU time 5.98 seconds
Started Jul 29 07:55:30 PM PDT 24
Finished Jul 29 07:55:36 PM PDT 24
Peak memory 574556 kb
Host smart-283d125d-881e-4756-896d-a1ccd950640f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987976297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay
s.1987976297
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all.4063387847
Short name T1784
Test name
Test status
Simulation time 14612062106 ps
CPU time 700.11 seconds
Started Jul 29 07:55:37 PM PDT 24
Finished Jul 29 08:07:18 PM PDT 24
Peak memory 575968 kb
Host smart-ac4bc23e-93d3-467d-be16-f78b2c8b995e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063387847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.4063387847
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.1658506405
Short name T1411
Test name
Test status
Simulation time 4979201048 ps
CPU time 149.48 seconds
Started Jul 29 07:55:48 PM PDT 24
Finished Jul 29 07:58:17 PM PDT 24
Peak memory 576100 kb
Host smart-ec7de347-598d-46e1-a8ec-fc7a9b03e7b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658506405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1658506405
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.3425502473
Short name T888
Test name
Test status
Simulation time 330269801 ps
CPU time 167.62 seconds
Started Jul 29 07:55:37 PM PDT 24
Finished Jul 29 07:58:24 PM PDT 24
Peak memory 576800 kb
Host smart-4bc128f8-14ad-48e1-a264-be835e5ced2d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425502473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all
_with_rand_reset.3425502473
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2155876538
Short name T905
Test name
Test status
Simulation time 220187052 ps
CPU time 60.79 seconds
Started Jul 29 07:55:37 PM PDT 24
Finished Jul 29 07:56:38 PM PDT 24
Peak memory 576772 kb
Host smart-021a8e1e-dc02-4611-876a-8eec1ee3130e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155876538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al
l_with_reset_error.2155876538
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.4026364013
Short name T639
Test name
Test status
Simulation time 953138186 ps
CPU time 35.01 seconds
Started Jul 29 07:55:46 PM PDT 24
Finished Jul 29 07:56:21 PM PDT 24
Peak memory 575944 kb
Host smart-a69774a3-904f-46e5-8529-acebb4e02d75
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026364013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.4026364013
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_access_same_device.3536546985
Short name T1527
Test name
Test status
Simulation time 295853964 ps
CPU time 15.19 seconds
Started Jul 29 07:55:46 PM PDT 24
Finished Jul 29 07:56:02 PM PDT 24
Peak memory 575936 kb
Host smart-04f72810-70dc-45e4-aa06-f1004922742f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536546985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device
.3536546985
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.1318524150
Short name T1770
Test name
Test status
Simulation time 63711244834 ps
CPU time 1093.14 seconds
Started Jul 29 07:55:47 PM PDT 24
Finished Jul 29 08:14:01 PM PDT 24
Peak memory 575988 kb
Host smart-63beeea7-db2f-4e33-bd6c-6a9334415bb4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318524150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_
device_slow_rsp.1318524150
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.1926135303
Short name T1966
Test name
Test status
Simulation time 128923189 ps
CPU time 14.56 seconds
Started Jul 29 07:55:49 PM PDT 24
Finished Jul 29 07:56:04 PM PDT 24
Peak memory 576008 kb
Host smart-ca2e3f20-af20-4e6a-9bb3-746a3dd2ee2e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926135303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add
r.1926135303
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_error_random.3517768275
Short name T1747
Test name
Test status
Simulation time 1061767796 ps
CPU time 34.36 seconds
Started Jul 29 07:55:47 PM PDT 24
Finished Jul 29 07:56:22 PM PDT 24
Peak memory 575668 kb
Host smart-4dc43c81-8cbf-4a9c-8f78-8b7afff65c1c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517768275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3517768275
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random.982866807
Short name T661
Test name
Test status
Simulation time 401796368 ps
CPU time 37.57 seconds
Started Jul 29 07:55:48 PM PDT 24
Finished Jul 29 07:56:25 PM PDT 24
Peak memory 575976 kb
Host smart-ad3cbeef-724a-4e21-b23c-7395e89374ba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982866807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.982866807
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.1258466931
Short name T2542
Test name
Test status
Simulation time 10368135238 ps
CPU time 106.77 seconds
Started Jul 29 07:55:48 PM PDT 24
Finished Jul 29 07:57:35 PM PDT 24
Peak memory 575904 kb
Host smart-99b53beb-a802-480d-b29b-3fc82fb5698d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258466931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1258466931
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.226277088
Short name T478
Test name
Test status
Simulation time 50827170759 ps
CPU time 845.68 seconds
Started Jul 29 07:55:47 PM PDT 24
Finished Jul 29 08:09:54 PM PDT 24
Peak memory 575944 kb
Host smart-ac87ed71-21e8-4de1-90ac-f55b8d5d2fb3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226277088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.226277088
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.1334043549
Short name T2130
Test name
Test status
Simulation time 334090949 ps
CPU time 31.17 seconds
Started Jul 29 07:55:46 PM PDT 24
Finished Jul 29 07:56:17 PM PDT 24
Peak memory 575896 kb
Host smart-a15e6bcb-0221-401f-9909-f96eb1695770
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334043549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del
ays.1334043549
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_same_source.2098147034
Short name T2637
Test name
Test status
Simulation time 1741249028 ps
CPU time 52.66 seconds
Started Jul 29 07:55:47 PM PDT 24
Finished Jul 29 07:56:40 PM PDT 24
Peak memory 575884 kb
Host smart-4ca56189-8cb8-4650-a370-36c196c6d407
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098147034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2098147034
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke.220477126
Short name T686
Test name
Test status
Simulation time 121633726 ps
CPU time 6.5 seconds
Started Jul 29 07:55:46 PM PDT 24
Finished Jul 29 07:55:52 PM PDT 24
Peak memory 573792 kb
Host smart-fd7094e3-3dbf-4eff-8b94-70331fe1e9eb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220477126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.220477126
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.1624856668
Short name T667
Test name
Test status
Simulation time 7781105526 ps
CPU time 82.07 seconds
Started Jul 29 07:55:46 PM PDT 24
Finished Jul 29 07:57:08 PM PDT 24
Peak memory 573880 kb
Host smart-aabdff78-b586-4e29-9587-fb9b6786a9c5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624856668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1624856668
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.3548957657
Short name T2035
Test name
Test status
Simulation time 6084501454 ps
CPU time 104.78 seconds
Started Jul 29 07:55:39 PM PDT 24
Finished Jul 29 07:57:24 PM PDT 24
Peak memory 574652 kb
Host smart-65e82cf9-04d2-4dd7-993a-c81b60b51f26
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548957657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3548957657
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.2089997067
Short name T1851
Test name
Test status
Simulation time 52134073 ps
CPU time 5.9 seconds
Started Jul 29 07:55:36 PM PDT 24
Finished Jul 29 07:55:42 PM PDT 24
Peak memory 574476 kb
Host smart-8db15bdd-c6df-4265-ac75-9200df0a8bc7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089997067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay
s.2089997067
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all.2493781766
Short name T2752
Test name
Test status
Simulation time 10717768722 ps
CPU time 358.16 seconds
Started Jul 29 07:55:48 PM PDT 24
Finished Jul 29 08:01:46 PM PDT 24
Peak memory 576468 kb
Host smart-a5360377-d38b-489f-80e6-97eba8542172
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493781766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2493781766
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.2096435161
Short name T551
Test name
Test status
Simulation time 1618313765 ps
CPU time 141.17 seconds
Started Jul 29 07:55:47 PM PDT 24
Finished Jul 29 07:58:08 PM PDT 24
Peak memory 575916 kb
Host smart-af284c57-cf77-4d0e-ab9e-63da6c75303d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096435161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2096435161
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.3401846519
Short name T471
Test name
Test status
Simulation time 4944465591 ps
CPU time 266.78 seconds
Started Jul 29 07:55:46 PM PDT 24
Finished Jul 29 08:00:13 PM PDT 24
Peak memory 576044 kb
Host smart-96355ddf-da96-43b4-bad8-0777aaa54049
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401846519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all
_with_rand_reset.3401846519
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3051869197
Short name T867
Test name
Test status
Simulation time 257765789 ps
CPU time 69.76 seconds
Started Jul 29 07:55:49 PM PDT 24
Finished Jul 29 07:56:59 PM PDT 24
Peak memory 576764 kb
Host smart-b84786d9-d01b-4dea-ab3c-c2c0925ebad9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051869197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al
l_with_reset_error.3051869197
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.559039571
Short name T2346
Test name
Test status
Simulation time 835249006 ps
CPU time 33.02 seconds
Started Jul 29 07:55:46 PM PDT 24
Finished Jul 29 07:56:19 PM PDT 24
Peak memory 576096 kb
Host smart-09824a51-9a5e-40d3-8575-75975357d636
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559039571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.559039571
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_access_same_device.2517224479
Short name T1663
Test name
Test status
Simulation time 3197000285 ps
CPU time 140.79 seconds
Started Jul 29 07:56:01 PM PDT 24
Finished Jul 29 07:58:22 PM PDT 24
Peak memory 576136 kb
Host smart-97987b7e-e5ab-429d-9e0b-f02abea86189
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517224479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device
.2517224479
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.1762892749
Short name T2508
Test name
Test status
Simulation time 90299182549 ps
CPU time 1645.21 seconds
Started Jul 29 07:55:57 PM PDT 24
Finished Jul 29 08:23:22 PM PDT 24
Peak memory 576136 kb
Host smart-06c781e7-9857-46e6-a691-cb828e2766c9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762892749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_
device_slow_rsp.1762892749
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.2530810526
Short name T1644
Test name
Test status
Simulation time 595451567 ps
CPU time 28.46 seconds
Started Jul 29 07:56:00 PM PDT 24
Finished Jul 29 07:56:29 PM PDT 24
Peak memory 576004 kb
Host smart-3af80b6c-6817-45ca-b8ab-8b6e09ae988c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530810526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add
r.2530810526
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_error_random.2732182766
Short name T2736
Test name
Test status
Simulation time 217976499 ps
CPU time 20.4 seconds
Started Jul 29 07:55:58 PM PDT 24
Finished Jul 29 07:56:19 PM PDT 24
Peak memory 575704 kb
Host smart-5efb74a0-7b04-40f1-90ae-c9eb16849987
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732182766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2732182766
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random.4181274870
Short name T1490
Test name
Test status
Simulation time 1211718673 ps
CPU time 45.39 seconds
Started Jul 29 07:55:58 PM PDT 24
Finished Jul 29 07:56:44 PM PDT 24
Peak memory 575984 kb
Host smart-b8d00af8-0fd1-491e-a90f-602c061a0275
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181274870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.4181274870
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.2762779914
Short name T2712
Test name
Test status
Simulation time 55467762424 ps
CPU time 588.81 seconds
Started Jul 29 07:56:00 PM PDT 24
Finished Jul 29 08:05:48 PM PDT 24
Peak memory 576108 kb
Host smart-d771a66a-c566-494a-a2b1-8d561e5dccb3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762779914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2762779914
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.3544679372
Short name T2868
Test name
Test status
Simulation time 31976855017 ps
CPU time 551.96 seconds
Started Jul 29 07:56:01 PM PDT 24
Finished Jul 29 08:05:13 PM PDT 24
Peak memory 576156 kb
Host smart-deb57319-77d5-4dd0-9012-d6ba7a792bd5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544679372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3544679372
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.583658433
Short name T2521
Test name
Test status
Simulation time 189644279 ps
CPU time 16.29 seconds
Started Jul 29 07:55:58 PM PDT 24
Finished Jul 29 07:56:15 PM PDT 24
Peak memory 575844 kb
Host smart-d2ee51d9-eefa-40e0-8a82-77415fcac87f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583658433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_dela
ys.583658433
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_same_source.2323856540
Short name T2630
Test name
Test status
Simulation time 594898801 ps
CPU time 18.47 seconds
Started Jul 29 07:55:59 PM PDT 24
Finished Jul 29 07:56:18 PM PDT 24
Peak memory 575804 kb
Host smart-641f2922-28bb-4b6e-ae36-de9e6cda858c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323856540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2323856540
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke.3163189982
Short name T2584
Test name
Test status
Simulation time 223190661 ps
CPU time 9.39 seconds
Started Jul 29 07:55:46 PM PDT 24
Finished Jul 29 07:55:55 PM PDT 24
Peak memory 573908 kb
Host smart-550d8a69-9409-4957-b07e-3dc1e528d053
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163189982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3163189982
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.2389614870
Short name T2006
Test name
Test status
Simulation time 8779160425 ps
CPU time 90.03 seconds
Started Jul 29 07:55:59 PM PDT 24
Finished Jul 29 07:57:29 PM PDT 24
Peak memory 573872 kb
Host smart-eb5d1aca-539e-4ab8-ae1d-0114a2e0ad73
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389614870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2389614870
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.4233567084
Short name T2866
Test name
Test status
Simulation time 5107365354 ps
CPU time 86.85 seconds
Started Jul 29 07:56:01 PM PDT 24
Finished Jul 29 07:57:28 PM PDT 24
Peak memory 574620 kb
Host smart-8d3823e9-986f-45c1-a71d-99ac7e7b6d51
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233567084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.4233567084
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.775502632
Short name T1788
Test name
Test status
Simulation time 42482066 ps
CPU time 6.21 seconds
Started Jul 29 07:55:47 PM PDT 24
Finished Jul 29 07:55:54 PM PDT 24
Peak memory 573888 kb
Host smart-dbb24d0c-77f6-4a69-b70a-c3036faf1dcf
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775502632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays
.775502632
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all.2950278903
Short name T1736
Test name
Test status
Simulation time 9035603350 ps
CPU time 360.52 seconds
Started Jul 29 07:55:58 PM PDT 24
Finished Jul 29 08:01:59 PM PDT 24
Peak memory 575972 kb
Host smart-55caef3b-062d-4d98-baa4-ca93df50ac06
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950278903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2950278903
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.2090060318
Short name T2159
Test name
Test status
Simulation time 117852490 ps
CPU time 35.6 seconds
Started Jul 29 07:55:58 PM PDT 24
Finished Jul 29 07:56:34 PM PDT 24
Peak memory 576644 kb
Host smart-643448b3-3217-49d9-9f21-cc4f04679e25
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090060318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al
l_with_reset_error.2090060318
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.3272602778
Short name T550
Test name
Test status
Simulation time 196743477 ps
CPU time 22.68 seconds
Started Jul 29 07:55:59 PM PDT 24
Finished Jul 29 07:56:22 PM PDT 24
Peak memory 575932 kb
Host smart-c3cdcfba-d927-44e0-ab8f-24dabb28a6b1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272602778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3272602778
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_access_same_device.3397195353
Short name T2848
Test name
Test status
Simulation time 3042799675 ps
CPU time 132.85 seconds
Started Jul 29 07:56:10 PM PDT 24
Finished Jul 29 07:58:23 PM PDT 24
Peak memory 576048 kb
Host smart-9054212d-d4a6-444b-a508-8da4a1872bf1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397195353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device
.3397195353
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.3659524152
Short name T2388
Test name
Test status
Simulation time 154161959061 ps
CPU time 2872.53 seconds
Started Jul 29 07:56:08 PM PDT 24
Finished Jul 29 08:44:01 PM PDT 24
Peak memory 576120 kb
Host smart-188e4e15-7cb5-4aef-90ef-60b8ec1daee4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659524152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_
device_slow_rsp.3659524152
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.2152460634
Short name T1415
Test name
Test status
Simulation time 102711990 ps
CPU time 12.74 seconds
Started Jul 29 07:56:09 PM PDT 24
Finished Jul 29 07:56:22 PM PDT 24
Peak memory 575896 kb
Host smart-68e5a3be-6754-4c28-883a-50b2c76b54b3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152460634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add
r.2152460634
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_error_random.3631072976
Short name T1593
Test name
Test status
Simulation time 1922546704 ps
CPU time 60.68 seconds
Started Jul 29 07:56:12 PM PDT 24
Finished Jul 29 07:57:13 PM PDT 24
Peak memory 576044 kb
Host smart-7a90cc76-20eb-4d9a-9f78-1952e62b1ac5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631072976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3631072976
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random.3130584704
Short name T611
Test name
Test status
Simulation time 2185205901 ps
CPU time 77.98 seconds
Started Jul 29 07:56:11 PM PDT 24
Finished Jul 29 07:57:29 PM PDT 24
Peak memory 575812 kb
Host smart-fa939b46-5050-414e-ae5c-05e2a2828524
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130584704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.3130584704
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.3166101760
Short name T1882
Test name
Test status
Simulation time 31408415571 ps
CPU time 324.34 seconds
Started Jul 29 07:56:13 PM PDT 24
Finished Jul 29 08:01:37 PM PDT 24
Peak memory 576064 kb
Host smart-46151458-f1cc-4a1e-a6cc-62f1fa246154
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166101760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3166101760
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.1974349094
Short name T1979
Test name
Test status
Simulation time 57574833168 ps
CPU time 1008.56 seconds
Started Jul 29 07:56:11 PM PDT 24
Finished Jul 29 08:12:59 PM PDT 24
Peak memory 576080 kb
Host smart-2d32d785-c1e8-4861-91e3-d965a9df590a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974349094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1974349094
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.4138997736
Short name T2449
Test name
Test status
Simulation time 368465034 ps
CPU time 33.11 seconds
Started Jul 29 07:56:10 PM PDT 24
Finished Jul 29 07:56:43 PM PDT 24
Peak memory 575828 kb
Host smart-6bb09e8d-5516-4e58-8c28-e030c50d8af5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138997736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del
ays.4138997736
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_same_source.2384204535
Short name T602
Test name
Test status
Simulation time 2734862270 ps
CPU time 79.13 seconds
Started Jul 29 07:56:10 PM PDT 24
Finished Jul 29 07:57:29 PM PDT 24
Peak memory 575928 kb
Host smart-08438b34-29b7-460c-9759-0460ec9060cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384204535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2384204535
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke.1449777393
Short name T579
Test name
Test status
Simulation time 43195528 ps
CPU time 6.62 seconds
Started Jul 29 07:55:58 PM PDT 24
Finished Jul 29 07:56:05 PM PDT 24
Peak memory 574568 kb
Host smart-049ea5cd-e6d8-4360-9905-ba4d0e36f33a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449777393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1449777393
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.1382218461
Short name T2224
Test name
Test status
Simulation time 8754885797 ps
CPU time 90.33 seconds
Started Jul 29 07:56:11 PM PDT 24
Finished Jul 29 07:57:42 PM PDT 24
Peak memory 573940 kb
Host smart-f00fd7db-8c21-447c-bd00-5c9386845034
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382218461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1382218461
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.2841243603
Short name T1764
Test name
Test status
Simulation time 4586194292 ps
CPU time 71.61 seconds
Started Jul 29 07:56:11 PM PDT 24
Finished Jul 29 07:57:23 PM PDT 24
Peak memory 573928 kb
Host smart-264323ca-baa4-40a1-9364-06e8bbf44f07
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841243603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2841243603
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.3609633206
Short name T1614
Test name
Test status
Simulation time 49921676 ps
CPU time 6.26 seconds
Started Jul 29 07:56:10 PM PDT 24
Finished Jul 29 07:56:17 PM PDT 24
Peak memory 573896 kb
Host smart-6539ae34-6f6b-4609-adeb-709b41f8b994
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609633206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay
s.3609633206
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all.1764360125
Short name T2002
Test name
Test status
Simulation time 11210694414 ps
CPU time 462.61 seconds
Started Jul 29 07:56:08 PM PDT 24
Finished Jul 29 08:03:51 PM PDT 24
Peak memory 576076 kb
Host smart-8809e191-1bb7-49cf-b0b2-da9754a691b4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764360125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1764360125
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.163531149
Short name T2602
Test name
Test status
Simulation time 2609836286 ps
CPU time 189.35 seconds
Started Jul 29 07:56:10 PM PDT 24
Finished Jul 29 07:59:19 PM PDT 24
Peak memory 576080 kb
Host smart-793242d9-19ca-49d8-b134-6259b5488b3c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163531149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.163531149
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.3546673836
Short name T2362
Test name
Test status
Simulation time 5607329758 ps
CPU time 431.82 seconds
Started Jul 29 07:56:12 PM PDT 24
Finished Jul 29 08:03:24 PM PDT 24
Peak memory 575992 kb
Host smart-8bb55320-d775-428d-9d0c-da905e92d82d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546673836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all
_with_rand_reset.3546673836
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.141990240
Short name T899
Test name
Test status
Simulation time 523739127 ps
CPU time 75.7 seconds
Started Jul 29 07:56:26 PM PDT 24
Finished Jul 29 07:57:42 PM PDT 24
Peak memory 576604 kb
Host smart-35ea1d91-9111-4f27-8aeb-b8c9a091512e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141990240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all
_with_reset_error.141990240
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.2791477377
Short name T2119
Test name
Test status
Simulation time 298392736 ps
CPU time 35.27 seconds
Started Jul 29 07:56:12 PM PDT 24
Finished Jul 29 07:56:47 PM PDT 24
Peak memory 576032 kb
Host smart-b36ee218-e827-461d-a10e-49220a364ebd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791477377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2791477377
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_access_same_device.673849324
Short name T2785
Test name
Test status
Simulation time 594047686 ps
CPU time 22.84 seconds
Started Jul 29 07:56:21 PM PDT 24
Finished Jul 29 07:56:44 PM PDT 24
Peak memory 575844 kb
Host smart-2240ee97-e2eb-4b0b-9ae1-0c866fdb73b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673849324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.
673849324
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2776362865
Short name T2529
Test name
Test status
Simulation time 39921296366 ps
CPU time 714.78 seconds
Started Jul 29 07:56:24 PM PDT 24
Finished Jul 29 08:08:19 PM PDT 24
Peak memory 576056 kb
Host smart-971e2d7a-b61c-4611-a5b4-d199a7a119a2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776362865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_
device_slow_rsp.2776362865
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.922941335
Short name T1900
Test name
Test status
Simulation time 829525262 ps
CPU time 35.47 seconds
Started Jul 29 07:56:23 PM PDT 24
Finished Jul 29 07:56:59 PM PDT 24
Peak memory 576000 kb
Host smart-b87f2f46-4cd3-4bc4-925a-bca9db507266
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922941335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr
.922941335
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_error_random.2707430138
Short name T1866
Test name
Test status
Simulation time 1380117008 ps
CPU time 49.87 seconds
Started Jul 29 07:56:22 PM PDT 24
Finished Jul 29 07:57:12 PM PDT 24
Peak memory 575992 kb
Host smart-c9acddc4-89fa-4190-b844-b933ac3edae7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707430138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2707430138
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random.2164252052
Short name T2828
Test name
Test status
Simulation time 814112158 ps
CPU time 33.59 seconds
Started Jul 29 07:56:22 PM PDT 24
Finished Jul 29 07:56:55 PM PDT 24
Peak memory 575924 kb
Host smart-905026de-5877-4ebe-a015-4e63137812bc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164252052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.2164252052
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.1078903792
Short name T2775
Test name
Test status
Simulation time 69300891312 ps
CPU time 735.64 seconds
Started Jul 29 07:56:22 PM PDT 24
Finished Jul 29 08:08:38 PM PDT 24
Peak memory 576068 kb
Host smart-aef97e30-b804-4425-922c-fce864c47d61
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078903792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1078903792
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.2026185026
Short name T1832
Test name
Test status
Simulation time 57672974932 ps
CPU time 996.12 seconds
Started Jul 29 07:56:21 PM PDT 24
Finished Jul 29 08:12:58 PM PDT 24
Peak memory 575940 kb
Host smart-f7afca6b-d5ba-4100-b0b0-6f55830d392a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026185026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2026185026
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.3252710543
Short name T2277
Test name
Test status
Simulation time 490441291 ps
CPU time 41.8 seconds
Started Jul 29 07:56:21 PM PDT 24
Finished Jul 29 07:57:03 PM PDT 24
Peak memory 575756 kb
Host smart-651dab0f-6d43-4ea1-a567-3e25979efdfd
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252710543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del
ays.3252710543
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_same_source.2929283582
Short name T2027
Test name
Test status
Simulation time 373723862 ps
CPU time 29.21 seconds
Started Jul 29 07:56:21 PM PDT 24
Finished Jul 29 07:56:51 PM PDT 24
Peak memory 576080 kb
Host smart-b801be6a-20f5-4a57-809d-f2f919ab18ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929283582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.2929283582
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke.2803002825
Short name T2826
Test name
Test status
Simulation time 182866166 ps
CPU time 8.47 seconds
Started Jul 29 07:56:22 PM PDT 24
Finished Jul 29 07:56:31 PM PDT 24
Peak memory 573888 kb
Host smart-ce1aa6c9-aade-4d1f-ae71-d7003b107713
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803002825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2803002825
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.1201259633
Short name T1438
Test name
Test status
Simulation time 9570235259 ps
CPU time 94.29 seconds
Started Jul 29 07:56:22 PM PDT 24
Finished Jul 29 07:57:57 PM PDT 24
Peak memory 574024 kb
Host smart-b9e80c08-746f-4459-908e-33cff80ab431
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201259633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1201259633
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.3277706789
Short name T2016
Test name
Test status
Simulation time 4983635454 ps
CPU time 84.77 seconds
Started Jul 29 07:56:23 PM PDT 24
Finished Jul 29 07:57:48 PM PDT 24
Peak memory 573988 kb
Host smart-023add65-876e-44cb-8c31-b59682e55381
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277706789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3277706789
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1017065902
Short name T619
Test name
Test status
Simulation time 62149240 ps
CPU time 7.11 seconds
Started Jul 29 07:56:25 PM PDT 24
Finished Jul 29 07:56:32 PM PDT 24
Peak memory 574488 kb
Host smart-196475b3-aab0-485a-a72b-e64d6db08997
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017065902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay
s.1017065902
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all.1417818689
Short name T2895
Test name
Test status
Simulation time 9207690558 ps
CPU time 374.45 seconds
Started Jul 29 07:56:21 PM PDT 24
Finished Jul 29 08:02:36 PM PDT 24
Peak memory 576020 kb
Host smart-f2747d32-d249-4ac9-9a61-b74b1cb18f2a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417818689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1417818689
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.3060416781
Short name T2345
Test name
Test status
Simulation time 874571349 ps
CPU time 72 seconds
Started Jul 29 07:56:21 PM PDT 24
Finished Jul 29 07:57:33 PM PDT 24
Peak memory 575868 kb
Host smart-8945f7b3-c6a3-4f4a-be4d-b4e866b166d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060416781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3060416781
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.436489100
Short name T1957
Test name
Test status
Simulation time 66056431 ps
CPU time 39.42 seconds
Started Jul 29 07:56:25 PM PDT 24
Finished Jul 29 07:57:04 PM PDT 24
Peak memory 575964 kb
Host smart-532e448a-9996-4124-b4fb-3da08aac81c5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436489100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_
with_rand_reset.436489100
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3779109517
Short name T2475
Test name
Test status
Simulation time 2389242040 ps
CPU time 222.89 seconds
Started Jul 29 07:56:38 PM PDT 24
Finished Jul 29 08:00:21 PM PDT 24
Peak memory 576080 kb
Host smart-5139ba70-93cc-4670-b322-8440f13858ef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779109517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al
l_with_reset_error.3779109517
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.1168444097
Short name T2121
Test name
Test status
Simulation time 294635756 ps
CPU time 32.57 seconds
Started Jul 29 07:56:24 PM PDT 24
Finished Jul 29 07:56:56 PM PDT 24
Peak memory 575940 kb
Host smart-3bc7d4a8-7dca-4984-bd0b-a7756e677a46
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168444097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1168444097
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_access_same_device.1502269929
Short name T1724
Test name
Test status
Simulation time 178876728 ps
CPU time 14.09 seconds
Started Jul 29 07:56:40 PM PDT 24
Finished Jul 29 07:56:54 PM PDT 24
Peak memory 575880 kb
Host smart-7aac1c6c-579e-47e5-b64a-729cd4a02fcf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502269929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device
.1502269929
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.3571857681
Short name T875
Test name
Test status
Simulation time 20833913792 ps
CPU time 378.7 seconds
Started Jul 29 07:56:40 PM PDT 24
Finished Jul 29 08:02:59 PM PDT 24
Peak memory 576056 kb
Host smart-16f80560-ee0a-4729-8bac-ec90165d66f2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571857681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_
device_slow_rsp.3571857681
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.3912666353
Short name T2476
Test name
Test status
Simulation time 848998084 ps
CPU time 30.19 seconds
Started Jul 29 07:56:38 PM PDT 24
Finished Jul 29 07:57:09 PM PDT 24
Peak memory 576040 kb
Host smart-ba44d618-a937-4b9e-a78e-00695ef43690
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912666353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add
r.3912666353
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_error_random.974906331
Short name T1498
Test name
Test status
Simulation time 1923478927 ps
CPU time 65.85 seconds
Started Jul 29 07:56:38 PM PDT 24
Finished Jul 29 07:57:44 PM PDT 24
Peak memory 575912 kb
Host smart-276b4da1-82d8-43a9-a1cc-4dfe5300f81a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974906331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.974906331
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random.3525978624
Short name T2622
Test name
Test status
Simulation time 220698313 ps
CPU time 11.16 seconds
Started Jul 29 07:56:37 PM PDT 24
Finished Jul 29 07:56:48 PM PDT 24
Peak memory 573892 kb
Host smart-51885c56-e4b0-4016-b5d9-fa7d53421e63
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525978624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.3525978624
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.1348716858
Short name T2822
Test name
Test status
Simulation time 103867882544 ps
CPU time 1046.13 seconds
Started Jul 29 07:56:36 PM PDT 24
Finished Jul 29 08:14:03 PM PDT 24
Peak memory 575916 kb
Host smart-f4cd4e79-deef-431a-a22b-76e3db406653
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348716858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1348716858
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.1117802910
Short name T2350
Test name
Test status
Simulation time 15035941871 ps
CPU time 257.41 seconds
Started Jul 29 07:56:37 PM PDT 24
Finished Jul 29 08:00:54 PM PDT 24
Peak memory 576052 kb
Host smart-7004774f-0c9e-45e3-a844-9865c84a7d45
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117802910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1117802910
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.896974115
Short name T1946
Test name
Test status
Simulation time 460396443 ps
CPU time 41.69 seconds
Started Jul 29 07:56:36 PM PDT 24
Finished Jul 29 07:57:17 PM PDT 24
Peak memory 575692 kb
Host smart-dee0cd79-eb33-4ca8-97a9-a9d7bce68dc3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896974115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_dela
ys.896974115
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_same_source.484945665
Short name T522
Test name
Test status
Simulation time 429249171 ps
CPU time 29.39 seconds
Started Jul 29 07:56:39 PM PDT 24
Finished Jul 29 07:57:08 PM PDT 24
Peak memory 575808 kb
Host smart-165a1f88-7482-4167-9cdd-ddd19ed87ce7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484945665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.484945665
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke.2538679126
Short name T2489
Test name
Test status
Simulation time 41444500 ps
CPU time 6.08 seconds
Started Jul 29 07:56:37 PM PDT 24
Finished Jul 29 07:56:43 PM PDT 24
Peak memory 573892 kb
Host smart-4e16183d-b613-4496-9d86-817eb6166820
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538679126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2538679126
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.1379420547
Short name T2412
Test name
Test status
Simulation time 9115563782 ps
CPU time 91.78 seconds
Started Jul 29 07:56:37 PM PDT 24
Finished Jul 29 07:58:09 PM PDT 24
Peak memory 574640 kb
Host smart-d886b277-b72f-4c16-9f49-1b069670942f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379420547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1379420547
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1695314696
Short name T2005
Test name
Test status
Simulation time 5147868343 ps
CPU time 89.64 seconds
Started Jul 29 07:56:38 PM PDT 24
Finished Jul 29 07:58:08 PM PDT 24
Peak memory 573912 kb
Host smart-e508a3d9-e37a-405e-b310-8904a22b84d1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695314696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1695314696
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.4199709506
Short name T2317
Test name
Test status
Simulation time 47298314 ps
CPU time 6.64 seconds
Started Jul 29 07:56:36 PM PDT 24
Finished Jul 29 07:56:43 PM PDT 24
Peak memory 573820 kb
Host smart-e2448522-8238-482e-a62e-ac833238e482
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199709506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay
s.4199709506
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all.3512760797
Short name T2344
Test name
Test status
Simulation time 15996391997 ps
CPU time 593.47 seconds
Started Jul 29 07:56:40 PM PDT 24
Finished Jul 29 08:06:33 PM PDT 24
Peak memory 576080 kb
Host smart-c2bf3111-39c1-4280-9566-6e4d749dc6a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512760797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3512760797
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.3794947038
Short name T2053
Test name
Test status
Simulation time 10886061406 ps
CPU time 388.64 seconds
Started Jul 29 07:56:38 PM PDT 24
Finished Jul 29 08:03:07 PM PDT 24
Peak memory 576804 kb
Host smart-dd577c13-ac14-4c31-badf-c4bc40ae70e7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794947038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3794947038
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.3600472217
Short name T2572
Test name
Test status
Simulation time 1906278395 ps
CPU time 203.54 seconds
Started Jul 29 07:56:39 PM PDT 24
Finished Jul 29 08:00:02 PM PDT 24
Peak memory 576812 kb
Host smart-6f2c4dc4-9890-4b22-820f-320f46044da1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600472217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al
l_with_reset_error.3600472217
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.3468466667
Short name T430
Test name
Test status
Simulation time 1229975325 ps
CPU time 54 seconds
Started Jul 29 07:56:37 PM PDT 24
Finished Jul 29 07:57:31 PM PDT 24
Peak memory 576028 kb
Host smart-296a1dc3-e670-43ae-9481-7eb658181d74
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468466667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3468466667
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.184436720
Short name T416
Test name
Test status
Simulation time 30225857023 ps
CPU time 5315.19 seconds
Started Jul 29 07:49:59 PM PDT 24
Finished Jul 29 09:18:35 PM PDT 24
Peak memory 594312 kb
Host smart-35474ce7-cc62-4f82-9940-79bb72848950
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184436720 -assert nopostproc +UVM_TESTNAME=chip_b
ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.chip_csr_aliasing.184436720
Directory /workspace/4.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.1592535634
Short name T2829
Test name
Test status
Simulation time 5961874940 ps
CPU time 481.37 seconds
Started Jul 29 07:50:01 PM PDT 24
Finished Jul 29 07:58:03 PM PDT 24
Peak memory 592824 kb
Host smart-07d61c85-9df7-4214-bd3f-6819511fcc9d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592535634 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.1592535634
Directory /workspace/4.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.267989583
Short name T1534
Test name
Test status
Simulation time 11181573780 ps
CPU time 727.34 seconds
Started Jul 29 07:50:03 PM PDT 24
Finished Jul 29 08:02:10 PM PDT 24
Peak memory 640592 kb
Host smart-d4a9a68a-dffe-49cc-9179-5c122b921ea4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267989583 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.267989583
Directory /workspace/4.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_rw.1831325788
Short name T2618
Test name
Test status
Simulation time 6064158384 ps
CPU time 658.11 seconds
Started Jul 29 07:50:03 PM PDT 24
Finished Jul 29 08:01:02 PM PDT 24
Peak memory 599124 kb
Host smart-0ca1f478-cb2a-4b93-8d95-e5f1834b8296
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831325788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.1831325788
Directory /workspace/4.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.811454027
Short name T1908
Test name
Test status
Simulation time 15890328058 ps
CPU time 1929.57 seconds
Started Jul 29 07:49:59 PM PDT 24
Finished Jul 29 08:22:09 PM PDT 24
Peak memory 592948 kb
Host smart-100cf69d-d1ae-414e-8210-1168e22837e1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811454027 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.chip_same_csr_outstanding.811454027
Directory /workspace/4.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.chip_tl_errors.2626892271
Short name T2240
Test name
Test status
Simulation time 3286369780 ps
CPU time 115.44 seconds
Started Jul 29 07:50:11 PM PDT 24
Finished Jul 29 07:52:06 PM PDT 24
Peak memory 603732 kb
Host smart-82f3133b-dbed-4535-9971-c0b1bfd7e155
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626892271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.2626892271
Directory /workspace/4.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_access_same_device.2091822596
Short name T856
Test name
Test status
Simulation time 1899018595 ps
CPU time 85.28 seconds
Started Jul 29 07:50:00 PM PDT 24
Finished Jul 29 07:51:26 PM PDT 24
Peak memory 575972 kb
Host smart-2efa8097-9ad8-446d-8fad-b4e5a3d0ccba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091822596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.
2091822596
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.759923045
Short name T2058
Test name
Test status
Simulation time 18083658535 ps
CPU time 299.92 seconds
Started Jul 29 07:49:57 PM PDT 24
Finished Jul 29 07:54:57 PM PDT 24
Peak memory 575964 kb
Host smart-1c4baf54-705a-4c76-9022-f9939d5d81d6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759923045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_de
vice_slow_rsp.759923045
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.1751239255
Short name T1516
Test name
Test status
Simulation time 1054376420 ps
CPU time 40.18 seconds
Started Jul 29 07:50:11 PM PDT 24
Finished Jul 29 07:50:52 PM PDT 24
Peak memory 576004 kb
Host smart-b5334897-9038-4862-b75f-d6efc794c521
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751239255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr
.1751239255
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_error_random.2535713176
Short name T1533
Test name
Test status
Simulation time 294109337 ps
CPU time 12.11 seconds
Started Jul 29 07:50:01 PM PDT 24
Finished Jul 29 07:50:13 PM PDT 24
Peak memory 576004 kb
Host smart-a8f2c922-dab0-41e0-b684-fb16db1db1fa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535713176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2535713176
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random.1137318826
Short name T2914
Test name
Test status
Simulation time 2055001982 ps
CPU time 69.81 seconds
Started Jul 29 07:50:08 PM PDT 24
Finished Jul 29 07:51:18 PM PDT 24
Peak memory 575772 kb
Host smart-4cdaf1b5-4d7f-4535-bc96-c3ee4e1a25c6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137318826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.1137318826
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.437403612
Short name T2580
Test name
Test status
Simulation time 16809883667 ps
CPU time 163.64 seconds
Started Jul 29 07:49:58 PM PDT 24
Finished Jul 29 07:52:42 PM PDT 24
Peak memory 575952 kb
Host smart-f88bd4ac-2c72-41c1-9c3b-29804805beca
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437403612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.437403612
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.143698615
Short name T1849
Test name
Test status
Simulation time 54311827179 ps
CPU time 896.67 seconds
Started Jul 29 07:50:01 PM PDT 24
Finished Jul 29 08:04:58 PM PDT 24
Peak memory 576064 kb
Host smart-54fc0e2c-13de-4387-a6fe-930a66e402f1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143698615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.143698615
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.3863857612
Short name T1531
Test name
Test status
Simulation time 385839173 ps
CPU time 34.12 seconds
Started Jul 29 07:50:00 PM PDT 24
Finished Jul 29 07:50:34 PM PDT 24
Peak memory 575896 kb
Host smart-ecaddcb0-5e28-4e4a-9174-449c6137756e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863857612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela
ys.3863857612
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_same_source.1094658671
Short name T2610
Test name
Test status
Simulation time 165997887 ps
CPU time 14.65 seconds
Started Jul 29 07:49:59 PM PDT 24
Finished Jul 29 07:50:14 PM PDT 24
Peak memory 575828 kb
Host smart-54b132b8-6beb-462c-ad6c-902f31bcc075
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094658671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1094658671
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke.1837630396
Short name T435
Test name
Test status
Simulation time 209044003 ps
CPU time 8.15 seconds
Started Jul 29 07:50:11 PM PDT 24
Finished Jul 29 07:50:19 PM PDT 24
Peak memory 574516 kb
Host smart-6ec3115c-a876-46ba-8091-15be2cbc97f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837630396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1837630396
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.1181711590
Short name T2638
Test name
Test status
Simulation time 8677294819 ps
CPU time 87.46 seconds
Started Jul 29 07:50:04 PM PDT 24
Finished Jul 29 07:51:31 PM PDT 24
Peak memory 574596 kb
Host smart-a18ead4f-2af5-4a53-b975-07ef44a90e40
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181711590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1181711590
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.1495513351
Short name T1795
Test name
Test status
Simulation time 5151657035 ps
CPU time 89.96 seconds
Started Jul 29 07:49:58 PM PDT 24
Finished Jul 29 07:51:28 PM PDT 24
Peak memory 574008 kb
Host smart-2509d31e-104b-47e3-9ece-859d8f42c791
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495513351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1495513351
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.3855967809
Short name T1706
Test name
Test status
Simulation time 53277608 ps
CPU time 6.2 seconds
Started Jul 29 07:50:02 PM PDT 24
Finished Jul 29 07:50:09 PM PDT 24
Peak memory 574548 kb
Host smart-32f1b5df-afd0-4f23-a257-11ffff4bafca
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855967809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays
.3855967809
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all.1564895782
Short name T436
Test name
Test status
Simulation time 1658849270 ps
CPU time 117.74 seconds
Started Jul 29 07:49:59 PM PDT 24
Finished Jul 29 07:51:57 PM PDT 24
Peak memory 576756 kb
Host smart-b6bb0bb2-1eb2-4c81-8d5a-ae54cf6a76f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564895782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1564895782
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.1963239091
Short name T2725
Test name
Test status
Simulation time 2562692857 ps
CPU time 212.33 seconds
Started Jul 29 07:50:04 PM PDT 24
Finished Jul 29 07:53:37 PM PDT 24
Peak memory 576848 kb
Host smart-d97cd038-3f9f-4233-a6d0-e96f3bd70e78
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963239091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1963239091
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.3604825481
Short name T2751
Test name
Test status
Simulation time 1779908481 ps
CPU time 279.93 seconds
Started Jul 29 07:50:03 PM PDT 24
Finished Jul 29 07:54:44 PM PDT 24
Peak memory 576788 kb
Host smart-307ff7fb-a457-440b-9d90-c066348ea246
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604825481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_
with_rand_reset.3604825481
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.669293245
Short name T1536
Test name
Test status
Simulation time 9107763275 ps
CPU time 348.04 seconds
Started Jul 29 07:50:02 PM PDT 24
Finished Jul 29 07:55:50 PM PDT 24
Peak memory 576008 kb
Host smart-8c572a38-6c08-496a-b17c-393d12ece6d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669293245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_
with_reset_error.669293245
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.1692882966
Short name T693
Test name
Test status
Simulation time 333517237 ps
CPU time 15.5 seconds
Started Jul 29 07:50:00 PM PDT 24
Finished Jul 29 07:50:15 PM PDT 24
Peak memory 575868 kb
Host smart-0befc96c-5aee-4482-b50a-057a0072bab6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692882966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1692882966
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_access_same_device.2216394636
Short name T2237
Test name
Test status
Simulation time 959630891 ps
CPU time 39.14 seconds
Started Jul 29 07:56:50 PM PDT 24
Finished Jul 29 07:57:29 PM PDT 24
Peak memory 575760 kb
Host smart-ca6a54e5-196c-431a-9a1e-32e079e314d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216394636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device
.2216394636
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.656022191
Short name T1630
Test name
Test status
Simulation time 28279685660 ps
CPU time 460.76 seconds
Started Jul 29 07:56:51 PM PDT 24
Finished Jul 29 08:04:32 PM PDT 24
Peak memory 576084 kb
Host smart-d41bae59-91eb-45ce-b62a-8f19555f26ab
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656022191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_d
evice_slow_rsp.656022191
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.2513243276
Short name T1753
Test name
Test status
Simulation time 52739854 ps
CPU time 5.82 seconds
Started Jul 29 07:56:53 PM PDT 24
Finished Jul 29 07:56:59 PM PDT 24
Peak memory 573920 kb
Host smart-4628961c-2a9e-445f-bfdf-845b24fa8d22
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513243276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add
r.2513243276
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_error_random.2369657763
Short name T2333
Test name
Test status
Simulation time 2589770088 ps
CPU time 84.95 seconds
Started Jul 29 07:56:53 PM PDT 24
Finished Jul 29 07:58:18 PM PDT 24
Peak memory 576016 kb
Host smart-e864b5df-636b-46ea-abce-afc428646f1d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369657763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2369657763
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random.3456502919
Short name T2552
Test name
Test status
Simulation time 2688113564 ps
CPU time 100.22 seconds
Started Jul 29 07:56:50 PM PDT 24
Finished Jul 29 07:58:30 PM PDT 24
Peak memory 575900 kb
Host smart-e28e130f-0cc7-4854-a772-5f2c7999c098
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456502919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.3456502919
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.3796876357
Short name T2853
Test name
Test status
Simulation time 18142931437 ps
CPU time 203.53 seconds
Started Jul 29 07:56:48 PM PDT 24
Finished Jul 29 08:00:12 PM PDT 24
Peak memory 576008 kb
Host smart-18dd484f-9777-4e6b-ab0d-aafbfe9354d4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796876357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3796876357
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.1024441474
Short name T2596
Test name
Test status
Simulation time 3900554104 ps
CPU time 60.43 seconds
Started Jul 29 07:56:48 PM PDT 24
Finished Jul 29 07:57:49 PM PDT 24
Peak memory 574604 kb
Host smart-917c4f3c-58bf-45df-8704-9c4d2ee27e75
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024441474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1024441474
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.1451888798
Short name T1779
Test name
Test status
Simulation time 558965113 ps
CPU time 49.33 seconds
Started Jul 29 07:56:51 PM PDT 24
Finished Jul 29 07:57:41 PM PDT 24
Peak memory 575976 kb
Host smart-6f3e0222-5d21-43b0-9fdd-b418c18488b1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451888798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del
ays.1451888798
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_same_source.3431286204
Short name T1846
Test name
Test status
Simulation time 2717496488 ps
CPU time 72.91 seconds
Started Jul 29 07:56:52 PM PDT 24
Finished Jul 29 07:58:05 PM PDT 24
Peak memory 575992 kb
Host smart-324dd266-8757-4f04-8aa9-4c339847929f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431286204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3431286204
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke.1162482821
Short name T2843
Test name
Test status
Simulation time 135392898 ps
CPU time 7.23 seconds
Started Jul 29 07:56:37 PM PDT 24
Finished Jul 29 07:56:45 PM PDT 24
Peak memory 573788 kb
Host smart-4e75e494-83ec-4a48-9146-6948762cc719
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162482821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1162482821
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.2609904725
Short name T2773
Test name
Test status
Simulation time 11054578048 ps
CPU time 113.43 seconds
Started Jul 29 07:56:54 PM PDT 24
Finished Jul 29 07:58:47 PM PDT 24
Peak memory 573984 kb
Host smart-5a036bcd-6b8c-4e3a-a726-6d6c859c271b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609904725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2609904725
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.1895568735
Short name T2506
Test name
Test status
Simulation time 4271733205 ps
CPU time 68.28 seconds
Started Jul 29 07:56:54 PM PDT 24
Finished Jul 29 07:58:02 PM PDT 24
Peak memory 574596 kb
Host smart-295eeb58-9033-47c4-bf84-51241d23a63e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895568735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1895568735
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.3347307499
Short name T2424
Test name
Test status
Simulation time 44599870 ps
CPU time 6.1 seconds
Started Jul 29 07:56:54 PM PDT 24
Finished Jul 29 07:57:00 PM PDT 24
Peak memory 574580 kb
Host smart-685340cb-823b-4987-99ec-1dd609982e42
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347307499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay
s.3347307499
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all.3518132843
Short name T2099
Test name
Test status
Simulation time 10730254794 ps
CPU time 363.35 seconds
Started Jul 29 07:56:50 PM PDT 24
Finished Jul 29 08:02:53 PM PDT 24
Peak memory 576840 kb
Host smart-b56c4789-4810-4354-a89c-33b5770f2240
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518132843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3518132843
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.3028693644
Short name T1796
Test name
Test status
Simulation time 10917820901 ps
CPU time 343.23 seconds
Started Jul 29 07:56:53 PM PDT 24
Finished Jul 29 08:02:36 PM PDT 24
Peak memory 576924 kb
Host smart-9f6a3c47-a20e-4eb4-9c14-b8f851642bda
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028693644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3028693644
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.3090581549
Short name T1951
Test name
Test status
Simulation time 309643135 ps
CPU time 115.64 seconds
Started Jul 29 07:56:48 PM PDT 24
Finished Jul 29 07:58:44 PM PDT 24
Peak memory 575960 kb
Host smart-4e036c48-1c37-4e29-a0aa-9a1355549e79
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090581549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all
_with_rand_reset.3090581549
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.754988912
Short name T2533
Test name
Test status
Simulation time 3479752657 ps
CPU time 318.33 seconds
Started Jul 29 07:56:53 PM PDT 24
Finished Jul 29 08:02:11 PM PDT 24
Peak memory 576120 kb
Host smart-02104212-093f-4017-b6e9-f67e74c6e8cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754988912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all
_with_reset_error.754988912
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.1413477558
Short name T1853
Test name
Test status
Simulation time 440545057 ps
CPU time 19.37 seconds
Started Jul 29 07:56:54 PM PDT 24
Finished Jul 29 07:57:13 PM PDT 24
Peak memory 575900 kb
Host smart-6f775197-97ac-4aa7-8e31-5319626a124c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413477558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1413477558
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_access_same_device.2926143904
Short name T2911
Test name
Test status
Simulation time 365476240 ps
CPU time 19.14 seconds
Started Jul 29 07:56:53 PM PDT 24
Finished Jul 29 07:57:12 PM PDT 24
Peak memory 575956 kb
Host smart-70aebfd0-f2fb-4974-8ff3-37f3dba871d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926143904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device
.2926143904
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.263703943
Short name T2889
Test name
Test status
Simulation time 127278662145 ps
CPU time 2317.21 seconds
Started Jul 29 07:56:53 PM PDT 24
Finished Jul 29 08:35:30 PM PDT 24
Peak memory 576128 kb
Host smart-1f781b8a-cb68-4052-a4a1-d4c91a44928b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263703943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_d
evice_slow_rsp.263703943
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.3455401741
Short name T1428
Test name
Test status
Simulation time 196457803 ps
CPU time 21.61 seconds
Started Jul 29 07:57:01 PM PDT 24
Finished Jul 29 07:57:23 PM PDT 24
Peak memory 575860 kb
Host smart-2f1f31e5-527b-4061-8436-3ff2feb12354
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455401741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add
r.3455401741
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_error_random.2938120826
Short name T1713
Test name
Test status
Simulation time 1096041226 ps
CPU time 36.75 seconds
Started Jul 29 07:56:59 PM PDT 24
Finished Jul 29 07:57:36 PM PDT 24
Peak memory 576008 kb
Host smart-04997e68-ea97-40ab-92d1-e9fbeb0bdedd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938120826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2938120826
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random.3060537003
Short name T527
Test name
Test status
Simulation time 316776607 ps
CPU time 28.54 seconds
Started Jul 29 07:56:50 PM PDT 24
Finished Jul 29 07:57:18 PM PDT 24
Peak memory 575836 kb
Host smart-f9a747b2-da16-4059-b3d1-85db2f275bd3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060537003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.3060537003
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.785468355
Short name T1432
Test name
Test status
Simulation time 12720782793 ps
CPU time 144.46 seconds
Started Jul 29 07:56:49 PM PDT 24
Finished Jul 29 07:59:14 PM PDT 24
Peak memory 575920 kb
Host smart-8c8417f6-a881-45d3-a032-233d52caa37d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785468355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.785468355
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.450462659
Short name T1754
Test name
Test status
Simulation time 50551766726 ps
CPU time 846.14 seconds
Started Jul 29 07:56:49 PM PDT 24
Finished Jul 29 08:10:55 PM PDT 24
Peak memory 575868 kb
Host smart-d19838dc-c025-4576-8317-3a5182ffe24f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450462659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.450462659
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.2447938092
Short name T582
Test name
Test status
Simulation time 276737049 ps
CPU time 28.7 seconds
Started Jul 29 07:56:48 PM PDT 24
Finished Jul 29 07:57:17 PM PDT 24
Peak memory 575828 kb
Host smart-1e3f4262-10c7-42d9-863e-df19e60958e0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447938092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del
ays.2447938092
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_same_source.1818385213
Short name T1871
Test name
Test status
Simulation time 1871885317 ps
CPU time 54.23 seconds
Started Jul 29 07:57:01 PM PDT 24
Finished Jul 29 07:57:56 PM PDT 24
Peak memory 576036 kb
Host smart-0309d48a-e680-46eb-87bd-c65931d78156
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818385213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1818385213
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke.3898455932
Short name T2465
Test name
Test status
Simulation time 193689466 ps
CPU time 8.84 seconds
Started Jul 29 07:56:48 PM PDT 24
Finished Jul 29 07:56:57 PM PDT 24
Peak memory 573768 kb
Host smart-09c24847-c10f-4802-9eef-946027dc6dfb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898455932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3898455932
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.2837825793
Short name T2880
Test name
Test status
Simulation time 6678575506 ps
CPU time 69.63 seconds
Started Jul 29 07:56:51 PM PDT 24
Finished Jul 29 07:58:00 PM PDT 24
Peak memory 573992 kb
Host smart-b415c0d8-8d5b-4d99-b08b-da3f576a1815
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837825793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2837825793
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.4173367770
Short name T2668
Test name
Test status
Simulation time 3698718621 ps
CPU time 65.29 seconds
Started Jul 29 07:56:53 PM PDT 24
Finished Jul 29 07:57:59 PM PDT 24
Peak memory 573928 kb
Host smart-0d60c01e-0afc-4541-afa1-feb64e5de787
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173367770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.4173367770
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.1830440356
Short name T2613
Test name
Test status
Simulation time 49948065 ps
CPU time 6.47 seconds
Started Jul 29 07:56:49 PM PDT 24
Finished Jul 29 07:56:55 PM PDT 24
Peak memory 573864 kb
Host smart-d50c3389-e593-48c6-a8f5-952ff843e67c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830440356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay
s.1830440356
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all.733323874
Short name T2768
Test name
Test status
Simulation time 12823040943 ps
CPU time 525.1 seconds
Started Jul 29 07:57:02 PM PDT 24
Finished Jul 29 08:05:47 PM PDT 24
Peak memory 576088 kb
Host smart-7fd91b5a-a241-42e8-b8bc-ec2601ea133d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733323874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.733323874
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.3882067898
Short name T1740
Test name
Test status
Simulation time 5366191740 ps
CPU time 381.32 seconds
Started Jul 29 07:57:00 PM PDT 24
Finished Jul 29 08:03:22 PM PDT 24
Peak memory 576860 kb
Host smart-e6846512-8540-4ca8-a8cb-258c83d451a9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882067898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3882067898
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.1619507354
Short name T2695
Test name
Test status
Simulation time 3211508070 ps
CPU time 263.92 seconds
Started Jul 29 07:57:01 PM PDT 24
Finished Jul 29 08:01:25 PM PDT 24
Peak memory 576844 kb
Host smart-af09a7dd-c03f-4aa2-938e-dd0532a59ed9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619507354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all
_with_rand_reset.1619507354
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.2630275223
Short name T2154
Test name
Test status
Simulation time 1225672294 ps
CPU time 172.85 seconds
Started Jul 29 07:57:01 PM PDT 24
Finished Jul 29 07:59:54 PM PDT 24
Peak memory 576944 kb
Host smart-5dd85da2-1365-4754-8b22-8d92f8e53207
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630275223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al
l_with_reset_error.2630275223
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.1568035553
Short name T2208
Test name
Test status
Simulation time 1279906667 ps
CPU time 52.59 seconds
Started Jul 29 07:57:00 PM PDT 24
Finished Jul 29 07:57:53 PM PDT 24
Peak memory 576080 kb
Host smart-8aea4d50-1ddc-425c-8284-e6149f1012b9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568035553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1568035553
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_access_same_device.3110684415
Short name T2074
Test name
Test status
Simulation time 842764371 ps
CPU time 32.98 seconds
Started Jul 29 07:56:59 PM PDT 24
Finished Jul 29 07:57:33 PM PDT 24
Peak memory 575980 kb
Host smart-36788e14-c61e-4fc3-8802-71475d6430d2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110684415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device
.3110684415
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.1795147168
Short name T838
Test name
Test status
Simulation time 144825382175 ps
CPU time 2480.68 seconds
Started Jul 29 07:57:19 PM PDT 24
Finished Jul 29 08:38:40 PM PDT 24
Peak memory 576096 kb
Host smart-b10bc9b8-2dd7-4c22-9dab-3ff8eda0b8b0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795147168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_
device_slow_rsp.1795147168
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.3509349591
Short name T2235
Test name
Test status
Simulation time 287273127 ps
CPU time 25.68 seconds
Started Jul 29 07:57:05 PM PDT 24
Finished Jul 29 07:57:30 PM PDT 24
Peak memory 575580 kb
Host smart-f8a3b091-79cc-44b4-8d7c-06e9f919bdd0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509349591 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add
r.3509349591
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_error_random.900627628
Short name T2926
Test name
Test status
Simulation time 356533413 ps
CPU time 27.2 seconds
Started Jul 29 07:57:19 PM PDT 24
Finished Jul 29 07:57:46 PM PDT 24
Peak memory 575984 kb
Host smart-ed630b05-f9a1-4459-9bb2-de123101aae8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900627628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.900627628
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random.3359615978
Short name T2583
Test name
Test status
Simulation time 1342156617 ps
CPU time 43.65 seconds
Started Jul 29 07:57:03 PM PDT 24
Finished Jul 29 07:57:47 PM PDT 24
Peak memory 575952 kb
Host smart-ef18eecf-6998-4eba-94a5-83eadec43fd1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359615978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.3359615978
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.1676406504
Short name T1843
Test name
Test status
Simulation time 50475941008 ps
CPU time 544.52 seconds
Started Jul 29 07:57:19 PM PDT 24
Finished Jul 29 08:06:24 PM PDT 24
Peak memory 576128 kb
Host smart-5b4e2eff-922c-4daa-94e9-3e24f1442c58
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676406504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1676406504
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.652335601
Short name T1714
Test name
Test status
Simulation time 62872362127 ps
CPU time 1066.87 seconds
Started Jul 29 07:57:00 PM PDT 24
Finished Jul 29 08:14:48 PM PDT 24
Peak memory 575952 kb
Host smart-811432dd-c67d-45fc-924f-c7ce9c923135
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652335601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.652335601
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.1331545460
Short name T2516
Test name
Test status
Simulation time 546477223 ps
CPU time 46.52 seconds
Started Jul 29 07:57:02 PM PDT 24
Finished Jul 29 07:57:49 PM PDT 24
Peak memory 575956 kb
Host smart-e1dcd3c2-29f2-49bc-9f3b-1fdf3304dbd5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331545460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del
ays.1331545460
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_same_source.2774127807
Short name T2655
Test name
Test status
Simulation time 88161346 ps
CPU time 9.4 seconds
Started Jul 29 07:57:05 PM PDT 24
Finished Jul 29 07:57:14 PM PDT 24
Peak memory 575852 kb
Host smart-daf00435-f072-4a4d-aa0c-8e61b9263eef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774127807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2774127807
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke.1046676034
Short name T1409
Test name
Test status
Simulation time 37219817 ps
CPU time 5.41 seconds
Started Jul 29 07:57:19 PM PDT 24
Finished Jul 29 07:57:25 PM PDT 24
Peak memory 573932 kb
Host smart-5f0848fe-8800-401c-84ef-48dab0ebee1c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046676034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1046676034
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.410004022
Short name T1410
Test name
Test status
Simulation time 9303036280 ps
CPU time 100.22 seconds
Started Jul 29 07:57:01 PM PDT 24
Finished Jul 29 07:58:41 PM PDT 24
Peak memory 573980 kb
Host smart-d2046fbe-74af-4f31-8191-f6b2e6489a6d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410004022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.410004022
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.1994386036
Short name T2398
Test name
Test status
Simulation time 6276699006 ps
CPU time 108.31 seconds
Started Jul 29 07:57:04 PM PDT 24
Finished Jul 29 07:58:52 PM PDT 24
Peak memory 573772 kb
Host smart-98a3ac4c-5cf8-401e-8f76-daef73735c46
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994386036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1994386036
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.3460365896
Short name T2892
Test name
Test status
Simulation time 42102811 ps
CPU time 6.09 seconds
Started Jul 29 07:57:01 PM PDT 24
Finished Jul 29 07:57:07 PM PDT 24
Peak memory 574512 kb
Host smart-2a47c4b7-8abd-4e96-abd8-e10baa5205bf
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460365896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay
s.3460365896
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all.3947960326
Short name T2340
Test name
Test status
Simulation time 1945824753 ps
CPU time 175.32 seconds
Started Jul 29 07:57:01 PM PDT 24
Finished Jul 29 07:59:56 PM PDT 24
Peak memory 576728 kb
Host smart-197940bd-6e0b-4c45-86a9-028c7ecaaa62
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947960326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3947960326
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.2664992170
Short name T2671
Test name
Test status
Simulation time 7481423114 ps
CPU time 243.59 seconds
Started Jul 29 07:57:00 PM PDT 24
Finished Jul 29 08:01:04 PM PDT 24
Peak memory 575996 kb
Host smart-3b8c67b5-704b-4ab4-a539-62be50342da6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664992170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2664992170
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2833178884
Short name T886
Test name
Test status
Simulation time 10458122666 ps
CPU time 665.28 seconds
Started Jul 29 07:57:05 PM PDT 24
Finished Jul 29 08:08:10 PM PDT 24
Peak memory 576032 kb
Host smart-ecaf5fbf-6546-4359-93ff-0f08012319a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833178884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all
_with_rand_reset.2833178884
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.511917317
Short name T626
Test name
Test status
Simulation time 1073673289 ps
CPU time 125.42 seconds
Started Jul 29 07:56:59 PM PDT 24
Finished Jul 29 07:59:05 PM PDT 24
Peak memory 576760 kb
Host smart-f48493c4-05bf-4ff6-a199-0b610d5c0ad4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511917317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all
_with_reset_error.511917317
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.582449979
Short name T2253
Test name
Test status
Simulation time 700701188 ps
CPU time 29.17 seconds
Started Jul 29 07:57:18 PM PDT 24
Finished Jul 29 07:57:48 PM PDT 24
Peak memory 576092 kb
Host smart-fa8e1db3-e497-47a1-b97d-ab93fb4f7181
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582449979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.582449979
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_access_same_device.1227116053
Short name T2374
Test name
Test status
Simulation time 220286507 ps
CPU time 17.7 seconds
Started Jul 29 07:57:10 PM PDT 24
Finished Jul 29 07:57:28 PM PDT 24
Peak memory 575988 kb
Host smart-55a6402e-c1c7-4585-be07-2cbe25d0199f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227116053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device
.1227116053
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1906828988
Short name T1845
Test name
Test status
Simulation time 89516451895 ps
CPU time 1667.55 seconds
Started Jul 29 07:57:09 PM PDT 24
Finished Jul 29 08:24:57 PM PDT 24
Peak memory 576120 kb
Host smart-990863eb-1af8-4c78-9d81-f302e6850c7e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906828988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_
device_slow_rsp.1906828988
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.84434951
Short name T1500
Test name
Test status
Simulation time 122320073 ps
CPU time 13.63 seconds
Started Jul 29 07:57:09 PM PDT 24
Finished Jul 29 07:57:23 PM PDT 24
Peak memory 575948 kb
Host smart-a5639dc3-90ba-4e75-82fd-25a98ff4aaca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84434951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.84434951
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_error_random.3886571268
Short name T656
Test name
Test status
Simulation time 1093084133 ps
CPU time 35.42 seconds
Started Jul 29 07:57:12 PM PDT 24
Finished Jul 29 07:57:47 PM PDT 24
Peak memory 575936 kb
Host smart-0cb3c8fe-cc11-4596-8f2e-54102ff90c8e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886571268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3886571268
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random.1219388967
Short name T2336
Test name
Test status
Simulation time 245102219 ps
CPU time 23.24 seconds
Started Jul 29 07:57:01 PM PDT 24
Finished Jul 29 07:57:24 PM PDT 24
Peak memory 575772 kb
Host smart-61314d3f-b3b3-472d-8a1a-4ce70a058e2e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219388967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.1219388967
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.107355855
Short name T1673
Test name
Test status
Simulation time 30849779942 ps
CPU time 321.44 seconds
Started Jul 29 07:57:09 PM PDT 24
Finished Jul 29 08:02:31 PM PDT 24
Peak memory 576036 kb
Host smart-93f38784-fea0-4802-98ed-bea17dbe64ab
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107355855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.107355855
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.836367294
Short name T2823
Test name
Test status
Simulation time 46615838823 ps
CPU time 814.19 seconds
Started Jul 29 07:57:15 PM PDT 24
Finished Jul 29 08:10:49 PM PDT 24
Peak memory 576016 kb
Host smart-703411f5-194f-4011-94e2-cf0a815b1cbb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836367294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.836367294
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.2764097918
Short name T1683
Test name
Test status
Simulation time 135624983 ps
CPU time 13.56 seconds
Started Jul 29 07:57:03 PM PDT 24
Finished Jul 29 07:57:17 PM PDT 24
Peak memory 575964 kb
Host smart-647df8a1-be72-40da-af5c-e99aa142344e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764097918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del
ays.2764097918
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_same_source.3137013015
Short name T1674
Test name
Test status
Simulation time 50291128 ps
CPU time 6.89 seconds
Started Jul 29 07:57:11 PM PDT 24
Finished Jul 29 07:57:18 PM PDT 24
Peak memory 574584 kb
Host smart-cc00b734-5efd-4284-bdad-ffea4d31533c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137013015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3137013015
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke.17300100
Short name T1541
Test name
Test status
Simulation time 185839003 ps
CPU time 8.52 seconds
Started Jul 29 07:57:02 PM PDT 24
Finished Jul 29 07:57:11 PM PDT 24
Peak memory 573848 kb
Host smart-903287e8-3006-44e4-a57d-53ac28888b47
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17300100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.17300100
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.520086490
Short name T1493
Test name
Test status
Simulation time 8334720644 ps
CPU time 84.17 seconds
Started Jul 29 07:56:59 PM PDT 24
Finished Jul 29 07:58:24 PM PDT 24
Peak memory 574640 kb
Host smart-7c26fe61-f62e-4b5a-92a8-a8690f334233
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520086490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.520086490
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.113811797
Short name T2470
Test name
Test status
Simulation time 4107213958 ps
CPU time 69.68 seconds
Started Jul 29 07:57:00 PM PDT 24
Finished Jul 29 07:58:10 PM PDT 24
Peak memory 574548 kb
Host smart-0411ec8f-e62d-4288-8024-6afd30bbdccb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113811797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.113811797
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.4101689023
Short name T2026
Test name
Test status
Simulation time 51918513 ps
CPU time 5.92 seconds
Started Jul 29 07:57:18 PM PDT 24
Finished Jul 29 07:57:24 PM PDT 24
Peak memory 573840 kb
Host smart-d435d709-68a5-4ceb-98e1-b62b1044eeb0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101689023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay
s.4101689023
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all.370171644
Short name T2882
Test name
Test status
Simulation time 11527840641 ps
CPU time 432.37 seconds
Started Jul 29 07:57:16 PM PDT 24
Finished Jul 29 08:04:28 PM PDT 24
Peak memory 576108 kb
Host smart-5138bdb9-5f1a-44aa-87c7-02f9d37853d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370171644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.370171644
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.4016549337
Short name T848
Test name
Test status
Simulation time 7558140761 ps
CPU time 286.21 seconds
Started Jul 29 07:57:10 PM PDT 24
Finished Jul 29 08:01:57 PM PDT 24
Peak memory 576020 kb
Host smart-81540572-aaf3-4148-95ab-7f825a66f089
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016549337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.4016549337
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.1793308781
Short name T2711
Test name
Test status
Simulation time 464291329 ps
CPU time 140.51 seconds
Started Jul 29 07:57:10 PM PDT 24
Finished Jul 29 07:59:30 PM PDT 24
Peak memory 576764 kb
Host smart-648c00ca-2724-4482-bbe1-f0bbc4235f72
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793308781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all
_with_rand_reset.1793308781
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.1207635704
Short name T2116
Test name
Test status
Simulation time 6697150219 ps
CPU time 354.39 seconds
Started Jul 29 07:57:10 PM PDT 24
Finished Jul 29 08:03:05 PM PDT 24
Peak memory 576824 kb
Host smart-cb840191-f996-4013-88b6-4630b57554e9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207635704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al
l_with_reset_error.1207635704
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.698490233
Short name T513
Test name
Test status
Simulation time 592895985 ps
CPU time 27.9 seconds
Started Jul 29 07:57:12 PM PDT 24
Finished Jul 29 07:57:40 PM PDT 24
Peak memory 575888 kb
Host smart-9cd366ea-cfc8-4093-b39e-eef689f37b0d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698490233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.698490233
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_access_same_device.3886378312
Short name T2647
Test name
Test status
Simulation time 702346544 ps
CPU time 55.54 seconds
Started Jul 29 07:57:20 PM PDT 24
Finished Jul 29 07:58:15 PM PDT 24
Peak memory 575928 kb
Host smart-8aeb8ffb-710c-4c27-b1df-4970249efd87
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886378312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device
.3886378312
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.2838092129
Short name T2782
Test name
Test status
Simulation time 76666333969 ps
CPU time 1361.66 seconds
Started Jul 29 07:57:21 PM PDT 24
Finished Jul 29 08:20:04 PM PDT 24
Peak memory 576088 kb
Host smart-a23db5f3-8a7b-4d60-b40e-d4879c087fde
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838092129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_
device_slow_rsp.2838092129
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.3278836464
Short name T2207
Test name
Test status
Simulation time 707012834 ps
CPU time 28.9 seconds
Started Jul 29 07:57:22 PM PDT 24
Finished Jul 29 07:57:51 PM PDT 24
Peak memory 575956 kb
Host smart-bb93a77b-e1c4-42c0-9027-e8a627e9f773
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278836464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add
r.3278836464
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_error_random.3990383668
Short name T74
Test name
Test status
Simulation time 744470123 ps
CPU time 27.68 seconds
Started Jul 29 07:57:27 PM PDT 24
Finished Jul 29 07:57:54 PM PDT 24
Peak memory 575932 kb
Host smart-14556269-c0bb-4423-be71-681ebbff79c3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990383668 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3990383668
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random.2472304829
Short name T577
Test name
Test status
Simulation time 1453990501 ps
CPU time 54.08 seconds
Started Jul 29 07:57:22 PM PDT 24
Finished Jul 29 07:58:16 PM PDT 24
Peak memory 575940 kb
Host smart-3e5693a1-1797-4eef-9e35-98bdcfc7879e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472304829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.2472304829
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.1189897901
Short name T2620
Test name
Test status
Simulation time 73049004806 ps
CPU time 821.6 seconds
Started Jul 29 07:57:21 PM PDT 24
Finished Jul 29 08:11:03 PM PDT 24
Peak memory 575876 kb
Host smart-ce572890-fc28-4ec3-af8f-a2c413268dd6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189897901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1189897901
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.3888508241
Short name T1787
Test name
Test status
Simulation time 57554955125 ps
CPU time 944.31 seconds
Started Jul 29 07:57:23 PM PDT 24
Finished Jul 29 08:13:07 PM PDT 24
Peak memory 575680 kb
Host smart-98776eac-93fc-4146-9434-2a2525f2a1e3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888508241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3888508241
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.207355106
Short name T2162
Test name
Test status
Simulation time 420491905 ps
CPU time 31.46 seconds
Started Jul 29 07:57:19 PM PDT 24
Finished Jul 29 07:57:51 PM PDT 24
Peak memory 575964 kb
Host smart-d945395a-a6ed-4ef6-949e-14f4d2166c88
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207355106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_dela
ys.207355106
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_same_source.1661755191
Short name T2893
Test name
Test status
Simulation time 321638232 ps
CPU time 22.93 seconds
Started Jul 29 07:57:22 PM PDT 24
Finished Jul 29 07:57:45 PM PDT 24
Peak memory 575812 kb
Host smart-11c7f14b-7ca7-4829-8307-adce17360158
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661755191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1661755191
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke.2135626087
Short name T2859
Test name
Test status
Simulation time 33035862 ps
CPU time 5.81 seconds
Started Jul 29 07:57:13 PM PDT 24
Finished Jul 29 07:57:19 PM PDT 24
Peak memory 573984 kb
Host smart-7452e5c5-48f4-4506-b825-488296218e35
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135626087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2135626087
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.1881189617
Short name T2139
Test name
Test status
Simulation time 8413084152 ps
CPU time 88.28 seconds
Started Jul 29 07:57:22 PM PDT 24
Finished Jul 29 07:58:51 PM PDT 24
Peak memory 574652 kb
Host smart-88d13b30-a35b-46aa-ac14-a4d1c0950721
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881189617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1881189617
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.3861336312
Short name T1396
Test name
Test status
Simulation time 5977076939 ps
CPU time 104.65 seconds
Started Jul 29 07:57:21 PM PDT 24
Finished Jul 29 07:59:06 PM PDT 24
Peak memory 573996 kb
Host smart-7123b5b9-0687-4a42-aa8a-3b5abafdb043
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861336312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.3861336312
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.3770329880
Short name T2922
Test name
Test status
Simulation time 45929218 ps
CPU time 6.07 seconds
Started Jul 29 07:57:12 PM PDT 24
Finished Jul 29 07:57:18 PM PDT 24
Peak memory 574532 kb
Host smart-51051b02-b3db-475a-946c-35ae5e698a87
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770329880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay
s.3770329880
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all.1781855460
Short name T2512
Test name
Test status
Simulation time 7772420780 ps
CPU time 319.02 seconds
Started Jul 29 07:57:25 PM PDT 24
Finished Jul 29 08:02:44 PM PDT 24
Peak memory 576832 kb
Host smart-04cf392b-2415-4bd5-b1a3-badecaa676b0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781855460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1781855460
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.228307844
Short name T2832
Test name
Test status
Simulation time 6727290598 ps
CPU time 260.52 seconds
Started Jul 29 07:57:28 PM PDT 24
Finished Jul 29 08:01:49 PM PDT 24
Peak memory 575972 kb
Host smart-572ae019-13d0-40db-b3c4-9c2eacad4540
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228307844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.228307844
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.2754154840
Short name T2931
Test name
Test status
Simulation time 434943090 ps
CPU time 121.68 seconds
Started Jul 29 07:57:22 PM PDT 24
Finished Jul 29 07:59:24 PM PDT 24
Peak memory 576764 kb
Host smart-f3646400-3ae4-4692-b69c-e83e3a0e6d03
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754154840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all
_with_rand_reset.2754154840
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.2346416232
Short name T901
Test name
Test status
Simulation time 7304924 ps
CPU time 11.18 seconds
Started Jul 29 07:57:28 PM PDT 24
Finished Jul 29 07:57:39 PM PDT 24
Peak memory 573836 kb
Host smart-c4a94327-7b90-4fa3-900b-c1550754f861
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346416232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al
l_with_reset_error.2346416232
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.4136240959
Short name T2385
Test name
Test status
Simulation time 543535047 ps
CPU time 22.82 seconds
Started Jul 29 07:57:22 PM PDT 24
Finished Jul 29 07:57:45 PM PDT 24
Peak memory 576024 kb
Host smart-2b9ebe9e-7106-4848-bcef-a704393250a8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136240959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.4136240959
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_access_same_device.670879341
Short name T2920
Test name
Test status
Simulation time 494775364 ps
CPU time 20.81 seconds
Started Jul 29 07:57:27 PM PDT 24
Finished Jul 29 07:57:48 PM PDT 24
Peak memory 575932 kb
Host smart-76dcc882-14fd-4ce6-bf44-4133d3396764
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670879341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.
670879341
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.3268132695
Short name T1699
Test name
Test status
Simulation time 85364917510 ps
CPU time 1529.48 seconds
Started Jul 29 07:57:29 PM PDT 24
Finished Jul 29 08:22:58 PM PDT 24
Peak memory 575960 kb
Host smart-fbd7fd8e-357e-4481-88bd-29ba887243d4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268132695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_
device_slow_rsp.3268132695
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.1142203563
Short name T2191
Test name
Test status
Simulation time 90716394 ps
CPU time 6.97 seconds
Started Jul 29 07:57:36 PM PDT 24
Finished Jul 29 07:57:44 PM PDT 24
Peak memory 574516 kb
Host smart-bc733a94-d9a3-49b4-87f3-838b44a4bac5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142203563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add
r.1142203563
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_error_random.2733087835
Short name T2129
Test name
Test status
Simulation time 275178820 ps
CPU time 23.77 seconds
Started Jul 29 07:57:30 PM PDT 24
Finished Jul 29 07:57:54 PM PDT 24
Peak memory 575940 kb
Host smart-48538ef3-4ea9-4707-8e98-975f5bd17ce7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733087835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2733087835
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random.2612311059
Short name T2196
Test name
Test status
Simulation time 366884659 ps
CPU time 32.73 seconds
Started Jul 29 07:57:29 PM PDT 24
Finished Jul 29 07:58:01 PM PDT 24
Peak memory 576032 kb
Host smart-53354c20-3053-4b16-804f-5cfa2102890e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612311059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.2612311059
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.1101688458
Short name T519
Test name
Test status
Simulation time 94097739969 ps
CPU time 967.24 seconds
Started Jul 29 07:57:34 PM PDT 24
Finished Jul 29 08:13:41 PM PDT 24
Peak memory 576116 kb
Host smart-7cef3b64-c9f5-4dd5-a095-f2fb6755441f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101688458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.1101688458
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.3454546432
Short name T2292
Test name
Test status
Simulation time 77357204232 ps
CPU time 1390.39 seconds
Started Jul 29 07:57:35 PM PDT 24
Finished Jul 29 08:20:46 PM PDT 24
Peak memory 576120 kb
Host smart-5dbb9005-7ed8-4d58-8d90-d40a5ee910a6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454546432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3454546432
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.2199311038
Short name T493
Test name
Test status
Simulation time 568879034 ps
CPU time 47.69 seconds
Started Jul 29 07:57:28 PM PDT 24
Finished Jul 29 07:58:16 PM PDT 24
Peak memory 575808 kb
Host smart-a1ba789f-65e7-4f17-a33c-d9e808470b7c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199311038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del
ays.2199311038
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_same_source.1107573173
Short name T2921
Test name
Test status
Simulation time 368774113 ps
CPU time 13.84 seconds
Started Jul 29 07:57:30 PM PDT 24
Finished Jul 29 07:57:44 PM PDT 24
Peak memory 575852 kb
Host smart-3e2c0ad0-d14f-4e65-9f1e-db413b9120e6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107573173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1107573173
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke.1479609498
Short name T1772
Test name
Test status
Simulation time 57271506 ps
CPU time 7.13 seconds
Started Jul 29 07:57:27 PM PDT 24
Finished Jul 29 07:57:34 PM PDT 24
Peak memory 574612 kb
Host smart-432e3857-2a7b-4765-8495-b156b132fa0c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479609498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1479609498
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.3098554395
Short name T1675
Test name
Test status
Simulation time 8024537340 ps
CPU time 78.6 seconds
Started Jul 29 07:57:28 PM PDT 24
Finished Jul 29 07:58:46 PM PDT 24
Peak memory 573976 kb
Host smart-3ab1dc4f-f843-444b-8465-64a6106e2003
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098554395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.3098554395
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.1758107481
Short name T2404
Test name
Test status
Simulation time 4938211530 ps
CPU time 76.11 seconds
Started Jul 29 07:57:33 PM PDT 24
Finished Jul 29 07:58:50 PM PDT 24
Peak memory 574000 kb
Host smart-0a7d90d8-4d1e-4349-bc04-77330f8bdd96
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758107481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1758107481
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.1611007706
Short name T1550
Test name
Test status
Simulation time 45177100 ps
CPU time 6.41 seconds
Started Jul 29 07:57:35 PM PDT 24
Finished Jul 29 07:57:42 PM PDT 24
Peak memory 574572 kb
Host smart-3f8a291d-a07a-4af3-becc-3cd3524c6b83
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611007706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay
s.1611007706
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all.432152781
Short name T2305
Test name
Test status
Simulation time 4541683037 ps
CPU time 293.3 seconds
Started Jul 29 07:57:46 PM PDT 24
Finished Jul 29 08:02:39 PM PDT 24
Peak memory 576052 kb
Host smart-f18443f5-3a03-4641-9e0d-6933505e3210
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432152781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.432152781
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.186900177
Short name T1831
Test name
Test status
Simulation time 860462114 ps
CPU time 56.81 seconds
Started Jul 29 07:57:45 PM PDT 24
Finished Jul 29 07:58:42 PM PDT 24
Peak memory 575876 kb
Host smart-6fb402c3-d518-4f9a-8b9d-886e2dc6ff34
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186900177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.186900177
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.2480978323
Short name T517
Test name
Test status
Simulation time 13958580729 ps
CPU time 644.78 seconds
Started Jul 29 07:57:36 PM PDT 24
Finished Jul 29 08:08:21 PM PDT 24
Peak memory 576060 kb
Host smart-5599f3fa-77c3-4b14-b56a-1107d43c685a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480978323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all
_with_rand_reset.2480978323
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.264613639
Short name T900
Test name
Test status
Simulation time 2326643857 ps
CPU time 278.45 seconds
Started Jul 29 07:57:37 PM PDT 24
Finished Jul 29 08:02:16 PM PDT 24
Peak memory 576844 kb
Host smart-4816063f-ded7-4233-a4f6-719e7c617d31
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264613639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all
_with_reset_error.264613639
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.2253795630
Short name T2815
Test name
Test status
Simulation time 53164355 ps
CPU time 8.82 seconds
Started Jul 29 07:57:30 PM PDT 24
Finished Jul 29 07:57:39 PM PDT 24
Peak memory 576032 kb
Host smart-6b6dc08a-1149-4715-92f8-2ae86269e496
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253795630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2253795630
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_access_same_device.146200637
Short name T1867
Test name
Test status
Simulation time 531897167 ps
CPU time 42.57 seconds
Started Jul 29 07:57:46 PM PDT 24
Finished Jul 29 07:58:29 PM PDT 24
Peak memory 575932 kb
Host smart-af324119-18f1-4627-92c8-ab42d8b3ce7a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146200637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.
146200637
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.3668717744
Short name T474
Test name
Test status
Simulation time 94068352621 ps
CPU time 1729.31 seconds
Started Jul 29 07:57:45 PM PDT 24
Finished Jul 29 08:26:35 PM PDT 24
Peak memory 576148 kb
Host smart-ffda15b9-a554-4730-bc98-f68ee98f1588
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668717744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_
device_slow_rsp.3668717744
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.3279036902
Short name T2012
Test name
Test status
Simulation time 768123192 ps
CPU time 32.27 seconds
Started Jul 29 07:57:51 PM PDT 24
Finished Jul 29 07:58:24 PM PDT 24
Peak memory 576024 kb
Host smart-2807db43-ad4b-4635-9419-2daac6af9c68
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279036902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add
r.3279036902
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_error_random.3950657563
Short name T2626
Test name
Test status
Simulation time 348039725 ps
CPU time 30.63 seconds
Started Jul 29 07:57:52 PM PDT 24
Finished Jul 29 07:58:23 PM PDT 24
Peak memory 575996 kb
Host smart-f37e394d-36cf-4567-b580-1293619aae00
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950657563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3950657563
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random.3697414847
Short name T2447
Test name
Test status
Simulation time 217195164 ps
CPU time 19.12 seconds
Started Jul 29 07:57:45 PM PDT 24
Finished Jul 29 07:58:04 PM PDT 24
Peak memory 575908 kb
Host smart-9eea16b8-e31c-4751-8fbd-3fe5d43e957b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697414847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.3697414847
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.1732319287
Short name T2457
Test name
Test status
Simulation time 80581722883 ps
CPU time 816.61 seconds
Started Jul 29 07:57:44 PM PDT 24
Finished Jul 29 08:11:20 PM PDT 24
Peak memory 575952 kb
Host smart-76083367-cef1-4f8f-b877-bfaf7e7fa391
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732319287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1732319287
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.1602912463
Short name T2636
Test name
Test status
Simulation time 10475393401 ps
CPU time 171.75 seconds
Started Jul 29 07:57:45 PM PDT 24
Finished Jul 29 08:00:36 PM PDT 24
Peak memory 576004 kb
Host smart-baddf95d-fd4e-45ec-8265-6ce143da6f3a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602912463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1602912463
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.3258197293
Short name T1745
Test name
Test status
Simulation time 315244886 ps
CPU time 26.77 seconds
Started Jul 29 07:57:45 PM PDT 24
Finished Jul 29 07:58:12 PM PDT 24
Peak memory 575900 kb
Host smart-fc28c337-ca26-4fb0-a6b4-f1130e3a477e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258197293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del
ays.3258197293
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_same_source.3559617360
Short name T1485
Test name
Test status
Simulation time 163776904 ps
CPU time 13.69 seconds
Started Jul 29 07:57:44 PM PDT 24
Finished Jul 29 07:57:58 PM PDT 24
Peak memory 575960 kb
Host smart-f819f93b-3d1d-4605-9b68-36290a2f2598
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559617360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3559617360
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke.4074658479
Short name T1646
Test name
Test status
Simulation time 218450426 ps
CPU time 9.21 seconds
Started Jul 29 07:57:46 PM PDT 24
Finished Jul 29 07:57:55 PM PDT 24
Peak memory 573904 kb
Host smart-2c5f82ce-2d41-45ca-b39b-8991e5b2f47b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074658479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.4074658479
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.1301349727
Short name T633
Test name
Test status
Simulation time 8559163401 ps
CPU time 91.71 seconds
Started Jul 29 07:57:37 PM PDT 24
Finished Jul 29 07:59:09 PM PDT 24
Peak memory 573936 kb
Host smart-5c9f1313-be51-4068-a724-5df3816a98c1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301349727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1301349727
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.1759141136
Short name T2048
Test name
Test status
Simulation time 5792954103 ps
CPU time 95.32 seconds
Started Jul 29 07:57:36 PM PDT 24
Finished Jul 29 07:59:11 PM PDT 24
Peak memory 574652 kb
Host smart-80e89c21-ebfe-48f1-9e4a-7905012b814f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759141136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1759141136
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.1537137024
Short name T1567
Test name
Test status
Simulation time 60111306 ps
CPU time 7.28 seconds
Started Jul 29 07:57:36 PM PDT 24
Finished Jul 29 07:57:44 PM PDT 24
Peak memory 574488 kb
Host smart-a51118f9-9a99-4179-b315-3ccf14207512
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537137024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay
s.1537137024
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all.3973760744
Short name T631
Test name
Test status
Simulation time 15343140829 ps
CPU time 552.09 seconds
Started Jul 29 07:57:53 PM PDT 24
Finished Jul 29 08:07:05 PM PDT 24
Peak memory 576144 kb
Host smart-933be8eb-1e27-4a2b-a935-b7398d703406
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973760744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3973760744
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.3909345692
Short name T2939
Test name
Test status
Simulation time 4180636300 ps
CPU time 296.01 seconds
Started Jul 29 07:57:51 PM PDT 24
Finished Jul 29 08:02:47 PM PDT 24
Peak memory 576344 kb
Host smart-9aa6a69a-4c4f-4d74-b76d-33573f7ff945
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909345692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3909345692
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.2911265925
Short name T2598
Test name
Test status
Simulation time 5356536955 ps
CPU time 730.12 seconds
Started Jul 29 07:57:52 PM PDT 24
Finished Jul 29 08:10:02 PM PDT 24
Peak memory 575916 kb
Host smart-07ca6840-f519-4adb-8550-f078c7cbf78a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911265925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all
_with_rand_reset.2911265925
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.2605332064
Short name T2456
Test name
Test status
Simulation time 76111043 ps
CPU time 30.19 seconds
Started Jul 29 07:57:51 PM PDT 24
Finished Jul 29 07:58:21 PM PDT 24
Peak memory 575916 kb
Host smart-2b5984cf-fbfd-4dd6-92db-960b3e7ce737
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605332064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al
l_with_reset_error.2605332064
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.3029287954
Short name T1995
Test name
Test status
Simulation time 69536036 ps
CPU time 10.43 seconds
Started Jul 29 07:57:52 PM PDT 24
Finished Jul 29 07:58:03 PM PDT 24
Peak memory 575856 kb
Host smart-d0137d4b-aa0b-42a3-a92d-bfa18613a504
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029287954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3029287954
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_access_same_device.2189667899
Short name T1937
Test name
Test status
Simulation time 1942613044 ps
CPU time 76.61 seconds
Started Jul 29 07:58:03 PM PDT 24
Finished Jul 29 07:59:19 PM PDT 24
Peak memory 575804 kb
Host smart-a54fc0bc-cff2-4946-9f89-fb845488f48c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189667899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device
.2189667899
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.3237087693
Short name T2030
Test name
Test status
Simulation time 23084209180 ps
CPU time 404.33 seconds
Started Jul 29 07:58:00 PM PDT 24
Finished Jul 29 08:04:45 PM PDT 24
Peak memory 575952 kb
Host smart-2de1cd1c-3393-49f8-897e-444267d43930
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237087693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_
device_slow_rsp.3237087693
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.2379093982
Short name T1809
Test name
Test status
Simulation time 280456953 ps
CPU time 13.71 seconds
Started Jul 29 07:58:00 PM PDT 24
Finished Jul 29 07:58:14 PM PDT 24
Peak memory 575936 kb
Host smart-43f847d5-8147-4dc1-8cd9-c80642983248
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379093982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add
r.2379093982
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_error_random.1379569940
Short name T2912
Test name
Test status
Simulation time 1413917908 ps
CPU time 51.86 seconds
Started Jul 29 07:58:00 PM PDT 24
Finished Jul 29 07:58:52 PM PDT 24
Peak memory 576024 kb
Host smart-044be11a-0172-4282-9dc8-26c52fedf732
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379569940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1379569940
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random.100983962
Short name T525
Test name
Test status
Simulation time 711809273 ps
CPU time 26.55 seconds
Started Jul 29 07:57:54 PM PDT 24
Finished Jul 29 07:58:20 PM PDT 24
Peak memory 575932 kb
Host smart-40b69a0d-5ccb-4713-baff-d37de5e63af1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100983962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.100983962
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.279121920
Short name T2071
Test name
Test status
Simulation time 88409701942 ps
CPU time 963.76 seconds
Started Jul 29 07:57:51 PM PDT 24
Finished Jul 29 08:13:55 PM PDT 24
Peak memory 576008 kb
Host smart-cd95f38f-29e8-45cc-8c8e-2dceb49eec77
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279121920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.279121920
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.1310153353
Short name T1776
Test name
Test status
Simulation time 7446921678 ps
CPU time 125.55 seconds
Started Jul 29 07:57:53 PM PDT 24
Finished Jul 29 07:59:59 PM PDT 24
Peak memory 576192 kb
Host smart-4e95b153-24a7-49d6-9339-7638e9303492
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310153353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1310153353
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.827117711
Short name T2726
Test name
Test status
Simulation time 510216178 ps
CPU time 45.46 seconds
Started Jul 29 07:57:53 PM PDT 24
Finished Jul 29 07:58:38 PM PDT 24
Peak memory 575788 kb
Host smart-91938d14-f5b1-4da3-9d5b-92856b24dd1d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827117711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_dela
ys.827117711
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_same_source.1179415596
Short name T1907
Test name
Test status
Simulation time 540774817 ps
CPU time 43.85 seconds
Started Jul 29 07:57:59 PM PDT 24
Finished Jul 29 07:58:43 PM PDT 24
Peak memory 575980 kb
Host smart-82059b5a-0de7-4606-ad17-b11167c887e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179415596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1179415596
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke.3768923228
Short name T2717
Test name
Test status
Simulation time 217420044 ps
CPU time 9.33 seconds
Started Jul 29 07:57:53 PM PDT 24
Finished Jul 29 07:58:03 PM PDT 24
Peak memory 573828 kb
Host smart-cc175531-4b76-4bd1-8bbf-81d1d8d0c2a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768923228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3768923228
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.927650979
Short name T1405
Test name
Test status
Simulation time 8614367625 ps
CPU time 88.8 seconds
Started Jul 29 07:57:55 PM PDT 24
Finished Jul 29 07:59:24 PM PDT 24
Peak memory 573992 kb
Host smart-1905c9ad-e323-4cd2-8129-1cd36e474acf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927650979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.927650979
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.2699211923
Short name T1922
Test name
Test status
Simulation time 4705102529 ps
CPU time 78.53 seconds
Started Jul 29 07:57:51 PM PDT 24
Finished Jul 29 07:59:10 PM PDT 24
Peak memory 573936 kb
Host smart-57472af6-8b51-456f-be93-f7a629cfede1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699211923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2699211923
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.1605465915
Short name T1455
Test name
Test status
Simulation time 53257383 ps
CPU time 6.05 seconds
Started Jul 29 07:57:54 PM PDT 24
Finished Jul 29 07:58:00 PM PDT 24
Peak memory 573828 kb
Host smart-84559141-de55-4e9f-954c-89ba53d93486
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605465915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay
s.1605465915
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all.2533102955
Short name T2779
Test name
Test status
Simulation time 2266230223 ps
CPU time 166.28 seconds
Started Jul 29 07:58:00 PM PDT 24
Finished Jul 29 08:00:46 PM PDT 24
Peak memory 576024 kb
Host smart-6a4c1316-9397-4348-9681-cac268549b02
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533102955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2533102955
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.1548304542
Short name T1987
Test name
Test status
Simulation time 3661510606 ps
CPU time 236.2 seconds
Started Jul 29 07:57:58 PM PDT 24
Finished Jul 29 08:01:54 PM PDT 24
Peak memory 576852 kb
Host smart-d9b7e0ad-6ba4-49a5-ac3d-b38c54cf9085
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548304542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1548304542
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.3901876168
Short name T2569
Test name
Test status
Simulation time 929384136 ps
CPU time 353.1 seconds
Started Jul 29 07:58:00 PM PDT 24
Finished Jul 29 08:03:53 PM PDT 24
Peak memory 576804 kb
Host smart-6a1f9aae-c52b-4c31-ace5-1fa4352206eb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901876168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all
_with_rand_reset.3901876168
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3436082266
Short name T882
Test name
Test status
Simulation time 706096415 ps
CPU time 203.99 seconds
Started Jul 29 07:57:59 PM PDT 24
Finished Jul 29 08:01:23 PM PDT 24
Peak memory 576776 kb
Host smart-b1b3dcdb-3c3d-4505-99c6-0a3c1e97ee42
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436082266 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al
l_with_reset_error.3436082266
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.2117247968
Short name T1624
Test name
Test status
Simulation time 983464083 ps
CPU time 41.26 seconds
Started Jul 29 07:57:59 PM PDT 24
Finished Jul 29 07:58:40 PM PDT 24
Peak memory 576024 kb
Host smart-13766267-3f70-4ff6-a6c4-48ecdc893307
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117247968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2117247968
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_access_same_device.2252554911
Short name T2719
Test name
Test status
Simulation time 1703989498 ps
CPU time 66.14 seconds
Started Jul 29 07:58:09 PM PDT 24
Finished Jul 29 07:59:16 PM PDT 24
Peak memory 575840 kb
Host smart-bd2841e9-d147-40dd-bbe1-bdb243034925
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252554911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device
.2252554911
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.3813439793
Short name T1591
Test name
Test status
Simulation time 111185290150 ps
CPU time 2001.56 seconds
Started Jul 29 07:58:10 PM PDT 24
Finished Jul 29 08:31:32 PM PDT 24
Peak memory 576116 kb
Host smart-23d3236e-9d9b-4bdf-81b1-64370aa57ea2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813439793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_
device_slow_rsp.3813439793
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.3389024118
Short name T1487
Test name
Test status
Simulation time 230077378 ps
CPU time 24.92 seconds
Started Jul 29 07:58:18 PM PDT 24
Finished Jul 29 07:58:43 PM PDT 24
Peak memory 575980 kb
Host smart-96b7f1ed-6e48-4d70-b0ab-f1a72f949f7b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389024118 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add
r.3389024118
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_error_random.2278609653
Short name T1424
Test name
Test status
Simulation time 658047692 ps
CPU time 44.04 seconds
Started Jul 29 07:58:11 PM PDT 24
Finished Jul 29 07:58:55 PM PDT 24
Peak memory 575904 kb
Host smart-5d4f5191-1363-4f9c-8b9e-606950efb63b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278609653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2278609653
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random.1352579990
Short name T1742
Test name
Test status
Simulation time 496935003 ps
CPU time 21.6 seconds
Started Jul 29 07:58:10 PM PDT 24
Finished Jul 29 07:58:32 PM PDT 24
Peak memory 576048 kb
Host smart-5e878928-359c-47d4-8685-ab7293ca8640
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352579990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.1352579990
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.2416153119
Short name T2791
Test name
Test status
Simulation time 6751664097 ps
CPU time 71.14 seconds
Started Jul 29 07:58:10 PM PDT 24
Finished Jul 29 07:59:21 PM PDT 24
Peak memory 574752 kb
Host smart-ed8410e6-b535-4825-9e71-29571ffdb8f0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416153119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2416153119
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.3559351579
Short name T2817
Test name
Test status
Simulation time 11406253760 ps
CPU time 183.07 seconds
Started Jul 29 07:58:10 PM PDT 24
Finished Jul 29 08:01:14 PM PDT 24
Peak memory 576032 kb
Host smart-4ff95cd1-4a09-4e97-b83d-9c7f5574b004
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559351579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3559351579
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.2119902207
Short name T518
Test name
Test status
Simulation time 610932377 ps
CPU time 55.19 seconds
Started Jul 29 07:58:11 PM PDT 24
Finished Jul 29 07:59:06 PM PDT 24
Peak memory 575808 kb
Host smart-03e87452-08e5-432a-a159-8c6d6eb4f636
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119902207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del
ays.2119902207
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_same_source.1796029069
Short name T564
Test name
Test status
Simulation time 2570638034 ps
CPU time 76.61 seconds
Started Jul 29 07:58:11 PM PDT 24
Finished Jul 29 07:59:28 PM PDT 24
Peak memory 575960 kb
Host smart-c532a68e-0b43-4664-a8b0-7071f3a762a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796029069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1796029069
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke.3147217029
Short name T1439
Test name
Test status
Simulation time 175132779 ps
CPU time 8.14 seconds
Started Jul 29 07:57:58 PM PDT 24
Finished Jul 29 07:58:06 PM PDT 24
Peak memory 573904 kb
Host smart-f0636aa2-6eb1-4154-830c-d851c7fe3c97
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147217029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3147217029
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.209635057
Short name T1868
Test name
Test status
Simulation time 6851317200 ps
CPU time 68.93 seconds
Started Jul 29 07:58:11 PM PDT 24
Finished Jul 29 07:59:20 PM PDT 24
Peak memory 574044 kb
Host smart-e5b8bf68-4440-4941-ae05-45542e4fa068
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209635057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.209635057
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.674102909
Short name T2201
Test name
Test status
Simulation time 5996886095 ps
CPU time 102.68 seconds
Started Jul 29 07:58:12 PM PDT 24
Finished Jul 29 07:59:54 PM PDT 24
Peak memory 573996 kb
Host smart-c9623ca3-90c8-4044-8003-5f06bd214ff4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674102909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.674102909
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.1241619105
Short name T2051
Test name
Test status
Simulation time 40599548 ps
CPU time 5.46 seconds
Started Jul 29 07:58:03 PM PDT 24
Finished Jul 29 07:58:09 PM PDT 24
Peak memory 573844 kb
Host smart-9134b9de-a72c-4b0b-98ee-6111b1f3d693
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241619105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay
s.1241619105
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all.3846516225
Short name T2698
Test name
Test status
Simulation time 4050408014 ps
CPU time 298.36 seconds
Started Jul 29 07:58:17 PM PDT 24
Finished Jul 29 08:03:16 PM PDT 24
Peak memory 576864 kb
Host smart-1e13b135-6482-427e-bfa6-7d3ad21118f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846516225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3846516225
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.740724427
Short name T1906
Test name
Test status
Simulation time 732628074 ps
CPU time 49.55 seconds
Started Jul 29 07:58:20 PM PDT 24
Finished Jul 29 07:59:10 PM PDT 24
Peak memory 575808 kb
Host smart-f01f1c62-714c-4fb0-b90e-e0ec497c7496
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740724427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.740724427
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.914783842
Short name T2405
Test name
Test status
Simulation time 104528534 ps
CPU time 27.99 seconds
Started Jul 29 07:58:19 PM PDT 24
Finished Jul 29 07:58:47 PM PDT 24
Peak memory 576744 kb
Host smart-082c0b44-4ea6-4fdb-a4cf-afbf93e0e3b0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914783842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_
with_rand_reset.914783842
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.2165324444
Short name T2355
Test name
Test status
Simulation time 3687854006 ps
CPU time 430.73 seconds
Started Jul 29 07:58:16 PM PDT 24
Finished Jul 29 08:05:27 PM PDT 24
Peak memory 576036 kb
Host smart-aea2b396-2664-456f-b527-061e6b752625
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165324444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al
l_with_reset_error.2165324444
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.4934155
Short name T1535
Test name
Test status
Simulation time 445086806 ps
CPU time 21.47 seconds
Started Jul 29 07:58:11 PM PDT 24
Finished Jul 29 07:58:32 PM PDT 24
Peak memory 576068 kb
Host smart-3a1de396-c12d-4576-949c-621179d7c403
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4934155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.4934155
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_access_same_device.1566594370
Short name T1561
Test name
Test status
Simulation time 608836670 ps
CPU time 51.76 seconds
Started Jul 29 07:58:19 PM PDT 24
Finished Jul 29 07:59:10 PM PDT 24
Peak memory 576048 kb
Host smart-47794d5a-6cf0-4514-bdd4-698d62a1eaab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566594370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device
.1566594370
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.384943585
Short name T874
Test name
Test status
Simulation time 67514466510 ps
CPU time 1108.18 seconds
Started Jul 29 07:58:18 PM PDT 24
Finished Jul 29 08:16:46 PM PDT 24
Peak memory 575936 kb
Host smart-4da684b1-a609-459a-b9ad-0e1a2a2f914a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384943585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_d
evice_slow_rsp.384943585
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.482187747
Short name T1573
Test name
Test status
Simulation time 294819464 ps
CPU time 27.61 seconds
Started Jul 29 07:58:27 PM PDT 24
Finished Jul 29 07:58:55 PM PDT 24
Peak memory 576100 kb
Host smart-aac533a0-c0d1-4c1d-881e-849e15ddd5ec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482187747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr
.482187747
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_error_random.263038235
Short name T2112
Test name
Test status
Simulation time 252222320 ps
CPU time 23.41 seconds
Started Jul 29 07:58:26 PM PDT 24
Finished Jul 29 07:58:50 PM PDT 24
Peak memory 576096 kb
Host smart-a9de8829-eb21-4d3d-b663-7086122d5b8a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263038235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.263038235
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random.3803540674
Short name T634
Test name
Test status
Simulation time 1181559358 ps
CPU time 38.5 seconds
Started Jul 29 07:58:18 PM PDT 24
Finished Jul 29 07:58:56 PM PDT 24
Peak memory 575840 kb
Host smart-7ae2a25b-9e60-4e70-85ce-848dc1192f81
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803540674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.3803540674
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.3958261032
Short name T1626
Test name
Test status
Simulation time 31882496131 ps
CPU time 338.38 seconds
Started Jul 29 07:58:18 PM PDT 24
Finished Jul 29 08:03:56 PM PDT 24
Peak memory 576036 kb
Host smart-9a90a72e-fb3f-4e6c-b328-c5ae212af1ef
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958261032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3958261032
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.558242467
Short name T1759
Test name
Test status
Simulation time 34261165646 ps
CPU time 515.69 seconds
Started Jul 29 07:58:22 PM PDT 24
Finished Jul 29 08:06:58 PM PDT 24
Peak memory 576032 kb
Host smart-8bf31d10-65fc-4070-a678-eb0f5d2123d6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558242467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.558242467
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.809033065
Short name T2509
Test name
Test status
Simulation time 525567092 ps
CPU time 38.78 seconds
Started Jul 29 07:58:23 PM PDT 24
Finished Jul 29 07:59:02 PM PDT 24
Peak memory 575748 kb
Host smart-edcafe1b-fad6-431e-8320-9efbc27dbbcc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809033065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_dela
ys.809033065
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_same_source.1607143855
Short name T483
Test name
Test status
Simulation time 1697376263 ps
CPU time 50.59 seconds
Started Jul 29 07:58:28 PM PDT 24
Finished Jul 29 07:59:19 PM PDT 24
Peak memory 575852 kb
Host smart-bc682a26-c0cb-480c-98dc-f099c0a16440
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607143855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1607143855
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke.982582906
Short name T2158
Test name
Test status
Simulation time 214359228 ps
CPU time 9.31 seconds
Started Jul 29 07:58:16 PM PDT 24
Finished Jul 29 07:58:25 PM PDT 24
Peak memory 574560 kb
Host smart-3fa8c39d-e984-405d-9687-329175b40e88
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982582906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.982582906
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.2224509484
Short name T1594
Test name
Test status
Simulation time 7869776097 ps
CPU time 76.35 seconds
Started Jul 29 07:58:23 PM PDT 24
Finished Jul 29 07:59:40 PM PDT 24
Peak memory 574572 kb
Host smart-46a8f2be-0fa6-411e-8e7c-1bce7ebf99ad
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224509484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2224509484
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.3291583215
Short name T1931
Test name
Test status
Simulation time 5374922057 ps
CPU time 89.65 seconds
Started Jul 29 07:58:18 PM PDT 24
Finished Jul 29 07:59:47 PM PDT 24
Peak memory 574000 kb
Host smart-2244b067-89ec-4029-b7d8-194cc4c2b7da
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291583215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3291583215
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3263243927
Short name T2650
Test name
Test status
Simulation time 51925873 ps
CPU time 6.87 seconds
Started Jul 29 07:58:29 PM PDT 24
Finished Jul 29 07:58:36 PM PDT 24
Peak memory 573820 kb
Host smart-2e914bd8-cfbc-4f47-901a-a3b0e4e13551
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263243927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay
s.3263243927
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all.3836700288
Short name T642
Test name
Test status
Simulation time 7094067116 ps
CPU time 284.71 seconds
Started Jul 29 07:58:24 PM PDT 24
Finished Jul 29 08:03:08 PM PDT 24
Peak memory 576000 kb
Host smart-4f626a03-0237-4a0b-8cd6-3d05beeeb05c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836700288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3836700288
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.678058861
Short name T2126
Test name
Test status
Simulation time 5108537685 ps
CPU time 151.37 seconds
Started Jul 29 07:58:24 PM PDT 24
Finished Jul 29 08:00:56 PM PDT 24
Peak memory 576008 kb
Host smart-67f746ad-8608-40f0-b557-0fe0c0a510d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678058861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.678058861
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.4198105851
Short name T2681
Test name
Test status
Simulation time 4822441926 ps
CPU time 646.63 seconds
Started Jul 29 07:58:24 PM PDT 24
Finished Jul 29 08:09:11 PM PDT 24
Peak memory 576840 kb
Host smart-b3a26f2f-a1f0-401c-a00f-97fe47adeca6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198105851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all
_with_rand_reset.4198105851
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.1857574202
Short name T890
Test name
Test status
Simulation time 4483404919 ps
CPU time 341.89 seconds
Started Jul 29 07:58:27 PM PDT 24
Finished Jul 29 08:04:09 PM PDT 24
Peak memory 576076 kb
Host smart-06cc2123-f256-4902-bb1d-f001f236e4b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857574202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al
l_with_reset_error.1857574202
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.356341585
Short name T2351
Test name
Test status
Simulation time 1297525144 ps
CPU time 52.18 seconds
Started Jul 29 07:58:25 PM PDT 24
Finished Jul 29 07:59:18 PM PDT 24
Peak memory 575968 kb
Host smart-083d4fba-e8d2-43a4-896c-54eb7d420e1f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356341585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.356341585
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.874421972
Short name T2132
Test name
Test status
Simulation time 7265365808 ps
CPU time 493.96 seconds
Started Jul 29 07:50:09 PM PDT 24
Finished Jul 29 07:58:23 PM PDT 24
Peak memory 638656 kb
Host smart-36575b57-1394-450c-9472-41be669d30c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874421972 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.874421972
Directory /workspace/5.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.chip_csr_rw.3320333851
Short name T2697
Test name
Test status
Simulation time 6360844126 ps
CPU time 437.12 seconds
Started Jul 29 07:50:15 PM PDT 24
Finished Jul 29 07:57:33 PM PDT 24
Peak memory 599824 kb
Host smart-d5163cc9-605f-4d60-8012-e0c255969bc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320333851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.3320333851
Directory /workspace/5.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.chip_tl_errors.2904741815
Short name T571
Test name
Test status
Simulation time 3285651198 ps
CPU time 179.31 seconds
Started Jul 29 07:50:03 PM PDT 24
Finished Jul 29 07:53:03 PM PDT 24
Peak memory 598720 kb
Host smart-e277c745-053d-44fc-b2e4-d69c6b0bfc15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904741815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.2904741815
Directory /workspace/5.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_access_same_device.1173089125
Short name T2352
Test name
Test status
Simulation time 654243141 ps
CPU time 57.56 seconds
Started Jul 29 07:50:03 PM PDT 24
Finished Jul 29 07:51:01 PM PDT 24
Peak memory 575972 kb
Host smart-abf0506c-6e40-4f05-84e4-0ec476d3e9be
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173089125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.
1173089125
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.3705349106
Short name T2685
Test name
Test status
Simulation time 61458334818 ps
CPU time 1090.59 seconds
Started Jul 29 07:50:03 PM PDT 24
Finished Jul 29 08:08:14 PM PDT 24
Peak memory 576080 kb
Host smart-dfb521a0-0ec9-4cac-8340-93c14cf4da6f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705349106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d
evice_slow_rsp.3705349106
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.3869888763
Short name T1975
Test name
Test status
Simulation time 247377800 ps
CPU time 26.63 seconds
Started Jul 29 07:50:00 PM PDT 24
Finished Jul 29 07:50:27 PM PDT 24
Peak memory 575884 kb
Host smart-54fab72a-a803-4c49-bf69-a3a9183a7376
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869888763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr
.3869888763
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_error_random.1644328952
Short name T1928
Test name
Test status
Simulation time 1086770730 ps
CPU time 35.93 seconds
Started Jul 29 07:50:07 PM PDT 24
Finished Jul 29 07:50:43 PM PDT 24
Peak memory 575736 kb
Host smart-5b0b198b-c5d2-454a-b9d2-6a4a569684c3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644328952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1644328952
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random.1216966440
Short name T530
Test name
Test status
Simulation time 1060538038 ps
CPU time 41.28 seconds
Started Jul 29 07:49:59 PM PDT 24
Finished Jul 29 07:50:41 PM PDT 24
Peak memory 575848 kb
Host smart-33d7e746-4fee-49da-ba28-bede313c58cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216966440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.1216966440
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.3594500264
Short name T2813
Test name
Test status
Simulation time 61777735237 ps
CPU time 690.38 seconds
Started Jul 29 07:50:08 PM PDT 24
Finished Jul 29 08:01:38 PM PDT 24
Peak memory 575876 kb
Host smart-c2572df6-7bc0-4259-b3fe-e83099000680
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594500264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3594500264
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.832937190
Short name T2152
Test name
Test status
Simulation time 7348425860 ps
CPU time 127.38 seconds
Started Jul 29 07:50:07 PM PDT 24
Finished Jul 29 07:52:14 PM PDT 24
Peak memory 575952 kb
Host smart-77878a37-81b6-4b9e-acc7-bcd7d7adc1a1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832937190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.832937190
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.2595958662
Short name T1628
Test name
Test status
Simulation time 536159319 ps
CPU time 42.31 seconds
Started Jul 29 07:50:03 PM PDT 24
Finished Jul 29 07:50:45 PM PDT 24
Peak memory 575788 kb
Host smart-2a75edba-1774-4f0e-847a-6f8ae16a8ed4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595958662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela
ys.2595958662
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_same_source.2279977707
Short name T2656
Test name
Test status
Simulation time 147252387 ps
CPU time 12.96 seconds
Started Jul 29 07:50:07 PM PDT 24
Finished Jul 29 07:50:20 PM PDT 24
Peak memory 575904 kb
Host smart-54c0f8cd-3516-4420-8fbc-0e828f88cb46
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279977707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2279977707
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke.4154189839
Short name T2043
Test name
Test status
Simulation time 50283714 ps
CPU time 6.18 seconds
Started Jul 29 07:50:03 PM PDT 24
Finished Jul 29 07:50:10 PM PDT 24
Peak memory 573896 kb
Host smart-e6762eb1-0884-452b-861d-ac6f84c5f287
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154189839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.4154189839
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.1569348701
Short name T1599
Test name
Test status
Simulation time 9991460878 ps
CPU time 98.18 seconds
Started Jul 29 07:50:04 PM PDT 24
Finished Jul 29 07:51:42 PM PDT 24
Peak memory 574656 kb
Host smart-39c33982-5819-49e7-b504-9ee863bc6f02
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569348701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1569348701
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.493582696
Short name T2434
Test name
Test status
Simulation time 5145860391 ps
CPU time 88.62 seconds
Started Jul 29 07:50:01 PM PDT 24
Finished Jul 29 07:51:30 PM PDT 24
Peak memory 574620 kb
Host smart-3b86fdb8-10bc-4bdc-a60c-dfd5af0a8fec
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493582696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.493582696
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.829893585
Short name T2530
Test name
Test status
Simulation time 47599372 ps
CPU time 5.83 seconds
Started Jul 29 07:50:03 PM PDT 24
Finished Jul 29 07:50:09 PM PDT 24
Peak memory 573852 kb
Host smart-7c7e7df6-ca78-4ae8-97d4-8352b819d277
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829893585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.
829893585
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.247516193
Short name T2263
Test name
Test status
Simulation time 481973319 ps
CPU time 17.29 seconds
Started Jul 29 07:50:15 PM PDT 24
Finished Jul 29 07:50:32 PM PDT 24
Peak memory 576040 kb
Host smart-3215a702-b40c-4dc4-aa83-cf298eadd282
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247516193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.247516193
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.851842231
Short name T511
Test name
Test status
Simulation time 12574753178 ps
CPU time 483 seconds
Started Jul 29 07:50:01 PM PDT 24
Finished Jul 29 07:58:05 PM PDT 24
Peak memory 576844 kb
Host smart-ff6515e1-b8ec-4bd5-b0df-bec7c1a7314e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851842231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_w
ith_rand_reset.851842231
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.2276138305
Short name T1465
Test name
Test status
Simulation time 149085661 ps
CPU time 56.35 seconds
Started Jul 29 07:50:16 PM PDT 24
Finished Jul 29 07:51:12 PM PDT 24
Peak memory 576692 kb
Host smart-8e9bcfe9-4a7b-45f6-8ba9-3eb890e76dce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276138305 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all
_with_reset_error.2276138305
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.3250266400
Short name T698
Test name
Test status
Simulation time 257491740 ps
CPU time 30.84 seconds
Started Jul 29 07:50:09 PM PDT 24
Finished Jul 29 07:50:40 PM PDT 24
Peak memory 575840 kb
Host smart-26d3e85d-64b6-47eb-9add-96df3d21eefc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250266400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3250266400
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_access_same_device.4284921801
Short name T2435
Test name
Test status
Simulation time 1323442502 ps
CPU time 63.15 seconds
Started Jul 29 07:58:31 PM PDT 24
Finished Jul 29 07:59:34 PM PDT 24
Peak memory 576020 kb
Host smart-e4a126c0-2440-4b88-bafb-5185f4107743
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284921801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device
.4284921801
Directory /workspace/50.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.921229595
Short name T2797
Test name
Test status
Simulation time 70630725762 ps
CPU time 1170.49 seconds
Started Jul 29 07:58:36 PM PDT 24
Finished Jul 29 08:18:06 PM PDT 24
Peak memory 575984 kb
Host smart-23800bc9-c30a-4945-a0c8-18111b355c41
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921229595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_d
evice_slow_rsp.921229595
Directory /workspace/50.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.773313796
Short name T1437
Test name
Test status
Simulation time 1148945272 ps
CPU time 44.38 seconds
Started Jul 29 07:58:31 PM PDT 24
Finished Jul 29 07:59:16 PM PDT 24
Peak memory 575936 kb
Host smart-d0a3351d-f00a-4126-90f9-91a96ff6cf24
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773313796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_addr
.773313796
Directory /workspace/50.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_error_random.3782340754
Short name T1901
Test name
Test status
Simulation time 504741864 ps
CPU time 42.19 seconds
Started Jul 29 07:58:33 PM PDT 24
Finished Jul 29 07:59:16 PM PDT 24
Peak memory 575980 kb
Host smart-53b416c9-435a-417a-8e6b-c16984c40271
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782340754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.3782340754
Directory /workspace/50.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random.2863464101
Short name T1898
Test name
Test status
Simulation time 328250833 ps
CPU time 30.89 seconds
Started Jul 29 07:58:26 PM PDT 24
Finished Jul 29 07:58:57 PM PDT 24
Peak memory 576020 kb
Host smart-098c28b8-685b-408e-a12b-a28479326ab1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863464101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.2863464101
Directory /workspace/50.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.2386116442
Short name T2733
Test name
Test status
Simulation time 40790601371 ps
CPU time 436.97 seconds
Started Jul 29 07:58:31 PM PDT 24
Finished Jul 29 08:05:48 PM PDT 24
Peak memory 575996 kb
Host smart-019eb157-174e-463b-97bb-d1a16016f567
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386116442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.2386116442
Directory /workspace/50.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.13729271
Short name T1778
Test name
Test status
Simulation time 30789537291 ps
CPU time 506.78 seconds
Started Jul 29 07:58:32 PM PDT 24
Finished Jul 29 08:06:58 PM PDT 24
Peak memory 576048 kb
Host smart-fa9c50b3-3129-4520-ba50-f2045d5f428d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13729271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.13729271
Directory /workspace/50.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.1644201255
Short name T438
Test name
Test status
Simulation time 254353547 ps
CPU time 22.95 seconds
Started Jul 29 07:58:25 PM PDT 24
Finished Jul 29 07:58:48 PM PDT 24
Peak memory 575896 kb
Host smart-f970de44-06dc-4d16-80d0-fab40c3233fa
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644201255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del
ays.1644201255
Directory /workspace/50.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_same_source.952774269
Short name T2903
Test name
Test status
Simulation time 2610157991 ps
CPU time 79.13 seconds
Started Jul 29 07:58:32 PM PDT 24
Finished Jul 29 07:59:51 PM PDT 24
Peak memory 576076 kb
Host smart-207cf8c6-2c9a-4525-b31b-13ed2450403a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952774269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.952774269
Directory /workspace/50.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke.2301955910
Short name T2522
Test name
Test status
Simulation time 49253068 ps
CPU time 6.28 seconds
Started Jul 29 07:58:25 PM PDT 24
Finished Jul 29 07:58:31 PM PDT 24
Peak memory 573740 kb
Host smart-8248e4c8-cb74-4ea3-b229-2132010e834a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301955910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.2301955910
Directory /workspace/50.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.8564853
Short name T2798
Test name
Test status
Simulation time 8309719075 ps
CPU time 85.7 seconds
Started Jul 29 07:58:26 PM PDT 24
Finished Jul 29 07:59:52 PM PDT 24
Peak memory 574616 kb
Host smart-14903570-416e-40e6-93f2-10a0124c8d76
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8564853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.8564853
Directory /workspace/50.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.1880482811
Short name T2468
Test name
Test status
Simulation time 4112711839 ps
CPU time 65.21 seconds
Started Jul 29 07:58:28 PM PDT 24
Finished Jul 29 07:59:34 PM PDT 24
Peak memory 573944 kb
Host smart-2b5577b4-c587-4ea6-8f7b-e7f8d1f97857
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880482811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.1880482811
Directory /workspace/50.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.3544793214
Short name T1391
Test name
Test status
Simulation time 51970573 ps
CPU time 6.69 seconds
Started Jul 29 07:58:25 PM PDT 24
Finished Jul 29 07:58:32 PM PDT 24
Peak memory 573808 kb
Host smart-4d1f6795-69ea-4b8c-a2b0-835abdf3d1f0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544793214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay
s.3544793214
Directory /workspace/50.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all.3027757530
Short name T2441
Test name
Test status
Simulation time 534263994 ps
CPU time 49.2 seconds
Started Jul 29 07:58:34 PM PDT 24
Finished Jul 29 07:59:24 PM PDT 24
Peak memory 575992 kb
Host smart-b42f45a7-4062-44a9-9eca-08deb199ecd4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027757530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.3027757530
Directory /workspace/50.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.4204143375
Short name T2296
Test name
Test status
Simulation time 1381371100 ps
CPU time 112.96 seconds
Started Jul 29 07:58:33 PM PDT 24
Finished Jul 29 08:00:26 PM PDT 24
Peak memory 576196 kb
Host smart-82ac0cf3-a5e3-4330-990d-58cd3ce91b80
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204143375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.4204143375
Directory /workspace/50.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3835123666
Short name T666
Test name
Test status
Simulation time 308533989 ps
CPU time 144.87 seconds
Started Jul 29 07:58:32 PM PDT 24
Finished Jul 29 08:00:57 PM PDT 24
Peak memory 576752 kb
Host smart-4411f868-2e29-4882-af27-0949a9e76b55
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835123666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all
_with_rand_reset.3835123666
Directory /workspace/50.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.996603233
Short name T2519
Test name
Test status
Simulation time 3652709154 ps
CPU time 340.15 seconds
Started Jul 29 07:58:31 PM PDT 24
Finished Jul 29 08:04:12 PM PDT 24
Peak memory 576868 kb
Host smart-68aa69ce-a066-440c-ac49-91322da048a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996603233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all
_with_reset_error.996603233
Directory /workspace/50.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.2801786801
Short name T1828
Test name
Test status
Simulation time 813494144 ps
CPU time 35.02 seconds
Started Jul 29 07:58:31 PM PDT 24
Finished Jul 29 07:59:07 PM PDT 24
Peak memory 575980 kb
Host smart-c87c8e74-3613-4911-a429-c9963d906829
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801786801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.2801786801
Directory /workspace/50.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_access_same_device.629568936
Short name T2124
Test name
Test status
Simulation time 995781815 ps
CPU time 38.51 seconds
Started Jul 29 07:58:42 PM PDT 24
Finished Jul 29 07:59:20 PM PDT 24
Peak memory 575948 kb
Host smart-5726faec-6020-4225-9f1c-454ecfc4a562
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629568936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device.
629568936
Directory /workspace/51.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.4193663833
Short name T1564
Test name
Test status
Simulation time 923183522 ps
CPU time 36.65 seconds
Started Jul 29 07:58:42 PM PDT 24
Finished Jul 29 07:59:18 PM PDT 24
Peak memory 576024 kb
Host smart-aad9c4f0-d97b-49f0-94c6-33707ef1f9cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193663833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add
r.4193663833
Directory /workspace/51.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_error_random.2850211288
Short name T2830
Test name
Test status
Simulation time 602036424 ps
CPU time 39.16 seconds
Started Jul 29 07:58:38 PM PDT 24
Finished Jul 29 07:59:18 PM PDT 24
Peak memory 576008 kb
Host smart-9b1720ed-eb2d-4037-a356-12635fb7c2f1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850211288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.2850211288
Directory /workspace/51.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random.1363825483
Short name T1586
Test name
Test status
Simulation time 500331623 ps
CPU time 43.42 seconds
Started Jul 29 07:58:33 PM PDT 24
Finished Jul 29 07:59:16 PM PDT 24
Peak memory 575872 kb
Host smart-8dae7448-8d92-4d81-872b-250343fe15d5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363825483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.1363825483
Directory /workspace/51.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.4223914858
Short name T2453
Test name
Test status
Simulation time 9539809378 ps
CPU time 100.51 seconds
Started Jul 29 07:58:32 PM PDT 24
Finished Jul 29 08:00:13 PM PDT 24
Peak memory 576044 kb
Host smart-57c01e13-5948-463b-82e3-17461a6f35c0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223914858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.4223914858
Directory /workspace/51.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.2264021550
Short name T2001
Test name
Test status
Simulation time 17257392037 ps
CPU time 295.39 seconds
Started Jul 29 07:58:39 PM PDT 24
Finished Jul 29 08:03:34 PM PDT 24
Peak memory 575912 kb
Host smart-8f678647-e2c2-4dc8-93b5-0b7612c7a77e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264021550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.2264021550
Directory /workspace/51.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.1894344641
Short name T2347
Test name
Test status
Simulation time 116237712 ps
CPU time 11.38 seconds
Started Jul 29 07:58:36 PM PDT 24
Finished Jul 29 07:58:48 PM PDT 24
Peak memory 575860 kb
Host smart-c0973ac9-75b6-4a23-b7fc-5c49d74a5e06
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894344641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del
ays.1894344641
Directory /workspace/51.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_same_source.3504398718
Short name T1918
Test name
Test status
Simulation time 1033927049 ps
CPU time 30.41 seconds
Started Jul 29 07:58:41 PM PDT 24
Finished Jul 29 07:59:12 PM PDT 24
Peak memory 575828 kb
Host smart-c88938b2-1751-496a-a92c-a37db5037973
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504398718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.3504398718
Directory /workspace/51.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke.879372324
Short name T2812
Test name
Test status
Simulation time 192142790 ps
CPU time 8.56 seconds
Started Jul 29 07:58:32 PM PDT 24
Finished Jul 29 07:58:41 PM PDT 24
Peak memory 573820 kb
Host smart-b29f89fd-16fd-4897-b712-30d9f399ef8b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879372324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.879372324
Directory /workspace/51.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.1049306817
Short name T2054
Test name
Test status
Simulation time 9484197830 ps
CPU time 98.03 seconds
Started Jul 29 07:58:32 PM PDT 24
Finished Jul 29 08:00:10 PM PDT 24
Peak memory 574540 kb
Host smart-36dba610-168c-42e2-8553-39a8d5e2cdf4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049306817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.1049306817
Directory /workspace/51.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1406095096
Short name T2754
Test name
Test status
Simulation time 5133525258 ps
CPU time 89.59 seconds
Started Jul 29 07:58:33 PM PDT 24
Finished Jul 29 08:00:02 PM PDT 24
Peak memory 574672 kb
Host smart-dcdab668-2d74-483c-a2fa-bf19ddb48424
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406095096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.1406095096
Directory /workspace/51.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.1911289257
Short name T1885
Test name
Test status
Simulation time 44508440 ps
CPU time 6.16 seconds
Started Jul 29 07:58:33 PM PDT 24
Finished Jul 29 07:58:40 PM PDT 24
Peak memory 573768 kb
Host smart-ec0c76e8-ecd8-4b9e-90e5-c4671631a11f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911289257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay
s.1911289257
Directory /workspace/51.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all.1259570713
Short name T2401
Test name
Test status
Simulation time 13669561156 ps
CPU time 502.04 seconds
Started Jul 29 07:58:39 PM PDT 24
Finished Jul 29 08:07:01 PM PDT 24
Peak memory 575972 kb
Host smart-a3c7c2a9-fc50-4ddb-9fb2-eeac049ecc8f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259570713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.1259570713
Directory /workspace/51.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.3831601408
Short name T1799
Test name
Test status
Simulation time 11676203748 ps
CPU time 371.71 seconds
Started Jul 29 07:58:40 PM PDT 24
Finished Jul 29 08:04:52 PM PDT 24
Peak memory 576824 kb
Host smart-39bc6eec-a7d2-45c0-815f-08fb2e486493
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831601408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.3831601408
Directory /workspace/51.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.3724259888
Short name T2505
Test name
Test status
Simulation time 938724814 ps
CPU time 141.66 seconds
Started Jul 29 07:58:49 PM PDT 24
Finished Jul 29 08:01:11 PM PDT 24
Peak memory 576804 kb
Host smart-4c58ce07-f594-4906-854c-438835c89300
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724259888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al
l_with_reset_error.3724259888
Directory /workspace/51.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.188860737
Short name T2314
Test name
Test status
Simulation time 921211117 ps
CPU time 39.31 seconds
Started Jul 29 07:58:40 PM PDT 24
Finished Jul 29 07:59:20 PM PDT 24
Peak memory 575868 kb
Host smart-240dfef1-2144-4b5d-b379-97ee5c171615
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188860737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.188860737
Directory /workspace/51.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_access_same_device.3697070610
Short name T2608
Test name
Test status
Simulation time 105766972 ps
CPU time 10.12 seconds
Started Jul 29 07:58:46 PM PDT 24
Finished Jul 29 07:58:57 PM PDT 24
Peak memory 574656 kb
Host smart-7ec7f538-a14c-47fb-a208-603e0b50bc2f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697070610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device
.3697070610
Directory /workspace/52.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.830651571
Short name T2376
Test name
Test status
Simulation time 56184795531 ps
CPU time 918.73 seconds
Started Jul 29 07:58:58 PM PDT 24
Finished Jul 29 08:14:17 PM PDT 24
Peak memory 576152 kb
Host smart-d8c46189-21ba-487c-b2a2-386add9e01ed
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830651571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_d
evice_slow_rsp.830651571
Directory /workspace/52.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.3422845865
Short name T2692
Test name
Test status
Simulation time 1426849755 ps
CPU time 46.71 seconds
Started Jul 29 07:58:47 PM PDT 24
Finished Jul 29 07:59:34 PM PDT 24
Peak memory 575744 kb
Host smart-fe9cdf26-dbf8-49b4-819c-24de722f6390
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422845865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add
r.3422845865
Directory /workspace/52.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_error_random.2680390178
Short name T2008
Test name
Test status
Simulation time 587824859 ps
CPU time 44.42 seconds
Started Jul 29 07:58:49 PM PDT 24
Finished Jul 29 07:59:33 PM PDT 24
Peak memory 575896 kb
Host smart-b1e9fde3-2f12-4f16-aebe-d03f341f4905
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680390178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.2680390178
Directory /workspace/52.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random.1387164198
Short name T1637
Test name
Test status
Simulation time 660824962 ps
CPU time 23.14 seconds
Started Jul 29 07:58:49 PM PDT 24
Finished Jul 29 07:59:13 PM PDT 24
Peak memory 575960 kb
Host smart-ab02e4fd-a2a0-4633-b443-e1b3457b16d4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387164198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.1387164198
Directory /workspace/52.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.1100270933
Short name T2004
Test name
Test status
Simulation time 36932984604 ps
CPU time 346.78 seconds
Started Jul 29 07:58:48 PM PDT 24
Finished Jul 29 08:04:35 PM PDT 24
Peak memory 576036 kb
Host smart-45350a28-ec79-4238-b6e9-05bec1f82a93
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100270933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.1100270933
Directory /workspace/52.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.2208245558
Short name T2205
Test name
Test status
Simulation time 47638363566 ps
CPU time 732.1 seconds
Started Jul 29 07:58:57 PM PDT 24
Finished Jul 29 08:11:09 PM PDT 24
Peak memory 575992 kb
Host smart-dd8382b2-9890-4599-b87c-050a56f83c2e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208245558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.2208245558
Directory /workspace/52.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.1553840484
Short name T2755
Test name
Test status
Simulation time 69286162 ps
CPU time 7.64 seconds
Started Jul 29 07:58:48 PM PDT 24
Finished Jul 29 07:58:56 PM PDT 24
Peak memory 575892 kb
Host smart-20d555dd-8bf7-43a4-92d6-d5dfe38af281
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553840484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del
ays.1553840484
Directory /workspace/52.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_same_source.2139467979
Short name T2364
Test name
Test status
Simulation time 279773084 ps
CPU time 19.3 seconds
Started Jul 29 07:58:50 PM PDT 24
Finished Jul 29 07:59:09 PM PDT 24
Peak memory 575888 kb
Host smart-f68a8d47-f0a7-4a2c-a85e-fb97da4e409f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139467979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.2139467979
Directory /workspace/52.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke.2630098939
Short name T2722
Test name
Test status
Simulation time 255946097 ps
CPU time 9.84 seconds
Started Jul 29 07:58:58 PM PDT 24
Finished Jul 29 07:59:08 PM PDT 24
Peak memory 573936 kb
Host smart-1bf81efd-a617-4949-ad8a-ca763c7ebe78
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630098939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.2630098939
Directory /workspace/52.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.562960004
Short name T1767
Test name
Test status
Simulation time 9631606558 ps
CPU time 97.13 seconds
Started Jul 29 07:58:46 PM PDT 24
Finished Jul 29 08:00:23 PM PDT 24
Peak memory 573920 kb
Host smart-416fd0bd-1b4b-4990-bd21-8572a6cd1bf4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562960004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.562960004
Directory /workspace/52.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.3837200045
Short name T2113
Test name
Test status
Simulation time 4329186165 ps
CPU time 69.88 seconds
Started Jul 29 07:58:58 PM PDT 24
Finished Jul 29 08:00:08 PM PDT 24
Peak memory 573948 kb
Host smart-679df4cf-134a-4d41-81db-0074b52bb6b9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837200045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.3837200045
Directory /workspace/52.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.1835698092
Short name T1934
Test name
Test status
Simulation time 42400294 ps
CPU time 6.13 seconds
Started Jul 29 07:58:48 PM PDT 24
Finished Jul 29 07:58:54 PM PDT 24
Peak memory 573860 kb
Host smart-c825b14c-d0e1-4410-8a12-1e6840796f9a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835698092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay
s.1835698092
Directory /workspace/52.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all.3986205924
Short name T1889
Test name
Test status
Simulation time 5458914265 ps
CPU time 209 seconds
Started Jul 29 07:58:48 PM PDT 24
Finished Jul 29 08:02:17 PM PDT 24
Peak memory 576792 kb
Host smart-00deb42c-5777-4b65-8883-a2e6b2a5e673
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986205924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.3986205924
Directory /workspace/52.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.1868793960
Short name T2484
Test name
Test status
Simulation time 4044811427 ps
CPU time 132.5 seconds
Started Jul 29 07:58:49 PM PDT 24
Finished Jul 29 08:01:01 PM PDT 24
Peak memory 576056 kb
Host smart-1a704de9-0328-4c24-9f92-914f38dcc704
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868793960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.1868793960
Directory /workspace/52.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.2287763178
Short name T2133
Test name
Test status
Simulation time 194535251 ps
CPU time 38.98 seconds
Started Jul 29 07:58:46 PM PDT 24
Finished Jul 29 07:59:25 PM PDT 24
Peak memory 575960 kb
Host smart-2837849e-8421-466e-a74c-91cd3bf143d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287763178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all
_with_rand_reset.2287763178
Directory /workspace/52.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.3800651703
Short name T2523
Test name
Test status
Simulation time 9195794966 ps
CPU time 371.27 seconds
Started Jul 29 07:58:47 PM PDT 24
Finished Jul 29 08:04:58 PM PDT 24
Peak memory 576840 kb
Host smart-94c14b80-f3fa-4e87-8249-b3a2f2e120a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800651703 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al
l_with_reset_error.3800651703
Directory /workspace/52.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.1999286269
Short name T649
Test name
Test status
Simulation time 200522794 ps
CPU time 24.23 seconds
Started Jul 29 07:58:48 PM PDT 24
Finished Jul 29 07:59:12 PM PDT 24
Peak memory 575944 kb
Host smart-42d61a9d-902e-4e08-a819-4c1f979e15b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999286269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.1999286269
Directory /workspace/52.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_access_same_device.2433769856
Short name T2517
Test name
Test status
Simulation time 2861250043 ps
CPU time 115.64 seconds
Started Jul 29 07:58:58 PM PDT 24
Finished Jul 29 08:00:53 PM PDT 24
Peak memory 576128 kb
Host smart-dfb03aaf-6516-419f-bffa-5eb3f3954d77
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433769856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device
.2433769856
Directory /workspace/53.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1085779532
Short name T2303
Test name
Test status
Simulation time 147315724624 ps
CPU time 2778.78 seconds
Started Jul 29 07:58:54 PM PDT 24
Finished Jul 29 08:45:13 PM PDT 24
Peak memory 576132 kb
Host smart-4ef0b540-945e-4c0c-b7e0-362b2adfebd1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085779532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_
device_slow_rsp.1085779532
Directory /workspace/53.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.3107224970
Short name T2767
Test name
Test status
Simulation time 1262494900 ps
CPU time 43.33 seconds
Started Jul 29 07:59:03 PM PDT 24
Finished Jul 29 07:59:47 PM PDT 24
Peak memory 575828 kb
Host smart-f0d19bd7-aff9-4018-9223-edcc88499097
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107224970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add
r.3107224970
Directory /workspace/53.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_error_random.2409655044
Short name T1658
Test name
Test status
Simulation time 2512496115 ps
CPU time 87.49 seconds
Started Jul 29 07:58:54 PM PDT 24
Finished Jul 29 08:00:22 PM PDT 24
Peak memory 575876 kb
Host smart-da06180e-2f6a-4b03-b706-8e65b6b40e89
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409655044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.2409655044
Directory /workspace/53.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random.10320313
Short name T2011
Test name
Test status
Simulation time 107095733 ps
CPU time 11.07 seconds
Started Jul 29 07:58:53 PM PDT 24
Finished Jul 29 07:59:04 PM PDT 24
Peak memory 575960 kb
Host smart-03e486eb-f99c-43b2-9651-5acae875d49f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10320313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.10320313
Directory /workspace/53.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.351408654
Short name T505
Test name
Test status
Simulation time 37428185542 ps
CPU time 409.2 seconds
Started Jul 29 07:58:55 PM PDT 24
Finished Jul 29 08:05:44 PM PDT 24
Peak memory 576000 kb
Host smart-69fb1459-8af5-469f-a36b-bbfba7ea44b3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351408654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.351408654
Directory /workspace/53.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.4221823639
Short name T647
Test name
Test status
Simulation time 53456403714 ps
CPU time 968.51 seconds
Started Jul 29 07:58:54 PM PDT 24
Finished Jul 29 08:15:02 PM PDT 24
Peak memory 575952 kb
Host smart-e792bdd8-5e98-4ada-9871-93716d330ff8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221823639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.4221823639
Directory /workspace/53.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.1322670626
Short name T2049
Test name
Test status
Simulation time 403988060 ps
CPU time 33.78 seconds
Started Jul 29 07:58:53 PM PDT 24
Finished Jul 29 07:59:27 PM PDT 24
Peak memory 575944 kb
Host smart-2cc00b1a-aea4-48c5-b3ba-2652c84a2f84
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322670626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del
ays.1322670626
Directory /workspace/53.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_same_source.3935000625
Short name T2511
Test name
Test status
Simulation time 283143279 ps
CPU time 20.09 seconds
Started Jul 29 07:58:55 PM PDT 24
Finished Jul 29 07:59:15 PM PDT 24
Peak memory 575940 kb
Host smart-6674ca6a-25dd-455a-9daa-09e99cb49907
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935000625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.3935000625
Directory /workspace/53.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke.2537087662
Short name T1632
Test name
Test status
Simulation time 190005857 ps
CPU time 9.06 seconds
Started Jul 29 07:58:54 PM PDT 24
Finished Jul 29 07:59:03 PM PDT 24
Peak memory 573772 kb
Host smart-3f119527-516f-487c-9704-46a266e78f60
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537087662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.2537087662
Directory /workspace/53.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.1392932227
Short name T1461
Test name
Test status
Simulation time 10502645337 ps
CPU time 112.79 seconds
Started Jul 29 07:58:55 PM PDT 24
Finished Jul 29 08:00:48 PM PDT 24
Peak memory 573984 kb
Host smart-7484e7b3-a5cf-4984-af16-743d7bcb3824
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392932227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.1392932227
Directory /workspace/53.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1634328986
Short name T2440
Test name
Test status
Simulation time 3205100400 ps
CPU time 53.46 seconds
Started Jul 29 07:58:56 PM PDT 24
Finished Jul 29 07:59:49 PM PDT 24
Peak memory 574560 kb
Host smart-b715acbc-7e17-40a5-b20d-68a13bb2dc85
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634328986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.1634328986
Directory /workspace/53.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.3034228128
Short name T2138
Test name
Test status
Simulation time 51954951 ps
CPU time 6.32 seconds
Started Jul 29 07:58:54 PM PDT 24
Finished Jul 29 07:59:01 PM PDT 24
Peak memory 574544 kb
Host smart-0d388886-d725-4e15-8b5e-f8c5e4301fa5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034228128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay
s.3034228128
Directory /workspace/53.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all.3055044144
Short name T504
Test name
Test status
Simulation time 7533300707 ps
CPU time 274.34 seconds
Started Jul 29 07:59:06 PM PDT 24
Finished Jul 29 08:03:41 PM PDT 24
Peak memory 576064 kb
Host smart-46f33536-0250-4017-a0c8-1840a0b11a9f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055044144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.3055044144
Directory /workspace/53.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.3622728339
Short name T2316
Test name
Test status
Simulation time 8073725912 ps
CPU time 252.87 seconds
Started Jul 29 07:59:14 PM PDT 24
Finished Jul 29 08:03:27 PM PDT 24
Peak memory 576288 kb
Host smart-de31f6db-4a71-4caf-b430-066cf4296de3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622728339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.3622728339
Directory /workspace/53.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.481956470
Short name T2325
Test name
Test status
Simulation time 230627838 ps
CPU time 72.56 seconds
Started Jul 29 07:59:03 PM PDT 24
Finished Jul 29 08:00:16 PM PDT 24
Peak memory 576768 kb
Host smart-35a51f2f-24a2-446d-884f-5e12cb3aba06
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481956470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all
_with_reset_error.481956470
Directory /workspace/53.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.1382758153
Short name T2094
Test name
Test status
Simulation time 85857192 ps
CPU time 6.43 seconds
Started Jul 29 07:58:54 PM PDT 24
Finished Jul 29 07:59:01 PM PDT 24
Peak memory 574480 kb
Host smart-deb4ddef-8f37-4ece-ac81-41f866371a05
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382758153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.1382758153
Directory /workspace/53.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_access_same_device.990438492
Short name T851
Test name
Test status
Simulation time 2466766317 ps
CPU time 106.72 seconds
Started Jul 29 07:59:03 PM PDT 24
Finished Jul 29 08:00:50 PM PDT 24
Peak memory 576056 kb
Host smart-13936757-36ef-4368-b5e1-931a9194c716
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990438492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device.
990438492
Directory /workspace/54.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.459935965
Short name T2539
Test name
Test status
Simulation time 113054962761 ps
CPU time 2006.2 seconds
Started Jul 29 07:59:11 PM PDT 24
Finished Jul 29 08:32:38 PM PDT 24
Peak memory 576104 kb
Host smart-1a2b15a5-474b-41c3-9f07-2eebb2c36570
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459935965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_d
evice_slow_rsp.459935965
Directory /workspace/54.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.3934935528
Short name T2459
Test name
Test status
Simulation time 1489795523 ps
CPU time 53.63 seconds
Started Jul 29 07:59:11 PM PDT 24
Finished Jul 29 08:00:05 PM PDT 24
Peak memory 575872 kb
Host smart-3634cacd-14ea-4d68-8c6b-a6ba69125d87
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934935528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add
r.3934935528
Directory /workspace/54.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_error_random.2214923741
Short name T2834
Test name
Test status
Simulation time 1783959820 ps
CPU time 56.23 seconds
Started Jul 29 07:59:19 PM PDT 24
Finished Jul 29 08:00:15 PM PDT 24
Peak memory 575828 kb
Host smart-4e1d7d27-0676-460a-a2c9-8ed1c3b68915
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214923741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.2214923741
Directory /workspace/54.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random.3684448308
Short name T2479
Test name
Test status
Simulation time 599108201 ps
CPU time 47.43 seconds
Started Jul 29 07:59:03 PM PDT 24
Finished Jul 29 07:59:50 PM PDT 24
Peak memory 576028 kb
Host smart-522b1db2-c917-4801-b8c1-ecbf5b2fc3f8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684448308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.3684448308
Directory /workspace/54.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.1240489192
Short name T1692
Test name
Test status
Simulation time 46081640603 ps
CPU time 450.99 seconds
Started Jul 29 07:59:14 PM PDT 24
Finished Jul 29 08:06:45 PM PDT 24
Peak memory 575896 kb
Host smart-c81235b8-5498-4c99-b45e-433d413a9635
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240489192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.1240489192
Directory /workspace/54.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.4188004947
Short name T1913
Test name
Test status
Simulation time 27364375211 ps
CPU time 453.65 seconds
Started Jul 29 07:59:03 PM PDT 24
Finished Jul 29 08:06:37 PM PDT 24
Peak memory 576024 kb
Host smart-781d356b-50c1-4519-9826-87c1a47b7442
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188004947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.4188004947
Directory /workspace/54.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.155982493
Short name T2900
Test name
Test status
Simulation time 262251693 ps
CPU time 23.81 seconds
Started Jul 29 07:59:05 PM PDT 24
Finished Jul 29 07:59:28 PM PDT 24
Peak memory 575808 kb
Host smart-5a4aff2c-e166-4d1a-afda-f49f3d2b4c10
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155982493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_dela
ys.155982493
Directory /workspace/54.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_same_source.2542232165
Short name T152
Test name
Test status
Simulation time 977087424 ps
CPU time 31.89 seconds
Started Jul 29 07:59:09 PM PDT 24
Finished Jul 29 07:59:41 PM PDT 24
Peak memory 575876 kb
Host smart-bd72682d-239c-4496-89e8-affd8ab70f9e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542232165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.2542232165
Directory /workspace/54.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke.73483997
Short name T2328
Test name
Test status
Simulation time 218146504 ps
CPU time 9.23 seconds
Started Jul 29 07:59:04 PM PDT 24
Finished Jul 29 07:59:13 PM PDT 24
Peak memory 574544 kb
Host smart-0f352e14-01fc-48da-a39e-c2e041b07966
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73483997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.73483997
Directory /workspace/54.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.2656114479
Short name T622
Test name
Test status
Simulation time 7748051209 ps
CPU time 78.76 seconds
Started Jul 29 07:59:14 PM PDT 24
Finished Jul 29 08:00:33 PM PDT 24
Peak memory 573948 kb
Host smart-6f09694b-e033-41d1-84a3-f5e65f88ca65
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656114479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.2656114479
Directory /workspace/54.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.3944512888
Short name T1557
Test name
Test status
Simulation time 3644654267 ps
CPU time 56.92 seconds
Started Jul 29 07:59:03 PM PDT 24
Finished Jul 29 08:00:00 PM PDT 24
Peak memory 573944 kb
Host smart-c9040460-a1a6-424f-8db0-97ff2ed739e3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944512888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.3944512888
Directory /workspace/54.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.4266260689
Short name T2013
Test name
Test status
Simulation time 34686483 ps
CPU time 5.52 seconds
Started Jul 29 07:59:13 PM PDT 24
Finished Jul 29 07:59:19 PM PDT 24
Peak memory 574540 kb
Host smart-8a64af26-6055-450b-9607-21550ceba274
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266260689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay
s.4266260689
Directory /workspace/54.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all.1829987693
Short name T604
Test name
Test status
Simulation time 1482275972 ps
CPU time 118.55 seconds
Started Jul 29 07:59:10 PM PDT 24
Finished Jul 29 08:01:09 PM PDT 24
Peak memory 575872 kb
Host smart-d1a1e8c2-3684-4f15-a957-575652e7bb59
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829987693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.1829987693
Directory /workspace/54.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.2622195479
Short name T2311
Test name
Test status
Simulation time 1191772124 ps
CPU time 48.24 seconds
Started Jul 29 07:59:16 PM PDT 24
Finished Jul 29 08:00:04 PM PDT 24
Peak memory 575900 kb
Host smart-8ef0256c-1e17-42a4-a181-90d250f28ed1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622195479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.2622195479
Directory /workspace/54.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3614180799
Short name T1862
Test name
Test status
Simulation time 159503428 ps
CPU time 51.9 seconds
Started Jul 29 07:59:20 PM PDT 24
Finished Jul 29 08:00:12 PM PDT 24
Peak memory 576772 kb
Host smart-33ddbb41-7c24-4cc6-a6ef-31820f8df465
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614180799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all
_with_rand_reset.3614180799
Directory /workspace/54.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3223123845
Short name T2269
Test name
Test status
Simulation time 6500103094 ps
CPU time 602.66 seconds
Started Jul 29 07:59:09 PM PDT 24
Finished Jul 29 08:09:12 PM PDT 24
Peak memory 576852 kb
Host smart-2e5b4fbd-b8c1-4f7e-9f08-31f2f0a1a8d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223123845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al
l_with_reset_error.3223123845
Directory /workspace/54.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.536105260
Short name T1452
Test name
Test status
Simulation time 105795625 ps
CPU time 13.28 seconds
Started Jul 29 07:59:10 PM PDT 24
Finished Jul 29 07:59:23 PM PDT 24
Peak memory 576024 kb
Host smart-e1637d97-e135-49d9-b39a-6299afab1a48
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536105260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.536105260
Directory /workspace/54.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_access_same_device.448298914
Short name T2060
Test name
Test status
Simulation time 587989919 ps
CPU time 26.11 seconds
Started Jul 29 07:59:11 PM PDT 24
Finished Jul 29 07:59:38 PM PDT 24
Peak memory 575824 kb
Host smart-14c49ce5-2786-4417-9d11-fa983396d6bb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448298914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device.
448298914
Directory /workspace/55.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.1453259095
Short name T2747
Test name
Test status
Simulation time 100217088612 ps
CPU time 1741.79 seconds
Started Jul 29 07:59:12 PM PDT 24
Finished Jul 29 08:28:14 PM PDT 24
Peak memory 575964 kb
Host smart-c7752963-bc95-49cc-8fda-2b5887a99c09
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453259095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_
device_slow_rsp.1453259095
Directory /workspace/55.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.3700024239
Short name T1983
Test name
Test status
Simulation time 271709423 ps
CPU time 12.91 seconds
Started Jul 29 07:59:22 PM PDT 24
Finished Jul 29 07:59:35 PM PDT 24
Peak memory 576032 kb
Host smart-ab88f29b-c904-4399-afa2-5d224e28c490
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700024239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add
r.3700024239
Directory /workspace/55.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_error_random.3872828128
Short name T1468
Test name
Test status
Simulation time 217560583 ps
CPU time 18.38 seconds
Started Jul 29 07:59:21 PM PDT 24
Finished Jul 29 07:59:39 PM PDT 24
Peak memory 576000 kb
Host smart-1dab568f-14e0-4b42-a51c-8966f58af408
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872828128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.3872828128
Directory /workspace/55.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random.2711131159
Short name T2297
Test name
Test status
Simulation time 123096787 ps
CPU time 13.88 seconds
Started Jul 29 07:59:10 PM PDT 24
Finished Jul 29 07:59:24 PM PDT 24
Peak memory 576000 kb
Host smart-a20feebb-cbf3-4688-81f1-fce5c477d704
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711131159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.2711131159
Directory /workspace/55.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.3357842391
Short name T1751
Test name
Test status
Simulation time 21968852075 ps
CPU time 232.58 seconds
Started Jul 29 07:59:20 PM PDT 24
Finished Jul 29 08:03:13 PM PDT 24
Peak memory 576092 kb
Host smart-d106bf01-3b7b-4363-b701-c8d71b9b1dd8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357842391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.3357842391
Directory /workspace/55.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.3356699652
Short name T2588
Test name
Test status
Simulation time 53902849248 ps
CPU time 900.19 seconds
Started Jul 29 07:59:10 PM PDT 24
Finished Jul 29 08:14:10 PM PDT 24
Peak memory 575964 kb
Host smart-bd890358-f0ba-423e-a600-8f412295a4ad
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356699652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.3356699652
Directory /workspace/55.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.74484945
Short name T2493
Test name
Test status
Simulation time 445574449 ps
CPU time 38.84 seconds
Started Jul 29 07:59:11 PM PDT 24
Finished Jul 29 07:59:50 PM PDT 24
Peak memory 575888 kb
Host smart-159a4af0-3145-4c1c-8113-5267052744fc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74484945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_delay
s.74484945
Directory /workspace/55.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_same_source.4262604000
Short name T2855
Test name
Test status
Simulation time 904515687 ps
CPU time 27.33 seconds
Started Jul 29 07:59:09 PM PDT 24
Finished Jul 29 07:59:36 PM PDT 24
Peak memory 575896 kb
Host smart-dea5720c-2b6a-4bd0-9460-34be5f9c2387
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262604000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.4262604000
Directory /workspace/55.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke.2907676836
Short name T1856
Test name
Test status
Simulation time 158311290 ps
CPU time 8.44 seconds
Started Jul 29 07:59:10 PM PDT 24
Finished Jul 29 07:59:18 PM PDT 24
Peak memory 573912 kb
Host smart-e02b0464-6109-4010-bcee-9348c3afe31b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907676836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.2907676836
Directory /workspace/55.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.77598882
Short name T1786
Test name
Test status
Simulation time 7003926415 ps
CPU time 67.09 seconds
Started Jul 29 07:59:12 PM PDT 24
Finished Jul 29 08:00:19 PM PDT 24
Peak memory 574620 kb
Host smart-b0484b4f-f12d-49c7-8d81-2d1958e1d7d1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77598882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.77598882
Directory /workspace/55.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.4030052497
Short name T2589
Test name
Test status
Simulation time 5802298920 ps
CPU time 98.96 seconds
Started Jul 29 07:59:12 PM PDT 24
Finished Jul 29 08:00:51 PM PDT 24
Peak memory 574600 kb
Host smart-f06fac7e-44c6-4c9a-829d-6f787fa8492a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030052497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.4030052497
Directory /workspace/55.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.1178513275
Short name T2168
Test name
Test status
Simulation time 48862502 ps
CPU time 6.14 seconds
Started Jul 29 07:59:09 PM PDT 24
Finished Jul 29 07:59:15 PM PDT 24
Peak memory 574536 kb
Host smart-fe06e744-939e-46a2-b1f8-0554d7bac83d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178513275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay
s.1178513275
Directory /workspace/55.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all.4170640577
Short name T2402
Test name
Test status
Simulation time 5458837882 ps
CPU time 228.96 seconds
Started Jul 29 07:59:17 PM PDT 24
Finished Jul 29 08:03:06 PM PDT 24
Peak memory 576128 kb
Host smart-5a3b7bd8-7a75-4ae7-aecf-cc03d10c0b00
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170640577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.4170640577
Directory /workspace/55.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.508149718
Short name T1660
Test name
Test status
Simulation time 149052168 ps
CPU time 12.91 seconds
Started Jul 29 07:59:16 PM PDT 24
Finished Jul 29 07:59:29 PM PDT 24
Peak memory 575944 kb
Host smart-783a2b36-e20d-40a5-93c1-7a58c890c2ec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508149718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.508149718
Directory /workspace/55.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.642197627
Short name T495
Test name
Test status
Simulation time 2942520022 ps
CPU time 551.72 seconds
Started Jul 29 07:59:17 PM PDT 24
Finished Jul 29 08:08:29 PM PDT 24
Peak memory 576016 kb
Host smart-9c6fdd96-62a9-4b8c-bc17-0bda757433d5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642197627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_
with_rand_reset.642197627
Directory /workspace/55.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.1372272158
Short name T894
Test name
Test status
Simulation time 579351150 ps
CPU time 145.64 seconds
Started Jul 29 07:59:23 PM PDT 24
Finished Jul 29 08:01:48 PM PDT 24
Peak memory 576816 kb
Host smart-80231cce-7451-4d5f-979d-8197a9764a4c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372272158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al
l_with_reset_error.1372272158
Directory /workspace/55.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.1898565514
Short name T2510
Test name
Test status
Simulation time 199775890 ps
CPU time 25.23 seconds
Started Jul 29 07:59:19 PM PDT 24
Finished Jul 29 07:59:44 PM PDT 24
Peak memory 576020 kb
Host smart-d50201d7-1f28-42b4-8dd9-c1a7a6826903
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898565514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.1898565514
Directory /workspace/55.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_access_same_device.2014635757
Short name T2432
Test name
Test status
Simulation time 3011107348 ps
CPU time 114.47 seconds
Started Jul 29 07:59:29 PM PDT 24
Finished Jul 29 08:01:24 PM PDT 24
Peak memory 576004 kb
Host smart-366fb734-af8e-47ae-bbdd-13c7d883bec9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014635757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device
.2014635757
Directory /workspace/56.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2736548583
Short name T1842
Test name
Test status
Simulation time 101364940796 ps
CPU time 1822.89 seconds
Started Jul 29 07:59:22 PM PDT 24
Finished Jul 29 08:29:46 PM PDT 24
Peak memory 575880 kb
Host smart-7664e5cc-b1da-4b0e-afdb-e76b64523343
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736548583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_
device_slow_rsp.2736548583
Directory /workspace/56.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.1954305838
Short name T2397
Test name
Test status
Simulation time 463315095 ps
CPU time 20.53 seconds
Started Jul 29 07:59:22 PM PDT 24
Finished Jul 29 07:59:43 PM PDT 24
Peak memory 575800 kb
Host smart-4b58cc71-52ed-4dc9-835d-c27e91a3458a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954305838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add
r.1954305838
Directory /workspace/56.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_error_random.3357295834
Short name T1394
Test name
Test status
Simulation time 474681680 ps
CPU time 18.61 seconds
Started Jul 29 07:59:22 PM PDT 24
Finished Jul 29 07:59:41 PM PDT 24
Peak memory 575732 kb
Host smart-6c0efefd-79f0-4d16-9fd5-e3ef631ed013
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357295834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.3357295834
Directory /workspace/56.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random.1397703076
Short name T1402
Test name
Test status
Simulation time 156776650 ps
CPU time 8.46 seconds
Started Jul 29 07:59:22 PM PDT 24
Finished Jul 29 07:59:31 PM PDT 24
Peak memory 574472 kb
Host smart-c1df0c71-39a7-4eb0-a4f7-1c0801e800fc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397703076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.1397703076
Directory /workspace/56.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.542246785
Short name T2852
Test name
Test status
Simulation time 11706279926 ps
CPU time 135.57 seconds
Started Jul 29 07:59:23 PM PDT 24
Finished Jul 29 08:01:39 PM PDT 24
Peak memory 575856 kb
Host smart-5f9b8f67-5047-479f-8139-ec819a55a22d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542246785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.542246785
Directory /workspace/56.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.2774800189
Short name T1422
Test name
Test status
Simulation time 7890029558 ps
CPU time 136.56 seconds
Started Jul 29 07:59:29 PM PDT 24
Finished Jul 29 08:01:46 PM PDT 24
Peak memory 575944 kb
Host smart-a33364ac-b8f9-4786-b688-21a32f791f2e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774800189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.2774800189
Directory /workspace/56.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.2310392764
Short name T2127
Test name
Test status
Simulation time 434636872 ps
CPU time 37.97 seconds
Started Jul 29 07:59:25 PM PDT 24
Finished Jul 29 08:00:04 PM PDT 24
Peak memory 575816 kb
Host smart-edf3808f-e935-4349-b598-a4d2883c06bc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310392764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del
ays.2310392764
Directory /workspace/56.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_same_source.3275042301
Short name T2380
Test name
Test status
Simulation time 365969836 ps
CPU time 26.39 seconds
Started Jul 29 07:59:22 PM PDT 24
Finished Jul 29 07:59:48 PM PDT 24
Peak memory 576124 kb
Host smart-bf38627c-7756-4f93-a5b4-5b78e7515964
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275042301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.3275042301
Directory /workspace/56.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke.328894832
Short name T1395
Test name
Test status
Simulation time 233691749 ps
CPU time 9.33 seconds
Started Jul 29 07:59:16 PM PDT 24
Finished Jul 29 07:59:25 PM PDT 24
Peak memory 573888 kb
Host smart-94f9d13b-2660-4d96-a26b-e9582c437fb9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328894832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.328894832
Directory /workspace/56.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.1548901723
Short name T1474
Test name
Test status
Simulation time 7525857969 ps
CPU time 78.9 seconds
Started Jul 29 07:59:27 PM PDT 24
Finished Jul 29 08:00:46 PM PDT 24
Peak memory 574652 kb
Host smart-97ef96e9-70b8-4808-8b63-9ee642dd2746
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548901723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.1548901723
Directory /workspace/56.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.2309034255
Short name T598
Test name
Test status
Simulation time 5251278138 ps
CPU time 90.61 seconds
Started Jul 29 07:59:23 PM PDT 24
Finished Jul 29 08:00:54 PM PDT 24
Peak memory 573964 kb
Host smart-69b3ddac-0a05-496e-aaa1-b584ef7501b5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309034255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.2309034255
Directory /workspace/56.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.354200175
Short name T632
Test name
Test status
Simulation time 53180150 ps
CPU time 6.57 seconds
Started Jul 29 07:59:22 PM PDT 24
Finished Jul 29 07:59:29 PM PDT 24
Peak memory 573812 kb
Host smart-fbdbd8fc-9bf2-4d38-a5cd-d6ed457646cd
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354200175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delays
.354200175
Directory /workspace/56.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all.1168069016
Short name T2930
Test name
Test status
Simulation time 2677583512 ps
CPU time 98.07 seconds
Started Jul 29 07:59:30 PM PDT 24
Finished Jul 29 08:01:08 PM PDT 24
Peak memory 576116 kb
Host smart-0c47ae46-129f-4d6c-b103-38096d9616aa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168069016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.1168069016
Directory /workspace/56.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.1724308403
Short name T1909
Test name
Test status
Simulation time 12152840880 ps
CPU time 545.31 seconds
Started Jul 29 07:59:30 PM PDT 24
Finished Jul 29 08:08:35 PM PDT 24
Peak memory 576816 kb
Host smart-97e5dcc0-a8bc-40f1-a05f-f677bb145c96
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724308403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al
l_with_reset_error.1724308403
Directory /workspace/56.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.4178576158
Short name T2042
Test name
Test status
Simulation time 105481824 ps
CPU time 12.5 seconds
Started Jul 29 07:59:29 PM PDT 24
Finished Jul 29 07:59:41 PM PDT 24
Peak memory 575904 kb
Host smart-7438b975-ba06-4ed1-82c5-14001100fa3c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178576158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.4178576158
Directory /workspace/56.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_access_same_device.2999444780
Short name T2532
Test name
Test status
Simulation time 589989359 ps
CPU time 48.79 seconds
Started Jul 29 07:59:46 PM PDT 24
Finished Jul 29 08:00:34 PM PDT 24
Peak memory 575764 kb
Host smart-b546d877-45bd-402b-ace3-f5946d8958da
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999444780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device
.2999444780
Directory /workspace/57.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3677073892
Short name T1926
Test name
Test status
Simulation time 146208515621 ps
CPU time 2636.28 seconds
Started Jul 29 07:59:35 PM PDT 24
Finished Jul 29 08:43:32 PM PDT 24
Peak memory 576008 kb
Host smart-a341f16b-42b6-463a-aa59-9ba1f42cbe2f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677073892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_
device_slow_rsp.3677073892
Directory /workspace/57.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.105808144
Short name T2273
Test name
Test status
Simulation time 636273571 ps
CPU time 25.56 seconds
Started Jul 29 07:59:36 PM PDT 24
Finished Jul 29 08:00:02 PM PDT 24
Peak memory 575996 kb
Host smart-94ab466f-ff80-4b86-bdd5-9282b7877d9d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105808144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_addr
.105808144
Directory /workspace/57.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_error_random.273868765
Short name T2079
Test name
Test status
Simulation time 558836381 ps
CPU time 45.73 seconds
Started Jul 29 07:59:45 PM PDT 24
Finished Jul 29 08:00:31 PM PDT 24
Peak memory 575660 kb
Host smart-c175d3ef-a559-497b-942f-afc368f27856
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273868765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.273868765
Directory /workspace/57.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random.1178148554
Short name T1930
Test name
Test status
Simulation time 1664495908 ps
CPU time 57.46 seconds
Started Jul 29 07:59:30 PM PDT 24
Finished Jul 29 08:00:27 PM PDT 24
Peak memory 576012 kb
Host smart-377e76d3-2438-4cad-ba10-803b6677304f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178148554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.1178148554
Directory /workspace/57.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.3199115017
Short name T674
Test name
Test status
Simulation time 39767567572 ps
CPU time 376.69 seconds
Started Jul 29 07:59:40 PM PDT 24
Finished Jul 29 08:05:57 PM PDT 24
Peak memory 576016 kb
Host smart-b37f71a7-fedc-43f4-982e-3cc7ca17065b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199115017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.3199115017
Directory /workspace/57.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.461644715
Short name T2387
Test name
Test status
Simulation time 3271136274 ps
CPU time 52.09 seconds
Started Jul 29 07:59:40 PM PDT 24
Finished Jul 29 08:00:32 PM PDT 24
Peak memory 574072 kb
Host smart-eb1203c7-b924-4290-81c5-a335cbf9321f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461644715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.461644715
Directory /workspace/57.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.2612977953
Short name T2568
Test name
Test status
Simulation time 583286999 ps
CPU time 45.63 seconds
Started Jul 29 07:59:36 PM PDT 24
Finished Jul 29 08:00:22 PM PDT 24
Peak memory 575896 kb
Host smart-88ee8ab4-1f57-4815-a95d-92a00346f3af
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612977953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del
ays.2612977953
Directory /workspace/57.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_same_source.2021429793
Short name T2609
Test name
Test status
Simulation time 92898617 ps
CPU time 9.54 seconds
Started Jul 29 07:59:36 PM PDT 24
Finished Jul 29 07:59:45 PM PDT 24
Peak memory 575828 kb
Host smart-265ac8cc-608e-4b61-909e-5183de79371a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021429793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.2021429793
Directory /workspace/57.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke.2450152636
Short name T2765
Test name
Test status
Simulation time 56762868 ps
CPU time 6.9 seconds
Started Jul 29 07:59:29 PM PDT 24
Finished Jul 29 07:59:36 PM PDT 24
Peak memory 573912 kb
Host smart-ab5b916f-8f4a-4a7e-9280-a9ec452b696c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450152636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.2450152636
Directory /workspace/57.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.2386708585
Short name T1514
Test name
Test status
Simulation time 10566787843 ps
CPU time 108.24 seconds
Started Jul 29 07:59:31 PM PDT 24
Finished Jul 29 08:01:19 PM PDT 24
Peak memory 574424 kb
Host smart-650cecd9-22d0-4988-8de8-73d7ac62a0ff
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386708585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.2386708585
Directory /workspace/57.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.335138022
Short name T1513
Test name
Test status
Simulation time 6596673267 ps
CPU time 108.99 seconds
Started Jul 29 07:59:29 PM PDT 24
Finished Jul 29 08:01:18 PM PDT 24
Peak memory 573992 kb
Host smart-10968845-920d-4755-96b7-7bcf883884d6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335138022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.335138022
Directory /workspace/57.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.2802651203
Short name T2718
Test name
Test status
Simulation time 55271379 ps
CPU time 6.83 seconds
Started Jul 29 07:59:32 PM PDT 24
Finished Jul 29 07:59:39 PM PDT 24
Peak memory 573852 kb
Host smart-60f088c7-96d8-4fe6-9084-39081eef6180
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802651203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay
s.2802651203
Directory /workspace/57.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all.2500197394
Short name T482
Test name
Test status
Simulation time 3662532822 ps
CPU time 298.74 seconds
Started Jul 29 07:59:40 PM PDT 24
Finished Jul 29 08:04:39 PM PDT 24
Peak memory 576952 kb
Host smart-b0f48f65-add7-4574-8340-a1e244f3bea8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500197394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.2500197394
Directory /workspace/57.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.2070617816
Short name T2816
Test name
Test status
Simulation time 6865403 ps
CPU time 3.8 seconds
Started Jul 29 07:59:42 PM PDT 24
Finished Jul 29 07:59:46 PM PDT 24
Peak memory 566208 kb
Host smart-36179aad-2ee9-4fe5-b128-2e43600c1348
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070617816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.2070617816
Directory /workspace/57.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.1729730747
Short name T662
Test name
Test status
Simulation time 611236970 ps
CPU time 150.99 seconds
Started Jul 29 07:59:41 PM PDT 24
Finished Jul 29 08:02:12 PM PDT 24
Peak memory 576860 kb
Host smart-b58e8b07-eadb-4e94-bf98-419aa25d69cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729730747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all
_with_rand_reset.1729730747
Directory /workspace/57.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.2958743843
Short name T2110
Test name
Test status
Simulation time 9067445154 ps
CPU time 430.54 seconds
Started Jul 29 07:59:43 PM PDT 24
Finished Jul 29 08:06:54 PM PDT 24
Peak memory 576808 kb
Host smart-3d2b89fd-2356-497c-a848-c5d42871a267
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958743843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al
l_with_reset_error.2958743843
Directory /workspace/57.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.313303866
Short name T1775
Test name
Test status
Simulation time 1129315007 ps
CPU time 48.4 seconds
Started Jul 29 07:59:46 PM PDT 24
Finished Jul 29 08:00:34 PM PDT 24
Peak memory 575776 kb
Host smart-92e334d3-6afa-4547-bd20-ca1aedc89463
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313303866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.313303866
Directory /workspace/57.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_access_same_device.4110830195
Short name T2356
Test name
Test status
Simulation time 443878033 ps
CPU time 35.27 seconds
Started Jul 29 07:59:49 PM PDT 24
Finished Jul 29 08:00:25 PM PDT 24
Peak memory 575964 kb
Host smart-2992f38e-107e-46e9-8e7a-5eb8ab0c32ee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110830195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device
.4110830195
Directory /workspace/58.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3760746391
Short name T2248
Test name
Test status
Simulation time 150253075460 ps
CPU time 2579.11 seconds
Started Jul 29 07:59:52 PM PDT 24
Finished Jul 29 08:42:51 PM PDT 24
Peak memory 576860 kb
Host smart-c7052b97-c6bf-4608-8bbd-55ddc8020b2a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760746391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_
device_slow_rsp.3760746391
Directory /workspace/58.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.4027663579
Short name T1650
Test name
Test status
Simulation time 131314934 ps
CPU time 14.31 seconds
Started Jul 29 07:59:53 PM PDT 24
Finished Jul 29 08:00:08 PM PDT 24
Peak memory 575820 kb
Host smart-00402d0e-f811-434e-a362-ea0bbfce0684
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027663579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add
r.4027663579
Directory /workspace/58.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_error_random.2497581688
Short name T2628
Test name
Test status
Simulation time 974190620 ps
CPU time 33.63 seconds
Started Jul 29 07:59:52 PM PDT 24
Finished Jul 29 08:00:25 PM PDT 24
Peak memory 575980 kb
Host smart-bb09684f-880e-4ae5-acc7-b71357317d01
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497581688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.2497581688
Directory /workspace/58.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random.686637246
Short name T2313
Test name
Test status
Simulation time 390260283 ps
CPU time 15.71 seconds
Started Jul 29 07:59:44 PM PDT 24
Finished Jul 29 08:00:00 PM PDT 24
Peak memory 575992 kb
Host smart-ef4d4431-9922-4af8-951d-44e9e61b1665
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686637246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.686637246
Directory /workspace/58.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.407871372
Short name T2190
Test name
Test status
Simulation time 99702512925 ps
CPU time 1063.44 seconds
Started Jul 29 07:59:46 PM PDT 24
Finished Jul 29 08:17:29 PM PDT 24
Peak memory 575964 kb
Host smart-9a574d70-2f3c-49fe-b6bb-7596356cfafa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407871372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.407871372
Directory /workspace/58.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.2079161888
Short name T2761
Test name
Test status
Simulation time 48286309940 ps
CPU time 759.12 seconds
Started Jul 29 07:59:50 PM PDT 24
Finished Jul 29 08:12:29 PM PDT 24
Peak memory 575956 kb
Host smart-edd37770-f35c-45b2-b581-fb0800f0ac48
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079161888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.2079161888
Directory /workspace/58.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.2153201105
Short name T687
Test name
Test status
Simulation time 364671084 ps
CPU time 30.99 seconds
Started Jul 29 07:59:43 PM PDT 24
Finished Jul 29 08:00:14 PM PDT 24
Peak memory 575792 kb
Host smart-f480346f-4c01-4496-933d-fa827bb4e81f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153201105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del
ays.2153201105
Directory /workspace/58.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_same_source.3186667778
Short name T683
Test name
Test status
Simulation time 1315888031 ps
CPU time 39.75 seconds
Started Jul 29 07:59:50 PM PDT 24
Finished Jul 29 08:00:30 PM PDT 24
Peak memory 575920 kb
Host smart-01e8e0e6-42d1-4ab8-a301-c12e8e8a5d00
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186667778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.3186667778
Directory /workspace/58.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke.96040205
Short name T2731
Test name
Test status
Simulation time 192308489 ps
CPU time 8.43 seconds
Started Jul 29 07:59:42 PM PDT 24
Finished Jul 29 07:59:51 PM PDT 24
Peak memory 573848 kb
Host smart-09a57a5a-d498-4786-a3a2-ea5717f0b8d9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96040205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.96040205
Directory /workspace/58.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.2047668427
Short name T2799
Test name
Test status
Simulation time 7270718708 ps
CPU time 75.12 seconds
Started Jul 29 07:59:43 PM PDT 24
Finished Jul 29 08:00:58 PM PDT 24
Peak memory 574680 kb
Host smart-a65dba39-ded2-462a-92e4-d4f03756802d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047668427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.2047668427
Directory /workspace/58.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.2429305036
Short name T2188
Test name
Test status
Simulation time 5115612877 ps
CPU time 85.8 seconds
Started Jul 29 07:59:45 PM PDT 24
Finished Jul 29 08:01:11 PM PDT 24
Peak memory 573992 kb
Host smart-32f33e75-11b8-4c6c-83b7-b53fb237d336
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429305036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.2429305036
Directory /workspace/58.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2358135937
Short name T2582
Test name
Test status
Simulation time 52675334 ps
CPU time 7 seconds
Started Jul 29 07:59:44 PM PDT 24
Finished Jul 29 07:59:51 PM PDT 24
Peak memory 573780 kb
Host smart-3d2dc6c2-814a-4a48-a190-44f9b92bdb3f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358135937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay
s.2358135937
Directory /workspace/58.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all.3310841230
Short name T2022
Test name
Test status
Simulation time 4030690769 ps
CPU time 128.57 seconds
Started Jul 29 07:59:50 PM PDT 24
Finished Jul 29 08:01:58 PM PDT 24
Peak memory 576096 kb
Host smart-a23baf30-4dcf-4afe-bd3a-f0f43c046977
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310841230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.3310841230
Directory /workspace/58.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.620467977
Short name T1693
Test name
Test status
Simulation time 3245624697 ps
CPU time 241.62 seconds
Started Jul 29 07:59:57 PM PDT 24
Finished Jul 29 08:03:59 PM PDT 24
Peak memory 576848 kb
Host smart-0b03d0f2-6fc6-4823-813c-effc61c34e2e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620467977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.620467977
Directory /workspace/58.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3001619890
Short name T688
Test name
Test status
Simulation time 2765076775 ps
CPU time 295.19 seconds
Started Jul 29 07:59:49 PM PDT 24
Finished Jul 29 08:04:44 PM PDT 24
Peak memory 576844 kb
Host smart-f0190c62-d43f-4d77-9f03-3f339be42be9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001619890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all
_with_rand_reset.3001619890
Directory /workspace/58.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.1398368255
Short name T2147
Test name
Test status
Simulation time 5412249806 ps
CPU time 520.05 seconds
Started Jul 29 07:59:57 PM PDT 24
Finished Jul 29 08:08:38 PM PDT 24
Peak memory 576844 kb
Host smart-c6b932f8-becb-4b31-a500-511c0e56f445
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398368255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al
l_with_reset_error.1398368255
Directory /workspace/58.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.2475091540
Short name T2585
Test name
Test status
Simulation time 87457598 ps
CPU time 6.63 seconds
Started Jul 29 07:59:50 PM PDT 24
Finished Jul 29 07:59:56 PM PDT 24
Peak memory 573884 kb
Host smart-6cfd0cea-4a0b-4be8-b725-3a9fa0222158
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475091540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.2475091540
Directory /workspace/58.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_access_same_device.1567077812
Short name T2702
Test name
Test status
Simulation time 524414029 ps
CPU time 46.48 seconds
Started Jul 29 07:59:55 PM PDT 24
Finished Jul 29 08:00:42 PM PDT 24
Peak memory 575936 kb
Host smart-4509df91-3199-44cd-80ea-31659f39a3f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567077812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device
.1567077812
Directory /workspace/59.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.224198331
Short name T878
Test name
Test status
Simulation time 50524950079 ps
CPU time 875.51 seconds
Started Jul 29 07:59:57 PM PDT 24
Finished Jul 29 08:14:32 PM PDT 24
Peak memory 576044 kb
Host smart-6e7d1fbe-b64c-47a7-a776-b79d831a1c9c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224198331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_d
evice_slow_rsp.224198331
Directory /workspace/59.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.2264857172
Short name T2485
Test name
Test status
Simulation time 1124752962 ps
CPU time 43.41 seconds
Started Jul 29 08:00:08 PM PDT 24
Finished Jul 29 08:00:51 PM PDT 24
Peak memory 575880 kb
Host smart-94b2de00-3a7e-496d-8f9f-727f9ea2bb5e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264857172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add
r.2264857172
Directory /workspace/59.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_error_random.1602444094
Short name T715
Test name
Test status
Simulation time 1795372014 ps
CPU time 57.5 seconds
Started Jul 29 07:59:57 PM PDT 24
Finished Jul 29 08:00:55 PM PDT 24
Peak memory 575904 kb
Host smart-277fa8c0-e19d-4254-80fd-8b3950e01a6d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602444094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.1602444094
Directory /workspace/59.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random.1999487883
Short name T2657
Test name
Test status
Simulation time 427014031 ps
CPU time 34.51 seconds
Started Jul 29 07:59:53 PM PDT 24
Finished Jul 29 08:00:28 PM PDT 24
Peak memory 575816 kb
Host smart-fe7c0779-b387-483e-800a-eac193ce2aa9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999487883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.1999487883
Directory /workspace/59.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.2683156268
Short name T640
Test name
Test status
Simulation time 57643837455 ps
CPU time 578.27 seconds
Started Jul 29 07:59:55 PM PDT 24
Finished Jul 29 08:09:34 PM PDT 24
Peak memory 575876 kb
Host smart-f015bf01-a619-4ec7-bd72-c47370a65ace
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683156268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.2683156268
Directory /workspace/59.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.3859577817
Short name T2547
Test name
Test status
Simulation time 63924797437 ps
CPU time 1136.73 seconds
Started Jul 29 08:00:02 PM PDT 24
Finished Jul 29 08:19:03 PM PDT 24
Peak memory 575716 kb
Host smart-6b8b3807-2b41-49c8-b6de-e83856f09943
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859577817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.3859577817
Directory /workspace/59.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.1745615465
Short name T2418
Test name
Test status
Simulation time 503628293 ps
CPU time 45.52 seconds
Started Jul 29 08:00:02 PM PDT 24
Finished Jul 29 08:00:51 PM PDT 24
Peak memory 575720 kb
Host smart-a2161b8e-7ee5-4be5-869f-e89e46205f0c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745615465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del
ays.1745615465
Directory /workspace/59.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_same_source.1043679227
Short name T2877
Test name
Test status
Simulation time 292659090 ps
CPU time 10.91 seconds
Started Jul 29 07:59:54 PM PDT 24
Finished Jul 29 08:00:05 PM PDT 24
Peak memory 575908 kb
Host smart-666f5331-292e-41cb-8953-eb8460dbe51f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043679227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.1043679227
Directory /workspace/59.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke.3966386653
Short name T1480
Test name
Test status
Simulation time 227257474 ps
CPU time 9.17 seconds
Started Jul 29 07:59:55 PM PDT 24
Finished Jul 29 08:00:05 PM PDT 24
Peak memory 573888 kb
Host smart-8f75e7f2-e770-4115-a481-e5234b22048e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966386653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.3966386653
Directory /workspace/59.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.320641642
Short name T2864
Test name
Test status
Simulation time 10012452839 ps
CPU time 103.59 seconds
Started Jul 29 07:59:54 PM PDT 24
Finished Jul 29 08:01:38 PM PDT 24
Peak memory 573988 kb
Host smart-9c3772c4-db6d-4119-9208-4b9d11d42b70
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320641642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.320641642
Directory /workspace/59.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.690473866
Short name T1547
Test name
Test status
Simulation time 4671634739 ps
CPU time 81.13 seconds
Started Jul 29 08:00:01 PM PDT 24
Finished Jul 29 08:01:27 PM PDT 24
Peak memory 574428 kb
Host smart-3ef38879-ba1b-4c39-a52b-c1d15fe4d117
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690473866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.690473866
Directory /workspace/59.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1848348714
Short name T1553
Test name
Test status
Simulation time 50899548 ps
CPU time 6.97 seconds
Started Jul 29 07:59:55 PM PDT 24
Finished Jul 29 08:00:02 PM PDT 24
Peak memory 574560 kb
Host smart-ad1fae1c-cfdf-4163-80b5-23a3477fd88f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848348714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay
s.1848348714
Directory /workspace/59.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all.405743918
Short name T2384
Test name
Test status
Simulation time 4175056785 ps
CPU time 155.84 seconds
Started Jul 29 08:00:06 PM PDT 24
Finished Jul 29 08:02:42 PM PDT 24
Peak memory 576116 kb
Host smart-752ff366-97c5-4851-9f2b-178b0c175dd6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405743918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.405743918
Directory /workspace/59.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.2914219248
Short name T1998
Test name
Test status
Simulation time 3597318446 ps
CPU time 128.85 seconds
Started Jul 29 08:00:06 PM PDT 24
Finished Jul 29 08:02:15 PM PDT 24
Peak memory 575980 kb
Host smart-5c3290ba-64eb-419a-9e16-61e4721dc126
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914219248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.2914219248
Directory /workspace/59.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.93713059
Short name T2142
Test name
Test status
Simulation time 5676999632 ps
CPU time 494.53 seconds
Started Jul 29 08:00:06 PM PDT 24
Finished Jul 29 08:08:21 PM PDT 24
Peak memory 576020 kb
Host smart-324aa749-73e1-43a8-afd5-3544d6f02293
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93713059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_w
ith_rand_reset.93713059
Directory /workspace/59.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.2849290689
Short name T1618
Test name
Test status
Simulation time 146112174 ps
CPU time 15.92 seconds
Started Jul 29 08:00:04 PM PDT 24
Finished Jul 29 08:00:22 PM PDT 24
Peak memory 576048 kb
Host smart-ed573c94-f565-4c87-959e-811e71db80ba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849290689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.2849290689
Directory /workspace/59.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.3748903900
Short name T1958
Test name
Test status
Simulation time 11515012785 ps
CPU time 825.6 seconds
Started Jul 29 07:50:28 PM PDT 24
Finished Jul 29 08:04:14 PM PDT 24
Peak memory 652520 kb
Host smart-b17e9999-2338-42bc-b546-86d3de6dcde3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748903900 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.3748903900
Directory /workspace/6.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.chip_csr_rw.3945891205
Short name T2212
Test name
Test status
Simulation time 5497364059 ps
CPU time 556.48 seconds
Started Jul 29 07:50:17 PM PDT 24
Finished Jul 29 07:59:34 PM PDT 24
Peak memory 598592 kb
Host smart-66469a9b-c282-4b84-a958-f0e14092425a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945891205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.3945891205
Directory /workspace/6.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.3339723021
Short name T1920
Test name
Test status
Simulation time 15267478900 ps
CPU time 1932.16 seconds
Started Jul 29 07:50:15 PM PDT 24
Finished Jul 29 08:22:27 PM PDT 24
Peak memory 593112 kb
Host smart-890a5191-41d9-4714-a775-bd34da963a1f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339723021 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.3339723021
Directory /workspace/6.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.chip_tl_errors.1207247993
Short name T733
Test name
Test status
Simulation time 2896711730 ps
CPU time 199.01 seconds
Started Jul 29 07:50:15 PM PDT 24
Finished Jul 29 07:53:34 PM PDT 24
Peak memory 598708 kb
Host smart-755d5856-63d1-4a83-a83d-e40e77d13d45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207247993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.1207247993
Directory /workspace/6.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_access_same_device.3914977633
Short name T1602
Test name
Test status
Simulation time 1079147345 ps
CPU time 71.83 seconds
Started Jul 29 07:50:02 PM PDT 24
Finished Jul 29 07:51:14 PM PDT 24
Peak memory 575912 kb
Host smart-c1ad1472-7404-4402-bf2b-c3508b2280a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914977633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.
3914977633
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.2965969642
Short name T868
Test name
Test status
Simulation time 38615973342 ps
CPU time 627.24 seconds
Started Jul 29 07:50:03 PM PDT 24
Finished Jul 29 08:00:30 PM PDT 24
Peak memory 575972 kb
Host smart-fa88ff62-77d1-4be9-a3a6-94337cf71c47
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965969642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d
evice_slow_rsp.2965969642
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.2479037046
Short name T2306
Test name
Test status
Simulation time 818486756 ps
CPU time 34.28 seconds
Started Jul 29 07:50:02 PM PDT 24
Finished Jul 29 07:50:36 PM PDT 24
Peak memory 575972 kb
Host smart-254dcfbb-85ca-4255-acf8-9a3ea8e9572e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479037046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr
.2479037046
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_error_random.1803760315
Short name T2689
Test name
Test status
Simulation time 726750222 ps
CPU time 24.38 seconds
Started Jul 29 07:50:02 PM PDT 24
Finished Jul 29 07:50:27 PM PDT 24
Peak memory 575768 kb
Host smart-7ad9bcc2-a344-475a-b9c0-e64c493c5929
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803760315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1803760315
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random.2324793146
Short name T691
Test name
Test status
Simulation time 1575318717 ps
CPU time 58.71 seconds
Started Jul 29 07:50:15 PM PDT 24
Finished Jul 29 07:51:14 PM PDT 24
Peak memory 575832 kb
Host smart-e5d476c1-2086-4f2e-b48a-f9132076f9e0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324793146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.2324793146
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.3542225
Short name T2084
Test name
Test status
Simulation time 11160231082 ps
CPU time 116.43 seconds
Started Jul 29 07:50:05 PM PDT 24
Finished Jul 29 07:52:01 PM PDT 24
Peak memory 576028 kb
Host smart-83fa85aa-fa49-45a8-b2be-e62d5d1da26d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3542225
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.2757508361
Short name T2885
Test name
Test status
Simulation time 42659927109 ps
CPU time 658.7 seconds
Started Jul 29 07:50:11 PM PDT 24
Finished Jul 29 08:01:10 PM PDT 24
Peak memory 576032 kb
Host smart-b1da3b0b-61e1-46ac-ba44-57d21e286e9b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757508361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2757508361
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.3198705312
Short name T2437
Test name
Test status
Simulation time 450297520 ps
CPU time 39.95 seconds
Started Jul 29 07:50:03 PM PDT 24
Finished Jul 29 07:50:43 PM PDT 24
Peak memory 575944 kb
Host smart-fe4848ce-63fd-4bb2-9c09-0893c28f5ed5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198705312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela
ys.3198705312
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_same_source.2027172466
Short name T1854
Test name
Test status
Simulation time 2326296102 ps
CPU time 70.98 seconds
Started Jul 29 07:50:09 PM PDT 24
Finished Jul 29 07:51:20 PM PDT 24
Peak memory 575640 kb
Host smart-f86c5de9-cb93-4f3b-8264-4443573e6d0d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027172466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2027172466
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke.1600522922
Short name T1511
Test name
Test status
Simulation time 35929681 ps
CPU time 5.39 seconds
Started Jul 29 07:50:08 PM PDT 24
Finished Jul 29 07:50:14 PM PDT 24
Peak memory 573812 kb
Host smart-7657ea61-678a-46de-ace1-281e8235e3b3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600522922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1600522922
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.3824536332
Short name T1648
Test name
Test status
Simulation time 9613869786 ps
CPU time 95.75 seconds
Started Jul 29 07:50:16 PM PDT 24
Finished Jul 29 07:51:51 PM PDT 24
Peak memory 573984 kb
Host smart-75e1e06e-4c8c-4706-b63f-c9feda01c335
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824536332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3824536332
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.2773581723
Short name T464
Test name
Test status
Simulation time 4219749663 ps
CPU time 75.21 seconds
Started Jul 29 07:50:08 PM PDT 24
Finished Jul 29 07:51:23 PM PDT 24
Peak memory 574604 kb
Host smart-6867d018-bc7e-484b-903d-43ec0d2af97e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773581723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2773581723
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.3668616688
Short name T1653
Test name
Test status
Simulation time 47312213 ps
CPU time 6.02 seconds
Started Jul 29 07:50:08 PM PDT 24
Finished Jul 29 07:50:14 PM PDT 24
Peak memory 573772 kb
Host smart-079ceced-1ed9-4579-915b-6a8be5ea782f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668616688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays
.3668616688
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all.2243127409
Short name T2820
Test name
Test status
Simulation time 2891764798 ps
CPU time 109.3 seconds
Started Jul 29 07:50:02 PM PDT 24
Finished Jul 29 07:51:52 PM PDT 24
Peak memory 575968 kb
Host smart-c0ded728-91e8-41f5-a195-ffc2dfc0098e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243127409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2243127409
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.682369093
Short name T1407
Test name
Test status
Simulation time 2056689525 ps
CPU time 76.52 seconds
Started Jul 29 07:50:11 PM PDT 24
Finished Jul 29 07:51:28 PM PDT 24
Peak memory 575852 kb
Host smart-c5a83356-0162-4496-8cab-3aee1cbe5bfa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682369093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.682369093
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.1076873295
Short name T2427
Test name
Test status
Simulation time 101481045 ps
CPU time 74.53 seconds
Started Jul 29 07:50:23 PM PDT 24
Finished Jul 29 07:51:37 PM PDT 24
Peak memory 576784 kb
Host smart-6e0a3bf4-607a-492d-b6ac-7e43cf9c2d5b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076873295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_
with_rand_reset.1076873295
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.2004605160
Short name T906
Test name
Test status
Simulation time 597979600 ps
CPU time 143.03 seconds
Started Jul 29 07:50:09 PM PDT 24
Finished Jul 29 07:52:33 PM PDT 24
Peak memory 576756 kb
Host smart-1553066d-6f7e-4766-b934-ff729ff6992f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004605160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all
_with_reset_error.2004605160
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.4196540606
Short name T1726
Test name
Test status
Simulation time 504526469 ps
CPU time 21.73 seconds
Started Jul 29 07:50:09 PM PDT 24
Finished Jul 29 07:50:31 PM PDT 24
Peak memory 575868 kb
Host smart-b6c90b7a-048d-4664-9d19-7013a8a60f46
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196540606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.4196540606
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_access_same_device.3152616248
Short name T1548
Test name
Test status
Simulation time 515213635 ps
CPU time 23.56 seconds
Started Jul 29 08:00:15 PM PDT 24
Finished Jul 29 08:00:39 PM PDT 24
Peak memory 575768 kb
Host smart-dde85ed1-4c3c-4623-9f50-391422776822
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152616248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device
.3152616248
Directory /workspace/60.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.2017993576
Short name T2101
Test name
Test status
Simulation time 20178831027 ps
CPU time 353.14 seconds
Started Jul 29 08:00:16 PM PDT 24
Finished Jul 29 08:06:09 PM PDT 24
Peak memory 575920 kb
Host smart-175b2cc0-83dd-4858-b2c7-eacbcd7bf1f3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017993576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_
device_slow_rsp.2017993576
Directory /workspace/60.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.599495727
Short name T1887
Test name
Test status
Simulation time 131245232 ps
CPU time 16.25 seconds
Started Jul 29 08:00:23 PM PDT 24
Finished Jul 29 08:00:39 PM PDT 24
Peak memory 575976 kb
Host smart-842a393d-89d1-4f1d-a8f6-1123a991ee79
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599495727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_addr
.599495727
Directory /workspace/60.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_error_random.663575994
Short name T1816
Test name
Test status
Simulation time 412090829 ps
CPU time 15.97 seconds
Started Jul 29 08:00:14 PM PDT 24
Finished Jul 29 08:00:30 PM PDT 24
Peak memory 575924 kb
Host smart-41701d3b-a052-4492-9fac-31aa208c6ddc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663575994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.663575994
Directory /workspace/60.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random.352999635
Short name T2558
Test name
Test status
Simulation time 2029256729 ps
CPU time 77.85 seconds
Started Jul 29 08:00:06 PM PDT 24
Finished Jul 29 08:01:24 PM PDT 24
Peak memory 575856 kb
Host smart-5688a6a8-5f89-4ea6-a895-b559b22f8502
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352999635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.352999635
Directory /workspace/60.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.2987624322
Short name T1601
Test name
Test status
Simulation time 31248992959 ps
CPU time 333.87 seconds
Started Jul 29 08:00:21 PM PDT 24
Finished Jul 29 08:05:55 PM PDT 24
Peak memory 576076 kb
Host smart-74a07409-29b6-4cbb-b2bd-400ca90df8ba
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987624322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.2987624322
Directory /workspace/60.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1007988611
Short name T1734
Test name
Test status
Simulation time 21204772492 ps
CPU time 348.53 seconds
Started Jul 29 08:00:16 PM PDT 24
Finished Jul 29 08:06:05 PM PDT 24
Peak memory 575904 kb
Host smart-e52cd384-8b73-4da3-b50f-a0721e8e6e91
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007988611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.1007988611
Directory /workspace/60.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.189268810
Short name T2669
Test name
Test status
Simulation time 113789087 ps
CPU time 12.34 seconds
Started Jul 29 08:00:06 PM PDT 24
Finished Jul 29 08:00:19 PM PDT 24
Peak memory 575972 kb
Host smart-78613e93-44b7-4f7b-acf8-8a0a496bfb43
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189268810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_dela
ys.189268810
Directory /workspace/60.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_same_source.1109289095
Short name T2643
Test name
Test status
Simulation time 2660531246 ps
CPU time 82.26 seconds
Started Jul 29 08:00:17 PM PDT 24
Finished Jul 29 08:01:40 PM PDT 24
Peak memory 575924 kb
Host smart-ef8f2c7c-b41e-4b4f-a75d-79db4ad99f4d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109289095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.1109289095
Directory /workspace/60.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke.1763409981
Short name T1475
Test name
Test status
Simulation time 161608656 ps
CPU time 7.99 seconds
Started Jul 29 08:00:05 PM PDT 24
Finished Jul 29 08:00:14 PM PDT 24
Peak memory 573812 kb
Host smart-8e2dbb10-f805-41d2-a513-5e6247c8b3b5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763409981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.1763409981
Directory /workspace/60.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.3984433217
Short name T2528
Test name
Test status
Simulation time 5008328244 ps
CPU time 52.67 seconds
Started Jul 29 08:00:05 PM PDT 24
Finished Jul 29 08:00:59 PM PDT 24
Peak memory 574528 kb
Host smart-bae34baf-b23b-404e-8bd1-86cab4abab58
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984433217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.3984433217
Directory /workspace/60.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1753705655
Short name T1479
Test name
Test status
Simulation time 3500172401 ps
CPU time 58.9 seconds
Started Jul 29 08:00:05 PM PDT 24
Finished Jul 29 08:01:05 PM PDT 24
Peak memory 573728 kb
Host smart-ffa27b08-df9e-48fb-994e-fb051adb1fd1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753705655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.1753705655
Directory /workspace/60.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2128523227
Short name T1789
Test name
Test status
Simulation time 50033159 ps
CPU time 6.71 seconds
Started Jul 29 08:00:05 PM PDT 24
Finished Jul 29 08:00:13 PM PDT 24
Peak memory 573888 kb
Host smart-ad61654a-77e6-4af8-9b46-0ada7a7cd07f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128523227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay
s.2128523227
Directory /workspace/60.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all.2821107468
Short name T2646
Test name
Test status
Simulation time 1934316519 ps
CPU time 190.91 seconds
Started Jul 29 08:00:16 PM PDT 24
Finished Jul 29 08:03:27 PM PDT 24
Peak memory 575856 kb
Host smart-6cbf078e-1b49-4d8b-80d0-b60e8bfc5eea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821107468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.2821107468
Directory /workspace/60.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.1932717969
Short name T2087
Test name
Test status
Simulation time 10244428 ps
CPU time 7.66 seconds
Started Jul 29 08:00:19 PM PDT 24
Finished Jul 29 08:00:27 PM PDT 24
Peak memory 574032 kb
Host smart-cffb7fef-7db7-405a-b173-a0d50c9b9221
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932717969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all
_with_rand_reset.1932717969
Directory /workspace/60.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.2936306316
Short name T869
Test name
Test status
Simulation time 149558750 ps
CPU time 46.47 seconds
Started Jul 29 08:00:15 PM PDT 24
Finished Jul 29 08:01:02 PM PDT 24
Peak memory 576700 kb
Host smart-a86920e3-8408-4cbd-a9a1-8fd42146f2d7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936306316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al
l_with_reset_error.2936306316
Directory /workspace/60.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.2016330980
Short name T507
Test name
Test status
Simulation time 1464715882 ps
CPU time 58.12 seconds
Started Jul 29 08:00:23 PM PDT 24
Finished Jul 29 08:01:21 PM PDT 24
Peak memory 575868 kb
Host smart-7b2a13c2-b201-46e6-83bb-df2bcc0d6991
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016330980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.2016330980
Directory /workspace/60.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_access_same_device.681979116
Short name T1715
Test name
Test status
Simulation time 1278951037 ps
CPU time 49.67 seconds
Started Jul 29 08:00:23 PM PDT 24
Finished Jul 29 08:01:13 PM PDT 24
Peak memory 575892 kb
Host smart-d0c804b6-766e-4c25-955a-dce4339e79ed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681979116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device.
681979116
Directory /workspace/61.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.960723841
Short name T2430
Test name
Test status
Simulation time 59298383830 ps
CPU time 1161.17 seconds
Started Jul 29 08:00:24 PM PDT 24
Finished Jul 29 08:19:46 PM PDT 24
Peak memory 576108 kb
Host smart-5778c8ce-2af9-431f-83f2-abf85e3fc727
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960723841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_d
evice_slow_rsp.960723841
Directory /workspace/61.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.5930855
Short name T1502
Test name
Test status
Simulation time 326317982 ps
CPU time 34.43 seconds
Started Jul 29 08:00:30 PM PDT 24
Finished Jul 29 08:01:05 PM PDT 24
Peak memory 576028 kb
Host smart-b128f9eb-6de3-4093-82b5-e620c8a0d0dd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5930855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_addr.5930855
Directory /workspace/61.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_error_random.3437580462
Short name T2825
Test name
Test status
Simulation time 1448696258 ps
CPU time 49.68 seconds
Started Jul 29 08:00:27 PM PDT 24
Finished Jul 29 08:01:17 PM PDT 24
Peak memory 575924 kb
Host smart-f505f09c-fb51-4d49-a53e-6722230a4666
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437580462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.3437580462
Directory /workspace/61.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random.3504831734
Short name T1710
Test name
Test status
Simulation time 1933225969 ps
CPU time 73.63 seconds
Started Jul 29 08:00:16 PM PDT 24
Finished Jul 29 08:01:29 PM PDT 24
Peak memory 575952 kb
Host smart-3655cb80-c8bd-4d19-bf25-c206262ec284
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504831734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.3504831734
Directory /workspace/61.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.3557506259
Short name T2185
Test name
Test status
Simulation time 113814272866 ps
CPU time 1221.85 seconds
Started Jul 29 08:00:15 PM PDT 24
Finished Jul 29 08:20:38 PM PDT 24
Peak memory 576064 kb
Host smart-1dfb6d25-4bfd-47bd-8068-fdbd38666d88
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557506259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.3557506259
Directory /workspace/61.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.680236049
Short name T1666
Test name
Test status
Simulation time 7487943457 ps
CPU time 119.27 seconds
Started Jul 29 08:00:20 PM PDT 24
Finished Jul 29 08:02:19 PM PDT 24
Peak memory 575904 kb
Host smart-9aed74eb-2804-42b7-8c52-9c38d58f95ba
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680236049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.680236049
Directory /workspace/61.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.1266066750
Short name T607
Test name
Test status
Simulation time 172056402 ps
CPU time 18.72 seconds
Started Jul 29 08:00:16 PM PDT 24
Finished Jul 29 08:00:35 PM PDT 24
Peak memory 575932 kb
Host smart-27392a2a-86c3-46a6-bfaf-a54e868840a0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266066750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del
ays.1266066750
Directory /workspace/61.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_same_source.4114583144
Short name T606
Test name
Test status
Simulation time 544061548 ps
CPU time 17.8 seconds
Started Jul 29 08:00:23 PM PDT 24
Finished Jul 29 08:00:41 PM PDT 24
Peak memory 575832 kb
Host smart-7e5c6ff5-f992-452f-ad73-7b9d7b0c25d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114583144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.4114583144
Directory /workspace/61.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke.3749481121
Short name T2300
Test name
Test status
Simulation time 40743859 ps
CPU time 5.92 seconds
Started Jul 29 08:00:15 PM PDT 24
Finished Jul 29 08:00:21 PM PDT 24
Peak memory 573836 kb
Host smart-92c652d0-1cff-4ead-b174-6d1ff41c98e6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749481121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.3749481121
Directory /workspace/61.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.3891786980
Short name T2137
Test name
Test status
Simulation time 4614359369 ps
CPU time 50.41 seconds
Started Jul 29 08:00:19 PM PDT 24
Finished Jul 29 08:01:09 PM PDT 24
Peak memory 573932 kb
Host smart-3a9f39b2-7b77-48a8-96d2-179cfb1883d4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891786980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.3891786980
Directory /workspace/61.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.3951859069
Short name T2641
Test name
Test status
Simulation time 3901920494 ps
CPU time 67.07 seconds
Started Jul 29 08:00:19 PM PDT 24
Finished Jul 29 08:01:26 PM PDT 24
Peak memory 574616 kb
Host smart-1f6a1d89-0d72-4d77-9e82-c64aa0097c4a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951859069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.3951859069
Directory /workspace/61.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.3948125158
Short name T1530
Test name
Test status
Simulation time 50825138 ps
CPU time 6.55 seconds
Started Jul 29 08:00:17 PM PDT 24
Finished Jul 29 08:00:24 PM PDT 24
Peak memory 574608 kb
Host smart-79f729c9-7f8c-4dc0-8fd4-7ea7acf1e563
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948125158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay
s.3948125158
Directory /workspace/61.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.3049544874
Short name T1532
Test name
Test status
Simulation time 1679182334 ps
CPU time 126.95 seconds
Started Jul 29 08:00:29 PM PDT 24
Finished Jul 29 08:02:36 PM PDT 24
Peak memory 576160 kb
Host smart-7048b55d-17cb-4c57-8933-6f6ddd503f47
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049544874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.3049544874
Directory /workspace/61.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.1526102065
Short name T1642
Test name
Test status
Simulation time 2658642005 ps
CPU time 280.13 seconds
Started Jul 29 08:00:30 PM PDT 24
Finished Jul 29 08:05:10 PM PDT 24
Peak memory 576036 kb
Host smart-758fa6e8-5bc7-46ca-8e0b-e6e870afc818
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526102065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all
_with_rand_reset.1526102065
Directory /workspace/61.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.996145024
Short name T2218
Test name
Test status
Simulation time 44793478 ps
CPU time 20.46 seconds
Started Jul 29 08:00:24 PM PDT 24
Finished Jul 29 08:00:45 PM PDT 24
Peak memory 576284 kb
Host smart-9daf7f7b-097e-403e-ba04-562928600a04
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996145024 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all
_with_reset_error.996145024
Directory /workspace/61.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.2932707259
Short name T516
Test name
Test status
Simulation time 625047870 ps
CPU time 24.98 seconds
Started Jul 29 08:00:25 PM PDT 24
Finished Jul 29 08:00:50 PM PDT 24
Peak memory 575244 kb
Host smart-a4143390-f247-4971-849a-f4df529f1f94
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932707259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.2932707259
Directory /workspace/61.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_access_same_device.614664131
Short name T2175
Test name
Test status
Simulation time 1302673614 ps
CPU time 51.26 seconds
Started Jul 29 08:00:29 PM PDT 24
Finished Jul 29 08:01:20 PM PDT 24
Peak memory 575940 kb
Host smart-fd9f95ac-d16c-416f-ac20-ff1ed22318ff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614664131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device.
614664131
Directory /workspace/62.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.2853369668
Short name T1678
Test name
Test status
Simulation time 30332507815 ps
CPU time 461.19 seconds
Started Jul 29 08:00:25 PM PDT 24
Finished Jul 29 08:08:07 PM PDT 24
Peak memory 575164 kb
Host smart-2b38898b-1a70-4c36-ae04-b7fc7c68809d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853369668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_
device_slow_rsp.2853369668
Directory /workspace/62.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.3982832576
Short name T2036
Test name
Test status
Simulation time 156609727 ps
CPU time 9.47 seconds
Started Jul 29 08:00:23 PM PDT 24
Finished Jul 29 08:00:33 PM PDT 24
Peak memory 573920 kb
Host smart-86860ea2-a418-4b6a-8b79-376d91327991
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982832576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add
r.3982832576
Directory /workspace/62.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_error_random.3927304062
Short name T543
Test name
Test status
Simulation time 1171105714 ps
CPU time 42.92 seconds
Started Jul 29 08:00:23 PM PDT 24
Finished Jul 29 08:01:06 PM PDT 24
Peak memory 575944 kb
Host smart-324aaf70-d969-4848-89c5-34fc5246f8ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927304062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.3927304062
Directory /workspace/62.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random.1432554026
Short name T1874
Test name
Test status
Simulation time 1028354174 ps
CPU time 37.6 seconds
Started Jul 29 08:00:29 PM PDT 24
Finished Jul 29 08:01:07 PM PDT 24
Peak memory 575820 kb
Host smart-efe859f0-70dc-44e5-ba92-05e3a14e4737
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432554026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.1432554026
Directory /workspace/62.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.3326721067
Short name T1972
Test name
Test status
Simulation time 98464739480 ps
CPU time 985.6 seconds
Started Jul 29 08:00:26 PM PDT 24
Finished Jul 29 08:16:51 PM PDT 24
Peak memory 575956 kb
Host smart-d68c1d72-88f1-4f4c-92fb-0eb426567628
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326721067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.3326721067
Directory /workspace/62.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.1133813775
Short name T601
Test name
Test status
Simulation time 45204038100 ps
CPU time 811.69 seconds
Started Jul 29 08:00:26 PM PDT 24
Finished Jul 29 08:13:58 PM PDT 24
Peak memory 576104 kb
Host smart-cfcdb2f3-0364-4f07-a703-9cc344d88807
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133813775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.1133813775
Directory /workspace/62.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.2926737841
Short name T2850
Test name
Test status
Simulation time 297981441 ps
CPU time 27.07 seconds
Started Jul 29 08:00:22 PM PDT 24
Finished Jul 29 08:00:50 PM PDT 24
Peak memory 575948 kb
Host smart-9d464c32-a6c0-47f7-8fdf-87ef5ef3cf15
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926737841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del
ays.2926737841
Directory /workspace/62.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_same_source.1787338231
Short name T2662
Test name
Test status
Simulation time 1516212298 ps
CPU time 42.67 seconds
Started Jul 29 08:00:23 PM PDT 24
Finished Jul 29 08:01:06 PM PDT 24
Peak memory 575924 kb
Host smart-b3805cdc-f219-432e-ab72-484076fa1777
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787338231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.1787338231
Directory /workspace/62.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke.2781193910
Short name T2327
Test name
Test status
Simulation time 233744477 ps
CPU time 9.31 seconds
Started Jul 29 08:00:26 PM PDT 24
Finished Jul 29 08:00:35 PM PDT 24
Peak memory 574000 kb
Host smart-9e69e1f5-03ca-4599-a691-8f32b9a9212c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781193910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.2781193910
Directory /workspace/62.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.2841395241
Short name T568
Test name
Test status
Simulation time 7330394724 ps
CPU time 75.31 seconds
Started Jul 29 08:00:28 PM PDT 24
Finished Jul 29 08:01:43 PM PDT 24
Peak memory 573948 kb
Host smart-458800fa-f8a2-4909-9108-18c865dbfbc2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841395241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.2841395241
Directory /workspace/62.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.795865068
Short name T2644
Test name
Test status
Simulation time 3139246341 ps
CPU time 53.98 seconds
Started Jul 29 08:00:23 PM PDT 24
Finished Jul 29 08:01:17 PM PDT 24
Peak memory 573884 kb
Host smart-792e80f7-0232-44c6-bf9b-f5f6258218f7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795865068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.795865068
Directory /workspace/62.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.8630930
Short name T1549
Test name
Test status
Simulation time 42015757 ps
CPU time 5.97 seconds
Started Jul 29 08:00:26 PM PDT 24
Finished Jul 29 08:00:32 PM PDT 24
Peak memory 573940 kb
Host smart-7f1e8451-ccfa-4be8-8519-c7cd9b8fd2fe
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8630930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delays.8630930
Directory /workspace/62.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all.1072706484
Short name T2038
Test name
Test status
Simulation time 1506172996 ps
CPU time 118.09 seconds
Started Jul 29 08:00:28 PM PDT 24
Finished Jul 29 08:02:26 PM PDT 24
Peak memory 575912 kb
Host smart-df04b2f2-b2e6-4bad-90d6-c9e91753b567
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072706484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.1072706484
Directory /workspace/62.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.2459500585
Short name T2161
Test name
Test status
Simulation time 5172774583 ps
CPU time 168.59 seconds
Started Jul 29 08:00:30 PM PDT 24
Finished Jul 29 08:03:19 PM PDT 24
Peak memory 576072 kb
Host smart-acf2d279-923f-4f78-8fa3-d596db544891
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459500585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.2459500585
Directory /workspace/62.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.215087283
Short name T2442
Test name
Test status
Simulation time 9074305380 ps
CPU time 637.18 seconds
Started Jul 29 08:00:26 PM PDT 24
Finished Jul 29 08:11:04 PM PDT 24
Peak memory 576020 kb
Host smart-05eb7a57-e7c0-434a-b898-531ad5f1c275
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215087283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_
with_rand_reset.215087283
Directory /workspace/62.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.1944849644
Short name T2308
Test name
Test status
Simulation time 1437407349 ps
CPU time 133.47 seconds
Started Jul 29 08:00:32 PM PDT 24
Finished Jul 29 08:02:46 PM PDT 24
Peak memory 576800 kb
Host smart-9d988152-654b-4f51-943b-59fdfaa64eec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944849644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al
l_with_reset_error.1944849644
Directory /workspace/62.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.3028621041
Short name T1904
Test name
Test status
Simulation time 109106334 ps
CPU time 13.93 seconds
Started Jul 29 08:00:26 PM PDT 24
Finished Jul 29 08:00:40 PM PDT 24
Peak memory 576148 kb
Host smart-de6a2621-a651-47c3-8aa2-e8515017bbad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028621041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.3028621041
Directory /workspace/62.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_access_same_device.1720378257
Short name T1449
Test name
Test status
Simulation time 1502226465 ps
CPU time 52.07 seconds
Started Jul 29 08:00:34 PM PDT 24
Finished Jul 29 08:01:26 PM PDT 24
Peak memory 575924 kb
Host smart-b2f9007b-0560-44c7-99c0-1b9c70d2e4c2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720378257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device
.1720378257
Directory /workspace/63.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1446604069
Short name T2632
Test name
Test status
Simulation time 20111078877 ps
CPU time 350.62 seconds
Started Jul 29 08:00:35 PM PDT 24
Finished Jul 29 08:06:26 PM PDT 24
Peak memory 576032 kb
Host smart-ac8f311e-6af3-4b49-b8db-cbc7c6323d8a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446604069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_
device_slow_rsp.1446604069
Directory /workspace/63.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.2054388940
Short name T1426
Test name
Test status
Simulation time 497704520 ps
CPU time 20.27 seconds
Started Jul 29 08:00:33 PM PDT 24
Finished Jul 29 08:00:53 PM PDT 24
Peak memory 575796 kb
Host smart-486b87bf-90b3-49f2-9d8f-9ba2a9d8f039
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054388940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add
r.2054388940
Directory /workspace/63.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_error_random.3121696987
Short name T2260
Test name
Test status
Simulation time 62190409 ps
CPU time 7.75 seconds
Started Jul 29 08:00:31 PM PDT 24
Finished Jul 29 08:00:39 PM PDT 24
Peak memory 575924 kb
Host smart-e31cd320-1fe3-488a-8c78-3aa973a4d50e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121696987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.3121696987
Directory /workspace/63.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random.2014952350
Short name T1552
Test name
Test status
Simulation time 589623402 ps
CPU time 51.52 seconds
Started Jul 29 08:00:35 PM PDT 24
Finished Jul 29 08:01:27 PM PDT 24
Peak memory 576068 kb
Host smart-32514cf7-c7b4-4f9f-91dd-daf1c1ee7d4d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014952350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.2014952350
Directory /workspace/63.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.1301152287
Short name T1848
Test name
Test status
Simulation time 17592099581 ps
CPU time 182.52 seconds
Started Jul 29 08:00:29 PM PDT 24
Finished Jul 29 08:03:32 PM PDT 24
Peak memory 576136 kb
Host smart-03fa9815-d7b2-4a8e-990d-5163e02875e1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301152287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.1301152287
Directory /workspace/63.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.3168721434
Short name T2258
Test name
Test status
Simulation time 7925578998 ps
CPU time 137.45 seconds
Started Jul 29 08:00:33 PM PDT 24
Finished Jul 29 08:02:50 PM PDT 24
Peak memory 575972 kb
Host smart-43466318-a923-4277-bcda-01bf82db2d09
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168721434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.3168721434
Directory /workspace/63.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.1125948544
Short name T2869
Test name
Test status
Simulation time 457792431 ps
CPU time 35.23 seconds
Started Jul 29 08:00:33 PM PDT 24
Finished Jul 29 08:01:08 PM PDT 24
Peak memory 575888 kb
Host smart-9e396e04-5129-4b48-8abe-a7e8fab137bc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125948544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del
ays.1125948544
Directory /workspace/63.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_same_source.4265065844
Short name T678
Test name
Test status
Simulation time 1486325569 ps
CPU time 43.69 seconds
Started Jul 29 08:00:31 PM PDT 24
Finished Jul 29 08:01:14 PM PDT 24
Peak memory 575784 kb
Host smart-3b4880ea-7a9e-4c4a-95ff-19720932bd99
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265065844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.4265065844
Directory /workspace/63.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke.2185044900
Short name T630
Test name
Test status
Simulation time 219468935 ps
CPU time 8.75 seconds
Started Jul 29 08:00:33 PM PDT 24
Finished Jul 29 08:00:42 PM PDT 24
Peak memory 573888 kb
Host smart-d9ba84e8-44f7-4d06-8ad2-8c1a1d64982e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185044900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.2185044900
Directory /workspace/63.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.1536683522
Short name T2229
Test name
Test status
Simulation time 5810599967 ps
CPU time 95.02 seconds
Started Jul 29 08:00:31 PM PDT 24
Finished Jul 29 08:02:06 PM PDT 24
Peak memory 573960 kb
Host smart-9a6fedc9-8fba-43fc-abbf-f2e71efa119f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536683522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.1536683522
Directory /workspace/63.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.2518061981
Short name T2014
Test name
Test status
Simulation time 50770110 ps
CPU time 6.45 seconds
Started Jul 29 08:00:30 PM PDT 24
Finished Jul 29 08:00:36 PM PDT 24
Peak memory 574500 kb
Host smart-71cb9337-ceb1-40bf-be4a-82aa99e9dfcc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518061981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay
s.2518061981
Directory /workspace/63.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all.1668647589
Short name T2326
Test name
Test status
Simulation time 4658831982 ps
CPU time 183.55 seconds
Started Jul 29 08:00:33 PM PDT 24
Finished Jul 29 08:03:36 PM PDT 24
Peak memory 575988 kb
Host smart-45ef08ea-9e7d-4774-a760-06b71aaa136e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668647589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.1668647589
Directory /workspace/63.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.3108921491
Short name T2302
Test name
Test status
Simulation time 530471545 ps
CPU time 42.39 seconds
Started Jul 29 08:00:33 PM PDT 24
Finished Jul 29 08:01:15 PM PDT 24
Peak memory 575868 kb
Host smart-73a59a55-4b00-44f1-b7e8-6585539f3638
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108921491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.3108921491
Directory /workspace/63.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.849360258
Short name T885
Test name
Test status
Simulation time 622258601 ps
CPU time 179.75 seconds
Started Jul 29 08:00:36 PM PDT 24
Finished Jul 29 08:03:35 PM PDT 24
Peak memory 575992 kb
Host smart-7717d40f-3a45-4467-9a1f-7777ce978170
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849360258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_
with_rand_reset.849360258
Directory /workspace/63.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.524177430
Short name T2068
Test name
Test status
Simulation time 711150208 ps
CPU time 30.7 seconds
Started Jul 29 08:00:30 PM PDT 24
Finished Jul 29 08:01:00 PM PDT 24
Peak memory 575936 kb
Host smart-7b82e0fa-57ac-4aa3-a9cd-e941c120eab2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524177430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.524177430
Directory /workspace/63.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_access_same_device.3542377079
Short name T526
Test name
Test status
Simulation time 3367209833 ps
CPU time 140.81 seconds
Started Jul 29 08:00:35 PM PDT 24
Finished Jul 29 08:02:56 PM PDT 24
Peak memory 576100 kb
Host smart-49e39386-fc12-4aee-9a82-1e38dacfb6dd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542377079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device
.3542377079
Directory /workspace/64.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.3802480795
Short name T2703
Test name
Test status
Simulation time 95202942832 ps
CPU time 1755.51 seconds
Started Jul 29 08:00:36 PM PDT 24
Finished Jul 29 08:29:51 PM PDT 24
Peak memory 576124 kb
Host smart-d5a6ef41-1b1b-48b9-911b-95134ec59d6b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802480795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_
device_slow_rsp.3802480795
Directory /workspace/64.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.1610148238
Short name T1794
Test name
Test status
Simulation time 583914985 ps
CPU time 25.31 seconds
Started Jul 29 08:01:06 PM PDT 24
Finished Jul 29 08:01:32 PM PDT 24
Peak memory 576036 kb
Host smart-b0ddd694-0040-4886-82a6-354354cc0242
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610148238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add
r.1610148238
Directory /workspace/64.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_error_random.1929282197
Short name T1491
Test name
Test status
Simulation time 1741153427 ps
CPU time 68.05 seconds
Started Jul 29 08:00:36 PM PDT 24
Finished Jul 29 08:01:44 PM PDT 24
Peak memory 576016 kb
Host smart-8185f983-7dc7-40bd-82a6-a59fd550cc68
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929282197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.1929282197
Directory /workspace/64.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random.2613039103
Short name T1477
Test name
Test status
Simulation time 1310015041 ps
CPU time 45.87 seconds
Started Jul 29 08:00:35 PM PDT 24
Finished Jul 29 08:01:21 PM PDT 24
Peak memory 575928 kb
Host smart-beb506d0-5dbe-4597-8edf-b3705200a878
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613039103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.2613039103
Directory /workspace/64.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.4873985
Short name T1814
Test name
Test status
Simulation time 33682077869 ps
CPU time 374.91 seconds
Started Jul 29 08:00:43 PM PDT 24
Finished Jul 29 08:06:58 PM PDT 24
Peak memory 575908 kb
Host smart-17797b12-d2aa-4149-ae13-edec94596f11
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4873985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.4873985
Directory /workspace/64.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.1217080223
Short name T1941
Test name
Test status
Simulation time 17712385258 ps
CPU time 281.24 seconds
Started Jul 29 08:00:37 PM PDT 24
Finished Jul 29 08:05:18 PM PDT 24
Peak memory 575808 kb
Host smart-8a0b7109-b4e3-4e40-b908-5ec04fa3464d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217080223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.1217080223
Directory /workspace/64.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.526464817
Short name T2786
Test name
Test status
Simulation time 275287927 ps
CPU time 24.53 seconds
Started Jul 29 08:00:39 PM PDT 24
Finished Jul 29 08:01:04 PM PDT 24
Peak memory 575872 kb
Host smart-4d4b7e8e-03e5-48c0-850e-ff004b2768b8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526464817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_dela
ys.526464817
Directory /workspace/64.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_same_source.2051832082
Short name T2096
Test name
Test status
Simulation time 475626589 ps
CPU time 15.57 seconds
Started Jul 29 08:00:43 PM PDT 24
Finished Jul 29 08:00:58 PM PDT 24
Peak memory 575780 kb
Host smart-395af9f8-57dd-4f9c-ab89-641f9b9d4eca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051832082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.2051832082
Directory /workspace/64.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke.3341589254
Short name T2414
Test name
Test status
Simulation time 51707228 ps
CPU time 6.99 seconds
Started Jul 29 08:00:36 PM PDT 24
Finished Jul 29 08:00:43 PM PDT 24
Peak memory 573908 kb
Host smart-fe0a08c8-fff0-4443-b0c4-3b9fa51b3cb4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341589254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.3341589254
Directory /workspace/64.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.941049953
Short name T627
Test name
Test status
Simulation time 8040093853 ps
CPU time 83.43 seconds
Started Jul 29 08:00:38 PM PDT 24
Finished Jul 29 08:02:02 PM PDT 24
Peak memory 574024 kb
Host smart-5a4df971-fadd-4b79-b421-b18f6eef35e3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941049953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.941049953
Directory /workspace/64.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.4189106786
Short name T1840
Test name
Test status
Simulation time 5217545310 ps
CPU time 83.71 seconds
Started Jul 29 08:00:36 PM PDT 24
Finished Jul 29 08:02:00 PM PDT 24
Peak memory 573976 kb
Host smart-ea48846e-8a57-4be2-9062-9500d0b998c5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189106786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.4189106786
Directory /workspace/64.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.1260318563
Short name T1677
Test name
Test status
Simulation time 53922318 ps
CPU time 6.21 seconds
Started Jul 29 08:00:39 PM PDT 24
Finished Jul 29 08:00:45 PM PDT 24
Peak memory 573820 kb
Host smart-22ebd5ea-49d9-41e3-8351-5c9638e36f5f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260318563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay
s.1260318563
Directory /workspace/64.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all.3665993351
Short name T465
Test name
Test status
Simulation time 8779556184 ps
CPU time 306.86 seconds
Started Jul 29 08:01:04 PM PDT 24
Finished Jul 29 08:06:11 PM PDT 24
Peak memory 576964 kb
Host smart-bae50762-f08b-4a3b-8686-3e4af5fdc9ff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665993351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.3665993351
Directory /workspace/64.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.1010777756
Short name T1781
Test name
Test status
Simulation time 19679890917 ps
CPU time 739.58 seconds
Started Jul 29 08:01:01 PM PDT 24
Finished Jul 29 08:13:20 PM PDT 24
Peak memory 576140 kb
Host smart-b9b3a8af-6bbc-4658-aab8-f7c4c1dec562
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010777756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.1010777756
Directory /workspace/64.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.232632055
Short name T1504
Test name
Test status
Simulation time 512982124 ps
CPU time 207.74 seconds
Started Jul 29 08:01:02 PM PDT 24
Finished Jul 29 08:04:30 PM PDT 24
Peak memory 576016 kb
Host smart-c491a5b4-eaef-4ad8-9db7-6d714eb99382
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232632055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_
with_rand_reset.232632055
Directory /workspace/64.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3490795385
Short name T903
Test name
Test status
Simulation time 231118306 ps
CPU time 70.12 seconds
Started Jul 29 08:01:11 PM PDT 24
Finished Jul 29 08:02:21 PM PDT 24
Peak memory 575868 kb
Host smart-c50be238-6c1f-421f-a93f-fd602973495b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490795385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al
l_with_reset_error.3490795385
Directory /workspace/64.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.694705439
Short name T2499
Test name
Test status
Simulation time 650097504 ps
CPU time 28.55 seconds
Started Jul 29 08:00:43 PM PDT 24
Finished Jul 29 08:01:11 PM PDT 24
Peak memory 575964 kb
Host smart-5b3d1497-988b-4093-a3e3-4cf7c034b505
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694705439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.694705439
Directory /workspace/64.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_access_same_device.1517421123
Short name T854
Test name
Test status
Simulation time 1263732595 ps
CPU time 46.73 seconds
Started Jul 29 08:01:09 PM PDT 24
Finished Jul 29 08:01:56 PM PDT 24
Peak memory 575956 kb
Host smart-d2d32312-7456-4f90-8f2a-83397a788f97
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517421123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device
.1517421123
Directory /workspace/65.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.1301196559
Short name T1971
Test name
Test status
Simulation time 61793276933 ps
CPU time 1090.15 seconds
Started Jul 29 08:01:14 PM PDT 24
Finished Jul 29 08:19:25 PM PDT 24
Peak memory 576072 kb
Host smart-e294cf2c-011c-4e5c-bb1c-b4ba8d8eaf1a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301196559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_
device_slow_rsp.1301196559
Directory /workspace/65.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.1364949931
Short name T1429
Test name
Test status
Simulation time 72829546 ps
CPU time 10.31 seconds
Started Jul 29 08:01:07 PM PDT 24
Finished Jul 29 08:01:17 PM PDT 24
Peak memory 575924 kb
Host smart-e61b6875-4c72-4493-85b3-086d6f00c96e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364949931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add
r.1364949931
Directory /workspace/65.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_error_random.186954741
Short name T2531
Test name
Test status
Simulation time 451901076 ps
CPU time 36.15 seconds
Started Jul 29 08:01:09 PM PDT 24
Finished Jul 29 08:01:45 PM PDT 24
Peak memory 576040 kb
Host smart-a7c0e0d7-c950-4144-b970-9d48c3b0f880
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186954741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.186954741
Directory /workspace/65.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random.3263208263
Short name T2423
Test name
Test status
Simulation time 2370432894 ps
CPU time 81.44 seconds
Started Jul 29 08:01:09 PM PDT 24
Finished Jul 29 08:02:30 PM PDT 24
Peak memory 575944 kb
Host smart-985fcacf-2055-4ec9-9e3c-48be49ffc767
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263208263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.3263208263
Directory /workspace/65.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.3363426568
Short name T2335
Test name
Test status
Simulation time 9937267904 ps
CPU time 106.8 seconds
Started Jul 29 08:01:09 PM PDT 24
Finished Jul 29 08:02:56 PM PDT 24
Peak memory 575892 kb
Host smart-d46a0f6c-288c-4f9c-9932-ad5c0651f44e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363426568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.3363426568
Directory /workspace/65.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.2454062705
Short name T2018
Test name
Test status
Simulation time 47161652867 ps
CPU time 793.65 seconds
Started Jul 29 08:01:09 PM PDT 24
Finished Jul 29 08:14:23 PM PDT 24
Peak memory 575952 kb
Host smart-78130bb4-508c-4805-b111-825ec26c40a6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454062705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.2454062705
Directory /workspace/65.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.481149115
Short name T1824
Test name
Test status
Simulation time 327659565 ps
CPU time 28.33 seconds
Started Jul 29 08:01:10 PM PDT 24
Finished Jul 29 08:01:38 PM PDT 24
Peak memory 575764 kb
Host smart-e121a20a-6c2f-4209-b87e-617289e9fa14
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481149115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_dela
ys.481149115
Directory /workspace/65.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_same_source.2525611520
Short name T2366
Test name
Test status
Simulation time 990375174 ps
CPU time 28.05 seconds
Started Jul 29 08:01:08 PM PDT 24
Finished Jul 29 08:01:36 PM PDT 24
Peak memory 575960 kb
Host smart-85e7c86f-6f8f-4ffa-b526-dc061995d403
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525611520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.2525611520
Directory /workspace/65.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke.962745231
Short name T1863
Test name
Test status
Simulation time 253491129 ps
CPU time 10.07 seconds
Started Jul 29 08:01:07 PM PDT 24
Finished Jul 29 08:01:17 PM PDT 24
Peak memory 573860 kb
Host smart-5cda0b53-9d0b-408d-af7c-270cf96e4954
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962745231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.962745231
Directory /workspace/65.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.3912221701
Short name T2563
Test name
Test status
Simulation time 7572838580 ps
CPU time 79.94 seconds
Started Jul 29 08:01:09 PM PDT 24
Finished Jul 29 08:02:29 PM PDT 24
Peak memory 573944 kb
Host smart-ebed2f93-5f91-462a-9d2a-56e3dae0e521
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912221701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.3912221701
Directory /workspace/65.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.215898849
Short name T1460
Test name
Test status
Simulation time 5967000449 ps
CPU time 106.18 seconds
Started Jul 29 08:01:08 PM PDT 24
Finished Jul 29 08:02:55 PM PDT 24
Peak memory 574620 kb
Host smart-8ee16b58-8ea8-43bc-9122-a290539d3a25
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215898849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.215898849
Directory /workspace/65.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.2318790146
Short name T2501
Test name
Test status
Simulation time 51528083 ps
CPU time 6.8 seconds
Started Jul 29 08:01:08 PM PDT 24
Finished Jul 29 08:01:15 PM PDT 24
Peak memory 573824 kb
Host smart-e59ddbc2-4bc4-4c59-bc9a-e23b802a297e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318790146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay
s.2318790146
Directory /workspace/65.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all.1113811963
Short name T2244
Test name
Test status
Simulation time 2119180048 ps
CPU time 169.59 seconds
Started Jul 29 08:01:18 PM PDT 24
Finished Jul 29 08:04:08 PM PDT 24
Peak memory 576080 kb
Host smart-e500f8a9-b8d5-4876-80c2-7adca11bfcb2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113811963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.1113811963
Directory /workspace/65.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.2928432558
Short name T2605
Test name
Test status
Simulation time 220920902 ps
CPU time 84.38 seconds
Started Jul 29 08:01:08 PM PDT 24
Finished Jul 29 08:02:33 PM PDT 24
Peak memory 576740 kb
Host smart-6b4d58c8-b650-403f-8b26-27261b9b077a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928432558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all
_with_rand_reset.2928432558
Directory /workspace/65.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.2602953236
Short name T1748
Test name
Test status
Simulation time 2963586520 ps
CPU time 402.89 seconds
Started Jul 29 08:01:07 PM PDT 24
Finished Jul 29 08:07:50 PM PDT 24
Peak memory 576856 kb
Host smart-a875ed8f-3e7c-4601-acb1-8c81e9b44ac7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602953236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al
l_with_reset_error.2602953236
Directory /workspace/65.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.2550053593
Short name T2463
Test name
Test status
Simulation time 657377922 ps
CPU time 30.87 seconds
Started Jul 29 08:01:09 PM PDT 24
Finished Jul 29 08:01:40 PM PDT 24
Peak memory 576080 kb
Host smart-4c5176d8-b115-4c45-b6f8-83a71f44ace4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550053593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.2550053593
Directory /workspace/65.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_access_same_device.386233777
Short name T584
Test name
Test status
Simulation time 598806266 ps
CPU time 46.74 seconds
Started Jul 29 08:01:19 PM PDT 24
Finished Jul 29 08:02:06 PM PDT 24
Peak memory 575940 kb
Host smart-24b99267-1ba9-4601-b5e1-1f437353d8a6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386233777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device.
386233777
Directory /workspace/66.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.1608897628
Short name T1858
Test name
Test status
Simulation time 124199606705 ps
CPU time 2328.53 seconds
Started Jul 29 08:01:20 PM PDT 24
Finished Jul 29 08:40:10 PM PDT 24
Peak memory 575960 kb
Host smart-16cd45d6-0228-4056-80fb-6ea012dc121b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608897628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_
device_slow_rsp.1608897628
Directory /workspace/66.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.1994725650
Short name T1576
Test name
Test status
Simulation time 71084351 ps
CPU time 9.68 seconds
Started Jul 29 08:01:21 PM PDT 24
Finished Jul 29 08:01:31 PM PDT 24
Peak memory 576020 kb
Host smart-8dba69d9-76d3-46ed-9d9f-5df8538e2bbe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994725650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add
r.1994725650
Directory /workspace/66.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_error_random.288924278
Short name T2089
Test name
Test status
Simulation time 1968217358 ps
CPU time 65.39 seconds
Started Jul 29 08:01:19 PM PDT 24
Finished Jul 29 08:02:25 PM PDT 24
Peak memory 576008 kb
Host smart-de62ffea-c671-4425-b727-d51163e2b94d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288924278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.288924278
Directory /workspace/66.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random.41666858
Short name T2863
Test name
Test status
Simulation time 417742342 ps
CPU time 35.67 seconds
Started Jul 29 08:01:19 PM PDT 24
Finished Jul 29 08:01:55 PM PDT 24
Peak memory 576036 kb
Host smart-4d4dea93-a029-4605-a5fe-97dd0b0688b6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41666858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.41666858
Directory /workspace/66.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.2211622689
Short name T2312
Test name
Test status
Simulation time 11597591799 ps
CPU time 118.82 seconds
Started Jul 29 08:01:16 PM PDT 24
Finished Jul 29 08:03:15 PM PDT 24
Peak memory 576020 kb
Host smart-56ad7a28-57c7-4201-bc47-cd307ee38f91
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211622689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.2211622689
Directory /workspace/66.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.3802722397
Short name T585
Test name
Test status
Simulation time 48308034381 ps
CPU time 868.85 seconds
Started Jul 29 08:01:18 PM PDT 24
Finished Jul 29 08:15:47 PM PDT 24
Peak memory 576012 kb
Host smart-ab9cfee4-dfe0-49af-b98e-0b30db00db1a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802722397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.3802722397
Directory /workspace/66.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.1120701728
Short name T2571
Test name
Test status
Simulation time 196673515 ps
CPU time 18.57 seconds
Started Jul 29 08:01:20 PM PDT 24
Finished Jul 29 08:01:39 PM PDT 24
Peak memory 575884 kb
Host smart-43fd442e-a338-4bc8-8ec0-ab7e26c6d8c0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120701728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del
ays.1120701728
Directory /workspace/66.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_same_source.3567935039
Short name T440
Test name
Test status
Simulation time 395078698 ps
CPU time 30.26 seconds
Started Jul 29 08:01:23 PM PDT 24
Finished Jul 29 08:01:54 PM PDT 24
Peak memory 575812 kb
Host smart-d896ff04-b588-4b6f-813d-4fe2478fd080
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567935039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.3567935039
Directory /workspace/66.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke.3492022413
Short name T2745
Test name
Test status
Simulation time 45861401 ps
CPU time 6.2 seconds
Started Jul 29 08:01:09 PM PDT 24
Finished Jul 29 08:01:15 PM PDT 24
Peak memory 573952 kb
Host smart-afd464ae-5fcf-4fef-ba4b-11f11706e3b3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492022413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.3492022413
Directory /workspace/66.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.648617826
Short name T2156
Test name
Test status
Simulation time 10129520355 ps
CPU time 111.1 seconds
Started Jul 29 08:01:07 PM PDT 24
Finished Jul 29 08:02:58 PM PDT 24
Peak memory 574604 kb
Host smart-3d8732ef-6d11-4b2a-a3d2-a6023ef8ed5d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648617826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.648617826
Directory /workspace/66.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.136982224
Short name T2527
Test name
Test status
Simulation time 4681165727 ps
CPU time 73.91 seconds
Started Jul 29 08:01:08 PM PDT 24
Finished Jul 29 08:02:22 PM PDT 24
Peak memory 574620 kb
Host smart-55db4bb4-7011-4ba5-b580-c5c8f91fe796
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136982224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.136982224
Directory /workspace/66.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.3834077450
Short name T1689
Test name
Test status
Simulation time 49329720 ps
CPU time 6.23 seconds
Started Jul 29 08:01:09 PM PDT 24
Finished Jul 29 08:01:15 PM PDT 24
Peak memory 574536 kb
Host smart-f6fdc616-5161-43ab-8898-601c1285a618
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834077450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay
s.3834077450
Directory /workspace/66.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all.4273910733
Short name T2534
Test name
Test status
Simulation time 2916856764 ps
CPU time 246.05 seconds
Started Jul 29 08:01:23 PM PDT 24
Finished Jul 29 08:05:29 PM PDT 24
Peak memory 576852 kb
Host smart-15108b21-2857-4224-95bb-f1fcce67dc8c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273910733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.4273910733
Directory /workspace/66.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.3275769431
Short name T1537
Test name
Test status
Simulation time 769670658 ps
CPU time 63.35 seconds
Started Jul 29 08:01:23 PM PDT 24
Finished Jul 29 08:02:26 PM PDT 24
Peak memory 576032 kb
Host smart-0ddd4a02-8b37-43dc-96d1-51db77523f31
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275769431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.3275769431
Directory /workspace/66.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.2695715658
Short name T2245
Test name
Test status
Simulation time 1380596166 ps
CPU time 298.29 seconds
Started Jul 29 08:01:30 PM PDT 24
Finished Jul 29 08:06:28 PM PDT 24
Peak memory 575940 kb
Host smart-3ad43264-641b-43bc-8ca7-3b25732db6e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695715658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all
_with_rand_reset.2695715658
Directory /workspace/66.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.660824371
Short name T2579
Test name
Test status
Simulation time 451281043 ps
CPU time 140.61 seconds
Started Jul 29 08:01:20 PM PDT 24
Finished Jul 29 08:03:41 PM PDT 24
Peak memory 575980 kb
Host smart-a27e85c6-7da5-4388-a2e2-8330d563b96c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660824371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all
_with_reset_error.660824371
Directory /workspace/66.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.4018467026
Short name T2835
Test name
Test status
Simulation time 193279224 ps
CPU time 20.88 seconds
Started Jul 29 08:01:17 PM PDT 24
Finished Jul 29 08:01:38 PM PDT 24
Peak memory 576088 kb
Host smart-9a921bbf-0794-410d-94d3-12a876c90cc6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018467026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.4018467026
Directory /workspace/66.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_access_same_device.741989094
Short name T846
Test name
Test status
Simulation time 530084938 ps
CPU time 34.51 seconds
Started Jul 29 08:01:20 PM PDT 24
Finished Jul 29 08:01:55 PM PDT 24
Peak memory 575844 kb
Host smart-0391e64c-1c84-40b6-b9dd-fc74da68d1dc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741989094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device.
741989094
Directory /workspace/67.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.1160572530
Short name T860
Test name
Test status
Simulation time 57429115604 ps
CPU time 982.46 seconds
Started Jul 29 08:01:22 PM PDT 24
Finished Jul 29 08:17:45 PM PDT 24
Peak memory 576116 kb
Host smart-066d6061-e918-4276-b562-fc7151ed7afd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160572530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_
device_slow_rsp.1160572530
Directory /workspace/67.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.108926707
Short name T2555
Test name
Test status
Simulation time 1104798207 ps
CPU time 48.49 seconds
Started Jul 29 08:01:17 PM PDT 24
Finished Jul 29 08:02:06 PM PDT 24
Peak memory 576036 kb
Host smart-87b4ee54-22c6-4499-b14c-063be533fa76
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108926707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_addr
.108926707
Directory /workspace/67.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_error_random.3360866910
Short name T2120
Test name
Test status
Simulation time 2283366786 ps
CPU time 79.32 seconds
Started Jul 29 08:01:21 PM PDT 24
Finished Jul 29 08:02:41 PM PDT 24
Peak memory 576020 kb
Host smart-0cebebad-a5e4-445b-952c-1cff90a61d17
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360866910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.3360866910
Directory /workspace/67.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random.3847317408
Short name T2034
Test name
Test status
Simulation time 647656016 ps
CPU time 24.18 seconds
Started Jul 29 08:01:17 PM PDT 24
Finished Jul 29 08:01:41 PM PDT 24
Peak memory 575824 kb
Host smart-0b7863cd-7a1a-4aac-8bdf-109df370e39f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847317408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.3847317408
Directory /workspace/67.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.1460231354
Short name T1436
Test name
Test status
Simulation time 4029300243 ps
CPU time 42.92 seconds
Started Jul 29 08:01:18 PM PDT 24
Finished Jul 29 08:02:01 PM PDT 24
Peak memory 573896 kb
Host smart-36cdb5e8-b7a8-4b12-a89e-d3597285323c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460231354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.1460231354
Directory /workspace/67.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.2714185973
Short name T2666
Test name
Test status
Simulation time 14065843359 ps
CPU time 224.46 seconds
Started Jul 29 08:01:20 PM PDT 24
Finished Jul 29 08:05:05 PM PDT 24
Peak memory 575940 kb
Host smart-8d690f74-7d4a-40de-abd2-fbed118ef3fe
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714185973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.2714185973
Directory /workspace/67.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.2728619115
Short name T2180
Test name
Test status
Simulation time 355004497 ps
CPU time 29.16 seconds
Started Jul 29 08:01:21 PM PDT 24
Finished Jul 29 08:01:51 PM PDT 24
Peak memory 575960 kb
Host smart-4c175f1b-811e-4240-9bd1-4d0171417dfa
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728619115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del
ays.2728619115
Directory /workspace/67.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_same_source.752745243
Short name T592
Test name
Test status
Simulation time 2500754562 ps
CPU time 77.05 seconds
Started Jul 29 08:01:22 PM PDT 24
Finished Jul 29 08:02:39 PM PDT 24
Peak memory 576092 kb
Host smart-b55a5b13-1d58-49a8-817e-0e58e13a355e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752745243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.752745243
Directory /workspace/67.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke.689477722
Short name T2860
Test name
Test status
Simulation time 220431636 ps
CPU time 9.35 seconds
Started Jul 29 08:01:20 PM PDT 24
Finished Jul 29 08:01:29 PM PDT 24
Peak memory 573848 kb
Host smart-68743a79-e668-4237-8e06-768b2df1e6c8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689477722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.689477722
Directory /workspace/67.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.1504651789
Short name T1631
Test name
Test status
Simulation time 7043364512 ps
CPU time 69.37 seconds
Started Jul 29 08:01:21 PM PDT 24
Finished Jul 29 08:02:31 PM PDT 24
Peak memory 574004 kb
Host smart-c0cca2a4-07ac-44d1-92df-471a844418d7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504651789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.1504651789
Directory /workspace/67.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.317972102
Short name T1855
Test name
Test status
Simulation time 6466036278 ps
CPU time 109.44 seconds
Started Jul 29 08:01:17 PM PDT 24
Finished Jul 29 08:03:07 PM PDT 24
Peak memory 573828 kb
Host smart-f8f58ab6-4801-4713-8413-6e84e6716387
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317972102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.317972102
Directory /workspace/67.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.4077164100
Short name T1501
Test name
Test status
Simulation time 52829189 ps
CPU time 6.68 seconds
Started Jul 29 08:01:19 PM PDT 24
Finished Jul 29 08:01:26 PM PDT 24
Peak memory 574680 kb
Host smart-2f251415-d9ef-416a-b1a9-486dc231db74
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077164100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay
s.4077164100
Directory /workspace/67.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all.3350806832
Short name T2322
Test name
Test status
Simulation time 2605540488 ps
CPU time 97.71 seconds
Started Jul 29 08:01:18 PM PDT 24
Finished Jul 29 08:02:56 PM PDT 24
Peak memory 576072 kb
Host smart-5e68fa10-a960-4a10-a10c-e916cc8b7216
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350806832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.3350806832
Directory /workspace/67.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.2024706404
Short name T2672
Test name
Test status
Simulation time 2405314363 ps
CPU time 177.75 seconds
Started Jul 29 08:01:21 PM PDT 24
Finished Jul 29 08:04:19 PM PDT 24
Peak memory 576180 kb
Host smart-6ccc9a79-4178-42e9-84a7-53265be9043b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024706404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.2024706404
Directory /workspace/67.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2310624940
Short name T2115
Test name
Test status
Simulation time 762684780 ps
CPU time 256.53 seconds
Started Jul 29 08:01:18 PM PDT 24
Finished Jul 29 08:05:34 PM PDT 24
Peak memory 575988 kb
Host smart-5e85f1d5-42ee-49a4-a889-3ff4682a3450
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310624940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all
_with_rand_reset.2310624940
Directory /workspace/67.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.4289853126
Short name T2368
Test name
Test status
Simulation time 4240543283 ps
CPU time 490.8 seconds
Started Jul 29 08:01:17 PM PDT 24
Finished Jul 29 08:09:28 PM PDT 24
Peak memory 576800 kb
Host smart-254a90ea-2d7b-4581-801a-e3cc714e6e3d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289853126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al
l_with_reset_error.4289853126
Directory /workspace/67.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.2629246043
Short name T1974
Test name
Test status
Simulation time 435785781 ps
CPU time 20.46 seconds
Started Jul 29 08:01:20 PM PDT 24
Finished Jul 29 08:01:40 PM PDT 24
Peak memory 575928 kb
Host smart-fc5da4e1-25cf-4ad0-af03-8b5296bf7403
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629246043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.2629246043
Directory /workspace/67.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_access_same_device.3228291322
Short name T855
Test name
Test status
Simulation time 574187842 ps
CPU time 27.05 seconds
Started Jul 29 08:01:25 PM PDT 24
Finished Jul 29 08:01:52 PM PDT 24
Peak memory 575800 kb
Host smart-00c5f143-930e-43b6-8970-9861c7de5e6b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228291322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device
.3228291322
Directory /workspace/68.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3001879949
Short name T2865
Test name
Test status
Simulation time 78695181556 ps
CPU time 1366.02 seconds
Started Jul 29 08:01:30 PM PDT 24
Finished Jul 29 08:24:17 PM PDT 24
Peak memory 575932 kb
Host smart-bb35a914-eb46-47db-b692-66584298608e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001879949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_
device_slow_rsp.3001879949
Directory /workspace/68.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.3478416396
Short name T1555
Test name
Test status
Simulation time 196341885 ps
CPU time 21.45 seconds
Started Jul 29 08:01:31 PM PDT 24
Finished Jul 29 08:01:52 PM PDT 24
Peak memory 575904 kb
Host smart-0186aa77-6ff0-4016-b04e-3ef8adc5b3da
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478416396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add
r.3478416396
Directory /workspace/68.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_error_random.1136472629
Short name T2814
Test name
Test status
Simulation time 847233925 ps
CPU time 29.66 seconds
Started Jul 29 08:01:30 PM PDT 24
Finished Jul 29 08:02:00 PM PDT 24
Peak memory 575940 kb
Host smart-c3979799-8ac1-4d44-98f9-ed01ee66cdfa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136472629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.1136472629
Directory /workspace/68.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.1106673385
Short name T2226
Test name
Test status
Simulation time 64457584902 ps
CPU time 718.87 seconds
Started Jul 29 08:01:18 PM PDT 24
Finished Jul 29 08:13:17 PM PDT 24
Peak memory 576020 kb
Host smart-1e4c8fda-6f7f-45ca-927a-6a6e5d0ef2b6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106673385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.1106673385
Directory /workspace/68.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.2017169311
Short name T1668
Test name
Test status
Simulation time 53047191405 ps
CPU time 912.92 seconds
Started Jul 29 08:01:18 PM PDT 24
Finished Jul 29 08:16:31 PM PDT 24
Peak memory 576056 kb
Host smart-48890787-de98-4066-b0e0-68a46a5db415
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017169311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.2017169311
Directory /workspace/68.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.643520756
Short name T1769
Test name
Test status
Simulation time 578476281 ps
CPU time 48.82 seconds
Started Jul 29 08:01:19 PM PDT 24
Finished Jul 29 08:02:08 PM PDT 24
Peak memory 575952 kb
Host smart-e7649dfc-38ef-4836-acf3-71e9e79f5f2e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643520756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_dela
ys.643520756
Directory /workspace/68.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_same_source.4026301376
Short name T2039
Test name
Test status
Simulation time 1795685290 ps
CPU time 51.38 seconds
Started Jul 29 08:01:30 PM PDT 24
Finished Jul 29 08:02:22 PM PDT 24
Peak memory 576008 kb
Host smart-f7057b17-0a8c-49e2-9070-c374c6f03934
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026301376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.4026301376
Directory /workspace/68.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke.1605535285
Short name T1942
Test name
Test status
Simulation time 182014089 ps
CPU time 8.49 seconds
Started Jul 29 08:01:19 PM PDT 24
Finished Jul 29 08:01:27 PM PDT 24
Peak memory 573808 kb
Host smart-8181a01c-00c1-4efd-bd6d-93f308c5160d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605535285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.1605535285
Directory /workspace/68.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.2278058058
Short name T2223
Test name
Test status
Simulation time 8877819254 ps
CPU time 92.58 seconds
Started Jul 29 08:01:17 PM PDT 24
Finished Jul 29 08:02:49 PM PDT 24
Peak memory 573956 kb
Host smart-a26b69ab-0bf4-4278-b77b-9929bf86b29b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278058058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.2278058058
Directory /workspace/68.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.3447252602
Short name T1416
Test name
Test status
Simulation time 5771164446 ps
CPU time 92.37 seconds
Started Jul 29 08:01:35 PM PDT 24
Finished Jul 29 08:03:08 PM PDT 24
Peak memory 573912 kb
Host smart-17b58154-915d-4b81-94e0-e5063ef896d4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447252602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.3447252602
Directory /workspace/68.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2843245486
Short name T2394
Test name
Test status
Simulation time 44238765 ps
CPU time 6.24 seconds
Started Jul 29 08:01:20 PM PDT 24
Finished Jul 29 08:01:26 PM PDT 24
Peak memory 573880 kb
Host smart-4549ec91-1e01-48b0-b0c9-f9f0ba9b90b8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843245486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay
s.2843245486
Directory /workspace/68.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all.3771154865
Short name T473
Test name
Test status
Simulation time 5909743495 ps
CPU time 198.27 seconds
Started Jul 29 08:01:29 PM PDT 24
Finished Jul 29 08:04:47 PM PDT 24
Peak memory 576256 kb
Host smart-78692c55-ac28-4219-b9ea-0b8412fabbf9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771154865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.3771154865
Directory /workspace/68.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.1142888820
Short name T1768
Test name
Test status
Simulation time 15620786322 ps
CPU time 584.38 seconds
Started Jul 29 08:01:32 PM PDT 24
Finished Jul 29 08:11:16 PM PDT 24
Peak memory 576848 kb
Host smart-055dff20-6e0c-4a56-b1b8-7dcbd2edf10c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142888820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.1142888820
Directory /workspace/68.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.411107497
Short name T625
Test name
Test status
Simulation time 482519907 ps
CPU time 185.28 seconds
Started Jul 29 08:01:29 PM PDT 24
Finished Jul 29 08:04:34 PM PDT 24
Peak memory 576776 kb
Host smart-2d13c69f-69fc-4926-adfa-98a675ffec57
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411107497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_
with_rand_reset.411107497
Directory /workspace/68.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3141573438
Short name T2250
Test name
Test status
Simulation time 1731505064 ps
CPU time 176.58 seconds
Started Jul 29 08:01:31 PM PDT 24
Finished Jul 29 08:04:27 PM PDT 24
Peak memory 576780 kb
Host smart-5bc304c2-e3f0-4c4e-bbd3-6c8dd3e713a9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141573438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al
l_with_reset_error.3141573438
Directory /workspace/68.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.356515077
Short name T1905
Test name
Test status
Simulation time 1251210335 ps
CPU time 52.83 seconds
Started Jul 29 08:01:32 PM PDT 24
Finished Jul 29 08:02:25 PM PDT 24
Peak memory 575876 kb
Host smart-5291eabe-6932-4b04-a8cc-a750dfa265cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356515077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.356515077
Directory /workspace/68.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_access_same_device.2913538340
Short name T2543
Test name
Test status
Simulation time 996559844 ps
CPU time 64.37 seconds
Started Jul 29 08:01:34 PM PDT 24
Finished Jul 29 08:02:39 PM PDT 24
Peak memory 576000 kb
Host smart-cde81cd6-fb53-4940-8f51-af122d237523
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913538340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device
.2913538340
Directory /workspace/69.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.532305353
Short name T2739
Test name
Test status
Simulation time 10592493830 ps
CPU time 186.76 seconds
Started Jul 29 08:01:41 PM PDT 24
Finished Jul 29 08:04:47 PM PDT 24
Peak memory 574060 kb
Host smart-80026afc-4d68-4b46-8e61-acaaddc654f9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532305353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_d
evice_slow_rsp.532305353
Directory /workspace/69.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.254739970
Short name T554
Test name
Test status
Simulation time 25499462 ps
CPU time 5.17 seconds
Started Jul 29 08:01:41 PM PDT 24
Finished Jul 29 08:01:46 PM PDT 24
Peak memory 574464 kb
Host smart-d393f4bb-7ecd-4d0f-b93f-e2bf94382c02
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254739970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_addr
.254739970
Directory /workspace/69.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_error_random.169967329
Short name T1595
Test name
Test status
Simulation time 398597590 ps
CPU time 17.52 seconds
Started Jul 29 08:01:47 PM PDT 24
Finished Jul 29 08:02:05 PM PDT 24
Peak memory 575964 kb
Host smart-a041fb12-a9f6-451b-832d-964e57fbffe1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169967329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.169967329
Directory /workspace/69.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random.2164897259
Short name T1961
Test name
Test status
Simulation time 2141934284 ps
CPU time 70.25 seconds
Started Jul 29 08:01:28 PM PDT 24
Finished Jul 29 08:02:38 PM PDT 24
Peak memory 575988 kb
Host smart-3b8d3f01-371e-40cc-bba1-07ed6d72c67b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164897259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.2164897259
Directory /workspace/69.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.119067752
Short name T484
Test name
Test status
Simulation time 62301510885 ps
CPU time 678.87 seconds
Started Jul 29 08:01:32 PM PDT 24
Finished Jul 29 08:12:52 PM PDT 24
Peak memory 575904 kb
Host smart-0a57697e-50d3-482a-89c3-28504e25324b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119067752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.119067752
Directory /workspace/69.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.1524100367
Short name T2540
Test name
Test status
Simulation time 37255131341 ps
CPU time 606.28 seconds
Started Jul 29 08:01:31 PM PDT 24
Finished Jul 29 08:11:38 PM PDT 24
Peak memory 576004 kb
Host smart-25837d07-a1b4-496b-8ad5-12b126947cc3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524100367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.1524100367
Directory /workspace/69.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.194155927
Short name T2729
Test name
Test status
Simulation time 163511413 ps
CPU time 15.96 seconds
Started Jul 29 08:01:30 PM PDT 24
Finished Jul 29 08:01:46 PM PDT 24
Peak memory 575944 kb
Host smart-e809c2c0-8962-48cb-9266-52b49ab2e197
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194155927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_dela
ys.194155927
Directory /workspace/69.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_same_source.2333862897
Short name T1810
Test name
Test status
Simulation time 556934980 ps
CPU time 37.5 seconds
Started Jul 29 08:01:41 PM PDT 24
Finished Jul 29 08:02:19 PM PDT 24
Peak memory 575816 kb
Host smart-89ddf553-8d8c-4fe7-a43a-660df145e697
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333862897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.2333862897
Directory /workspace/69.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke.2432948346
Short name T2789
Test name
Test status
Simulation time 49986136 ps
CPU time 6.53 seconds
Started Jul 29 08:01:29 PM PDT 24
Finished Jul 29 08:01:36 PM PDT 24
Peak memory 573988 kb
Host smart-bc080fab-9a2f-4c1b-af5a-c9fd3c467c2f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432948346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.2432948346
Directory /workspace/69.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.114119679
Short name T1841
Test name
Test status
Simulation time 7192179530 ps
CPU time 70.17 seconds
Started Jul 29 08:01:29 PM PDT 24
Finished Jul 29 08:02:40 PM PDT 24
Peak memory 574680 kb
Host smart-9c5ac2bc-0f66-4e26-94ab-9e3146928cc8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114119679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.114119679
Directory /workspace/69.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.913634975
Short name T2436
Test name
Test status
Simulation time 4491587802 ps
CPU time 75.33 seconds
Started Jul 29 08:01:34 PM PDT 24
Finished Jul 29 08:02:49 PM PDT 24
Peak memory 573916 kb
Host smart-fa3b9154-65a1-4d9b-a2f2-39aefc93a25b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913634975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.913634975
Directory /workspace/69.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.1959789833
Short name T2125
Test name
Test status
Simulation time 41250142 ps
CPU time 6.32 seconds
Started Jul 29 08:01:30 PM PDT 24
Finished Jul 29 08:01:36 PM PDT 24
Peak memory 573868 kb
Host smart-34bf7657-9814-4edd-907a-01a80a45c65d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959789833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay
s.1959789833
Directory /workspace/69.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all.78958646
Short name T2525
Test name
Test status
Simulation time 1330375935 ps
CPU time 54.18 seconds
Started Jul 29 08:01:41 PM PDT 24
Finished Jul 29 08:02:35 PM PDT 24
Peak memory 575976 kb
Host smart-34b45ace-3e96-4055-9582-e3498236ea74
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78958646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.78958646
Directory /workspace/69.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.741683144
Short name T2674
Test name
Test status
Simulation time 7714795058 ps
CPU time 238.12 seconds
Started Jul 29 08:01:40 PM PDT 24
Finished Jul 29 08:05:38 PM PDT 24
Peak memory 576280 kb
Host smart-494348c7-8219-4eb4-929d-e61d75a46dde
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741683144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.741683144
Directory /workspace/69.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.2727786523
Short name T2524
Test name
Test status
Simulation time 420519746 ps
CPU time 158.68 seconds
Started Jul 29 08:01:39 PM PDT 24
Finished Jul 29 08:04:18 PM PDT 24
Peak memory 576740 kb
Host smart-e5ffd080-91d5-4c2e-a4d8-3b36f773528a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727786523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all
_with_rand_reset.2727786523
Directory /workspace/69.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.4249801121
Short name T2282
Test name
Test status
Simulation time 109240105 ps
CPU time 21.13 seconds
Started Jul 29 08:01:41 PM PDT 24
Finished Jul 29 08:02:02 PM PDT 24
Peak memory 576084 kb
Host smart-3c9a510b-2c12-414a-8a49-e6a983a02a81
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249801121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al
l_with_reset_error.4249801121
Directory /workspace/69.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.2451712268
Short name T2906
Test name
Test status
Simulation time 230776379 ps
CPU time 11.84 seconds
Started Jul 29 08:01:42 PM PDT 24
Finished Jul 29 08:01:54 PM PDT 24
Peak memory 575992 kb
Host smart-b9345451-1d64-4fb0-b628-84d6aa7ff2b6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451712268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.2451712268
Directory /workspace/69.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.1670665121
Short name T2458
Test name
Test status
Simulation time 8686735782 ps
CPU time 800.41 seconds
Started Jul 29 07:50:18 PM PDT 24
Finished Jul 29 08:03:38 PM PDT 24
Peak memory 652100 kb
Host smart-b9f89d02-6617-4e56-91f7-d76abdea4426
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670665121 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.1670665121
Directory /workspace/7.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.chip_csr_rw.1902223427
Short name T2062
Test name
Test status
Simulation time 6310384600 ps
CPU time 636.13 seconds
Started Jul 29 07:50:21 PM PDT 24
Finished Jul 29 08:00:57 PM PDT 24
Peak memory 598936 kb
Host smart-d4b19fd6-7267-4039-8b77-e3b9a252b363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902223427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.1902223427
Directory /workspace/7.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.3707027401
Short name T382
Test name
Test status
Simulation time 29597600720 ps
CPU time 4371.01 seconds
Started Jul 29 07:50:15 PM PDT 24
Finished Jul 29 09:03:06 PM PDT 24
Peak memory 593456 kb
Host smart-be25146a-d726-460a-a67c-3a68a0aa786b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707027401 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.3707027401
Directory /workspace/7.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_access_same_device.2218014137
Short name T1977
Test name
Test status
Simulation time 3644793785 ps
CPU time 143.8 seconds
Started Jul 29 07:50:13 PM PDT 24
Finished Jul 29 07:52:37 PM PDT 24
Peak memory 576044 kb
Host smart-6013ea38-0fad-4d4b-b76a-8c9f3ab2eca3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218014137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.
2218014137
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.2987321486
Short name T1945
Test name
Test status
Simulation time 19293428132 ps
CPU time 326.42 seconds
Started Jul 29 07:50:14 PM PDT 24
Finished Jul 29 07:55:41 PM PDT 24
Peak memory 576192 kb
Host smart-de0e3b08-e504-492e-b223-3e0ac3cae6b9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987321486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d
evice_slow_rsp.2987321486
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.2042492806
Short name T2032
Test name
Test status
Simulation time 297527117 ps
CPU time 32.13 seconds
Started Jul 29 07:50:23 PM PDT 24
Finished Jul 29 07:50:55 PM PDT 24
Peak memory 575848 kb
Host smart-8c103215-d45e-4f6c-bc19-5747ba5255a6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042492806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr
.2042492806
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_error_random.3971648652
Short name T2216
Test name
Test status
Simulation time 2490380348 ps
CPU time 83.97 seconds
Started Jul 29 07:50:18 PM PDT 24
Finished Jul 29 07:51:42 PM PDT 24
Peak memory 575796 kb
Host smart-6af586d1-3db8-481c-b09d-de9af8590ab6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971648652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3971648652
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random.2479816237
Short name T2261
Test name
Test status
Simulation time 178168973 ps
CPU time 16.99 seconds
Started Jul 29 07:50:18 PM PDT 24
Finished Jul 29 07:50:35 PM PDT 24
Peak memory 575988 kb
Host smart-ab3f9b4e-ade2-4971-b09f-2a24cec58559
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479816237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.2479816237
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.3106099520
Short name T2118
Test name
Test status
Simulation time 80422336866 ps
CPU time 841.55 seconds
Started Jul 29 07:50:10 PM PDT 24
Finished Jul 29 08:04:12 PM PDT 24
Peak memory 576104 kb
Host smart-fb17019b-df30-42c6-8ddb-385e7fbafe56
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106099520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3106099520
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.1015751495
Short name T2876
Test name
Test status
Simulation time 11418405201 ps
CPU time 185.92 seconds
Started Jul 29 07:50:13 PM PDT 24
Finished Jul 29 07:53:19 PM PDT 24
Peak memory 575980 kb
Host smart-d47b16c4-b368-42c5-9d28-64d42904c530
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015751495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1015751495
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.3035687655
Short name T576
Test name
Test status
Simulation time 322217138 ps
CPU time 28.17 seconds
Started Jul 29 07:50:13 PM PDT 24
Finished Jul 29 07:50:41 PM PDT 24
Peak memory 575932 kb
Host smart-ebb602be-aa3d-4ac8-b560-28423086630a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035687655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela
ys.3035687655
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_same_source.3672575228
Short name T1804
Test name
Test status
Simulation time 809294195 ps
CPU time 24.47 seconds
Started Jul 29 07:50:23 PM PDT 24
Finished Jul 29 07:50:47 PM PDT 24
Peak memory 576012 kb
Host smart-d4f2a3bc-f6cb-4a7c-b9e4-ffde4f010a9e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672575228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3672575228
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke.3627750525
Short name T2108
Test name
Test status
Simulation time 213922733 ps
CPU time 9.25 seconds
Started Jul 29 07:50:14 PM PDT 24
Finished Jul 29 07:50:23 PM PDT 24
Peak memory 573920 kb
Host smart-27dc6f20-06d2-4449-8da8-44d8c28d00ec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627750525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3627750525
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.2783431441
Short name T2557
Test name
Test status
Simulation time 7739712949 ps
CPU time 77.36 seconds
Started Jul 29 07:50:17 PM PDT 24
Finished Jul 29 07:51:34 PM PDT 24
Peak memory 573996 kb
Host smart-d49053e8-987d-4ae7-903d-280066835b21
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783431441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2783431441
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.1581954615
Short name T1891
Test name
Test status
Simulation time 3799427827 ps
CPU time 64.45 seconds
Started Jul 29 07:50:21 PM PDT 24
Finished Jul 29 07:51:25 PM PDT 24
Peak memory 573916 kb
Host smart-b78b635a-e0ec-4ebe-9f75-c9f7831e9880
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581954615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1581954615
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.4052481486
Short name T2349
Test name
Test status
Simulation time 47873013 ps
CPU time 6.18 seconds
Started Jul 29 07:50:14 PM PDT 24
Finished Jul 29 07:50:20 PM PDT 24
Peak memory 573856 kb
Host smart-7e5717ed-73d2-4c04-95a2-93a437268e40
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052481486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays
.4052481486
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all.4005501365
Short name T609
Test name
Test status
Simulation time 4140852517 ps
CPU time 360.49 seconds
Started Jul 29 07:50:13 PM PDT 24
Finished Jul 29 07:56:14 PM PDT 24
Peak memory 576868 kb
Host smart-37e5aabc-07f9-489a-b0d0-f5fd2d7b6af8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005501365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.4005501365
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.1049216477
Short name T2861
Test name
Test status
Simulation time 16434466568 ps
CPU time 604.65 seconds
Started Jul 29 07:50:20 PM PDT 24
Finished Jul 29 08:00:25 PM PDT 24
Peak memory 576996 kb
Host smart-98c1e313-6948-4ee0-84e4-2f75cbdf7f40
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049216477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1049216477
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.2328221454
Short name T2391
Test name
Test status
Simulation time 166126032 ps
CPU time 123.27 seconds
Started Jul 29 07:50:25 PM PDT 24
Finished Jul 29 07:52:28 PM PDT 24
Peak memory 576760 kb
Host smart-f3f68eb9-1242-4ed4-ae85-d8319a24ecbe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328221454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_
with_rand_reset.2328221454
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3611808142
Short name T2481
Test name
Test status
Simulation time 3019190608 ps
CPU time 263.7 seconds
Started Jul 29 07:50:24 PM PDT 24
Finished Jul 29 07:54:48 PM PDT 24
Peak memory 576056 kb
Host smart-40f5c9e0-066e-4e22-8490-f47bbc967ef6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611808142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all
_with_reset_error.3611808142
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.2974581261
Short name T1571
Test name
Test status
Simulation time 368137575 ps
CPU time 17.45 seconds
Started Jul 29 07:50:11 PM PDT 24
Finished Jul 29 07:50:28 PM PDT 24
Peak memory 575876 kb
Host smart-4491ab96-f1b3-42e4-8775-0759bc422352
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974581261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2974581261
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_access_same_device.2738514898
Short name T2776
Test name
Test status
Simulation time 2361020975 ps
CPU time 85.69 seconds
Started Jul 29 08:01:46 PM PDT 24
Finished Jul 29 08:03:12 PM PDT 24
Peak memory 576112 kb
Host smart-e501add9-2690-404b-8365-146eee3ea83b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738514898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device
.2738514898
Directory /workspace/70.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.575131914
Short name T2623
Test name
Test status
Simulation time 23604509505 ps
CPU time 390.2 seconds
Started Jul 29 08:01:40 PM PDT 24
Finished Jul 29 08:08:10 PM PDT 24
Peak memory 576036 kb
Host smart-11f51010-6cce-4b53-bba8-408e9e1a8bd3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575131914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_d
evice_slow_rsp.575131914
Directory /workspace/70.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.422497510
Short name T2677
Test name
Test status
Simulation time 859031641 ps
CPU time 33.28 seconds
Started Jul 29 08:01:47 PM PDT 24
Finished Jul 29 08:02:20 PM PDT 24
Peak memory 575564 kb
Host smart-d22fedfe-d826-4be3-b5e4-af25bd93a407
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422497510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_addr
.422497510
Directory /workspace/70.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_error_random.3178980339
Short name T1994
Test name
Test status
Simulation time 155755716 ps
CPU time 12.93 seconds
Started Jul 29 08:01:47 PM PDT 24
Finished Jul 29 08:02:00 PM PDT 24
Peak memory 575992 kb
Host smart-f72b68af-b625-44f3-896c-022df4fc4265
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178980339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.3178980339
Directory /workspace/70.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random.2497507112
Short name T696
Test name
Test status
Simulation time 571170260 ps
CPU time 41.95 seconds
Started Jul 29 08:01:40 PM PDT 24
Finished Jul 29 08:02:22 PM PDT 24
Peak memory 575980 kb
Host smart-45fd6ae9-3f27-4412-ad9a-755713f5a34a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497507112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.2497507112
Directory /workspace/70.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.1355718570
Short name T2171
Test name
Test status
Simulation time 116125539555 ps
CPU time 1236.99 seconds
Started Jul 29 08:01:47 PM PDT 24
Finished Jul 29 08:22:25 PM PDT 24
Peak memory 575932 kb
Host smart-74f03522-db31-47bd-bdf9-f783a5039ebf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355718570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.1355718570
Directory /workspace/70.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.719035880
Short name T605
Test name
Test status
Simulation time 63586930886 ps
CPU time 1087.17 seconds
Started Jul 29 08:01:41 PM PDT 24
Finished Jul 29 08:19:49 PM PDT 24
Peak memory 576140 kb
Host smart-cd337cee-8112-44e0-a610-ec5529bd8693
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719035880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.719035880
Directory /workspace/70.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.3401379773
Short name T2778
Test name
Test status
Simulation time 504998461 ps
CPU time 44.17 seconds
Started Jul 29 08:01:40 PM PDT 24
Finished Jul 29 08:02:24 PM PDT 24
Peak memory 575820 kb
Host smart-c5192180-277e-4ba3-a0a6-1dc636fe33e9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401379773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del
ays.3401379773
Directory /workspace/70.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_same_source.405980429
Short name T2078
Test name
Test status
Simulation time 586370419 ps
CPU time 18.29 seconds
Started Jul 29 08:01:43 PM PDT 24
Finished Jul 29 08:02:01 PM PDT 24
Peak memory 575688 kb
Host smart-69a9deb7-031a-4f49-a9e0-806ae4172f35
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405980429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.405980429
Directory /workspace/70.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke.2072645749
Short name T2578
Test name
Test status
Simulation time 209527897 ps
CPU time 8.43 seconds
Started Jul 29 08:01:43 PM PDT 24
Finished Jul 29 08:01:51 PM PDT 24
Peak memory 573832 kb
Host smart-719ab92c-d442-4c39-acdc-f70d04de9e8d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072645749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.2072645749
Directory /workspace/70.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.3623920431
Short name T1562
Test name
Test status
Simulation time 7575916186 ps
CPU time 82.5 seconds
Started Jul 29 08:01:40 PM PDT 24
Finished Jul 29 08:03:03 PM PDT 24
Peak memory 574644 kb
Host smart-65aafa3a-339c-4134-9776-d69a4042cbf3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623920431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.3623920431
Directory /workspace/70.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.1791574397
Short name T2200
Test name
Test status
Simulation time 5359153163 ps
CPU time 90.82 seconds
Started Jul 29 08:01:47 PM PDT 24
Finished Jul 29 08:03:18 PM PDT 24
Peak memory 573952 kb
Host smart-f03f8781-9225-4bba-b23c-5a35c9fcdce1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791574397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.1791574397
Directory /workspace/70.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.3745698952
Short name T2144
Test name
Test status
Simulation time 49369050 ps
CPU time 6.46 seconds
Started Jul 29 08:01:41 PM PDT 24
Finished Jul 29 08:01:47 PM PDT 24
Peak memory 574492 kb
Host smart-466a4e15-2600-40b8-bae9-57d006b5385c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745698952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay
s.3745698952
Directory /workspace/70.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all.362384936
Short name T2149
Test name
Test status
Simulation time 14486161934 ps
CPU time 572.28 seconds
Started Jul 29 08:01:49 PM PDT 24
Finished Jul 29 08:11:21 PM PDT 24
Peak memory 576260 kb
Host smart-bf5432f8-2736-454b-9279-2ebed3f70341
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362384936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.362384936
Directory /workspace/70.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.4147067021
Short name T1894
Test name
Test status
Simulation time 13307049594 ps
CPU time 473.82 seconds
Started Jul 29 08:01:55 PM PDT 24
Finished Jul 29 08:09:49 PM PDT 24
Peak memory 576872 kb
Host smart-e6d5adaf-9b6b-4069-b1d3-db5c591948f8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147067021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.4147067021
Directory /workspace/70.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.3202172969
Short name T2901
Test name
Test status
Simulation time 5542275376 ps
CPU time 306.17 seconds
Started Jul 29 08:01:50 PM PDT 24
Finished Jul 29 08:06:57 PM PDT 24
Peak memory 576012 kb
Host smart-e55dea80-871a-4cee-a63b-8ec84e3b0e31
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202172969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all
_with_rand_reset.3202172969
Directory /workspace/70.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.1104254127
Short name T2252
Test name
Test status
Simulation time 210018326 ps
CPU time 49.39 seconds
Started Jul 29 08:01:52 PM PDT 24
Finished Jul 29 08:02:42 PM PDT 24
Peak memory 576620 kb
Host smart-9e0b5c5f-a644-4737-83dd-48eaa6e28f26
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104254127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al
l_with_reset_error.1104254127
Directory /workspace/70.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.3392806087
Short name T638
Test name
Test status
Simulation time 266617075 ps
CPU time 13.58 seconds
Started Jul 29 08:01:54 PM PDT 24
Finished Jul 29 08:02:08 PM PDT 24
Peak memory 575880 kb
Host smart-13c241ee-735c-4277-86b7-37eada0e96b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392806087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.3392806087
Directory /workspace/70.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_access_same_device.4086354917
Short name T2804
Test name
Test status
Simulation time 883531959 ps
CPU time 66.39 seconds
Started Jul 29 08:01:49 PM PDT 24
Finished Jul 29 08:02:56 PM PDT 24
Peak memory 575992 kb
Host smart-dedc67ee-6591-4b2c-98dd-65c6a2a98fb0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086354917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device
.4086354917
Directory /workspace/71.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2421238850
Short name T2741
Test name
Test status
Simulation time 132488917843 ps
CPU time 2254.17 seconds
Started Jul 29 08:01:51 PM PDT 24
Finished Jul 29 08:39:25 PM PDT 24
Peak memory 576228 kb
Host smart-9aa1fd69-f1e9-4f02-99a1-0bd28e57d9f5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421238850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_
device_slow_rsp.2421238850
Directory /workspace/71.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2750058004
Short name T2870
Test name
Test status
Simulation time 1470579630 ps
CPU time 59.07 seconds
Started Jul 29 08:01:58 PM PDT 24
Finished Jul 29 08:02:57 PM PDT 24
Peak memory 575976 kb
Host smart-67799096-aebf-453b-9e5b-df6fbe6ea334
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750058004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add
r.2750058004
Directory /workspace/71.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_error_random.3780479435
Short name T1803
Test name
Test status
Simulation time 597788180 ps
CPU time 47.49 seconds
Started Jul 29 08:01:54 PM PDT 24
Finished Jul 29 08:02:42 PM PDT 24
Peak memory 576028 kb
Host smart-c8282a1e-dccb-42fd-8328-31ede3170d11
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780479435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.3780479435
Directory /workspace/71.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random.754150020
Short name T2710
Test name
Test status
Simulation time 580798286 ps
CPU time 52.95 seconds
Started Jul 29 08:01:52 PM PDT 24
Finished Jul 29 08:02:45 PM PDT 24
Peak memory 576152 kb
Host smart-a242c796-62ad-4f75-adc8-5271f5b9bfc5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754150020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.754150020
Directory /workspace/71.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.2586869140
Short name T2134
Test name
Test status
Simulation time 3164766539 ps
CPU time 35.29 seconds
Started Jul 29 08:01:49 PM PDT 24
Finished Jul 29 08:02:24 PM PDT 24
Peak memory 573876 kb
Host smart-f9ef752c-93f1-43bc-b2f0-3c77fdb66278
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586869140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.2586869140
Directory /workspace/71.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.1550557638
Short name T1999
Test name
Test status
Simulation time 66014701244 ps
CPU time 1108.12 seconds
Started Jul 29 08:01:49 PM PDT 24
Finished Jul 29 08:20:17 PM PDT 24
Peak memory 576120 kb
Host smart-165e3f44-136d-4e0b-a21b-07139917322b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550557638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.1550557638
Directory /workspace/71.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.1699637543
Short name T1478
Test name
Test status
Simulation time 91529970 ps
CPU time 10.95 seconds
Started Jul 29 08:01:49 PM PDT 24
Finished Jul 29 08:02:00 PM PDT 24
Peak memory 575784 kb
Host smart-586af0b3-2147-4d6f-acc6-9e94d4462bf0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699637543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del
ays.1699637543
Directory /workspace/71.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_same_source.3321130399
Short name T2684
Test name
Test status
Simulation time 201075971 ps
CPU time 8.96 seconds
Started Jul 29 08:01:55 PM PDT 24
Finished Jul 29 08:02:04 PM PDT 24
Peak memory 573868 kb
Host smart-1a51bdc3-5aba-43fd-aa31-7b5a3278dc62
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321130399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.3321130399
Directory /workspace/71.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke.2370906174
Short name T617
Test name
Test status
Simulation time 203599704 ps
CPU time 9.21 seconds
Started Jul 29 08:01:54 PM PDT 24
Finished Jul 29 08:02:03 PM PDT 24
Peak memory 573732 kb
Host smart-a0472f91-c372-4ca1-972b-a7fe86bb1f1d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370906174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.2370906174
Directory /workspace/71.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.1465295563
Short name T2727
Test name
Test status
Simulation time 8191542462 ps
CPU time 82.45 seconds
Started Jul 29 08:01:49 PM PDT 24
Finished Jul 29 08:03:12 PM PDT 24
Peak memory 573960 kb
Host smart-8ed8d4fc-8e8b-486e-9d1e-c9ae7a81a113
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465295563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.1465295563
Directory /workspace/71.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.381110837
Short name T2256
Test name
Test status
Simulation time 3645342122 ps
CPU time 60.46 seconds
Started Jul 29 08:01:53 PM PDT 24
Finished Jul 29 08:02:54 PM PDT 24
Peak memory 573880 kb
Host smart-dc28287b-69ee-4d0a-b010-0a4d5d37e83c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381110837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.381110837
Directory /workspace/71.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.3291877089
Short name T2730
Test name
Test status
Simulation time 40395978 ps
CPU time 5.93 seconds
Started Jul 29 08:01:48 PM PDT 24
Finished Jul 29 08:01:54 PM PDT 24
Peak memory 574492 kb
Host smart-b3a1b58d-4149-4189-8c5a-f852a10cdd25
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291877089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay
s.3291877089
Directory /workspace/71.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all.3309826287
Short name T2270
Test name
Test status
Simulation time 13673259197 ps
CPU time 470.37 seconds
Started Jul 29 08:01:59 PM PDT 24
Finished Jul 29 08:09:49 PM PDT 24
Peak memory 576764 kb
Host smart-1f4730ee-ccb1-41b5-b697-09c9b3d25779
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309826287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.3309826287
Directory /workspace/71.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.3573008112
Short name T646
Test name
Test status
Simulation time 2955725296 ps
CPU time 227.2 seconds
Started Jul 29 08:01:57 PM PDT 24
Finished Jul 29 08:05:44 PM PDT 24
Peak memory 576708 kb
Host smart-f9d8eb23-0e21-4158-8b50-bed3605d869e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573008112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.3573008112
Directory /workspace/71.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.1220868743
Short name T588
Test name
Test status
Simulation time 2932661433 ps
CPU time 266.26 seconds
Started Jul 29 08:01:57 PM PDT 24
Finished Jul 29 08:06:23 PM PDT 24
Peak memory 575956 kb
Host smart-a8b3f12f-a701-4e52-86c3-b415654ce99b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220868743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all
_with_rand_reset.1220868743
Directory /workspace/71.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.3956875150
Short name T2806
Test name
Test status
Simulation time 281925167 ps
CPU time 33.2 seconds
Started Jul 29 08:02:04 PM PDT 24
Finished Jul 29 08:02:37 PM PDT 24
Peak memory 576076 kb
Host smart-0785f861-9d20-4671-8ec8-61f55342ce65
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956875150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.3956875150
Directory /workspace/71.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_access_same_device.232000430
Short name T1792
Test name
Test status
Simulation time 942205250 ps
CPU time 71.32 seconds
Started Jul 29 08:02:03 PM PDT 24
Finished Jul 29 08:03:15 PM PDT 24
Peak memory 575988 kb
Host smart-64d13451-cdae-45e9-abdd-c5ff66120c08
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232000430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device.
232000430
Directory /workspace/72.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.1539371492
Short name T2915
Test name
Test status
Simulation time 23647225740 ps
CPU time 411.53 seconds
Started Jul 29 08:02:05 PM PDT 24
Finished Jul 29 08:08:57 PM PDT 24
Peak memory 575880 kb
Host smart-d18a4582-cff2-491e-ae7d-7a381af34ec0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539371492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_
device_slow_rsp.1539371492
Directory /workspace/72.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.2363864705
Short name T1629
Test name
Test status
Simulation time 780989725 ps
CPU time 31.88 seconds
Started Jul 29 08:02:05 PM PDT 24
Finished Jul 29 08:02:37 PM PDT 24
Peak memory 576124 kb
Host smart-351a33e0-ee69-4a59-923b-95a1da7ed440
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363864705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add
r.2363864705
Directory /workspace/72.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_error_random.279079825
Short name T1701
Test name
Test status
Simulation time 456994561 ps
CPU time 18.07 seconds
Started Jul 29 08:02:04 PM PDT 24
Finished Jul 29 08:02:23 PM PDT 24
Peak memory 575920 kb
Host smart-0a47bf9f-d533-4b21-896d-08c514ff14a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279079825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.279079825
Directory /workspace/72.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random.2497152373
Short name T1850
Test name
Test status
Simulation time 408407332 ps
CPU time 15.99 seconds
Started Jul 29 08:01:56 PM PDT 24
Finished Jul 29 08:02:12 PM PDT 24
Peak memory 575980 kb
Host smart-16a7f190-f906-4517-9ecf-2a9e059012c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497152373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.2497152373
Directory /workspace/72.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.960933586
Short name T2471
Test name
Test status
Simulation time 71410777790 ps
CPU time 804.85 seconds
Started Jul 29 08:02:04 PM PDT 24
Finished Jul 29 08:15:29 PM PDT 24
Peak memory 576092 kb
Host smart-f45f8c96-613b-41b4-9c69-d8ff346df815
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960933586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.960933586
Directory /workspace/72.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.3657449756
Short name T1521
Test name
Test status
Simulation time 36578400931 ps
CPU time 609.94 seconds
Started Jul 29 08:01:58 PM PDT 24
Finished Jul 29 08:12:08 PM PDT 24
Peak memory 576040 kb
Host smart-d2db71c8-d57c-451e-9636-140ef1fd08c6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657449756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.3657449756
Directory /workspace/72.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.3198374480
Short name T467
Test name
Test status
Simulation time 436995782 ps
CPU time 37.59 seconds
Started Jul 29 08:01:58 PM PDT 24
Finished Jul 29 08:02:36 PM PDT 24
Peak memory 575824 kb
Host smart-f1fd2096-45ab-4a2f-95c0-a22190f232e7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198374480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del
ays.3198374480
Directory /workspace/72.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_same_source.3666305264
Short name T2615
Test name
Test status
Simulation time 286784169 ps
CPU time 21.14 seconds
Started Jul 29 08:02:06 PM PDT 24
Finished Jul 29 08:02:28 PM PDT 24
Peak memory 575960 kb
Host smart-4293205a-e7c6-4d94-8381-c7392e4950b9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666305264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.3666305264
Directory /workspace/72.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke.2778181981
Short name T1421
Test name
Test status
Simulation time 187203235 ps
CPU time 8.96 seconds
Started Jul 29 08:01:58 PM PDT 24
Finished Jul 29 08:02:07 PM PDT 24
Peak memory 573884 kb
Host smart-480e7a4f-7dfb-4e51-93db-baf49a6e46cd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778181981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.2778181981
Directory /workspace/72.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.3667844387
Short name T1499
Test name
Test status
Simulation time 10240597272 ps
CPU time 103.49 seconds
Started Jul 29 08:01:58 PM PDT 24
Finished Jul 29 08:03:41 PM PDT 24
Peak memory 574648 kb
Host smart-e1860220-29cd-4763-8222-68e0784a2fd7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667844387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.3667844387
Directory /workspace/72.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.2173196901
Short name T2482
Test name
Test status
Simulation time 5392776278 ps
CPU time 87.77 seconds
Started Jul 29 08:01:58 PM PDT 24
Finished Jul 29 08:03:26 PM PDT 24
Peak memory 574640 kb
Host smart-6ddd412b-6c6c-4bb8-8214-eac27ca85786
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173196901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.2173196901
Directory /workspace/72.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1152960356
Short name T2507
Test name
Test status
Simulation time 44430443 ps
CPU time 6.5 seconds
Started Jul 29 08:01:58 PM PDT 24
Finished Jul 29 08:02:04 PM PDT 24
Peak memory 573740 kb
Host smart-6a12a689-01c7-488c-86ca-52f9cb56c27e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152960356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay
s.1152960356
Directory /workspace/72.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all.1375695161
Short name T2265
Test name
Test status
Simulation time 4394125570 ps
CPU time 150.44 seconds
Started Jul 29 08:02:07 PM PDT 24
Finished Jul 29 08:04:38 PM PDT 24
Peak memory 575964 kb
Host smart-ebb681de-6417-4d6d-96af-aff8d19e79c0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375695161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.1375695161
Directory /workspace/72.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.3497690135
Short name T842
Test name
Test status
Simulation time 4114220926 ps
CPU time 141.33 seconds
Started Jul 29 08:02:04 PM PDT 24
Finished Jul 29 08:04:25 PM PDT 24
Peak memory 575888 kb
Host smart-26f2792e-a9d2-47fc-b777-a3cf857b4698
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497690135 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.3497690135
Directory /workspace/72.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.2629809029
Short name T600
Test name
Test status
Simulation time 1679985949 ps
CPU time 287.18 seconds
Started Jul 29 08:02:08 PM PDT 24
Finished Jul 29 08:06:55 PM PDT 24
Peak memory 575964 kb
Host smart-140d325a-4486-4ede-9d7e-351e7be6acc1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629809029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all
_with_rand_reset.2629809029
Directory /workspace/72.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.2731039848
Short name T2837
Test name
Test status
Simulation time 6346210741 ps
CPU time 680.07 seconds
Started Jul 29 08:02:08 PM PDT 24
Finished Jul 29 08:13:28 PM PDT 24
Peak memory 582804 kb
Host smart-dbc019e2-057b-43bb-a843-14863ef6bcd2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731039848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al
l_with_reset_error.2731039848
Directory /workspace/72.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.359760178
Short name T1544
Test name
Test status
Simulation time 873647413 ps
CPU time 33.55 seconds
Started Jul 29 08:02:07 PM PDT 24
Finished Jul 29 08:02:40 PM PDT 24
Peak memory 576020 kb
Host smart-1f037679-5633-4f43-a17a-f3a2fc6cdb1a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359760178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.359760178
Directory /workspace/72.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_access_same_device.4121548110
Short name T861
Test name
Test status
Simulation time 1571274420 ps
CPU time 61.31 seconds
Started Jul 29 08:02:12 PM PDT 24
Finished Jul 29 08:03:14 PM PDT 24
Peak memory 575828 kb
Host smart-0d60ef5b-1bc3-48b5-a1c6-d37f4da5d1b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121548110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device
.4121548110
Directory /workspace/73.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.3125221363
Short name T2809
Test name
Test status
Simulation time 63642132847 ps
CPU time 1131.18 seconds
Started Jul 29 08:02:13 PM PDT 24
Finished Jul 29 08:21:05 PM PDT 24
Peak memory 576048 kb
Host smart-4b5beb3d-6bbf-47bf-945f-6036dec00c29
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125221363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_
device_slow_rsp.3125221363
Directory /workspace/73.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.2920305080
Short name T2735
Test name
Test status
Simulation time 331861883 ps
CPU time 33.96 seconds
Started Jul 29 08:02:13 PM PDT 24
Finished Jul 29 08:02:47 PM PDT 24
Peak memory 576004 kb
Host smart-d59269a8-2f2a-4ec1-9902-1af66ce14016
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920305080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add
r.2920305080
Directory /workspace/73.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_error_random.1447636395
Short name T2111
Test name
Test status
Simulation time 1339723939 ps
CPU time 44.23 seconds
Started Jul 29 08:02:15 PM PDT 24
Finished Jul 29 08:03:00 PM PDT 24
Peak memory 575768 kb
Host smart-500e02f4-ce59-47d2-841a-b9b0dda19872
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447636395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.1447636395
Directory /workspace/73.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random.1748042807
Short name T599
Test name
Test status
Simulation time 945749959 ps
CPU time 30.44 seconds
Started Jul 29 08:02:10 PM PDT 24
Finished Jul 29 08:02:40 PM PDT 24
Peak memory 575956 kb
Host smart-18abdd8b-3a62-4499-938c-58d3df353ca7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748042807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.1748042807
Directory /workspace/73.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.1442706633
Short name T2446
Test name
Test status
Simulation time 63192188825 ps
CPU time 662.33 seconds
Started Jul 29 08:02:11 PM PDT 24
Finished Jul 29 08:13:14 PM PDT 24
Peak memory 575888 kb
Host smart-07b55f8f-2f4e-4af2-9a05-f5d40af2a733
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442706633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.1442706633
Directory /workspace/73.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.2189662867
Short name T1505
Test name
Test status
Simulation time 62486662556 ps
CPU time 1121.52 seconds
Started Jul 29 08:02:13 PM PDT 24
Finished Jul 29 08:20:55 PM PDT 24
Peak memory 576096 kb
Host smart-b7ffa593-fe13-4d81-b0ad-d8ea0df89864
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189662867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.2189662867
Directory /workspace/73.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.2989321057
Short name T2490
Test name
Test status
Simulation time 310717777 ps
CPU time 25.39 seconds
Started Jul 29 08:02:15 PM PDT 24
Finished Jul 29 08:02:40 PM PDT 24
Peak memory 575980 kb
Host smart-c81603b8-4a1d-4920-bb7d-20d965f5eabb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989321057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del
ays.2989321057
Directory /workspace/73.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_same_source.3386602706
Short name T2884
Test name
Test status
Simulation time 277608250 ps
CPU time 20.64 seconds
Started Jul 29 08:02:10 PM PDT 24
Finished Jul 29 08:02:31 PM PDT 24
Peak memory 575804 kb
Host smart-dd3633e2-814d-4362-9441-a345cdc6939d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386602706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.3386602706
Directory /workspace/73.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke.1636448021
Short name T2792
Test name
Test status
Simulation time 37082345 ps
CPU time 5.71 seconds
Started Jul 29 08:02:04 PM PDT 24
Finished Jul 29 08:02:10 PM PDT 24
Peak memory 573892 kb
Host smart-6136a8d0-6ce0-4764-b829-e07d68320839
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636448021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.1636448021
Directory /workspace/73.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.1668831113
Short name T2182
Test name
Test status
Simulation time 10018019285 ps
CPU time 100.13 seconds
Started Jul 29 08:02:05 PM PDT 24
Finished Jul 29 08:03:45 PM PDT 24
Peak memory 573936 kb
Host smart-861f652d-e9f7-4b4c-9be7-e9b4234eef8b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668831113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.1668831113
Directory /workspace/73.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1374498725
Short name T1608
Test name
Test status
Simulation time 2801574761 ps
CPU time 48.63 seconds
Started Jul 29 08:02:05 PM PDT 24
Finished Jul 29 08:02:54 PM PDT 24
Peak memory 574616 kb
Host smart-5c946f43-1390-4d09-adfd-b0eecb0f0e5a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374498725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.1374498725
Directory /workspace/73.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.1499660228
Short name T1515
Test name
Test status
Simulation time 42732352 ps
CPU time 6.23 seconds
Started Jul 29 08:02:04 PM PDT 24
Finished Jul 29 08:02:10 PM PDT 24
Peak memory 574520 kb
Host smart-22ee2c81-7e73-41d5-b400-b4f80f6580e8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499660228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay
s.1499660228
Directory /workspace/73.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all.2977254963
Short name T2635
Test name
Test status
Simulation time 13725354590 ps
CPU time 572.24 seconds
Started Jul 29 08:02:12 PM PDT 24
Finished Jul 29 08:11:45 PM PDT 24
Peak memory 576868 kb
Host smart-32ba3301-c6f5-4669-845a-e6e20a343a06
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977254963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.2977254963
Directory /workspace/73.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.2937970374
Short name T1393
Test name
Test status
Simulation time 466669126 ps
CPU time 34.72 seconds
Started Jul 29 08:02:15 PM PDT 24
Finished Jul 29 08:02:50 PM PDT 24
Peak memory 576024 kb
Host smart-5699bd16-0439-434a-aa53-f2230672a539
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937970374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.2937970374
Directory /workspace/73.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.591529325
Short name T566
Test name
Test status
Simulation time 725343139 ps
CPU time 276.49 seconds
Started Jul 29 08:02:16 PM PDT 24
Finished Jul 29 08:06:52 PM PDT 24
Peak memory 576796 kb
Host smart-86515a15-cd25-4258-ab25-6ce17947f5ee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591529325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_
with_rand_reset.591529325
Directory /workspace/73.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.559375980
Short name T2667
Test name
Test status
Simulation time 352306374 ps
CPU time 78.31 seconds
Started Jul 29 08:02:12 PM PDT 24
Finished Jul 29 08:03:31 PM PDT 24
Peak memory 576908 kb
Host smart-03fef8ef-54ab-4f65-87e0-2b3e46824993
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559375980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all
_with_reset_error.559375980
Directory /workspace/73.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.3830310521
Short name T1694
Test name
Test status
Simulation time 248998812 ps
CPU time 28.71 seconds
Started Jul 29 08:02:13 PM PDT 24
Finished Jul 29 08:02:41 PM PDT 24
Peak memory 576000 kb
Host smart-f36ffb95-4ade-4e7f-9a8d-04db21e32a73
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830310521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.3830310521
Directory /workspace/73.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_access_same_device.1559747379
Short name T1529
Test name
Test status
Simulation time 2036154566 ps
CPU time 76.89 seconds
Started Jul 29 08:02:21 PM PDT 24
Finished Jul 29 08:03:38 PM PDT 24
Peak memory 575932 kb
Host smart-053ddc45-4b40-4680-8b90-6798581f87f8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559747379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device
.1559747379
Directory /workspace/74.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.2079041144
Short name T2184
Test name
Test status
Simulation time 36162391475 ps
CPU time 619.64 seconds
Started Jul 29 08:02:17 PM PDT 24
Finished Jul 29 08:12:36 PM PDT 24
Peak memory 576096 kb
Host smart-614e9a90-721e-4805-86bb-e55dfe3ca942
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079041144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_
device_slow_rsp.2079041144
Directory /workspace/74.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.395846794
Short name T1727
Test name
Test status
Simulation time 552024330 ps
CPU time 23.58 seconds
Started Jul 29 08:02:18 PM PDT 24
Finished Jul 29 08:02:41 PM PDT 24
Peak memory 575992 kb
Host smart-1bcaec9e-2ff6-443c-b53c-7a7250a54dff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395846794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_addr
.395846794
Directory /workspace/74.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random.1476910922
Short name T653
Test name
Test status
Simulation time 349468672 ps
CPU time 27.61 seconds
Started Jul 29 08:02:18 PM PDT 24
Finished Jul 29 08:02:46 PM PDT 24
Peak memory 575816 kb
Host smart-f1f89c2b-1757-4d31-ba20-a90b417738de
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476910922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.1476910922
Directory /workspace/74.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.2581793734
Short name T2015
Test name
Test status
Simulation time 5799943304 ps
CPU time 58.86 seconds
Started Jul 29 08:02:19 PM PDT 24
Finished Jul 29 08:03:18 PM PDT 24
Peak memory 574668 kb
Host smart-0f932d90-2d07-4c1a-ae7f-babedf53703b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581793734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.2581793734
Directory /workspace/74.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.3569375680
Short name T2025
Test name
Test status
Simulation time 56539448819 ps
CPU time 1064.28 seconds
Started Jul 29 08:02:18 PM PDT 24
Finished Jul 29 08:20:02 PM PDT 24
Peak memory 576108 kb
Host smart-f4d6fe7c-d5f1-4a37-a3ac-69acc6334a49
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569375680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.3569375680
Directory /workspace/74.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.547776993
Short name T2709
Test name
Test status
Simulation time 465015034 ps
CPU time 43.77 seconds
Started Jul 29 08:02:19 PM PDT 24
Finished Jul 29 08:03:02 PM PDT 24
Peak memory 575912 kb
Host smart-534496fa-9b2e-4dce-879a-fe08e1896df7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547776993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_dela
ys.547776993
Directory /workspace/74.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_same_source.1479435720
Short name T1509
Test name
Test status
Simulation time 785331159 ps
CPU time 24.71 seconds
Started Jul 29 08:02:20 PM PDT 24
Finished Jul 29 08:02:44 PM PDT 24
Peak memory 575796 kb
Host smart-5a8934ff-38a8-4f59-9b7c-f4815d07fd81
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479435720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.1479435720
Directory /workspace/74.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke.2217127903
Short name T1645
Test name
Test status
Simulation time 46492646 ps
CPU time 6.18 seconds
Started Jul 29 08:02:15 PM PDT 24
Finished Jul 29 08:02:22 PM PDT 24
Peak memory 573860 kb
Host smart-29d6e506-a014-4dc2-ad74-a1504a3e72f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217127903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.2217127903
Directory /workspace/74.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.928705596
Short name T1414
Test name
Test status
Simulation time 6643785953 ps
CPU time 73.18 seconds
Started Jul 29 08:02:15 PM PDT 24
Finished Jul 29 08:03:28 PM PDT 24
Peak memory 573992 kb
Host smart-7d606412-eeec-435b-9133-9c6f08ea0240
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928705596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.928705596
Directory /workspace/74.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.76175330
Short name T1664
Test name
Test status
Simulation time 6511358088 ps
CPU time 111.8 seconds
Started Jul 29 08:02:21 PM PDT 24
Finished Jul 29 08:04:13 PM PDT 24
Peak memory 573992 kb
Host smart-32472c11-a3d8-47ec-8e79-d58a4712e4c3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76175330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.76175330
Directory /workspace/74.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.3869482043
Short name T2566
Test name
Test status
Simulation time 59597284 ps
CPU time 6.88 seconds
Started Jul 29 08:02:16 PM PDT 24
Finished Jul 29 08:02:23 PM PDT 24
Peak memory 573804 kb
Host smart-090df80d-5f7c-4182-b648-0edc665d9948
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869482043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay
s.3869482043
Directory /workspace/74.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all.2660584127
Short name T636
Test name
Test status
Simulation time 7514619266 ps
CPU time 306.92 seconds
Started Jul 29 08:02:17 PM PDT 24
Finished Jul 29 08:07:24 PM PDT 24
Peak memory 576696 kb
Host smart-31f586f3-a6e1-4ddb-a76d-fbc0dd3e2193
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660584127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.2660584127
Directory /workspace/74.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.1253068765
Short name T538
Test name
Test status
Simulation time 13088235187 ps
CPU time 457.35 seconds
Started Jul 29 08:02:23 PM PDT 24
Finished Jul 29 08:10:01 PM PDT 24
Peak memory 576232 kb
Host smart-f32d6a41-60fa-49e5-90c9-b4ed631c0c47
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253068765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.1253068765
Directory /workspace/74.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.1245161939
Short name T2802
Test name
Test status
Simulation time 847847741 ps
CPU time 262.4 seconds
Started Jul 29 08:02:20 PM PDT 24
Finished Jul 29 08:06:42 PM PDT 24
Peak memory 576792 kb
Host smart-6a7add3a-1c7f-4d61-96cc-7a751cb578fb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245161939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all
_with_rand_reset.1245161939
Directory /workspace/74.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3608582648
Short name T896
Test name
Test status
Simulation time 439443741 ps
CPU time 109.95 seconds
Started Jul 29 08:02:23 PM PDT 24
Finished Jul 29 08:04:13 PM PDT 24
Peak memory 575980 kb
Host smart-4521937f-edc8-439e-8e12-b74d93c0c264
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608582648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al
l_with_reset_error.3608582648
Directory /workspace/74.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.3096352128
Short name T2649
Test name
Test status
Simulation time 36561578 ps
CPU time 6.69 seconds
Started Jul 29 08:02:21 PM PDT 24
Finished Jul 29 08:02:28 PM PDT 24
Peak memory 573944 kb
Host smart-4b535e22-1a3e-4a83-9cc4-ac2e49ab120f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096352128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.3096352128
Directory /workspace/74.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_access_same_device.2210348975
Short name T1665
Test name
Test status
Simulation time 544761567 ps
CPU time 39.25 seconds
Started Jul 29 08:02:31 PM PDT 24
Finished Jul 29 08:03:10 PM PDT 24
Peak memory 575856 kb
Host smart-c01686c0-f659-4cf3-a607-22283eccdb02
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210348975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device
.2210348975
Directory /workspace/75.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1993897273
Short name T2037
Test name
Test status
Simulation time 80064944048 ps
CPU time 1435.46 seconds
Started Jul 29 08:02:31 PM PDT 24
Finished Jul 29 08:26:27 PM PDT 24
Peak memory 576148 kb
Host smart-d5fdb2ea-b0fe-43e0-93a2-705161b4029e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993897273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_
device_slow_rsp.1993897273
Directory /workspace/75.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.2493381498
Short name T2093
Test name
Test status
Simulation time 316180573 ps
CPU time 32.8 seconds
Started Jul 29 08:02:42 PM PDT 24
Finished Jul 29 08:03:15 PM PDT 24
Peak memory 576020 kb
Host smart-db550892-0d05-4311-91d3-7c1b9fe23986
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493381498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add
r.2493381498
Directory /workspace/75.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_error_random.2269875116
Short name T556
Test name
Test status
Simulation time 636301447 ps
CPU time 48.75 seconds
Started Jul 29 08:02:38 PM PDT 24
Finished Jul 29 08:03:27 PM PDT 24
Peak memory 575952 kb
Host smart-13469d78-b97f-4c4d-a8ca-8d858f1e99ea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269875116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.2269875116
Directory /workspace/75.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random.2210471147
Short name T2321
Test name
Test status
Simulation time 431073061 ps
CPU time 16.16 seconds
Started Jul 29 08:02:29 PM PDT 24
Finished Jul 29 08:02:45 PM PDT 24
Peak memory 575812 kb
Host smart-07eaa789-a2e7-4d00-9797-51e70a4493a8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210471147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.2210471147
Directory /workspace/75.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.760751343
Short name T664
Test name
Test status
Simulation time 34776926897 ps
CPU time 364.11 seconds
Started Jul 29 08:02:29 PM PDT 24
Finished Jul 29 08:08:34 PM PDT 24
Peak memory 576088 kb
Host smart-e010e2bd-1ae8-4f1e-98a8-8cdc1c85b980
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760751343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.760751343
Directory /workspace/75.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.2471941707
Short name T1623
Test name
Test status
Simulation time 6446926248 ps
CPU time 110.76 seconds
Started Jul 29 08:02:29 PM PDT 24
Finished Jul 29 08:04:20 PM PDT 24
Peak memory 575960 kb
Host smart-668b1eca-76bf-4259-a311-4764ac690281
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471941707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.2471941707
Directory /workspace/75.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.3613769841
Short name T2192
Test name
Test status
Simulation time 501742412 ps
CPU time 41.83 seconds
Started Jul 29 08:02:29 PM PDT 24
Finished Jul 29 08:03:11 PM PDT 24
Peak memory 575604 kb
Host smart-46c39ef0-31de-4ce5-8ecf-9c0f514480cd
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613769841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del
ays.3613769841
Directory /workspace/75.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_same_source.3388499884
Short name T1679
Test name
Test status
Simulation time 73989208 ps
CPU time 8.51 seconds
Started Jul 29 08:02:41 PM PDT 24
Finished Jul 29 08:02:50 PM PDT 24
Peak memory 575836 kb
Host smart-c41ea819-0428-448e-94c0-ba92620fbc5d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388499884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.3388499884
Directory /workspace/75.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke.1189668621
Short name T1948
Test name
Test status
Simulation time 45694762 ps
CPU time 5.75 seconds
Started Jul 29 08:02:29 PM PDT 24
Finished Jul 29 08:02:35 PM PDT 24
Peak memory 574524 kb
Host smart-c77f5f16-415c-4411-9241-d7446e7f44a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189668621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.1189668621
Directory /workspace/75.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.3074993284
Short name T2774
Test name
Test status
Simulation time 6732090702 ps
CPU time 74.36 seconds
Started Jul 29 08:02:28 PM PDT 24
Finished Jul 29 08:03:42 PM PDT 24
Peak memory 574636 kb
Host smart-536dbf9c-9833-42f2-89d9-064eae64f32e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074993284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.3074993284
Directory /workspace/75.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.1814887228
Short name T1667
Test name
Test status
Simulation time 5192665668 ps
CPU time 82.85 seconds
Started Jul 29 08:02:29 PM PDT 24
Finished Jul 29 08:03:52 PM PDT 24
Peak memory 574732 kb
Host smart-24ec207e-bc70-4a85-9293-be39cd7ba382
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814887228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.1814887228
Directory /workspace/75.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2457268096
Short name T1398
Test name
Test status
Simulation time 45889150 ps
CPU time 6.14 seconds
Started Jul 29 08:02:27 PM PDT 24
Finished Jul 29 08:02:34 PM PDT 24
Peak memory 573788 kb
Host smart-48b88d74-7494-48c5-b1e0-33bc51969111
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457268096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay
s.2457268096
Directory /workspace/75.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all.3760072332
Short name T2151
Test name
Test status
Simulation time 6186416688 ps
CPU time 216.85 seconds
Started Jul 29 08:02:37 PM PDT 24
Finished Jul 29 08:06:14 PM PDT 24
Peak memory 576104 kb
Host smart-c200b971-a3bb-488d-93af-adaaabaa7396
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760072332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.3760072332
Directory /workspace/75.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.4101300218
Short name T542
Test name
Test status
Simulation time 735211427 ps
CPU time 64.19 seconds
Started Jul 29 08:02:39 PM PDT 24
Finished Jul 29 08:03:44 PM PDT 24
Peak memory 576084 kb
Host smart-37ec27e5-fd08-473b-94d0-cddbe722665b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101300218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.4101300218
Directory /workspace/75.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.2530478808
Short name T2611
Test name
Test status
Simulation time 19230818842 ps
CPU time 1020.03 seconds
Started Jul 29 08:02:38 PM PDT 24
Finished Jul 29 08:19:39 PM PDT 24
Peak memory 576732 kb
Host smart-98fcfbd9-7815-4e3f-8591-8717822d1bb9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530478808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all
_with_rand_reset.2530478808
Directory /workspace/75.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.2022331441
Short name T2183
Test name
Test status
Simulation time 2321138614 ps
CPU time 265.83 seconds
Started Jul 29 08:02:48 PM PDT 24
Finished Jul 29 08:07:14 PM PDT 24
Peak memory 576044 kb
Host smart-9ed21754-8b91-48ce-b3fb-71250965061a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022331441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al
l_with_reset_error.2022331441
Directory /workspace/75.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.2944044918
Short name T2700
Test name
Test status
Simulation time 81238948 ps
CPU time 11.65 seconds
Started Jul 29 08:02:37 PM PDT 24
Finished Jul 29 08:02:49 PM PDT 24
Peak memory 576012 kb
Host smart-597640ae-dc86-48e2-9570-a94bfdb86843
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944044918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.2944044918
Directory /workspace/75.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_access_same_device.4242080662
Short name T2811
Test name
Test status
Simulation time 1082317551 ps
CPU time 71.91 seconds
Started Jul 29 08:02:39 PM PDT 24
Finished Jul 29 08:03:51 PM PDT 24
Peak memory 575844 kb
Host smart-2a8b367e-1a90-4852-8bd8-ecdb65f8ec07
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242080662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device
.4242080662
Directory /workspace/76.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3101842547
Short name T2763
Test name
Test status
Simulation time 24543624462 ps
CPU time 415.98 seconds
Started Jul 29 08:02:47 PM PDT 24
Finished Jul 29 08:09:43 PM PDT 24
Peak memory 576124 kb
Host smart-334e1251-3bae-490f-aa90-59d1b4a53f97
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101842547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_
device_slow_rsp.3101842547
Directory /workspace/76.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.106173807
Short name T1466
Test name
Test status
Simulation time 490758368 ps
CPU time 19.88 seconds
Started Jul 29 08:02:47 PM PDT 24
Finished Jul 29 08:03:07 PM PDT 24
Peak memory 576000 kb
Host smart-cbb0c57f-e78b-475a-9e5e-8ae1e4db1827
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106173807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_addr
.106173807
Directory /workspace/76.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_error_random.3525951137
Short name T1890
Test name
Test status
Simulation time 589469038 ps
CPU time 43.23 seconds
Started Jul 29 08:02:48 PM PDT 24
Finished Jul 29 08:03:32 PM PDT 24
Peak memory 575856 kb
Host smart-8f7818c0-8982-4371-8c87-41dc01b869d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525951137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.3525951137
Directory /workspace/76.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random.93037270
Short name T1559
Test name
Test status
Simulation time 505499918 ps
CPU time 46.83 seconds
Started Jul 29 08:02:47 PM PDT 24
Finished Jul 29 08:03:34 PM PDT 24
Peak memory 576048 kb
Host smart-728bc5b3-8982-4ceb-9455-44e2567096d7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93037270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.93037270
Directory /workspace/76.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.1652822645
Short name T2044
Test name
Test status
Simulation time 89094312285 ps
CPU time 967.78 seconds
Started Jul 29 08:02:39 PM PDT 24
Finished Jul 29 08:18:47 PM PDT 24
Peak memory 576096 kb
Host smart-a2ed6ccb-e206-4b41-af39-0d34d4ab3f24
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652822645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.1652822645
Directory /workspace/76.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.559392091
Short name T580
Test name
Test status
Simulation time 44310911944 ps
CPU time 832.76 seconds
Started Jul 29 08:02:41 PM PDT 24
Finished Jul 29 08:16:34 PM PDT 24
Peak memory 575924 kb
Host smart-0b266f3a-dbe1-41e4-ab8f-8537bd93184a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559392091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.559392091
Directory /workspace/76.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.1958020113
Short name T1879
Test name
Test status
Simulation time 534438317 ps
CPU time 44.74 seconds
Started Jul 29 08:02:40 PM PDT 24
Finished Jul 29 08:03:25 PM PDT 24
Peak memory 575948 kb
Host smart-207cda22-d658-4597-adbc-61e9fb8f00eb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958020113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del
ays.1958020113
Directory /workspace/76.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_same_source.3106809259
Short name T2624
Test name
Test status
Simulation time 1150234502 ps
CPU time 34.67 seconds
Started Jul 29 08:02:50 PM PDT 24
Finished Jul 29 08:03:25 PM PDT 24
Peak memory 575892 kb
Host smart-71f018be-34bc-4792-a214-4af88f592bd6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106809259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.3106809259
Directory /workspace/76.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke.2864024957
Short name T2371
Test name
Test status
Simulation time 47769198 ps
CPU time 6.56 seconds
Started Jul 29 08:02:38 PM PDT 24
Finished Jul 29 08:02:44 PM PDT 24
Peak memory 573992 kb
Host smart-d7d0517b-fe4b-4602-a61d-9bbab6204b55
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864024957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.2864024957
Directory /workspace/76.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.740544765
Short name T621
Test name
Test status
Simulation time 7511482237 ps
CPU time 75.88 seconds
Started Jul 29 08:02:43 PM PDT 24
Finished Jul 29 08:03:59 PM PDT 24
Peak memory 573968 kb
Host smart-126c0398-baa5-4516-a43e-95ae3cbabf0e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740544765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.740544765
Directory /workspace/76.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.4214893229
Short name T1682
Test name
Test status
Simulation time 6171608160 ps
CPU time 96.45 seconds
Started Jul 29 08:02:41 PM PDT 24
Finished Jul 29 08:04:18 PM PDT 24
Peak memory 573924 kb
Host smart-4d5e472c-951c-401e-87cd-99f62e981abb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214893229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.4214893229
Directory /workspace/76.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.597360628
Short name T2663
Test name
Test status
Simulation time 42524587 ps
CPU time 6.22 seconds
Started Jul 29 08:02:47 PM PDT 24
Finished Jul 29 08:02:53 PM PDT 24
Peak memory 573892 kb
Host smart-9f538930-0433-4302-b667-4d4d3b10cf80
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597360628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays
.597360628
Directory /workspace/76.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all.829706568
Short name T2217
Test name
Test status
Simulation time 3527386739 ps
CPU time 283.05 seconds
Started Jul 29 08:02:47 PM PDT 24
Finished Jul 29 08:07:30 PM PDT 24
Peak memory 576024 kb
Host smart-a251dab3-3314-4557-91af-6098d1e8004e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829706568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.829706568
Directory /workspace/76.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.2244534313
Short name T1762
Test name
Test status
Simulation time 550099805 ps
CPU time 18.85 seconds
Started Jul 29 08:02:50 PM PDT 24
Finished Jul 29 08:03:09 PM PDT 24
Peak memory 575780 kb
Host smart-93983c8e-a59b-4349-a97f-457d426fa65f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244534313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.2244534313
Directory /workspace/76.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.4176164547
Short name T2337
Test name
Test status
Simulation time 3246064351 ps
CPU time 604.29 seconds
Started Jul 29 08:02:56 PM PDT 24
Finished Jul 29 08:13:00 PM PDT 24
Peak memory 576828 kb
Host smart-7f771f3a-c846-43a2-9f52-c0ce9d7a4f08
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176164547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all
_with_rand_reset.4176164547
Directory /workspace/76.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.4165973644
Short name T2286
Test name
Test status
Simulation time 311193997 ps
CPU time 92.61 seconds
Started Jul 29 08:02:48 PM PDT 24
Finished Jul 29 08:04:20 PM PDT 24
Peak memory 576808 kb
Host smart-97de5bd1-f2da-4310-bf8f-6b1d94568968
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165973644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al
l_with_reset_error.4165973644
Directory /workspace/76.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.1745815239
Short name T1611
Test name
Test status
Simulation time 1169741048 ps
CPU time 44.38 seconds
Started Jul 29 08:02:46 PM PDT 24
Finished Jul 29 08:03:31 PM PDT 24
Peak memory 575916 kb
Host smart-3c86bb34-6611-43f4-8d9c-11a408e98cf0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745815239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.1745815239
Directory /workspace/76.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_access_same_device.2373442509
Short name T578
Test name
Test status
Simulation time 428572577 ps
CPU time 15.68 seconds
Started Jul 29 08:03:02 PM PDT 24
Finished Jul 29 08:03:18 PM PDT 24
Peak memory 575776 kb
Host smart-fb41ed46-bebd-4d0d-8c25-d630e3ce3eed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373442509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device
.2373442509
Directory /workspace/77.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.268133297
Short name T2445
Test name
Test status
Simulation time 124290113323 ps
CPU time 2192.23 seconds
Started Jul 29 08:02:56 PM PDT 24
Finished Jul 29 08:39:29 PM PDT 24
Peak memory 576112 kb
Host smart-a4a6e6b3-b368-44ad-9247-8072194f8b30
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268133297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_d
evice_slow_rsp.268133297
Directory /workspace/77.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.1706316411
Short name T2515
Test name
Test status
Simulation time 65278392 ps
CPU time 6.18 seconds
Started Jul 29 08:02:53 PM PDT 24
Finished Jul 29 08:03:00 PM PDT 24
Peak memory 574524 kb
Host smart-0b6cd7f1-836f-402b-a402-7bc9c6c9d360
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706316411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add
r.1706316411
Directory /workspace/77.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_error_random.1604557411
Short name T1835
Test name
Test status
Simulation time 202474694 ps
CPU time 10.02 seconds
Started Jul 29 08:02:53 PM PDT 24
Finished Jul 29 08:03:03 PM PDT 24
Peak memory 574464 kb
Host smart-f43ef761-b65a-482c-82a5-5e650d0e5e83
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604557411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.1604557411
Directory /workspace/77.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random.3570744704
Short name T1545
Test name
Test status
Simulation time 189891081 ps
CPU time 17.44 seconds
Started Jul 29 08:02:47 PM PDT 24
Finished Jul 29 08:03:05 PM PDT 24
Peak memory 575992 kb
Host smart-70db797d-2db3-41af-8d64-964adb0194d3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570744704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.3570744704
Directory /workspace/77.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.1114053460
Short name T1886
Test name
Test status
Simulation time 30203532348 ps
CPU time 313.27 seconds
Started Jul 29 08:02:48 PM PDT 24
Finished Jul 29 08:08:02 PM PDT 24
Peak memory 575904 kb
Host smart-63309d14-1460-47be-bd73-406b70bc967f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114053460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.1114053460
Directory /workspace/77.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.1830170613
Short name T1592
Test name
Test status
Simulation time 13044690485 ps
CPU time 205.01 seconds
Started Jul 29 08:02:47 PM PDT 24
Finished Jul 29 08:06:12 PM PDT 24
Peak memory 575840 kb
Host smart-bf59e92d-911e-4124-920b-f75312f65803
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830170613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.1830170613
Directory /workspace/77.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.3494721404
Short name T562
Test name
Test status
Simulation time 600514561 ps
CPU time 49.2 seconds
Started Jul 29 08:02:48 PM PDT 24
Finished Jul 29 08:03:37 PM PDT 24
Peak memory 575880 kb
Host smart-7022cdea-c77d-41e2-8883-16af3144460e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494721404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del
ays.3494721404
Directory /workspace/77.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_same_source.2477232572
Short name T2262
Test name
Test status
Simulation time 1396732966 ps
CPU time 33.82 seconds
Started Jul 29 08:03:02 PM PDT 24
Finished Jul 29 08:03:36 PM PDT 24
Peak memory 575800 kb
Host smart-c5222cb9-e69c-44e0-9866-1075d1564f8b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477232572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.2477232572
Directory /workspace/77.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke.3884803877
Short name T1497
Test name
Test status
Simulation time 240769255 ps
CPU time 10.5 seconds
Started Jul 29 08:02:49 PM PDT 24
Finished Jul 29 08:02:59 PM PDT 24
Peak memory 573880 kb
Host smart-9093b5d1-ee12-42c1-95b9-9b0ec645ae48
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884803877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.3884803877
Directory /workspace/77.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.1801864839
Short name T2728
Test name
Test status
Simulation time 9642828950 ps
CPU time 106.59 seconds
Started Jul 29 08:02:50 PM PDT 24
Finished Jul 29 08:04:37 PM PDT 24
Peak memory 574600 kb
Host smart-bc4ca287-09ef-4606-b52f-32bf848f7014
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801864839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.1801864839
Directory /workspace/77.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1836183851
Short name T1902
Test name
Test status
Simulation time 4941298393 ps
CPU time 86.46 seconds
Started Jul 29 08:02:46 PM PDT 24
Finished Jul 29 08:04:13 PM PDT 24
Peak memory 574732 kb
Host smart-1d16b968-6086-4240-9c55-63bfe0c58759
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836183851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.1836183851
Directory /workspace/77.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.367104855
Short name T2315
Test name
Test status
Simulation time 40826728 ps
CPU time 6.02 seconds
Started Jul 29 08:02:50 PM PDT 24
Finished Jul 29 08:02:56 PM PDT 24
Peak memory 573784 kb
Host smart-f55b1620-ee85-4fa7-8861-e9aca7bc6dde
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367104855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delays
.367104855
Directory /workspace/77.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all.1224541648
Short name T1888
Test name
Test status
Simulation time 11460479995 ps
CPU time 378 seconds
Started Jul 29 08:02:57 PM PDT 24
Finished Jul 29 08:09:15 PM PDT 24
Peak memory 576820 kb
Host smart-ec5acb8f-73c5-42b6-85ba-f084312e6516
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224541648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.1224541648
Directory /workspace/77.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.611121394
Short name T1992
Test name
Test status
Simulation time 560731899 ps
CPU time 38.78 seconds
Started Jul 29 08:03:03 PM PDT 24
Finished Jul 29 08:03:42 PM PDT 24
Peak memory 575968 kb
Host smart-cdf9a871-c315-4987-a854-7a8650e842f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611121394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.611121394
Directory /workspace/77.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2477608685
Short name T2590
Test name
Test status
Simulation time 2764125296 ps
CPU time 220.32 seconds
Started Jul 29 08:02:54 PM PDT 24
Finished Jul 29 08:06:34 PM PDT 24
Peak memory 576036 kb
Host smart-0a726e93-9c32-4920-b68c-ef0e61a71270
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477608685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all
_with_rand_reset.2477608685
Directory /workspace/77.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.1175639006
Short name T2301
Test name
Test status
Simulation time 1615837317 ps
CPU time 222.07 seconds
Started Jul 29 08:02:55 PM PDT 24
Finished Jul 29 08:06:38 PM PDT 24
Peak memory 575908 kb
Host smart-b9477180-9a1d-4ee0-a37c-941ad61831df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175639006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al
l_with_reset_error.1175639006
Directory /workspace/77.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.970547289
Short name T2426
Test name
Test status
Simulation time 558658356 ps
CPU time 24.45 seconds
Started Jul 29 08:02:53 PM PDT 24
Finished Jul 29 08:03:18 PM PDT 24
Peak memory 575876 kb
Host smart-df5f6ed9-ea1b-4f5b-abff-dc7a55805454
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970547289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.970547289
Directory /workspace/77.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_access_same_device.966189628
Short name T1780
Test name
Test status
Simulation time 1614468433 ps
CPU time 68.27 seconds
Started Jul 29 08:03:09 PM PDT 24
Finished Jul 29 08:04:17 PM PDT 24
Peak memory 575948 kb
Host smart-0a267077-9535-4291-afd0-9cb41780f6ca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966189628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device.
966189628
Directory /workspace/78.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3126992621
Short name T2348
Test name
Test status
Simulation time 113917380490 ps
CPU time 1868.16 seconds
Started Jul 29 08:03:02 PM PDT 24
Finished Jul 29 08:34:11 PM PDT 24
Peak memory 576024 kb
Host smart-91af4f29-6c8b-4fe4-a430-36c5ad379078
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126992621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_
device_slow_rsp.3126992621
Directory /workspace/78.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.196920720
Short name T1661
Test name
Test status
Simulation time 92122041 ps
CPU time 11.81 seconds
Started Jul 29 08:03:09 PM PDT 24
Finished Jul 29 08:03:21 PM PDT 24
Peak memory 575760 kb
Host smart-5e21acb4-8b7e-4a67-8072-c532a4304b3b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196920720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_addr
.196920720
Directory /workspace/78.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_error_random.1716123984
Short name T1469
Test name
Test status
Simulation time 2207851476 ps
CPU time 78.54 seconds
Started Jul 29 08:03:02 PM PDT 24
Finished Jul 29 08:04:21 PM PDT 24
Peak memory 576136 kb
Host smart-da978d89-e741-46c7-ba86-709a709deab5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716123984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.1716123984
Directory /workspace/78.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random.3509792436
Short name T2659
Test name
Test status
Simulation time 2559062924 ps
CPU time 91.93 seconds
Started Jul 29 08:02:54 PM PDT 24
Finished Jul 29 08:04:26 PM PDT 24
Peak memory 576004 kb
Host smart-19066661-bc8e-4069-a2f6-8d54510c9bf5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509792436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.3509792436
Directory /workspace/78.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.4274913107
Short name T2687
Test name
Test status
Simulation time 44181342223 ps
CPU time 461.63 seconds
Started Jul 29 08:02:52 PM PDT 24
Finished Jul 29 08:10:34 PM PDT 24
Peak memory 575912 kb
Host smart-fbb14162-e93d-4b1e-8db4-b2a77a327de5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274913107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.4274913107
Directory /workspace/78.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.2416188312
Short name T587
Test name
Test status
Simulation time 51462387599 ps
CPU time 941.1 seconds
Started Jul 29 08:03:03 PM PDT 24
Finished Jul 29 08:18:44 PM PDT 24
Peak memory 576092 kb
Host smart-f60ef049-783f-4f90-852c-583d32c39b2d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416188312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.2416188312
Directory /workspace/78.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.1614164366
Short name T2883
Test name
Test status
Simulation time 85959764 ps
CPU time 9.87 seconds
Started Jul 29 08:02:53 PM PDT 24
Finished Jul 29 08:03:03 PM PDT 24
Peak memory 575944 kb
Host smart-b8d1ccc8-711c-4c42-96a0-b18c210c741e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614164366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del
ays.1614164366
Directory /workspace/78.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_same_source.3082642197
Short name T637
Test name
Test status
Simulation time 1136096671 ps
CPU time 35.17 seconds
Started Jul 29 08:03:05 PM PDT 24
Finished Jul 29 08:03:40 PM PDT 24
Peak memory 575908 kb
Host smart-580a3dd2-0240-40d6-a998-627700666627
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082642197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.3082642197
Directory /workspace/78.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke.2033037022
Short name T2464
Test name
Test status
Simulation time 220588296 ps
CPU time 8.36 seconds
Started Jul 29 08:02:53 PM PDT 24
Finished Jul 29 08:03:01 PM PDT 24
Peak memory 573864 kb
Host smart-4553ce80-16fe-4935-b579-302c2d1f60b0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033037022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.2033037022
Directory /workspace/78.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.683861933
Short name T2395
Test name
Test status
Simulation time 7810970404 ps
CPU time 79.21 seconds
Started Jul 29 08:02:54 PM PDT 24
Finished Jul 29 08:04:13 PM PDT 24
Peak memory 574012 kb
Host smart-3efacb0c-458a-402d-9ba2-cb93e243bd48
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683861933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.683861933
Directory /workspace/78.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.1597020611
Short name T1932
Test name
Test status
Simulation time 6353759440 ps
CPU time 109.69 seconds
Started Jul 29 08:02:52 PM PDT 24
Finished Jul 29 08:04:42 PM PDT 24
Peak memory 573896 kb
Host smart-d24ebd01-1c0e-4596-bc98-6bc61db99618
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597020611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.1597020611
Directory /workspace/78.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.87857194
Short name T2473
Test name
Test status
Simulation time 48601218 ps
CPU time 6.2 seconds
Started Jul 29 08:02:55 PM PDT 24
Finished Jul 29 08:03:01 PM PDT 24
Peak memory 574536 kb
Host smart-e37e7f75-5d51-44ca-b446-9e1d8f46ffab
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87857194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delays.87857194
Directory /workspace/78.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all.2917372853
Short name T608
Test name
Test status
Simulation time 3894919509 ps
CPU time 300.59 seconds
Started Jul 29 08:03:02 PM PDT 24
Finished Jul 29 08:08:02 PM PDT 24
Peak memory 575968 kb
Host smart-e98895e0-e6d9-4894-af09-a4b1189fa9f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917372853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.2917372853
Directory /workspace/78.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.1299552806
Short name T2827
Test name
Test status
Simulation time 2358576844 ps
CPU time 154.72 seconds
Started Jul 29 08:03:02 PM PDT 24
Finished Jul 29 08:05:36 PM PDT 24
Peak memory 575960 kb
Host smart-350f6f8c-cfab-4d3a-9640-68ed64773c18
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299552806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.1299552806
Directory /workspace/78.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.1005859016
Short name T2831
Test name
Test status
Simulation time 3870092303 ps
CPU time 608.77 seconds
Started Jul 29 08:03:03 PM PDT 24
Finished Jul 29 08:13:12 PM PDT 24
Peak memory 576080 kb
Host smart-d937937b-0d92-4762-8579-202b88ea09c8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005859016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all
_with_rand_reset.1005859016
Directory /workspace/78.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.706730493
Short name T1704
Test name
Test status
Simulation time 79282076 ps
CPU time 12.86 seconds
Started Jul 29 08:03:03 PM PDT 24
Finished Jul 29 08:03:16 PM PDT 24
Peak memory 575928 kb
Host smart-1a55a103-7fce-4f94-978b-005852ec1947
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706730493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all
_with_reset_error.706730493
Directory /workspace/78.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.553211096
Short name T469
Test name
Test status
Simulation time 169438346 ps
CPU time 19.11 seconds
Started Jul 29 08:03:05 PM PDT 24
Finished Jul 29 08:03:24 PM PDT 24
Peak memory 576048 kb
Host smart-bbcead5c-2162-4ee2-bf93-3fbcaac96856
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553211096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.553211096
Directory /workspace/78.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_access_same_device.3885812222
Short name T497
Test name
Test status
Simulation time 2106532533 ps
CPU time 79.57 seconds
Started Jul 29 08:03:09 PM PDT 24
Finished Jul 29 08:04:29 PM PDT 24
Peak memory 576016 kb
Host smart-b9080199-770e-4947-b90b-5c0e6fb0ced1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885812222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device
.3885812222
Directory /workspace/79.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3763715896
Short name T2029
Test name
Test status
Simulation time 81429226 ps
CPU time 11.82 seconds
Started Jul 29 08:03:12 PM PDT 24
Finished Jul 29 08:03:24 PM PDT 24
Peak memory 575792 kb
Host smart-15d8ac7d-5318-4df5-9318-2900b1c7e449
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763715896 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add
r.3763715896
Directory /workspace/79.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_error_random.417602847
Short name T2251
Test name
Test status
Simulation time 373468914 ps
CPU time 28.08 seconds
Started Jul 29 08:03:10 PM PDT 24
Finished Jul 29 08:03:39 PM PDT 24
Peak memory 575968 kb
Host smart-01b2c650-c73d-46e2-b7ef-b8f9ea68f1da
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417602847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.417602847
Directory /workspace/79.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random.3681082485
Short name T2862
Test name
Test status
Simulation time 1537196717 ps
CPU time 59.41 seconds
Started Jul 29 08:03:09 PM PDT 24
Finished Jul 29 08:04:08 PM PDT 24
Peak memory 576040 kb
Host smart-db85929d-2b65-4589-9383-5d95bc300408
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681082485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.3681082485
Directory /workspace/79.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.3534150744
Short name T2600
Test name
Test status
Simulation time 107661236077 ps
CPU time 1184.35 seconds
Started Jul 29 08:03:10 PM PDT 24
Finished Jul 29 08:22:55 PM PDT 24
Peak memory 575920 kb
Host smart-fda4c66a-8814-492e-b76e-838719422f42
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534150744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.3534150744
Directory /workspace/79.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.94712620
Short name T2455
Test name
Test status
Simulation time 59594575192 ps
CPU time 1049.97 seconds
Started Jul 29 08:03:10 PM PDT 24
Finished Jul 29 08:20:41 PM PDT 24
Peak memory 576100 kb
Host smart-8b934f9a-79e0-4f67-8fa8-ba9049eaefc3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94712620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.94712620
Directory /workspace/79.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.23077814
Short name T1575
Test name
Test status
Simulation time 75601369 ps
CPU time 8.88 seconds
Started Jul 29 08:03:11 PM PDT 24
Finished Jul 29 08:03:20 PM PDT 24
Peak memory 575792 kb
Host smart-e69768bc-779d-453e-8167-7ad5e53b54e8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23077814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_delay
s.23077814
Directory /workspace/79.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_same_source.2714966313
Short name T1944
Test name
Test status
Simulation time 596985763 ps
CPU time 17.74 seconds
Started Jul 29 08:03:15 PM PDT 24
Finished Jul 29 08:03:32 PM PDT 24
Peak memory 575864 kb
Host smart-f00706d6-3a7b-447d-a1b7-40c9c95754a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714966313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.2714966313
Directory /workspace/79.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke.3076513264
Short name T677
Test name
Test status
Simulation time 213789549 ps
CPU time 8.35 seconds
Started Jul 29 08:03:02 PM PDT 24
Finished Jul 29 08:03:11 PM PDT 24
Peak memory 574576 kb
Host smart-df6e4301-24c8-40e1-9ad0-3dc4973d9010
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076513264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.3076513264
Directory /workspace/79.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.306609231
Short name T2550
Test name
Test status
Simulation time 9000068552 ps
CPU time 92.19 seconds
Started Jul 29 08:03:02 PM PDT 24
Finished Jul 29 08:04:34 PM PDT 24
Peak memory 574008 kb
Host smart-14f02097-2a5b-4bdc-967f-d1611b7c82dc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306609231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.306609231
Directory /workspace/79.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.419704401
Short name T2760
Test name
Test status
Simulation time 4137762314 ps
CPU time 73.62 seconds
Started Jul 29 08:03:01 PM PDT 24
Finished Jul 29 08:04:15 PM PDT 24
Peak memory 574596 kb
Host smart-c0a98686-cf32-4ccf-ad6f-9fc97fee1c7b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419704401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.419704401
Directory /workspace/79.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.555315802
Short name T1730
Test name
Test status
Simulation time 40184693 ps
CPU time 6.56 seconds
Started Jul 29 08:03:02 PM PDT 24
Finished Jul 29 08:03:08 PM PDT 24
Peak memory 573884 kb
Host smart-c54b98bc-d014-481e-895d-d1637e50bde9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555315802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delays
.555315802
Directory /workspace/79.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all.3046998475
Short name T2875
Test name
Test status
Simulation time 579429890 ps
CPU time 48.32 seconds
Started Jul 29 08:03:10 PM PDT 24
Finished Jul 29 08:03:58 PM PDT 24
Peak memory 575884 kb
Host smart-462b950d-95d7-456d-9c13-b74c44d3c4eb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046998475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.3046998475
Directory /workspace/79.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.1900537057
Short name T1723
Test name
Test status
Simulation time 406245610 ps
CPU time 36.7 seconds
Started Jul 29 08:03:12 PM PDT 24
Finished Jul 29 08:03:49 PM PDT 24
Peak memory 576088 kb
Host smart-225e2894-1642-40bc-870c-df51f7c39b59
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900537057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.1900537057
Directory /workspace/79.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.4278668624
Short name T2236
Test name
Test status
Simulation time 202082355 ps
CPU time 53.93 seconds
Started Jul 29 08:03:11 PM PDT 24
Finished Jul 29 08:04:05 PM PDT 24
Peak memory 576760 kb
Host smart-b6535980-b706-4461-ba6f-4f746de8f505
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278668624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al
l_with_reset_error.4278668624
Directory /workspace/79.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.3114919934
Short name T1806
Test name
Test status
Simulation time 40617304 ps
CPU time 7.88 seconds
Started Jul 29 08:03:10 PM PDT 24
Finished Jul 29 08:03:18 PM PDT 24
Peak memory 573988 kb
Host smart-2d83aa33-e51d-4195-83eb-6ea261a033f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114919934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.3114919934
Directory /workspace/79.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/8.chip_csr_rw.338017378
Short name T2342
Test name
Test status
Simulation time 4810466288 ps
CPU time 464.25 seconds
Started Jul 29 07:50:21 PM PDT 24
Finished Jul 29 07:58:05 PM PDT 24
Peak memory 597632 kb
Host smart-f5455f78-0909-4681-91cb-299b6734d0c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338017378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.338017378
Directory /workspace/8.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.2708861234
Short name T397
Test name
Test status
Simulation time 15741966009 ps
CPU time 2317.02 seconds
Started Jul 29 07:50:25 PM PDT 24
Finished Jul 29 08:29:02 PM PDT 24
Peak memory 593312 kb
Host smart-2ddc1425-df7e-4a09-a6a6-f336d5854610
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708861234 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.2708861234
Directory /workspace/8.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_access_same_device.4038259898
Short name T2867
Test name
Test status
Simulation time 3089790707 ps
CPU time 130.36 seconds
Started Jul 29 07:50:09 PM PDT 24
Finished Jul 29 07:52:19 PM PDT 24
Peak memory 576256 kb
Host smart-f11a9e69-24f2-494c-b603-6e24b2bb0ede
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038259898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.
4038259898
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.3797250452
Short name T2565
Test name
Test status
Simulation time 85388450116 ps
CPU time 1319.26 seconds
Started Jul 29 07:50:14 PM PDT 24
Finished Jul 29 08:12:14 PM PDT 24
Peak memory 576040 kb
Host smart-7760a6dd-4101-49aa-ab19-8b84cbb1e147
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797250452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d
evice_slow_rsp.3797250452
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.4072689535
Short name T549
Test name
Test status
Simulation time 218762670 ps
CPU time 23.95 seconds
Started Jul 29 07:50:25 PM PDT 24
Finished Jul 29 07:50:49 PM PDT 24
Peak memory 575956 kb
Host smart-6938adbc-b90e-49b4-8d1d-f1aa3abec329
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072689535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr
.4072689535
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_error_random.2228834932
Short name T2762
Test name
Test status
Simulation time 1987796885 ps
CPU time 57.17 seconds
Started Jul 29 07:50:20 PM PDT 24
Finished Jul 29 07:51:17 PM PDT 24
Peak memory 575904 kb
Host smart-a636e543-74e4-42e7-b1de-7f55ef810866
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228834932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2228834932
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random.3007382961
Short name T494
Test name
Test status
Simulation time 2171210443 ps
CPU time 70.62 seconds
Started Jul 29 07:50:28 PM PDT 24
Finished Jul 29 07:51:39 PM PDT 24
Peak memory 576084 kb
Host smart-685179f3-2079-4fed-9e91-11021c1cd5c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007382961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.3007382961
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.3534208714
Short name T2309
Test name
Test status
Simulation time 19141299664 ps
CPU time 205.7 seconds
Started Jul 29 07:50:20 PM PDT 24
Finished Jul 29 07:53:46 PM PDT 24
Peak memory 576056 kb
Host smart-a4019a32-6fc5-485f-a2cb-cf21de7c3314
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534208714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3534208714
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.3360315777
Short name T1652
Test name
Test status
Simulation time 61510358209 ps
CPU time 1009.77 seconds
Started Jul 29 07:50:17 PM PDT 24
Finished Jul 29 08:07:07 PM PDT 24
Peak memory 576000 kb
Host smart-3ff9de06-7453-4f0a-93be-546519979855
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360315777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3360315777
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.3425327450
Short name T2577
Test name
Test status
Simulation time 591586728 ps
CPU time 50.84 seconds
Started Jul 29 07:50:08 PM PDT 24
Finished Jul 29 07:50:59 PM PDT 24
Peak memory 575948 kb
Host smart-725664c3-3d3f-4b07-ac56-b2976354f141
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425327450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela
ys.3425327450
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_same_source.555682022
Short name T1604
Test name
Test status
Simulation time 467797841 ps
CPU time 15.02 seconds
Started Jul 29 07:50:13 PM PDT 24
Finished Jul 29 07:50:28 PM PDT 24
Peak memory 575948 kb
Host smart-f982eae1-13a9-41ad-b46f-c37e030acf7b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555682022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.555682022
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke.2050179701
Short name T1425
Test name
Test status
Simulation time 45197847 ps
CPU time 6.32 seconds
Started Jul 29 07:50:20 PM PDT 24
Finished Jul 29 07:50:26 PM PDT 24
Peak memory 573972 kb
Host smart-84043334-2146-4de2-8197-422a08490e91
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050179701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2050179701
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.2102302533
Short name T1960
Test name
Test status
Simulation time 6571837828 ps
CPU time 68.88 seconds
Started Jul 29 07:50:21 PM PDT 24
Finished Jul 29 07:51:30 PM PDT 24
Peak memory 573928 kb
Host smart-ba733490-ed7e-46b9-9028-ca9c0f3e6cc7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102302533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2102302533
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.563413762
Short name T1447
Test name
Test status
Simulation time 5627488236 ps
CPU time 89.55 seconds
Started Jul 29 07:50:17 PM PDT 24
Finished Jul 29 07:51:47 PM PDT 24
Peak memory 573884 kb
Host smart-2e0ea799-288b-4e48-9dae-7ae0136b420a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563413762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.563413762
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.1793430806
Short name T2769
Test name
Test status
Simulation time 54335313 ps
CPU time 6.47 seconds
Started Jul 29 07:50:15 PM PDT 24
Finished Jul 29 07:50:22 PM PDT 24
Peak memory 574440 kb
Host smart-1016f88e-bd24-4774-8d04-11d59604e39e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793430806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays
.1793430806
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all.2858647629
Short name T2805
Test name
Test status
Simulation time 5890080482 ps
CPU time 221.86 seconds
Started Jul 29 07:50:13 PM PDT 24
Finished Jul 29 07:53:55 PM PDT 24
Peak memory 576172 kb
Host smart-0b95749f-8efa-4886-916f-fdd8b266ed1a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858647629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2858647629
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.3068835041
Short name T1435
Test name
Test status
Simulation time 811448155 ps
CPU time 57.97 seconds
Started Jul 29 07:50:28 PM PDT 24
Finished Jul 29 07:51:26 PM PDT 24
Peak memory 576084 kb
Host smart-464c4175-1b97-43bc-a333-2eedd0fb7fc2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068835041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3068835041
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1598251695
Short name T880
Test name
Test status
Simulation time 1999120925 ps
CPU time 202 seconds
Started Jul 29 07:50:12 PM PDT 24
Finished Jul 29 07:53:34 PM PDT 24
Peak memory 576788 kb
Host smart-44e7b1df-f373-4b5a-b120-f9c76323d2be
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598251695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_
with_rand_reset.1598251695
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.2083464055
Short name T1445
Test name
Test status
Simulation time 7965550359 ps
CPU time 373.97 seconds
Started Jul 29 07:50:19 PM PDT 24
Finished Jul 29 07:56:33 PM PDT 24
Peak memory 576740 kb
Host smart-7b84b9bf-a694-4f48-b5b1-77f66f78beed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083464055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all
_with_reset_error.2083464055
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.2466994133
Short name T2801
Test name
Test status
Simulation time 64772825 ps
CPU time 9.31 seconds
Started Jul 29 07:50:21 PM PDT 24
Finished Jul 29 07:50:31 PM PDT 24
Peak memory 575848 kb
Host smart-3fcaabb3-3457-45a9-bf15-4a283153536d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466994133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2466994133
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_access_same_device.4060828060
Short name T1676
Test name
Test status
Simulation time 198436740 ps
CPU time 18.6 seconds
Started Jul 29 08:03:15 PM PDT 24
Finished Jul 29 08:03:33 PM PDT 24
Peak memory 575932 kb
Host smart-076d8f31-719e-454d-8fe7-28f551fa71d4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060828060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device
.4060828060
Directory /workspace/80.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.579221185
Short name T2851
Test name
Test status
Simulation time 132797493102 ps
CPU time 2297.93 seconds
Started Jul 29 08:03:18 PM PDT 24
Finished Jul 29 08:41:36 PM PDT 24
Peak memory 576168 kb
Host smart-996f6e32-a01e-4c5b-8b95-f26e5fa19852
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579221185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_d
evice_slow_rsp.579221185
Directory /workspace/80.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.951648848
Short name T1578
Test name
Test status
Simulation time 1091307920 ps
CPU time 41.31 seconds
Started Jul 29 08:03:24 PM PDT 24
Finished Jul 29 08:04:05 PM PDT 24
Peak memory 575720 kb
Host smart-5624af43-2218-4a53-a042-88592ecf6447
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951648848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_addr
.951648848
Directory /workspace/80.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_error_random.829266721
Short name T2378
Test name
Test status
Simulation time 106704326 ps
CPU time 6.79 seconds
Started Jul 29 08:03:17 PM PDT 24
Finished Jul 29 08:03:24 PM PDT 24
Peak memory 574468 kb
Host smart-3b6fb7c1-b06f-4f76-bf5e-3eb60ac20de0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829266721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.829266721
Directory /workspace/80.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random.3566527335
Short name T2172
Test name
Test status
Simulation time 180989891 ps
CPU time 16.32 seconds
Started Jul 29 08:03:18 PM PDT 24
Finished Jul 29 08:03:35 PM PDT 24
Peak memory 575972 kb
Host smart-9b0eaf78-4e39-4208-aa39-80805466bb00
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566527335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.3566527335
Directory /workspace/80.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.2524528329
Short name T681
Test name
Test status
Simulation time 13266910111 ps
CPU time 137.33 seconds
Started Jul 29 08:03:19 PM PDT 24
Finished Jul 29 08:05:37 PM PDT 24
Peak memory 576112 kb
Host smart-10a2b44f-2e42-42e6-985f-c0555131f170
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524528329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.2524528329
Directory /workspace/80.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.2891286742
Short name T1525
Test name
Test status
Simulation time 17935719443 ps
CPU time 302.65 seconds
Started Jul 29 08:03:16 PM PDT 24
Finished Jul 29 08:08:19 PM PDT 24
Peak memory 575992 kb
Host smart-0fa4ed5f-815a-48da-a028-034cac237c9e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891286742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.2891286742
Directory /workspace/80.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.3060550648
Short name T470
Test name
Test status
Simulation time 612637704 ps
CPU time 49.97 seconds
Started Jul 29 08:03:14 PM PDT 24
Finished Jul 29 08:04:05 PM PDT 24
Peak memory 575952 kb
Host smart-0873a437-5a60-4183-b6f0-c73105c4eb4c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060550648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del
ays.3060550648
Directory /workspace/80.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_same_source.668351105
Short name T1695
Test name
Test status
Simulation time 1865168531 ps
CPU time 51.66 seconds
Started Jul 29 08:03:18 PM PDT 24
Finished Jul 29 08:04:10 PM PDT 24
Peak memory 576068 kb
Host smart-2f168b56-457a-46de-96e0-8d0c813bec1a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668351105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.668351105
Directory /workspace/80.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke.4164582941
Short name T2498
Test name
Test status
Simulation time 221050981 ps
CPU time 8.9 seconds
Started Jul 29 08:03:11 PM PDT 24
Finished Jul 29 08:03:20 PM PDT 24
Peak memory 574332 kb
Host smart-79bc640c-c9b6-401a-bbbd-df2928c18ac5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164582941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.4164582941
Directory /workspace/80.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.1134778365
Short name T1473
Test name
Test status
Simulation time 8633762092 ps
CPU time 94.07 seconds
Started Jul 29 08:03:10 PM PDT 24
Finished Jul 29 08:04:44 PM PDT 24
Peak memory 574636 kb
Host smart-6ea22e1e-563f-4ae8-99f3-eb96d211c6e2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134778365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.1134778365
Directory /workspace/80.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.3918953113
Short name T2417
Test name
Test status
Simulation time 4313875553 ps
CPU time 73.01 seconds
Started Jul 29 08:03:14 PM PDT 24
Finished Jul 29 08:04:27 PM PDT 24
Peak memory 574652 kb
Host smart-6af77b87-64e8-4f8f-9451-38c4d38c93b8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918953113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.3918953113
Directory /workspace/80.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.3475803116
Short name T1830
Test name
Test status
Simulation time 41965871 ps
CPU time 5.98 seconds
Started Jul 29 08:03:10 PM PDT 24
Finished Jul 29 08:03:17 PM PDT 24
Peak memory 574548 kb
Host smart-b0c522d2-9867-422b-9cc9-3680debc9a2f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475803116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay
s.3475803116
Directory /workspace/80.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all.2454933867
Short name T1662
Test name
Test status
Simulation time 812344054 ps
CPU time 75.08 seconds
Started Jul 29 08:03:23 PM PDT 24
Finished Jul 29 08:04:38 PM PDT 24
Peak memory 575964 kb
Host smart-8d3db31e-ea44-4dad-9fd5-11f0fa0ad6ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454933867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.2454933867
Directory /workspace/80.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.2536181526
Short name T654
Test name
Test status
Simulation time 18512880605 ps
CPU time 695.69 seconds
Started Jul 29 08:03:22 PM PDT 24
Finished Jul 29 08:14:58 PM PDT 24
Peak memory 576376 kb
Host smart-fb5632aa-ca9a-483c-acfc-c48742257b2d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536181526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.2536181526
Directory /workspace/80.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2472174627
Short name T2454
Test name
Test status
Simulation time 57225443 ps
CPU time 9.9 seconds
Started Jul 29 08:03:23 PM PDT 24
Finished Jul 29 08:03:33 PM PDT 24
Peak memory 573964 kb
Host smart-59b5072a-e539-426c-8410-bec4773cbbf7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472174627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all
_with_rand_reset.2472174627
Directory /workspace/80.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3118545014
Short name T862
Test name
Test status
Simulation time 5981318696 ps
CPU time 548.04 seconds
Started Jul 29 08:03:22 PM PDT 24
Finished Jul 29 08:12:30 PM PDT 24
Peak memory 581852 kb
Host smart-cb2673b3-ee06-4df3-bf4c-e29f7f01d9e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118545014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al
l_with_reset_error.3118545014
Directory /workspace/80.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.185726499
Short name T450
Test name
Test status
Simulation time 1413989042 ps
CPU time 58.94 seconds
Started Jul 29 08:03:22 PM PDT 24
Finished Jul 29 08:04:21 PM PDT 24
Peak memory 575832 kb
Host smart-e047911d-80c1-4010-a80b-dda30caa24ff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185726499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.185726499
Directory /workspace/80.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_access_same_device.4056116535
Short name T1837
Test name
Test status
Simulation time 2603363467 ps
CPU time 95.05 seconds
Started Jul 29 08:03:35 PM PDT 24
Finished Jul 29 08:05:10 PM PDT 24
Peak memory 575948 kb
Host smart-5813c98d-1b9a-4937-b54e-823abfa26924
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056116535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device
.4056116535
Directory /workspace/81.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.2336254773
Short name T844
Test name
Test status
Simulation time 51060829619 ps
CPU time 898.15 seconds
Started Jul 29 08:03:42 PM PDT 24
Finished Jul 29 08:18:41 PM PDT 24
Peak memory 576008 kb
Host smart-f467d2bb-2813-45bd-8d03-5c56ffb8ef11
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336254773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_
device_slow_rsp.2336254773
Directory /workspace/81.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.3708893401
Short name T2284
Test name
Test status
Simulation time 64095499 ps
CPU time 9.88 seconds
Started Jul 29 08:03:35 PM PDT 24
Finished Jul 29 08:03:45 PM PDT 24
Peak memory 575912 kb
Host smart-f4e05048-6dc3-4260-a35a-5144ed7559d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708893401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add
r.3708893401
Directory /workspace/81.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_error_random.1503928444
Short name T1450
Test name
Test status
Simulation time 1294866024 ps
CPU time 41.79 seconds
Started Jul 29 08:03:34 PM PDT 24
Finished Jul 29 08:04:16 PM PDT 24
Peak memory 575908 kb
Host smart-fe447dfe-9140-464c-8197-344d2ee66ab8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503928444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.1503928444
Directory /workspace/81.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random.844408997
Short name T567
Test name
Test status
Simulation time 316867800 ps
CPU time 14.38 seconds
Started Jul 29 08:03:22 PM PDT 24
Finished Jul 29 08:03:37 PM PDT 24
Peak memory 575920 kb
Host smart-0247e31b-9e30-44cd-b89d-d4abc585db3e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844408997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.844408997
Directory /workspace/81.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.1505782690
Short name T2410
Test name
Test status
Simulation time 21356213137 ps
CPU time 223.58 seconds
Started Jul 29 08:03:33 PM PDT 24
Finished Jul 29 08:07:17 PM PDT 24
Peak memory 576176 kb
Host smart-6957c897-3a85-4c7d-ba4c-e0c26e252d2c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505782690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.1505782690
Directory /workspace/81.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.3826902765
Short name T1969
Test name
Test status
Simulation time 30398264364 ps
CPU time 527.89 seconds
Started Jul 29 08:03:33 PM PDT 24
Finished Jul 29 08:12:21 PM PDT 24
Peak memory 576056 kb
Host smart-29706fed-7f75-4eb0-a2a1-86520ae97db3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826902765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.3826902765
Directory /workspace/81.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.1509479515
Short name T2173
Test name
Test status
Simulation time 279259936 ps
CPU time 23.88 seconds
Started Jul 29 08:03:42 PM PDT 24
Finished Jul 29 08:04:06 PM PDT 24
Peak memory 575780 kb
Host smart-144ebdbb-9ded-4c7a-9b63-97c55316dbd2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509479515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del
ays.1509479515
Directory /workspace/81.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_same_source.1241987021
Short name T2041
Test name
Test status
Simulation time 542621714 ps
CPU time 17.29 seconds
Started Jul 29 08:03:36 PM PDT 24
Finished Jul 29 08:03:53 PM PDT 24
Peak memory 575816 kb
Host smart-65db9b93-bef8-41af-b4dc-640f675115a4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241987021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.1241987021
Directory /workspace/81.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke.458773668
Short name T2061
Test name
Test status
Simulation time 42152341 ps
CPU time 6.46 seconds
Started Jul 29 08:03:23 PM PDT 24
Finished Jul 29 08:03:30 PM PDT 24
Peak memory 573812 kb
Host smart-0554681b-fb08-4b13-8327-25deab9f26b0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458773668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.458773668
Directory /workspace/81.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.1931709497
Short name T1729
Test name
Test status
Simulation time 9211670973 ps
CPU time 93.62 seconds
Started Jul 29 08:03:22 PM PDT 24
Finished Jul 29 08:04:56 PM PDT 24
Peak memory 573912 kb
Host smart-4dbc4553-7dd2-4993-aa98-a2cfdfbe3631
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931709497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.1931709497
Directory /workspace/81.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.1478022468
Short name T2756
Test name
Test status
Simulation time 5226407203 ps
CPU time 91.38 seconds
Started Jul 29 08:03:22 PM PDT 24
Finished Jul 29 08:04:54 PM PDT 24
Peak memory 573996 kb
Host smart-0fd9f42d-a300-41bb-bf14-552f1e6123fc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478022468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.1478022468
Directory /workspace/81.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.1394681745
Short name T2148
Test name
Test status
Simulation time 44484265 ps
CPU time 5.89 seconds
Started Jul 29 08:03:22 PM PDT 24
Finished Jul 29 08:03:27 PM PDT 24
Peak memory 573852 kb
Host smart-4d674b09-339c-4a62-8c66-d0977e1ed24c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394681745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay
s.1394681745
Directory /workspace/81.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all.1865483038
Short name T2744
Test name
Test status
Simulation time 16167671471 ps
CPU time 588.91 seconds
Started Jul 29 08:03:34 PM PDT 24
Finished Jul 29 08:13:23 PM PDT 24
Peak memory 576248 kb
Host smart-f334dc08-0049-4a8d-8b76-f7a53b8de80a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865483038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.1865483038
Directory /workspace/81.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.581596482
Short name T1418
Test name
Test status
Simulation time 5893188 ps
CPU time 3.8 seconds
Started Jul 29 08:03:36 PM PDT 24
Finished Jul 29 08:03:40 PM PDT 24
Peak memory 566196 kb
Host smart-5f78123b-7ad2-4580-8f3f-6333c358cdde
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581596482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.581596482
Directory /workspace/81.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.3029078582
Short name T883
Test name
Test status
Simulation time 261561172 ps
CPU time 96.62 seconds
Started Jul 29 08:03:34 PM PDT 24
Finished Jul 29 08:05:11 PM PDT 24
Peak memory 575940 kb
Host smart-5ff45a6c-799e-4bdd-8335-fcc34f2464fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029078582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all
_with_rand_reset.3029078582
Directory /workspace/81.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.3257570311
Short name T2723
Test name
Test status
Simulation time 2334130442 ps
CPU time 272.99 seconds
Started Jul 29 08:03:38 PM PDT 24
Finished Jul 29 08:08:11 PM PDT 24
Peak memory 576864 kb
Host smart-9f205f9b-5063-4c8c-ae56-8738da193703
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257570311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al
l_with_reset_error.3257570311
Directory /workspace/81.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.89046086
Short name T1444
Test name
Test status
Simulation time 81259318 ps
CPU time 6.41 seconds
Started Jul 29 08:03:35 PM PDT 24
Finished Jul 29 08:03:42 PM PDT 24
Peak memory 574564 kb
Host smart-0a6a5feb-21fb-4749-bbdd-675d2f3bc97c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89046086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.89046086
Directory /workspace/81.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_access_same_device.1103577622
Short name T2633
Test name
Test status
Simulation time 697283101 ps
CPU time 44.64 seconds
Started Jul 29 08:03:43 PM PDT 24
Finished Jul 29 08:04:28 PM PDT 24
Peak memory 575996 kb
Host smart-ad149caf-2145-4327-9f23-cc2ab9089bea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103577622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device
.1103577622
Directory /workspace/82.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1228621096
Short name T1802
Test name
Test status
Simulation time 16648762974 ps
CPU time 283.68 seconds
Started Jul 29 08:03:45 PM PDT 24
Finished Jul 29 08:08:29 PM PDT 24
Peak memory 576036 kb
Host smart-58263c2e-93f1-4be4-9ad0-a85c2deab98d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228621096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_
device_slow_rsp.1228621096
Directory /workspace/82.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.1819332595
Short name T2764
Test name
Test status
Simulation time 20156195 ps
CPU time 5.29 seconds
Started Jul 29 08:03:43 PM PDT 24
Finished Jul 29 08:03:48 PM PDT 24
Peak memory 573880 kb
Host smart-d0df1f70-1c68-4286-933f-3e1b532fdcf5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819332595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add
r.1819332595
Directory /workspace/82.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_error_random.1603934938
Short name T2268
Test name
Test status
Simulation time 2549586330 ps
CPU time 86.66 seconds
Started Jul 29 08:03:45 PM PDT 24
Finished Jul 29 08:05:12 PM PDT 24
Peak memory 575940 kb
Host smart-dacda487-b767-4015-8cb8-725677286157
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603934938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.1603934938
Directory /workspace/82.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random.3655884149
Short name T2575
Test name
Test status
Simulation time 252953816 ps
CPU time 22.92 seconds
Started Jul 29 08:03:42 PM PDT 24
Finished Jul 29 08:04:06 PM PDT 24
Peak memory 575984 kb
Host smart-2211a12a-aa7c-4a8d-85ca-fd410df89f11
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655884149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.3655884149
Directory /workspace/82.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.3520724652
Short name T2135
Test name
Test status
Simulation time 14541574556 ps
CPU time 150.14 seconds
Started Jul 29 08:03:36 PM PDT 24
Finished Jul 29 08:06:06 PM PDT 24
Peak memory 576084 kb
Host smart-e272e59d-8c76-41eb-b766-8b5c7ae64bbc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520724652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.3520724652
Directory /workspace/82.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.2487053600
Short name T690
Test name
Test status
Simulation time 39488840738 ps
CPU time 650.88 seconds
Started Jul 29 08:03:38 PM PDT 24
Finished Jul 29 08:14:29 PM PDT 24
Peak memory 575976 kb
Host smart-fa801253-06c1-49cd-bbb5-ef18095396d1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487053600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.2487053600
Directory /workspace/82.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.973187050
Short name T2627
Test name
Test status
Simulation time 213190239 ps
CPU time 20.37 seconds
Started Jul 29 08:03:43 PM PDT 24
Finished Jul 29 08:04:03 PM PDT 24
Peak memory 575772 kb
Host smart-236740b3-3655-412a-8c7d-d93a5b7d276f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973187050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_dela
ys.973187050
Directory /workspace/82.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_same_source.3969252377
Short name T492
Test name
Test status
Simulation time 2518043358 ps
CPU time 70.84 seconds
Started Jul 29 08:03:45 PM PDT 24
Finished Jul 29 08:04:56 PM PDT 24
Peak memory 575984 kb
Host smart-95eae299-7bfe-4375-a5fa-146f91c04790
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969252377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.3969252377
Directory /workspace/82.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke.1947192264
Short name T1782
Test name
Test status
Simulation time 43463327 ps
CPU time 5.76 seconds
Started Jul 29 08:03:36 PM PDT 24
Finished Jul 29 08:03:42 PM PDT 24
Peak memory 573908 kb
Host smart-fa072d26-c653-4c77-935e-21c1c198d2c0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947192264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.1947192264
Directory /workspace/82.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.390892128
Short name T1588
Test name
Test status
Simulation time 9320695737 ps
CPU time 88.56 seconds
Started Jul 29 08:03:37 PM PDT 24
Finished Jul 29 08:05:06 PM PDT 24
Peak memory 574028 kb
Host smart-b1df00f7-86aa-4ce2-8f86-46d8ae4a365e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390892128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.390892128
Directory /workspace/82.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.2500822402
Short name T2898
Test name
Test status
Simulation time 5176049164 ps
CPU time 92.26 seconds
Started Jul 29 08:03:36 PM PDT 24
Finished Jul 29 08:05:09 PM PDT 24
Peak memory 574644 kb
Host smart-ff53ca80-41fd-4ba8-ae14-6f94a1b94514
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500822402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.2500822402
Directory /workspace/82.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.3861898196
Short name T2474
Test name
Test status
Simulation time 51916187 ps
CPU time 5.98 seconds
Started Jul 29 08:03:39 PM PDT 24
Finished Jul 29 08:03:45 PM PDT 24
Peak memory 573788 kb
Host smart-c1c1a90a-570c-475d-ac6c-26b17c8ac94f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861898196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay
s.3861898196
Directory /workspace/82.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all.2481026137
Short name T523
Test name
Test status
Simulation time 8826730563 ps
CPU time 294.79 seconds
Started Jul 29 08:03:46 PM PDT 24
Finished Jul 29 08:08:40 PM PDT 24
Peak memory 576072 kb
Host smart-9682a0a8-3f7f-4b85-8101-3f2ab73f900a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481026137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.2481026137
Directory /workspace/82.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.1936060234
Short name T1950
Test name
Test status
Simulation time 13692317602 ps
CPU time 482.07 seconds
Started Jul 29 08:03:45 PM PDT 24
Finished Jul 29 08:11:47 PM PDT 24
Peak memory 576304 kb
Host smart-8221fb47-a9d8-4c60-8ddf-8ad9bb8f34ef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936060234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.1936060234
Directory /workspace/82.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.4244239953
Short name T1672
Test name
Test status
Simulation time 11037999207 ps
CPU time 603.86 seconds
Started Jul 29 08:03:44 PM PDT 24
Finished Jul 29 08:13:48 PM PDT 24
Peak memory 576820 kb
Host smart-de61a138-ee51-43b1-8e73-2cc5ab4a4a52
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244239953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all
_with_rand_reset.4244239953
Directory /workspace/82.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.2406235221
Short name T2167
Test name
Test status
Simulation time 2879766533 ps
CPU time 269.89 seconds
Started Jul 29 08:03:44 PM PDT 24
Finished Jul 29 08:08:14 PM PDT 24
Peak memory 576000 kb
Host smart-e36f5562-342b-455b-9f47-86c6a4a6776b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406235221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al
l_with_reset_error.2406235221
Directory /workspace/82.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.482870375
Short name T1861
Test name
Test status
Simulation time 1432930961 ps
CPU time 55.12 seconds
Started Jul 29 08:03:42 PM PDT 24
Finished Jul 29 08:04:38 PM PDT 24
Peak memory 576096 kb
Host smart-d2aafb49-4141-440d-9e19-07d8b5fcec3d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482870375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.482870375
Directory /workspace/82.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_access_same_device.125867469
Short name T2275
Test name
Test status
Simulation time 1949384986 ps
CPU time 79.74 seconds
Started Jul 29 08:03:41 PM PDT 24
Finished Jul 29 08:05:01 PM PDT 24
Peak memory 576100 kb
Host smart-dfe7b1e2-d7a2-45c9-9007-7734c4eda589
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125867469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device.
125867469
Directory /workspace/83.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.239669987
Short name T2549
Test name
Test status
Simulation time 69804506882 ps
CPU time 1272.55 seconds
Started Jul 29 08:03:47 PM PDT 24
Finished Jul 29 08:24:59 PM PDT 24
Peak memory 576248 kb
Host smart-4666cb1a-a4fd-4004-ac81-1e565938f3c8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239669987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_d
evice_slow_rsp.239669987
Directory /workspace/83.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.381313474
Short name T1520
Test name
Test status
Simulation time 23988624 ps
CPU time 5.67 seconds
Started Jul 29 08:03:49 PM PDT 24
Finished Jul 29 08:03:55 PM PDT 24
Peak memory 574000 kb
Host smart-01d69c39-918d-40de-acaf-31c265022030
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381313474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_addr
.381313474
Directory /workspace/83.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_error_random.734623771
Short name T2019
Test name
Test status
Simulation time 334441560 ps
CPU time 13.4 seconds
Started Jul 29 08:03:51 PM PDT 24
Finished Jul 29 08:04:04 PM PDT 24
Peak memory 576020 kb
Host smart-a1f24dc4-9a85-46f5-9631-880a90f93f22
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734623771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.734623771
Directory /workspace/83.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random.995316845
Short name T1939
Test name
Test status
Simulation time 524351302 ps
CPU time 43.48 seconds
Started Jul 29 08:03:45 PM PDT 24
Finished Jul 29 08:04:28 PM PDT 24
Peak memory 576080 kb
Host smart-2cc87140-530e-4079-9c72-446d43d4ccae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995316845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.995316845
Directory /workspace/83.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.1306811497
Short name T1982
Test name
Test status
Simulation time 63887583046 ps
CPU time 667.73 seconds
Started Jul 29 08:03:45 PM PDT 24
Finished Jul 29 08:14:53 PM PDT 24
Peak memory 576008 kb
Host smart-d083eaba-e036-4a29-8e3c-b639ad0bcbb7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306811497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.1306811497
Directory /workspace/83.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.1549377891
Short name T2612
Test name
Test status
Simulation time 3421403690 ps
CPU time 60.42 seconds
Started Jul 29 08:03:42 PM PDT 24
Finished Jul 29 08:04:43 PM PDT 24
Peak memory 573976 kb
Host smart-920fd38b-fca4-4ce1-be47-fa083e1a590e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549377891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.1549377891
Directory /workspace/83.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.4145809462
Short name T2045
Test name
Test status
Simulation time 306261538 ps
CPU time 29.87 seconds
Started Jul 29 08:03:43 PM PDT 24
Finished Jul 29 08:04:14 PM PDT 24
Peak memory 575844 kb
Host smart-c110bef1-5f9f-42e4-82c8-05b91a110a6a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145809462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del
ays.4145809462
Directory /workspace/83.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_same_source.3642653698
Short name T613
Test name
Test status
Simulation time 935827097 ps
CPU time 27.05 seconds
Started Jul 29 08:03:44 PM PDT 24
Finished Jul 29 08:04:11 PM PDT 24
Peak memory 575856 kb
Host smart-3db68b98-bdfa-4887-967f-61a3cbafb323
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642653698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.3642653698
Directory /workspace/83.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke.3366743697
Short name T2295
Test name
Test status
Simulation time 209439057 ps
CPU time 8.11 seconds
Started Jul 29 08:03:42 PM PDT 24
Finished Jul 29 08:03:51 PM PDT 24
Peak memory 574580 kb
Host smart-7a30d710-5176-4187-9cd9-2a6c58a57ddc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366743697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.3366743697
Directory /workspace/83.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.2239822748
Short name T1684
Test name
Test status
Simulation time 7422575747 ps
CPU time 78.57 seconds
Started Jul 29 08:03:44 PM PDT 24
Finished Jul 29 08:05:03 PM PDT 24
Peak memory 573976 kb
Host smart-8f83ca33-f911-47df-9515-d40d29b46ea5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239822748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.2239822748
Directory /workspace/83.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.2406085852
Short name T1925
Test name
Test status
Simulation time 5769074954 ps
CPU time 98.2 seconds
Started Jul 29 08:03:45 PM PDT 24
Finished Jul 29 08:05:23 PM PDT 24
Peak memory 573988 kb
Host smart-e9b7e561-cfa4-40cc-a583-20333966f7c2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406085852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.2406085852
Directory /workspace/83.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.3161927997
Short name T1773
Test name
Test status
Simulation time 53735766 ps
CPU time 6.85 seconds
Started Jul 29 08:03:43 PM PDT 24
Finished Jul 29 08:03:50 PM PDT 24
Peak memory 574544 kb
Host smart-be0898f3-a959-4560-92d7-a18c636c7a43
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161927997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay
s.3161927997
Directory /workspace/83.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.2798828081
Short name T2604
Test name
Test status
Simulation time 3951578843 ps
CPU time 129.23 seconds
Started Jul 29 08:03:50 PM PDT 24
Finished Jul 29 08:06:00 PM PDT 24
Peak memory 575944 kb
Host smart-5ef4ca07-cf51-4d89-98d3-9ec513c89cd9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798828081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.2798828081
Directory /workspace/83.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.2657463687
Short name T429
Test name
Test status
Simulation time 4026270407 ps
CPU time 495.96 seconds
Started Jul 29 08:03:55 PM PDT 24
Finished Jul 29 08:12:11 PM PDT 24
Peak memory 575992 kb
Host smart-8a04ff83-1ad7-4f02-b060-293961f6e3af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657463687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all
_with_rand_reset.2657463687
Directory /workspace/83.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.2166914274
Short name T726
Test name
Test status
Simulation time 3639341863 ps
CPU time 368.19 seconds
Started Jul 29 08:03:51 PM PDT 24
Finished Jul 29 08:09:59 PM PDT 24
Peak memory 576860 kb
Host smart-dcb7b65a-8e5d-4cda-9356-91333ac126d9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166914274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al
l_with_reset_error.2166914274
Directory /workspace/83.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.544065048
Short name T2310
Test name
Test status
Simulation time 123003776 ps
CPU time 8.28 seconds
Started Jul 29 08:03:50 PM PDT 24
Finished Jul 29 08:03:59 PM PDT 24
Peak memory 573992 kb
Host smart-9965df5f-0058-47a4-b346-bc440826abb7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544065048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.544065048
Directory /workspace/83.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_access_same_device.418667955
Short name T2919
Test name
Test status
Simulation time 323524721 ps
CPU time 13.44 seconds
Started Jul 29 08:03:57 PM PDT 24
Finished Jul 29 08:04:11 PM PDT 24
Peak memory 573864 kb
Host smart-e850ed56-14f4-4ea1-87ba-869031998e19
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418667955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device.
418667955
Directory /workspace/84.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.320882342
Short name T2849
Test name
Test status
Simulation time 73850770798 ps
CPU time 1276.29 seconds
Started Jul 29 08:03:58 PM PDT 24
Finished Jul 29 08:25:15 PM PDT 24
Peak memory 576112 kb
Host smart-1eafec74-2528-4fa5-a0e0-42252367b60b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320882342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_d
evice_slow_rsp.320882342
Directory /workspace/84.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.4026188976
Short name T2396
Test name
Test status
Simulation time 313106450 ps
CPU time 27.25 seconds
Started Jul 29 08:04:05 PM PDT 24
Finished Jul 29 08:04:33 PM PDT 24
Peak memory 575784 kb
Host smart-f6b66814-027c-408c-8f7e-ad92b0f75de5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026188976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add
r.4026188976
Directory /workspace/84.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_error_random.944534709
Short name T2606
Test name
Test status
Simulation time 378344447 ps
CPU time 32.15 seconds
Started Jul 29 08:04:06 PM PDT 24
Finished Jul 29 08:04:38 PM PDT 24
Peak memory 575672 kb
Host smart-08c1abbb-0ebe-4541-9215-473a6b021e77
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944534709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.944534709
Directory /workspace/84.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random.4244541571
Short name T2274
Test name
Test status
Simulation time 1730445144 ps
CPU time 64.55 seconds
Started Jul 29 08:03:56 PM PDT 24
Finished Jul 29 08:05:00 PM PDT 24
Peak memory 575960 kb
Host smart-284469b0-99ab-484b-b732-4dad825d0a92
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244541571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.4244541571
Directory /workspace/84.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.117017334
Short name T2597
Test name
Test status
Simulation time 92313134761 ps
CPU time 1007.19 seconds
Started Jul 29 08:03:56 PM PDT 24
Finished Jul 29 08:20:43 PM PDT 24
Peak memory 576004 kb
Host smart-f4f08741-0f33-4ab9-aaac-3aee39a19846
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117017334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.117017334
Directory /workspace/84.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.313581259
Short name T1702
Test name
Test status
Simulation time 36207569668 ps
CPU time 630.98 seconds
Started Jul 29 08:03:57 PM PDT 24
Finished Jul 29 08:14:28 PM PDT 24
Peak memory 575908 kb
Host smart-8d8b2d2c-bc2c-46e0-b36c-30bbc047a2e8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313581259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.313581259
Directory /workspace/84.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.1058851747
Short name T2020
Test name
Test status
Simulation time 339676261 ps
CPU time 28.91 seconds
Started Jul 29 08:03:57 PM PDT 24
Finished Jul 29 08:04:26 PM PDT 24
Peak memory 575880 kb
Host smart-a27dd196-2014-4eff-9809-c1a98e50009a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058851747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del
ays.1058851747
Directory /workspace/84.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_same_source.958831957
Short name T1523
Test name
Test status
Simulation time 533811734 ps
CPU time 18.76 seconds
Started Jul 29 08:03:56 PM PDT 24
Finished Jul 29 08:04:15 PM PDT 24
Peak memory 575980 kb
Host smart-58f9f737-75f0-410c-b71a-9113dd2e1925
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958831957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.958831957
Directory /workspace/84.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke.1975234237
Short name T2794
Test name
Test status
Simulation time 46042611 ps
CPU time 5.97 seconds
Started Jul 29 08:03:54 PM PDT 24
Finished Jul 29 08:04:00 PM PDT 24
Peak memory 573892 kb
Host smart-eed7fbed-9315-470d-8b91-6792f7abdbaa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975234237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.1975234237
Directory /workspace/84.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.604021106
Short name T1619
Test name
Test status
Simulation time 8992777582 ps
CPU time 88.56 seconds
Started Jul 29 08:03:52 PM PDT 24
Finished Jul 29 08:05:21 PM PDT 24
Peak memory 574648 kb
Host smart-037c7826-5ba5-4d93-abe3-38efd159b14f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604021106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.604021106
Directory /workspace/84.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.932035259
Short name T1448
Test name
Test status
Simulation time 5420215755 ps
CPU time 93.54 seconds
Started Jul 29 08:04:05 PM PDT 24
Finished Jul 29 08:05:39 PM PDT 24
Peak memory 574764 kb
Host smart-08649a68-2828-4491-8662-8cea5b170641
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932035259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.932035259
Directory /workspace/84.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.311676281
Short name T1993
Test name
Test status
Simulation time 52063780 ps
CPU time 6.38 seconds
Started Jul 29 08:03:52 PM PDT 24
Finished Jul 29 08:03:58 PM PDT 24
Peak memory 574552 kb
Host smart-04d47eb3-8aa7-4e8c-b21d-76820fd94fc9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311676281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delays
.311676281
Directory /workspace/84.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all.4284874701
Short name T2487
Test name
Test status
Simulation time 7114834456 ps
CPU time 207.85 seconds
Started Jul 29 08:04:06 PM PDT 24
Finished Jul 29 08:07:34 PM PDT 24
Peak memory 576040 kb
Host smart-759e0dc5-b977-4d7c-9228-9b7c2b88dda7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284874701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.4284874701
Directory /workspace/84.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.842700982
Short name T1744
Test name
Test status
Simulation time 1473829320 ps
CPU time 104.55 seconds
Started Jul 29 08:04:05 PM PDT 24
Finished Jul 29 08:05:50 PM PDT 24
Peak memory 576020 kb
Host smart-acf690e1-a8ac-4cc9-8573-e44f9a10af23
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842700982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.842700982
Directory /workspace/84.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.2116754552
Short name T437
Test name
Test status
Simulation time 4476817751 ps
CPU time 655.69 seconds
Started Jul 29 08:04:05 PM PDT 24
Finished Jul 29 08:15:01 PM PDT 24
Peak memory 576996 kb
Host smart-4fdda719-6d39-4401-9315-7438b7bea443
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116754552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all
_with_rand_reset.2116754552
Directory /workspace/84.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.3533113009
Short name T537
Test name
Test status
Simulation time 2125079086 ps
CPU time 191.67 seconds
Started Jul 29 08:03:58 PM PDT 24
Finished Jul 29 08:07:10 PM PDT 24
Peak memory 576808 kb
Host smart-b63b369f-84f6-420e-a60f-346ce25da46b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533113009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al
l_with_reset_error.3533113009
Directory /workspace/84.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.2082352080
Short name T1962
Test name
Test status
Simulation time 1350115633 ps
CPU time 56.38 seconds
Started Jul 29 08:04:05 PM PDT 24
Finished Jul 29 08:05:01 PM PDT 24
Peak memory 575956 kb
Host smart-4350ad14-101b-4dbe-b645-8f2914d8e5ca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082352080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.2082352080
Directory /workspace/84.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_access_same_device.2595196584
Short name T1456
Test name
Test status
Simulation time 1160369446 ps
CPU time 84.21 seconds
Started Jul 29 08:04:04 PM PDT 24
Finished Jul 29 08:05:28 PM PDT 24
Peak memory 576032 kb
Host smart-61356cdc-59bd-46e9-b43b-f0f24a843fb7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595196584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device
.2595196584
Directory /workspace/85.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.2696608033
Short name T2425
Test name
Test status
Simulation time 92849378687 ps
CPU time 1866.84 seconds
Started Jul 29 08:04:04 PM PDT 24
Finished Jul 29 08:35:11 PM PDT 24
Peak memory 576140 kb
Host smart-13087759-2168-46ad-b376-90fef9bb341f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696608033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_
device_slow_rsp.2696608033
Directory /workspace/85.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1911576806
Short name T2429
Test name
Test status
Simulation time 102042332 ps
CPU time 13.31 seconds
Started Jul 29 08:04:12 PM PDT 24
Finished Jul 29 08:04:25 PM PDT 24
Peak memory 575764 kb
Host smart-25976daa-6eb0-44fe-b1d2-40b8fcc0946a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911576806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add
r.1911576806
Directory /workspace/85.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_error_random.2263846212
Short name T1600
Test name
Test status
Simulation time 37054104 ps
CPU time 5.96 seconds
Started Jul 29 08:04:04 PM PDT 24
Finished Jul 29 08:04:10 PM PDT 24
Peak memory 573940 kb
Host smart-e7f8d8c9-499d-4a7f-99cd-623e5f2e1862
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263846212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.2263846212
Directory /workspace/85.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random.3128562504
Short name T2554
Test name
Test status
Simulation time 1117793945 ps
CPU time 37.93 seconds
Started Jul 29 08:04:06 PM PDT 24
Finished Jul 29 08:04:44 PM PDT 24
Peak memory 575792 kb
Host smart-6a19711d-5d97-4888-a0d4-55dc7b147384
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128562504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.3128562504
Directory /workspace/85.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.1199087079
Short name T1654
Test name
Test status
Simulation time 9832314270 ps
CPU time 104.35 seconds
Started Jul 29 08:04:04 PM PDT 24
Finished Jul 29 08:05:49 PM PDT 24
Peak memory 575992 kb
Host smart-04dc912b-ffe1-497d-bf0c-c4f22032b297
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199087079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.1199087079
Directory /workspace/85.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.3045791020
Short name T1991
Test name
Test status
Simulation time 22535815179 ps
CPU time 376.3 seconds
Started Jul 29 08:04:03 PM PDT 24
Finished Jul 29 08:10:19 PM PDT 24
Peak memory 576032 kb
Host smart-0db77c11-dec4-4da5-825f-9c2d0c951fa7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045791020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.3045791020
Directory /workspace/85.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.715343428
Short name T596
Test name
Test status
Simulation time 554050686 ps
CPU time 45.14 seconds
Started Jul 29 08:04:05 PM PDT 24
Finished Jul 29 08:04:50 PM PDT 24
Peak memory 575812 kb
Host smart-ba992a42-6333-4245-b16b-014d4ee134d7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715343428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_dela
ys.715343428
Directory /workspace/85.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_same_source.1641589736
Short name T659
Test name
Test status
Simulation time 1019930509 ps
CPU time 31.28 seconds
Started Jul 29 08:04:05 PM PDT 24
Finished Jul 29 08:04:36 PM PDT 24
Peak memory 575936 kb
Host smart-f40f7408-5770-4d76-8292-22bad3a9b2a4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641589736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.1641589736
Directory /workspace/85.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke.1104691370
Short name T1953
Test name
Test status
Simulation time 223343113 ps
CPU time 9.24 seconds
Started Jul 29 08:04:07 PM PDT 24
Finished Jul 29 08:04:16 PM PDT 24
Peak memory 573904 kb
Host smart-a45ab1a5-6474-4d40-b4ea-60a379d817cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104691370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.1104691370
Directory /workspace/85.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.1468479325
Short name T2599
Test name
Test status
Simulation time 6260699179 ps
CPU time 70 seconds
Started Jul 29 08:04:05 PM PDT 24
Finished Jul 29 08:05:15 PM PDT 24
Peak memory 573924 kb
Host smart-ff0f26c6-5103-48a2-aa93-4f3ded8fae5a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468479325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.1468479325
Directory /workspace/85.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.2832256294
Short name T553
Test name
Test status
Simulation time 7468857431 ps
CPU time 122.85 seconds
Started Jul 29 08:04:06 PM PDT 24
Finished Jul 29 08:06:09 PM PDT 24
Peak memory 573940 kb
Host smart-7a70c662-0231-48a2-8490-431831c9d66d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832256294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.2832256294
Directory /workspace/85.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.4038958253
Short name T1641
Test name
Test status
Simulation time 56792542 ps
CPU time 6.38 seconds
Started Jul 29 08:04:03 PM PDT 24
Finished Jul 29 08:04:09 PM PDT 24
Peak memory 573840 kb
Host smart-b3816873-f0a8-4a0a-b52c-7670ce509c8a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038958253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay
s.4038958253
Directory /workspace/85.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all.4260747389
Short name T1872
Test name
Test status
Simulation time 9580592917 ps
CPU time 364.06 seconds
Started Jul 29 08:04:11 PM PDT 24
Finished Jul 29 08:10:15 PM PDT 24
Peak memory 576808 kb
Host smart-c4f5678a-bd5d-4619-8e4e-9b7db118919c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260747389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.4260747389
Directory /workspace/85.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.3135599712
Short name T2411
Test name
Test status
Simulation time 2494443183 ps
CPU time 171.76 seconds
Started Jul 29 08:04:11 PM PDT 24
Finished Jul 29 08:07:03 PM PDT 24
Peak memory 576216 kb
Host smart-e1a50938-44ef-462f-b7a5-a884fc555aff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135599712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.3135599712
Directory /workspace/85.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.3779912030
Short name T481
Test name
Test status
Simulation time 2090005770 ps
CPU time 363.71 seconds
Started Jul 29 08:04:10 PM PDT 24
Finished Jul 29 08:10:14 PM PDT 24
Peak memory 576780 kb
Host smart-8fcd4ef6-199f-4af3-a70d-3a895dc457f0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779912030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all
_with_rand_reset.3779912030
Directory /workspace/85.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.1096089728
Short name T877
Test name
Test status
Simulation time 164245147 ps
CPU time 33.08 seconds
Started Jul 29 08:04:11 PM PDT 24
Finished Jul 29 08:04:45 PM PDT 24
Peak memory 575920 kb
Host smart-86f0b942-a45f-4275-98ef-4e8d742c808d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096089728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al
l_with_reset_error.1096089728
Directory /workspace/85.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.3450741161
Short name T1434
Test name
Test status
Simulation time 620843569 ps
CPU time 25.92 seconds
Started Jul 29 08:04:09 PM PDT 24
Finished Jul 29 08:04:35 PM PDT 24
Peak memory 576040 kb
Host smart-922c39ca-7db7-426d-9f97-2a57aaf8ea53
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450741161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3450741161
Directory /workspace/85.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_access_same_device.2869439040
Short name T1621
Test name
Test status
Simulation time 963631395 ps
CPU time 36.93 seconds
Started Jul 29 08:04:17 PM PDT 24
Finished Jul 29 08:04:54 PM PDT 24
Peak memory 576008 kb
Host smart-b8d462e6-25d2-4dac-9ec3-f51832bf3102
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869439040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device
.2869439040
Directory /workspace/86.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.61118265
Short name T2233
Test name
Test status
Simulation time 23449704895 ps
CPU time 400.87 seconds
Started Jul 29 08:04:21 PM PDT 24
Finished Jul 29 08:11:02 PM PDT 24
Peak memory 576056 kb
Host smart-4d4e7d1e-06c6-4da5-bb04-1d6636905fbf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61118265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_de
vice_slow_rsp.61118265
Directory /workspace/86.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.85310871
Short name T1451
Test name
Test status
Simulation time 569201175 ps
CPU time 25.16 seconds
Started Jul 29 08:04:20 PM PDT 24
Finished Jul 29 08:04:45 PM PDT 24
Peak memory 575808 kb
Host smart-5dc61e34-a7ac-4bb1-ba5b-268fad3c3604
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85310871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_addr.85310871
Directory /workspace/86.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_error_random.868078659
Short name T2431
Test name
Test status
Simulation time 363153682 ps
CPU time 30.8 seconds
Started Jul 29 08:04:19 PM PDT 24
Finished Jul 29 08:04:50 PM PDT 24
Peak memory 575940 kb
Host smart-9f0b9c82-044b-49c6-ad3c-ef5618860eb2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868078659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.868078659
Directory /workspace/86.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random.2325614705
Short name T2933
Test name
Test status
Simulation time 712848536 ps
CPU time 29.35 seconds
Started Jul 29 08:04:12 PM PDT 24
Finished Jul 29 08:04:41 PM PDT 24
Peak memory 575896 kb
Host smart-de1ff1de-f0c6-4c2b-b91c-c9680e3729c8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325614705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.2325614705
Directory /workspace/86.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.1547460592
Short name T2033
Test name
Test status
Simulation time 70711148006 ps
CPU time 790.95 seconds
Started Jul 29 08:04:19 PM PDT 24
Finished Jul 29 08:17:30 PM PDT 24
Peak memory 576072 kb
Host smart-e4a589b3-0e44-421f-8831-b581608cff47
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547460592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.1547460592
Directory /workspace/86.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.390754364
Short name T2203
Test name
Test status
Simulation time 25448495715 ps
CPU time 493.1 seconds
Started Jul 29 08:04:19 PM PDT 24
Finished Jul 29 08:12:32 PM PDT 24
Peak memory 576096 kb
Host smart-ec016b02-7235-48a8-9fee-ff4223cef721
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390754364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.390754364
Directory /workspace/86.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.4135889246
Short name T1686
Test name
Test status
Simulation time 284694861 ps
CPU time 29.02 seconds
Started Jul 29 08:04:19 PM PDT 24
Finished Jul 29 08:04:48 PM PDT 24
Peak memory 575904 kb
Host smart-0034b5ef-e134-403f-b3f9-5f5a88e429f7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135889246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del
ays.4135889246
Directory /workspace/86.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_same_source.1328630755
Short name T670
Test name
Test status
Simulation time 368318020 ps
CPU time 13.34 seconds
Started Jul 29 08:04:18 PM PDT 24
Finished Jul 29 08:04:31 PM PDT 24
Peak memory 575888 kb
Host smart-5ad12c61-f643-49ec-b5fe-a351b8f2c771
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328630755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.1328630755
Directory /workspace/86.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke.3529447531
Short name T2771
Test name
Test status
Simulation time 247199537 ps
CPU time 10.26 seconds
Started Jul 29 08:04:12 PM PDT 24
Finished Jul 29 08:04:22 PM PDT 24
Peak memory 574520 kb
Host smart-b3d1bfe8-8501-43fb-ac60-9839ecfeb2a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529447531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.3529447531
Directory /workspace/86.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.4188178003
Short name T685
Test name
Test status
Simulation time 6035610450 ps
CPU time 62.75 seconds
Started Jul 29 08:04:10 PM PDT 24
Finished Jul 29 08:05:13 PM PDT 24
Peak memory 573872 kb
Host smart-82f29724-dba8-4566-babb-fe89fe1da1b0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188178003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.4188178003
Directory /workspace/86.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.1764687727
Short name T2023
Test name
Test status
Simulation time 5895846117 ps
CPU time 99.35 seconds
Started Jul 29 08:04:13 PM PDT 24
Finished Jul 29 08:05:52 PM PDT 24
Peak memory 573932 kb
Host smart-2276ee75-f379-4bb5-94f2-b5a685aa2b64
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764687727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.1764687727
Directory /workspace/86.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.1358384614
Short name T2721
Test name
Test status
Simulation time 41329566 ps
CPU time 5.79 seconds
Started Jul 29 08:04:10 PM PDT 24
Finished Jul 29 08:04:16 PM PDT 24
Peak memory 574516 kb
Host smart-6e9ea07d-9018-48b7-91f6-ec5191aa8d27
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358384614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay
s.1358384614
Directory /workspace/86.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all.3727581124
Short name T597
Test name
Test status
Simulation time 10624039831 ps
CPU time 399.65 seconds
Started Jul 29 08:04:16 PM PDT 24
Finished Jul 29 08:10:56 PM PDT 24
Peak memory 576788 kb
Host smart-a596a2c2-64ec-4041-8b2e-6bf7ff0f0839
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727581124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.3727581124
Directory /workspace/86.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.4159679745
Short name T2581
Test name
Test status
Simulation time 4060287686 ps
CPU time 324.32 seconds
Started Jul 29 08:04:21 PM PDT 24
Finished Jul 29 08:09:46 PM PDT 24
Peak memory 576192 kb
Host smart-fc0aedbe-f088-45c3-b1b0-7ea830cddf90
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159679745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.4159679745
Directory /workspace/86.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.3567363895
Short name T2249
Test name
Test status
Simulation time 6401090729 ps
CPU time 691.53 seconds
Started Jul 29 08:04:20 PM PDT 24
Finished Jul 29 08:15:52 PM PDT 24
Peak memory 576028 kb
Host smart-283bf034-d49d-47ea-bac2-121273e82c82
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567363895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all
_with_rand_reset.3567363895
Directory /workspace/86.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.1947533425
Short name T1507
Test name
Test status
Simulation time 1937377471 ps
CPU time 181.27 seconds
Started Jul 29 08:04:19 PM PDT 24
Finished Jul 29 08:07:21 PM PDT 24
Peak memory 576792 kb
Host smart-1ea6b21a-1e39-4d1d-ab27-10bec2bc04b7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947533425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al
l_with_reset_error.1947533425
Directory /workspace/86.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.1001461320
Short name T2136
Test name
Test status
Simulation time 195538848 ps
CPU time 10.27 seconds
Started Jul 29 08:04:17 PM PDT 24
Finished Jul 29 08:04:27 PM PDT 24
Peak memory 576016 kb
Host smart-96b6050e-b493-457e-984c-143a1e191481
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001461320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.1001461320
Directory /workspace/86.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_access_same_device.1019699276
Short name T2894
Test name
Test status
Simulation time 736779136 ps
CPU time 61.73 seconds
Started Jul 29 08:04:25 PM PDT 24
Finished Jul 29 08:05:27 PM PDT 24
Peak memory 576060 kb
Host smart-7db53014-2104-4492-b0e6-2822e0510abb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019699276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device
.1019699276
Directory /workspace/87.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.1628655806
Short name T2648
Test name
Test status
Simulation time 64514935651 ps
CPU time 1113.03 seconds
Started Jul 29 08:04:29 PM PDT 24
Finished Jul 29 08:23:02 PM PDT 24
Peak memory 575764 kb
Host smart-3ebbbcaf-44a0-43f6-a934-d3df01250c75
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628655806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_
device_slow_rsp.1628655806
Directory /workspace/87.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.316921248
Short name T2339
Test name
Test status
Simulation time 638699482 ps
CPU time 27.85 seconds
Started Jul 29 08:04:25 PM PDT 24
Finished Jul 29 08:04:53 PM PDT 24
Peak memory 575800 kb
Host smart-f83152ec-1c82-431c-a76d-f584e92e96f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316921248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_addr
.316921248
Directory /workspace/87.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_error_random.1544676597
Short name T2838
Test name
Test status
Simulation time 1845584601 ps
CPU time 67.93 seconds
Started Jul 29 08:04:29 PM PDT 24
Finished Jul 29 08:05:37 PM PDT 24
Peak memory 575720 kb
Host smart-bd9fff90-8756-4473-855c-28844112d51b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544676597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.1544676597
Directory /workspace/87.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random.3413317050
Short name T1570
Test name
Test status
Simulation time 278963079 ps
CPU time 11.74 seconds
Started Jul 29 08:04:26 PM PDT 24
Finished Jul 29 08:04:38 PM PDT 24
Peak memory 575980 kb
Host smart-c14f0bc7-0b68-4010-b775-1309ae798d0b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413317050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.3413317050
Directory /workspace/87.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.3493576645
Short name T2082
Test name
Test status
Simulation time 17947818831 ps
CPU time 192.8 seconds
Started Jul 29 08:04:25 PM PDT 24
Finished Jul 29 08:07:38 PM PDT 24
Peak memory 576076 kb
Host smart-813ab3f3-35e6-4556-a661-7214164eb6b9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493576645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.3493576645
Directory /workspace/87.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.1473084957
Short name T466
Test name
Test status
Simulation time 47608339241 ps
CPU time 856.63 seconds
Started Jul 29 08:04:27 PM PDT 24
Finished Jul 29 08:18:44 PM PDT 24
Peak memory 576128 kb
Host smart-ea35a29b-d1f3-4e02-9fbf-739daefdc06e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473084957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.1473084957
Directory /workspace/87.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.3450159849
Short name T1506
Test name
Test status
Simulation time 71346505 ps
CPU time 8.51 seconds
Started Jul 29 08:04:26 PM PDT 24
Finished Jul 29 08:04:34 PM PDT 24
Peak memory 575944 kb
Host smart-5933153b-1b0f-435c-836d-3aa2391592d5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450159849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del
ays.3450159849
Directory /workspace/87.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_same_source.3448096263
Short name T2913
Test name
Test status
Simulation time 530101567 ps
CPU time 36.82 seconds
Started Jul 29 08:04:25 PM PDT 24
Finished Jul 29 08:05:02 PM PDT 24
Peak memory 575836 kb
Host smart-6ae08c44-b6b5-4ab9-adb7-30e0afc267a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448096263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.3448096263
Directory /workspace/87.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke.3692058847
Short name T2155
Test name
Test status
Simulation time 208040116 ps
CPU time 8.68 seconds
Started Jul 29 08:04:19 PM PDT 24
Finished Jul 29 08:04:28 PM PDT 24
Peak memory 573884 kb
Host smart-1c0b2c5e-7217-41cf-aad9-988999fb0159
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692058847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.3692058847
Directory /workspace/87.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.958595604
Short name T1820
Test name
Test status
Simulation time 4926355348 ps
CPU time 49.36 seconds
Started Jul 29 08:04:27 PM PDT 24
Finished Jul 29 08:05:16 PM PDT 24
Peak memory 573984 kb
Host smart-ab3c58aa-0937-4306-8ba4-1598a3a98be4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958595604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.958595604
Directory /workspace/87.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.2749689951
Short name T2443
Test name
Test status
Simulation time 5931013990 ps
CPU time 97.18 seconds
Started Jul 29 08:04:28 PM PDT 24
Finished Jul 29 08:06:05 PM PDT 24
Peak memory 573996 kb
Host smart-389bef46-edb8-4715-8414-9e767228c358
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749689951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.2749689951
Directory /workspace/87.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.1312500413
Short name T1612
Test name
Test status
Simulation time 53512513 ps
CPU time 6.65 seconds
Started Jul 29 08:04:27 PM PDT 24
Finished Jul 29 08:04:34 PM PDT 24
Peak memory 573824 kb
Host smart-847609b8-a2f8-4cea-a971-eda394135411
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312500413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay
s.1312500413
Directory /workspace/87.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all.3300937628
Short name T1431
Test name
Test status
Simulation time 193816157 ps
CPU time 8.65 seconds
Started Jul 29 08:04:29 PM PDT 24
Finished Jul 29 08:04:38 PM PDT 24
Peak memory 574544 kb
Host smart-b2612a49-00a2-4c7b-a4c8-d8cc750f34af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300937628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.3300937628
Directory /workspace/87.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.3905438689
Short name T1605
Test name
Test status
Simulation time 1889373475 ps
CPU time 140.03 seconds
Started Jul 29 08:04:35 PM PDT 24
Finished Jul 29 08:06:55 PM PDT 24
Peak memory 576072 kb
Host smart-776563dc-33de-46f8-b7b0-f75db4f47860
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905438689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.3905438689
Directory /workspace/87.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.1498686840
Short name T2810
Test name
Test status
Simulation time 3615118981 ps
CPU time 392.62 seconds
Started Jul 29 08:04:37 PM PDT 24
Finished Jul 29 08:11:09 PM PDT 24
Peak memory 576036 kb
Host smart-7b0695db-3564-414e-bea5-456c76d3f3ae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498686840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all
_with_rand_reset.1498686840
Directory /workspace/87.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.4032188311
Short name T891
Test name
Test status
Simulation time 2354747191 ps
CPU time 279.59 seconds
Started Jul 29 08:04:35 PM PDT 24
Finished Jul 29 08:09:15 PM PDT 24
Peak memory 576840 kb
Host smart-994656b9-d189-44a6-ab5d-adfdcd476d12
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032188311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al
l_with_reset_error.4032188311
Directory /workspace/87.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.3721257147
Short name T1472
Test name
Test status
Simulation time 67731733 ps
CPU time 9.87 seconds
Started Jul 29 08:04:29 PM PDT 24
Finished Jul 29 08:04:39 PM PDT 24
Peak memory 575860 kb
Host smart-005df74f-eb60-4006-99f9-b8607789af70
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721257147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.3721257147
Directory /workspace/87.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_access_same_device.3335181772
Short name T2548
Test name
Test status
Simulation time 1309582299 ps
CPU time 47.69 seconds
Started Jul 29 08:04:42 PM PDT 24
Finished Jul 29 08:05:30 PM PDT 24
Peak memory 575884 kb
Host smart-c6dac0c9-d814-4a94-8d0b-3ac0bad92974
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335181772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device
.3335181772
Directory /workspace/88.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.3634289517
Short name T2738
Test name
Test status
Simulation time 126653382757 ps
CPU time 2211.09 seconds
Started Jul 29 08:04:42 PM PDT 24
Finished Jul 29 08:41:34 PM PDT 24
Peak memory 576132 kb
Host smart-a7049cab-86d1-471b-aae3-5013e697f2cf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634289517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_
device_slow_rsp.3634289517
Directory /workspace/88.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.367424083
Short name T2177
Test name
Test status
Simulation time 1108047205 ps
CPU time 43.52 seconds
Started Jul 29 08:04:44 PM PDT 24
Finished Jul 29 08:05:27 PM PDT 24
Peak memory 576036 kb
Host smart-5b69f850-b87d-43dc-8808-c96ef86605b5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367424083 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_addr
.367424083
Directory /workspace/88.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_error_random.1340903891
Short name T2363
Test name
Test status
Simulation time 1075902185 ps
CPU time 40.46 seconds
Started Jul 29 08:04:42 PM PDT 24
Finished Jul 29 08:05:23 PM PDT 24
Peak memory 575956 kb
Host smart-fcccf7d4-c67b-47b7-b050-a6fc56c7dd49
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340903891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.1340903891
Directory /workspace/88.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random.2399560345
Short name T2304
Test name
Test status
Simulation time 2267507628 ps
CPU time 76.08 seconds
Started Jul 29 08:04:36 PM PDT 24
Finished Jul 29 08:05:52 PM PDT 24
Peak memory 576144 kb
Host smart-889dfe56-3aac-4251-baaa-e2b0e76694bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399560345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.2399560345
Directory /workspace/88.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.3577029599
Short name T2461
Test name
Test status
Simulation time 99010594353 ps
CPU time 1009.73 seconds
Started Jul 29 08:04:35 PM PDT 24
Finished Jul 29 08:21:25 PM PDT 24
Peak memory 576108 kb
Host smart-8d302b08-7c48-4e17-8378-06ddf491b74c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577029599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.3577029599
Directory /workspace/88.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.4113357529
Short name T2107
Test name
Test status
Simulation time 60321631885 ps
CPU time 1073.7 seconds
Started Jul 29 08:04:36 PM PDT 24
Finished Jul 29 08:22:30 PM PDT 24
Peak memory 576000 kb
Host smart-aa8bbef5-2f85-4f3b-95d5-63778994921d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113357529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.4113357529
Directory /workspace/88.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.3738673546
Short name T673
Test name
Test status
Simulation time 97183530 ps
CPU time 11.63 seconds
Started Jul 29 08:04:37 PM PDT 24
Finished Jul 29 08:04:49 PM PDT 24
Peak memory 575920 kb
Host smart-2f3e99e7-01ff-4ac6-adf2-29ee980e0919
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738673546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del
ays.3738673546
Directory /workspace/88.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_same_source.1878767155
Short name T2146
Test name
Test status
Simulation time 1771847597 ps
CPU time 49.47 seconds
Started Jul 29 08:04:47 PM PDT 24
Finished Jul 29 08:05:36 PM PDT 24
Peak memory 575868 kb
Host smart-0d1401dd-4074-498b-9772-b8e5b28dcfbe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878767155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.1878767155
Directory /workspace/88.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke.3954661640
Short name T2283
Test name
Test status
Simulation time 48818966 ps
CPU time 6.26 seconds
Started Jul 29 08:04:35 PM PDT 24
Finished Jul 29 08:04:41 PM PDT 24
Peak memory 574036 kb
Host smart-7f4557f3-3b4d-44c0-9076-a865cb359081
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954661640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.3954661640
Directory /workspace/88.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.2140479835
Short name T1453
Test name
Test status
Simulation time 9361137232 ps
CPU time 94.91 seconds
Started Jul 29 08:04:37 PM PDT 24
Finished Jul 29 08:06:12 PM PDT 24
Peak memory 573920 kb
Host smart-f87dba0e-2758-4cea-8993-41b24c1a4eb4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140479835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.2140479835
Directory /workspace/88.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.1050319072
Short name T658
Test name
Test status
Simulation time 3778269084 ps
CPU time 61.75 seconds
Started Jul 29 08:04:38 PM PDT 24
Finished Jul 29 08:05:40 PM PDT 24
Peak memory 573964 kb
Host smart-de0f8456-f467-4588-ac9e-34ea9c4ac091
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050319072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.1050319072
Directory /workspace/88.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.172685205
Short name T2783
Test name
Test status
Simulation time 45596295 ps
CPU time 6.12 seconds
Started Jul 29 08:04:37 PM PDT 24
Finished Jul 29 08:04:43 PM PDT 24
Peak memory 573880 kb
Host smart-db6fe4ac-3d2c-4865-a2cb-269755b72126
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172685205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delays
.172685205
Directory /workspace/88.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all.4189753265
Short name T1819
Test name
Test status
Simulation time 3076414150 ps
CPU time 266.36 seconds
Started Jul 29 08:04:42 PM PDT 24
Finished Jul 29 08:09:08 PM PDT 24
Peak memory 575968 kb
Host smart-20657fb7-05e9-478d-a8a6-9660b9eadc18
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189753265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.4189753265
Directory /workspace/88.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.2504614377
Short name T2367
Test name
Test status
Simulation time 361250154 ps
CPU time 136.25 seconds
Started Jul 29 08:04:49 PM PDT 24
Finished Jul 29 08:07:06 PM PDT 24
Peak memory 575972 kb
Host smart-63b3aa86-1c5a-4223-84f9-db0016107723
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504614377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all
_with_rand_reset.2504614377
Directory /workspace/88.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.3088448824
Short name T651
Test name
Test status
Simulation time 10964560588 ps
CPU time 505.5 seconds
Started Jul 29 08:04:44 PM PDT 24
Finished Jul 29 08:13:09 PM PDT 24
Peak memory 576752 kb
Host smart-9dcc9c7c-0b09-4ac1-8546-d45983ae1c71
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088448824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al
l_with_reset_error.3088448824
Directory /workspace/88.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.1421206519
Short name T1620
Test name
Test status
Simulation time 1102512040 ps
CPU time 48.01 seconds
Started Jul 29 08:04:43 PM PDT 24
Finished Jul 29 08:05:32 PM PDT 24
Peak memory 576000 kb
Host smart-b93bb545-78dc-4cc2-92e7-7861450dd3ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421206519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.1421206519
Directory /workspace/88.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_access_same_device.2055858804
Short name T2734
Test name
Test status
Simulation time 2668110466 ps
CPU time 111.96 seconds
Started Jul 29 08:04:44 PM PDT 24
Finished Jul 29 08:06:36 PM PDT 24
Peak memory 575944 kb
Host smart-19b8c4ec-a710-40eb-9b16-9396bdf9fba3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055858804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device
.2055858804
Directory /workspace/89.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.1489132291
Short name T545
Test name
Test status
Simulation time 39381863083 ps
CPU time 699.55 seconds
Started Jul 29 08:04:49 PM PDT 24
Finished Jul 29 08:16:28 PM PDT 24
Peak memory 576116 kb
Host smart-2f4ac551-9e0f-4962-af6f-0553e67a987e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489132291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_
device_slow_rsp.1489132291
Directory /workspace/89.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.3343308132
Short name T2407
Test name
Test status
Simulation time 1485753169 ps
CPU time 59.25 seconds
Started Jul 29 08:04:44 PM PDT 24
Finished Jul 29 08:05:44 PM PDT 24
Peak memory 576016 kb
Host smart-a770333e-c3c3-49d8-8090-c62b6833f63d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343308132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add
r.3343308132
Directory /workspace/89.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_error_random.1469518437
Short name T2651
Test name
Test status
Simulation time 179057890 ps
CPU time 14.28 seconds
Started Jul 29 08:04:44 PM PDT 24
Finished Jul 29 08:04:58 PM PDT 24
Peak memory 576004 kb
Host smart-d2a56b96-3895-401d-a7be-8f569847391c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469518437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.1469518437
Directory /workspace/89.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random.2777306554
Short name T2104
Test name
Test status
Simulation time 40927007 ps
CPU time 6.46 seconds
Started Jul 29 08:04:44 PM PDT 24
Finished Jul 29 08:04:51 PM PDT 24
Peak memory 573888 kb
Host smart-3cd73efc-f9a3-4abc-930c-15d6f6f37bbc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777306554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.2777306554
Directory /workspace/89.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.3751872937
Short name T509
Test name
Test status
Simulation time 26239188733 ps
CPU time 288.83 seconds
Started Jul 29 08:04:43 PM PDT 24
Finished Jul 29 08:09:32 PM PDT 24
Peak memory 576116 kb
Host smart-77a3fb5a-3580-4248-8db6-310eb9cca61b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751872937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.3751872937
Directory /workspace/89.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.3397610637
Short name T2661
Test name
Test status
Simulation time 43334144294 ps
CPU time 750.13 seconds
Started Jul 29 08:04:50 PM PDT 24
Finished Jul 29 08:17:20 PM PDT 24
Peak memory 576036 kb
Host smart-b04cd4b3-a83f-4cec-97ad-1020097cc919
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397610637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.3397610637
Directory /workspace/89.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.3234166160
Short name T2841
Test name
Test status
Simulation time 430132071 ps
CPU time 34.6 seconds
Started Jul 29 08:04:48 PM PDT 24
Finished Jul 29 08:05:23 PM PDT 24
Peak memory 575988 kb
Host smart-7afe4157-568a-46dc-82ac-106e0feac635
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234166160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del
ays.3234166160
Directory /workspace/89.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_same_source.2219472364
Short name T451
Test name
Test status
Simulation time 578014986 ps
CPU time 39.18 seconds
Started Jul 29 08:04:49 PM PDT 24
Finished Jul 29 08:05:28 PM PDT 24
Peak memory 575816 kb
Host smart-f19e2d8f-ecb9-49e2-9417-0e6f6672730a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219472364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.2219472364
Directory /workspace/89.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke.2497637979
Short name T2241
Test name
Test status
Simulation time 48593991 ps
CPU time 6.42 seconds
Started Jul 29 08:04:42 PM PDT 24
Finished Jul 29 08:04:49 PM PDT 24
Peak memory 573856 kb
Host smart-0148c23d-7c4b-4a0e-a246-4b0af133d059
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497637979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.2497637979
Directory /workspace/89.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.91912895
Short name T1408
Test name
Test status
Simulation time 9226504158 ps
CPU time 88.9 seconds
Started Jul 29 08:04:49 PM PDT 24
Finished Jul 29 08:06:18 PM PDT 24
Peak memory 573884 kb
Host smart-34b5f378-883d-4a92-818f-f20bcf074f07
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91912895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.91912895
Directory /workspace/89.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.2870785765
Short name T2781
Test name
Test status
Simulation time 4866686032 ps
CPU time 80.93 seconds
Started Jul 29 08:04:44 PM PDT 24
Finished Jul 29 08:06:05 PM PDT 24
Peak memory 573880 kb
Host smart-28e70a5e-7fca-4568-bd76-a42f8431da0e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870785765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.2870785765
Directory /workspace/89.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.3762532407
Short name T1916
Test name
Test status
Simulation time 38244513 ps
CPU time 5.52 seconds
Started Jul 29 08:04:43 PM PDT 24
Finished Jul 29 08:04:48 PM PDT 24
Peak memory 573876 kb
Host smart-ad7df145-ac65-402b-9312-694892af8287
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762532407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay
s.3762532407
Directory /workspace/89.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all.327146324
Short name T2067
Test name
Test status
Simulation time 20170540886 ps
CPU time 665.48 seconds
Started Jul 29 08:04:49 PM PDT 24
Finished Jul 29 08:15:54 PM PDT 24
Peak memory 576872 kb
Host smart-ef1b4ef6-8d57-4a80-9bf0-243ff104bccc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327146324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.327146324
Directory /workspace/89.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.953399822
Short name T1636
Test name
Test status
Simulation time 4061452947 ps
CPU time 277.46 seconds
Started Jul 29 08:04:51 PM PDT 24
Finished Jul 29 08:09:28 PM PDT 24
Peak memory 576032 kb
Host smart-5d196599-fd6c-46f7-b921-ff45882885e0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953399822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.953399822
Directory /workspace/89.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.284597544
Short name T902
Test name
Test status
Simulation time 191011187 ps
CPU time 73.88 seconds
Started Jul 29 08:04:51 PM PDT 24
Finished Jul 29 08:06:05 PM PDT 24
Peak memory 575960 kb
Host smart-b190aaa9-0f7e-4672-9944-b4c251c4af34
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284597544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_
with_rand_reset.284597544
Directory /workspace/89.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.877130239
Short name T2683
Test name
Test status
Simulation time 9337311149 ps
CPU time 443.39 seconds
Started Jul 29 08:04:49 PM PDT 24
Finished Jul 29 08:12:13 PM PDT 24
Peak memory 576060 kb
Host smart-a44c37d2-7171-40c7-9fd8-80acfa4193cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877130239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all
_with_reset_error.877130239
Directory /workspace/89.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.2419827325
Short name T1800
Test name
Test status
Simulation time 179915973 ps
CPU time 21.91 seconds
Started Jul 29 08:04:42 PM PDT 24
Finished Jul 29 08:05:04 PM PDT 24
Peak memory 575932 kb
Host smart-259470c8-993b-486c-ad8e-3fcca4b2a6f0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419827325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.2419827325
Directory /workspace/89.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.114643340
Short name T2365
Test name
Test status
Simulation time 7494302980 ps
CPU time 517.12 seconds
Started Jul 29 07:50:21 PM PDT 24
Finished Jul 29 07:58:59 PM PDT 24
Peak memory 642712 kb
Host smart-c8741875-9623-4d2b-bdfd-6deff5b53f5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114643340 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.114643340
Directory /workspace/9.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.chip_csr_rw.3398100676
Short name T2562
Test name
Test status
Simulation time 4012942268 ps
CPU time 243.32 seconds
Started Jul 29 07:50:26 PM PDT 24
Finished Jul 29 07:54:30 PM PDT 24
Peak memory 599324 kb
Host smart-408c5e36-777e-4434-8b1b-aa5909fff74d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398100676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.3398100676
Directory /workspace/9.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.1718399998
Short name T457
Test name
Test status
Simulation time 30526685154 ps
CPU time 4040.06 seconds
Started Jul 29 07:50:27 PM PDT 24
Finished Jul 29 08:57:48 PM PDT 24
Peak memory 593308 kb
Host smart-9f341e5a-bb84-4952-bd4f-93202c8f46dc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718399998 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.1718399998
Directory /workspace/9.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.chip_tl_errors.4167002605
Short name T559
Test name
Test status
Simulation time 3621752988 ps
CPU time 185.31 seconds
Started Jul 29 07:50:20 PM PDT 24
Finished Jul 29 07:53:25 PM PDT 24
Peak memory 603688 kb
Host smart-53067f36-be2d-4bfd-a19f-2f1a202a1682
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167002605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.4167002605
Directory /workspace/9.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_access_same_device.4208105569
Short name T1551
Test name
Test status
Simulation time 380778978 ps
CPU time 19.17 seconds
Started Jul 29 07:50:25 PM PDT 24
Finished Jul 29 07:50:45 PM PDT 24
Peak memory 575812 kb
Host smart-d4b3e1a3-e01b-4239-9988-bfdede946f9e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208105569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.
4208105569
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2772061879
Short name T849
Test name
Test status
Simulation time 128067056108 ps
CPU time 2091.54 seconds
Started Jul 29 07:50:19 PM PDT 24
Finished Jul 29 08:25:11 PM PDT 24
Peak memory 575832 kb
Host smart-18b8fa67-564a-4bf7-bdeb-d448ea5afa61
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772061879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d
evice_slow_rsp.2772061879
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.1462440152
Short name T1892
Test name
Test status
Simulation time 1064859345 ps
CPU time 40.08 seconds
Started Jul 29 07:50:25 PM PDT 24
Finished Jul 29 07:51:05 PM PDT 24
Peak memory 575832 kb
Host smart-fb1da497-7a15-4f2c-9d43-47e1e802a140
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462440152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr
.1462440152
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_error_random.3395649473
Short name T1471
Test name
Test status
Simulation time 72762851 ps
CPU time 7.98 seconds
Started Jul 29 07:50:27 PM PDT 24
Finished Jul 29 07:50:35 PM PDT 24
Peak memory 576004 kb
Host smart-a67e113d-60ae-4d09-9d32-4cb5d65661a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395649473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3395649473
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random.755902342
Short name T2936
Test name
Test status
Simulation time 2323601833 ps
CPU time 81.05 seconds
Started Jul 29 07:50:21 PM PDT 24
Finished Jul 29 07:51:42 PM PDT 24
Peak memory 576204 kb
Host smart-3a401dc0-9779-4896-9539-182cecba6cda
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755902342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.755902342
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.89296219
Short name T1462
Test name
Test status
Simulation time 11176690122 ps
CPU time 114.28 seconds
Started Jul 29 07:50:09 PM PDT 24
Finished Jul 29 07:52:04 PM PDT 24
Peak memory 576036 kb
Host smart-86e59406-b74a-4556-87b8-0c7183d77684
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89296219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.89296219
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.2658610771
Short name T574
Test name
Test status
Simulation time 18704255803 ps
CPU time 305.71 seconds
Started Jul 29 07:50:27 PM PDT 24
Finished Jul 29 07:55:33 PM PDT 24
Peak memory 575904 kb
Host smart-45067dc4-8e3c-4b20-94da-fd32b344d9a6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658610771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2658610771
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.4110769502
Short name T2075
Test name
Test status
Simulation time 575636175 ps
CPU time 53.01 seconds
Started Jul 29 07:50:21 PM PDT 24
Finished Jul 29 07:51:14 PM PDT 24
Peak memory 575948 kb
Host smart-bacee818-6dea-469e-b217-083e4b9c8a60
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110769502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela
ys.4110769502
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_same_source.2627312494
Short name T2202
Test name
Test status
Simulation time 640321134 ps
CPU time 18.76 seconds
Started Jul 29 07:50:21 PM PDT 24
Finished Jul 29 07:50:40 PM PDT 24
Peak memory 575772 kb
Host smart-efa9f2a5-6af3-41d5-a737-2624f7b5fb98
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627312494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2627312494
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke.2806981090
Short name T2807
Test name
Test status
Simulation time 36861699 ps
CPU time 5.39 seconds
Started Jul 29 07:50:12 PM PDT 24
Finished Jul 29 07:50:18 PM PDT 24
Peak memory 574532 kb
Host smart-1ea65cdf-66a6-4e04-926e-8355899d6b1d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806981090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2806981090
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.3157118276
Short name T1400
Test name
Test status
Simulation time 8043269833 ps
CPU time 80.81 seconds
Started Jul 29 07:50:25 PM PDT 24
Finished Jul 29 07:51:46 PM PDT 24
Peak memory 573992 kb
Host smart-7497fb97-f7cc-4b50-b4ee-bb3a92368d3b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157118276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3157118276
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.4214634386
Short name T547
Test name
Test status
Simulation time 4611268554 ps
CPU time 73.71 seconds
Started Jul 29 07:50:20 PM PDT 24
Finished Jul 29 07:51:34 PM PDT 24
Peak memory 573872 kb
Host smart-ee7d0616-6a4e-4c05-9beb-3ebccb1eac7e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214634386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.4214634386
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.125604404
Short name T1640
Test name
Test status
Simulation time 52138163 ps
CPU time 6.89 seconds
Started Jul 29 07:50:13 PM PDT 24
Finished Jul 29 07:50:20 PM PDT 24
Peak memory 573880 kb
Host smart-0d24a198-b63d-47cb-b0c6-6e6bea6d097a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125604404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.
125604404
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all.1528147492
Short name T1997
Test name
Test status
Simulation time 8113560449 ps
CPU time 284.84 seconds
Started Jul 29 07:50:22 PM PDT 24
Finished Jul 29 07:55:07 PM PDT 24
Peak memory 576908 kb
Host smart-0028d0c9-9dcd-4662-a7a5-b1bdb90dfc44
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528147492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1528147492
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.3418222722
Short name T2298
Test name
Test status
Simulation time 2866931181 ps
CPU time 91.07 seconds
Started Jul 29 07:50:20 PM PDT 24
Finished Jul 29 07:51:51 PM PDT 24
Peak memory 576208 kb
Host smart-01c483e1-d27c-4be4-aa5f-7a5b3fb21453
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418222722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3418222722
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.3602578009
Short name T472
Test name
Test status
Simulation time 7878279002 ps
CPU time 473.41 seconds
Started Jul 29 07:50:21 PM PDT 24
Finished Jul 29 07:58:14 PM PDT 24
Peak memory 576808 kb
Host smart-29947930-fd47-43b3-a664-7b88c0a70c02
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602578009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_
with_rand_reset.3602578009
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.3821000004
Short name T2753
Test name
Test status
Simulation time 13897344366 ps
CPU time 644.97 seconds
Started Jul 29 07:50:27 PM PDT 24
Finished Jul 29 08:01:12 PM PDT 24
Peak memory 576868 kb
Host smart-3e5e7afe-a6b3-4565-aaeb-ab5ed5673d93
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821000004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all
_with_reset_error.3821000004
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.2161525851
Short name T2056
Test name
Test status
Simulation time 32854179 ps
CPU time 6.45 seconds
Started Jul 29 07:50:14 PM PDT 24
Finished Jul 29 07:50:20 PM PDT 24
Peak memory 574076 kb
Host smart-41487e2a-26c7-4b86-9058-a1b5174bf670
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161525851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2161525851
Directory /workspace/9.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_access_same_device.1038164784
Short name T1688
Test name
Test status
Simulation time 3267910368 ps
CPU time 115.69 seconds
Started Jul 29 08:04:56 PM PDT 24
Finished Jul 29 08:06:52 PM PDT 24
Peak memory 575900 kb
Host smart-19066695-fe41-4402-a56e-5d34ffde6b36
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038164784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device
.1038164784
Directory /workspace/90.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.1435081638
Short name T2573
Test name
Test status
Simulation time 161547656160 ps
CPU time 3132.16 seconds
Started Jul 29 08:04:58 PM PDT 24
Finished Jul 29 08:57:11 PM PDT 24
Peak memory 576124 kb
Host smart-5aaefc95-6a44-48f0-a139-9776ebb02827
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435081638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_
device_slow_rsp.1435081638
Directory /workspace/90.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.1460838729
Short name T2645
Test name
Test status
Simulation time 284801625 ps
CPU time 29.85 seconds
Started Jul 29 08:05:00 PM PDT 24
Finished Jul 29 08:05:30 PM PDT 24
Peak memory 575764 kb
Host smart-bad42e17-c36a-4245-9d74-6a4bc2a077d2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460838729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add
r.1460838729
Directory /workspace/90.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_error_random.835934010
Short name T1808
Test name
Test status
Simulation time 90670031 ps
CPU time 9.94 seconds
Started Jul 29 08:04:59 PM PDT 24
Finished Jul 29 08:05:09 PM PDT 24
Peak memory 575972 kb
Host smart-3dd4bfa8-425b-40b5-b124-496483b9ff25
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835934010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.835934010
Directory /workspace/90.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random.3132200101
Short name T2526
Test name
Test status
Simulation time 371949050 ps
CPU time 35.29 seconds
Started Jul 29 08:04:49 PM PDT 24
Finished Jul 29 08:05:24 PM PDT 24
Peak memory 575872 kb
Host smart-8d6ac040-e2ad-405a-9186-ec8297459e04
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132200101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.3132200101
Directory /workspace/90.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.3272604241
Short name T2050
Test name
Test status
Simulation time 32396887061 ps
CPU time 327.83 seconds
Started Jul 29 08:04:50 PM PDT 24
Finished Jul 29 08:10:18 PM PDT 24
Peak memory 575972 kb
Host smart-52db62b9-1084-460e-8e15-fbaa01645956
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272604241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.3272604241
Directory /workspace/90.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.472409371
Short name T2213
Test name
Test status
Simulation time 62820912290 ps
CPU time 1118.04 seconds
Started Jul 29 08:04:51 PM PDT 24
Finished Jul 29 08:23:29 PM PDT 24
Peak memory 576060 kb
Host smart-24076247-0a2f-4b2b-947a-924f3a77171b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472409371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.472409371
Directory /workspace/90.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.37424531
Short name T591
Test name
Test status
Simulation time 421354366 ps
CPU time 37.09 seconds
Started Jul 29 08:04:51 PM PDT 24
Finished Jul 29 08:05:28 PM PDT 24
Peak memory 575940 kb
Host smart-21701ebf-822a-4c49-ad26-cc3722f29818
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37424531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_delay
s.37424531
Directory /workspace/90.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_same_source.2603304731
Short name T2642
Test name
Test status
Simulation time 404421460 ps
CPU time 28.3 seconds
Started Jul 29 08:04:57 PM PDT 24
Finished Jul 29 08:05:26 PM PDT 24
Peak memory 575972 kb
Host smart-aa5d3d7e-642e-4a9d-be1a-d6135ec3766d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603304731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.2603304731
Directory /workspace/90.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke.659795498
Short name T1763
Test name
Test status
Simulation time 191532768 ps
CPU time 8.64 seconds
Started Jul 29 08:04:50 PM PDT 24
Finished Jul 29 08:04:59 PM PDT 24
Peak memory 573828 kb
Host smart-2292da91-66cc-4bbb-b2d1-d200fb6cbdd0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659795498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.659795498
Directory /workspace/90.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.2827612860
Short name T2128
Test name
Test status
Simulation time 4899400492 ps
CPU time 48.82 seconds
Started Jul 29 08:04:56 PM PDT 24
Finished Jul 29 08:05:45 PM PDT 24
Peak memory 574592 kb
Host smart-998a53a1-d487-44da-99ed-dc964c337512
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827612860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.2827612860
Directory /workspace/90.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.1307061461
Short name T1927
Test name
Test status
Simulation time 5846456883 ps
CPU time 92.53 seconds
Started Jul 29 08:04:50 PM PDT 24
Finished Jul 29 08:06:22 PM PDT 24
Peak memory 573988 kb
Host smart-7d743f28-fadb-44ce-b174-7748d5b3ae3f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307061461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.1307061461
Directory /workspace/90.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2053517643
Short name T2691
Test name
Test status
Simulation time 57033334 ps
CPU time 7.4 seconds
Started Jul 29 08:04:50 PM PDT 24
Finished Jul 29 08:04:58 PM PDT 24
Peak memory 574532 kb
Host smart-82d72420-ae94-4f6b-8eac-09733db522c6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053517643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay
s.2053517643
Directory /workspace/90.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all.951120264
Short name T2375
Test name
Test status
Simulation time 14910840320 ps
CPU time 500.48 seconds
Started Jul 29 08:04:57 PM PDT 24
Finished Jul 29 08:13:18 PM PDT 24
Peak memory 576212 kb
Host smart-5cfe4a77-629f-4f7b-8509-6028715c9325
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951120264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.951120264
Directory /workspace/90.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.2874632708
Short name T1685
Test name
Test status
Simulation time 5493543498 ps
CPU time 349.67 seconds
Started Jul 29 08:04:56 PM PDT 24
Finished Jul 29 08:10:46 PM PDT 24
Peak memory 576220 kb
Host smart-521d874c-7461-4d9d-8905-37395fe69266
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874632708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.2874632708
Directory /workspace/90.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.2309080750
Short name T2496
Test name
Test status
Simulation time 70721726 ps
CPU time 19.76 seconds
Started Jul 29 08:04:56 PM PDT 24
Finished Jul 29 08:05:16 PM PDT 24
Peak memory 575968 kb
Host smart-4b9bc157-f6a2-4c69-b42a-933651bc12b6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309080750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all
_with_rand_reset.2309080750
Directory /workspace/90.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.4110798333
Short name T2748
Test name
Test status
Simulation time 861692654 ps
CPU time 35.33 seconds
Started Jul 29 08:04:58 PM PDT 24
Finished Jul 29 08:05:33 PM PDT 24
Peak memory 575984 kb
Host smart-eead22e6-97e5-4867-be23-874615e89527
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110798333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.4110798333
Directory /workspace/90.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_access_same_device.3575113604
Short name T2081
Test name
Test status
Simulation time 997543570 ps
CPU time 69.98 seconds
Started Jul 29 08:05:02 PM PDT 24
Finished Jul 29 08:06:12 PM PDT 24
Peak memory 575988 kb
Host smart-5c4c7545-1859-4af8-aa1f-28601dd34210
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575113604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device
.3575113604
Directory /workspace/91.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.3126186066
Short name T1697
Test name
Test status
Simulation time 25116963480 ps
CPU time 406.37 seconds
Started Jul 29 08:05:04 PM PDT 24
Finished Jul 29 08:11:50 PM PDT 24
Peak memory 576136 kb
Host smart-73b6d818-1b53-4bd8-9a56-d602c177e015
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126186066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_
device_slow_rsp.3126186066
Directory /workspace/91.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.1988878319
Short name T2206
Test name
Test status
Simulation time 1248094426 ps
CPU time 51.11 seconds
Started Jul 29 08:05:09 PM PDT 24
Finished Jul 29 08:06:00 PM PDT 24
Peak memory 576024 kb
Host smart-b6cd3333-d736-44bd-bc09-01cfec71028e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988878319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add
r.1988878319
Directory /workspace/91.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_error_random.3960124238
Short name T2174
Test name
Test status
Simulation time 1179466231 ps
CPU time 39.78 seconds
Started Jul 29 08:05:10 PM PDT 24
Finished Jul 29 08:05:49 PM PDT 24
Peak memory 575988 kb
Host smart-013fd5c3-1087-47d6-b96a-2a7476941beb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960124238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.3960124238
Directory /workspace/91.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random.2623990288
Short name T629
Test name
Test status
Simulation time 2200059001 ps
CPU time 77.47 seconds
Started Jul 29 08:05:07 PM PDT 24
Finished Jul 29 08:06:25 PM PDT 24
Peak memory 576024 kb
Host smart-05b874aa-adbd-47c7-9a44-b82d933fdb9b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623990288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.2623990288
Directory /workspace/91.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.2593467263
Short name T2341
Test name
Test status
Simulation time 98869007420 ps
CPU time 1125.23 seconds
Started Jul 29 08:05:04 PM PDT 24
Finished Jul 29 08:23:50 PM PDT 24
Peak memory 576096 kb
Host smart-4033e7dc-e413-45bd-9879-45e22762e69b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593467263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.2593467263
Directory /workspace/91.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.1645060912
Short name T2324
Test name
Test status
Simulation time 38758422271 ps
CPU time 654.33 seconds
Started Jul 29 08:05:02 PM PDT 24
Finished Jul 29 08:15:57 PM PDT 24
Peak memory 576092 kb
Host smart-aeaac8d7-b668-49c1-b063-e87ec9f0d1b5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645060912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.1645060912
Directory /workspace/91.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.219718233
Short name T514
Test name
Test status
Simulation time 327986573 ps
CPU time 33.07 seconds
Started Jul 29 08:05:03 PM PDT 24
Finished Jul 29 08:05:36 PM PDT 24
Peak memory 575932 kb
Host smart-2e0e08ef-365c-4319-b6df-fb0e757214c6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219718233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_dela
ys.219718233
Directory /workspace/91.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_same_source.305786129
Short name T520
Test name
Test status
Simulation time 2223539227 ps
CPU time 62.31 seconds
Started Jul 29 08:05:02 PM PDT 24
Finished Jul 29 08:06:05 PM PDT 24
Peak memory 576004 kb
Host smart-e83e1eef-6324-4223-baba-6064f94b0775
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305786129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.305786129
Directory /workspace/91.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke.84932868
Short name T2369
Test name
Test status
Simulation time 55128360 ps
CPU time 6.69 seconds
Started Jul 29 08:05:21 PM PDT 24
Finished Jul 29 08:05:27 PM PDT 24
Peak memory 573904 kb
Host smart-fa73ccd4-38e7-44e4-9bb2-1487236652bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84932868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.84932868
Directory /workspace/91.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.1228657678
Short name T2593
Test name
Test status
Simulation time 6767577241 ps
CPU time 68.86 seconds
Started Jul 29 08:05:03 PM PDT 24
Finished Jul 29 08:06:12 PM PDT 24
Peak memory 573992 kb
Host smart-b26e3c11-433b-4bec-a398-af128ce14f47
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228657678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.1228657678
Directory /workspace/91.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.2538212595
Short name T1669
Test name
Test status
Simulation time 5881484760 ps
CPU time 103.42 seconds
Started Jul 29 08:05:04 PM PDT 24
Finished Jul 29 08:06:47 PM PDT 24
Peak memory 573980 kb
Host smart-067411e0-d4ce-4d14-8683-b9cb32fa3f60
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538212595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.2538212595
Directory /workspace/91.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.2587007664
Short name T1596
Test name
Test status
Simulation time 53306985 ps
CPU time 6.18 seconds
Started Jul 29 08:05:03 PM PDT 24
Finished Jul 29 08:05:09 PM PDT 24
Peak memory 573884 kb
Host smart-eacee84d-aab0-40ef-b5ad-edba8c090789
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587007664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay
s.2587007664
Directory /workspace/91.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all.679465100
Short name T1989
Test name
Test status
Simulation time 2596105243 ps
CPU time 94.51 seconds
Started Jul 29 08:05:14 PM PDT 24
Finished Jul 29 08:06:49 PM PDT 24
Peak memory 576052 kb
Host smart-ceb9d272-b879-45a9-ba95-e2774a30eb78
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679465100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.679465100
Directory /workspace/91.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.812415335
Short name T1647
Test name
Test status
Simulation time 280639229 ps
CPU time 26.79 seconds
Started Jul 29 08:05:10 PM PDT 24
Finished Jul 29 08:05:37 PM PDT 24
Peak memory 575856 kb
Host smart-72fbb286-96b6-4440-9aa4-3249df00c28a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812415335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.812415335
Directory /workspace/91.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.2233391189
Short name T2888
Test name
Test status
Simulation time 7110096186 ps
CPU time 519.74 seconds
Started Jul 29 08:05:11 PM PDT 24
Finished Jul 29 08:13:51 PM PDT 24
Peak memory 576860 kb
Host smart-8c602803-ffcd-4939-a98c-ae52dc272919
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233391189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all
_with_rand_reset.2233391189
Directory /workspace/91.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.2276315230
Short name T2009
Test name
Test status
Simulation time 1343618817 ps
CPU time 197.64 seconds
Started Jul 29 08:05:14 PM PDT 24
Finished Jul 29 08:08:31 PM PDT 24
Peak memory 576800 kb
Host smart-a80efc18-8f46-4f69-a908-3071bbc9170a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276315230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al
l_with_reset_error.2276315230
Directory /workspace/91.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.3004446582
Short name T1476
Test name
Test status
Simulation time 616972563 ps
CPU time 27.48 seconds
Started Jul 29 08:05:04 PM PDT 24
Finished Jul 29 08:05:32 PM PDT 24
Peak memory 575988 kb
Host smart-9795f1c6-353e-4c1d-b47d-7b95dd3055c3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004446582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.3004446582
Directory /workspace/91.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_access_same_device.2002000399
Short name T490
Test name
Test status
Simulation time 786459667 ps
CPU time 55.69 seconds
Started Jul 29 08:05:17 PM PDT 24
Finished Jul 29 08:06:13 PM PDT 24
Peak memory 575916 kb
Host smart-a7a9f559-8758-455d-9d6f-bd66535a5141
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002000399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device
.2002000399
Directory /workspace/92.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.2225008434
Short name T2230
Test name
Test status
Simulation time 935819726 ps
CPU time 34.51 seconds
Started Jul 29 08:05:19 PM PDT 24
Finished Jul 29 08:05:54 PM PDT 24
Peak memory 576164 kb
Host smart-8406f2c5-5915-4f17-b406-58c4fdd1800b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225008434 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add
r.2225008434
Directory /workspace/92.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_error_random.2037736997
Short name T1556
Test name
Test status
Simulation time 385844906 ps
CPU time 16.46 seconds
Started Jul 29 08:05:18 PM PDT 24
Finished Jul 29 08:05:34 PM PDT 24
Peak memory 576004 kb
Host smart-8aca771a-8622-4ab7-8dee-42b9312dc4cc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037736997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.2037736997
Directory /workspace/92.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random.1042497798
Short name T2518
Test name
Test status
Simulation time 2057388253 ps
CPU time 74.22 seconds
Started Jul 29 08:05:12 PM PDT 24
Finished Jul 29 08:06:26 PM PDT 24
Peak memory 575872 kb
Host smart-d52249bd-b905-47a1-94fa-240516605959
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042497798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.1042497798
Directory /workspace/92.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.1084720168
Short name T1681
Test name
Test status
Simulation time 107968739065 ps
CPU time 1049.1 seconds
Started Jul 29 08:05:18 PM PDT 24
Finished Jul 29 08:22:48 PM PDT 24
Peak memory 575936 kb
Host smart-f958d03f-0996-4670-b99e-f0235e569fc5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084720168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.1084720168
Directory /workspace/92.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.362207179
Short name T2323
Test name
Test status
Simulation time 50459562313 ps
CPU time 874.85 seconds
Started Jul 29 08:05:17 PM PDT 24
Finished Jul 29 08:19:52 PM PDT 24
Peak memory 575920 kb
Host smart-5adc7747-2a7b-4cc5-a28d-bcc4d9764b81
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362207179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.362207179
Directory /workspace/92.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.4040208873
Short name T2704
Test name
Test status
Simulation time 60628191 ps
CPU time 7.26 seconds
Started Jul 29 08:05:10 PM PDT 24
Finished Jul 29 08:05:18 PM PDT 24
Peak memory 575768 kb
Host smart-3ed45146-6857-4590-9b64-e5e80788cc1b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040208873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del
ays.4040208873
Directory /workspace/92.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_same_source.2972448985
Short name T2102
Test name
Test status
Simulation time 391376014 ps
CPU time 28.53 seconds
Started Jul 29 08:05:16 PM PDT 24
Finished Jul 29 08:05:45 PM PDT 24
Peak memory 575964 kb
Host smart-57d752c6-b37e-44f9-8206-def1cdaafba6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972448985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.2972448985
Directory /workspace/92.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke.788402506
Short name T1963
Test name
Test status
Simulation time 226072563 ps
CPU time 8.78 seconds
Started Jul 29 08:05:15 PM PDT 24
Finished Jul 29 08:05:24 PM PDT 24
Peak memory 573912 kb
Host smart-4ca98e9e-1546-4419-b338-04849e579b1e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788402506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.788402506
Directory /workspace/92.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.1134292000
Short name T1720
Test name
Test status
Simulation time 7577586575 ps
CPU time 77 seconds
Started Jul 29 08:05:13 PM PDT 24
Finished Jul 29 08:06:31 PM PDT 24
Peak memory 573920 kb
Host smart-25a7e840-6b4b-4cd5-86aa-def0f388bf42
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134292000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.1134292000
Directory /workspace/92.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.3345645504
Short name T2858
Test name
Test status
Simulation time 5030913030 ps
CPU time 79.86 seconds
Started Jul 29 08:05:13 PM PDT 24
Finished Jul 29 08:06:33 PM PDT 24
Peak memory 573976 kb
Host smart-8c5e4d47-2519-40ed-9b56-6e011f2f9353
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345645504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.3345645504
Directory /workspace/92.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.670472839
Short name T2878
Test name
Test status
Simulation time 49648975 ps
CPU time 5.98 seconds
Started Jul 29 08:05:10 PM PDT 24
Finished Jul 29 08:05:16 PM PDT 24
Peak memory 573652 kb
Host smart-5baa26af-693e-4982-b02c-4ec74cf23f8f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670472839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delays
.670472839
Directory /workspace/92.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all.3371160292
Short name T2495
Test name
Test status
Simulation time 4981413028 ps
CPU time 207.58 seconds
Started Jul 29 08:05:16 PM PDT 24
Finished Jul 29 08:08:44 PM PDT 24
Peak memory 576836 kb
Host smart-bd391a1c-3535-483a-ad06-5c5ec8d71c24
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371160292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.3371160292
Directory /workspace/92.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.4085144448
Short name T2787
Test name
Test status
Simulation time 9373470217 ps
CPU time 317.02 seconds
Started Jul 29 08:05:19 PM PDT 24
Finished Jul 29 08:10:36 PM PDT 24
Peak memory 576924 kb
Host smart-4893591b-7f83-4058-8255-aa86a447bb7a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085144448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.4085144448
Directory /workspace/92.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.461470890
Short name T2225
Test name
Test status
Simulation time 8037846376 ps
CPU time 562.1 seconds
Started Jul 29 08:05:17 PM PDT 24
Finished Jul 29 08:14:40 PM PDT 24
Peak memory 576640 kb
Host smart-a247aeae-5ecc-4f89-a7de-f8bb4b7c24d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461470890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_
with_rand_reset.461470890
Directory /workspace/92.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.3193227852
Short name T2784
Test name
Test status
Simulation time 19091475000 ps
CPU time 708.69 seconds
Started Jul 29 08:05:18 PM PDT 24
Finished Jul 29 08:17:07 PM PDT 24
Peak memory 576860 kb
Host smart-9e63d551-2168-40fb-bfe2-b47d4d779751
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193227852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al
l_with_reset_error.3193227852
Directory /workspace/92.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.645218098
Short name T2625
Test name
Test status
Simulation time 1331440823 ps
CPU time 52.76 seconds
Started Jul 29 08:05:16 PM PDT 24
Finished Jul 29 08:06:09 PM PDT 24
Peak memory 576072 kb
Host smart-ef712253-73ec-417c-abd8-1cca15f0bb08
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645218098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.645218098
Directory /workspace/92.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_access_same_device.359110426
Short name T847
Test name
Test status
Simulation time 2320195995 ps
CPU time 90.26 seconds
Started Jul 29 08:05:23 PM PDT 24
Finished Jul 29 08:06:54 PM PDT 24
Peak memory 576060 kb
Host smart-048786c7-b59e-4d56-ac1e-95b5a473c126
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359110426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device.
359110426
Directory /workspace/93.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.4068482637
Short name T2189
Test name
Test status
Simulation time 104635469368 ps
CPU time 1897.08 seconds
Started Jul 29 08:05:24 PM PDT 24
Finished Jul 29 08:37:02 PM PDT 24
Peak memory 576140 kb
Host smart-27ddc31c-21d8-4534-9e50-a9a69009436c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068482637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_
device_slow_rsp.4068482637
Directory /workspace/93.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.3964166067
Short name T2770
Test name
Test status
Simulation time 1070080749 ps
CPU time 41.24 seconds
Started Jul 29 08:05:23 PM PDT 24
Finished Jul 29 08:06:05 PM PDT 24
Peak memory 575916 kb
Host smart-2d85869d-d8d4-4553-8a69-d7b84d45db10
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964166067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add
r.3964166067
Directory /workspace/93.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_error_random.2099211150
Short name T2160
Test name
Test status
Simulation time 440767823 ps
CPU time 37.4 seconds
Started Jul 29 08:05:25 PM PDT 24
Finished Jul 29 08:06:02 PM PDT 24
Peak memory 575712 kb
Host smart-9cf2ccbe-fc25-491a-a8e3-7e0cf95bd857
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099211150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.2099211150
Directory /workspace/93.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random.3013062575
Short name T581
Test name
Test status
Simulation time 2293774830 ps
CPU time 79.07 seconds
Started Jul 29 08:05:18 PM PDT 24
Finished Jul 29 08:06:38 PM PDT 24
Peak memory 575828 kb
Host smart-d83dae82-d7bc-49c6-bf26-d546f5b43004
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013062575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.3013062575
Directory /workspace/93.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.1132336261
Short name T2193
Test name
Test status
Simulation time 25630457591 ps
CPU time 267.7 seconds
Started Jul 29 08:05:24 PM PDT 24
Finished Jul 29 08:09:52 PM PDT 24
Peak memory 576108 kb
Host smart-8debabb4-c58d-4def-b7a5-dda0278f16d9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132336261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.1132336261
Directory /workspace/93.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.3023614850
Short name T1737
Test name
Test status
Simulation time 52575706986 ps
CPU time 954.47 seconds
Started Jul 29 08:05:24 PM PDT 24
Finished Jul 29 08:21:18 PM PDT 24
Peak memory 576060 kb
Host smart-37c8aabb-7fb4-4e4f-809a-176fa78b3d3e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023614850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.3023614850
Directory /workspace/93.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.972980973
Short name T1577
Test name
Test status
Simulation time 77209715 ps
CPU time 9.06 seconds
Started Jul 29 08:05:17 PM PDT 24
Finished Jul 29 08:05:26 PM PDT 24
Peak memory 575980 kb
Host smart-9bc9a6c5-78b5-4ee1-a9cd-1da320caef0a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972980973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_dela
ys.972980973
Directory /workspace/93.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_same_source.209203009
Short name T2329
Test name
Test status
Simulation time 2405409553 ps
CPU time 71.08 seconds
Started Jul 29 08:05:27 PM PDT 24
Finished Jul 29 08:06:38 PM PDT 24
Peak memory 575912 kb
Host smart-3bb2fe9a-751d-48c8-b380-38b78e2a90ed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209203009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.209203009
Directory /workspace/93.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke.1564810936
Short name T1756
Test name
Test status
Simulation time 242553643 ps
CPU time 9.42 seconds
Started Jul 29 08:05:22 PM PDT 24
Finished Jul 29 08:05:32 PM PDT 24
Peak memory 574548 kb
Host smart-ffcb026f-39cd-4f8d-8112-dcb372e207aa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564810936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.1564810936
Directory /workspace/93.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.191340161
Short name T1834
Test name
Test status
Simulation time 9018989027 ps
CPU time 91.15 seconds
Started Jul 29 08:05:18 PM PDT 24
Finished Jul 29 08:06:49 PM PDT 24
Peak memory 573984 kb
Host smart-724b8792-31e7-492e-9349-672a323a9bdb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191340161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.191340161
Directory /workspace/93.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.2189234731
Short name T1938
Test name
Test status
Simulation time 5469561571 ps
CPU time 91.25 seconds
Started Jul 29 08:05:16 PM PDT 24
Finished Jul 29 08:06:47 PM PDT 24
Peak memory 574104 kb
Host smart-c7890b56-dfb9-4975-b50c-7117d7ffa497
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189234731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.2189234731
Directory /workspace/93.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.1747510778
Short name T2254
Test name
Test status
Simulation time 50607090 ps
CPU time 6.31 seconds
Started Jul 29 08:05:19 PM PDT 24
Finished Jul 29 08:05:26 PM PDT 24
Peak memory 573888 kb
Host smart-15acf3b8-bcfe-42c5-8258-74ebd0643194
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747510778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay
s.1747510778
Directory /workspace/93.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all.1770400639
Short name T680
Test name
Test status
Simulation time 11739304091 ps
CPU time 427.37 seconds
Started Jul 29 08:05:23 PM PDT 24
Finished Jul 29 08:12:31 PM PDT 24
Peak memory 576260 kb
Host smart-17fe8cd8-48c4-462f-8a3a-2b834b4927fd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770400639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.1770400639
Directory /workspace/93.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.1218560943
Short name T2024
Test name
Test status
Simulation time 10066411532 ps
CPU time 329.55 seconds
Started Jul 29 08:05:25 PM PDT 24
Finished Jul 29 08:10:55 PM PDT 24
Peak memory 576796 kb
Host smart-94b19985-23e7-4c7f-81a3-cd1744a99571
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218560943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.1218560943
Directory /workspace/93.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1207518838
Short name T1970
Test name
Test status
Simulation time 938255014 ps
CPU time 316.12 seconds
Started Jul 29 08:05:24 PM PDT 24
Finished Jul 29 08:10:40 PM PDT 24
Peak memory 575956 kb
Host smart-316763cb-4250-46bf-a967-03dd52ee1450
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207518838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all
_with_rand_reset.1207518838
Directory /workspace/93.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.3567379995
Short name T2477
Test name
Test status
Simulation time 9104890226 ps
CPU time 424.22 seconds
Started Jul 29 08:05:24 PM PDT 24
Finished Jul 29 08:12:28 PM PDT 24
Peak memory 576804 kb
Host smart-5b3ea8a1-31d8-425b-96b0-79409ce4ed04
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567379995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al
l_with_reset_error.3567379995
Directory /workspace/93.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.1761248712
Short name T2238
Test name
Test status
Simulation time 54334525 ps
CPU time 8.16 seconds
Started Jul 29 08:05:26 PM PDT 24
Finished Jul 29 08:05:35 PM PDT 24
Peak memory 576132 kb
Host smart-c5acbf7f-c911-4526-be3c-8f7a6ab70ca0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761248712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.1761248712
Directory /workspace/93.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_access_same_device.3602260076
Short name T589
Test name
Test status
Simulation time 891345395 ps
CPU time 63.8 seconds
Started Jul 29 08:05:36 PM PDT 24
Finished Jul 29 08:06:39 PM PDT 24
Peak memory 575844 kb
Host smart-20648040-45f0-417a-95b8-ff693c444e93
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602260076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device
.3602260076
Directory /workspace/94.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.2140673379
Short name T1818
Test name
Test status
Simulation time 69804283917 ps
CPU time 1288.05 seconds
Started Jul 29 08:05:32 PM PDT 24
Finished Jul 29 08:27:00 PM PDT 24
Peak memory 576120 kb
Host smart-ced212f8-2375-48b9-8073-2c3a228ed40b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140673379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_
device_slow_rsp.2140673379
Directory /workspace/94.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.1809742887
Short name T2844
Test name
Test status
Simulation time 338250060 ps
CPU time 37.69 seconds
Started Jul 29 08:05:35 PM PDT 24
Finished Jul 29 08:06:12 PM PDT 24
Peak memory 576108 kb
Host smart-60647dc7-2abb-4f60-a261-e10c8e5255fb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809742887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add
r.1809742887
Directory /workspace/94.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_error_random.2325629897
Short name T1758
Test name
Test status
Simulation time 73028591 ps
CPU time 8.62 seconds
Started Jul 29 08:05:34 PM PDT 24
Finished Jul 29 08:05:43 PM PDT 24
Peak memory 576028 kb
Host smart-33eb1e28-74cb-450e-b435-24af0e39fbc2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325629897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.2325629897
Directory /workspace/94.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random.4001370883
Short name T2716
Test name
Test status
Simulation time 259044303 ps
CPU time 22.38 seconds
Started Jul 29 08:05:33 PM PDT 24
Finished Jul 29 08:05:55 PM PDT 24
Peak memory 576016 kb
Host smart-643edeaa-2716-4fef-a5cf-bd0db3bc45f0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001370883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.4001370883
Directory /workspace/94.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.1311466786
Short name T1464
Test name
Test status
Simulation time 34149754962 ps
CPU time 393.2 seconds
Started Jul 29 08:05:33 PM PDT 24
Finished Jul 29 08:12:07 PM PDT 24
Peak memory 576096 kb
Host smart-fe9f2453-9da3-4672-b8a7-123c7d1903d7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311466786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.1311466786
Directory /workspace/94.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.1140931366
Short name T1610
Test name
Test status
Simulation time 66966832974 ps
CPU time 1109.6 seconds
Started Jul 29 08:05:31 PM PDT 24
Finished Jul 29 08:24:01 PM PDT 24
Peak memory 576120 kb
Host smart-6461af49-b200-49fa-960d-bf622571b747
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140931366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.1140931366
Directory /workspace/94.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.2021233122
Short name T2114
Test name
Test status
Simulation time 537289264 ps
CPU time 46.14 seconds
Started Jul 29 08:05:33 PM PDT 24
Finished Jul 29 08:06:20 PM PDT 24
Peak memory 575788 kb
Host smart-92cd5211-1c5c-473d-962f-2b61b3ea6e8f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021233122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del
ays.2021233122
Directory /workspace/94.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_same_source.3542855929
Short name T1687
Test name
Test status
Simulation time 1663049250 ps
CPU time 46.97 seconds
Started Jul 29 08:05:35 PM PDT 24
Finished Jul 29 08:06:22 PM PDT 24
Peak memory 575992 kb
Host smart-bd042291-5b5d-4c09-a73e-fafef19b541b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542855929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.3542855929
Directory /workspace/94.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke.3027332395
Short name T2281
Test name
Test status
Simulation time 48175040 ps
CPU time 6.15 seconds
Started Jul 29 08:05:35 PM PDT 24
Finished Jul 29 08:05:41 PM PDT 24
Peak memory 573924 kb
Host smart-bb613b25-d2a0-43cb-84be-fe8e4fe4add5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027332395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.3027332395
Directory /workspace/94.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.1485640465
Short name T2257
Test name
Test status
Simulation time 6636054122 ps
CPU time 65.93 seconds
Started Jul 29 08:05:35 PM PDT 24
Finished Jul 29 08:06:41 PM PDT 24
Peak memory 574012 kb
Host smart-148dbee8-fe23-4279-9b22-902e530790bf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485640465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.1485640465
Directory /workspace/94.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.1727793182
Short name T1929
Test name
Test status
Simulation time 4171412273 ps
CPU time 75.28 seconds
Started Jul 29 08:05:33 PM PDT 24
Finished Jul 29 08:06:48 PM PDT 24
Peak memory 574636 kb
Host smart-85047f58-09d0-4dd1-ac79-c15c65fb1db4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727793182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.1727793182
Directory /workspace/94.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.3608872450
Short name T2150
Test name
Test status
Simulation time 49521315 ps
CPU time 6.2 seconds
Started Jul 29 08:05:33 PM PDT 24
Finished Jul 29 08:05:39 PM PDT 24
Peak memory 573808 kb
Host smart-dd25351b-ef1e-4b74-b2c0-915f2d3c7c93
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608872450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay
s.3608872450
Directory /workspace/94.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all.1338097152
Short name T2077
Test name
Test status
Simulation time 4249859422 ps
CPU time 150.58 seconds
Started Jul 29 08:05:41 PM PDT 24
Finished Jul 29 08:08:12 PM PDT 24
Peak memory 576584 kb
Host smart-07992d0f-ccf2-4e2f-80d4-d1733e5bc0af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338097152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.1338097152
Directory /workspace/94.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.993139519
Short name T2472
Test name
Test status
Simulation time 5424939090 ps
CPU time 170.03 seconds
Started Jul 29 08:05:41 PM PDT 24
Finished Jul 29 08:08:31 PM PDT 24
Peak memory 576148 kb
Host smart-4bf26c59-d345-4b08-b0a1-aa4f55d755f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993139519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.993139519
Directory /workspace/94.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.1972453606
Short name T2857
Test name
Test status
Simulation time 6237682702 ps
CPU time 374.68 seconds
Started Jul 29 08:05:40 PM PDT 24
Finished Jul 29 08:11:54 PM PDT 24
Peak memory 576024 kb
Host smart-b9b66ed7-5c93-401e-855a-b6e1c174a403
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972453606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all
_with_rand_reset.1972453606
Directory /workspace/94.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.3435106759
Short name T1517
Test name
Test status
Simulation time 1121376708 ps
CPU time 172.53 seconds
Started Jul 29 08:05:39 PM PDT 24
Finished Jul 29 08:08:32 PM PDT 24
Peak memory 576812 kb
Host smart-76e8b137-d6cb-4454-9480-600b7d9719fa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435106759 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al
l_with_reset_error.3435106759
Directory /workspace/94.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.1678916857
Short name T2749
Test name
Test status
Simulation time 249098106 ps
CPU time 13.48 seconds
Started Jul 29 08:05:34 PM PDT 24
Finished Jul 29 08:05:48 PM PDT 24
Peak memory 575996 kb
Host smart-42e63972-46fc-4412-81ca-c5144931860f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678916857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.1678916857
Directory /workspace/94.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_access_same_device.97571480
Short name T850
Test name
Test status
Simulation time 978520160 ps
CPU time 42.22 seconds
Started Jul 29 08:05:41 PM PDT 24
Finished Jul 29 08:06:24 PM PDT 24
Peak memory 575924 kb
Host smart-c1560062-3246-4bb1-9449-ae547ca47dd6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97571480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device.97571480
Directory /workspace/95.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.3732218911
Short name T2909
Test name
Test status
Simulation time 43410287323 ps
CPU time 773.18 seconds
Started Jul 29 08:05:41 PM PDT 24
Finished Jul 29 08:18:34 PM PDT 24
Peak memory 575916 kb
Host smart-2b71f9a9-d380-4e71-855c-ab445574329e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732218911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_
device_slow_rsp.3732218911
Directory /workspace/95.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.1677244921
Short name T2097
Test name
Test status
Simulation time 286122635 ps
CPU time 31.09 seconds
Started Jul 29 08:05:39 PM PDT 24
Finished Jul 29 08:06:11 PM PDT 24
Peak memory 575956 kb
Host smart-db9e445a-3ece-492f-99bb-1c80262dad82
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677244921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add
r.1677244921
Directory /workspace/95.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_error_random.3974259584
Short name T2280
Test name
Test status
Simulation time 129127857 ps
CPU time 7.17 seconds
Started Jul 29 08:05:40 PM PDT 24
Finished Jul 29 08:05:48 PM PDT 24
Peak memory 574464 kb
Host smart-131bbb73-6fa4-479c-9ea4-59e887ff5db5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974259584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.3974259584
Directory /workspace/95.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random.751743881
Short name T1427
Test name
Test status
Simulation time 168433398 ps
CPU time 8.61 seconds
Started Jul 29 08:05:40 PM PDT 24
Finished Jul 29 08:05:49 PM PDT 24
Peak memory 574540 kb
Host smart-6b6ff4ec-20f0-446a-a091-a96389eb8978
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751743881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.751743881
Directory /workspace/95.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.443580209
Short name T1719
Test name
Test status
Simulation time 40414306190 ps
CPU time 436.35 seconds
Started Jul 29 08:05:43 PM PDT 24
Finished Jul 29 08:12:59 PM PDT 24
Peak memory 576008 kb
Host smart-d02660b7-948a-45ec-9410-b0ab5d78b40c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443580209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.443580209
Directory /workspace/95.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.1329514213
Short name T2123
Test name
Test status
Simulation time 7526930041 ps
CPU time 123.44 seconds
Started Jul 29 08:05:44 PM PDT 24
Finished Jul 29 08:07:47 PM PDT 24
Peak memory 576024 kb
Host smart-69b3b81f-8f02-47a4-ab62-34831dc52af3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329514213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.1329514213
Directory /workspace/95.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.1670168235
Short name T1607
Test name
Test status
Simulation time 557792918 ps
CPU time 44.7 seconds
Started Jul 29 08:05:40 PM PDT 24
Finished Jul 29 08:06:25 PM PDT 24
Peak memory 576052 kb
Host smart-a760e5ac-0150-406e-bb60-ce7a33186807
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670168235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del
ays.1670168235
Directory /workspace/95.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_same_source.379554435
Short name T2676
Test name
Test status
Simulation time 1739645409 ps
CPU time 51.32 seconds
Started Jul 29 08:05:43 PM PDT 24
Finished Jul 29 08:06:35 PM PDT 24
Peak memory 575872 kb
Host smart-684e3a16-f631-4777-931d-686a5cf8117d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379554435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.379554435
Directory /workspace/95.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke.296471794
Short name T2083
Test name
Test status
Simulation time 239213971 ps
CPU time 10.13 seconds
Started Jul 29 08:05:42 PM PDT 24
Finished Jul 29 08:05:52 PM PDT 24
Peak memory 574528 kb
Host smart-c4aca9f2-7a5a-4fcf-8060-4f0d41147426
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296471794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.296471794
Directory /workspace/95.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.1976414003
Short name T2795
Test name
Test status
Simulation time 9864724414 ps
CPU time 97.15 seconds
Started Jul 29 08:05:46 PM PDT 24
Finished Jul 29 08:07:23 PM PDT 24
Peak memory 573844 kb
Host smart-189bc9f9-eaaf-47b1-970b-df7f770ec503
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976414003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.1976414003
Directory /workspace/95.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.2262313382
Short name T2743
Test name
Test status
Simulation time 6399943723 ps
CPU time 113.45 seconds
Started Jul 29 08:05:42 PM PDT 24
Finished Jul 29 08:07:36 PM PDT 24
Peak memory 574628 kb
Host smart-84223757-cfe1-450e-8c08-3d2ca17d9d9e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262313382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.2262313382
Directory /workspace/95.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.4055274858
Short name T2090
Test name
Test status
Simulation time 46903702 ps
CPU time 6.24 seconds
Started Jul 29 08:05:41 PM PDT 24
Finished Jul 29 08:05:48 PM PDT 24
Peak memory 573772 kb
Host smart-0131903b-7b88-4ca0-ad72-7e2fc312f123
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055274858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay
s.4055274858
Directory /workspace/95.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all.1503627321
Short name T1976
Test name
Test status
Simulation time 955960885 ps
CPU time 34.54 seconds
Started Jul 29 08:05:42 PM PDT 24
Finished Jul 29 08:06:16 PM PDT 24
Peak memory 575936 kb
Host smart-2c0190ad-2056-4a49-b85a-67a58afeb981
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503627321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.1503627321
Directory /workspace/95.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.1802120126
Short name T1821
Test name
Test status
Simulation time 13757476524 ps
CPU time 495.32 seconds
Started Jul 29 08:05:42 PM PDT 24
Finished Jul 29 08:13:57 PM PDT 24
Peak memory 576812 kb
Host smart-4e9cd1bb-7215-40ab-8366-de2ca363c8f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802120126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.1802120126
Directory /workspace/95.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.2017699945
Short name T1459
Test name
Test status
Simulation time 66903154 ps
CPU time 22.21 seconds
Started Jul 29 08:05:41 PM PDT 24
Finished Jul 29 08:06:04 PM PDT 24
Peak memory 575964 kb
Host smart-256349e3-8b05-4e88-a359-77c1998ca37a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017699945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all
_with_rand_reset.2017699945
Directory /workspace/95.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.2502777498
Short name T1512
Test name
Test status
Simulation time 143629502 ps
CPU time 32.28 seconds
Started Jul 29 08:05:41 PM PDT 24
Finished Jul 29 08:06:13 PM PDT 24
Peak memory 576136 kb
Host smart-5755b560-b24b-4b8e-99ba-c54c0980f544
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502777498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al
l_with_reset_error.2502777498
Directory /workspace/95.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.2407468559
Short name T548
Test name
Test status
Simulation time 283716881 ps
CPU time 13.24 seconds
Started Jul 29 08:05:39 PM PDT 24
Finished Jul 29 08:05:53 PM PDT 24
Peak memory 576044 kb
Host smart-09115e74-47e4-42ab-976d-37f0d0f1d48b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407468559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.2407468559
Directory /workspace/95.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_access_same_device.3354128041
Short name T1735
Test name
Test status
Simulation time 1465773827 ps
CPU time 62.74 seconds
Started Jul 29 08:05:47 PM PDT 24
Finished Jul 29 08:06:50 PM PDT 24
Peak memory 575648 kb
Host smart-b25c6486-df1f-4ee9-bf93-8c8e31ffffa4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354128041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device
.3354128041
Directory /workspace/96.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.1119846743
Short name T2788
Test name
Test status
Simulation time 136024401510 ps
CPU time 2442.86 seconds
Started Jul 29 08:05:49 PM PDT 24
Finished Jul 29 08:46:33 PM PDT 24
Peak memory 576224 kb
Host smart-3c93d20b-6dcb-4ce7-9578-dda8c39f835a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119846743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_
device_slow_rsp.1119846743
Directory /workspace/96.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.2351383877
Short name T2332
Test name
Test status
Simulation time 252510664 ps
CPU time 26.43 seconds
Started Jul 29 08:05:49 PM PDT 24
Finished Jul 29 08:06:16 PM PDT 24
Peak memory 576164 kb
Host smart-bd4109ce-73dd-4a7a-91ae-b6b644375c31
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351383877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add
r.2351383877
Directory /workspace/96.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_error_random.1951779570
Short name T2908
Test name
Test status
Simulation time 66759879 ps
CPU time 8.97 seconds
Started Jul 29 08:05:48 PM PDT 24
Finished Jul 29 08:05:57 PM PDT 24
Peak memory 576016 kb
Host smart-54588f7e-1234-445a-b6e7-a500264f3ba9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951779570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.1951779570
Directory /workspace/96.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random.3137168538
Short name T1897
Test name
Test status
Simulation time 116006731 ps
CPU time 12.99 seconds
Started Jul 29 08:05:49 PM PDT 24
Finished Jul 29 08:06:02 PM PDT 24
Peak memory 576056 kb
Host smart-3929c058-519f-418b-adf7-bef496c72cad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137168538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.3137168538
Directory /workspace/96.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.67894665
Short name T2393
Test name
Test status
Simulation time 13334135268 ps
CPU time 140.49 seconds
Started Jul 29 08:05:54 PM PDT 24
Finished Jul 29 08:08:15 PM PDT 24
Peak memory 575832 kb
Host smart-262dd99a-e8d9-40b6-9012-627f2ad5512c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67894665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.67894665
Directory /workspace/96.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.3355136584
Short name T2514
Test name
Test status
Simulation time 30020510208 ps
CPU time 551.16 seconds
Started Jul 29 08:05:50 PM PDT 24
Finished Jul 29 08:15:01 PM PDT 24
Peak memory 575924 kb
Host smart-0e9e088f-5125-4830-ad25-61235bc4e2ce
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355136584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.3355136584
Directory /workspace/96.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.859618666
Short name T529
Test name
Test status
Simulation time 157954487 ps
CPU time 16.88 seconds
Started Jul 29 08:05:49 PM PDT 24
Finished Jul 29 08:06:06 PM PDT 24
Peak memory 575912 kb
Host smart-3b5316f1-8776-48c7-9bf8-b2fdeaf0c2f0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859618666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_dela
ys.859618666
Directory /workspace/96.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_same_source.3736721675
Short name T1752
Test name
Test status
Simulation time 239745774 ps
CPU time 9.84 seconds
Started Jul 29 08:05:49 PM PDT 24
Finished Jul 29 08:05:59 PM PDT 24
Peak memory 575760 kb
Host smart-383c94df-2d15-4d53-819a-1658951e1249
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736721675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.3736721675
Directory /workspace/96.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke.833595577
Short name T665
Test name
Test status
Simulation time 221876790 ps
CPU time 9.15 seconds
Started Jul 29 08:05:44 PM PDT 24
Finished Jul 29 08:05:53 PM PDT 24
Peak memory 573856 kb
Host smart-2e951d2d-0fa5-4420-8730-56a1778b18d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833595577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.833595577
Directory /workspace/96.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.1907692554
Short name T671
Test name
Test status
Simulation time 8289592557 ps
CPU time 83.48 seconds
Started Jul 29 08:05:54 PM PDT 24
Finished Jul 29 08:07:18 PM PDT 24
Peak memory 573824 kb
Host smart-046cb200-7ffc-48e7-bf69-1b48003f3ecd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907692554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.1907692554
Directory /workspace/96.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.2159125234
Short name T1441
Test name
Test status
Simulation time 5285004026 ps
CPU time 84.59 seconds
Started Jul 29 08:05:49 PM PDT 24
Finished Jul 29 08:07:14 PM PDT 24
Peak memory 574632 kb
Host smart-ede6ca20-51c0-4d58-a9d8-edf47b990a48
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159125234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.2159125234
Directory /workspace/96.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.4042013354
Short name T643
Test name
Test status
Simulation time 48638208 ps
CPU time 6.23 seconds
Started Jul 29 08:05:47 PM PDT 24
Finished Jul 29 08:05:54 PM PDT 24
Peak memory 574536 kb
Host smart-818c7e4a-1f42-48bd-8de1-53e218d2b086
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042013354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay
s.4042013354
Directory /workspace/96.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all.2268057618
Short name T2228
Test name
Test status
Simulation time 569623536 ps
CPU time 52.73 seconds
Started Jul 29 08:05:57 PM PDT 24
Finished Jul 29 08:06:50 PM PDT 24
Peak memory 576064 kb
Host smart-b4e507b9-f846-4738-8e31-82968b13ed1c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268057618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.2268057618
Directory /workspace/96.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.3845789558
Short name T2181
Test name
Test status
Simulation time 1013915010 ps
CPU time 79.49 seconds
Started Jul 29 08:05:57 PM PDT 24
Finished Jul 29 08:07:17 PM PDT 24
Peak memory 575928 kb
Host smart-4c350815-76fe-4641-aec3-1c2ccd82b291
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845789558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.3845789558
Directory /workspace/96.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.222916792
Short name T2545
Test name
Test status
Simulation time 7690339932 ps
CPU time 374.64 seconds
Started Jul 29 08:05:57 PM PDT 24
Finished Jul 29 08:12:12 PM PDT 24
Peak memory 576152 kb
Host smart-3887783d-4be6-49fc-a16b-3f11ead50f8f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222916792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_
with_rand_reset.222916792
Directory /workspace/96.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.3216221782
Short name T893
Test name
Test status
Simulation time 3817162346 ps
CPU time 235.67 seconds
Started Jul 29 08:05:56 PM PDT 24
Finished Jul 29 08:09:53 PM PDT 24
Peak memory 576104 kb
Host smart-c192efc1-1418-4938-a7a4-0abbf47b1826
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216221782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al
l_with_reset_error.3216221782
Directory /workspace/96.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.1390160906
Short name T1484
Test name
Test status
Simulation time 470827314 ps
CPU time 22.6 seconds
Started Jul 29 08:05:49 PM PDT 24
Finished Jul 29 08:06:12 PM PDT 24
Peak memory 576036 kb
Host smart-049fd269-2024-4452-ae7a-881088f09b3e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390160906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.1390160906
Directory /workspace/96.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_access_same_device.524763458
Short name T1733
Test name
Test status
Simulation time 2698306818 ps
CPU time 115.84 seconds
Started Jul 29 08:05:57 PM PDT 24
Finished Jul 29 08:07:53 PM PDT 24
Peak memory 575964 kb
Host smart-ed6e1b3c-ff2c-4649-b0ed-24f373e8bd53
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524763458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device.
524763458
Directory /workspace/97.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1880751926
Short name T1857
Test name
Test status
Simulation time 52993615328 ps
CPU time 874.41 seconds
Started Jul 29 08:05:58 PM PDT 24
Finished Jul 29 08:20:33 PM PDT 24
Peak memory 576076 kb
Host smart-396b87d9-7576-476d-b7ea-0a323c481e12
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880751926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_
device_slow_rsp.1880751926
Directory /workspace/97.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.315601994
Short name T2520
Test name
Test status
Simulation time 242139115 ps
CPU time 26.52 seconds
Started Jul 29 08:06:04 PM PDT 24
Finished Jul 29 08:06:30 PM PDT 24
Peak memory 576000 kb
Host smart-6d2efbc2-8976-433b-9741-97f4605c678a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315601994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_addr
.315601994
Directory /workspace/97.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_error_random.758763697
Short name T2199
Test name
Test status
Simulation time 1898658963 ps
CPU time 60.88 seconds
Started Jul 29 08:06:05 PM PDT 24
Finished Jul 29 08:07:06 PM PDT 24
Peak memory 576008 kb
Host smart-3be97ecb-ad53-4654-8ef1-0a6ed52447b9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758763697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.758763697
Directory /workspace/97.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random.1244751009
Short name T1903
Test name
Test status
Simulation time 430343029 ps
CPU time 36.61 seconds
Started Jul 29 08:05:58 PM PDT 24
Finished Jul 29 08:06:34 PM PDT 24
Peak memory 575988 kb
Host smart-a154bb40-c281-4262-b736-ed4be17c9682
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244751009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.1244751009
Directory /workspace/97.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.1116378517
Short name T1643
Test name
Test status
Simulation time 41794713275 ps
CPU time 400.39 seconds
Started Jul 29 08:05:57 PM PDT 24
Finished Jul 29 08:12:37 PM PDT 24
Peak memory 575968 kb
Host smart-955350b7-07cd-4c56-8583-6a64965df3d7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116378517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.1116378517
Directory /workspace/97.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.1485320193
Short name T1635
Test name
Test status
Simulation time 68907770322 ps
CPU time 1260.99 seconds
Started Jul 29 08:05:56 PM PDT 24
Finished Jul 29 08:26:57 PM PDT 24
Peak memory 575932 kb
Host smart-49bfa830-8570-4986-9a83-4fca59de0053
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485320193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.1485320193
Directory /workspace/97.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.795141447
Short name T628
Test name
Test status
Simulation time 453572660 ps
CPU time 39.72 seconds
Started Jul 29 08:05:56 PM PDT 24
Finished Jul 29 08:06:36 PM PDT 24
Peak memory 575876 kb
Host smart-8e8b330c-57a1-41ab-8711-474648427605
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795141447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_dela
ys.795141447
Directory /workspace/97.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_same_source.1630022792
Short name T2732
Test name
Test status
Simulation time 132965964 ps
CPU time 11.91 seconds
Started Jul 29 08:06:05 PM PDT 24
Finished Jul 29 08:06:17 PM PDT 24
Peak memory 575948 kb
Host smart-a0efd3ca-ad33-4ac9-bb14-5801fabf26d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630022792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.1630022792
Directory /workspace/97.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke.2347598069
Short name T1585
Test name
Test status
Simulation time 46300486 ps
CPU time 6.41 seconds
Started Jul 29 08:05:57 PM PDT 24
Finished Jul 29 08:06:03 PM PDT 24
Peak memory 573796 kb
Host smart-70901c6f-ba6c-4135-8307-5140203021b9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347598069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.2347598069
Directory /workspace/97.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.782995816
Short name T1919
Test name
Test status
Simulation time 9484775453 ps
CPU time 99.08 seconds
Started Jul 29 08:05:58 PM PDT 24
Finished Jul 29 08:07:37 PM PDT 24
Peak memory 574004 kb
Host smart-f602d191-d37e-4df6-a5c4-4e318811a8f9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782995816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.782995816
Directory /workspace/97.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.2238230961
Short name T1540
Test name
Test status
Simulation time 5456500611 ps
CPU time 92.3 seconds
Started Jul 29 08:05:57 PM PDT 24
Finished Jul 29 08:07:29 PM PDT 24
Peak memory 573944 kb
Host smart-1e004d27-00a2-4286-9b5d-145845a920a0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238230961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.2238230961
Directory /workspace/97.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.1876759414
Short name T2399
Test name
Test status
Simulation time 58668239 ps
CPU time 6.75 seconds
Started Jul 29 08:05:56 PM PDT 24
Finished Jul 29 08:06:03 PM PDT 24
Peak memory 573812 kb
Host smart-19452079-d14a-4b55-b64b-d2872c12422c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876759414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay
s.1876759414
Directory /workspace/97.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all.2750752953
Short name T614
Test name
Test status
Simulation time 5067142855 ps
CPU time 163.2 seconds
Started Jul 29 08:06:10 PM PDT 24
Finished Jul 29 08:08:53 PM PDT 24
Peak memory 575972 kb
Host smart-5f5d5c3c-f2c1-4f26-b9fc-4729da389981
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750752953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.2750752953
Directory /workspace/97.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.2978091335
Short name T1797
Test name
Test status
Simulation time 8524754513 ps
CPU time 291.55 seconds
Started Jul 29 08:06:05 PM PDT 24
Finished Jul 29 08:10:57 PM PDT 24
Peak memory 576188 kb
Host smart-631ddba5-daac-4747-af63-9ea958e62e7f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978091335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.2978091335
Directory /workspace/97.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1073101413
Short name T2758
Test name
Test status
Simulation time 178729000 ps
CPU time 89.35 seconds
Started Jul 29 08:06:06 PM PDT 24
Finished Jul 29 08:07:35 PM PDT 24
Peak memory 576640 kb
Host smart-f4ab88fc-a836-4865-88aa-ee57b82b2726
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073101413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all
_with_rand_reset.1073101413
Directory /workspace/97.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.261108366
Short name T1870
Test name
Test status
Simulation time 16048034221 ps
CPU time 718.73 seconds
Started Jul 29 08:06:07 PM PDT 24
Finished Jul 29 08:18:06 PM PDT 24
Peak memory 577888 kb
Host smart-bced8ea2-9302-4cd4-ad87-5be287aa3400
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261108366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all
_with_reset_error.261108366
Directory /workspace/97.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.980765545
Short name T2383
Test name
Test status
Simulation time 481588110 ps
CPU time 20.09 seconds
Started Jul 29 08:06:10 PM PDT 24
Finished Jul 29 08:06:30 PM PDT 24
Peak memory 575916 kb
Host smart-eb323075-479f-4d4a-835e-dd3832f686a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980765545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.980765545
Directory /workspace/97.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_access_same_device.3419837629
Short name T1587
Test name
Test status
Simulation time 1293508853 ps
CPU time 51.48 seconds
Started Jul 29 08:06:17 PM PDT 24
Finished Jul 29 08:07:08 PM PDT 24
Peak memory 575944 kb
Host smart-b7430bd2-9df1-4a40-8090-266c50226cc9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419837629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device
.3419837629
Directory /workspace/98.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.3191179578
Short name T864
Test name
Test status
Simulation time 10449848570 ps
CPU time 186.19 seconds
Started Jul 29 08:06:15 PM PDT 24
Finished Jul 29 08:09:21 PM PDT 24
Peak memory 573908 kb
Host smart-4de74993-fe38-4d07-adfd-d42955f222e7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191179578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_
device_slow_rsp.3191179578
Directory /workspace/98.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.1494704137
Short name T1404
Test name
Test status
Simulation time 1131694152 ps
CPU time 46.92 seconds
Started Jul 29 08:06:14 PM PDT 24
Finished Jul 29 08:07:01 PM PDT 24
Peak memory 575996 kb
Host smart-ddaf16b9-920c-4f83-bcbd-33ee6bf948a6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494704137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add
r.1494704137
Directory /workspace/98.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_error_random.2820101953
Short name T2854
Test name
Test status
Simulation time 1538882005 ps
CPU time 54.69 seconds
Started Jul 29 08:06:15 PM PDT 24
Finished Jul 29 08:07:10 PM PDT 24
Peak memory 575768 kb
Host smart-ee09a1ac-40ab-4e95-ab64-1e1348a37932
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820101953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.2820101953
Directory /workspace/98.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random.3895369790
Short name T2492
Test name
Test status
Simulation time 428220079 ps
CPU time 16.08 seconds
Started Jul 29 08:06:06 PM PDT 24
Finished Jul 29 08:06:23 PM PDT 24
Peak memory 576004 kb
Host smart-a3954316-b226-437a-a5a1-29a70c13f20d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895369790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.3895369790
Directory /workspace/98.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.1788592443
Short name T1412
Test name
Test status
Simulation time 17020112054 ps
CPU time 169.37 seconds
Started Jul 29 08:06:14 PM PDT 24
Finished Jul 29 08:09:03 PM PDT 24
Peak memory 575792 kb
Host smart-b8cb1fa4-31f4-4978-9a4b-4d7a43331f7c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788592443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.1788592443
Directory /workspace/98.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.2006881290
Short name T2195
Test name
Test status
Simulation time 17563680840 ps
CPU time 299.19 seconds
Started Jul 29 08:06:15 PM PDT 24
Finished Jul 29 08:11:15 PM PDT 24
Peak memory 576128 kb
Host smart-deb1f43a-4b9b-4210-bb64-3616b6f2d511
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006881290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.2006881290
Directory /workspace/98.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.2211531225
Short name T2419
Test name
Test status
Simulation time 277118678 ps
CPU time 25.5 seconds
Started Jul 29 08:06:06 PM PDT 24
Finished Jul 29 08:06:32 PM PDT 24
Peak memory 575952 kb
Host smart-04c52386-a7bc-4ad7-91f7-7f4a3e3e70e3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211531225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del
ays.2211531225
Directory /workspace/98.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_same_source.2168842375
Short name T1712
Test name
Test status
Simulation time 447386497 ps
CPU time 30.85 seconds
Started Jul 29 08:06:20 PM PDT 24
Finished Jul 29 08:06:51 PM PDT 24
Peak memory 575956 kb
Host smart-f509022f-f375-4ea3-967d-272fe4039d41
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168842375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.2168842375
Directory /workspace/98.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke.649985328
Short name T1419
Test name
Test status
Simulation time 216787312 ps
CPU time 8.9 seconds
Started Jul 29 08:06:09 PM PDT 24
Finished Jul 29 08:06:18 PM PDT 24
Peak memory 573904 kb
Host smart-3c0491c8-93df-4d3e-aee1-00b8ef0d0233
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649985328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.649985328
Directory /workspace/98.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.3699809988
Short name T2086
Test name
Test status
Simulation time 9432252413 ps
CPU time 101.12 seconds
Started Jul 29 08:06:08 PM PDT 24
Finished Jul 29 08:07:49 PM PDT 24
Peak memory 573940 kb
Host smart-3c9c282c-2311-4b89-af58-9e03483e4d67
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699809988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.3699809988
Directory /workspace/98.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.1764961201
Short name T2227
Test name
Test status
Simulation time 4163354785 ps
CPU time 68.17 seconds
Started Jul 29 08:06:08 PM PDT 24
Finished Jul 29 08:07:16 PM PDT 24
Peak memory 574584 kb
Host smart-b274c8d7-887a-453f-a967-69df1d4e6219
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764961201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.1764961201
Directory /workspace/98.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2119972787
Short name T672
Test name
Test status
Simulation time 52787217 ps
CPU time 7.1 seconds
Started Jul 29 08:06:07 PM PDT 24
Finished Jul 29 08:06:14 PM PDT 24
Peak memory 573852 kb
Host smart-51a00169-0fed-4499-92a6-29e2eccb36aa
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119972787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay
s.2119972787
Directory /workspace/98.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all.3756729343
Short name T2165
Test name
Test status
Simulation time 4195953281 ps
CPU time 161.07 seconds
Started Jul 29 08:06:15 PM PDT 24
Finished Jul 29 08:08:56 PM PDT 24
Peak memory 576140 kb
Host smart-7ae252c5-6709-455f-ad8f-78478612890a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756729343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.3756729343
Directory /workspace/98.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.2316374469
Short name T1852
Test name
Test status
Simulation time 8910385564 ps
CPU time 312.38 seconds
Started Jul 29 08:06:21 PM PDT 24
Finished Jul 29 08:11:33 PM PDT 24
Peak memory 576748 kb
Host smart-1ce561c7-4bce-4e06-9f86-f2cdab981580
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316374469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.2316374469
Directory /workspace/98.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.3189197506
Short name T897
Test name
Test status
Simulation time 86790127 ps
CPU time 29.15 seconds
Started Jul 29 08:06:15 PM PDT 24
Finished Jul 29 08:06:44 PM PDT 24
Peak memory 576008 kb
Host smart-a596ec1d-16e1-4cca-ab71-d4d87182c76b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189197506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all
_with_rand_reset.3189197506
Directory /workspace/98.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.867232843
Short name T2570
Test name
Test status
Simulation time 2224366366 ps
CPU time 294.13 seconds
Started Jul 29 08:06:14 PM PDT 24
Finished Jul 29 08:11:08 PM PDT 24
Peak memory 576864 kb
Host smart-4ec9aa37-08fe-461c-ac0a-500b4203d728
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867232843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all
_with_reset_error.867232843
Directory /workspace/98.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.557423761
Short name T1481
Test name
Test status
Simulation time 368344217 ps
CPU time 17.27 seconds
Started Jul 29 08:06:15 PM PDT 24
Finished Jul 29 08:06:32 PM PDT 24
Peak memory 575848 kb
Host smart-992c2952-881d-4bf1-be19-863ca830cf64
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557423761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.557423761
Directory /workspace/98.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_access_same_device.3624986127
Short name T2222
Test name
Test status
Simulation time 617645799 ps
CPU time 54.13 seconds
Started Jul 29 08:06:23 PM PDT 24
Finished Jul 29 08:07:17 PM PDT 24
Peak memory 575972 kb
Host smart-2a21bb40-38a4-461c-9b99-d878437a4bb1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624986127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device
.3624986127
Directory /workspace/99.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.1046128141
Short name T859
Test name
Test status
Simulation time 46293334558 ps
CPU time 856.28 seconds
Started Jul 29 08:06:23 PM PDT 24
Finished Jul 29 08:20:39 PM PDT 24
Peak memory 575752 kb
Host smart-c1874d73-8ba1-43b1-8141-42f0ae251461
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046128141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_
device_slow_rsp.1046128141
Directory /workspace/99.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.150309181
Short name T1996
Test name
Test status
Simulation time 838348048 ps
CPU time 36.84 seconds
Started Jul 29 08:06:31 PM PDT 24
Finished Jul 29 08:07:08 PM PDT 24
Peak memory 575960 kb
Host smart-c96ea4f6-a6ec-46ac-af90-8540a354a7c1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150309181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_addr
.150309181
Directory /workspace/99.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_error_random.2866248045
Short name T1392
Test name
Test status
Simulation time 402852953 ps
CPU time 15.06 seconds
Started Jul 29 08:06:24 PM PDT 24
Finished Jul 29 08:06:39 PM PDT 24
Peak memory 575908 kb
Host smart-b3506070-d62a-457e-8c60-a0db7947ce9c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866248045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.2866248045
Directory /workspace/99.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random.5326808
Short name T1711
Test name
Test status
Simulation time 1825933560 ps
CPU time 59.54 seconds
Started Jul 29 08:06:24 PM PDT 24
Finished Jul 29 08:07:24 PM PDT 24
Peak memory 575912 kb
Host smart-f8264fc1-814e-4ff9-bddf-07df32f4a9c4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5326808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.5326808
Directory /workspace/99.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.1245477375
Short name T2198
Test name
Test status
Simulation time 81536796867 ps
CPU time 861.29 seconds
Started Jul 29 08:06:30 PM PDT 24
Finished Jul 29 08:20:52 PM PDT 24
Peak memory 576048 kb
Host smart-e6ec72e5-20c3-4645-b762-3072f1f05dfb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245477375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.1245477375
Directory /workspace/99.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.2533728747
Short name T1766
Test name
Test status
Simulation time 24146434534 ps
CPU time 456.38 seconds
Started Jul 29 08:06:29 PM PDT 24
Finished Jul 29 08:14:06 PM PDT 24
Peak memory 576080 kb
Host smart-988b0961-9e53-40ac-b622-1e23061ef94c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533728747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.2533728747
Directory /workspace/99.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.3125319447
Short name T508
Test name
Test status
Simulation time 514761381 ps
CPU time 48.01 seconds
Started Jul 29 08:06:23 PM PDT 24
Finished Jul 29 08:07:11 PM PDT 24
Peak memory 575816 kb
Host smart-c820b500-ebb4-4105-b877-152fdc8fb0ee
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125319447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del
ays.3125319447
Directory /workspace/99.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_same_source.2226875278
Short name T1917
Test name
Test status
Simulation time 2566980733 ps
CPU time 73.59 seconds
Started Jul 29 08:06:23 PM PDT 24
Finished Jul 29 08:07:36 PM PDT 24
Peak memory 576028 kb
Host smart-937e9143-2531-4394-a66e-f3e55115e1d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226875278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.2226875278
Directory /workspace/99.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke.927252162
Short name T2504
Test name
Test status
Simulation time 186128344 ps
CPU time 8.81 seconds
Started Jul 29 08:06:14 PM PDT 24
Finished Jul 29 08:06:23 PM PDT 24
Peak memory 573828 kb
Host smart-282a592a-4483-4ed9-8c4a-d15692a3e354
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927252162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.927252162
Directory /workspace/99.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.2642731699
Short name T2088
Test name
Test status
Simulation time 8275060299 ps
CPU time 84.93 seconds
Started Jul 29 08:06:25 PM PDT 24
Finished Jul 29 08:07:50 PM PDT 24
Peak memory 573820 kb
Host smart-1b149af1-cd03-4f96-93bf-78ed2bbcee92
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642731699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.2642731699
Directory /workspace/99.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.4233458574
Short name T2267
Test name
Test status
Simulation time 2484943055 ps
CPU time 42.79 seconds
Started Jul 29 08:06:22 PM PDT 24
Finished Jul 29 08:07:05 PM PDT 24
Peak memory 574560 kb
Host smart-4b3e7451-6106-49ef-9232-72dee6ee6869
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233458574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.4233458574
Directory /workspace/99.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.2337608565
Short name T1914
Test name
Test status
Simulation time 53536334 ps
CPU time 6.3 seconds
Started Jul 29 08:06:22 PM PDT 24
Finished Jul 29 08:06:29 PM PDT 24
Peak memory 574528 kb
Host smart-ac940ffd-f760-4148-8948-28b33d8c0c49
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337608565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay
s.2337608565
Directory /workspace/99.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all.951316264
Short name T2856
Test name
Test status
Simulation time 464219177 ps
CPU time 45.83 seconds
Started Jul 29 08:06:32 PM PDT 24
Finished Jul 29 08:07:18 PM PDT 24
Peak memory 575948 kb
Host smart-432a03a0-193b-4d5a-b0f0-8dda2a604631
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951316264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.951316264
Directory /workspace/99.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.1813617098
Short name T2713
Test name
Test status
Simulation time 3706182369 ps
CPU time 135.9 seconds
Started Jul 29 08:06:33 PM PDT 24
Finished Jul 29 08:08:49 PM PDT 24
Peak memory 576108 kb
Host smart-adaafc69-8c3e-46f3-8b02-b92b6ed3e78a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813617098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.1813617098
Directory /workspace/99.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.4019838868
Short name T620
Test name
Test status
Simulation time 6130296584 ps
CPU time 704.13 seconds
Started Jul 29 08:06:32 PM PDT 24
Finished Jul 29 08:18:16 PM PDT 24
Peak memory 576908 kb
Host smart-83b70a0a-5781-46b0-8d56-9e2073aa033a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019838868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all
_with_rand_reset.4019838868
Directory /workspace/99.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.2152646068
Short name T2840
Test name
Test status
Simulation time 6555719707 ps
CPU time 436.85 seconds
Started Jul 29 08:06:32 PM PDT 24
Finished Jul 29 08:13:49 PM PDT 24
Peak memory 576032 kb
Host smart-77e0979f-a547-4fa7-9f1d-cc9553620c78
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152646068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al
l_with_reset_error.2152646068
Directory /workspace/99.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.3968078343
Short name T660
Test name
Test status
Simulation time 547759913 ps
CPU time 23.64 seconds
Started Jul 29 08:06:25 PM PDT 24
Finished Jul 29 08:06:49 PM PDT 24
Peak memory 575888 kb
Host smart-0c41c8bb-fa67-4950-bad8-db554ad5cdde
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968078343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.3968078343
Directory /workspace/99.xbar_unmapped_addr/latest

Test location /workspace/coverage/default/0.chip_sival_flash_info_access.1971266299
Short name T346
Test name
Test status
Simulation time 3152594308 ps
CPU time 234.78 seconds
Started Jul 29 08:13:42 PM PDT 24
Finished Jul 29 08:17:37 PM PDT 24
Peak memory 609944 kb
Host smart-3a0db902-f78c-44c1-921b-d0386e7c833f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=1971266299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.1971266299
Directory /workspace/0.chip_sival_flash_info_access/latest

Test location /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1663117749
Short name T1313
Test name
Test status
Simulation time 18449043760 ps
CPU time 478.2 seconds
Started Jul 29 08:16:06 PM PDT 24
Finished Jul 29 08:24:05 PM PDT 24
Peak memory 619392 kb
Host smart-958c3c3e-5d8a-4e45-a16b-f049dea53080
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1663117749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1663117749
Directory /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location /workspace/coverage/default/0.chip_sw_aes_enc.2434356485
Short name T1190
Test name
Test status
Simulation time 2734898646 ps
CPU time 234.46 seconds
Started Jul 29 08:14:14 PM PDT 24
Finished Jul 29 08:18:08 PM PDT 24
Peak memory 609652 kb
Host smart-f374795f-5367-4dd9-a4ba-b3cf7284f4d6
User root
Command /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434356485 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.2434356485
Directory /workspace/0.chip_sw_aes_enc/latest

Test location /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1060978866
Short name T1052
Test name
Test status
Simulation time 3506203195 ps
CPU time 313.75 seconds
Started Jul 29 08:16:07 PM PDT 24
Finished Jul 29 08:21:21 PM PDT 24
Peak memory 609788 kb
Host smart-95c195b3-eeb8-47b7-b372-a5ed94a0749d
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060
978866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.1060978866
Directory /workspace/0.chip_sw_aes_enc_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3781254148
Short name T1234
Test name
Test status
Simulation time 3000936520 ps
CPU time 210.52 seconds
Started Jul 29 08:17:30 PM PDT 24
Finished Jul 29 08:21:01 PM PDT 24
Peak memory 609576 kb
Host smart-1b60b1df-06cb-4043-bd74-d3a528bda350
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3781254148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.3781254148
Directory /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_aes_entropy.139635649
Short name T1306
Test name
Test status
Simulation time 3034306268 ps
CPU time 229.05 seconds
Started Jul 29 08:13:53 PM PDT 24
Finished Jul 29 08:17:43 PM PDT 24
Peak memory 609624 kb
Host smart-cafb11de-c7dc-4357-9b38-9fcf4a52549f
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139635649 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.139635649
Directory /workspace/0.chip_sw_aes_entropy/latest

Test location /workspace/coverage/default/0.chip_sw_aes_idle.70569571
Short name T1246
Test name
Test status
Simulation time 2301161320 ps
CPU time 238.72 seconds
Started Jul 29 08:14:50 PM PDT 24
Finished Jul 29 08:18:49 PM PDT 24
Peak memory 609564 kb
Host smart-9a965fd4-b327-469e-969e-e4d03caf166a
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70569571 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.70569571
Directory /workspace/0.chip_sw_aes_idle/latest

Test location /workspace/coverage/default/0.chip_sw_aes_masking_off.3748925659
Short name T1316
Test name
Test status
Simulation time 3460081966 ps
CPU time 378.61 seconds
Started Jul 29 08:16:59 PM PDT 24
Finished Jul 29 08:23:18 PM PDT 24
Peak memory 610476 kb
Host smart-c07b8915-4454-4dfe-a820-cb6264ca44fe
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748925659 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.3748925659
Directory /workspace/0.chip_sw_aes_masking_off/latest

Test location /workspace/coverage/default/0.chip_sw_aes_smoketest.364647029
Short name T3
Test name
Test status
Simulation time 2448207250 ps
CPU time 222.33 seconds
Started Jul 29 08:24:24 PM PDT 24
Finished Jul 29 08:28:06 PM PDT 24
Peak memory 609664 kb
Host smart-8f09ed29-598d-4bb2-bcd5-708698c0e41c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364647029 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_aes_smoketest.364647029
Directory /workspace/0.chip_sw_aes_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_entropy.317438925
Short name T1387
Test name
Test status
Simulation time 3346969032 ps
CPU time 247.27 seconds
Started Jul 29 08:15:04 PM PDT 24
Finished Jul 29 08:19:12 PM PDT 24
Peak memory 609452 kb
Host smart-48edfaee-0a39-4cca-b4e5-793351fce730
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=317438925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.317438925
Directory /workspace/0.chip_sw_alert_handler_entropy/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_escalation.707175538
Short name T1129
Test name
Test status
Simulation time 6445414448 ps
CPU time 553.59 seconds
Started Jul 29 08:18:05 PM PDT 24
Finished Jul 29 08:27:18 PM PDT 24
Peak memory 619688 kb
Host smart-668c2ad5-82d9-495d-9374-4aef8d3406de
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=707175538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.707175538
Directory /workspace/0.chip_sw_alert_handler_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2417133572
Short name T214
Test name
Test status
Simulation time 7774092928 ps
CPU time 1537.47 seconds
Started Jul 29 08:16:54 PM PDT 24
Finished Jul 29 08:42:32 PM PDT 24
Peak memory 610244 kb
Host smart-c08edd36-2a1d-469f-999f-0fb51454c700
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2417133572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg
le.2417133572
Directory /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.305482150
Short name T1154
Test name
Test status
Simulation time 5277457772 ps
CPU time 568.64 seconds
Started Jul 29 08:16:14 PM PDT 24
Finished Jul 29 08:25:43 PM PDT 24
Peak memory 609940 kb
Host smart-86c80f00-9b7f-483d-93bb-cbb73a55d696
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=305482150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.305482150
Directory /workspace/0.chip_sw_alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1165371775
Short name T247
Test name
Test status
Simulation time 256338147744 ps
CPU time 11624 seconds
Started Jul 29 08:15:03 PM PDT 24
Finished Jul 29 11:28:49 PM PDT 24
Peak memory 610892 kb
Host smart-3fcfd270-d86b-4071-8a24-3a3752c89e58
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165371775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1165371775
Directory /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location /workspace/coverage/default/0.chip_sw_alert_test.3795770270
Short name T51
Test name
Test status
Simulation time 3262216200 ps
CPU time 328.85 seconds
Started Jul 29 08:16:27 PM PDT 24
Finished Jul 29 08:21:57 PM PDT 24
Peak memory 609912 kb
Host smart-7aca5437-a9c5-46a9-86eb-ebe4589c81b7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795770270 -assert nopostproc +UVM_TESTNAME=chip_ba
se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.chip_sw_alert_test.3795770270
Directory /workspace/0.chip_sw_alert_test/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4088064298
Short name T1253
Test name
Test status
Simulation time 7264247392 ps
CPU time 628.47 seconds
Started Jul 29 08:15:17 PM PDT 24
Finished Jul 29 08:25:46 PM PDT 24
Peak memory 609160 kb
Host smart-d68d521b-b911-446c-99c2-7e6ee4394dce
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4088064298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4088064298
Directory /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2429819582
Short name T996
Test name
Test status
Simulation time 3569764516 ps
CPU time 346.75 seconds
Started Jul 29 08:25:09 PM PDT 24
Finished Jul 29 08:30:56 PM PDT 24
Peak memory 609680 kb
Host smart-cc479cae-da44-4150-8fe2-d0b833afaee1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429819582 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.chip_sw_aon_timer_smoketest.2429819582
Directory /workspace/0.chip_sw_aon_timer_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2751574245
Short name T1289
Test name
Test status
Simulation time 10130877888 ps
CPU time 1029.66 seconds
Started Jul 29 08:14:46 PM PDT 24
Finished Jul 29 08:31:56 PM PDT 24
Peak memory 610524 kb
Host smart-1c7cfaf3-481e-4f6e-8be4-e4da1e38a225
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2751574245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.2751574245
Directory /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.901374692
Short name T926
Test name
Test status
Simulation time 5653469450 ps
CPU time 550.68 seconds
Started Jul 29 08:14:36 PM PDT 24
Finished Jul 29 08:23:46 PM PDT 24
Peak memory 610556 kb
Host smart-ec83764a-3a2a-4617-a978-878e3466d523
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=901374692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.901374692
Directory /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location /workspace/coverage/default/0.chip_sw_ast_clk_outputs.3524722566
Short name T750
Test name
Test status
Simulation time 7826326704 ps
CPU time 996.66 seconds
Started Jul 29 08:15:51 PM PDT 24
Finished Jul 29 08:32:28 PM PDT 24
Peak memory 616284 kb
Host smart-e23d9661-4717-4b18-b141-5e32f80ef4fc
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524722566 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.3524722566
Directory /workspace/0.chip_sw_ast_clk_outputs/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.237318204
Short name T1182
Test name
Test status
Simulation time 11951114071 ps
CPU time 1127.53 seconds
Started Jul 29 08:17:42 PM PDT 24
Finished Jul 29 08:36:30 PM PDT 24
Peak memory 620464 kb
Host smart-d9126d4d-d194-4a24-8d17-11f9ce17de8b
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=237318204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.237318204
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3522830752
Short name T1213
Test name
Test status
Simulation time 3855436588 ps
CPU time 617.7 seconds
Started Jul 29 08:17:45 PM PDT 24
Finished Jul 29 08:28:03 PM PDT 24
Peak memory 612012 kb
Host smart-0868dfb8-f347-4325-a91a-7c063546e563
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522830752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_dev.3522830752
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3434991735
Short name T1138
Test name
Test status
Simulation time 3419113240 ps
CPU time 565.6 seconds
Started Jul 29 08:18:33 PM PDT 24
Finished Jul 29 08:27:59 PM PDT 24
Peak memory 612008 kb
Host smart-685a87b7-4973-4546-aeba-41eeb27af6b5
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434991735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_rma.3434991735
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2810802640
Short name T147
Test name
Test status
Simulation time 3888974192 ps
CPU time 595.52 seconds
Started Jul 29 08:14:54 PM PDT 24
Finished Jul 29 08:24:50 PM PDT 24
Peak memory 613036 kb
Host smart-fc540802-ce3e-4b85-abbc-17b0c55c486e
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810802640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2810802640
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3826687295
Short name T1062
Test name
Test status
Simulation time 4653367280 ps
CPU time 498.35 seconds
Started Jul 29 08:14:34 PM PDT 24
Finished Jul 29 08:22:53 PM PDT 24
Peak memory 612092 kb
Host smart-88298bee-fd55-4987-8b0d-e1ccf95e45ea
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826687295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_dev.3826687295
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1550513429
Short name T94
Test name
Test status
Simulation time 5026647820 ps
CPU time 592.33 seconds
Started Jul 29 08:16:06 PM PDT 24
Finished Jul 29 08:25:58 PM PDT 24
Peak memory 612120 kb
Host smart-42141155-419c-46c8-ba0a-de7ba2de4e70
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550513429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_rma.1550513429
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.65611489
Short name T1327
Test name
Test status
Simulation time 4452984360 ps
CPU time 471.4 seconds
Started Jul 29 08:17:46 PM PDT 24
Finished Jul 29 08:25:37 PM PDT 24
Peak memory 612948 kb
Host smart-18cc06bc-8815-49a2-b7fd-dd2ef15c8c90
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65611489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_
TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c
hip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.65611489
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_jitter.982534778
Short name T1057
Test name
Test status
Simulation time 2947802794 ps
CPU time 196.96 seconds
Started Jul 29 08:15:00 PM PDT 24
Finished Jul 29 08:18:17 PM PDT 24
Peak memory 609620 kb
Host smart-4fa8263b-23dc-4d5f-ac50-744eb43f8129
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982534778 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_clkmgr_jitter.982534778
Directory /workspace/0.chip_sw_clkmgr_jitter/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.372721125
Short name T1245
Test name
Test status
Simulation time 3160737512 ps
CPU time 383.92 seconds
Started Jul 29 08:16:52 PM PDT 24
Finished Jul 29 08:23:16 PM PDT 24
Peak memory 609764 kb
Host smart-07f2e28b-a0d3-4f7d-a4d5-08c20585fcf4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372721125 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.372721125
Directory /workspace/0.chip_sw_clkmgr_jitter_frequency/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2634141872
Short name T103
Test name
Test status
Simulation time 3008901201 ps
CPU time 160.79 seconds
Started Jul 29 08:17:53 PM PDT 24
Finished Jul 29 08:20:34 PM PDT 24
Peak memory 609192 kb
Host smart-f12bae05-c47c-41b1-9e12-914b18eea274
User root
Command /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634141872 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.2634141872
Directory /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.535340302
Short name T281
Test name
Test status
Simulation time 3550444240 ps
CPU time 399.93 seconds
Started Jul 29 08:17:57 PM PDT 24
Finished Jul 29 08:24:37 PM PDT 24
Peak memory 610116 kb
Host smart-8218bb7c-5689-4cb7-9a33-dcea9a5ace71
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535340302 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.535340302
Directory /workspace/0.chip_sw_clkmgr_off_aes_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2408343517
Short name T1303
Test name
Test status
Simulation time 5259121492 ps
CPU time 656.55 seconds
Started Jul 29 08:17:01 PM PDT 24
Finished Jul 29 08:27:58 PM PDT 24
Peak memory 610456 kb
Host smart-8b723d92-16fc-4e96-866f-89af6f4a52f2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408343517 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.2408343517
Directory /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3488690207
Short name T1388
Test name
Test status
Simulation time 4651787728 ps
CPU time 639.28 seconds
Started Jul 29 08:15:08 PM PDT 24
Finished Jul 29 08:25:48 PM PDT 24
Peak memory 610216 kb
Host smart-e88f558d-a286-4f75-8975-078827274489
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488690207 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.3488690207
Directory /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2983659700
Short name T1089
Test name
Test status
Simulation time 4245485520 ps
CPU time 377.31 seconds
Started Jul 29 08:16:06 PM PDT 24
Finished Jul 29 08:22:24 PM PDT 24
Peak memory 609892 kb
Host smart-25bdb70c-0c08-41ea-b5e6-ea43fea7c122
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983659700 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.2983659700
Directory /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2603319484
Short name T1088
Test name
Test status
Simulation time 10994918676 ps
CPU time 1721.08 seconds
Started Jul 29 08:15:44 PM PDT 24
Finished Jul 29 08:44:25 PM PDT 24
Peak memory 610568 kb
Host smart-b054bd17-c107-4856-a7ba-de8e091f12f8
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603319484
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.2603319484
Directory /workspace/0.chip_sw_clkmgr_off_peri/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2916638388
Short name T1170
Test name
Test status
Simulation time 3461446520 ps
CPU time 396.22 seconds
Started Jul 29 08:19:28 PM PDT 24
Finished Jul 29 08:26:05 PM PDT 24
Peak memory 608548 kb
Host smart-0132d573-a25c-4f8d-8b88-cebbf983bc99
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916638388 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.2916638388
Directory /workspace/0.chip_sw_clkmgr_reset_frequency/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.569276456
Short name T928
Test name
Test status
Simulation time 4081652750 ps
CPU time 547.39 seconds
Started Jul 29 08:16:18 PM PDT 24
Finished Jul 29 08:25:26 PM PDT 24
Peak memory 609664 kb
Host smart-b89086c4-9578-469b-bf96-1658243a6ca4
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569276456 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.569276456
Directory /workspace/0.chip_sw_clkmgr_sleep_frequency/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.293065166
Short name T1002
Test name
Test status
Simulation time 2923913316 ps
CPU time 265.32 seconds
Started Jul 29 08:25:40 PM PDT 24
Finished Jul 29 08:30:06 PM PDT 24
Peak memory 609644 kb
Host smart-b501169c-344e-4429-9cab-d113544d0b64
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293065166 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.chip_sw_clkmgr_smoketest.293065166
Directory /workspace/0.chip_sw_clkmgr_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_coremark.1536875303
Short name T927
Test name
Test status
Simulation time 72063415322 ps
CPU time 14960.9 seconds
Started Jul 29 08:18:04 PM PDT 24
Finished Jul 30 12:27:25 AM PDT 24
Peak memory 610464 kb
Host smart-72141869-02b8-4ded-b846-8781aea0ace3
User root
Command /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1536875303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.1536875303
Directory /workspace/0.chip_sw_coremark/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2180320783
Short name T1268
Test name
Test status
Simulation time 20521349400 ps
CPU time 4744.23 seconds
Started Jul 29 08:17:42 PM PDT 24
Finished Jul 29 09:36:47 PM PDT 24
Peak memory 610408 kb
Host smart-03563af8-8e6e-4ec9-960f-e20ea18ae05a
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180320783 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.2180320783
Directory /workspace/0.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_kat_test.3864871642
Short name T1001
Test name
Test status
Simulation time 3181043756 ps
CPU time 321.33 seconds
Started Jul 29 08:22:53 PM PDT 24
Finished Jul 29 08:28:15 PM PDT 24
Peak memory 609276 kb
Host smart-5730ba3a-a4b5-4b25-944d-d3fb720a360c
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864871642 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.3864871642
Directory /workspace/0.chip_sw_csrng_kat_test/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_smoketest.2355569204
Short name T1022
Test name
Test status
Simulation time 2839209482 ps
CPU time 289.03 seconds
Started Jul 29 08:24:09 PM PDT 24
Finished Jul 29 08:28:58 PM PDT 24
Peak memory 609552 kb
Host smart-3d2fbf1a-4d2d-4e4a-9b7a-db31793c8317
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355569204 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.chip_sw_csrng_smoketest.2355569204
Directory /workspace/0.chip_sw_csrng_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_data_integrity_escalation.698647407
Short name T248
Test name
Test status
Simulation time 4909684600 ps
CPU time 633.95 seconds
Started Jul 29 08:14:31 PM PDT 24
Finished Jul 29 08:25:06 PM PDT 24
Peak memory 611168 kb
Host smart-36fb0cb3-50e5-4293-b3c9-31d5e35b2cac
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=698647407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.698647407
Directory /workspace/0.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_edn_auto_mode.1421397394
Short name T1343
Test name
Test status
Simulation time 4317031960 ps
CPU time 1185.71 seconds
Started Jul 29 08:16:53 PM PDT 24
Finished Jul 29 08:36:39 PM PDT 24
Peak memory 610048 kb
Host smart-fee06c60-bb45-4029-898f-bb61a165e56e
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421397394 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_
auto_mode.1421397394
Directory /workspace/0.chip_sw_edn_auto_mode/latest

Test location /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2730640155
Short name T1039
Test name
Test status
Simulation time 7415033592 ps
CPU time 1119.31 seconds
Started Jul 29 08:16:13 PM PDT 24
Finished Jul 29 08:34:53 PM PDT 24
Peak memory 610980 kb
Host smart-3d38692f-e55e-4e4e-bab9-f04f86075401
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed
n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2730640155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.2730640155
Directory /workspace/0.chip_sw_edn_entropy_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3038620748
Short name T1248
Test name
Test status
Simulation time 5504191885 ps
CPU time 810.43 seconds
Started Jul 29 08:15:42 PM PDT 24
Finished Jul 29 08:29:13 PM PDT 24
Peak memory 610968 kb
Host smart-30c84805-e80d-439c-abd4-3436ba47f4c0
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e
ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038620748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.3038620748
Directory /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest

Test location /workspace/coverage/default/0.chip_sw_edn_kat.3508928033
Short name T1107
Test name
Test status
Simulation time 3092292344 ps
CPU time 546.53 seconds
Started Jul 29 08:16:52 PM PDT 24
Finished Jul 29 08:25:59 PM PDT 24
Peak memory 615260 kb
Host smart-6b302819-f93a-48f5-9808-cb49c7dd59c5
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3
+accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508928033 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_edn_kat.3508928033
Directory /workspace/0.chip_sw_edn_kat/latest

Test location /workspace/coverage/default/0.chip_sw_edn_sw_mode.2950353179
Short name T1101
Test name
Test status
Simulation time 8417093098 ps
CPU time 1914.74 seconds
Started Jul 29 08:17:55 PM PDT 24
Finished Jul 29 08:49:50 PM PDT 24
Peak memory 609440 kb
Host smart-33cab688-d298-4630-88a7-cbe219d36425
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950353179 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.2950353179
Directory /workspace/0.chip_sw_edn_sw_mode/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2099907825
Short name T1359
Test name
Test status
Simulation time 2827522678 ps
CPU time 184.3 seconds
Started Jul 29 08:15:59 PM PDT 24
Finished Jul 29 08:19:04 PM PDT 24
Peak memory 609648 kb
Host smart-a401f35e-b8d9-4144-983f-137174d0545b
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20
99907825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.2099907825
Directory /workspace/0.chip_sw_entropy_src_ast_rng_req/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2968892
Short name T297
Test name
Test status
Simulation time 2854313908 ps
CPU time 174.19 seconds
Started Jul 29 08:14:19 PM PDT 24
Finished Jul 29 08:17:13 PM PDT 24
Peak memory 609388 kb
Host smart-862a0024-0250-44ee-8b1c-22b4f4fc4470
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968892 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.2968892
Directory /workspace/0.chip_sw_entropy_src_kat_test/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3034000671
Short name T975
Test name
Test status
Simulation time 4106537552 ps
CPU time 568.64 seconds
Started Jul 29 08:24:20 PM PDT 24
Finished Jul 29 08:33:49 PM PDT 24
Peak memory 609784 kb
Host smart-a45d8f11-0b28-4d3f-bca3-3c87c778c6ef
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3034000671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.3034000671
Directory /workspace/0.chip_sw_entropy_src_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_example_concurrency.1364584156
Short name T375
Test name
Test status
Simulation time 2467991856 ps
CPU time 192.41 seconds
Started Jul 29 08:13:10 PM PDT 24
Finished Jul 29 08:16:23 PM PDT 24
Peak memory 609476 kb
Host smart-40b6973f-6b56-4627-8112-9bab58fd6967
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364584156 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.chip_sw_example_concurrency.1364584156
Directory /workspace/0.chip_sw_example_concurrency/latest

Test location /workspace/coverage/default/0.chip_sw_example_flash.1427211543
Short name T944
Test name
Test status
Simulation time 2476247634 ps
CPU time 240.72 seconds
Started Jul 29 08:15:03 PM PDT 24
Finished Jul 29 08:19:04 PM PDT 24
Peak memory 608304 kb
Host smart-97642acd-574f-4847-a903-9894096f88df
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427211543 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_example_flash.1427211543
Directory /workspace/0.chip_sw_example_flash/latest

Test location /workspace/coverage/default/0.chip_sw_example_manufacturer.778428038
Short name T1385
Test name
Test status
Simulation time 3274140816 ps
CPU time 186.57 seconds
Started Jul 29 08:14:40 PM PDT 24
Finished Jul 29 08:17:47 PM PDT 24
Peak memory 609612 kb
Host smart-c61e7ed1-fce2-42cf-acf9-905764a9d277
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778428038 -assert nopostproc +UVM_TESTNAME=chip_b
ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.chip_sw_example_manufacturer.778428038
Directory /workspace/0.chip_sw_example_manufacturer/latest

Test location /workspace/coverage/default/0.chip_sw_example_rom.4218414084
Short name T1362
Test name
Test status
Simulation time 2625754292 ps
CPU time 118.24 seconds
Started Jul 29 08:12:39 PM PDT 24
Finished Jul 29 08:14:38 PM PDT 24
Peak memory 607920 kb
Host smart-b06aff3f-d753-477e-817d-41492ff88597
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218414084 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_example_rom.4218414084
Directory /workspace/0.chip_sw_example_rom/latest

Test location /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1006467904
Short name T1118
Test name
Test status
Simulation time 59986417820 ps
CPU time 10576.5 seconds
Started Jul 29 08:15:25 PM PDT 24
Finished Jul 29 11:11:43 PM PDT 24
Peak memory 624788 kb
Host smart-156ddade-0396-4e67-9fb6-6eafb6df9e2d
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=1006467904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.1006467904
Directory /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest

Test location /workspace/coverage/default/0.chip_sw_flash_crash_alert.3603152597
Short name T1241
Test name
Test status
Simulation time 6207886816 ps
CPU time 665.24 seconds
Started Jul 29 08:26:51 PM PDT 24
Finished Jul 29 08:37:57 PM PDT 24
Peak memory 611248 kb
Host smart-9c8348f3-4e43-487a-a909-af82b29f55e9
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:
new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=3603152597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.3603152597
Directory /workspace/0.chip_sw_flash_crash_alert/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1329297253
Short name T994
Test name
Test status
Simulation time 6479057120 ps
CPU time 1136.14 seconds
Started Jul 29 08:14:11 PM PDT 24
Finished Jul 29 08:33:07 PM PDT 24
Peak memory 610176 kb
Host smart-8d0ee998-e52b-49b6-ad7e-2ca9c37aac2b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329297253 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.chip_sw_flash_ctrl_access.1329297253
Directory /workspace/0.chip_sw_flash_ctrl_access/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.136000346
Short name T1369
Test name
Test status
Simulation time 5588677733 ps
CPU time 1051.58 seconds
Started Jul 29 08:16:14 PM PDT 24
Finished Jul 29 08:33:46 PM PDT 24
Peak memory 609916 kb
Host smart-c12eab7b-cf96-4584-9556-11a6e0b286ab
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136000346 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.136000346
Directory /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3976430012
Short name T1105
Test name
Test status
Simulation time 7080240139 ps
CPU time 1392.44 seconds
Started Jul 29 08:16:31 PM PDT 24
Finished Jul 29 08:39:44 PM PDT 24
Peak memory 610268 kb
Host smart-0b8823b5-79b3-4abc-bf66-b7532bb238de
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976430012 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3976430012
Directory /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3360273201
Short name T118
Test name
Test status
Simulation time 5622407597 ps
CPU time 1163.67 seconds
Started Jul 29 08:15:58 PM PDT 24
Finished Jul 29 08:35:22 PM PDT 24
Peak memory 609812 kb
Host smart-80125901-6e75-4f00-99d2-759d212f42da
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360273201 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.3360273201
Directory /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3214054993
Short name T1187
Test name
Test status
Simulation time 3104830756 ps
CPU time 401.86 seconds
Started Jul 29 08:16:55 PM PDT 24
Finished Jul 29 08:23:37 PM PDT 24
Peak memory 609796 kb
Host smart-e59823ee-64ac-48fc-a4b8-293498ed196c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214054993 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.3214054993
Directory /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2588480890
Short name T1251
Test name
Test status
Simulation time 5325212711 ps
CPU time 522.71 seconds
Started Jul 29 08:13:49 PM PDT 24
Finished Jul 29 08:22:32 PM PDT 24
Peak memory 609656 kb
Host smart-293ebc9a-ccd1-4210-8c05-0c117947be0a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25
88480890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.2588480890
Directory /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1853822443
Short name T1124
Test name
Test status
Simulation time 5640401672 ps
CPU time 1294.37 seconds
Started Jul 29 08:16:33 PM PDT 24
Finished Jul 29 08:38:08 PM PDT 24
Peak memory 610172 kb
Host smart-10fa580e-9dd2-44d9-bcee-a71e3c2aed3d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853822443 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.1853822443
Directory /workspace/0.chip_sw_flash_ctrl_mem_protection/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3801572021
Short name T1019
Test name
Test status
Simulation time 4778106541 ps
CPU time 717.84 seconds
Started Jul 29 08:15:42 PM PDT 24
Finished Jul 29 08:27:40 PM PDT 24
Peak memory 610184 kb
Host smart-1dce6d10-e002-42e3-ae82-510f09e2224b
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_
rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3801572021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3801572021
Directory /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3064933536
Short name T1169
Test name
Test status
Simulation time 3655088394 ps
CPU time 288.46 seconds
Started Jul 29 08:17:57 PM PDT 24
Finished Jul 29 08:22:45 PM PDT 24
Peak memory 608544 kb
Host smart-94f67e0c-6b83-4191-9001-80fa128d931c
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064933
536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.3064933536
Directory /workspace/0.chip_sw_flash_ctrl_write_clear/latest

Test location /workspace/coverage/default/0.chip_sw_flash_init.2428714403
Short name T1357
Test name
Test status
Simulation time 16978771014 ps
CPU time 2346.59 seconds
Started Jul 29 08:14:43 PM PDT 24
Finished Jul 29 08:53:50 PM PDT 24
Peak memory 612460 kb
Host smart-13f46ecb-da98-4240-ac1f-0cbcb31226a2
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428714403 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.2428714403
Directory /workspace/0.chip_sw_flash_init/latest

Test location /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.4179568163
Short name T241
Test name
Test status
Simulation time 23716096934 ps
CPU time 1894.87 seconds
Started Jul 29 08:16:42 PM PDT 24
Finished Jul 29 08:48:17 PM PDT 24
Peak memory 613596 kb
Host smart-b91427f2-2511-47d3-9e38-21a8dd337055
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4179568163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.4179568163
Directory /workspace/0.chip_sw_flash_init_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3604234224
Short name T1330
Test name
Test status
Simulation time 3251519072 ps
CPU time 164.21 seconds
Started Jul 29 08:18:43 PM PDT 24
Finished Jul 29 08:21:28 PM PDT 24
Peak memory 609540 kb
Host smart-e2ec28af-1d44-4be2-8336-e9a7012bd2a0
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket
est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3604234224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.3604234224
Directory /workspace/0.chip_sw_flash_scrambling_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_gpio_smoketest.1639156666
Short name T217
Test name
Test status
Simulation time 2534259150 ps
CPU time 251.53 seconds
Started Jul 29 08:23:43 PM PDT 24
Finished Jul 29 08:27:55 PM PDT 24
Peak memory 608764 kb
Host smart-86019202-0bad-4702-8fd2-7174acac4319
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639156666 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_sw_gpio_smoketest.1639156666
Directory /workspace/0.chip_sw_gpio_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc.2237207193
Short name T288
Test name
Test status
Simulation time 3002535078 ps
CPU time 349.88 seconds
Started Jul 29 08:22:29 PM PDT 24
Finished Jul 29 08:28:19 PM PDT 24
Peak memory 609764 kb
Host smart-c8e49e52-4ab6-4b3e-b511-83b30e787b45
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237207193 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_hmac_enc.2237207193
Directory /workspace/0.chip_sw_hmac_enc/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc_idle.3176939685
Short name T742
Test name
Test status
Simulation time 2649478410 ps
CPU time 240.83 seconds
Started Jul 29 08:16:31 PM PDT 24
Finished Jul 29 08:20:32 PM PDT 24
Peak memory 608432 kb
Host smart-c965f51c-9117-4267-a6ac-120f64fd5074
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176939685 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_hmac_enc_idle.3176939685
Directory /workspace/0.chip_sw_hmac_enc_idle/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.4037682145
Short name T1305
Test name
Test status
Simulation time 3005241569 ps
CPU time 231.6 seconds
Started Jul 29 08:17:36 PM PDT 24
Finished Jul 29 08:21:29 PM PDT 24
Peak memory 609876 kb
Host smart-acc68927-3773-49d0-95af-f4ba952fc493
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037682145 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.4037682145
Directory /workspace/0.chip_sw_hmac_enc_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1801627019
Short name T1353
Test name
Test status
Simulation time 3055968933 ps
CPU time 199.82 seconds
Started Jul 29 08:17:11 PM PDT 24
Finished Jul 29 08:20:31 PM PDT 24
Peak memory 609860 kb
Host smart-2c00a6fc-d73a-429e-89f6-093674e8b736
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801627019 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.1801627019
Directory /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_multistream.1820115856
Short name T1175
Test name
Test status
Simulation time 8604494960 ps
CPU time 1988.05 seconds
Started Jul 29 08:19:05 PM PDT 24
Finished Jul 29 08:52:14 PM PDT 24
Peak memory 610128 kb
Host smart-b2aeba94-5c8a-4b53-8815-760a00cccf4e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820115856 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.chip_sw_hmac_multistream.1820115856
Directory /workspace/0.chip_sw_hmac_multistream/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_oneshot.1229520051
Short name T1373
Test name
Test status
Simulation time 2782978696 ps
CPU time 268.37 seconds
Started Jul 29 08:16:43 PM PDT 24
Finished Jul 29 08:21:13 PM PDT 24
Peak memory 609664 kb
Host smart-8ee45bf4-4a49-4dd5-bae3-ff1c213eb892
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229520051 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_hmac_oneshot.1229520051
Directory /workspace/0.chip_sw_hmac_oneshot/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_smoketest.323179940
Short name T1150
Test name
Test status
Simulation time 3351379298 ps
CPU time 404.14 seconds
Started Jul 29 08:25:34 PM PDT 24
Finished Jul 29 08:32:19 PM PDT 24
Peak memory 608456 kb
Host smart-803fc3e2-710e-44a2-86cb-2c4c7b7e5b51
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323179940 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_hmac_smoketest.323179940
Directory /workspace/0.chip_sw_hmac_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1538064222
Short name T347
Test name
Test status
Simulation time 4648319600 ps
CPU time 701.03 seconds
Started Jul 29 08:14:56 PM PDT 24
Finished Jul 29 08:26:39 PM PDT 24
Peak memory 609224 kb
Host smart-4bf9c73e-8bc6-4515-a728-a9c26b44a577
User root
Command /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538064222 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.1538064222
Directory /workspace/0.chip_sw_i2c_host_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2357880760
Short name T326
Test name
Test status
Simulation time 5133646644 ps
CPU time 953.73 seconds
Started Jul 29 08:15:34 PM PDT 24
Finished Jul 29 08:31:28 PM PDT 24
Peak memory 609364 kb
Host smart-af86534d-7f3a-4d32-a3b3-a78c32c0373c
User root
Command /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357880760 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.2357880760
Directory /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1517128058
Short name T354
Test name
Test status
Simulation time 5070763740 ps
CPU time 769.71 seconds
Started Jul 29 08:13:35 PM PDT 24
Finished Jul 29 08:26:26 PM PDT 24
Peak memory 609220 kb
Host smart-e617df59-5118-497f-9355-81a4fd7664a4
User root
Command /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517128058 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.1517128058
Directory /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest

Test location /workspace/coverage/default/0.chip_sw_inject_scramble_seed.1540890110
Short name T365
Test name
Test status
Simulation time 64809108728 ps
CPU time 11859 seconds
Started Jul 29 08:13:58 PM PDT 24
Finished Jul 29 11:31:39 PM PDT 24
Peak memory 624684 kb
Host smart-d8526885-7eac-4779-a511-5a424301cebb
User root
Command /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1540890110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.1540890110
Directory /workspace/0.chip_sw_inject_scramble_seed/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.892659749
Short name T1242
Test name
Test status
Simulation time 11112375976 ps
CPU time 2246.95 seconds
Started Jul 29 08:16:47 PM PDT 24
Finished Jul 29 08:54:14 PM PDT 24
Peak memory 617936 kb
Host smart-31c5f5fa-5de1-46f5-8bed-d501295d7b41
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8926
59749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.892659749
Directory /workspace/0.chip_sw_keymgr_key_derivation/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.657809116
Short name T1040
Test name
Test status
Simulation time 10262023544 ps
CPU time 1936.11 seconds
Started Jul 29 08:16:51 PM PDT 24
Finished Jul 29 08:49:08 PM PDT 24
Peak memory 616636 kb
Host smart-d4242a75-bfcc-4dc3-aaff-12576f293f1a
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=657809116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.657809116
Directory /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1788083397
Short name T1201
Test name
Test status
Simulation time 12418271211 ps
CPU time 2071.04 seconds
Started Jul 29 08:17:11 PM PDT 24
Finished Jul 29 08:51:42 PM PDT 24
Peak memory 616944 kb
Host smart-ea1fb168-5418-43af-922e-5d1d764f7401
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1788083397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en
_reduced_freq.1788083397
Directory /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2705148500
Short name T123
Test name
Test status
Simulation time 6226967792 ps
CPU time 1154.51 seconds
Started Jul 29 08:17:00 PM PDT 24
Finished Jul 29 08:36:15 PM PDT 24
Peak memory 618160 kb
Host smart-8804f31f-d51d-4686-92ae-98ac91c1b7e4
User root
Command /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2705148500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.2705148500
Directory /workspace/0.chip_sw_keymgr_key_derivation_prod/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.137325844
Short name T233
Test name
Test status
Simulation time 11330291774 ps
CPU time 2910.66 seconds
Started Jul 29 08:15:21 PM PDT 24
Finished Jul 29 09:03:52 PM PDT 24
Peak memory 610724 kb
Host smart-73b221a9-4fb1-4257-8774-c9fc12bff9b0
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137325
844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.137325844
Directory /workspace/0.chip_sw_keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2160272629
Short name T1015
Test name
Test status
Simulation time 9915215480 ps
CPU time 1837.74 seconds
Started Jul 29 08:16:52 PM PDT 24
Finished Jul 29 08:47:30 PM PDT 24
Peak memory 609776 kb
Host smart-6dffe9a5-fea1-476e-bb63-cb264ec1914c
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21602
72629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.2160272629
Directory /workspace/0.chip_sw_keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.33218441
Short name T235
Test name
Test status
Simulation time 17059426520 ps
CPU time 4136.54 seconds
Started Jul 29 08:15:12 PM PDT 24
Finished Jul 29 09:24:09 PM PDT 24
Peak memory 610892 kb
Host smart-fd9740d3-c3e1-48f7-ac45-5c61c2f7f31f
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33218
441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.33218441
Directory /workspace/0.chip_sw_keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_app_rom.3016749396
Short name T403
Test name
Test status
Simulation time 2862233872 ps
CPU time 241.04 seconds
Started Jul 29 08:15:46 PM PDT 24
Finished Jul 29 08:19:47 PM PDT 24
Peak memory 608400 kb
Host smart-03256fbc-2f72-4003-a8c3-b283af10ca30
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016749396 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_kmac_app_rom.3016749396
Directory /workspace/0.chip_sw_kmac_app_rom/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_entropy.2692596261
Short name T1322
Test name
Test status
Simulation time 2636215790 ps
CPU time 204.93 seconds
Started Jul 29 08:15:44 PM PDT 24
Finished Jul 29 08:19:09 PM PDT 24
Peak memory 609664 kb
Host smart-2f865016-d785-427d-9cb0-4b076ba1aad4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692596261 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_kmac_entropy.2692596261
Directory /workspace/0.chip_sw_kmac_entropy/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_idle.598442247
Short name T1026
Test name
Test status
Simulation time 3442696904 ps
CPU time 252.02 seconds
Started Jul 29 08:18:51 PM PDT 24
Finished Jul 29 08:23:03 PM PDT 24
Peak memory 609656 kb
Host smart-31195d6d-f98a-411c-a154-0d353f416007
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598442247 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_kmac_idle.598442247
Directory /workspace/0.chip_sw_kmac_idle/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1167131871
Short name T1284
Test name
Test status
Simulation time 2796494460 ps
CPU time 245.25 seconds
Started Jul 29 08:18:51 PM PDT 24
Finished Jul 29 08:22:56 PM PDT 24
Peak memory 609572 kb
Host smart-3667b36e-46ab-4b24-8c35-bf5965ef4ccd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167131871 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.chip_sw_kmac_mode_cshake.1167131871
Directory /workspace/0.chip_sw_kmac_mode_cshake/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.534903839
Short name T1143
Test name
Test status
Simulation time 2977648066 ps
CPU time 344.42 seconds
Started Jul 29 08:18:05 PM PDT 24
Finished Jul 29 08:23:50 PM PDT 24
Peak memory 609612 kb
Host smart-6da8a8e3-3004-4440-be0c-9730c45f668a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534903839 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_kmac_mode_kmac.534903839
Directory /workspace/0.chip_sw_kmac_mode_kmac/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2949042799
Short name T1006
Test name
Test status
Simulation time 2993801111 ps
CPU time 325.28 seconds
Started Jul 29 08:16:15 PM PDT 24
Finished Jul 29 08:21:40 PM PDT 24
Peak memory 609264 kb
Host smart-d9bb25f3-e465-4a9f-946f-f70e5d7cc4f6
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949042799 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.2949042799
Directory /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2463503124
Short name T1148
Test name
Test status
Simulation time 3568154648 ps
CPU time 291.2 seconds
Started Jul 29 08:16:26 PM PDT 24
Finished Jul 29 08:21:17 PM PDT 24
Peak memory 609736 kb
Host smart-5b6b6619-3de5-4bfb-9f67-9c0f1ea73088
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24635031
24 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2463503124
Directory /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_smoketest.741524537
Short name T976
Test name
Test status
Simulation time 3092542324 ps
CPU time 298.07 seconds
Started Jul 29 08:25:01 PM PDT 24
Finished Jul 29 08:29:59 PM PDT 24
Peak memory 609640 kb
Host smart-a5c49602-f4f1-43f1-a8c5-7cdfcef8f4ac
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741524537 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_kmac_smoketest.741524537
Directory /workspace/0.chip_sw_kmac_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.363948173
Short name T1383
Test name
Test status
Simulation time 2544570916 ps
CPU time 319.5 seconds
Started Jul 29 08:14:05 PM PDT 24
Finished Jul 29 08:19:25 PM PDT 24
Peak memory 609624 kb
Host smart-b40f6bd5-1c3c-4f45-9c63-e67640ea3b64
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363948173 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.363948173
Directory /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3794553317
Short name T1239
Test name
Test status
Simulation time 2870110497 ps
CPU time 158.79 seconds
Started Jul 29 08:15:31 PM PDT 24
Finished Jul 29 08:18:11 PM PDT 24
Peak memory 621784 kb
Host smart-b5055d8e-f8eb-4795-94b1-8e761f61482a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37945533
17 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.3794553317
Directory /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2693810015
Short name T1212
Test name
Test status
Simulation time 3256423224 ps
CPU time 128.26 seconds
Started Jul 29 08:13:41 PM PDT 24
Finished Jul 29 08:15:49 PM PDT 24
Peak memory 620756 kb
Host smart-a9da46d1-b777-4ad7-83c9-289b74d03f5a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules
,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2693810015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.2693810015
Directory /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2196164127
Short name T181
Test name
Test status
Simulation time 2922819602 ps
CPU time 119.09 seconds
Started Jul 29 08:15:28 PM PDT 24
Finished Jul 29 08:17:27 PM PDT 24
Peak memory 620088 kb
Host smart-47d69cf0-ae5a-4281-8d3f-b99a3bd7c263
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196164127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.2196164127
Directory /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3730574386
Short name T1346
Test name
Test status
Simulation time 2197909707 ps
CPU time 104.96 seconds
Started Jul 29 08:14:13 PM PDT 24
Finished Jul 29 08:15:58 PM PDT 24
Peak memory 616952 kb
Host smart-dc345a71-6370-4433-99e2-38b796ae6de1
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes
t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3730574386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.3730574386
Directory /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3661373711
Short name T722
Test name
Test status
Simulation time 1878785023 ps
CPU time 92.26 seconds
Started Jul 29 08:16:39 PM PDT 24
Finished Jul 29 08:18:12 PM PDT 24
Peak memory 617508 kb
Host smart-614fa33f-6cb1-458b-9bc2-5f5d533b3bb5
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s
im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661373711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3661373711
Directory /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1261678129
Short name T1233
Test name
Test status
Simulation time 50873652632 ps
CPU time 5627.82 seconds
Started Jul 29 08:15:54 PM PDT 24
Finished Jul 29 09:49:43 PM PDT 24
Peak memory 620732 kb
Host smart-acb439fe-9162-4c76-a2cd-db328e71ca72
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d
evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261678129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi
p_sw_lc_walkthrough_prod.1261678129
Directory /workspace/0.chip_sw_lc_walkthrough_prod/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3744998111
Short name T1053
Test name
Test status
Simulation time 10531667601 ps
CPU time 813.52 seconds
Started Jul 29 08:15:29 PM PDT 24
Finished Jul 29 08:29:04 PM PDT 24
Peak memory 619308 kb
Host smart-451bcb0b-3a45-4ea1-b1d4-3ef3ae0f1605
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa
lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744998111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.3744998111
Directory /workspace/0.chip_sw_lc_walkthrough_prodend/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2743339847
Short name T239
Test name
Test status
Simulation time 44772392936 ps
CPU time 5316.55 seconds
Started Jul 29 08:14:21 PM PDT 24
Finished Jul 29 09:42:58 PM PDT 24
Peak memory 620312 kb
Host smart-a96833f5-6a96-4f13-9829-e41eeef2d841
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743339847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip
_sw_lc_walkthrough_rma.2743339847
Directory /workspace/0.chip_sw_lc_walkthrough_rma/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.252939626
Short name T406
Test name
Test status
Simulation time 27524999244 ps
CPU time 2105.27 seconds
Started Jul 29 08:14:04 PM PDT 24
Finished Jul 29 08:49:10 PM PDT 24
Peak memory 621344 kb
Host smart-5830c0a8-945c-425d-93ad-58bfc73ada87
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks
_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=252939626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testunl
ocks.252939626
Directory /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2321308748
Short name T1318
Test name
Test status
Simulation time 16720717946 ps
CPU time 4110.19 seconds
Started Jul 29 08:14:25 PM PDT 24
Finished Jul 29 09:22:56 PM PDT 24
Peak memory 610268 kb
Host smart-1a661cb1-c43d-4129-ad59-66dcdbad549f
User root
Command /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_
rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2321308748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.2321308748
Directory /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2075196293
Short name T150
Test name
Test status
Simulation time 24887815346 ps
CPU time 4051.86 seconds
Started Jul 29 08:19:01 PM PDT 24
Finished Jul 29 09:26:33 PM PDT 24
Peak memory 610356 kb
Host smart-cad37937-0ce6-4325-be3b-cc9c41c93b90
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e
cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075196293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu
ced_freq.2075196293
Directory /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2445027426
Short name T1326
Test name
Test status
Simulation time 3802731104 ps
CPU time 521.84 seconds
Started Jul 29 08:15:54 PM PDT 24
Finished Jul 29 08:24:37 PM PDT 24
Peak memory 608696 kb
Host smart-f4a2dfa6-070e-43c8-b565-80cf605ec91a
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn
_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445027426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.2445027426
Directory /workspace/0.chip_sw_otbn_mem_scramble/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_randomness.1135682756
Short name T1224
Test name
Test status
Simulation time 6010880108 ps
CPU time 949.78 seconds
Started Jul 29 08:14:42 PM PDT 24
Finished Jul 29 08:30:32 PM PDT 24
Peak memory 610240 kb
Host smart-21a4c891-a5af-4dd3-81c4-519a168d4bae
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1135682756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.1135682756
Directory /workspace/0.chip_sw_otbn_randomness/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_smoketest.1747198466
Short name T982
Test name
Test status
Simulation time 9294440928 ps
CPU time 2166.52 seconds
Started Jul 29 08:25:25 PM PDT 24
Finished Jul 29 09:01:32 PM PDT 24
Peak memory 610268 kb
Host smart-139cb4bf-4d88-4f53-b6af-3d8e29548f55
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747198466 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_otbn_smoketest.1747198466
Directory /workspace/0.chip_sw_otbn_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3282843807
Short name T922
Test name
Test status
Simulation time 27941256704 ps
CPU time 5669.18 seconds
Started Jul 29 08:15:45 PM PDT 24
Finished Jul 29 09:50:15 PM PDT 24
Peak memory 610492 kb
Host smart-07bdb8bd-30c9-4a04-b070-fc834b6648a8
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328284
3807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.3282843807
Directory /workspace/0.chip_sw_otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.447166297
Short name T918
Test name
Test status
Simulation time 3049284318 ps
CPU time 207.31 seconds
Started Jul 29 08:13:07 PM PDT 24
Finished Jul 29 08:16:34 PM PDT 24
Peak memory 610056 kb
Host smart-b2c46f54-afcc-43db-9846-81bf7d741b15
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447166297 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.447166297
Directory /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.4008737893
Short name T999
Test name
Test status
Simulation time 7226575064 ps
CPU time 1009.86 seconds
Started Jul 29 08:13:57 PM PDT 24
Finished Jul 29 08:30:47 PM PDT 24
Peak memory 610784 kb
Host smart-6fa27c6b-5096-472e-be90-1e12d64c7fc8
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=4008737893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.4008737893
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1343276425
Short name T1220
Test name
Test status
Simulation time 6478734480 ps
CPU time 1064.65 seconds
Started Jul 29 08:15:18 PM PDT 24
Finished Jul 29 08:33:03 PM PDT 24
Peak memory 610472 kb
Host smart-a5c89b36-be6f-4b47-a7c1-25ac5d79d324
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1343276425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.1343276425
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3421551247
Short name T224
Test name
Test status
Simulation time 8734442844 ps
CPU time 1291.39 seconds
Started Jul 29 08:15:33 PM PDT 24
Finished Jul 29 08:37:04 PM PDT 24
Peak memory 610680 kb
Host smart-3fc231d7-d281-4fb7-a61d-b4c8282780c0
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3421551247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.3421551247
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3044776323
Short name T172
Test name
Test status
Simulation time 4363596968 ps
CPU time 698.29 seconds
Started Jul 29 08:15:03 PM PDT 24
Finished Jul 29 08:26:42 PM PDT 24
Peak memory 610204 kb
Host smart-50b19ec4-9fba-4642-a6b8-07d901e3f47a
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=3044776323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3044776323
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.763071539
Short name T1280
Test name
Test status
Simulation time 2560462816 ps
CPU time 295.94 seconds
Started Jul 29 08:24:28 PM PDT 24
Finished Jul 29 08:29:24 PM PDT 24
Peak memory 608452 kb
Host smart-03397da8-423b-4f89-9837-da227de761f9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763071539 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_otp_ctrl_smoketest.763071539
Directory /workspace/0.chip_sw_otp_ctrl_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_pattgen_ios.4127883895
Short name T355
Test name
Test status
Simulation time 3682847256 ps
CPU time 260.24 seconds
Started Jul 29 08:14:42 PM PDT 24
Finished Jul 29 08:19:04 PM PDT 24
Peak memory 610472 kb
Host smart-210697d0-7761-4484-8efe-1f1759eae48e
User root
Command /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127883895 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.4127883895
Directory /workspace/0.chip_sw_pattgen_ios/latest

Test location /workspace/coverage/default/0.chip_sw_power_idle_load.3101328479
Short name T144
Test name
Test status
Simulation time 4009950260 ps
CPU time 594.01 seconds
Started Jul 29 08:16:40 PM PDT 24
Finished Jul 29 08:26:35 PM PDT 24
Peak memory 608864 kb
Host smart-d2ee800e-3f0f-43d4-b2a5-d48179bd77b2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101328479 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.3101328479
Directory /workspace/0.chip_sw_power_idle_load/latest

Test location /workspace/coverage/default/0.chip_sw_power_sleep_load.1881045670
Short name T422
Test name
Test status
Simulation time 10384984700 ps
CPU time 499.31 seconds
Started Jul 29 08:16:32 PM PDT 24
Finished Jul 29 08:24:52 PM PDT 24
Peak memory 610356 kb
Host smart-1bd82007-d4d1-4098-afd7-502b223d8faa
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881045670 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.1881045670
Directory /workspace/0.chip_sw_power_sleep_load/latest

Test location /workspace/coverage/default/0.chip_sw_power_virus.3950178891
Short name T204
Test name
Test status
Simulation time 5922818572 ps
CPU time 1422.71 seconds
Started Jul 29 08:21:01 PM PDT 24
Finished Jul 29 08:44:44 PM PDT 24
Peak memory 625000 kb
Host smart-5645aa8a-b683-443a-93db-ec322ab66859
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_
power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes
t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3950178891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.3950178891
Directory /workspace/0.chip_sw_power_virus/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2469098588
Short name T536
Test name
Test status
Simulation time 13866484357 ps
CPU time 1610.87 seconds
Started Jul 29 08:14:17 PM PDT 24
Finished Jul 29 08:41:09 PM PDT 24
Peak memory 611416 kb
Host smart-c1a780ef-ea6c-4dd2-affd-4bad70b02809
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469
098588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.2469098588
Directory /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.59064141
Short name T1372
Test name
Test status
Simulation time 16580155844 ps
CPU time 1898.87 seconds
Started Jul 29 08:15:01 PM PDT 24
Finished Jul 29 08:46:41 PM PDT 24
Peak memory 611172 kb
Host smart-3817abbb-4e06-4369-b227-e91e84ad438e
User root
Command /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590
64141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.59064141
Directory /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.945179385
Short name T1043
Test name
Test status
Simulation time 15178954144 ps
CPU time 1732 seconds
Started Jul 29 08:16:51 PM PDT 24
Finished Jul 29 08:45:43 PM PDT 24
Peak memory 611276 kb
Host smart-8e8790ee-5abe-460b-a7a5-f990614dd00c
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=945179385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.945179385
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.882430114
Short name T101
Test name
Test status
Simulation time 20363191406 ps
CPU time 1646.16 seconds
Started Jul 29 08:15:37 PM PDT 24
Finished Jul 29 08:43:03 PM PDT 24
Peak memory 611104 kb
Host smart-416e4e9f-939b-49df-acc8-6c6b9dc7a0bf
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
882430114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.882430114
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1778561399
Short name T420
Test name
Test status
Simulation time 9896045628 ps
CPU time 763.7 seconds
Started Jul 29 08:21:16 PM PDT 24
Finished Jul 29 08:34:02 PM PDT 24
Peak memory 610808 kb
Host smart-28b251a2-2d75-4a91-8dd0-d8029296ee75
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778561399 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.1778561399
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3904375108
Short name T374
Test name
Test status
Simulation time 4688246532 ps
CPU time 405.42 seconds
Started Jul 29 08:15:16 PM PDT 24
Finished Jul 29 08:22:01 PM PDT 24
Peak memory 616372 kb
Host smart-19be2131-d841-4faf-bc8b-d4a763386756
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3904375108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.3904375108
Directory /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1928417477
Short name T970
Test name
Test status
Simulation time 13631130648 ps
CPU time 1612.06 seconds
Started Jul 29 08:16:07 PM PDT 24
Finished Jul 29 08:43:00 PM PDT 24
Peak memory 611600 kb
Host smart-22b37eff-3b7d-4a7e-811f-3789d407f9c7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928417477 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1928417477
Directory /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3896687418
Short name T410
Test name
Test status
Simulation time 7130396168 ps
CPU time 311.83 seconds
Started Jul 29 08:16:13 PM PDT 24
Finished Jul 29 08:21:26 PM PDT 24
Peak memory 610628 kb
Host smart-c46e7ef7-7b0e-4ce9-b648-60e8bdf1f15d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896687418 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3896687418
Directory /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.505985229
Short name T1265
Test name
Test status
Simulation time 7159422180 ps
CPU time 708.71 seconds
Started Jul 29 08:17:39 PM PDT 24
Finished Jul 29 08:29:28 PM PDT 24
Peak memory 610760 kb
Host smart-891cdb07-1287-446f-a629-f9ca6e872180
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505985229 -assert nopostpro
c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.505985229
Directory /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.198567412
Short name T360
Test name
Test status
Simulation time 31384839028 ps
CPU time 2829.89 seconds
Started Jul 29 08:15:05 PM PDT 24
Finished Jul 29 09:02:15 PM PDT 24
Peak memory 612040 kb
Host smart-2f5e0d70-ab00-4683-97ba-2df33edf40ae
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power
_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198567412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sl
eep_power_glitch_reset.198567412
Directory /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.359740932
Short name T367
Test name
Test status
Simulation time 6521752650 ps
CPU time 384.1 seconds
Started Jul 29 08:16:05 PM PDT 24
Finished Jul 29 08:22:30 PM PDT 24
Peak memory 611016 kb
Host smart-7aa3fa9a-216e-456a-99fe-3e33c3b86326
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul
es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=359740932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_sl
eep_wake_up.359740932
Directory /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2691296473
Short name T730
Test name
Test status
Simulation time 2992032808 ps
CPU time 321.32 seconds
Started Jul 29 08:19:57 PM PDT 24
Finished Jul 29 08:25:19 PM PDT 24
Peak memory 609488 kb
Host smart-d8bb9172-c344-44bd-b798-2bc6ad2be315
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691296473 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.2691296473
Directory /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1786402507
Short name T1377
Test name
Test status
Simulation time 5668691419 ps
CPU time 415.81 seconds
Started Jul 29 08:15:25 PM PDT 24
Finished Jul 29 08:22:22 PM PDT 24
Peak memory 617572 kb
Host smart-46e882e1-c4a7-41f6-9796-ebab6bc246e0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=1786402507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.1786402507
Directory /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.4255333259
Short name T1041
Test name
Test status
Simulation time 6497693684 ps
CPU time 405.87 seconds
Started Jul 29 08:16:34 PM PDT 24
Finished Jul 29 08:23:20 PM PDT 24
Peak memory 610764 kb
Host smart-08801526-180b-4bda-9805-14027a148861
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4255333259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.4255333259
Directory /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3449050761
Short name T1046
Test name
Test status
Simulation time 5996471176 ps
CPU time 496.74 seconds
Started Jul 29 08:25:03 PM PDT 24
Finished Jul 29 08:33:20 PM PDT 24
Peak memory 610300 kb
Host smart-7ed3e365-cef8-4c5d-b890-4df48d840ac7
User root
Command /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449050761 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.3449050761
Directory /workspace/0.chip_sw_pwrmgr_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1594430998
Short name T949
Test name
Test status
Simulation time 7792371612 ps
CPU time 1333.49 seconds
Started Jul 29 08:21:06 PM PDT 24
Finished Jul 29 08:43:22 PM PDT 24
Peak memory 610848 kb
Host smart-ee67d544-b18d-4784-9b0d-63d7007154c8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594430998 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.1594430998
Directory /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1252550925
Short name T1025
Test name
Test status
Simulation time 5313280072 ps
CPU time 492.47 seconds
Started Jul 29 08:16:03 PM PDT 24
Finished Jul 29 08:24:16 PM PDT 24
Peak memory 610420 kb
Host smart-29fcae7e-63c5-48b4-8847-8201f76225a3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252550925 -assert no
postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1252550925
Directory /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2366847135
Short name T400
Test name
Test status
Simulation time 6065558496 ps
CPU time 384.36 seconds
Started Jul 29 08:26:01 PM PDT 24
Finished Jul 29 08:32:26 PM PDT 24
Peak memory 610080 kb
Host smart-a6afdf93-d872-495d-86c7-cc21290f0a8e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366847135 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.2366847135
Directory /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1243940829
Short name T1086
Test name
Test status
Simulation time 5596087928 ps
CPU time 574.02 seconds
Started Jul 29 08:15:26 PM PDT 24
Finished Jul 29 08:25:01 PM PDT 24
Peak memory 609124 kb
Host smart-bb4939a7-a9d1-4744-88b4-611f13bc566b
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124
3940829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.1243940829
Directory /workspace/0.chip_sw_pwrmgr_wdog_reset/latest

Test location /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1549967759
Short name T1366
Test name
Test status
Simulation time 8483029547 ps
CPU time 614.86 seconds
Started Jul 29 08:15:33 PM PDT 24
Finished Jul 29 08:25:48 PM PDT 24
Peak memory 624744 kb
Host smart-f2a594c2-5de7-4f29-8c1c-7731bf674c37
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549967759 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.1549967759
Directory /workspace/0.chip_sw_rom_ctrl_integrity_check/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1675788104
Short name T267
Test name
Test status
Simulation time 6811377520 ps
CPU time 877.49 seconds
Started Jul 29 08:15:47 PM PDT 24
Finished Jul 29 08:30:25 PM PDT 24
Peak memory 610400 kb
Host smart-06307e1c-e209-47d8-a77c-681b9847e477
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675788104 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.1675788104
Directory /workspace/0.chip_sw_rstmgr_cpu_info/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.4117789775
Short name T1155
Test name
Test status
Simulation time 4864848040 ps
CPU time 743.45 seconds
Started Jul 29 08:15:40 PM PDT 24
Finished Jul 29 08:28:04 PM PDT 24
Peak memory 641452 kb
Host smart-34758803-cabf-4e55-9d6e-4e55e1fc23d1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4117789775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.4117789775
Directory /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3658479424
Short name T1258
Test name
Test status
Simulation time 3142865040 ps
CPU time 217.93 seconds
Started Jul 29 08:25:40 PM PDT 24
Finished Jul 29 08:29:18 PM PDT 24
Peak memory 608468 kb
Host smart-e3d692f4-dba8-4b33-a9c6-966b67db376e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658479424 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.chip_sw_rstmgr_smoketest.3658479424
Directory /workspace/0.chip_sw_rstmgr_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2754233109
Short name T958
Test name
Test status
Simulation time 5306444392 ps
CPU time 508.04 seconds
Started Jul 29 08:15:13 PM PDT 24
Finished Jul 29 08:23:42 PM PDT 24
Peak memory 610428 kb
Host smart-09bf447c-0185-489e-a54d-ef99c8439335
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754233109 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_rstmgr_sw_req.2754233109
Directory /workspace/0.chip_sw_rstmgr_sw_req/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.554212843
Short name T388
Test name
Test status
Simulation time 2662959708 ps
CPU time 283.92 seconds
Started Jul 29 08:21:33 PM PDT 24
Finished Jul 29 08:26:18 PM PDT 24
Peak memory 609632 kb
Host smart-c2bd06f9-5429-4db9-9b19-7f30055838ac
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554212843 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.554212843
Directory /workspace/0.chip_sw_rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1835262737
Short name T301
Test name
Test status
Simulation time 2853666968 ps
CPU time 238.18 seconds
Started Jul 29 08:18:22 PM PDT 24
Finished Jul 29 08:22:21 PM PDT 24
Peak memory 608396 kb
Host smart-3e170df5-652a-487c-a092-a7252053d929
User root
Command /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1835262737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.1835262737
Directory /workspace/0.chip_sw_rv_core_ibex_address_translation/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3647198102
Short name T302
Test name
Test status
Simulation time 3470165506 ps
CPU time 283.74 seconds
Started Jul 29 08:19:11 PM PDT 24
Finished Jul 29 08:23:55 PM PDT 24
Peak memory 609328 kb
Host smart-9d68613f-7d93-4127-b22e-d81f4316fe43
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647198102 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.3647198102
Directory /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.250790624
Short name T969
Test name
Test status
Simulation time 5369929956 ps
CPU time 1046.67 seconds
Started Jul 29 08:15:54 PM PDT 24
Finished Jul 29 08:33:21 PM PDT 24
Peak memory 610116 kb
Host smart-d2a482e5-80cd-40b2-ad04-b825e0b7b3df
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=250790624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.250790624
Directory /workspace/0.chip_sw_rv_core_ibex_rnd/latest

Test location /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1517914749
Short name T284
Test name
Test status
Simulation time 6652336320 ps
CPU time 462.19 seconds
Started Jul 29 08:18:32 PM PDT 24
Finished Jul 29 08:26:14 PM PDT 24
Peak memory 620496 kb
Host smart-8b5722d3-e67d-466a-a388-ea682542e2de
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517914749 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.1517914749
Directory /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest

Test location /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2188500860
Short name T305
Test name
Test status
Simulation time 5882381664 ps
CPU time 498.68 seconds
Started Jul 29 08:17:45 PM PDT 24
Finished Jul 29 08:26:04 PM PDT 24
Peak memory 619624 kb
Host smart-22d2c7cb-9204-48de-8ae8-6a887c88b955
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218850
0860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2188500860
Directory /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2175815405
Short name T442
Test name
Test status
Simulation time 3061714880 ps
CPU time 221.84 seconds
Started Jul 29 08:25:14 PM PDT 24
Finished Jul 29 08:28:56 PM PDT 24
Peak memory 608372 kb
Host smart-0662aac2-6f93-4e6e-ac83-f59c41f6fcfc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175815405 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_rv_plic_smoketest.2175815405
Directory /workspace/0.chip_sw_rv_plic_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_rv_timer_irq.3470325516
Short name T1047
Test name
Test status
Simulation time 2897229584 ps
CPU time 233.28 seconds
Started Jul 29 08:14:15 PM PDT 24
Finished Jul 29 08:18:08 PM PDT 24
Peak memory 609560 kb
Host smart-8acd1687-9c37-4f0a-ad7e-831ef2979bc9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470325516 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_rv_timer_irq.3470325516
Directory /workspace/0.chip_sw_rv_timer_irq/latest

Test location /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1316062768
Short name T1368
Test name
Test status
Simulation time 3254620072 ps
CPU time 266.64 seconds
Started Jul 29 08:25:46 PM PDT 24
Finished Jul 29 08:30:13 PM PDT 24
Peak memory 609588 kb
Host smart-83c4eb18-66b7-4fae-bbef-bcdcf96c6b72
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316062768 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_rv_timer_smoketest.1316062768
Directory /workspace/0.chip_sw_rv_timer_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2743851592
Short name T115
Test name
Test status
Simulation time 2847434271 ps
CPU time 210.96 seconds
Started Jul 29 08:17:54 PM PDT 24
Finished Jul 29 08:21:26 PM PDT 24
Peak memory 610404 kb
Host smart-6f31a92b-5a57-441a-909d-99391d89f15c
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743851
592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.2743851592
Directory /workspace/0.chip_sw_sensor_ctrl_status/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3618951490
Short name T100
Test name
Test status
Simulation time 3002768420 ps
CPU time 274.88 seconds
Started Jul 29 08:15:45 PM PDT 24
Finished Jul 29 08:20:21 PM PDT 24
Peak memory 609240 kb
Host smart-99864f5c-65a5-4194-a40b-bc6a7c509ad5
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618951490
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.3618951490
Directory /workspace/0.chip_sw_sleep_pin_wake/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3957382197
Short name T1074
Test name
Test status
Simulation time 9102732528 ps
CPU time 1398.86 seconds
Started Jul 29 08:13:31 PM PDT 24
Finished Jul 29 08:36:50 PM PDT 24
Peak memory 610720 kb
Host smart-d949930e-9ec8-4f9d-b9ff-08fe5f9d20d0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957382197 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.3957382197
Directory /workspace/0.chip_sw_sleep_pwm_pulses/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3332128960
Short name T282
Test name
Test status
Simulation time 6974893784 ps
CPU time 564.68 seconds
Started Jul 29 08:15:37 PM PDT 24
Finished Jul 29 08:25:02 PM PDT 24
Peak memory 610632 kb
Host smart-b51b34e6-be43-4aa1-b2ec-712dd1ff5d18
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332128960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl
eep_sram_ret_contents_no_scramble.3332128960
Directory /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3580435551
Short name T1269
Test name
Test status
Simulation time 7681498876 ps
CPU time 616.97 seconds
Started Jul 29 08:15:35 PM PDT 24
Finished Jul 29 08:25:52 PM PDT 24
Peak memory 610580 kb
Host smart-7d621e40-cc19-4467-8e14-53f798e9dcbb
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580435551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep
_sram_ret_contents_scramble.3580435551
Directory /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_pass_through.534275047
Short name T41
Test name
Test status
Simulation time 6498152529 ps
CPU time 895.5 seconds
Started Jul 29 08:15:37 PM PDT 24
Finished Jul 29 08:30:33 PM PDT 24
Peak memory 624832 kb
Host smart-fd9ba492-c540-4cb8-b67c-7ac74172436d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534275047 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.534275047
Directory /workspace/0.chip_sw_spi_device_pass_through/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3351165775
Short name T205
Test name
Test status
Simulation time 4590895747 ps
CPU time 461.71 seconds
Started Jul 29 08:14:26 PM PDT 24
Finished Jul 29 08:22:08 PM PDT 24
Peak memory 624852 kb
Host smart-4087a8e4-6f8b-4a76-bbcd-57c669f130ed
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351165775 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.3351165775
Directory /workspace/0.chip_sw_spi_device_pass_through_collision/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_tpm.1810122259
Short name T38
Test name
Test status
Simulation time 3719769579 ps
CPU time 417.13 seconds
Started Jul 29 08:15:41 PM PDT 24
Finished Jul 29 08:22:38 PM PDT 24
Peak memory 619736 kb
Host smart-90c60b13-2d37-4432-8d0b-21e8c479f487
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810122259 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.1810122259
Directory /workspace/0.chip_sw_spi_device_tpm/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3470747750
Short name T304
Test name
Test status
Simulation time 10525785090 ps
CPU time 901.71 seconds
Started Jul 29 08:16:59 PM PDT 24
Finished Jul 29 08:32:01 PM PDT 24
Peak memory 610848 kb
Host smart-dd53b219-6e23-4099-b8e9-0161bfee321b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470747750 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.3470747750
Directory /workspace/0.chip_sw_sram_ctrl_execution_main/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2934939920
Short name T291
Test name
Test status
Simulation time 6146595192 ps
CPU time 663.69 seconds
Started Jul 29 08:15:14 PM PDT 24
Finished Jul 29 08:26:18 PM PDT 24
Peak memory 609828 kb
Host smart-72817c76-b1e8-4552-b72c-6ad817b65e59
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934939920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr
l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw
_sram_ctrl_scrambled_access.2934939920
Directory /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.4281189351
Short name T1225
Test name
Test status
Simulation time 4281790015 ps
CPU time 689.53 seconds
Started Jul 29 08:16:48 PM PDT 24
Finished Jul 29 08:28:18 PM PDT 24
Peak memory 609620 kb
Host smart-d42adaf0-5ce6-4bf0-85c6-d5e423daff36
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s
w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281189351 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.4281189351
Directory /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3347512730
Short name T293
Test name
Test status
Simulation time 5263058579 ps
CPU time 569.68 seconds
Started Jul 29 08:16:19 PM PDT 24
Finished Jul 29 08:25:50 PM PDT 24
Peak memory 610812 kb
Host smart-24d2137e-99b5-4340-8ded-e0fe72875489
User root
Command /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk
_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347512730 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3347512730
Directory /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3246795038
Short name T1320
Test name
Test status
Simulation time 2588584926 ps
CPU time 180.47 seconds
Started Jul 29 08:25:42 PM PDT 24
Finished Jul 29 08:28:43 PM PDT 24
Peak memory 609660 kb
Host smart-b7ae287f-3795-4cd2-967e-fbd4786b2bd0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246795038 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.3246795038
Directory /workspace/0.chip_sw_sram_ctrl_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2488100171
Short name T1339
Test name
Test status
Simulation time 20345388053 ps
CPU time 3804.94 seconds
Started Jul 29 08:13:29 PM PDT 24
Finished Jul 29 09:16:55 PM PDT 24
Peak memory 610580 kb
Host smart-d218add1-1a6b-4d92-9650-15f01f85a37d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488100171 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.2488100171
Directory /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3993273516
Short name T758
Test name
Test status
Simulation time 4729146307 ps
CPU time 599.48 seconds
Started Jul 29 08:14:46 PM PDT 24
Finished Jul 29 08:24:47 PM PDT 24
Peak memory 613756 kb
Host smart-a0b6d6b0-7668-492f-8501-3ad66792ffe2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993273516 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.3993273516
Directory /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.2794461974
Short name T23
Test name
Test status
Simulation time 3794057820 ps
CPU time 384.52 seconds
Started Jul 29 08:15:41 PM PDT 24
Finished Jul 29 08:22:06 PM PDT 24
Peak memory 610024 kb
Host smart-6a18f225-3cb5-4fef-8638-7c609a800940
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794461974 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.2794461974
Directory /workspace/0.chip_sw_sysrst_ctrl_outputs/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.893418483
Short name T1294
Test name
Test status
Simulation time 23874252500 ps
CPU time 2209.5 seconds
Started Jul 29 08:15:26 PM PDT 24
Finished Jul 29 08:52:16 PM PDT 24
Peak memory 613108 kb
Host smart-7dbcefec-7b62-481d-84f6-141cc17c64ac
User root
Command /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89341848
3 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.893418483
Directory /workspace/0.chip_sw_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2807376498
Short name T37
Test name
Test status
Simulation time 5705416768 ps
CPU time 585.79 seconds
Started Jul 29 08:15:47 PM PDT 24
Finished Jul 29 08:25:34 PM PDT 24
Peak memory 610848 kb
Host smart-da57f9e5-aa90-44fd-90bc-d8cbb23298cf
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807376498 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2807376498
Directory /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2734033400
Short name T1228
Test name
Test status
Simulation time 3902897742 ps
CPU time 615.7 seconds
Started Jul 29 08:15:25 PM PDT 24
Finished Jul 29 08:25:40 PM PDT 24
Peak memory 624468 kb
Host smart-dd9015e7-2ef8-4c8e-944d-14e669fb78f1
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2734033400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.2734033400
Directory /workspace/0.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/0.chip_sw_uart_smoketest.1833416152
Short name T908
Test name
Test status
Simulation time 3090006068 ps
CPU time 187.47 seconds
Started Jul 29 08:25:15 PM PDT 24
Finished Jul 29 08:28:23 PM PDT 24
Peak memory 614928 kb
Host smart-c68319cb-5737-44de-9150-b37caf65746b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833416152 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_sw_uart_smoketest.1833416152
Directory /workspace/0.chip_sw_uart_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx.1297438720
Short name T1324
Test name
Test status
Simulation time 4427994256 ps
CPU time 748.28 seconds
Started Jul 29 08:16:21 PM PDT 24
Finished Jul 29 08:28:49 PM PDT 24
Peak memory 624160 kb
Host smart-b48204d2-7b99-47fd-a11a-e368d22ad5cf
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297438720 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.1297438720
Directory /workspace/0.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3901107791
Short name T1034
Test name
Test status
Simulation time 12448065161 ps
CPU time 3329.13 seconds
Started Jul 29 08:14:21 PM PDT 24
Finished Jul 29 09:09:51 PM PDT 24
Peak memory 624600 kb
Host smart-e5a6d94b-fb81-4148-8a6c-a57808b27543
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901107791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx
_alt_clk_freq.3901107791
Directory /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3256539531
Short name T332
Test name
Test status
Simulation time 4523109288 ps
CPU time 416.44 seconds
Started Jul 29 08:15:14 PM PDT 24
Finished Jul 29 08:22:11 PM PDT 24
Peak memory 619716 kb
Host smart-bc8ce407-3fef-416e-a2dc-8f828d89c907
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256539531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.3256539531
Directory /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3091373140
Short name T1371
Test name
Test status
Simulation time 4434706380 ps
CPU time 552.21 seconds
Started Jul 29 08:13:52 PM PDT 24
Finished Jul 29 08:23:05 PM PDT 24
Peak memory 624312 kb
Host smart-b261cbd2-c7c8-4d21-9935-b6de38dd1065
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091373140 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.3091373140
Directory /workspace/0.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1083845104
Short name T273
Test name
Test status
Simulation time 4160021400 ps
CPU time 503.21 seconds
Started Jul 29 08:15:11 PM PDT 24
Finished Jul 29 08:23:34 PM PDT 24
Peak memory 623616 kb
Host smart-1b942b29-7b51-4f78-abac-465c97d7100f
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083845104 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.1083845104
Directory /workspace/0.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3475783954
Short name T394
Test name
Test status
Simulation time 3361260917 ps
CPU time 417.35 seconds
Started Jul 29 08:17:11 PM PDT 24
Finished Jul 29 08:24:08 PM PDT 24
Peak memory 610052 kb
Host smart-39cb8fb6-575c-4f06-b6fc-ebdcfb834cb7
User root
Command /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475783954
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.3475783954
Directory /workspace/0.chip_sw_usb_ast_clk_calib/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_config_host.2743283575
Short name T20
Test name
Test status
Simulation time 8277035052 ps
CPU time 1734.74 seconds
Started Jul 29 08:13:20 PM PDT 24
Finished Jul 29 08:42:16 PM PDT 24
Peak memory 610180 kb
Host smart-644bdaa7-a68c-4b4b-a419-36ebebb6751f
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27432
83575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.2743283575
Directory /workspace/0.chip_sw_usbdev_config_host/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_dpi.4071371579
Short name T25
Test name
Test status
Simulation time 12011896868 ps
CPU time 2942.19 seconds
Started Jul 29 08:13:45 PM PDT 24
Finished Jul 29 09:02:48 PM PDT 24
Peak memory 610196 kb
Host smart-581dbc78-1289-4595-b40f-f5c7e01c7752
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=4071371579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.4071371579
Directory /workspace/0.chip_sw_usbdev_dpi/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_pullup.3224076544
Short name T72
Test name
Test status
Simulation time 3545402570 ps
CPU time 299.36 seconds
Started Jul 29 08:14:00 PM PDT 24
Finished Jul 29 08:18:59 PM PDT 24
Peak memory 609792 kb
Host smart-001ec10d-92ae-49ba-aa93-f7e07d888fe5
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224076544
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.3224076544
Directory /workspace/0.chip_sw_usbdev_pullup/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_setuprx.4129126947
Short name T1044
Test name
Test status
Simulation time 3817561360 ps
CPU time 608.4 seconds
Started Jul 29 08:15:56 PM PDT 24
Finished Jul 29 08:26:05 PM PDT 24
Peak memory 609792 kb
Host smart-4361029a-d949-4729-97eb-41239d213889
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412912694
7 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.4129126947
Directory /workspace/0.chip_sw_usbdev_setuprx/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_stream.3564127071
Short name T1112
Test name
Test status
Simulation time 18526462204 ps
CPU time 4003.03 seconds
Started Jul 29 08:15:14 PM PDT 24
Finished Jul 29 09:21:58 PM PDT 24
Peak memory 609064 kb
Host smart-641e7482-2402-4521-b354-5401f25e6efe
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru
les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3564127071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.3564127071
Directory /workspace/0.chip_sw_usbdev_stream/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_vbus.3205659959
Short name T1297
Test name
Test status
Simulation time 2730348900 ps
CPU time 189.28 seconds
Started Jul 29 08:13:45 PM PDT 24
Finished Jul 29 08:16:55 PM PDT 24
Peak memory 609848 kb
Host smart-bdd36476-42dd-4849-a463-be3bd95112cd
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205659959 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.3205659959
Directory /workspace/0.chip_sw_usbdev_vbus/latest

Test location /workspace/coverage/default/0.chip_tap_straps_prod.2590862512
Short name T968
Test name
Test status
Simulation time 3065288473 ps
CPU time 176.12 seconds
Started Jul 29 08:17:13 PM PDT 24
Finished Jul 29 08:20:09 PM PDT 24
Peak memory 621504 kb
Host smart-db9bfb6a-9651-408b-8c00-3f9b08112657
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2590862512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.2590862512
Directory /workspace/0.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_dev.4022281472
Short name T1214
Test name
Test status
Simulation time 15461399880 ps
CPU time 3502.54 seconds
Started Jul 29 08:28:31 PM PDT 24
Finished Jul 29 09:26:54 PM PDT 24
Peak memory 610296 kb
Host smart-2dee1d66-501b-474f-982d-65fcc8d56abd
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022281472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rom_e2e_asm_init_dev.4022281472
Directory /workspace/0.rom_e2e_asm_init_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_prod.1983621610
Short name T1198
Test name
Test status
Simulation time 15597506928 ps
CPU time 3640.67 seconds
Started Jul 29 08:28:33 PM PDT 24
Finished Jul 29 09:29:15 PM PDT 24
Peak memory 610316 kb
Host smart-02026469-8e0c-4b8e-a6f8-f36c248728de
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983621610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_
SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rom_e2e_asm_init_prod.1983621610
Directory /workspace/0.rom_e2e_asm_init_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.752114501
Short name T1334
Test name
Test status
Simulation time 15572808188 ps
CPU time 4252.39 seconds
Started Jul 29 08:29:10 PM PDT 24
Finished Jul 29 09:40:03 PM PDT 24
Peak memory 610368 kb
Host smart-f3819b1b-8551-4b0a-bee8-abfd1a383dac
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752114501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.rom_e2e_asm_init_prod_end.752114501
Directory /workspace/0.rom_e2e_asm_init_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_rma.2077419726
Short name T1076
Test name
Test status
Simulation time 15455424448 ps
CPU time 3731.37 seconds
Started Jul 29 08:30:26 PM PDT 24
Finished Jul 29 09:32:38 PM PDT 24
Peak memory 610344 kb
Host smart-8cdfec29-38cb-4144-90d4-20236c36023a
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077419726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rom_e2e_asm_init_rma.2077419726
Directory /workspace/0.rom_e2e_asm_init_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.820113492
Short name T915
Test name
Test status
Simulation time 11636171598 ps
CPU time 3043.05 seconds
Started Jul 29 08:30:30 PM PDT 24
Finished Jul 29 09:21:14 PM PDT 24
Peak memory 610372 kb
Host smart-29f5c42b-291b-4d70-a411-8b9e6e7f186e
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820113492 -assert nopostproc +UVM_TESTNAME=chip_base_tes
t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.rom_e2e_asm_init_test_unlocked0.820113492
Directory /workspace/0.rom_e2e_asm_init_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2254657266
Short name T1333
Test name
Test status
Simulation time 24564936520 ps
CPU time 6053.77 seconds
Started Jul 29 08:29:21 PM PDT 24
Finished Jul 29 10:10:16 PM PDT 24
Peak memory 610156 kb
Host smart-37f17866-aa7e-471c-9920-2c73659e1fd3
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2254657266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2254657266
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.190442558
Short name T1142
Test name
Test status
Simulation time 24687726688 ps
CPU time 6237.28 seconds
Started Jul 29 08:31:57 PM PDT 24
Finished Jul 29 10:15:55 PM PDT 24
Peak memory 610144 kb
Host smart-76009768-4864-4ffb-8f5e-52815506f21a
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=190442558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.190442558
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3523235156
Short name T391
Test name
Test status
Simulation time 23629047394 ps
CPU time 5827.59 seconds
Started Jul 29 08:31:15 PM PDT 24
Finished Jul 29 10:08:24 PM PDT 24
Peak memory 610092 kb
Host smart-7baf8a33-7e07-4ef1-a0e9-044640348d13
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3523235156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3523235156
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2223993944
Short name T390
Test name
Test status
Simulation time 18710033400 ps
CPU time 4434.38 seconds
Started Jul 29 08:28:22 PM PDT 24
Finished Jul 29 09:42:17 PM PDT 24
Peak memory 609988 kb
Host smart-8721ba0f-f6ba-46e7-8621-66aba4917976
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,
mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2223993944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2223993944
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.914929649
Short name T377
Test name
Test status
Simulation time 15448484020 ps
CPU time 4035.99 seconds
Started Jul 29 08:31:48 PM PDT 24
Finished Jul 29 09:39:05 PM PDT 24
Peak memory 610168 kb
Host smart-28d54ac7-5e83-4d70-85e6-cee4a2037198
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=914929649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.914929649
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.511889360
Short name T1031
Test name
Test status
Simulation time 14972641980 ps
CPU time 3847.36 seconds
Started Jul 29 08:32:50 PM PDT 24
Finished Jul 29 09:36:58 PM PDT 24
Peak memory 610112 kb
Host smart-4c48eae5-0641-492f-939d-0e217f30627b
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=511889360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.511889360
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3848643146
Short name T1060
Test name
Test status
Simulation time 16296141552 ps
CPU time 3841.08 seconds
Started Jul 29 08:30:09 PM PDT 24
Finished Jul 29 09:34:11 PM PDT 24
Peak memory 609936 kb
Host smart-0002d02a-1541-459f-a634-d5a7e40abf20
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3848643146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3848643146
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1487453541
Short name T1027
Test name
Test status
Simulation time 15012666812 ps
CPU time 3653.23 seconds
Started Jul 29 08:31:30 PM PDT 24
Finished Jul 29 09:32:24 PM PDT 24
Peak memory 610104 kb
Host smart-cb56677e-2c0d-4037-b942-7459163a6ae8
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1487453541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1487453541
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1739863825
Short name T1005
Test name
Test status
Simulation time 11899216148 ps
CPU time 2802.3 seconds
Started Jul 29 08:31:19 PM PDT 24
Finished Jul 29 09:18:02 PM PDT 24
Peak memory 610180 kb
Host smart-0fb70168-a698-4e08-ad9f-75b55296ad5b
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4,
mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1739863825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1739863825
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.688321479
Short name T1184
Test name
Test status
Simulation time 15231095910 ps
CPU time 4132.48 seconds
Started Jul 29 08:31:09 PM PDT 24
Finished Jul 29 09:40:02 PM PDT 24
Peak memory 609444 kb
Host smart-25a5bcf6-c7db-400f-9be9-8d5956fc9f5a
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688321479 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.688321479
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1060282828
Short name T1210
Test name
Test status
Simulation time 15005263306 ps
CPU time 3197.03 seconds
Started Jul 29 08:31:14 PM PDT 24
Finished Jul 29 09:24:32 PM PDT 24
Peak memory 610224 kb
Host smart-dc413d6d-d758-4489-a63c-bfee7b0262d2
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060282828
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1060282828
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3547327074
Short name T992
Test name
Test status
Simulation time 16163825562 ps
CPU time 3415.13 seconds
Started Jul 29 08:31:14 PM PDT 24
Finished Jul 29 09:28:10 PM PDT 24
Peak memory 609528 kb
Host smart-0ed4f3d4-3711-484a-a346-5870be5722ed
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354732
7074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3547327074
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1956386903
Short name T1243
Test name
Test status
Simulation time 15367436090 ps
CPU time 3063.74 seconds
Started Jul 29 08:29:30 PM PDT 24
Finished Jul 29 09:20:34 PM PDT 24
Peak memory 610224 kb
Host smart-331d1958-89a1-4b5f-9376-236c1966d1bc
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956386903
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1956386903
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1323496807
Short name T1267
Test name
Test status
Simulation time 11154474144 ps
CPU time 3103.45 seconds
Started Jul 29 08:28:50 PM PDT 24
Finished Jul 29 09:20:34 PM PDT 24
Peak memory 610268 kb
Host smart-e2a8458a-d06e-4bbe-aed1-0d3bea018f81
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1323496807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1323496807
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.2385735341
Short name T263
Test name
Test status
Simulation time 11408698954 ps
CPU time 1926.42 seconds
Started Jul 29 08:26:27 PM PDT 24
Finished Jul 29 08:58:35 PM PDT 24
Peak memory 624552 kb
Host smart-cf89204e-d2de-4205-a30e-18844d4996d3
User root
Command /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23857
35341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.2385735341
Directory /workspace/0.rom_e2e_jtag_debug_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.1878161500
Short name T262
Test name
Test status
Simulation time 11404841386 ps
CPU time 1839.34 seconds
Started Jul 29 08:26:16 PM PDT 24
Finished Jul 29 08:56:57 PM PDT 24
Peak memory 624412 kb
Host smart-445d66f5-48f9-4d8f-b0d5-3a3372a46c5d
User root
Command /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1878161500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.1878161500
Directory /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.1756137361
Short name T269
Test name
Test status
Simulation time 24314302055 ps
CPU time 2762.31 seconds
Started Jul 29 08:26:43 PM PDT 24
Finished Jul 29 09:12:45 PM PDT 24
Peak memory 620404 kb
Host smart-689eed9c-1ec4-4081-a015-79a4a1abff0a
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di
sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1756137361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.1756137361
Directory /workspace/0.rom_e2e_jtag_inject_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.971959097
Short name T261
Test name
Test status
Simulation time 24874812214 ps
CPU time 2243.68 seconds
Started Jul 29 08:27:27 PM PDT 24
Finished Jul 29 09:04:53 PM PDT 24
Peak memory 623884 kb
Host smart-a49c048b-f2cf-45b8-9ac5-8e266ffd1ecc
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di
sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=971959097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.971959097
Directory /workspace/0.rom_e2e_jtag_inject_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2033855418
Short name T454
Test name
Test status
Simulation time 24682829473 ps
CPU time 2708.66 seconds
Started Jul 29 08:26:32 PM PDT 24
Finished Jul 29 09:11:42 PM PDT 24
Peak memory 620416 kb
Host smart-2ce05646-2920-4426-b573-1680616380ae
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock
ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033855418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_
inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject
_test_unlocked0.2033855418
Directory /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3507814773
Short name T967
Test name
Test status
Simulation time 15069762536 ps
CPU time 4373.65 seconds
Started Jul 29 08:28:58 PM PDT 24
Finished Jul 29 09:41:52 PM PDT 24
Peak memory 610264 kb
Host smart-a0949bc4-f153-4e0c-aa34-eae64e56349b
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid
_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507814773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip
_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in
it_rom_ext_invalid_meas.3507814773
Directory /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3586475743
Short name T1136
Test name
Test status
Simulation time 15098722078 ps
CPU time 4093.81 seconds
Started Jul 29 08:30:07 PM PDT 24
Finished Jul 29 09:38:22 PM PDT 24
Peak memory 609980 kb
Host smart-4aec9b98-29be-45b1-beec-abdaef968819
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:
new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586475743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.3586475743
Directory /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2703477912
Short name T1075
Test name
Test status
Simulation time 15310600216 ps
CPU time 4009.13 seconds
Started Jul 29 08:29:48 PM PDT 24
Finished Jul 29 09:36:38 PM PDT 24
Peak memory 609988 kb
Host smart-3d633f68-be02-42f9-9d82-65565947a820
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas
:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703477912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext
_no_meas.2703477912
Directory /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location /workspace/coverage/default/0.rom_e2e_self_hash.2320728661
Short name T959
Test name
Test status
Simulation time 26475371212 ps
CPU time 6071.1 seconds
Started Jul 29 08:29:43 PM PDT 24
Finished Jul 29 10:10:55 PM PDT 24
Peak memory 610188 kb
Host smart-26de6f12-6c40-428e-9b9e-347f77caa688
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r
ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320728661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.2320728661
Directory /workspace/0.rom_e2e_self_hash/latest

Test location /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1066833727
Short name T277
Test name
Test status
Simulation time 14392422675 ps
CPU time 3965.62 seconds
Started Jul 29 08:22:22 PM PDT 24
Finished Jul 29 09:28:28 PM PDT 24
Peak memory 611404 kb
Host smart-91eb9060-bbff-4882-b466-36b40d6ca9bc
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne
w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066833727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu
tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_
shutdown_exception_c.1066833727
Directory /workspace/0.rom_e2e_shutdown_exception_c/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2489926898
Short name T1344
Test name
Test status
Simulation time 23571409226 ps
CPU time 6086.39 seconds
Started Jul 29 08:30:21 PM PDT 24
Finished Jul 29 10:11:48 PM PDT 24
Peak memory 610496 kb
Host smart-ed90d7c0-e1c2-4ec9-aec7-89b13cbbb1dc
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev
:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2489926898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b
ad_dev.2489926898
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.236504915
Short name T272
Test name
Test status
Simulation time 23729619184 ps
CPU time 4995.55 seconds
Started Jul 29 08:29:53 PM PDT 24
Finished Jul 29 09:53:09 PM PDT 24
Peak memory 609380 kb
Host smart-ab4d568e-4708-49f5-8d96-8bc840ff662d
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p
rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=236504915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b
_bad_prod.236504915
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2690798210
Short name T1300
Test name
Test status
Simulation time 23651369382 ps
CPU time 5634.16 seconds
Started Jul 29 08:30:14 PM PDT 24
Finished Jul 29 10:04:09 PM PDT 24
Peak memory 610124 kb
Host smart-816b4586-c965-4afb-8c8a-3f5821615e11
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p
rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=2690798210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_
bad_b_bad_prod_end.2690798210
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3346602303
Short name T1048
Test name
Test status
Simulation time 22664305173 ps
CPU time 5401.48 seconds
Started Jul 29 08:31:22 PM PDT 24
Finished Jul 29 10:01:25 PM PDT 24
Peak memory 609376 kb
Host smart-f417c33d-37e1-4204-8240-7f07eba7c30b
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r
ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=3346602303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b
_bad_rma.3346602303
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.4045644831
Short name T1153
Test name
Test status
Simulation time 18172498777 ps
CPU time 5002.07 seconds
Started Jul 29 08:31:00 PM PDT 24
Finished Jul 29 09:54:23 PM PDT 24
Peak memory 609588 kb
Host smart-d4386791-f97e-423f-a110-fb9f50e204e8
User root
Command /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t
est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4045644831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b
_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw
ays_a_bad_b_bad_test_unlocked0.4045644831
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3049344837
Short name T1304
Test name
Test status
Simulation time 14978301214 ps
CPU time 3724.93 seconds
Started Jul 29 08:29:43 PM PDT 24
Finished Jul 29 09:31:49 PM PDT 24
Peak memory 609368 kb
Host smart-57b9635d-f59a-447b-b27e-4b7c41cc04d9
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049344837 -assert nopostproc +UVM_TESTNAME=chip_base_
test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3049344837
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2492116105
Short name T1230
Test name
Test status
Simulation time 14245635644 ps
CPU time 2969.85 seconds
Started Jul 29 08:28:36 PM PDT 24
Finished Jul 29 09:18:06 PM PDT 24
Peak memory 609344 kb
Host smart-8eb60831-420e-4c41-a649-adadf9ed7a5b
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492116105 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2492116105
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2797393033
Short name T275
Test name
Test status
Simulation time 14904902940 ps
CPU time 4429.91 seconds
Started Jul 29 08:29:39 PM PDT 24
Finished Jul 29 09:43:30 PM PDT 24
Peak memory 609348 kb
Host smart-c55bfe32-8032-4257-9a24-ef54418d33c5
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797393033 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2797393033
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.365238482
Short name T274
Test name
Test status
Simulation time 14210773119 ps
CPU time 4351.42 seconds
Started Jul 29 08:30:04 PM PDT 24
Finished Jul 29 09:42:36 PM PDT 24
Peak memory 611264 kb
Host smart-6748fa5d-54bc-4c7b-ab89-f43b8c5e370d
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365238482 -assert nopostproc +UVM_TESTNAME=chip_base_
test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.365238482
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.598131544
Short name T964
Test name
Test status
Simulation time 10934110768 ps
CPU time 2794.97 seconds
Started Jul 29 08:27:21 PM PDT 24
Finished Jul 29 09:13:57 PM PDT 24
Peak memory 610784 kb
Host smart-f1f110e1-f88d-4eeb-a270-bf36aca26d43
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598131544 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.598131544
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.57825709
Short name T428
Test name
Test status
Simulation time 14618852717 ps
CPU time 4344.21 seconds
Started Jul 29 08:29:45 PM PDT 24
Finished Jul 29 09:42:09 PM PDT 24
Peak memory 610120 kb
Host smart-c8d21a8b-861b-463c-b714-aba773ca4774
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57825709 -assert nopostproc +UVM_TESTNAME=chip_base_te
st +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.57825709
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2454954689
Short name T929
Test name
Test status
Simulation time 14966647747 ps
CPU time 3436.19 seconds
Started Jul 29 08:28:48 PM PDT 24
Finished Jul 29 09:26:05 PM PDT 24
Peak memory 610328 kb
Host smart-f1bdcd54-4ef3-4e9a-9f80-a7fc6b59bf7a
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454954689 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2454954689
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.196879276
Short name T1157
Test name
Test status
Simulation time 14657435828 ps
CPU time 2779.36 seconds
Started Jul 29 08:29:04 PM PDT 24
Finished Jul 29 09:15:24 PM PDT 24
Peak memory 610188 kb
Host smart-f3d85126-5540-468f-9df9-d08204104273
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196879276 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.196879276
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.229476152
Short name T925
Test name
Test status
Simulation time 14325252648 ps
CPU time 3454.86 seconds
Started Jul 29 08:31:50 PM PDT 24
Finished Jul 29 09:29:25 PM PDT 24
Peak memory 611292 kb
Host smart-49beb53e-d8dd-4e10-bb37-a2da33579810
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229476152 -assert nopostproc +UVM_TESTNAME=chip_base_
test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.229476152
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2237641467
Short name T173
Test name
Test status
Simulation time 11457965384 ps
CPU time 2637.12 seconds
Started Jul 29 08:28:18 PM PDT 24
Finished Jul 29 09:12:16 PM PDT 24
Peak memory 609704 kb
Host smart-a5833d09-7b67-4fad-8db9-42f36440cea2
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237641467 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2237641467
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_smoke.3765070468
Short name T1059
Test name
Test status
Simulation time 14544363948 ps
CPU time 4236.63 seconds
Started Jul 29 08:21:56 PM PDT 24
Finished Jul 29 09:32:34 PM PDT 24
Peak memory 609940 kb
Host smart-df06d627-f245-4719-bb08-3fd8448681a9
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img
_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to
p/hw/dv/tools/sim.tcl +ntb_random_seed=3765070468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.3765070468
Directory /workspace/0.rom_e2e_smoke/latest

Test location /workspace/coverage/default/0.rom_e2e_static_critical.3147428138
Short name T1144
Test name
Test status
Simulation time 17027931210 ps
CPU time 3978.01 seconds
Started Jul 29 08:29:16 PM PDT 24
Finished Jul 29 09:35:35 PM PDT 24
Peak memory 610244 kb
Host smart-5f8720f3-ffaa-4a61-aa31-fde66760663a
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul
es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147428138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.3147428138
Directory /workspace/0.rom_e2e_static_critical/latest

Test location /workspace/coverage/default/0.rom_keymgr_functest.1744638113
Short name T972
Test name
Test status
Simulation time 4207894956 ps
CPU time 653.91 seconds
Started Jul 29 08:25:37 PM PDT 24
Finished Jul 29 08:36:32 PM PDT 24
Peak memory 609960 kb
Host smart-9bb6a783-8dd7-49d8-9241-25815df5f197
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744638113 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.1744638113
Directory /workspace/0.rom_keymgr_functest/latest

Test location /workspace/coverage/default/0.rom_raw_unlock.1116272698
Short name T748
Test name
Test status
Simulation time 6195176593 ps
CPU time 286.85 seconds
Started Jul 29 08:25:50 PM PDT 24
Finished Jul 29 08:30:37 PM PDT 24
Peak memory 619824 kb
Host smart-55d12a47-d936-400a-bcaf-303fae4eba82
User root
Command /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE
xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1116272698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.1116272698
Directory /workspace/0.rom_raw_unlock/latest

Test location /workspace/coverage/default/0.rom_volatile_raw_unlock.2711571803
Short name T1374
Test name
Test status
Simulation time 2661814130 ps
CPU time 135.72 seconds
Started Jul 29 08:24:26 PM PDT 24
Finished Jul 29 08:26:42 PM PDT 24
Peak memory 617560 kb
Host smart-48657735-eeb2-484f-a036-46664e5a617f
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1
+sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711571803 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.2711571803
Directory /workspace/0.rom_volatile_raw_unlock/latest

Test location /workspace/coverage/default/1.chip_jtag_mem_access.1354964948
Short name T208
Test name
Test status
Simulation time 13621978000 ps
CPU time 1905.14 seconds
Started Jul 29 08:19:15 PM PDT 24
Finished Jul 29 08:51:00 PM PDT 24
Peak memory 607928 kb
Host smart-24aa5120-1d33-40b4-929d-8257a507e599
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354964948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_
mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.1
354964948
Directory /workspace/1.chip_jtag_mem_access/latest

Test location /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.220602239
Short name T409
Test name
Test status
Simulation time 3503003680 ps
CPU time 463.53 seconds
Started Jul 29 08:27:45 PM PDT 24
Finished Jul 29 08:35:29 PM PDT 24
Peak memory 620048 kb
Host smart-d34ef3e1-289f-4a5b-8238-ddfc43c19ee2
User root
Command /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2
20602239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.220602239
Directory /workspace/1.chip_rv_dm_ndm_reset_req/latest

Test location /workspace/coverage/default/1.chip_sival_flash_info_access.3070137611
Short name T1348
Test name
Test status
Simulation time 2465603112 ps
CPU time 350.18 seconds
Started Jul 29 08:26:58 PM PDT 24
Finished Jul 29 08:32:48 PM PDT 24
Peak memory 609920 kb
Host smart-38b97aad-39e7-4a7b-917c-f78648bb4a1f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=3070137611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.3070137611
Directory /workspace/1.chip_sival_flash_info_access/latest

Test location /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2011575544
Short name T1292
Test name
Test status
Simulation time 18005019780 ps
CPU time 407.25 seconds
Started Jul 29 08:27:04 PM PDT 24
Finished Jul 29 08:33:52 PM PDT 24
Peak memory 618984 kb
Host smart-0a474fe2-104f-4f09-9ccc-4d5525b3ab5b
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2011575544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2011575544
Directory /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_aes_enc.4270955110
Short name T1195
Test name
Test status
Simulation time 3330335732 ps
CPU time 380.74 seconds
Started Jul 29 08:29:58 PM PDT 24
Finished Jul 29 08:36:21 PM PDT 24
Peak memory 609244 kb
Host smart-f3843cc2-1b7b-4d50-8b0c-b1ccf78b39a3
User root
Command /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270955110 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.4270955110
Directory /workspace/1.chip_sw_aes_enc/latest

Test location /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1703343760
Short name T1208
Test name
Test status
Simulation time 3521872498 ps
CPU time 325.34 seconds
Started Jul 29 08:29:43 PM PDT 24
Finished Jul 29 08:35:09 PM PDT 24
Peak memory 608496 kb
Host smart-e9edfea8-14c1-496c-b5ce-7fa646c7f3d8
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703
343760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.1703343760
Directory /workspace/1.chip_sw_aes_enc_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.4044787395
Short name T971
Test name
Test status
Simulation time 3650065718 ps
CPU time 212.15 seconds
Started Jul 29 08:27:34 PM PDT 24
Finished Jul 29 08:31:06 PM PDT 24
Peak memory 608764 kb
Host smart-173e9d43-b1c2-440a-8775-53580adde581
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4044787395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.4044787395
Directory /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_aes_entropy.2304747040
Short name T379
Test name
Test status
Simulation time 3454594800 ps
CPU time 215.32 seconds
Started Jul 29 08:28:45 PM PDT 24
Finished Jul 29 08:32:21 PM PDT 24
Peak memory 609692 kb
Host smart-1365ac5f-1abf-4f2a-a9f8-7aea50026527
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304747040 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.2304747040
Directory /workspace/1.chip_sw_aes_entropy/latest

Test location /workspace/coverage/default/1.chip_sw_aes_idle.3029783556
Short name T912
Test name
Test status
Simulation time 2783584324 ps
CPU time 190.67 seconds
Started Jul 29 08:30:27 PM PDT 24
Finished Jul 29 08:33:38 PM PDT 24
Peak memory 609660 kb
Host smart-19b11546-4993-476e-aa5e-4b9047d274cb
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029783556 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.3029783556
Directory /workspace/1.chip_sw_aes_idle/latest

Test location /workspace/coverage/default/1.chip_sw_aes_masking_off.4087564990
Short name T703
Test name
Test status
Simulation time 2470397162 ps
CPU time 245.15 seconds
Started Jul 29 08:28:54 PM PDT 24
Finished Jul 29 08:33:00 PM PDT 24
Peak memory 610172 kb
Host smart-c712d356-2817-4fb3-8374-907a2915795d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087564990 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.4087564990
Directory /workspace/1.chip_sw_aes_masking_off/latest

Test location /workspace/coverage/default/1.chip_sw_aes_smoketest.2766097750
Short name T977
Test name
Test status
Simulation time 2783440040 ps
CPU time 393.24 seconds
Started Jul 29 08:34:59 PM PDT 24
Finished Jul 29 08:41:33 PM PDT 24
Peak memory 608400 kb
Host smart-c492aea3-caa0-4a9e-a320-524b2559f5ed
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766097750 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_aes_smoketest.2766097750
Directory /workspace/1.chip_sw_aes_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_entropy.2431185671
Short name T84
Test name
Test status
Simulation time 3468561657 ps
CPU time 288.12 seconds
Started Jul 29 08:29:56 PM PDT 24
Finished Jul 29 08:34:44 PM PDT 24
Peak memory 609692 kb
Host smart-b4b2eb51-2dac-4c35-a689-adc0269aa22e
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2431185671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.2431185671
Directory /workspace/1.chip_sw_alert_handler_entropy/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_escalation.714080672
Short name T227
Test name
Test status
Simulation time 3967887160 ps
CPU time 489.03 seconds
Started Jul 29 08:31:32 PM PDT 24
Finished Jul 29 08:39:42 PM PDT 24
Peak memory 619352 kb
Host smart-0fdf47e6-8a94-44b6-b98f-d109e56b6787
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=714080672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.714080672
Directory /workspace/1.chip_sw_alert_handler_escalation/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3987018580
Short name T271
Test name
Test status
Simulation time 7866456344 ps
CPU time 1828.34 seconds
Started Jul 29 08:30:59 PM PDT 24
Finished Jul 29 09:01:28 PM PDT 24
Peak memory 610308 kb
Host smart-83143db5-445e-4066-b331-f4bce26759a6
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3987018580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.3987018580
Directory /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2090555281
Short name T215
Test name
Test status
Simulation time 7502679540 ps
CPU time 1664.33 seconds
Started Jul 29 08:31:40 PM PDT 24
Finished Jul 29 08:59:25 PM PDT 24
Peak memory 610268 kb
Host smart-ba0f2057-f97a-4ef2-bf06-0c0e265e8da8
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2090555281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg
le.2090555281
Directory /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1353493325
Short name T1240
Test name
Test status
Simulation time 11277533932 ps
CPU time 1383.02 seconds
Started Jul 29 08:31:44 PM PDT 24
Finished Jul 29 08:54:47 PM PDT 24
Peak memory 611000 kb
Host smart-82d0463b-9710-4957-9857-c1afdd7bcb26
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler
_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353493325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han
dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.chip_sw_alert_handler_lpg_sleep_mode_pings.1353493325
Directory /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.285466077
Short name T762
Test name
Test status
Simulation time 8100781100 ps
CPU time 1588.83 seconds
Started Jul 29 08:30:59 PM PDT 24
Finished Jul 29 08:57:29 PM PDT 24
Peak memory 610044 kb
Host smart-f316059e-76f5-46c3-a96e-daa5be26acf3
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=285466077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.285466077
Directory /workspace/1.chip_sw_alert_handler_ping_ok/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.890767652
Short name T381
Test name
Test status
Simulation time 5520620456 ps
CPU time 592.92 seconds
Started Jul 29 08:31:44 PM PDT 24
Finished Jul 29 08:41:37 PM PDT 24
Peak memory 610196 kb
Host smart-feeb2579-ad3c-40c8-be16-4de46be36a1e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=890767652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.890767652
Directory /workspace/1.chip_sw_alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3907767090
Short name T85
Test name
Test status
Simulation time 255999701268 ps
CPU time 10979.5 seconds
Started Jul 29 08:30:49 PM PDT 24
Finished Jul 29 11:33:51 PM PDT 24
Peak memory 610764 kb
Host smart-376defc1-fd18-45c3-a210-84ced41b423f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907767090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3907767090
Directory /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_irq.2123875640
Short name T280
Test name
Test status
Simulation time 4079704446 ps
CPU time 417.57 seconds
Started Jul 29 08:27:15 PM PDT 24
Finished Jul 29 08:34:12 PM PDT 24
Peak memory 609528 kb
Host smart-299034b4-48b0-4350-9ec0-b3aa1ceaafe3
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123875640 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.2123875640
Directory /workspace/1.chip_sw_aon_timer_irq/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.713804736
Short name T1029
Test name
Test status
Simulation time 6866137284 ps
CPU time 434.96 seconds
Started Jul 29 08:27:49 PM PDT 24
Finished Jul 29 08:35:04 PM PDT 24
Peak memory 609168 kb
Host smart-a81f5bec-cd83-4fa9-a8e4-8ab5d8d75388
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=713804736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.713804736
Directory /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3431723602
Short name T988
Test name
Test status
Simulation time 3352063312 ps
CPU time 369.24 seconds
Started Jul 29 08:29:04 PM PDT 24
Finished Jul 29 08:35:13 PM PDT 24
Peak memory 609580 kb
Host smart-ba59c6a2-1ed1-49f8-a998-5aaef164bf25
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431723602 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_aon_timer_smoketest.3431723602
Directory /workspace/1.chip_sw_aon_timer_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.137381846
Short name T1096
Test name
Test status
Simulation time 8768947444 ps
CPU time 1057.96 seconds
Started Jul 29 08:30:18 PM PDT 24
Finished Jul 29 08:47:56 PM PDT 24
Peak memory 610252 kb
Host smart-8d828a4f-d92e-40c6-9143-d56cad0f8ca5
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
137381846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.137381846
Directory /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.4208684826
Short name T1188
Test name
Test status
Simulation time 5705120554 ps
CPU time 711.27 seconds
Started Jul 29 08:27:21 PM PDT 24
Finished Jul 29 08:39:14 PM PDT 24
Peak memory 610432 kb
Host smart-473a7ef2-6c8a-49ac-8f18-be9a6c92c5d1
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4208684826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.4208684826
Directory /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location /workspace/coverage/default/1.chip_sw_ast_clk_outputs.3825939139
Short name T749
Test name
Test status
Simulation time 8075157258 ps
CPU time 1062.88 seconds
Started Jul 29 08:30:01 PM PDT 24
Finished Jul 29 08:47:45 PM PDT 24
Peak memory 616296 kb
Host smart-4199515f-fb09-4b7d-a07f-36314576b1ba
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825939139 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.3825939139
Directory /workspace/1.chip_sw_ast_clk_outputs/latest

Test location /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.3169556109
Short name T119
Test name
Test status
Simulation time 28769543574 ps
CPU time 4888.32 seconds
Started Jul 29 08:28:48 PM PDT 24
Finished Jul 29 09:50:17 PM PDT 24
Peak memory 610788 kb
Host smart-6ea759cc-8d7c-4e04-a4ad-9790490d9fa9
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169556109
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.3169556109
Directory /workspace/1.chip_sw_ast_clk_rst_inputs/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2887652814
Short name T1350
Test name
Test status
Simulation time 12146819077 ps
CPU time 748.82 seconds
Started Jul 29 08:27:44 PM PDT 24
Finished Jul 29 08:40:14 PM PDT 24
Peak memory 621532 kb
Host smart-368f3286-c7f1-42b5-a320-77468f832078
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=2887652814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.2887652814
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3114615621
Short name T1338
Test name
Test status
Simulation time 4834498960 ps
CPU time 921.19 seconds
Started Jul 29 08:27:29 PM PDT 24
Finished Jul 29 08:42:50 PM PDT 24
Peak memory 612928 kb
Host smart-08fe125e-1c24-4e3a-b3fa-34f90f1dbfb6
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114615621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_dev.3114615621
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.686108954
Short name T1156
Test name
Test status
Simulation time 3718949300 ps
CPU time 631.85 seconds
Started Jul 29 08:27:45 PM PDT 24
Finished Jul 29 08:38:17 PM PDT 24
Peak memory 612020 kb
Host smart-6711cf4e-8322-4b83-89e2-6f57dce1cc03
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686108954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl
kmgr_external_clk_src_for_sw_fast_rma.686108954
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2367201128
Short name T1028
Test name
Test status
Simulation time 3952990840 ps
CPU time 615.51 seconds
Started Jul 29 08:25:12 PM PDT 24
Finished Jul 29 08:35:27 PM PDT 24
Peak memory 613144 kb
Host smart-6973a0ca-1e28-4cd5-a915-97b3bbd7710a
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367201128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2367201128
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.980329603
Short name T1098
Test name
Test status
Simulation time 4177654932 ps
CPU time 671.94 seconds
Started Jul 29 08:29:23 PM PDT 24
Finished Jul 29 08:40:35 PM PDT 24
Peak memory 613056 kb
Host smart-02652370-1ef7-4ef1-844c-522ab368316d
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980329603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl
kmgr_external_clk_src_for_sw_slow_dev.980329603
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1466482110
Short name T1078
Test name
Test status
Simulation time 5112250552 ps
CPU time 763.1 seconds
Started Jul 29 08:28:17 PM PDT 24
Finished Jul 29 08:41:02 PM PDT 24
Peak memory 613132 kb
Host smart-ac74b353-2c7b-47fb-8887-795b558897e7
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466482110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_rma.1466482110
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.776994825
Short name T931
Test name
Test status
Simulation time 5093627008 ps
CPU time 698.52 seconds
Started Jul 29 08:26:52 PM PDT 24
Finished Jul 29 08:38:31 PM PDT 24
Peak memory 612960 kb
Host smart-7cb8e45b-77ea-4009-86ed-4a7dbe8c1770
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776994825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM
_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.776994825
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_jitter.1808898292
Short name T449
Test name
Test status
Simulation time 2980360881 ps
CPU time 286.13 seconds
Started Jul 29 08:33:18 PM PDT 24
Finished Jul 29 08:38:04 PM PDT 24
Peak memory 608372 kb
Host smart-c3f1b282-0e39-44ea-bef0-71a33d4e53d8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808898292 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_clkmgr_jitter.1808898292
Directory /workspace/1.chip_sw_clkmgr_jitter/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.4128608895
Short name T917
Test name
Test status
Simulation time 3703178974 ps
CPU time 599.86 seconds
Started Jul 29 08:27:03 PM PDT 24
Finished Jul 29 08:37:03 PM PDT 24
Peak memory 609668 kb
Host smart-3b502a1e-1b7c-4864-9158-d7292a75d6fe
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128608895 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.4128608895
Directory /workspace/1.chip_sw_clkmgr_jitter_frequency/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.4202408562
Short name T1116
Test name
Test status
Simulation time 2988633431 ps
CPU time 295.37 seconds
Started Jul 29 08:28:23 PM PDT 24
Finished Jul 29 08:33:20 PM PDT 24
Peak memory 609804 kb
Host smart-0ebe9f9c-c05e-4444-9e93-05fd28ecd91f
User root
Command /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202408562 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.4202408562
Directory /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2794968980
Short name T1183
Test name
Test status
Simulation time 5931156800 ps
CPU time 613.94 seconds
Started Jul 29 08:30:55 PM PDT 24
Finished Jul 29 08:41:10 PM PDT 24
Peak memory 610372 kb
Host smart-905f2460-6035-41ec-9b79-763edacc5da9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794968980 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.2794968980
Directory /workspace/1.chip_sw_clkmgr_off_aes_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2740082173
Short name T979
Test name
Test status
Simulation time 5756345096 ps
CPU time 585.66 seconds
Started Jul 29 08:31:52 PM PDT 24
Finished Jul 29 08:41:38 PM PDT 24
Peak memory 610488 kb
Host smart-af1353bc-e05a-4b25-9a07-1a081cfd7935
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740082173 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.2740082173
Directory /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3632726304
Short name T1172
Test name
Test status
Simulation time 3874366044 ps
CPU time 430.25 seconds
Started Jul 29 08:31:25 PM PDT 24
Finished Jul 29 08:38:36 PM PDT 24
Peak memory 609896 kb
Host smart-0bbea941-985f-477d-994c-b5d967e0e558
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632726304 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.3632726304
Directory /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3064367299
Short name T1376
Test name
Test status
Simulation time 4645571822 ps
CPU time 483.81 seconds
Started Jul 29 08:28:54 PM PDT 24
Finished Jul 29 08:36:59 PM PDT 24
Peak memory 610480 kb
Host smart-4cfe60f1-e2f3-4aab-ab23-ba232622096a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064367299 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.3064367299
Directory /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3434201770
Short name T1329
Test name
Test status
Simulation time 9603510608 ps
CPU time 1278.21 seconds
Started Jul 29 08:31:14 PM PDT 24
Finished Jul 29 08:52:32 PM PDT 24
Peak memory 610484 kb
Host smart-97edb854-33bb-4c46-b8df-d230df773df3
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434201770
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.3434201770
Directory /workspace/1.chip_sw_clkmgr_off_peri/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2271520891
Short name T1217
Test name
Test status
Simulation time 3072753548 ps
CPU time 479.63 seconds
Started Jul 29 08:32:40 PM PDT 24
Finished Jul 29 08:40:40 PM PDT 24
Peak memory 609812 kb
Host smart-3ef1900e-2194-4f32-980c-412f64c70e91
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271520891 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.2271520891
Directory /workspace/1.chip_sw_clkmgr_reset_frequency/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2575611477
Short name T909
Test name
Test status
Simulation time 4497588400 ps
CPU time 506.79 seconds
Started Jul 29 08:26:29 PM PDT 24
Finished Jul 29 08:34:56 PM PDT 24
Peak memory 610300 kb
Host smart-4e702b37-c7f2-4bfd-8a8c-9f45d3a3229c
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575611477 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.2575611477
Directory /workspace/1.chip_sw_clkmgr_sleep_frequency/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3061033858
Short name T981
Test name
Test status
Simulation time 3376818440 ps
CPU time 254.23 seconds
Started Jul 29 08:30:13 PM PDT 24
Finished Jul 29 08:34:27 PM PDT 24
Peak memory 609528 kb
Host smart-18cc84d8-3636-4446-bd73-c04ac1c40cd5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061033858 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.chip_sw_clkmgr_smoketest.3061033858
Directory /workspace/1.chip_sw_clkmgr_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1438975377
Short name T1221
Test name
Test status
Simulation time 12032982680 ps
CPU time 2535.02 seconds
Started Jul 29 08:26:23 PM PDT 24
Finished Jul 29 09:08:38 PM PDT 24
Peak memory 610380 kb
Host smart-f3ad2bd6-c95a-42a5-be5c-4073f65e8262
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438975377 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.1438975377
Directory /workspace/1.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3437844781
Short name T127
Test name
Test status
Simulation time 21401991249 ps
CPU time 3539.47 seconds
Started Jul 29 08:28:54 PM PDT 24
Finished Jul 29 09:27:54 PM PDT 24
Peak memory 610340 kb
Host smart-f4aa82de-cb80-472e-8603-3d186fb0ab16
User root
Command /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_
cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3437844781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.3437844781
Directory /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3487410502
Short name T194
Test name
Test status
Simulation time 4611458408 ps
CPU time 396.02 seconds
Started Jul 29 08:30:37 PM PDT 24
Finished Jul 29 08:37:13 PM PDT 24
Peak memory 610900 kb
Host smart-0bfea8b2-1f3b-4c74-8fd8-6eef60b2e908
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34874
10502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.3487410502
Directory /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_kat_test.237349777
Short name T990
Test name
Test status
Simulation time 2754130996 ps
CPU time 311.95 seconds
Started Jul 29 08:28:49 PM PDT 24
Finished Jul 29 08:34:02 PM PDT 24
Peak memory 609412 kb
Host smart-d2e8c59a-b864-47af-b0da-c80065188a1c
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237349777 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.237349777
Directory /workspace/1.chip_sw_csrng_kat_test/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2906900184
Short name T1000
Test name
Test status
Simulation time 6810696280 ps
CPU time 597.37 seconds
Started Jul 29 08:30:49 PM PDT 24
Finished Jul 29 08:40:46 PM PDT 24
Peak memory 611076 kb
Host smart-14727c21-5e8b-4fea-ad4b-6050708e610f
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima
ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906900184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_
lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr
ng_lc_hw_debug_en_test.2906900184
Directory /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_smoketest.517648895
Short name T916
Test name
Test status
Simulation time 3136413752 ps
CPU time 287.35 seconds
Started Jul 29 08:31:51 PM PDT 24
Finished Jul 29 08:36:39 PM PDT 24
Peak memory 609652 kb
Host smart-75a268f5-5580-4878-bc8a-bbb8e0ff3aaa
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517648895 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_csrng_smoketest.517648895
Directory /workspace/1.chip_sw_csrng_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_edn_auto_mode.1056587228
Short name T1023
Test name
Test status
Simulation time 4833650232 ps
CPU time 1137.63 seconds
Started Jul 29 08:29:33 PM PDT 24
Finished Jul 29 08:48:32 PM PDT 24
Peak memory 610064 kb
Host smart-566b003b-f09a-40fc-836e-5f33655b52fb
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056587228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_
auto_mode.1056587228
Directory /workspace/1.chip_sw_edn_auto_mode/latest

Test location /workspace/coverage/default/1.chip_sw_edn_boot_mode.2188931417
Short name T122
Test name
Test status
Simulation time 2884388588 ps
CPU time 622.19 seconds
Started Jul 29 08:32:30 PM PDT 24
Finished Jul 29 08:42:54 PM PDT 24
Peak memory 609988 kb
Host smart-56b919ba-88a6-45e4-bb27-237bf530c9c8
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188931417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_
boot_mode.2188931417
Directory /workspace/1.chip_sw_edn_boot_mode/latest

Test location /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2108480528
Short name T462
Test name
Test status
Simulation time 5905003132 ps
CPU time 901.19 seconds
Started Jul 29 08:30:59 PM PDT 24
Finished Jul 29 08:46:01 PM PDT 24
Peak memory 610984 kb
Host smart-69ca80cd-1974-403e-9670-90a2856668e5
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed
n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2108480528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.2108480528
Directory /workspace/1.chip_sw_edn_entropy_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3628576629
Short name T110
Test name
Test status
Simulation time 6606269212 ps
CPU time 1206.88 seconds
Started Jul 29 08:28:24 PM PDT 24
Finished Jul 29 08:48:31 PM PDT 24
Peak memory 610944 kb
Host smart-45778fc8-14f5-45ab-b556-e582dbc3c519
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e
ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628576629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.3628576629
Directory /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest

Test location /workspace/coverage/default/1.chip_sw_edn_kat.3424463896
Short name T707
Test name
Test status
Simulation time 2982084328 ps
CPU time 646.03 seconds
Started Jul 29 08:30:44 PM PDT 24
Finished Jul 29 08:41:31 PM PDT 24
Peak memory 615556 kb
Host smart-9db07d4e-a029-4dce-b4c2-0804fecdcb37
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3
+accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424463896 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_edn_kat.3424463896
Directory /workspace/1.chip_sw_edn_kat/latest

Test location /workspace/coverage/default/1.chip_sw_edn_sw_mode.2944166904
Short name T1090
Test name
Test status
Simulation time 6924005972 ps
CPU time 1468.24 seconds
Started Jul 29 08:30:53 PM PDT 24
Finished Jul 29 08:55:22 PM PDT 24
Peak memory 610072 kb
Host smart-88b6100d-4d98-48c3-8ba0-095c84c648a1
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944166904 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.2944166904
Directory /workspace/1.chip_sw_edn_sw_mode/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1934060980
Short name T1168
Test name
Test status
Simulation time 2836313624 ps
CPU time 370.54 seconds
Started Jul 29 08:29:05 PM PDT 24
Finished Jul 29 08:35:16 PM PDT 24
Peak memory 609712 kb
Host smart-2639f285-2715-45a4-81af-55036d4502be
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19
34060980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.1934060980
Directory /workspace/1.chip_sw_entropy_src_ast_rng_req/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_csrng.578486514
Short name T330
Test name
Test status
Simulation time 7508806164 ps
CPU time 1755.93 seconds
Started Jul 29 08:30:36 PM PDT 24
Finished Jul 29 08:59:53 PM PDT 24
Peak memory 610000 kb
Host smart-1ec3dd74-eca4-4aa1-baa1-290042b29888
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_
csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=578486514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.578486514
Directory /workspace/1.chip_sw_entropy_src_csrng/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1827306872
Short name T945
Test name
Test status
Simulation time 2929980488 ps
CPU time 356.41 seconds
Started Jul 29 08:29:59 PM PDT 24
Finished Jul 29 08:35:57 PM PDT 24
Peak memory 609696 kb
Host smart-62c71a36-cd41-432a-bc50-6e66802fe1b5
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827306872
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.1827306872
Directory /workspace/1.chip_sw_entropy_src_kat_test/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2572247544
Short name T1203
Test name
Test status
Simulation time 3649546360 ps
CPU time 669.76 seconds
Started Jul 29 08:30:20 PM PDT 24
Finished Jul 29 08:41:30 PM PDT 24
Peak memory 608788 kb
Host smart-0d17d0ef-d4dc-482e-a033-945594af42be
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2572247544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.2572247544
Directory /workspace/1.chip_sw_entropy_src_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_example_concurrency.2244235761
Short name T1307
Test name
Test status
Simulation time 2327941448 ps
CPU time 230.61 seconds
Started Jul 29 08:28:00 PM PDT 24
Finished Jul 29 08:31:51 PM PDT 24
Peak memory 609548 kb
Host smart-bcf122b5-81b1-4cb4-ba66-49111ae254bc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244235761 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.chip_sw_example_concurrency.2244235761
Directory /workspace/1.chip_sw_example_concurrency/latest

Test location /workspace/coverage/default/1.chip_sw_example_flash.3753580638
Short name T948
Test name
Test status
Simulation time 2475277056 ps
CPU time 169.45 seconds
Started Jul 29 08:24:58 PM PDT 24
Finished Jul 29 08:27:48 PM PDT 24
Peak memory 609536 kb
Host smart-f50fc1bc-6955-4deb-926f-3115be0d8b6e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753580638 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_example_flash.3753580638
Directory /workspace/1.chip_sw_example_flash/latest

Test location /workspace/coverage/default/1.chip_sw_example_manufacturer.1111818628
Short name T1066
Test name
Test status
Simulation time 2656013630 ps
CPU time 288.3 seconds
Started Jul 29 08:25:49 PM PDT 24
Finished Jul 29 08:30:37 PM PDT 24
Peak memory 609644 kb
Host smart-7147ef24-41a5-4a6b-85f8-9241643b2c71
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111818628 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_example_manufacturer.1111818628
Directory /workspace/1.chip_sw_example_manufacturer/latest

Test location /workspace/coverage/default/1.chip_sw_example_rom.1024431340
Short name T942
Test name
Test status
Simulation time 2317697924 ps
CPU time 134.79 seconds
Started Jul 29 08:26:05 PM PDT 24
Finished Jul 29 08:28:20 PM PDT 24
Peak memory 610084 kb
Host smart-e6d3b856-295a-4042-94d7-6c32b7521bb0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024431340 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_example_rom.1024431340
Directory /workspace/1.chip_sw_example_rom/latest

Test location /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.378989875
Short name T155
Test name
Test status
Simulation time 59623687045 ps
CPU time 10201 seconds
Started Jul 29 08:28:00 PM PDT 24
Finished Jul 29 11:18:02 PM PDT 24
Peak memory 624776 kb
Host smart-456805ab-2959-47bf-b0ae-eb7dadcba018
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=378989875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.378989875
Directory /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest

Test location /workspace/coverage/default/1.chip_sw_flash_crash_alert.936982221
Short name T1045
Test name
Test status
Simulation time 4657188124 ps
CPU time 604.3 seconds
Started Jul 29 08:27:06 PM PDT 24
Finished Jul 29 08:37:11 PM PDT 24
Peak memory 611276 kb
Host smart-b02730e2-3933-43ef-89a4-4e15d2be3f03
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:
new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=936982221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.936982221
Directory /workspace/1.chip_sw_flash_crash_alert/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_access.906316506
Short name T986
Test name
Test status
Simulation time 5714897588 ps
CPU time 1218.3 seconds
Started Jul 29 08:26:09 PM PDT 24
Finished Jul 29 08:46:29 PM PDT 24
Peak memory 608816 kb
Host smart-ab005aea-af5b-4d03-b513-9e2fa50960c0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906316506 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_flash_ctrl_access.906316506
Directory /workspace/1.chip_sw_flash_ctrl_access/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.19140388
Short name T1312
Test name
Test status
Simulation time 5448859747 ps
CPU time 1074.28 seconds
Started Jul 29 08:26:39 PM PDT 24
Finished Jul 29 08:44:34 PM PDT 24
Peak memory 609936 kb
Host smart-3a70aaab-beb8-4236-8280-da695c9f24d7
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19140388 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.19140388
Directory /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2618332687
Short name T933
Test name
Test status
Simulation time 7632091827 ps
CPU time 1015.05 seconds
Started Jul 29 08:26:14 PM PDT 24
Finished Jul 29 08:43:09 PM PDT 24
Peak memory 609040 kb
Host smart-ab1e77c2-bf3c-48cc-a961-12944e6ed4ee
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618332687 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2618332687
Directory /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3977958094
Short name T1106
Test name
Test status
Simulation time 5441884434 ps
CPU time 889.56 seconds
Started Jul 29 08:27:42 PM PDT 24
Finished Jul 29 08:42:32 PM PDT 24
Peak memory 610180 kb
Host smart-9d76f05a-0b95-4e4f-a4c6-a959bba1e93c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977958094 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.3977958094
Directory /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2347089241
Short name T1386
Test name
Test status
Simulation time 3525791746 ps
CPU time 310.47 seconds
Started Jul 29 08:26:43 PM PDT 24
Finished Jul 29 08:31:53 PM PDT 24
Peak memory 609540 kb
Host smart-8dbecbf6-86a5-4ad7-91de-d3e6c896f333
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347089241 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.2347089241
Directory /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.166948072
Short name T424
Test name
Test status
Simulation time 5618514670 ps
CPU time 1211.27 seconds
Started Jul 29 08:34:35 PM PDT 24
Finished Jul 29 08:54:46 PM PDT 24
Peak memory 610152 kb
Host smart-d0afbf4d-73c4-4d61-b830-8b38e98bdf40
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166948072 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.166948072
Directory /workspace/1.chip_sw_flash_ctrl_mem_protection/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3257861103
Short name T351
Test name
Test status
Simulation time 4136000176 ps
CPU time 717.51 seconds
Started Jul 29 08:29:03 PM PDT 24
Finished Jul 29 08:41:01 PM PDT 24
Peak memory 609788 kb
Host smart-645edb14-1b0d-4778-b85d-58ec4725ebe8
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257861103
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.3257861103
Directory /workspace/1.chip_sw_flash_ctrl_ops/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.609453519
Short name T352
Test name
Test status
Simulation time 4517084762 ps
CPU time 709.05 seconds
Started Jul 29 08:27:18 PM PDT 24
Finished Jul 29 08:39:08 PM PDT 24
Peak memory 610396 kb
Host smart-41285d1b-73dd-4a2f-a720-9dfa55073ceb
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=609453519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.609453519
Directory /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3181499239
Short name T1140
Test name
Test status
Simulation time 5080694737 ps
CPU time 779.58 seconds
Started Jul 29 08:33:26 PM PDT 24
Finished Jul 29 08:46:26 PM PDT 24
Peak memory 610268 kb
Host smart-6ca5fd36-d901-4f2c-ba12-3281328bd514
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_
rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3181499239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3181499239
Directory /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1969738357
Short name T963
Test name
Test status
Simulation time 2506476520 ps
CPU time 381.96 seconds
Started Jul 29 08:32:52 PM PDT 24
Finished Jul 29 08:39:15 PM PDT 24
Peak memory 609812 kb
Host smart-29e388f6-90bb-4c02-a204-c90eea779215
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969738
357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.1969738357
Directory /workspace/1.chip_sw_flash_ctrl_write_clear/latest

Test location /workspace/coverage/default/1.chip_sw_flash_init.1703034110
Short name T238
Test name
Test status
Simulation time 22177592254 ps
CPU time 1932.33 seconds
Started Jul 29 08:26:01 PM PDT 24
Finished Jul 29 08:58:14 PM PDT 24
Peak memory 612436 kb
Host smart-32367e28-abc4-4da6-8874-5c12ae769632
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703034110 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.1703034110
Directory /workspace/1.chip_sw_flash_init/latest

Test location /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3290592611
Short name T242
Test name
Test status
Simulation time 22428487659 ps
CPU time 2304.17 seconds
Started Jul 29 08:26:59 PM PDT 24
Finished Jul 29 09:05:24 PM PDT 24
Peak memory 613584 kb
Host smart-47c6253d-ece3-46e9-963b-a53302079796
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3290592611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.3290592611
Directory /workspace/1.chip_sw_flash_init_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1099862694
Short name T921
Test name
Test status
Simulation time 3262562468 ps
CPU time 258.85 seconds
Started Jul 29 08:33:23 PM PDT 24
Finished Jul 29 08:37:42 PM PDT 24
Peak memory 609640 kb
Host smart-411287e2-c760-4c6a-b89d-7d101179e78d
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket
est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1099862694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.1099862694
Directory /workspace/1.chip_sw_flash_scrambling_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_gpio_smoketest.2510116051
Short name T1345
Test name
Test status
Simulation time 3584138391 ps
CPU time 269.48 seconds
Started Jul 29 08:29:36 PM PDT 24
Finished Jul 29 08:34:06 PM PDT 24
Peak memory 608940 kb
Host smart-c9ca35b1-da50-41a5-8f7b-ae0c272a49a7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510116051 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_sw_gpio_smoketest.2510116051
Directory /workspace/1.chip_sw_gpio_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc.1124414121
Short name T1266
Test name
Test status
Simulation time 2453690072 ps
CPU time 308.57 seconds
Started Jul 29 08:29:21 PM PDT 24
Finished Jul 29 08:34:30 PM PDT 24
Peak memory 608472 kb
Host smart-289e800e-cb2e-40f7-b70c-8cbe699fd1b6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124414121 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_hmac_enc.1124414121
Directory /workspace/1.chip_sw_hmac_enc/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc_idle.2330793536
Short name T1117
Test name
Test status
Simulation time 3696238170 ps
CPU time 323.09 seconds
Started Jul 29 08:29:47 PM PDT 24
Finished Jul 29 08:35:11 PM PDT 24
Peak memory 608528 kb
Host smart-4c061b10-f5dc-4f73-9bae-ab959c00d0a5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330793536 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_hmac_enc_idle.2330793536
Directory /workspace/1.chip_sw_hmac_enc_idle/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.638090866
Short name T1227
Test name
Test status
Simulation time 3202303369 ps
CPU time 330.25 seconds
Started Jul 29 08:30:03 PM PDT 24
Finished Jul 29 08:35:33 PM PDT 24
Peak memory 609772 kb
Host smart-9abb114e-ee1d-457a-a237-db85b79ab49c
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638090866 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.638090866
Directory /workspace/1.chip_sw_hmac_enc_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3680022256
Short name T1162
Test name
Test status
Simulation time 3130033232 ps
CPU time 311.3 seconds
Started Jul 29 08:28:31 PM PDT 24
Finished Jul 29 08:33:43 PM PDT 24
Peak memory 609756 kb
Host smart-784ae7d7-4fda-47ff-905c-7eb876295458
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680022256 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.3680022256
Directory /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_multistream.1921300075
Short name T965
Test name
Test status
Simulation time 8164751250 ps
CPU time 1854.2 seconds
Started Jul 29 08:30:04 PM PDT 24
Finished Jul 29 09:00:59 PM PDT 24
Peak memory 608884 kb
Host smart-e9f85a1f-3140-4d54-a7fb-4ed8b16b2b4e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921300075 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_hmac_multistream.1921300075
Directory /workspace/1.chip_sw_hmac_multistream/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_oneshot.3642516487
Short name T980
Test name
Test status
Simulation time 2922661800 ps
CPU time 278.78 seconds
Started Jul 29 08:29:47 PM PDT 24
Finished Jul 29 08:34:26 PM PDT 24
Peak memory 609628 kb
Host smart-5827bb63-0722-4872-b711-d297a8fc03cd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642516487 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_hmac_oneshot.3642516487
Directory /workspace/1.chip_sw_hmac_oneshot/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_smoketest.773074680
Short name T983
Test name
Test status
Simulation time 3552613848 ps
CPU time 381.3 seconds
Started Jul 29 08:35:41 PM PDT 24
Finished Jul 29 08:42:03 PM PDT 24
Peak memory 608448 kb
Host smart-09fe9166-296f-462e-8f7d-bc7b2553603f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773074680 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_hmac_smoketest.773074680
Directory /workspace/1.chip_sw_hmac_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.607336805
Short name T334
Test name
Test status
Simulation time 5223108920 ps
CPU time 722.24 seconds
Started Jul 29 08:25:30 PM PDT 24
Finished Jul 29 08:37:33 PM PDT 24
Peak memory 610040 kb
Host smart-c5dc949d-4a49-4bda-847b-ed77e6f414e2
User root
Command /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607336805 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.607336805
Directory /workspace/1.chip_sw_i2c_host_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1568598168
Short name T325
Test name
Test status
Simulation time 4624397160 ps
CPU time 725.6 seconds
Started Jul 29 08:25:28 PM PDT 24
Finished Jul 29 08:37:34 PM PDT 24
Peak memory 609264 kb
Host smart-486af8b9-4f14-48e6-b524-21f99e468571
User root
Command /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568598168 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.1568598168
Directory /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1486613199
Short name T335
Test name
Test status
Simulation time 4974168780 ps
CPU time 892.43 seconds
Started Jul 29 08:26:58 PM PDT 24
Finished Jul 29 08:41:51 PM PDT 24
Peak memory 609220 kb
Host smart-9711292f-f96a-4c33-ad45-86dc01b9a803
User root
Command /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486613199 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.1486613199
Directory /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest

Test location /workspace/coverage/default/1.chip_sw_inject_scramble_seed.4103670114
Short name T1104
Test name
Test status
Simulation time 64738263108 ps
CPU time 11391.2 seconds
Started Jul 29 08:25:13 PM PDT 24
Finished Jul 29 11:35:06 PM PDT 24
Peak memory 624792 kb
Host smart-bc28d862-3b12-4b8a-98eb-dcfbd9165270
User root
Command /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4103670114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.4103670114
Directory /workspace/1.chip_sw_inject_scramble_seed/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1522436164
Short name T1014
Test name
Test status
Simulation time 11682481706 ps
CPU time 2111.67 seconds
Started Jul 29 08:29:13 PM PDT 24
Finished Jul 29 09:04:26 PM PDT 24
Peak memory 616816 kb
Host smart-34d82a63-7fe9-42bb-88b7-e17368b71cdc
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522
436164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.1522436164
Directory /workspace/1.chip_sw_keymgr_key_derivation/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2100532760
Short name T1325
Test name
Test status
Simulation time 8993794097 ps
CPU time 1393.39 seconds
Started Jul 29 08:28:15 PM PDT 24
Finished Jul 29 08:51:30 PM PDT 24
Peak memory 617860 kb
Host smart-877d4c3f-8b0b-4c4d-b293-89a668ed51e4
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2100532760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.2100532760
Directory /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1642965165
Short name T1382
Test name
Test status
Simulation time 11683716485 ps
CPU time 2392.81 seconds
Started Jul 29 08:30:28 PM PDT 24
Finished Jul 29 09:10:21 PM PDT 24
Peak memory 618148 kb
Host smart-e8a356a2-76eb-49f8-a87d-12edb9518ebe
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1642965165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en
_reduced_freq.1642965165
Directory /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1636263188
Short name T1087
Test name
Test status
Simulation time 6921853400 ps
CPU time 1177.31 seconds
Started Jul 29 08:29:18 PM PDT 24
Finished Jul 29 08:48:56 PM PDT 24
Peak memory 618156 kb
Host smart-ccf0d3a3-1334-4cf0-b510-67ddc98284f2
User root
Command /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1636263188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.1636263188
Directory /workspace/1.chip_sw_keymgr_key_derivation_prod/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.410334821
Short name T234
Test name
Test status
Simulation time 7611152520 ps
CPU time 1584.39 seconds
Started Jul 29 08:30:06 PM PDT 24
Finished Jul 29 08:56:30 PM PDT 24
Peak memory 611172 kb
Host smart-b8cfe6ab-2e90-45bb-812d-849facdb03ec
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410334
821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.410334821
Directory /workspace/1.chip_sw_keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.4084417630
Short name T1108
Test name
Test status
Simulation time 7945941004 ps
CPU time 1207.86 seconds
Started Jul 29 08:30:12 PM PDT 24
Finished Jul 29 08:50:21 PM PDT 24
Peak memory 610792 kb
Host smart-c8a604f2-c77a-429f-9dbf-a2443d595d52
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40844
17630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.4084417630
Directory /workspace/1.chip_sw_keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2137862752
Short name T236
Test name
Test status
Simulation time 17976973860 ps
CPU time 3720.5 seconds
Started Jul 29 08:31:48 PM PDT 24
Finished Jul 29 09:33:50 PM PDT 24
Peak memory 609640 kb
Host smart-5a9b42f1-14b5-4f5e-8ec2-a53bb312c251
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21378
62752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.2137862752
Directory /workspace/1.chip_sw_keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_app_rom.3396767516
Short name T1094
Test name
Test status
Simulation time 3035114526 ps
CPU time 255.61 seconds
Started Jul 29 08:30:19 PM PDT 24
Finished Jul 29 08:34:36 PM PDT 24
Peak memory 609580 kb
Host smart-d680ef33-3be3-456e-be84-f61b6a3a6e01
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396767516 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_kmac_app_rom.3396767516
Directory /workspace/1.chip_sw_kmac_app_rom/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_entropy.2333307912
Short name T1260
Test name
Test status
Simulation time 2419560784 ps
CPU time 227.89 seconds
Started Jul 29 08:26:35 PM PDT 24
Finished Jul 29 08:30:24 PM PDT 24
Peak memory 609568 kb
Host smart-e57fa7c8-19e8-4ea7-8eb3-ccbd9820e5ef
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333307912 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_kmac_entropy.2333307912
Directory /workspace/1.chip_sw_kmac_entropy/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_idle.4181743711
Short name T1171
Test name
Test status
Simulation time 2948028196 ps
CPU time 170.84 seconds
Started Jul 29 08:30:28 PM PDT 24
Finished Jul 29 08:33:19 PM PDT 24
Peak memory 609648 kb
Host smart-8fb5503d-4c8a-47ee-8aa7-11be7e8bb928
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181743711 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_kmac_idle.4181743711
Directory /workspace/1.chip_sw_kmac_idle/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.777290834
Short name T955
Test name
Test status
Simulation time 2903991396 ps
CPU time 284.02 seconds
Started Jul 29 08:27:43 PM PDT 24
Finished Jul 29 08:32:28 PM PDT 24
Peak memory 609584 kb
Host smart-0a602569-1920-4479-b51a-55875ead44a4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777290834 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_sw_kmac_mode_cshake.777290834
Directory /workspace/1.chip_sw_kmac_mode_cshake/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2122184151
Short name T460
Test name
Test status
Simulation time 3469056876 ps
CPU time 253.86 seconds
Started Jul 29 08:30:01 PM PDT 24
Finished Jul 29 08:34:16 PM PDT 24
Peak memory 609704 kb
Host smart-707deb75-6c52-4608-84aa-0868be84fab7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122184151 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_kmac_mode_kmac.2122184151
Directory /workspace/1.chip_sw_kmac_mode_kmac/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2698794483
Short name T1179
Test name
Test status
Simulation time 3179849531 ps
CPU time 401.37 seconds
Started Jul 29 08:31:18 PM PDT 24
Finished Jul 29 08:38:01 PM PDT 24
Peak memory 609768 kb
Host smart-d839c063-3ebf-4d65-bd74-f0332b851aae
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698794483 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.2698794483
Directory /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2951853891
Short name T1340
Test name
Test status
Simulation time 3468407430 ps
CPU time 342.67 seconds
Started Jul 29 08:34:22 PM PDT 24
Finished Jul 29 08:40:05 PM PDT 24
Peak memory 608512 kb
Host smart-c38ee154-6851-48ac-8efb-99f0fe32a6a5
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29518538
91 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2951853891
Directory /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_smoketest.3602120353
Short name T1141
Test name
Test status
Simulation time 3040095040 ps
CPU time 365.47 seconds
Started Jul 29 08:32:52 PM PDT 24
Finished Jul 29 08:38:58 PM PDT 24
Peak memory 608484 kb
Host smart-1687d273-ff3f-402f-a0c3-088d637fd788
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602120353 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_kmac_smoketest.3602120353
Directory /workspace/1.chip_sw_kmac_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.583411279
Short name T1038
Test name
Test status
Simulation time 3459470390 ps
CPU time 328.41 seconds
Started Jul 29 08:26:10 PM PDT 24
Finished Jul 29 08:31:39 PM PDT 24
Peak memory 609724 kb
Host smart-46ed84a0-94d0-458a-89e0-5537ba578e5e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583411279 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.583411279
Directory /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.319794140
Short name T177
Test name
Test status
Simulation time 4363810838 ps
CPU time 625.42 seconds
Started Jul 29 08:26:22 PM PDT 24
Finished Jul 29 08:36:48 PM PDT 24
Peak memory 611116 kb
Host smart-d5ac6cb0-877d-48bb-8a98-8fcb8422e16e
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=319794140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.319794140
Directory /workspace/1.chip_sw_lc_ctrl_program_error/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1620573081
Short name T183
Test name
Test status
Simulation time 3604772766 ps
CPU time 229.01 seconds
Started Jul 29 08:27:13 PM PDT 24
Finished Jul 29 08:31:02 PM PDT 24
Peak memory 621428 kb
Host smart-986ed7f7-e494-4413-bd05-c95c80804543
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16205730
81 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.1620573081
Directory /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2822962116
Short name T1222
Test name
Test status
Simulation time 5429644432 ps
CPU time 554.23 seconds
Started Jul 29 08:26:54 PM PDT 24
Finished Jul 29 08:36:09 PM PDT 24
Peak memory 624716 kb
Host smart-191bdf57-31fe-460d-bbb3-90992f1cb949
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822962116 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.2822962116
Directory /workspace/1.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2397956545
Short name T170
Test name
Test status
Simulation time 2486289297 ps
CPU time 130.58 seconds
Started Jul 29 08:28:32 PM PDT 24
Finished Jul 29 08:30:44 PM PDT 24
Peak memory 617692 kb
Host smart-c159536b-5d94-46de-85d4-1ee7857b928a
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes
t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2397956545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.2397956545
Directory /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3625540875
Short name T421
Test name
Test status
Simulation time 2899490970 ps
CPU time 115.47 seconds
Started Jul 29 08:27:03 PM PDT 24
Finished Jul 29 08:28:59 PM PDT 24
Peak memory 617660 kb
Host smart-384d15f6-3438-42f3-9624-6ea353743808
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s
im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625540875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3625540875
Directory /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2561154054
Short name T180
Test name
Test status
Simulation time 47861597626 ps
CPU time 5296.23 seconds
Started Jul 29 08:28:00 PM PDT 24
Finished Jul 29 09:56:17 PM PDT 24
Peak memory 620620 kb
Host smart-1037296d-6abc-4065-94c4-7f570b2ca278
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561154054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip
_sw_lc_walkthrough_dev.2561154054
Directory /workspace/1.chip_sw_lc_walkthrough_dev/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.348669964
Short name T245
Test name
Test status
Simulation time 49928307812 ps
CPU time 5517.68 seconds
Started Jul 29 08:28:01 PM PDT 24
Finished Jul 29 10:00:00 PM PDT 24
Peak memory 619608 kb
Host smart-389e340a-5a79-4814-971c-f1d52f366118
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d
evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348669964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip
_sw_lc_walkthrough_prod.348669964
Directory /workspace/1.chip_sw_lc_walkthrough_prod/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.817354818
Short name T1079
Test name
Test status
Simulation time 8725478588 ps
CPU time 915.39 seconds
Started Jul 29 08:27:47 PM PDT 24
Finished Jul 29 08:43:02 PM PDT 24
Peak memory 619384 kb
Host smart-5fb9f15b-a509-412b-88f0-8452c996fbd9
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa
lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=817354818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.817354818
Directory /workspace/1.chip_sw_lc_walkthrough_prodend/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1366717260
Short name T244
Test name
Test status
Simulation time 47526801230 ps
CPU time 5515.62 seconds
Started Jul 29 08:26:57 PM PDT 24
Finished Jul 29 09:58:53 PM PDT 24
Peak memory 620564 kb
Host smart-807d24fb-726c-4fc6-a186-b6f72d739bea
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366717260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip
_sw_lc_walkthrough_rma.1366717260
Directory /workspace/1.chip_sw_lc_walkthrough_rma/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2732913777
Short name T182
Test name
Test status
Simulation time 33545102992 ps
CPU time 2842.91 seconds
Started Jul 29 08:27:00 PM PDT 24
Finished Jul 29 09:14:24 PM PDT 24
Peak memory 621696 kb
Host smart-1b9ed51a-8d96-46ee-adeb-6186bd30ddf4
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks
_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2732913777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun
locks.2732913777
Directory /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.334221605
Short name T151
Test name
Test status
Simulation time 17288765644 ps
CPU time 3219.47 seconds
Started Jul 29 08:27:56 PM PDT 24
Finished Jul 29 09:21:36 PM PDT 24
Peak memory 610288 kb
Host smart-89b3a02c-4a4e-42a2-aa3a-2402a9fad762
User root
Command /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_
rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=334221605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.334221605
Directory /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.427837008
Short name T1192
Test name
Test status
Simulation time 18937549077 ps
CPU time 3368.74 seconds
Started Jul 29 08:28:54 PM PDT 24
Finished Jul 29 09:25:04 PM PDT 24
Peak memory 610384 kb
Host smart-b0aaccd5-3e54-4319-b765-d970e02df3c0
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne
w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=427837008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.427837008
Directory /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3557151828
Short name T1390
Test name
Test status
Simulation time 25505856507 ps
CPU time 3511.65 seconds
Started Jul 29 08:27:15 PM PDT 24
Finished Jul 29 09:25:47 PM PDT 24
Peak memory 610096 kb
Host smart-3bb0a924-89c8-455d-89ce-d35346d48187
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e
cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557151828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu
ced_freq.3557151828
Directory /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3581848652
Short name T249
Test name
Test status
Simulation time 3428083136 ps
CPU time 532.54 seconds
Started Jul 29 08:27:56 PM PDT 24
Finished Jul 29 08:36:49 PM PDT 24
Peak memory 609876 kb
Host smart-3681ffdc-9064-498e-9ef8-e4c191bd9d75
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn
_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581848652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.3581848652
Directory /workspace/1.chip_sw_otbn_mem_scramble/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_randomness.2770743335
Short name T1093
Test name
Test status
Simulation time 6017991000 ps
CPU time 1121.02 seconds
Started Jul 29 08:29:32 PM PDT 24
Finished Jul 29 08:48:14 PM PDT 24
Peak memory 610280 kb
Host smart-b9db3d9d-d170-4b31-bcd2-95e021a1aa2b
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2770743335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.2770743335
Directory /workspace/1.chip_sw_otbn_randomness/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_smoketest.588746461
Short name T998
Test name
Test status
Simulation time 9914310790 ps
CPU time 1933.42 seconds
Started Jul 29 08:30:45 PM PDT 24
Finished Jul 29 09:02:59 PM PDT 24
Peak memory 610336 kb
Host smart-60e4afb5-d623-46b3-b28d-b44e69cea53d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588746461 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_otbn_smoketest.588746461
Directory /workspace/1.chip_sw_otbn_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.967754676
Short name T1356
Test name
Test status
Simulation time 2521961237 ps
CPU time 273.23 seconds
Started Jul 29 08:30:36 PM PDT 24
Finished Jul 29 08:35:11 PM PDT 24
Peak memory 609572 kb
Host smart-83611767-8992-4f9d-be6b-ba1becfb655e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967754676 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.967754676
Directory /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3411632889
Short name T1363
Test name
Test status
Simulation time 6646369272 ps
CPU time 1338.81 seconds
Started Jul 29 08:27:46 PM PDT 24
Finished Jul 29 08:50:05 PM PDT 24
Peak memory 610780 kb
Host smart-375d9a33-1aaa-48bf-babd-d6c5dc809485
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3411632889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.3411632889
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3847232692
Short name T1341
Test name
Test status
Simulation time 6531891570 ps
CPU time 1270.26 seconds
Started Jul 29 08:26:40 PM PDT 24
Finished Jul 29 08:47:51 PM PDT 24
Peak memory 610672 kb
Host smart-8ba4dfaa-b93d-46b9-aa53-dac126d68271
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3847232692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.3847232692
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3793055415
Short name T1137
Test name
Test status
Simulation time 8111582816 ps
CPU time 1623.96 seconds
Started Jul 29 08:29:20 PM PDT 24
Finished Jul 29 08:56:24 PM PDT 24
Peak memory 610672 kb
Host smart-51f6007f-2008-45f6-ba33-cb9d7d5e9e76
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3793055415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.3793055415
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2979186039
Short name T1310
Test name
Test status
Simulation time 4000317580 ps
CPU time 671.7 seconds
Started Jul 29 08:27:39 PM PDT 24
Finished Jul 29 08:38:51 PM PDT 24
Peak memory 609884 kb
Host smart-35b9a2ce-5015-455c-8b74-6a5e4e3495ab
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=2979186039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2979186039
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2657582699
Short name T1194
Test name
Test status
Simulation time 3319010264 ps
CPU time 272.38 seconds
Started Jul 29 08:30:29 PM PDT 24
Finished Jul 29 08:35:01 PM PDT 24
Peak memory 608384 kb
Host smart-3fbca9d3-0d87-429c-baae-5fcaa0661da6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657582699 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_otp_ctrl_smoketest.2657582699
Directory /workspace/1.chip_sw_otp_ctrl_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_pattgen_ios.3424116379
Short name T349
Test name
Test status
Simulation time 2720799952 ps
CPU time 260.09 seconds
Started Jul 29 08:26:45 PM PDT 24
Finished Jul 29 08:31:06 PM PDT 24
Peak memory 610384 kb
Host smart-940002e9-04ca-4008-bfe2-38c21b902c1c
User root
Command /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424116379 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.3424116379
Directory /workspace/1.chip_sw_pattgen_ios/latest

Test location /workspace/coverage/default/1.chip_sw_plic_sw_irq.3132579625
Short name T1278
Test name
Test status
Simulation time 2353189390 ps
CPU time 258.77 seconds
Started Jul 29 08:26:41 PM PDT 24
Finished Jul 29 08:31:00 PM PDT 24
Peak memory 609624 kb
Host smart-0a3e4ded-5097-40b0-a523-c2ab67a36b05
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132579625 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.chip_sw_plic_sw_irq.3132579625
Directory /workspace/1.chip_sw_plic_sw_irq/latest

Test location /workspace/coverage/default/1.chip_sw_power_idle_load.264862644
Short name T1271
Test name
Test status
Simulation time 4801043940 ps
CPU time 690.87 seconds
Started Jul 29 08:28:51 PM PDT 24
Finished Jul 29 08:40:22 PM PDT 24
Peak memory 609172 kb
Host smart-ac0c2e3d-44fc-4441-b9c1-27ab29ac7f0d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264862644 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.264862644
Directory /workspace/1.chip_sw_power_idle_load/latest

Test location /workspace/coverage/default/1.chip_sw_power_sleep_load.3368846528
Short name T256
Test name
Test status
Simulation time 4394028048 ps
CPU time 370.92 seconds
Started Jul 29 08:30:44 PM PDT 24
Finished Jul 29 08:36:55 PM PDT 24
Peak memory 609220 kb
Host smart-07eeebc9-baf7-4636-bcf2-84050a761b77
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368846528 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.3368846528
Directory /workspace/1.chip_sw_power_sleep_load/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.658145576
Short name T535
Test name
Test status
Simulation time 10727425243 ps
CPU time 1487.81 seconds
Started Jul 29 08:31:20 PM PDT 24
Finished Jul 29 08:56:09 PM PDT 24
Peak memory 611200 kb
Host smart-46125d81-c1cb-4f6e-8471-dd65f272c13e
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6581
45576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.658145576
Directory /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2058227826
Short name T1103
Test name
Test status
Simulation time 22931416260 ps
CPU time 2968.8 seconds
Started Jul 29 08:29:23 PM PDT 24
Finished Jul 29 09:18:53 PM PDT 24
Peak memory 610808 kb
Host smart-d2c9a6a3-66b5-4f41-a0d0-ecbcbae7fa4c
User root
Command /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205
8227826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.2058227826
Directory /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1974748759
Short name T1335
Test name
Test status
Simulation time 18627475915 ps
CPU time 1786.13 seconds
Started Jul 29 08:26:40 PM PDT 24
Finished Jul 29 08:56:27 PM PDT 24
Peak memory 611604 kb
Host smart-e5aea9f8-f21a-4f3a-a8c3-af936dfa2232
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1974748759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1974748759
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3979905104
Short name T431
Test name
Test status
Simulation time 21644322878 ps
CPU time 2048 seconds
Started Jul 29 08:27:23 PM PDT 24
Finished Jul 29 09:01:31 PM PDT 24
Peak memory 610540 kb
Host smart-0d4d4b76-e19a-4b6f-a8c5-93d89d66045e
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3979905104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3979905104
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2040536654
Short name T117
Test name
Test status
Simulation time 8001419522 ps
CPU time 674.55 seconds
Started Jul 29 08:26:26 PM PDT 24
Finished Jul 29 08:37:41 PM PDT 24
Peak memory 610620 kb
Host smart-9379337e-f186-4890-b28c-e017a6a8d8cc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040536654 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.2040536654
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.61442050
Short name T1008
Test name
Test status
Simulation time 7073339344 ps
CPU time 631.73 seconds
Started Jul 29 08:29:28 PM PDT 24
Finished Jul 29 08:40:00 PM PDT 24
Peak memory 616620 kb
Host smart-d94eeee6-289e-43bb-8298-6002e036e36b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=61442050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.61442050
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1900950783
Short name T1166
Test name
Test status
Simulation time 8236969728 ps
CPU time 628.22 seconds
Started Jul 29 08:29:10 PM PDT 24
Finished Jul 29 08:39:38 PM PDT 24
Peak memory 610408 kb
Host smart-ff393498-24f1-40f7-83af-175fcd5703b6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900950783 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.1900950783
Directory /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3573545912
Short name T1232
Test name
Test status
Simulation time 4540309320 ps
CPU time 484.67 seconds
Started Jul 29 08:26:46 PM PDT 24
Finished Jul 29 08:34:51 PM PDT 24
Peak memory 616768 kb
Host smart-77ef8317-a5b4-4695-917a-cd57ed9eb921
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3573545912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.3573545912
Directory /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1033122762
Short name T319
Test name
Test status
Simulation time 10246138400 ps
CPU time 1155.69 seconds
Started Jul 29 08:28:19 PM PDT 24
Finished Jul 29 08:47:35 PM PDT 24
Peak memory 611400 kb
Host smart-03690b53-25ff-4c74-96a1-e071b2ab3518
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033122762 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1033122762
Directory /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3430824977
Short name T1021
Test name
Test status
Simulation time 6956080928 ps
CPU time 848.91 seconds
Started Jul 29 08:31:46 PM PDT 24
Finished Jul 29 08:45:55 PM PDT 24
Peak memory 610744 kb
Host smart-5f584484-2260-4faf-82a8-a25adf0c4a52
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430824977 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.3430824977
Directory /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2782021219
Short name T1354
Test name
Test status
Simulation time 27014225694 ps
CPU time 2076.09 seconds
Started Jul 29 08:28:16 PM PDT 24
Finished Jul 29 09:02:53 PM PDT 24
Peak memory 611472 kb
Host smart-233bb46d-b53c-4412-bb4f-56f07bf3ab01
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2782021219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2782021219
Directory /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1892270666
Short name T18
Test name
Test status
Simulation time 21717819544 ps
CPU time 1871.29 seconds
Started Jul 29 08:28:05 PM PDT 24
Finished Jul 29 08:59:16 PM PDT 24
Peak memory 611040 kb
Host smart-c9ebbe88-f621-485a-af30-2e817ebe4678
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1892270666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1892270666
Directory /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2789988372
Short name T299
Test name
Test status
Simulation time 34216347735 ps
CPU time 2889.12 seconds
Started Jul 29 08:31:51 PM PDT 24
Finished Jul 29 09:20:01 PM PDT 24
Peak memory 611784 kb
Host smart-d39c864e-33fc-4b86-9df0-7d1892f43395
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power
_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789988372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit
ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s
leep_power_glitch_reset.2789988372
Directory /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3752432096
Short name T366
Test name
Test status
Simulation time 5767302244 ps
CPU time 458.2 seconds
Started Jul 29 08:26:46 PM PDT 24
Finished Jul 29 08:34:25 PM PDT 24
Peak memory 610972 kb
Host smart-2104910d-ed51-484b-bbeb-96dc440a8968
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul
es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3752432096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s
leep_wake_up.3752432096
Directory /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1288984421
Short name T729
Test name
Test status
Simulation time 3262956860 ps
CPU time 244.77 seconds
Started Jul 29 08:28:15 PM PDT 24
Finished Jul 29 08:32:20 PM PDT 24
Peak memory 609208 kb
Host smart-c4bc94ab-eda2-4519-8943-bd9843cf2d47
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288984421 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.1288984421
Directory /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3901178310
Short name T1247
Test name
Test status
Simulation time 4376737709 ps
CPU time 633.18 seconds
Started Jul 29 08:27:23 PM PDT 24
Finished Jul 29 08:37:57 PM PDT 24
Peak memory 617760 kb
Host smart-6c05f63f-4107-41c7-9802-36b904f72e13
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=3901178310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.3901178310
Directory /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1816874806
Short name T128
Test name
Test status
Simulation time 5364895428 ps
CPU time 395.28 seconds
Started Jul 29 08:31:09 PM PDT 24
Finished Jul 29 08:37:45 PM PDT 24
Peak memory 609956 kb
Host smart-ab41c918-9972-478e-8d93-9f24ab85f20b
User root
Command /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18168748
06 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1816874806
Directory /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2505026131
Short name T1100
Test name
Test status
Simulation time 6014325440 ps
CPU time 451.13 seconds
Started Jul 29 08:32:18 PM PDT 24
Finished Jul 29 08:39:50 PM PDT 24
Peak memory 610716 kb
Host smart-452b4f39-87a5-47d4-97e1-0d79859c9b2c
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2505026131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.2505026131
Directory /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1851874119
Short name T1256
Test name
Test status
Simulation time 5528769512 ps
CPU time 553.61 seconds
Started Jul 29 08:32:08 PM PDT 24
Finished Jul 29 08:41:22 PM PDT 24
Peak memory 610344 kb
Host smart-d10bfd8e-7322-4617-86e7-f92cb063b38a
User root
Command /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851874119 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.1851874119
Directory /workspace/1.chip_sw_pwrmgr_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2973528835
Short name T1207
Test name
Test status
Simulation time 7880222180 ps
CPU time 1127.15 seconds
Started Jul 29 08:26:48 PM PDT 24
Finished Jul 29 08:45:35 PM PDT 24
Peak memory 610848 kb
Host smart-a862e79b-1b25-4c33-8563-eab9df217ed6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973528835 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.2973528835
Directory /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1309222021
Short name T1378
Test name
Test status
Simulation time 4948740212 ps
CPU time 431.06 seconds
Started Jul 29 08:27:56 PM PDT 24
Finished Jul 29 08:35:08 PM PDT 24
Peak memory 609076 kb
Host smart-7517bfc9-7649-4a20-b673-d4e3f1810c92
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309222021 -assert no
postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1309222021
Directory /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.789218572
Short name T1127
Test name
Test status
Simulation time 5572492948 ps
CPU time 554.14 seconds
Started Jul 29 08:29:50 PM PDT 24
Finished Jul 29 08:39:04 PM PDT 24
Peak memory 610124 kb
Host smart-1ef97e9b-f1e4-4efd-86a2-6a0e3e430ed1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789218572 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.789218572
Directory /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1488450450
Short name T1016
Test name
Test status
Simulation time 3979533350 ps
CPU time 535.15 seconds
Started Jul 29 08:24:22 PM PDT 24
Finished Jul 29 08:33:18 PM PDT 24
Peak memory 608880 kb
Host smart-9cf0eafd-3acc-4005-b224-f64277afc5d7
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148
8450450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.1488450450
Directory /workspace/1.chip_sw_pwrmgr_wdog_reset/latest

Test location /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.4292427414
Short name T1193
Test name
Test status
Simulation time 8799407909 ps
CPU time 657.78 seconds
Started Jul 29 08:31:03 PM PDT 24
Finished Jul 29 08:42:01 PM PDT 24
Peak memory 624808 kb
Host smart-be612f74-b9cb-4a53-9546-92019d26c1cf
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292427414 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.4292427414
Directory /workspace/1.chip_sw_rom_ctrl_integrity_check/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.735879007
Short name T329
Test name
Test status
Simulation time 13160918816 ps
CPU time 1987.65 seconds
Started Jul 29 08:27:47 PM PDT 24
Finished Jul 29 09:00:55 PM PDT 24
Peak memory 611000 kb
Host smart-091d53eb-e990-4159-85cd-4dc6ef9d1b78
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=735879007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.735879007
Directory /workspace/1.chip_sw_rstmgr_alert_info/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.4113185334
Short name T252
Test name
Test status
Simulation time 7069336236 ps
CPU time 752.95 seconds
Started Jul 29 08:26:59 PM PDT 24
Finished Jul 29 08:39:32 PM PDT 24
Peak memory 610492 kb
Host smart-628826c6-8b61-4738-80a3-eb8f3aded1e6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113185334 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.4113185334
Directory /workspace/1.chip_sw_rstmgr_cpu_info/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2951111819
Short name T1264
Test name
Test status
Simulation time 5624461920 ps
CPU time 763.57 seconds
Started Jul 29 08:25:20 PM PDT 24
Finished Jul 29 08:38:05 PM PDT 24
Peak memory 641712 kb
Host smart-f5ca37a2-ce29-4a9e-a9df-1e11f00619ba
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2951111819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.2951111819
Directory /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.97690299
Short name T966
Test name
Test status
Simulation time 3490967170 ps
CPU time 185.92 seconds
Started Jul 29 08:30:54 PM PDT 24
Finished Jul 29 08:34:00 PM PDT 24
Peak memory 608460 kb
Host smart-ec64fb57-fc1e-42d0-a7c9-b294263408c3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97690299 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_rstmgr_smoketest.97690299
Directory /workspace/1.chip_sw_rstmgr_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.244232658
Short name T1055
Test name
Test status
Simulation time 5399395606 ps
CPU time 431.66 seconds
Started Jul 29 08:27:15 PM PDT 24
Finished Jul 29 08:34:27 PM PDT 24
Peak memory 610552 kb
Host smart-24306f42-7e84-4eda-a9d7-d6dcde314362
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244232658 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_rstmgr_sw_req.244232658
Directory /workspace/1.chip_sw_rstmgr_sw_req/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1120250314
Short name T1054
Test name
Test status
Simulation time 3084480392 ps
CPU time 214.06 seconds
Started Jul 29 08:26:40 PM PDT 24
Finished Jul 29 08:30:14 PM PDT 24
Peak memory 609768 kb
Host smart-86a0a7d1-fbd6-46d7-9118-24887292692f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120250314 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.1120250314
Directory /workspace/1.chip_sw_rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.609373178
Short name T300
Test name
Test status
Simulation time 3461803072 ps
CPU time 312.05 seconds
Started Jul 29 08:27:33 PM PDT 24
Finished Jul 29 08:32:46 PM PDT 24
Peak memory 609680 kb
Host smart-4b292c34-de62-4cc2-abf2-f5432a8da984
User root
Command /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=609373178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.609373178
Directory /workspace/1.chip_sw_rv_core_ibex_address_translation/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.551170942
Short name T187
Test name
Test status
Simulation time 3274680593 ps
CPU time 254.11 seconds
Started Jul 29 08:30:46 PM PDT 24
Finished Jul 29 08:35:01 PM PDT 24
Peak memory 609876 kb
Host smart-b926f8cf-4db3-4579-92c1-1653979cc869
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551170942 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.551170942
Directory /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.383905938
Short name T534
Test name
Test status
Simulation time 4365783160 ps
CPU time 941.55 seconds
Started Jul 29 08:27:59 PM PDT 24
Finished Jul 29 08:43:41 PM PDT 24
Peak memory 608944 kb
Host smart-255eb501-fe42-4b18-8866-7464f41c6bd3
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38390
5938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.383905938
Directory /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1939050185
Short name T124
Test name
Test status
Simulation time 5907766446 ps
CPU time 994.13 seconds
Started Jul 29 08:27:29 PM PDT 24
Finished Jul 29 08:44:05 PM PDT 24
Peak memory 610100 kb
Host smart-a7add9a6-80b3-4e4c-808a-a2037d44aac0
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1939050185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.1939050185
Directory /workspace/1.chip_sw_rv_core_ibex_rnd/latest

Test location /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2570725097
Short name T46
Test name
Test status
Simulation time 5727961874 ps
CPU time 642.51 seconds
Started Jul 29 08:30:24 PM PDT 24
Finished Jul 29 08:41:07 PM PDT 24
Peak memory 624300 kb
Host smart-b4fc645e-bae2-459a-b18c-52085d18da90
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570725097 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.2570725097
Directory /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.336318750
Short name T1283
Test name
Test status
Simulation time 4868865200 ps
CPU time 322.98 seconds
Started Jul 29 08:33:26 PM PDT 24
Finished Jul 29 08:38:49 PM PDT 24
Peak memory 621248 kb
Host smart-d2027583-3b6e-4812-909d-f5ff31026ea9
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336318750 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.336318750
Directory /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.865585229
Short name T76
Test name
Test status
Simulation time 5392612930 ps
CPU time 672.31 seconds
Started Jul 29 08:28:51 PM PDT 24
Finished Jul 29 08:40:04 PM PDT 24
Peak memory 621460 kb
Host smart-0f1ad31c-8afb-4782-beac-9dd23745a663
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865585
229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.865585229
Directory /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.766177212
Short name T1360
Test name
Test status
Simulation time 2749406160 ps
CPU time 267.16 seconds
Started Jul 29 08:32:27 PM PDT 24
Finished Jul 29 08:36:55 PM PDT 24
Peak memory 609548 kb
Host smart-05aaf433-eb48-4e2f-a882-598374405c8b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766177212 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.chip_sw_rv_plic_smoketest.766177212
Directory /workspace/1.chip_sw_rv_plic_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_rv_timer_irq.1061292296
Short name T443
Test name
Test status
Simulation time 2590977546 ps
CPU time 288.83 seconds
Started Jul 29 08:26:50 PM PDT 24
Finished Jul 29 08:31:40 PM PDT 24
Peak memory 609512 kb
Host smart-693e2554-acf6-4505-9c8c-f94d4e9bf86e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061292296 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_rv_timer_irq.1061292296
Directory /workspace/1.chip_sw_rv_timer_irq/latest

Test location /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.445413378
Short name T259
Test name
Test status
Simulation time 3084132720 ps
CPU time 304.94 seconds
Started Jul 29 08:30:10 PM PDT 24
Finished Jul 29 08:35:15 PM PDT 24
Peak memory 608400 kb
Host smart-a156cda0-acd9-455a-b715-62902c240b3e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445413378 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_rv_timer_smoketest.445413378
Directory /workspace/1.chip_sw_rv_timer_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.860434123
Short name T131
Test name
Test status
Simulation time 7046361430 ps
CPU time 927.55 seconds
Started Jul 29 08:30:14 PM PDT 24
Finished Jul 29 08:45:43 PM PDT 24
Peak memory 610260 kb
Host smart-72a7a72d-440b-449d-ade2-65d388e82dd4
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86043412
3 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.860434123
Directory /workspace/1.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2003413549
Short name T114
Test name
Test status
Simulation time 2889679558 ps
CPU time 188.65 seconds
Started Jul 29 08:30:41 PM PDT 24
Finished Jul 29 08:33:51 PM PDT 24
Peak memory 610468 kb
Host smart-48c8e2d7-b60d-456e-9ebf-326d79db25e5
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003413
549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.2003413549
Directory /workspace/1.chip_sw_sensor_ctrl_status/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3316350017
Short name T26
Test name
Test status
Simulation time 3675788360 ps
CPU time 363.87 seconds
Started Jul 29 08:25:50 PM PDT 24
Finished Jul 29 08:31:54 PM PDT 24
Peak memory 610128 kb
Host smart-ee0695aa-4131-4567-98c1-8b1414e2c1f1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316350017 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.3316350017
Directory /workspace/1.chip_sw_sleep_pin_retention/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pin_wake.4283279383
Short name T99
Test name
Test status
Simulation time 2828695036 ps
CPU time 232.2 seconds
Started Jul 29 08:25:38 PM PDT 24
Finished Jul 29 08:29:30 PM PDT 24
Peak memory 610180 kb
Host smart-462f076a-2c83-4922-bcec-7618e1b7271b
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283279383
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.4283279383
Directory /workspace/1.chip_sw_sleep_pin_wake/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.4049059777
Short name T1061
Test name
Test status
Simulation time 9654521700 ps
CPU time 1216.67 seconds
Started Jul 29 08:25:57 PM PDT 24
Finished Jul 29 08:46:15 PM PDT 24
Peak memory 610844 kb
Host smart-5ad04bc3-74e7-42f9-815d-403fc13b2e77
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049059777 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.4049059777
Directory /workspace/1.chip_sw_sleep_pwm_pulses/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3933515737
Short name T1083
Test name
Test status
Simulation time 6952925120 ps
CPU time 640.03 seconds
Started Jul 29 08:29:20 PM PDT 24
Finished Jul 29 08:40:01 PM PDT 24
Peak memory 610592 kb
Host smart-6c65167f-51be-4632-b10e-baa6edce363d
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933515737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl
eep_sram_ret_contents_no_scramble.3933515737
Directory /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2181958301
Short name T1238
Test name
Test status
Simulation time 7900882206 ps
CPU time 735.33 seconds
Started Jul 29 08:32:25 PM PDT 24
Finished Jul 29 08:44:42 PM PDT 24
Peak memory 610644 kb
Host smart-32c02790-b239-40aa-aef3-8ae04708d5c4
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181958301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep
_sram_ret_contents_scramble.2181958301
Directory /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3845151929
Short name T203
Test name
Test status
Simulation time 7688347290 ps
CPU time 817.15 seconds
Started Jul 29 08:26:46 PM PDT 24
Finished Jul 29 08:40:23 PM PDT 24
Peak memory 624948 kb
Host smart-e12522a2-8ed8-456e-9dff-9961f67ba617
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845151929 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.3845151929
Directory /workspace/1.chip_sw_spi_device_pass_through/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3987856173
Short name T12
Test name
Test status
Simulation time 4151724227 ps
CPU time 670.01 seconds
Started Jul 29 08:25:29 PM PDT 24
Finished Jul 29 08:36:40 PM PDT 24
Peak memory 624816 kb
Host smart-0057c3ff-7f27-4abe-9e29-114f767a91ef
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987856173 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.3987856173
Directory /workspace/1.chip_sw_spi_device_pass_through_collision/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2643211874
Short name T53
Test name
Test status
Simulation time 4012603580 ps
CPU time 319.28 seconds
Started Jul 29 08:27:11 PM PDT 24
Finished Jul 29 08:32:30 PM PDT 24
Peak memory 617692 kb
Host smart-8daf7264-21f2-41c1-82c0-80afcd45fc7b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643211874 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.2643211874
Directory /workspace/1.chip_sw_spi_device_pinmux_sleep_retention/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_tpm.3157542868
Short name T40
Test name
Test status
Simulation time 2782087729 ps
CPU time 389.75 seconds
Started Jul 29 08:28:12 PM PDT 24
Finished Jul 29 08:34:42 PM PDT 24
Peak memory 618104 kb
Host smart-b946bd68-6fe4-4a1c-a503-ed7b8df33dae
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157542868 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.3157542868
Directory /workspace/1.chip_sw_spi_device_tpm/latest

Test location /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.4268979354
Short name T33
Test name
Test status
Simulation time 2959290936 ps
CPU time 264.36 seconds
Started Jul 29 08:28:12 PM PDT 24
Finished Jul 29 08:32:36 PM PDT 24
Peak memory 610096 kb
Host smart-ebaabf5f-c5c0-4b6d-ba2d-0795a656e7c2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268979354 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.4268979354
Directory /workspace/1.chip_sw_spi_host_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3053931570
Short name T303
Test name
Test status
Simulation time 6590554064 ps
CPU time 691.22 seconds
Started Jul 29 08:29:01 PM PDT 24
Finished Jul 29 08:40:33 PM PDT 24
Peak memory 610632 kb
Host smart-74e25f09-2ec2-4b5f-8320-d4353518247d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053931570 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.3053931570
Directory /workspace/1.chip_sw_sram_ctrl_execution_main/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1686504137
Short name T294
Test name
Test status
Simulation time 4695656828 ps
CPU time 804.07 seconds
Started Jul 29 08:29:14 PM PDT 24
Finished Jul 29 08:42:39 PM PDT 24
Peak memory 610844 kb
Host smart-84535f14-4429-4c8d-8a1f-450fee8d05d8
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686504137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr
l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw
_sram_ctrl_scrambled_access.1686504137
Directory /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2948903240
Short name T1317
Test name
Test status
Simulation time 5204632553 ps
CPU time 607.42 seconds
Started Jul 29 08:27:44 PM PDT 24
Finished Jul 29 08:37:52 PM PDT 24
Peak memory 611068 kb
Host smart-eb30ab32-e420-4b9c-8d88-7204dc3c10c5
User root
Command /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk
_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948903240 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2948903240
Directory /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2357238573
Short name T1012
Test name
Test status
Simulation time 2970085560 ps
CPU time 264.06 seconds
Started Jul 29 08:33:49 PM PDT 24
Finished Jul 29 08:38:13 PM PDT 24
Peak memory 609656 kb
Host smart-44c26ceb-9b8a-4236-8813-114a9af45a7e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357238573 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.2357238573
Directory /workspace/1.chip_sw_sram_ctrl_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3529903818
Short name T1085
Test name
Test status
Simulation time 20321783053 ps
CPU time 3187.8 seconds
Started Jul 29 08:29:30 PM PDT 24
Finished Jul 29 09:22:40 PM PDT 24
Peak memory 610584 kb
Host smart-b84c25fb-b54a-4e07-bc84-a3959bf19fce
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529903818 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.3529903818
Directory /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3560986936
Short name T211
Test name
Test status
Simulation time 4715641438 ps
CPU time 612.94 seconds
Started Jul 29 08:26:56 PM PDT 24
Finished Jul 29 08:37:11 PM PDT 24
Peak memory 613356 kb
Host smart-d61b24ff-7e99-4656-ad38-a342aa739045
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560986936 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.3560986936
Directory /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3774688797
Short name T96
Test name
Test status
Simulation time 3207775290 ps
CPU time 381.37 seconds
Started Jul 29 08:29:20 PM PDT 24
Finished Jul 29 08:35:43 PM PDT 24
Peak memory 613332 kb
Host smart-49aebc0b-3607-4e10-a810-a4b4db971d09
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774688797 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.3774688797
Directory /workspace/1.chip_sw_sysrst_ctrl_inputs/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.426823383
Short name T1342
Test name
Test status
Simulation time 3495360384 ps
CPU time 422.48 seconds
Started Jul 29 08:29:15 PM PDT 24
Finished Jul 29 08:36:19 PM PDT 24
Peak memory 610052 kb
Host smart-b96b0881-4b4f-4258-805c-a95b56be32e6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426823383 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.426823383
Directory /workspace/1.chip_sw_sysrst_ctrl_outputs/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2429176367
Short name T35
Test name
Test status
Simulation time 5167771812 ps
CPU time 363.08 seconds
Started Jul 29 08:29:35 PM PDT 24
Finished Jul 29 08:35:39 PM PDT 24
Peak memory 610512 kb
Host smart-d1024379-456a-45a8-8f5b-598dd6437ab8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429176367 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2429176367
Directory /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.96675710
Short name T1084
Test name
Test status
Simulation time 8826543812 ps
CPU time 1970.96 seconds
Started Jul 29 08:28:10 PM PDT 24
Finished Jul 29 09:01:02 PM PDT 24
Peak memory 624468 kb
Host smart-2ffe5394-ab88-4191-98de-a8aa3e037265
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=96675710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.96675710
Directory /workspace/1.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/1.chip_sw_uart_smoketest.1077392039
Short name T919
Test name
Test status
Simulation time 2458715490 ps
CPU time 281.27 seconds
Started Jul 29 08:34:46 PM PDT 24
Finished Jul 29 08:39:28 PM PDT 24
Peak memory 610048 kb
Host smart-4caa82f2-2b07-4b24-a48d-ab4d7523ca52
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077392039 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_sw_uart_smoketest.1077392039
Directory /workspace/1.chip_sw_uart_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx.4110822035
Short name T1308
Test name
Test status
Simulation time 4384550156 ps
CPU time 712.91 seconds
Started Jul 29 08:25:17 PM PDT 24
Finished Jul 29 08:37:10 PM PDT 24
Peak memory 623876 kb
Host smart-d0b318b3-267f-478c-a98d-bc89c2fc1920
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110822035 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.4110822035
Directory /workspace/1.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.933022242
Short name T1181
Test name
Test status
Simulation time 8431758345 ps
CPU time 1639.19 seconds
Started Jul 29 08:26:23 PM PDT 24
Finished Jul 29 08:53:42 PM PDT 24
Peak memory 623292 kb
Host smart-b9a9e049-8bd8-47f7-b64b-2a2f66bdb1a6
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933022242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba
udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_
alt_clk_freq.933022242
Directory /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2854701042
Short name T937
Test name
Test status
Simulation time 9236096859 ps
CPU time 1244.44 seconds
Started Jul 29 08:25:48 PM PDT 24
Finished Jul 29 08:46:33 PM PDT 24
Peak memory 619724 kb
Host smart-a9fe2eeb-ca70-440c-a5ce-ce50ef27a2ec
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854701042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.2854701042
Directory /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3761551887
Short name T1110
Test name
Test status
Simulation time 77600435630 ps
CPU time 13058.5 seconds
Started Jul 29 08:28:05 PM PDT 24
Finished Jul 30 12:05:45 AM PDT 24
Peak memory 636044 kb
Host smart-6774e67b-bcc9-47a8-8c88-fc0edb615d65
User root
Command /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3761551887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.3761551887
Directory /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2341748963
Short name T935
Test name
Test status
Simulation time 3982450134 ps
CPU time 466.98 seconds
Started Jul 29 08:26:43 PM PDT 24
Finished Jul 29 08:34:30 PM PDT 24
Peak memory 623924 kb
Host smart-d66e61ef-f621-4d23-acb1-3b4b9e942d9b
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341748963 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.2341748963
Directory /workspace/1.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3249178497
Short name T337
Test name
Test status
Simulation time 4342340982 ps
CPU time 727.01 seconds
Started Jul 29 08:27:29 PM PDT 24
Finished Jul 29 08:39:37 PM PDT 24
Peak memory 623952 kb
Host smart-abba2588-bd8e-44f6-a73e-a8e93145299a
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249178497 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.3249178497
Directory /workspace/1.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.117321193
Short name T1351
Test name
Test status
Simulation time 3801875332 ps
CPU time 672.38 seconds
Started Jul 29 08:25:37 PM PDT 24
Finished Jul 29 08:36:50 PM PDT 24
Peak memory 623840 kb
Host smart-e41eb703-2f13-4978-ac27-451e5644020d
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117321193 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.117321193
Directory /workspace/1.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/1.chip_tap_straps_dev.820853631
Short name T1361
Test name
Test status
Simulation time 3872409344 ps
CPU time 308.69 seconds
Started Jul 29 08:29:44 PM PDT 24
Finished Jul 29 08:34:52 PM PDT 24
Peak memory 624204 kb
Host smart-a3098256-2b58-43f6-baf7-2c76e4a7348c
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=820853631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.820853631
Directory /workspace/1.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/1.chip_tap_straps_rma.1273579143
Short name T64
Test name
Test status
Simulation time 6730711355 ps
CPU time 877.87 seconds
Started Jul 29 08:27:39 PM PDT 24
Finished Jul 29 08:42:17 PM PDT 24
Peak memory 632856 kb
Host smart-b5230a7a-112a-44b3-9b0f-77ffee8e218d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273579143 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.1273579143
Directory /workspace/1.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/1.chip_tap_straps_testunlock0.3260821298
Short name T65
Test name
Test status
Simulation time 3817954500 ps
CPU time 319.21 seconds
Started Jul 29 08:26:47 PM PDT 24
Finished Jul 29 08:32:06 PM PDT 24
Peak memory 621036 kb
Host smart-0fcd4b4a-d042-4d7f-9499-29acb517c323
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260821298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.3260821298
Directory /workspace/1.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_dev.1338606664
Short name T993
Test name
Test status
Simulation time 16204213880 ps
CPU time 4298.95 seconds
Started Jul 29 08:39:15 PM PDT 24
Finished Jul 29 09:50:55 PM PDT 24
Peak memory 610244 kb
Host smart-07d2f220-5407-4f23-974a-b604176e0b86
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338606664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rom_e2e_asm_init_dev.1338606664
Directory /workspace/1.rom_e2e_asm_init_dev/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_prod.3628096720
Short name T1033
Test name
Test status
Simulation time 15598984524 ps
CPU time 4281.52 seconds
Started Jul 29 08:39:14 PM PDT 24
Finished Jul 29 09:50:36 PM PDT 24
Peak memory 610248 kb
Host smart-c981018c-f251-4da9-aa53-b635e4429adb
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628096720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_
SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rom_e2e_asm_init_prod.3628096720
Directory /workspace/1.rom_e2e_asm_init_prod/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1360369466
Short name T946
Test name
Test status
Simulation time 15503736570 ps
CPU time 4386.08 seconds
Started Jul 29 08:34:02 PM PDT 24
Finished Jul 29 09:47:09 PM PDT 24
Peak memory 610276 kb
Host smart-f195b8c0-f5a2-4db2-a19c-b11a322a935c
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360369466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_e2e_asm_init_prod_end.1360369466
Directory /workspace/1.rom_e2e_asm_init_prod_end/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_rma.3590281757
Short name T1035
Test name
Test status
Simulation time 15079459469 ps
CPU time 3371 seconds
Started Jul 29 08:32:57 PM PDT 24
Finished Jul 29 09:29:09 PM PDT 24
Peak memory 610164 kb
Host smart-eb8b28fc-7c2f-4a47-9ad1-04fa46b21b95
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590281757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rom_e2e_asm_init_rma.3590281757
Directory /workspace/1.rom_e2e_asm_init_rma/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3578077233
Short name T962
Test name
Test status
Simulation time 11198456506 ps
CPU time 2833.79 seconds
Started Jul 29 08:33:47 PM PDT 24
Finished Jul 29 09:21:01 PM PDT 24
Peak memory 610560 kb
Host smart-64fcf5d9-af43-4dc5-a06e-609c5c101d68
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578077233 -assert nopostproc +UVM_TESTNAME=chip_base_te
st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.rom_e2e_asm_init_test_unlocked0.3578077233
Directory /workspace/1.rom_e2e_asm_init_test_unlocked0/latest

Test location /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2521785929
Short name T1164
Test name
Test status
Simulation time 14891849992 ps
CPU time 4270.66 seconds
Started Jul 29 08:39:57 PM PDT 24
Finished Jul 29 09:51:08 PM PDT 24
Peak memory 609948 kb
Host smart-aba4bb1f-a56b-4a27-9d0b-7c040fe6f336
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid
_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521785929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip
_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in
it_rom_ext_invalid_meas.2521785929
Directory /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.3454303761
Short name T1069
Test name
Test status
Simulation time 15139410900 ps
CPU time 4352.58 seconds
Started Jul 29 08:39:50 PM PDT 24
Finished Jul 29 09:52:23 PM PDT 24
Peak memory 609952 kb
Host smart-55b5bcf9-cb28-41a3-845b-9523493e2f42
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:
new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454303761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.3454303761
Directory /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.4062394609
Short name T399
Test name
Test status
Simulation time 15347739608 ps
CPU time 3594.87 seconds
Started Jul 29 08:34:24 PM PDT 24
Finished Jul 29 09:34:19 PM PDT 24
Peak memory 610088 kb
Host smart-7074f5dd-a1f6-4daf-b7d7-c1454f474f38
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas
:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062394609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext
_no_meas.4062394609
Directory /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location /workspace/coverage/default/1.rom_e2e_self_hash.955969391
Short name T1139
Test name
Test status
Simulation time 26572804180 ps
CPU time 5560.95 seconds
Started Jul 29 08:31:49 PM PDT 24
Finished Jul 29 10:04:30 PM PDT 24
Peak memory 610072 kb
Host smart-f0c4187a-129d-4704-8ec8-65fbfc97792b
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r
ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955969391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.955969391
Directory /workspace/1.rom_e2e_self_hash/latest

Test location /workspace/coverage/default/1.rom_e2e_shutdown_output.1860372725
Short name T276
Test name
Test status
Simulation time 22281641400 ps
CPU time 3620.25 seconds
Started Jul 29 08:35:04 PM PDT 24
Finished Jul 29 09:35:25 PM PDT 24
Peak memory 611784 kb
Host smart-ab545ab5-a42b-40bc-97a1-56b17a85e6f8
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f
lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860372725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rom_e2e_shutdown_output.1860372725
Directory /workspace/1.rom_e2e_shutdown_output/latest

Test location /workspace/coverage/default/1.rom_e2e_smoke.3643504503
Short name T1290
Test name
Test status
Simulation time 15498258804 ps
CPU time 3475.97 seconds
Started Jul 29 08:37:02 PM PDT 24
Finished Jul 29 09:34:58 PM PDT 24
Peak memory 610016 kb
Host smart-c610a46e-0974-44f8-8c2c-e1d3c2ef8075
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img
_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to
p/hw/dv/tools/sim.tcl +ntb_random_seed=3643504503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.3643504503
Directory /workspace/1.rom_e2e_smoke/latest

Test location /workspace/coverage/default/1.rom_e2e_static_critical.3198525960
Short name T1037
Test name
Test status
Simulation time 17623613528 ps
CPU time 4370.31 seconds
Started Jul 29 08:39:45 PM PDT 24
Finished Jul 29 09:52:36 PM PDT 24
Peak memory 609948 kb
Host smart-945c8de9-ea70-4f45-94e4-af6687aa792d
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul
es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198525960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.3198525960
Directory /workspace/1.rom_e2e_static_critical/latest

Test location /workspace/coverage/default/1.rom_keymgr_functest.458760506
Short name T1146
Test name
Test status
Simulation time 3749427140 ps
CPU time 613.16 seconds
Started Jul 29 08:31:17 PM PDT 24
Finished Jul 29 08:41:31 PM PDT 24
Peak memory 610272 kb
Host smart-a5679500-4adb-41d4-85d3-4256ea43ff0b
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458760506 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.458760506
Directory /workspace/1.rom_keymgr_functest/latest

Test location /workspace/coverage/default/1.rom_raw_unlock.2340526837
Short name T747
Test name
Test status
Simulation time 5893989688 ps
CPU time 292.98 seconds
Started Jul 29 08:30:34 PM PDT 24
Finished Jul 29 08:35:27 PM PDT 24
Peak memory 619860 kb
Host smart-fe40af1f-ec1e-4a22-9c19-e833144bb0f5
User root
Command /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE
xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2340526837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.2340526837
Directory /workspace/1.rom_raw_unlock/latest

Test location /workspace/coverage/default/1.rom_volatile_raw_unlock.2292272337
Short name T97
Test name
Test status
Simulation time 3186882968 ps
CPU time 136.05 seconds
Started Jul 29 08:30:43 PM PDT 24
Finished Jul 29 08:33:00 PM PDT 24
Peak memory 618148 kb
Host smart-ec2f8b65-ecff-420f-a999-06d8452dce6f
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1
+sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292272337 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.2292272337
Directory /workspace/1.rom_volatile_raw_unlock/latest

Test location /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1570549216
Short name T104
Test name
Test status
Simulation time 3944162464 ps
CPU time 421.83 seconds
Started Jul 29 08:44:19 PM PDT 24
Finished Jul 29 08:51:21 PM PDT 24
Peak memory 618656 kb
Host smart-45439d1d-1da7-4336-bc17-07afc6746d93
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570549216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1570549216
Directory /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3219260820
Short name T1285
Test name
Test status
Simulation time 12986751137 ps
CPU time 921.73 seconds
Started Jul 29 08:44:55 PM PDT 24
Finished Jul 29 09:00:17 PM PDT 24
Peak memory 620624 kb
Host smart-36ebb59c-c4a2-4f4e-94d4-6a4798cebb13
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219260820 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.3219260820
Directory /workspace/10.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2576665175
Short name T221
Test name
Test status
Simulation time 3494554254 ps
CPU time 464.36 seconds
Started Jul 29 08:43:48 PM PDT 24
Finished Jul 29 08:51:33 PM PDT 24
Peak memory 623224 kb
Host smart-a12e461b-edc0-472f-a6c9-61aace553306
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2576665175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.2576665175
Directory /workspace/10.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.103528282
Short name T1020
Test name
Test status
Simulation time 10746141934 ps
CPU time 896.72 seconds
Started Jul 29 08:43:04 PM PDT 24
Finished Jul 29 08:58:01 PM PDT 24
Peak memory 620472 kb
Host smart-b2c455f2-1ff6-4d22-9a7d-e77290515fc2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103528282 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.103528282
Directory /workspace/11.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1299658456
Short name T954
Test name
Test status
Simulation time 13393466562 ps
CPU time 2137.35 seconds
Started Jul 29 08:43:50 PM PDT 24
Finished Jul 29 09:19:28 PM PDT 24
Peak memory 624584 kb
Host smart-68098a24-74c0-4127-bf27-84e1b58207bc
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1299658456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.1299658456
Directory /workspace/11.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.528834138
Short name T1149
Test name
Test status
Simulation time 7344458247 ps
CPU time 559.14 seconds
Started Jul 29 08:43:18 PM PDT 24
Finished Jul 29 08:52:37 PM PDT 24
Peak memory 620520 kb
Host smart-e694d589-2f27-417f-a46b-5684c96ef28f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528834138 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.528834138
Directory /workspace/12.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1382462770
Short name T1080
Test name
Test status
Simulation time 8481035548 ps
CPU time 1798.05 seconds
Started Jul 29 08:44:12 PM PDT 24
Finished Jul 29 09:14:10 PM PDT 24
Peak memory 624448 kb
Host smart-1f6e0e39-099e-4428-bd75-cdb09349c3c0
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1382462770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.1382462770
Directory /workspace/12.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/13.chip_sw_all_escalation_resets.3516688921
Short name T791
Test name
Test status
Simulation time 4683663896 ps
CPU time 520.92 seconds
Started Jul 29 08:44:01 PM PDT 24
Finished Jul 29 08:52:42 PM PDT 24
Peak memory 650680 kb
Host smart-d42327b8-5818-40f5-a0e8-34b9b63bbcea
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3516688921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.3516688921
Directory /workspace/13.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2891150392
Short name T1125
Test name
Test status
Simulation time 12131881571 ps
CPU time 987.16 seconds
Started Jul 29 08:43:04 PM PDT 24
Finished Jul 29 08:59:31 PM PDT 24
Peak memory 620888 kb
Host smart-c1f5180d-a574-44fc-8860-30bc077accf8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891150392 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.2891150392
Directory /workspace/13.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.378449924
Short name T14
Test name
Test status
Simulation time 4109964152 ps
CPU time 462.48 seconds
Started Jul 29 08:45:23 PM PDT 24
Finished Jul 29 08:53:06 PM PDT 24
Peak memory 623296 kb
Host smart-4b1158b8-1ae9-42b7-993a-6f276fed8dd1
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=378449924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.378449924
Directory /workspace/13.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3024389864
Short name T1119
Test name
Test status
Simulation time 13414844036 ps
CPU time 2189.72 seconds
Started Jul 29 08:46:02 PM PDT 24
Finished Jul 29 09:22:34 PM PDT 24
Peak memory 624688 kb
Host smart-c5dd6ebd-da36-4486-8f44-41e6e7cc4259
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3024389864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.3024389864
Directory /workspace/14.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3507576982
Short name T142
Test name
Test status
Simulation time 7633603188 ps
CPU time 1278.12 seconds
Started Jul 29 08:44:37 PM PDT 24
Finished Jul 29 09:05:55 PM PDT 24
Peak memory 623144 kb
Host smart-a435a609-e191-4690-9eb2-b543341bc589
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3507576982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.3507576982
Directory /workspace/15.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/16.chip_sw_all_escalation_resets.2561789718
Short name T423
Test name
Test status
Simulation time 5534852792 ps
CPU time 710.29 seconds
Started Jul 29 08:43:44 PM PDT 24
Finished Jul 29 08:55:35 PM PDT 24
Peak memory 650100 kb
Host smart-0a639963-49c8-434f-9ed2-d0602b697dc5
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2561789718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.2561789718
Directory /workspace/16.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2018596467
Short name T1011
Test name
Test status
Simulation time 8565641310 ps
CPU time 1353.94 seconds
Started Jul 29 08:44:11 PM PDT 24
Finished Jul 29 09:06:45 PM PDT 24
Peak memory 623344 kb
Host smart-b2b891c4-1d29-4c4f-9d1d-974d3ebd1164
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2018596467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.2018596467
Directory /workspace/16.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3731385780
Short name T805
Test name
Test status
Simulation time 3590848140 ps
CPU time 338.19 seconds
Started Jul 29 08:44:24 PM PDT 24
Finished Jul 29 08:50:02 PM PDT 24
Peak memory 648836 kb
Host smart-9b0d9d63-f5d0-4704-8e27-43cc29ded8f9
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731385780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3731385780
Directory /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/18.chip_sw_all_escalation_resets.2891606658
Short name T807
Test name
Test status
Simulation time 5854807224 ps
CPU time 598.87 seconds
Started Jul 29 08:43:50 PM PDT 24
Finished Jul 29 08:53:49 PM PDT 24
Peak memory 650256 kb
Host smart-c04dcbf4-267e-45b5-9440-b887aefd1abe
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2891606658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.2891606658
Directory /workspace/18.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1262672912
Short name T1158
Test name
Test status
Simulation time 13473894100 ps
CPU time 2436.08 seconds
Started Jul 29 08:43:51 PM PDT 24
Finished Jul 29 09:24:28 PM PDT 24
Peak memory 624568 kb
Host smart-e215c343-2ed8-4e88-b2d9-1ac552a1b1b2
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1262672912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.1262672912
Directory /workspace/18.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/19.chip_sw_all_escalation_resets.2569938491
Short name T404
Test name
Test status
Simulation time 5096509688 ps
CPU time 509.34 seconds
Started Jul 29 08:44:58 PM PDT 24
Finished Jul 29 08:53:27 PM PDT 24
Peak memory 650636 kb
Host smart-70cc1d56-6321-432d-ad6f-0a9138883a06
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2569938491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.2569938491
Directory /workspace/19.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1321973103
Short name T1063
Test name
Test status
Simulation time 12378483016 ps
CPU time 2047.47 seconds
Started Jul 29 08:45:49 PM PDT 24
Finished Jul 29 09:19:57 PM PDT 24
Peak memory 624592 kb
Host smart-27f03a49-52b2-46e9-9b68-79f8a4fdf674
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1321973103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.1321973103
Directory /workspace/19.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/2.chip_jtag_csr_rw.1473220927
Short name T86
Test name
Test status
Simulation time 11989827347 ps
CPU time 1550.94 seconds
Started Jul 29 08:30:04 PM PDT 24
Finished Jul 29 08:55:56 PM PDT 24
Peak memory 608104 kb
Host smart-6ce3635d-d610-41f5-b5be-17b71d3f99a6
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473220927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c
hip_jtag_csr_rw.1473220927
Directory /workspace/2.chip_jtag_csr_rw/latest

Test location /workspace/coverage/default/2.chip_jtag_mem_access.1191973994
Short name T78
Test name
Test status
Simulation time 13226359272 ps
CPU time 1764.77 seconds
Started Jul 29 08:29:44 PM PDT 24
Finished Jul 29 08:59:09 PM PDT 24
Peak memory 607988 kb
Host smart-da40aefc-9547-4b43-a72e-070f4a85604e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191973994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_
mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.1
191973994
Directory /workspace/2.chip_jtag_mem_access/latest

Test location /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3566131819
Short name T408
Test name
Test status
Simulation time 4788540686 ps
CPU time 545.17 seconds
Started Jul 29 08:38:06 PM PDT 24
Finished Jul 29 08:47:11 PM PDT 24
Peak memory 621160 kb
Host smart-7ea7f23b-8e62-4812-ae0e-3f5c70664e3c
User root
Command /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3
566131819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.3566131819
Directory /workspace/2.chip_rv_dm_ndm_reset_req/latest

Test location /workspace/coverage/default/2.chip_sival_flash_info_access.1542196266
Short name T985
Test name
Test status
Simulation time 3196951244 ps
CPU time 260.44 seconds
Started Jul 29 08:29:42 PM PDT 24
Finished Jul 29 08:34:03 PM PDT 24
Peak memory 609908 kb
Host smart-a30c403f-4732-47b2-91b8-3174da1059ed
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=1542196266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.1542196266
Directory /workspace/2.chip_sival_flash_info_access/latest

Test location /workspace/coverage/default/2.chip_sw_aes_enc.1635617524
Short name T414
Test name
Test status
Simulation time 3214023584 ps
CPU time 228.05 seconds
Started Jul 29 08:39:12 PM PDT 24
Finished Jul 29 08:43:01 PM PDT 24
Peak memory 609328 kb
Host smart-3cd847b7-5e74-4491-8945-389f218b3905
User root
Command /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635617524 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.1635617524
Directory /workspace/2.chip_sw_aes_enc/latest

Test location /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3985937706
Short name T1134
Test name
Test status
Simulation time 3309650883 ps
CPU time 257.86 seconds
Started Jul 29 08:39:16 PM PDT 24
Finished Jul 29 08:43:34 PM PDT 24
Peak memory 608612 kb
Host smart-a74c2ce4-98e1-476f-a681-4f0282e31211
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985
937706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.3985937706
Directory /workspace/2.chip_sw_aes_enc_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1583256083
Short name T1296
Test name
Test status
Simulation time 3540413098 ps
CPU time 208.23 seconds
Started Jul 29 08:40:34 PM PDT 24
Finished Jul 29 08:44:02 PM PDT 24
Peak memory 609600 kb
Host smart-a019acd5-88b0-43e5-a1ab-a75637858aab
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1583256083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.1583256083
Directory /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_aes_entropy.1155916683
Short name T936
Test name
Test status
Simulation time 2825809644 ps
CPU time 227.62 seconds
Started Jul 29 08:33:59 PM PDT 24
Finished Jul 29 08:37:47 PM PDT 24
Peak memory 609396 kb
Host smart-1246e532-a23b-4ffb-b4fa-902e6f21ec71
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155916683 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.1155916683
Directory /workspace/2.chip_sw_aes_entropy/latest

Test location /workspace/coverage/default/2.chip_sw_aes_idle.4174630413
Short name T106
Test name
Test status
Simulation time 2408534908 ps
CPU time 228.65 seconds
Started Jul 29 08:33:09 PM PDT 24
Finished Jul 29 08:36:58 PM PDT 24
Peak memory 609668 kb
Host smart-a1f7efa8-5968-4fff-8cc7-615840f909a8
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174630413 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.4174630413
Directory /workspace/2.chip_sw_aes_idle/latest

Test location /workspace/coverage/default/2.chip_sw_aes_masking_off.1593461766
Short name T702
Test name
Test status
Simulation time 2841064643 ps
CPU time 298.72 seconds
Started Jul 29 08:33:13 PM PDT 24
Finished Jul 29 08:38:12 PM PDT 24
Peak memory 609400 kb
Host smart-95d79eef-b48f-4fa3-a7b5-fe0022450209
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593461766 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.1593461766
Directory /workspace/2.chip_sw_aes_masking_off/latest

Test location /workspace/coverage/default/2.chip_sw_aes_smoketest.4021867415
Short name T1167
Test name
Test status
Simulation time 2981336356 ps
CPU time 312.59 seconds
Started Jul 29 08:39:14 PM PDT 24
Finished Jul 29 08:44:27 PM PDT 24
Peak memory 609728 kb
Host smart-334106b3-dd93-4f1f-85f0-89ff276fbe97
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021867415 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_aes_smoketest.4021867415
Directory /workspace/2.chip_sw_aes_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_entropy.985793019
Short name T161
Test name
Test status
Simulation time 3366166787 ps
CPU time 292.47 seconds
Started Jul 29 08:34:02 PM PDT 24
Finished Jul 29 08:38:55 PM PDT 24
Peak memory 609700 kb
Host smart-48df06ac-662a-4f74-858c-1aaa66fe8ada
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=985793019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.985793019
Directory /workspace/2.chip_sw_alert_handler_entropy/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_escalation.981025799
Short name T66
Test name
Test status
Simulation time 4702070252 ps
CPU time 587.32 seconds
Started Jul 29 08:37:16 PM PDT 24
Finished Jul 29 08:47:03 PM PDT 24
Peak memory 619512 kb
Host smart-b54d39d2-dbc6-4b58-aa5e-b01ae29c7929
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=981025799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.981025799
Directory /workspace/2.chip_sw_alert_handler_escalation/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2729950987
Short name T310
Test name
Test status
Simulation time 8406643360 ps
CPU time 1889 seconds
Started Jul 29 08:35:22 PM PDT 24
Finished Jul 29 09:06:51 PM PDT 24
Peak memory 610184 kb
Host smart-c4f3f1d4-9a18-4790-903f-56d2b5883df2
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2729950987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.2729950987
Directory /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.504091563
Short name T216
Test name
Test status
Simulation time 6479015756 ps
CPU time 1299.74 seconds
Started Jul 29 08:34:00 PM PDT 24
Finished Jul 29 08:55:40 PM PDT 24
Peak memory 610224 kb
Host smart-39f79230-9c29-4daa-94be-203cd0fbc954
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=504091563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_toggle.504091563
Directory /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.55110645
Short name T1099
Test name
Test status
Simulation time 3258006760 ps
CPU time 401.06 seconds
Started Jul 29 08:37:20 PM PDT 24
Finished Jul 29 08:44:01 PM PDT 24
Peak memory 618884 kb
Host smart-f2e93547-bf14-4afb-a98b-12b32b3b6f46
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55110645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_
escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_
alert_handler_lpg_sleep_mode_alerts.55110645
Directory /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2732350795
Short name T83
Test name
Test status
Simulation time 12573238298 ps
CPU time 1458.63 seconds
Started Jul 29 08:35:41 PM PDT 24
Finished Jul 29 09:00:00 PM PDT 24
Peak memory 610656 kb
Host smart-38ccee39-2c02-401f-bcc9-f1b7c0c4f72c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler
_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732350795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han
dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.chip_sw_alert_handler_lpg_sleep_mode_pings.2732350795
Directory /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.730030548
Short name T1018
Test name
Test status
Simulation time 8101327492 ps
CPU time 1366.43 seconds
Started Jul 29 08:34:54 PM PDT 24
Finished Jul 29 08:57:41 PM PDT 24
Peak memory 610092 kb
Host smart-29d4d3d5-876e-47df-b5c4-01128559d19d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=730030548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.730030548
Directory /workspace/2.chip_sw_alert_handler_ping_ok/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3634419989
Short name T1174
Test name
Test status
Simulation time 6078221204 ps
CPU time 511.16 seconds
Started Jul 29 08:39:48 PM PDT 24
Finished Jul 29 08:48:19 PM PDT 24
Peak memory 610280 kb
Host smart-b3bbcf00-50ec-4157-9b35-f54a89543d92
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3634419989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.3634419989
Directory /workspace/2.chip_sw_alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1657182332
Short name T166
Test name
Test status
Simulation time 254750029314 ps
CPU time 12427 seconds
Started Jul 29 08:34:45 PM PDT 24
Finished Jul 30 12:01:54 AM PDT 24
Peak memory 610700 kb
Host smart-36878588-7b46-4f8f-8583-537ca45efbaa
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657182332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1657182332
Directory /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location /workspace/coverage/default/2.chip_sw_alert_test.2855677046
Short name T52
Test name
Test status
Simulation time 2674067420 ps
CPU time 323.17 seconds
Started Jul 29 08:33:24 PM PDT 24
Finished Jul 29 08:38:47 PM PDT 24
Peak memory 609984 kb
Host smart-a6f3d10e-d43b-41ba-8a96-35e144d541df
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855677046 -assert nopostproc +UVM_TESTNAME=chip_ba
se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.chip_sw_alert_test.2855677046
Directory /workspace/2.chip_sw_alert_test/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_irq.3205553893
Short name T1122
Test name
Test status
Simulation time 3846344168 ps
CPU time 382.21 seconds
Started Jul 29 08:33:55 PM PDT 24
Finished Jul 29 08:40:18 PM PDT 24
Peak memory 609764 kb
Host smart-fc40a7e5-e045-4d30-a210-6e05fc0c51e0
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205553893 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.3205553893
Directory /workspace/2.chip_sw_aon_timer_irq/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3508995380
Short name T1056
Test name
Test status
Simulation time 7952480670 ps
CPU time 492.89 seconds
Started Jul 29 08:35:22 PM PDT 24
Finished Jul 29 08:43:35 PM PDT 24
Peak memory 610576 kb
Host smart-fb23c7f5-8b30-4b01-ae1e-7fcb1f256b32
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3508995380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3508995380
Directory /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1054623874
Short name T1249
Test name
Test status
Simulation time 3681968414 ps
CPU time 362.46 seconds
Started Jul 29 08:38:59 PM PDT 24
Finished Jul 29 08:45:01 PM PDT 24
Peak memory 609696 kb
Host smart-33826554-27da-4752-906a-0eccc8dbdfaf
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054623874 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_aon_timer_smoketest.1054623874
Directory /workspace/2.chip_sw_aon_timer_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3683697385
Short name T1301
Test name
Test status
Simulation time 8109881736 ps
CPU time 777.83 seconds
Started Jul 29 08:38:03 PM PDT 24
Finished Jul 29 08:51:02 PM PDT 24
Peak memory 610580 kb
Host smart-39b600cd-1689-44dd-85b7-4b3f5efb35fe
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3683697385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.3683697385
Directory /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1894402982
Short name T721
Test name
Test status
Simulation time 5434002610 ps
CPU time 524.47 seconds
Started Jul 29 08:35:21 PM PDT 24
Finished Jul 29 08:44:06 PM PDT 24
Peak memory 610772 kb
Host smart-c1a7f8ef-4dfc-4c05-90eb-d88b49221577
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1894402982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.1894402982
Directory /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location /workspace/coverage/default/2.chip_sw_ast_clk_outputs.487171983
Short name T777
Test name
Test status
Simulation time 6419943068 ps
CPU time 1097.53 seconds
Started Jul 29 08:36:09 PM PDT 24
Finished Jul 29 08:54:27 PM PDT 24
Peak memory 616216 kb
Host smart-4cc69041-d56d-4a6f-930e-1a3e415f17de
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487171983 -assert nopos
tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.487171983
Directory /workspace/2.chip_sw_ast_clk_outputs/latest

Test location /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1407055544
Short name T140
Test name
Test status
Simulation time 19594039085 ps
CPU time 2295.93 seconds
Started Jul 29 08:37:49 PM PDT 24
Finished Jul 29 09:16:06 PM PDT 24
Peak memory 611176 kb
Host smart-29955aad-19b1-4748-ba15-cab06cc5ece8
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407055544
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.1407055544
Directory /workspace/2.chip_sw_ast_clk_rst_inputs/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.589753138
Short name T1298
Test name
Test status
Simulation time 7223757671 ps
CPU time 463.24 seconds
Started Jul 29 08:35:42 PM PDT 24
Finished Jul 29 08:43:26 PM PDT 24
Peak memory 621532 kb
Host smart-8e246ed3-af27-4b51-b975-84050894bb71
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=589753138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.589753138
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2138787457
Short name T1165
Test name
Test status
Simulation time 3787317026 ps
CPU time 559.72 seconds
Started Jul 29 08:36:46 PM PDT 24
Finished Jul 29 08:46:06 PM PDT 24
Peak memory 612008 kb
Host smart-09fda8de-5fa2-4bb5-8ce3-35b1d88fd419
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138787457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_dev.2138787457
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1906457349
Short name T1111
Test name
Test status
Simulation time 4479736612 ps
CPU time 682.28 seconds
Started Jul 29 08:37:04 PM PDT 24
Finished Jul 29 08:48:27 PM PDT 24
Peak memory 612120 kb
Host smart-02049c76-3441-4c83-9ea7-107610e7491c
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906457349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_rma.1906457349
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.220915008
Short name T146
Test name
Test status
Simulation time 5123619936 ps
CPU time 730.44 seconds
Started Jul 29 08:38:18 PM PDT 24
Finished Jul 29 08:50:29 PM PDT 24
Peak memory 612184 kb
Host smart-03bc9881-c8ae-498b-ba7c-d183331af04c
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220915008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl
kmgr_external_clk_src_for_sw_slow_dev.220915008
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1402709287
Short name T1042
Test name
Test status
Simulation time 5108820392 ps
CPU time 487.53 seconds
Started Jul 29 08:36:25 PM PDT 24
Finished Jul 29 08:44:32 PM PDT 24
Peak memory 613128 kb
Host smart-cd7f5c3b-1904-49dc-a49f-4104f1abf80e
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402709287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_rma.1402709287
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3690352949
Short name T951
Test name
Test status
Simulation time 4906541928 ps
CPU time 709.35 seconds
Started Jul 29 08:37:23 PM PDT 24
Finished Jul 29 08:49:13 PM PDT 24
Peak memory 612896 kb
Host smart-d8fcb4b3-f1b7-40c7-9913-a29639a6d9f2
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690352949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3690352949
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3138473659
Short name T911
Test name
Test status
Simulation time 3312208581 ps
CPU time 207.62 seconds
Started Jul 29 08:37:33 PM PDT 24
Finished Jul 29 08:41:01 PM PDT 24
Peak memory 609540 kb
Host smart-67fe81a9-eae9-4a23-89da-32286aeca11f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138473659 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_clkmgr_jitter.3138473659
Directory /workspace/2.chip_sw_clkmgr_jitter/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1623456616
Short name T1073
Test name
Test status
Simulation time 3312637016 ps
CPU time 401.51 seconds
Started Jul 29 08:36:57 PM PDT 24
Finished Jul 29 08:43:39 PM PDT 24
Peak memory 609672 kb
Host smart-4f946ec7-9230-4a7c-8c0f-21145f060979
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623456616 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.1623456616
Directory /workspace/2.chip_sw_clkmgr_jitter_frequency/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.4080390233
Short name T1131
Test name
Test status
Simulation time 2680678980 ps
CPU time 233.8 seconds
Started Jul 29 08:38:24 PM PDT 24
Finished Jul 29 08:42:18 PM PDT 24
Peak memory 609604 kb
Host smart-b18a4490-97c3-4e35-a989-4d2e81a88fb2
User root
Command /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080390233 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.4080390233
Directory /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1552621795
Short name T991
Test name
Test status
Simulation time 4912149248 ps
CPU time 516.96 seconds
Started Jul 29 08:36:14 PM PDT 24
Finished Jul 29 08:44:51 PM PDT 24
Peak memory 610464 kb
Host smart-ae2e710e-248c-4356-a275-6d8f9c2d15b2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552621795 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.1552621795
Directory /workspace/2.chip_sw_clkmgr_off_aes_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1617950476
Short name T960
Test name
Test status
Simulation time 3843673192 ps
CPU time 455.42 seconds
Started Jul 29 08:38:52 PM PDT 24
Finished Jul 29 08:46:28 PM PDT 24
Peak memory 609884 kb
Host smart-4e36c55b-2df3-403d-a19d-2ceb30b895ba
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617950476 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.1617950476
Directory /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3497786688
Short name T987
Test name
Test status
Simulation time 4606642300 ps
CPU time 394.51 seconds
Started Jul 29 08:35:19 PM PDT 24
Finished Jul 29 08:41:53 PM PDT 24
Peak memory 610500 kb
Host smart-b42c23cc-4711-4fd2-a518-8b4bcd867e73
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497786688 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.3497786688
Directory /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.2480736348
Short name T1328
Test name
Test status
Simulation time 4146432600 ps
CPU time 543.71 seconds
Started Jul 29 08:37:53 PM PDT 24
Finished Jul 29 08:46:57 PM PDT 24
Peak memory 610048 kb
Host smart-a79a582a-1910-4e77-8c94-f72b19a81d56
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480736348 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.2480736348
Directory /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3727721009
Short name T1186
Test name
Test status
Simulation time 12476376162 ps
CPU time 1367.75 seconds
Started Jul 29 08:35:46 PM PDT 24
Finished Jul 29 08:58:34 PM PDT 24
Peak memory 610568 kb
Host smart-354d4084-d8d5-4791-8503-93b5460f1146
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727721009
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.3727721009
Directory /workspace/2.chip_sw_clkmgr_off_peri/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.4029580894
Short name T1364
Test name
Test status
Simulation time 3946136964 ps
CPU time 635.32 seconds
Started Jul 29 08:37:02 PM PDT 24
Finished Jul 29 08:47:38 PM PDT 24
Peak memory 609768 kb
Host smart-fbbea9cb-30db-487d-9e36-9480a05f13a7
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029580894 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.4029580894
Directory /workspace/2.chip_sw_clkmgr_reset_frequency/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2466872099
Short name T372
Test name
Test status
Simulation time 4944001800 ps
CPU time 616.86 seconds
Started Jul 29 08:37:31 PM PDT 24
Finished Jul 29 08:47:48 PM PDT 24
Peak memory 610292 kb
Host smart-50aed525-61d1-4ff6-a3b8-a9fa613db43b
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466872099 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.2466872099
Directory /workspace/2.chip_sw_clkmgr_sleep_frequency/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2629216407
Short name T910
Test name
Test status
Simulation time 2697768920 ps
CPU time 292.62 seconds
Started Jul 29 08:39:17 PM PDT 24
Finished Jul 29 08:44:10 PM PDT 24
Peak memory 609648 kb
Host smart-4dd6b75e-da65-4bea-bbd7-6d5511303980
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629216407 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.chip_sw_clkmgr_smoketest.2629216407
Directory /workspace/2.chip_sw_clkmgr_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.4079762151
Short name T426
Test name
Test status
Simulation time 16780241020 ps
CPU time 4612.56 seconds
Started Jul 29 08:35:23 PM PDT 24
Finished Jul 29 09:52:16 PM PDT 24
Peak memory 610444 kb
Host smart-8f110b7a-54d0-451d-a00d-ae76f5902c34
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079762151 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.4079762151
Directory /workspace/2.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.4011271451
Short name T705
Test name
Test status
Simulation time 138327147810 ps
CPU time 18657.8 seconds
Started Jul 29 08:39:06 PM PDT 24
Finished Jul 30 01:50:05 AM PDT 24
Peak memory 610400 kb
Host smart-e2536b0f-4bc7-4227-a0ce-26d37690425b
User root
Command /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_
cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4011271451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.4011271451
Directory /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3701431224
Short name T193
Test name
Test status
Simulation time 3817886580 ps
CPU time 469.26 seconds
Started Jul 29 08:35:11 PM PDT 24
Finished Jul 29 08:43:00 PM PDT 24
Peak memory 609296 kb
Host smart-bd28d0ee-357d-4b03-831b-be8dade83468
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37014
31224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.3701431224
Directory /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_kat_test.1586196071
Short name T924
Test name
Test status
Simulation time 2875939674 ps
CPU time 196.27 seconds
Started Jul 29 08:34:12 PM PDT 24
Finished Jul 29 08:37:29 PM PDT 24
Peak memory 609620 kb
Host smart-1fcfc8f9-f2fc-4dff-8620-fa0a9066d56a
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586196071 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.1586196071
Directory /workspace/2.chip_sw_csrng_kat_test/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.284092253
Short name T1365
Test name
Test status
Simulation time 7771490870 ps
CPU time 777.36 seconds
Started Jul 29 08:37:20 PM PDT 24
Finished Jul 29 08:50:18 PM PDT 24
Peak memory 610816 kb
Host smart-b5c87921-7c7c-4ffa-af0e-7f3fb36e2c27
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima
ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284092253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l
c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrn
g_lc_hw_debug_en_test.284092253
Directory /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_smoketest.756646250
Short name T1071
Test name
Test status
Simulation time 2702872206 ps
CPU time 252.4 seconds
Started Jul 29 08:41:30 PM PDT 24
Finished Jul 29 08:45:43 PM PDT 24
Peak memory 609584 kb
Host smart-df2d8502-23ea-4e4b-8e52-00c1ac0ce463
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756646250 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_csrng_smoketest.756646250
Directory /workspace/2.chip_sw_csrng_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_data_integrity_escalation.2941477965
Short name T1205
Test name
Test status
Simulation time 6391172056 ps
CPU time 787.05 seconds
Started Jul 29 08:32:28 PM PDT 24
Finished Jul 29 08:45:35 PM PDT 24
Peak memory 611052 kb
Host smart-161e8097-35e6-42c1-b186-8d5bb5211837
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2941477965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.2941477965
Directory /workspace/2.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/2.chip_sw_edn_auto_mode.700305611
Short name T1010
Test name
Test status
Simulation time 6283524912 ps
CPU time 1607.82 seconds
Started Jul 29 08:33:52 PM PDT 24
Finished Jul 29 09:00:40 PM PDT 24
Peak memory 610320 kb
Host smart-23eab8be-284b-49ae-8d92-25c412fa0d23
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700305611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_a
uto_mode.700305611
Directory /workspace/2.chip_sw_edn_auto_mode/latest

Test location /workspace/coverage/default/2.chip_sw_edn_boot_mode.826935120
Short name T699
Test name
Test status
Simulation time 3050427200 ps
CPU time 592 seconds
Started Jul 29 08:35:27 PM PDT 24
Finished Jul 29 08:45:19 PM PDT 24
Peak memory 609740 kb
Host smart-93ed263b-c83d-4ccc-bf08-a7b1e8ca33d3
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826935120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_b
oot_mode.826935120
Directory /workspace/2.chip_sw_edn_boot_mode/latest

Test location /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.866555615
Short name T1032
Test name
Test status
Simulation time 6541216832 ps
CPU time 1049.88 seconds
Started Jul 29 08:35:34 PM PDT 24
Finished Jul 29 08:53:04 PM PDT 24
Peak memory 610980 kb
Host smart-f6348fae-3872-4ab0-a6e2-88a4c3d9392b
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e
ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866555615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.866555615
Directory /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest

Test location /workspace/coverage/default/2.chip_sw_edn_kat.2028711165
Short name T708
Test name
Test status
Simulation time 3249348052 ps
CPU time 706.97 seconds
Started Jul 29 08:37:23 PM PDT 24
Finished Jul 29 08:49:10 PM PDT 24
Peak memory 616548 kb
Host smart-dda003e5-102c-4324-97c0-a816cc94f69e
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3
+accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028711165 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_edn_kat.2028711165
Directory /workspace/2.chip_sw_edn_kat/latest

Test location /workspace/coverage/default/2.chip_sw_edn_sw_mode.3955856622
Short name T1161
Test name
Test status
Simulation time 9613330958 ps
CPU time 1894.05 seconds
Started Jul 29 08:33:56 PM PDT 24
Finished Jul 29 09:05:31 PM PDT 24
Peak memory 609804 kb
Host smart-0f64c145-ddfc-4d0a-8c76-ef0b82438bcc
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955856622 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.3955856622
Directory /workspace/2.chip_sw_edn_sw_mode/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1307026881
Short name T448
Test name
Test status
Simulation time 2463543910 ps
CPU time 209.53 seconds
Started Jul 29 08:35:48 PM PDT 24
Finished Jul 29 08:39:18 PM PDT 24
Peak memory 608664 kb
Host smart-3e6595a3-3582-489c-970d-dec45678d3d7
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13
07026881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.1307026881
Directory /workspace/2.chip_sw_entropy_src_ast_rng_req/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2946977604
Short name T331
Test name
Test status
Simulation time 5953062526 ps
CPU time 1471.78 seconds
Started Jul 29 08:37:34 PM PDT 24
Finished Jul 29 09:02:07 PM PDT 24
Peak memory 608984 kb
Host smart-319f11b1-e21c-4ec8-b8a3-5bc1647680d8
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_
csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2946977604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.2946977604
Directory /workspace/2.chip_sw_entropy_src_csrng/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.615481469
Short name T932
Test name
Test status
Simulation time 2645224432 ps
CPU time 320.5 seconds
Started Jul 29 08:37:18 PM PDT 24
Finished Jul 29 08:42:39 PM PDT 24
Peak memory 608644 kb
Host smart-4afe56d5-b7eb-443f-826d-897f2f146819
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615481469
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.615481469
Directory /workspace/2.chip_sw_entropy_src_kat_test/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3068009744
Short name T1336
Test name
Test status
Simulation time 3715763880 ps
CPU time 663.52 seconds
Started Jul 29 08:40:52 PM PDT 24
Finished Jul 29 08:51:56 PM PDT 24
Peak memory 609792 kb
Host smart-7a8d9edd-364a-4432-95f3-55a826fcb94f
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3068009744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.3068009744
Directory /workspace/2.chip_sw_entropy_src_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_example_concurrency.1708238391
Short name T1030
Test name
Test status
Simulation time 3426767670 ps
CPU time 239.63 seconds
Started Jul 29 08:34:37 PM PDT 24
Finished Jul 29 08:38:36 PM PDT 24
Peak memory 609700 kb
Host smart-2915ceba-d972-4397-a97b-2ddc17c31727
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708238391 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.chip_sw_example_concurrency.1708238391
Directory /workspace/2.chip_sw_example_concurrency/latest

Test location /workspace/coverage/default/2.chip_sw_example_flash.1301702653
Short name T940
Test name
Test status
Simulation time 2370817560 ps
CPU time 317.79 seconds
Started Jul 29 08:33:38 PM PDT 24
Finished Jul 29 08:38:56 PM PDT 24
Peak memory 609532 kb
Host smart-4ceb2a19-3e4e-474c-8c93-a93280bd0e61
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301702653 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_example_flash.1301702653
Directory /workspace/2.chip_sw_example_flash/latest

Test location /workspace/coverage/default/2.chip_sw_example_manufacturer.3324504053
Short name T1276
Test name
Test status
Simulation time 3105469470 ps
CPU time 333.99 seconds
Started Jul 29 08:30:52 PM PDT 24
Finished Jul 29 08:36:26 PM PDT 24
Peak memory 609456 kb
Host smart-01ac12b2-4ca2-46b3-a9ce-c154bbd90797
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324504053 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_example_manufacturer.3324504053
Directory /workspace/2.chip_sw_example_manufacturer/latest

Test location /workspace/coverage/default/2.chip_sw_example_rom.1734859078
Short name T412
Test name
Test status
Simulation time 2720986872 ps
CPU time 114.05 seconds
Started Jul 29 08:29:05 PM PDT 24
Finished Jul 29 08:30:59 PM PDT 24
Peak memory 607920 kb
Host smart-b534415c-bb2c-46e0-a8b6-3fd4aa3a61a6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734859078 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_example_rom.1734859078
Directory /workspace/2.chip_sw_example_rom/latest

Test location /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1112730716
Short name T153
Test name
Test status
Simulation time 58669936962 ps
CPU time 9930.45 seconds
Started Jul 29 08:30:18 PM PDT 24
Finished Jul 29 11:15:50 PM PDT 24
Peak memory 624796 kb
Host smart-6c4ed171-08a4-4ad4-833b-2f76efd079a2
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=1112730716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.1112730716
Directory /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest

Test location /workspace/coverage/default/2.chip_sw_flash_crash_alert.3973805284
Short name T458
Test name
Test status
Simulation time 5147402160 ps
CPU time 617.77 seconds
Started Jul 29 08:39:35 PM PDT 24
Finished Jul 29 08:49:53 PM PDT 24
Peak memory 611292 kb
Host smart-f9048e9c-ec64-45a7-9c4b-b63db939c020
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:
new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=3973805284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.3973805284
Directory /workspace/2.chip_sw_flash_crash_alert/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_access.2914265650
Short name T1163
Test name
Test status
Simulation time 5684525246 ps
CPU time 1010.71 seconds
Started Jul 29 08:34:52 PM PDT 24
Finished Jul 29 08:51:43 PM PDT 24
Peak memory 610040 kb
Host smart-2893325e-760d-4519-ac1f-b2122c67958d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914265650 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.chip_sw_flash_ctrl_access.2914265650
Directory /workspace/2.chip_sw_flash_ctrl_access/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3800957022
Short name T1121
Test name
Test status
Simulation time 6303303143 ps
CPU time 938.85 seconds
Started Jul 29 08:34:29 PM PDT 24
Finished Jul 29 08:50:08 PM PDT 24
Peak memory 609860 kb
Host smart-fadaa93f-ae42-4e37-b9e7-280370574c30
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800957022 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.3800957022
Directory /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.272564730
Short name T1147
Test name
Test status
Simulation time 7710652815 ps
CPU time 1076.34 seconds
Started Jul 29 08:37:23 PM PDT 24
Finished Jul 29 08:55:19 PM PDT 24
Peak memory 608876 kb
Host smart-ef491859-f6be-4573-81aa-dbb1e95c8643
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272564730 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.272564730
Directory /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3181018348
Short name T938
Test name
Test status
Simulation time 5236249037 ps
CPU time 1162.65 seconds
Started Jul 29 08:32:21 PM PDT 24
Finished Jul 29 08:51:44 PM PDT 24
Peak memory 610092 kb
Host smart-62cc70ba-4ccf-41a3-9242-c9d1117189e3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181018348 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.3181018348
Directory /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3637457757
Short name T361
Test name
Test status
Simulation time 3833142848 ps
CPU time 406.57 seconds
Started Jul 29 08:32:03 PM PDT 24
Finished Jul 29 08:38:50 PM PDT 24
Peak memory 609776 kb
Host smart-c59c89d0-0ad0-4f93-b913-0a03ede8d119
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637457757 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.3637457757
Directory /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1974961147
Short name T243
Test name
Test status
Simulation time 4651059740 ps
CPU time 566.81 seconds
Started Jul 29 08:33:10 PM PDT 24
Finished Jul 29 08:42:37 PM PDT 24
Peak memory 609936 kb
Host smart-1c621f56-676e-41c0-a19f-e4d6a14b111b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19
74961147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.1974961147
Directory /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.444139423
Short name T1102
Test name
Test status
Simulation time 5561413700 ps
CPU time 1045.43 seconds
Started Jul 29 08:39:00 PM PDT 24
Finished Jul 29 08:56:26 PM PDT 24
Peak memory 610116 kb
Host smart-234205e5-989f-44ef-accf-db0767849f91
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444139423 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.444139423
Directory /workspace/2.chip_sw_flash_ctrl_mem_protection/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2056224327
Short name T363
Test name
Test status
Simulation time 4222270972 ps
CPU time 628.97 seconds
Started Jul 29 08:34:57 PM PDT 24
Finished Jul 29 08:45:26 PM PDT 24
Peak memory 609752 kb
Host smart-39c0173e-7412-47c7-be6c-e36c79fd85c7
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056224327
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.2056224327
Directory /workspace/2.chip_sw_flash_ctrl_ops/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1864060091
Short name T973
Test name
Test status
Simulation time 4540853279 ps
CPU time 752.72 seconds
Started Jul 29 08:34:14 PM PDT 24
Finished Jul 29 08:46:47 PM PDT 24
Peak memory 608964 kb
Host smart-39bbb19b-dd99-43dd-bbb4-dd56ae09c63f
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1864060091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.1864060091
Directory /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.691695098
Short name T344
Test name
Test status
Simulation time 4821006033 ps
CPU time 932.29 seconds
Started Jul 29 08:39:24 PM PDT 24
Finished Jul 29 08:54:56 PM PDT 24
Peak memory 610236 kb
Host smart-6ad35307-0d32-45e6-9775-8eae569547c8
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_
rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=691695098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.691695098
Directory /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.2725873472
Short name T455
Test name
Test status
Simulation time 3096275028 ps
CPU time 442.03 seconds
Started Jul 29 08:39:05 PM PDT 24
Finished Jul 29 08:46:27 PM PDT 24
Peak memory 609804 kb
Host smart-83de504f-0125-4b38-ab3a-b38f27ee1268
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725873
472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.2725873472
Directory /workspace/2.chip_sw_flash_ctrl_write_clear/latest

Test location /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2283331635
Short name T237
Test name
Test status
Simulation time 18380157467 ps
CPU time 1512.35 seconds
Started Jul 29 08:39:26 PM PDT 24
Finished Jul 29 09:04:39 PM PDT 24
Peak memory 613548 kb
Host smart-d854c972-defb-45d3-823c-70ac91c763d6
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2283331635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.2283331635
Directory /workspace/2.chip_sw_flash_init_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3771131709
Short name T989
Test name
Test status
Simulation time 2760518600 ps
CPU time 214.15 seconds
Started Jul 29 08:43:26 PM PDT 24
Finished Jul 29 08:47:01 PM PDT 24
Peak memory 609452 kb
Host smart-7a9f16a3-bea6-4f1d-8122-bc15a1a17250
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket
est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3771131709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.3771131709
Directory /workspace/2.chip_sw_flash_scrambling_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_gpio.3438498021
Short name T28
Test name
Test status
Simulation time 4156308686 ps
CPU time 491.91 seconds
Started Jul 29 08:34:24 PM PDT 24
Finished Jul 29 08:42:36 PM PDT 24
Peak memory 610324 kb
Host smart-c517a8fe-d0d4-4f17-af12-f17dfb2b0bf6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438498021 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.chip_sw_gpio.3438498021
Directory /workspace/2.chip_sw_gpio/latest

Test location /workspace/coverage/default/2.chip_sw_gpio_smoketest.3046961008
Short name T1319
Test name
Test status
Simulation time 2779853114 ps
CPU time 231.34 seconds
Started Jul 29 08:40:10 PM PDT 24
Finished Jul 29 08:44:01 PM PDT 24
Peak memory 610000 kb
Host smart-498a23ed-2c3d-483e-8edc-b1aae5925c0d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046961008 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_sw_gpio_smoketest.3046961008
Directory /workspace/2.chip_sw_gpio_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc.1723254297
Short name T1196
Test name
Test status
Simulation time 3507220220 ps
CPU time 334.05 seconds
Started Jul 29 08:36:29 PM PDT 24
Finished Jul 29 08:42:03 PM PDT 24
Peak memory 609756 kb
Host smart-bec69d02-8e20-40fe-81de-ee836f745fe6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723254297 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_hmac_enc.1723254297
Directory /workspace/2.chip_sw_hmac_enc/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc_idle.2807369314
Short name T1017
Test name
Test status
Simulation time 2897708850 ps
CPU time 363.59 seconds
Started Jul 29 08:35:10 PM PDT 24
Finished Jul 29 08:41:15 PM PDT 24
Peak memory 609596 kb
Host smart-b36dd735-c7bb-4a53-9882-96bd287e05b9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807369314 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_hmac_enc_idle.2807369314
Directory /workspace/2.chip_sw_hmac_enc_idle/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1974292490
Short name T1286
Test name
Test status
Simulation time 3118340715 ps
CPU time 353.64 seconds
Started Jul 29 08:35:23 PM PDT 24
Finished Jul 29 08:41:18 PM PDT 24
Peak memory 609512 kb
Host smart-4848badd-cc99-4e56-a82c-203d0494bb81
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974292490 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.1974292490
Directory /workspace/2.chip_sw_hmac_enc_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.544645309
Short name T111
Test name
Test status
Simulation time 2940422135 ps
CPU time 235.48 seconds
Started Jul 29 08:39:54 PM PDT 24
Finished Jul 29 08:43:49 PM PDT 24
Peak memory 609836 kb
Host smart-bf65e494-f5e7-4bbf-b10f-686a6bfc85a5
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544645309 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.544645309
Directory /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_multistream.620825525
Short name T1009
Test name
Test status
Simulation time 7522343708 ps
CPU time 1493.63 seconds
Started Jul 29 08:35:10 PM PDT 24
Finished Jul 29 09:00:04 PM PDT 24
Peak memory 608856 kb
Host smart-840634ee-951d-4442-8ab8-ab2ee419d02a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620825525 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.chip_sw_hmac_multistream.620825525
Directory /workspace/2.chip_sw_hmac_multistream/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_oneshot.2142462140
Short name T741
Test name
Test status
Simulation time 3293651710 ps
CPU time 368.12 seconds
Started Jul 29 08:37:31 PM PDT 24
Finished Jul 29 08:43:39 PM PDT 24
Peak memory 609656 kb
Host smart-7580ee05-45f7-4b3e-a218-6184bfb69290
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142462140 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_hmac_oneshot.2142462140
Directory /workspace/2.chip_sw_hmac_oneshot/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_smoketest.1053988271
Short name T1189
Test name
Test status
Simulation time 3627164248 ps
CPU time 380.46 seconds
Started Jul 29 08:41:21 PM PDT 24
Finished Jul 29 08:47:41 PM PDT 24
Peak memory 608484 kb
Host smart-94535b97-a7ec-45bc-a7a4-efd3c3002d3d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053988271 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_hmac_smoketest.1053988271
Directory /workspace/2.chip_sw_hmac_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.74544617
Short name T348
Test name
Test status
Simulation time 3392817736 ps
CPU time 479.89 seconds
Started Jul 29 08:32:18 PM PDT 24
Finished Jul 29 08:40:19 PM PDT 24
Peak memory 609772 kb
Host smart-2396b8a3-e5d1-4b96-a1f7-b9d61b6f3f7a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74544617 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.74544617
Directory /workspace/2.chip_sw_i2c_device_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.4098722105
Short name T1204
Test name
Test status
Simulation time 4754198088 ps
CPU time 789.53 seconds
Started Jul 29 08:31:06 PM PDT 24
Finished Jul 29 08:44:16 PM PDT 24
Peak memory 609276 kb
Host smart-ce3883f5-5d24-4583-9390-3b1676fd8e58
User root
Command /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098722105 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.4098722105
Directory /workspace/2.chip_sw_i2c_host_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3243674008
Short name T327
Test name
Test status
Simulation time 5041288232 ps
CPU time 765.57 seconds
Started Jul 29 08:33:22 PM PDT 24
Finished Jul 29 08:46:08 PM PDT 24
Peak memory 610024 kb
Host smart-42460227-5acf-46cc-8702-8d62a663b1e6
User root
Command /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243674008 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.3243674008
Directory /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3457306047
Short name T336
Test name
Test status
Simulation time 5330597816 ps
CPU time 917.19 seconds
Started Jul 29 08:37:57 PM PDT 24
Finished Jul 29 08:53:15 PM PDT 24
Peak memory 609240 kb
Host smart-34697cf8-7bcb-4e2e-b2c3-b0a2b2c736bd
User root
Command /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457306047 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.3457306047
Directory /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest

Test location /workspace/coverage/default/2.chip_sw_inject_scramble_seed.908642625
Short name T1275
Test name
Test status
Simulation time 65200284893 ps
CPU time 10715.6 seconds
Started Jul 29 08:30:31 PM PDT 24
Finished Jul 29 11:29:08 PM PDT 24
Peak memory 624800 kb
Host smart-fce1412e-1b0a-4d6a-8215-95f065233c93
User root
Command /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=908642625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.908642625
Directory /workspace/2.chip_sw_inject_scramble_seed/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2598733153
Short name T1215
Test name
Test status
Simulation time 12212106892 ps
CPU time 2618.67 seconds
Started Jul 29 08:35:35 PM PDT 24
Finished Jul 29 09:19:16 PM PDT 24
Peak memory 618272 kb
Host smart-dcd6c1f4-73d9-4883-977c-225f7f837f74
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598
733153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.2598733153
Directory /workspace/2.chip_sw_keymgr_key_derivation/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.501302880
Short name T1288
Test name
Test status
Simulation time 10787158292 ps
CPU time 1558.92 seconds
Started Jul 29 08:37:22 PM PDT 24
Finished Jul 29 09:03:21 PM PDT 24
Peak memory 616668 kb
Host smart-f50121d9-ac9d-4f2e-a6d3-21e9867c9d03
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=501302880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.501302880
Directory /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3952264166
Short name T230
Test name
Test status
Simulation time 11151929147 ps
CPU time 1585.06 seconds
Started Jul 29 08:40:02 PM PDT 24
Finished Jul 29 09:06:28 PM PDT 24
Peak memory 617936 kb
Host smart-a0ee8e98-caf6-446e-a6fb-d19db9d07a6f
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3952264166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en
_reduced_freq.3952264166
Directory /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.211213376
Short name T1206
Test name
Test status
Simulation time 7402696568 ps
CPU time 1382.15 seconds
Started Jul 29 08:35:19 PM PDT 24
Finished Jul 29 08:58:21 PM PDT 24
Peak memory 617644 kb
Host smart-a1163e2a-b21e-4aef-8f3f-3f0ed11b7b07
User root
Command /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=211213376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.211213376
Directory /workspace/2.chip_sw_keymgr_key_derivation_prod/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.4275417129
Short name T1389
Test name
Test status
Simulation time 8807041272 ps
CPU time 1669.23 seconds
Started Jul 29 08:35:11 PM PDT 24
Finished Jul 29 09:03:01 PM PDT 24
Peak memory 611000 kb
Host smart-0651a850-5a20-4a2e-a682-570464e672bd
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42754
17129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.4275417129
Directory /workspace/2.chip_sw_keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_app_rom.1921756019
Short name T401
Test name
Test status
Simulation time 2704252600 ps
CPU time 244.51 seconds
Started Jul 29 08:36:06 PM PDT 24
Finished Jul 29 08:40:11 PM PDT 24
Peak memory 608340 kb
Host smart-af990b54-3f50-4dd0-893c-3f6ae5fe7810
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921756019 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_kmac_app_rom.1921756019
Directory /workspace/2.chip_sw_kmac_app_rom/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_entropy.3659357698
Short name T1370
Test name
Test status
Simulation time 2894067660 ps
CPU time 303.69 seconds
Started Jul 29 08:32:04 PM PDT 24
Finished Jul 29 08:37:08 PM PDT 24
Peak memory 609644 kb
Host smart-17f7c51a-5592-42db-8c6a-6be5acd1d83f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659357698 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_kmac_entropy.3659357698
Directory /workspace/2.chip_sw_kmac_entropy/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_idle.1411779221
Short name T89
Test name
Test status
Simulation time 3315816760 ps
CPU time 272.51 seconds
Started Jul 29 08:37:33 PM PDT 24
Finished Jul 29 08:42:06 PM PDT 24
Peak memory 609640 kb
Host smart-8bf1eb75-d218-4feb-9403-47289c2acdb0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411779221 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_kmac_idle.1411779221
Directory /workspace/2.chip_sw_kmac_idle/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3372174327
Short name T378
Test name
Test status
Simulation time 3054637910 ps
CPU time 215.71 seconds
Started Jul 29 08:42:45 PM PDT 24
Finished Jul 29 08:46:21 PM PDT 24
Peak memory 609764 kb
Host smart-42aa0a96-bbc4-4355-ae7b-a9816a1aeff3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372174327 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.chip_sw_kmac_mode_cshake.3372174327
Directory /workspace/2.chip_sw_kmac_mode_cshake/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3392455427
Short name T978
Test name
Test status
Simulation time 2486727972 ps
CPU time 375.22 seconds
Started Jul 29 08:35:59 PM PDT 24
Finished Jul 29 08:42:14 PM PDT 24
Peak memory 608556 kb
Host smart-a591c901-2eb6-4ac3-bf6a-e77d479ec4dc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392455427 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_kmac_mode_kmac.3392455427
Directory /workspace/2.chip_sw_kmac_mode_kmac/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3865901933
Short name T1151
Test name
Test status
Simulation time 3234148268 ps
CPU time 381.01 seconds
Started Jul 29 08:34:08 PM PDT 24
Finished Jul 29 08:40:29 PM PDT 24
Peak memory 609740 kb
Host smart-54d86bdc-c142-4522-b6c3-d30293ca776e
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865901933 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.3865901933
Directory /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3577763258
Short name T1229
Test name
Test status
Simulation time 2968766389 ps
CPU time 324.81 seconds
Started Jul 29 08:37:36 PM PDT 24
Finished Jul 29 08:43:01 PM PDT 24
Peak memory 609776 kb
Host smart-f911e4c0-99bf-45bf-9c0e-2d2c237ba834
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35777632
58 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3577763258
Directory /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_smoketest.1280542368
Short name T1092
Test name
Test status
Simulation time 2459256450 ps
CPU time 278.66 seconds
Started Jul 29 08:39:30 PM PDT 24
Finished Jul 29 08:44:10 PM PDT 24
Peak memory 609776 kb
Host smart-34bce5eb-5077-433d-9efd-b0fd9682bb27
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280542368 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_kmac_smoketest.1280542368
Directory /workspace/2.chip_sw_kmac_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1533808696
Short name T1274
Test name
Test status
Simulation time 2830507724 ps
CPU time 226.49 seconds
Started Jul 29 08:33:38 PM PDT 24
Finished Jul 29 08:37:24 PM PDT 24
Peak memory 609420 kb
Host smart-e188e44f-4a71-417b-839e-1de0fa711595
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533808696 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.1533808696
Directory /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.224620179
Short name T176
Test name
Test status
Simulation time 4697549472 ps
CPU time 567.81 seconds
Started Jul 29 08:37:54 PM PDT 24
Finished Jul 29 08:47:23 PM PDT 24
Peak memory 610792 kb
Host smart-3e258360-46da-468d-9566-8a9dc05e5023
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=224620179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.224620179
Directory /workspace/2.chip_sw_lc_ctrl_program_error/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1630837365
Short name T1358
Test name
Test status
Simulation time 3829918971 ps
CPU time 250.5 seconds
Started Jul 29 08:32:34 PM PDT 24
Finished Jul 29 08:36:45 PM PDT 24
Peak memory 621764 kb
Host smart-bc1fd66a-bd52-41c2-8019-9e4af495eac0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16308373
65 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.1630837365
Directory /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.4231895554
Short name T1332
Test name
Test status
Simulation time 6091302508 ps
CPU time 503.02 seconds
Started Jul 29 08:38:02 PM PDT 24
Finished Jul 29 08:46:25 PM PDT 24
Peak memory 620464 kb
Host smart-27df2b45-39eb-4319-bb07-9ecca56755a8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231895554 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.4231895554
Directory /workspace/2.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.4265022262
Short name T171
Test name
Test status
Simulation time 2955088419 ps
CPU time 111.03 seconds
Started Jul 29 08:34:23 PM PDT 24
Finished Jul 29 08:36:14 PM PDT 24
Peak memory 617192 kb
Host smart-c1f18b30-49fa-4e10-8264-f2c6d42e7425
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes
t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4265022262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.4265022262
Directory /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2538327564
Short name T270
Test name
Test status
Simulation time 3014726673 ps
CPU time 106.69 seconds
Started Jul 29 08:31:57 PM PDT 24
Finished Jul 29 08:33:44 PM PDT 24
Peak memory 616952 kb
Host smart-7ad8af92-f68c-494d-b50f-85586d802d12
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s
im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538327564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2538327564
Directory /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1653520699
Short name T246
Test name
Test status
Simulation time 51736991696 ps
CPU time 5414.61 seconds
Started Jul 29 08:36:39 PM PDT 24
Finished Jul 29 10:06:54 PM PDT 24
Peak memory 619360 kb
Host smart-22493d79-4970-468b-8c7e-1086b1eea3b7
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d
evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653520699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi
p_sw_lc_walkthrough_prod.1653520699
Directory /workspace/2.chip_sw_lc_walkthrough_prod/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.333204754
Short name T997
Test name
Test status
Simulation time 9861833131 ps
CPU time 953.05 seconds
Started Jul 29 08:32:00 PM PDT 24
Finished Jul 29 08:47:54 PM PDT 24
Peak memory 619164 kb
Host smart-aaec6858-e4cc-49cb-a75c-cd75f3223bea
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa
lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=333204754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.333204754
Directory /workspace/2.chip_sw_lc_walkthrough_prodend/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2100722478
Short name T1218
Test name
Test status
Simulation time 47565210168 ps
CPU time 5661.42 seconds
Started Jul 29 08:34:14 PM PDT 24
Finished Jul 29 10:08:37 PM PDT 24
Peak memory 620584 kb
Host smart-71cee994-333a-4d50-9994-7f695151c993
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100722478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip
_sw_lc_walkthrough_rma.2100722478
Directory /workspace/2.chip_sw_lc_walkthrough_rma/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2405747964
Short name T1072
Test name
Test status
Simulation time 30616047592 ps
CPU time 2278.88 seconds
Started Jul 29 08:34:50 PM PDT 24
Finished Jul 29 09:12:49 PM PDT 24
Peak memory 620284 kb
Host smart-1bdb7a65-3cd6-4ed0-8c4b-6885ef74947d
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks
_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2405747964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun
locks.2405747964
Directory /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.891158185
Short name T1199
Test name
Test status
Simulation time 17259960280 ps
CPU time 3185.55 seconds
Started Jul 29 08:33:44 PM PDT 24
Finished Jul 29 09:26:50 PM PDT 24
Peak memory 610008 kb
Host smart-4fc9a730-48ad-4563-87cd-ad8a15b202ca
User root
Command /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_
rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=891158185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.891158185
Directory /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1533569168
Short name T995
Test name
Test status
Simulation time 18204085799 ps
CPU time 3692.56 seconds
Started Jul 29 08:34:14 PM PDT 24
Finished Jul 29 09:35:47 PM PDT 24
Peak memory 610332 kb
Host smart-cc5ee0a5-dea6-4359-8c89-1ab26960df50
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne
w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1533569168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1533569168
Directory /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1943360356
Short name T1130
Test name
Test status
Simulation time 24684036949 ps
CPU time 3204.59 seconds
Started Jul 29 08:39:48 PM PDT 24
Finished Jul 29 09:33:13 PM PDT 24
Peak memory 610416 kb
Host smart-55a70b5a-80f6-443c-bebc-c5b6185a34f5
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e
cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943360356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu
ced_freq.1943360356
Directory /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2550947162
Short name T1185
Test name
Test status
Simulation time 3387695010 ps
CPU time 428.67 seconds
Started Jul 29 08:33:59 PM PDT 24
Finished Jul 29 08:41:08 PM PDT 24
Peak memory 609896 kb
Host smart-dc0adc2f-a669-408a-a273-5b3043037299
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn
_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550947162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.2550947162
Directory /workspace/2.chip_sw_otbn_mem_scramble/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_randomness.2336643699
Short name T1067
Test name
Test status
Simulation time 5685347766 ps
CPU time 941.99 seconds
Started Jul 29 08:39:14 PM PDT 24
Finished Jul 29 08:54:56 PM PDT 24
Peak memory 609020 kb
Host smart-070b6ef2-7826-4ca6-99b4-ab4d7bb2b7da
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2336643699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.2336643699
Directory /workspace/2.chip_sw_otbn_randomness/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_smoketest.59430492
Short name T149
Test name
Test status
Simulation time 7244882512 ps
CPU time 1474.29 seconds
Started Jul 29 08:39:41 PM PDT 24
Finished Jul 29 09:04:15 PM PDT 24
Peak memory 610268 kb
Host smart-0350b0af-6a2c-44d6-ae29-801b8ff0bdac
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59430492 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_otbn_smoketest.59430492
Directory /workspace/2.chip_sw_otbn_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3182091015
Short name T1226
Test name
Test status
Simulation time 2792242091 ps
CPU time 218.93 seconds
Started Jul 29 08:32:05 PM PDT 24
Finished Jul 29 08:35:44 PM PDT 24
Peak memory 609788 kb
Host smart-2bb3888c-190f-4b02-ab0d-4c28dc36f3e3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182091015 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.3182091015
Directory /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.4168335735
Short name T1152
Test name
Test status
Simulation time 7387271790 ps
CPU time 1347.6 seconds
Started Jul 29 08:34:26 PM PDT 24
Finished Jul 29 08:56:54 PM PDT 24
Peak memory 610684 kb
Host smart-cd0589a0-3fcc-4f13-8294-fff2463a31e4
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=4168335735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.4168335735
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2213829211
Short name T1219
Test name
Test status
Simulation time 8176008164 ps
CPU time 1315.43 seconds
Started Jul 29 08:32:40 PM PDT 24
Finished Jul 29 08:54:35 PM PDT 24
Peak memory 610748 kb
Host smart-dcec2284-38ea-444a-ad8b-a7e600634eff
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2213829211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.2213829211
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3887945193
Short name T229
Test name
Test status
Simulation time 9033893560 ps
CPU time 1170.61 seconds
Started Jul 29 08:31:51 PM PDT 24
Finished Jul 29 08:51:23 PM PDT 24
Peak memory 610460 kb
Host smart-b737dd7f-7449-4ce9-aa65-0d54da1ce26d
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3887945193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.3887945193
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1010472438
Short name T1367
Test name
Test status
Simulation time 4244372972 ps
CPU time 693.81 seconds
Started Jul 29 08:33:45 PM PDT 24
Finished Jul 29 08:45:19 PM PDT 24
Peak memory 609580 kb
Host smart-8eeb697b-1050-4d04-8546-fb2007bbb202
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=1010472438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1010472438
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3524991459
Short name T1261
Test name
Test status
Simulation time 2813788900 ps
CPU time 247.36 seconds
Started Jul 29 08:40:55 PM PDT 24
Finished Jul 29 08:45:03 PM PDT 24
Peak memory 609576 kb
Host smart-2148cd73-90ee-42c7-b077-b63df29fd31d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524991459 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_otp_ctrl_smoketest.3524991459
Directory /workspace/2.chip_sw_otp_ctrl_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_pattgen_ios.468697515
Short name T220
Test name
Test status
Simulation time 2698706360 ps
CPU time 206.75 seconds
Started Jul 29 08:31:24 PM PDT 24
Finished Jul 29 08:34:51 PM PDT 24
Peak memory 612352 kb
Host smart-57677cc7-0bd8-4b84-9304-75601a91a9f7
User root
Command /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468697515 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.468697515
Directory /workspace/2.chip_sw_pattgen_ios/latest

Test location /workspace/coverage/default/2.chip_sw_plic_sw_irq.1088269408
Short name T258
Test name
Test status
Simulation time 3808244090 ps
CPU time 379.72 seconds
Started Jul 29 08:37:39 PM PDT 24
Finished Jul 29 08:43:59 PM PDT 24
Peak memory 609640 kb
Host smart-9b2a5bd4-a34c-4d74-9c95-6a172b3967bd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088269408 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.chip_sw_plic_sw_irq.1088269408
Directory /workspace/2.chip_sw_plic_sw_irq/latest

Test location /workspace/coverage/default/2.chip_sw_power_idle_load.3816658504
Short name T143
Test name
Test status
Simulation time 4212078104 ps
CPU time 443.63 seconds
Started Jul 29 08:40:05 PM PDT 24
Finished Jul 29 08:47:29 PM PDT 24
Peak memory 609348 kb
Host smart-ee9b559c-0eb9-40c8-b525-71ae071f7839
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816658504 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.3816658504
Directory /workspace/2.chip_sw_power_idle_load/latest

Test location /workspace/coverage/default/2.chip_sw_power_sleep_load.3389471299
Short name T1128
Test name
Test status
Simulation time 11351484840 ps
CPU time 477.67 seconds
Started Jul 29 08:40:31 PM PDT 24
Finished Jul 29 08:48:29 PM PDT 24
Peak memory 610912 kb
Host smart-2eab9e07-6277-4392-af9c-46b2a8736107
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389471299 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.3389471299
Directory /workspace/2.chip_sw_power_sleep_load/latest

Test location /workspace/coverage/default/2.chip_sw_power_virus.4059853124
Short name T206
Test name
Test status
Simulation time 5505548574 ps
CPU time 1233.14 seconds
Started Jul 29 08:41:47 PM PDT 24
Finished Jul 29 09:02:21 PM PDT 24
Peak memory 625056 kb
Host smart-4a2300c5-5910-4bf6-988a-a9da97d1cc0e
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_
power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes
t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4059853124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.4059853124
Directory /workspace/2.chip_sw_power_virus/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.464694629
Short name T1314
Test name
Test status
Simulation time 13677824650 ps
CPU time 2086.05 seconds
Started Jul 29 08:35:17 PM PDT 24
Finished Jul 29 09:10:03 PM PDT 24
Peak memory 611516 kb
Host smart-c5fc840b-d609-4f23-8a15-a1372361ce25
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4646
94629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.464694629
Directory /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.4160786059
Short name T974
Test name
Test status
Simulation time 19748038518 ps
CPU time 1841.3 seconds
Started Jul 29 08:36:46 PM PDT 24
Finished Jul 29 09:07:28 PM PDT 24
Peak memory 610556 kb
Host smart-02f9e9a6-0d33-4304-916a-3405bc40ff56
User root
Command /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416
0786059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.4160786059
Directory /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3584115310
Short name T934
Test name
Test status
Simulation time 15593872820 ps
CPU time 1441.61 seconds
Started Jul 29 08:34:13 PM PDT 24
Finished Jul 29 08:58:14 PM PDT 24
Peak memory 611504 kb
Host smart-de325809-10e5-46ac-9086-c0c9730ef9c8
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3584115310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3584115310
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3837925621
Short name T411
Test name
Test status
Simulation time 20355487064 ps
CPU time 1514.16 seconds
Started Jul 29 08:36:35 PM PDT 24
Finished Jul 29 09:01:50 PM PDT 24
Peak memory 610860 kb
Host smart-35679d7c-2768-4434-9fbc-fdbae6fc8720
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3837925621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3837925621
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2169320856
Short name T956
Test name
Test status
Simulation time 9305147562 ps
CPU time 912.18 seconds
Started Jul 29 08:33:01 PM PDT 24
Finished Jul 29 08:48:14 PM PDT 24
Peak memory 610564 kb
Host smart-c8328d7d-20eb-4e12-95b0-61202176a073
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169320856 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.2169320856
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.900353888
Short name T943
Test name
Test status
Simulation time 7765621640 ps
CPU time 531.79 seconds
Started Jul 29 08:34:04 PM PDT 24
Finished Jul 29 08:42:56 PM PDT 24
Peak memory 617664 kb
Host smart-1c983f95-d57a-4135-85ac-db9c927306fd
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=900353888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.900353888
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.211677347
Short name T1352
Test name
Test status
Simulation time 6714399048 ps
CPU time 461.77 seconds
Started Jul 29 08:34:13 PM PDT 24
Finished Jul 29 08:41:55 PM PDT 24
Peak memory 610808 kb
Host smart-125b07c9-ee2f-44b9-b9d3-fcfedb6d4925
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211677347 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.211677347
Directory /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2006873462
Short name T341
Test name
Test status
Simulation time 3485855332 ps
CPU time 491.82 seconds
Started Jul 29 08:38:25 PM PDT 24
Finished Jul 29 08:46:37 PM PDT 24
Peak memory 609668 kb
Host smart-1caf9747-ebf0-4246-9fb2-efeea96312e9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006873462 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.2006873462
Directory /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1995296870
Short name T1082
Test name
Test status
Simulation time 4773174298 ps
CPU time 544.49 seconds
Started Jul 29 08:35:01 PM PDT 24
Finished Jul 29 08:44:06 PM PDT 24
Peak memory 616356 kb
Host smart-85fe27fd-bcfc-4132-b374-134fc4b10da4
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1995296870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.1995296870
Directory /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4193533727
Short name T318
Test name
Test status
Simulation time 11194115933 ps
CPU time 1274.27 seconds
Started Jul 29 08:34:42 PM PDT 24
Finished Jul 29 08:55:57 PM PDT 24
Peak memory 611472 kb
Host smart-0272144e-ab62-4576-a180-be6eb2f97ce1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193533727 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4193533727
Directory /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2515676028
Short name T59
Test name
Test status
Simulation time 7317137992 ps
CPU time 447.54 seconds
Started Jul 29 08:39:14 PM PDT 24
Finished Jul 29 08:46:42 PM PDT 24
Peak memory 609692 kb
Host smart-191c3598-b828-4f9b-ae99-eefa6832e61b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515676028 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2515676028
Directory /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1630895757
Short name T1113
Test name
Test status
Simulation time 7542903665 ps
CPU time 889.26 seconds
Started Jul 29 08:33:58 PM PDT 24
Finished Jul 29 08:48:48 PM PDT 24
Peak memory 610868 kb
Host smart-4073bfb7-b169-4e97-a04e-f000484af9d0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630895757 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.1630895757
Directory /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1657767790
Short name T113
Test name
Test status
Simulation time 23684628392 ps
CPU time 1303.26 seconds
Started Jul 29 08:38:47 PM PDT 24
Finished Jul 29 09:00:31 PM PDT 24
Peak memory 611000 kb
Host smart-49ba0ab0-9164-4afa-85b6-dee815696311
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1657767790 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1657767790
Directory /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2026854478
Short name T947
Test name
Test status
Simulation time 32525792396 ps
CPU time 3359.53 seconds
Started Jul 29 08:34:19 PM PDT 24
Finished Jul 29 09:30:19 PM PDT 24
Peak memory 612004 kb
Host smart-8084dc5c-1540-4327-8c4b-2557a4d1711c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power
_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026854478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit
ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s
leep_power_glitch_reset.2026854478
Directory /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.470969605
Short name T1237
Test name
Test status
Simulation time 3589740184 ps
CPU time 306.76 seconds
Started Jul 29 08:38:15 PM PDT 24
Finished Jul 29 08:43:22 PM PDT 24
Peak memory 609700 kb
Host smart-36cc8d58-3503-4e73-ab5e-b7dcad812cd9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470969605 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.470969605
Directory /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.395135689
Short name T447
Test name
Test status
Simulation time 4759661112 ps
CPU time 584.18 seconds
Started Jul 29 08:33:14 PM PDT 24
Finished Jul 29 08:42:59 PM PDT 24
Peak memory 616256 kb
Host smart-73efd823-b696-4f62-9e12-7b33b8fd5add
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=395135689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.395135689
Directory /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2819012183
Short name T129
Test name
Test status
Simulation time 5604151600 ps
CPU time 499.02 seconds
Started Jul 29 08:35:21 PM PDT 24
Finished Jul 29 08:43:42 PM PDT 24
Peak memory 609956 kb
Host smart-9241e218-b27b-417b-978a-4b3d6aaeb4bf
User root
Command /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28190121
83 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2819012183
Directory /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3557103373
Short name T1375
Test name
Test status
Simulation time 5915998462 ps
CPU time 531.75 seconds
Started Jul 29 08:37:21 PM PDT 24
Finished Jul 29 08:46:13 PM PDT 24
Peak memory 610752 kb
Host smart-e135160a-bd9c-4b6c-9e0f-d6f039f2fbd7
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3557103373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.3557103373
Directory /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.728009298
Short name T953
Test name
Test status
Simulation time 6176714064 ps
CPU time 461.81 seconds
Started Jul 29 08:40:25 PM PDT 24
Finished Jul 29 08:48:07 PM PDT 24
Peak memory 610512 kb
Host smart-55e6e542-b776-436b-94d1-e490cb0a1c21
User root
Command /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728009298 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.728009298
Directory /workspace/2.chip_sw_pwrmgr_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2873448369
Short name T1050
Test name
Test status
Simulation time 7296085433 ps
CPU time 1082.19 seconds
Started Jul 29 08:33:26 PM PDT 24
Finished Jul 29 08:51:29 PM PDT 24
Peak memory 610520 kb
Host smart-a248eff0-82ca-4907-833b-4d65c1d6f8cb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873448369 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.2873448369
Directory /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1588092430
Short name T1077
Test name
Test status
Simulation time 3954437864 ps
CPU time 554.4 seconds
Started Jul 29 08:32:27 PM PDT 24
Finished Jul 29 08:41:42 PM PDT 24
Peak memory 610084 kb
Host smart-b02a3812-ecb8-44e9-9f36-a09066f49478
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588092430 -assert no
postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1588092430
Directory /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2875328538
Short name T1231
Test name
Test status
Simulation time 6507539568 ps
CPU time 462.3 seconds
Started Jul 29 08:40:40 PM PDT 24
Finished Jul 29 08:48:23 PM PDT 24
Peak memory 610156 kb
Host smart-bff20c8f-2b80-4e98-b5f3-4db1c153378b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875328538 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.2875328538
Directory /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2575122524
Short name T950
Test name
Test status
Simulation time 3561000548 ps
CPU time 482.92 seconds
Started Jul 29 08:35:39 PM PDT 24
Finished Jul 29 08:43:42 PM PDT 24
Peak memory 610116 kb
Host smart-08fcf9e4-e347-4483-b781-0815ca22128b
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257
5122524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.2575122524
Directory /workspace/2.chip_sw_pwrmgr_wdog_reset/latest

Test location /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1897961546
Short name T402
Test name
Test status
Simulation time 8592797028 ps
CPU time 656.29 seconds
Started Jul 29 08:36:53 PM PDT 24
Finished Jul 29 08:47:50 PM PDT 24
Peak memory 624820 kb
Host smart-d47060ac-74c0-4044-a180-fbb3899be085
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897961546 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.1897961546
Directory /workspace/2.chip_sw_rom_ctrl_integrity_check/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.935686419
Short name T251
Test name
Test status
Simulation time 6940666532 ps
CPU time 860.67 seconds
Started Jul 29 08:38:12 PM PDT 24
Finished Jul 29 08:52:33 PM PDT 24
Peak memory 609204 kb
Host smart-98c844b3-4441-4034-ad82-881420c761b7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935686419 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_rstmgr_cpu_info.935686419
Directory /workspace/2.chip_sw_rstmgr_cpu_info/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2213348691
Short name T350
Test name
Test status
Simulation time 4702788586 ps
CPU time 597.05 seconds
Started Jul 29 08:31:08 PM PDT 24
Finished Jul 29 08:41:06 PM PDT 24
Peak memory 641408 kb
Host smart-62b783ef-09ef-48c8-9244-33f31fb76599
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2213348691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.2213348691
Directory /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1735597388
Short name T1095
Test name
Test status
Simulation time 2496179618 ps
CPU time 234.88 seconds
Started Jul 29 08:40:32 PM PDT 24
Finished Jul 29 08:44:27 PM PDT 24
Peak memory 609656 kb
Host smart-f0242264-ee5a-48ee-93ea-17d6129ee987
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735597388 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.chip_sw_rstmgr_smoketest.1735597388
Directory /workspace/2.chip_sw_rstmgr_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1331040829
Short name T1272
Test name
Test status
Simulation time 3646768892 ps
CPU time 492.05 seconds
Started Jul 29 08:32:13 PM PDT 24
Finished Jul 29 08:40:26 PM PDT 24
Peak memory 610024 kb
Host smart-3ac5bb91-9899-4868-9885-087acfe4ba66
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331040829 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_rstmgr_sw_req.1331040829
Directory /workspace/2.chip_sw_rstmgr_sw_req/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1999067165
Short name T1177
Test name
Test status
Simulation time 2118690436 ps
CPU time 202.75 seconds
Started Jul 29 08:36:40 PM PDT 24
Finished Jul 29 08:40:04 PM PDT 24
Peak memory 609612 kb
Host smart-060e7803-7c01-4228-ac8f-1886f942bdce
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999067165 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.1999067165
Directory /workspace/2.chip_sw_rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3433312678
Short name T188
Test name
Test status
Simulation time 3256816996 ps
CPU time 284.42 seconds
Started Jul 29 08:38:45 PM PDT 24
Finished Jul 29 08:43:30 PM PDT 24
Peak memory 610044 kb
Host smart-2d841422-ff79-490b-8e86-fc80c1ffe860
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433312678 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.3433312678
Directory /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.317803180
Short name T533
Test name
Test status
Simulation time 4855308848 ps
CPU time 751.2 seconds
Started Jul 29 08:39:51 PM PDT 24
Finished Jul 29 08:52:23 PM PDT 24
Peak memory 610292 kb
Host smart-3f2d7704-cf9a-4b4a-b9be-c97f9c773237
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31780
3180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.317803180
Directory /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.212436987
Short name T1013
Test name
Test status
Simulation time 5816368280 ps
CPU time 1021.44 seconds
Started Jul 29 08:38:34 PM PDT 24
Finished Jul 29 08:55:36 PM PDT 24
Peak memory 610176 kb
Host smart-f5d4dc35-215b-43c5-93d3-67ea006ba1e2
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=212436987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.212436987
Directory /workspace/2.chip_sw_rv_core_ibex_rnd/latest

Test location /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1001569642
Short name T226
Test name
Test status
Simulation time 4962487162 ps
CPU time 485.48 seconds
Started Jul 29 08:37:42 PM PDT 24
Finished Jul 29 08:45:48 PM PDT 24
Peak memory 624460 kb
Host smart-40f744e1-bc6d-4f03-a364-d715f243f0f8
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001569642 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.1001569642
Directory /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3551569878
Short name T1281
Test name
Test status
Simulation time 6277275980 ps
CPU time 372.66 seconds
Started Jul 29 08:36:53 PM PDT 24
Finished Jul 29 08:43:06 PM PDT 24
Peak memory 621496 kb
Host smart-3eec4d76-0a47-43b8-ad00-6a906dda27c0
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551569878 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.3551569878
Directory /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1132066228
Short name T306
Test name
Test status
Simulation time 3987431166 ps
CPU time 420.2 seconds
Started Jul 29 08:39:10 PM PDT 24
Finished Jul 29 08:46:10 PM PDT 24
Peak memory 621348 kb
Host smart-aa2d16a3-3a1f-428e-b725-881b9294125a
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113206
6228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1132066228
Directory /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.4248814848
Short name T1293
Test name
Test status
Simulation time 3473566372 ps
CPU time 301.41 seconds
Started Jul 29 08:39:55 PM PDT 24
Finished Jul 29 08:44:57 PM PDT 24
Peak memory 609520 kb
Host smart-27774a49-a716-4157-ba2f-7694660c8220
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248814848 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_rv_plic_smoketest.4248814848
Directory /workspace/2.chip_sw_rv_plic_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_rv_timer_irq.145916506
Short name T260
Test name
Test status
Simulation time 2490729172 ps
CPU time 266.55 seconds
Started Jul 29 08:35:56 PM PDT 24
Finished Jul 29 08:40:23 PM PDT 24
Peak memory 609652 kb
Host smart-79f4d891-cc69-44ac-9286-c04c957781d3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145916506 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_rv_timer_irq.145916506
Directory /workspace/2.chip_sw_rv_timer_irq/latest

Test location /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3351711863
Short name T1126
Test name
Test status
Simulation time 2576630056 ps
CPU time 211.12 seconds
Started Jul 29 08:40:54 PM PDT 24
Finished Jul 29 08:44:25 PM PDT 24
Peak memory 608436 kb
Host smart-b8f6a20d-c038-4bbb-9311-ea046f7dff05
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351711863 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_rv_timer_smoketest.3351711863
Directory /workspace/2.chip_sw_rv_timer_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2451084358
Short name T1180
Test name
Test status
Simulation time 3371263811 ps
CPU time 321.51 seconds
Started Jul 29 08:36:30 PM PDT 24
Finished Jul 29 08:41:52 PM PDT 24
Peak memory 610776 kb
Host smart-84365e46-5aae-4bcd-9e13-a02bf558a4d8
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451084
358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.2451084358
Directory /workspace/2.chip_sw_sensor_ctrl_status/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pin_retention.552381266
Short name T54
Test name
Test status
Simulation time 4368843780 ps
CPU time 330.08 seconds
Started Jul 29 08:30:53 PM PDT 24
Finished Jul 29 08:36:23 PM PDT 24
Peak memory 609136 kb
Host smart-2f2699ff-76c7-4ab3-bc92-40742dec9721
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552381266 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.552381266
Directory /workspace/2.chip_sw_sleep_pin_retention/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1494679196
Short name T1081
Test name
Test status
Simulation time 9161712314 ps
CPU time 1318.94 seconds
Started Jul 29 08:32:58 PM PDT 24
Finished Jul 29 08:54:57 PM PDT 24
Peak memory 609552 kb
Host smart-369a3f72-642e-4593-8cc1-b685b428b9eb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494679196 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.1494679196
Directory /workspace/2.chip_sw_sleep_pwm_pulses/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3151002374
Short name T1384
Test name
Test status
Simulation time 8313062194 ps
CPU time 653.14 seconds
Started Jul 29 08:36:35 PM PDT 24
Finished Jul 29 08:47:28 PM PDT 24
Peak memory 610292 kb
Host smart-89e15c73-c5bd-4f17-893f-5e632c30d5f5
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151002374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl
eep_sram_ret_contents_no_scramble.3151002374
Directory /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2794021885
Short name T184
Test name
Test status
Simulation time 8860246824 ps
CPU time 821.77 seconds
Started Jul 29 08:38:19 PM PDT 24
Finished Jul 29 08:52:01 PM PDT 24
Peak memory 610628 kb
Host smart-1424e886-f88b-41d9-87d0-6f8b7136330c
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794021885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep
_sram_ret_contents_scramble.2794021885
Directory /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_pass_through.2946428122
Short name T13
Test name
Test status
Simulation time 6351337190 ps
CPU time 529.97 seconds
Started Jul 29 08:31:02 PM PDT 24
Finished Jul 29 08:39:52 PM PDT 24
Peak memory 624812 kb
Host smart-0445b33b-7e66-4721-bf00-f6ca75958158
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946428122 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.2946428122
Directory /workspace/2.chip_sw_spi_device_pass_through/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1392616855
Short name T207
Test name
Test status
Simulation time 4778696764 ps
CPU time 502.11 seconds
Started Jul 29 08:32:40 PM PDT 24
Finished Jul 29 08:41:02 PM PDT 24
Peak memory 624728 kb
Host smart-b6cd9d79-aeee-4fde-a408-fff752cb24cb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392616855 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.1392616855
Directory /workspace/2.chip_sw_spi_device_pass_through_collision/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2595664343
Short name T57
Test name
Test status
Simulation time 2997142230 ps
CPU time 246.34 seconds
Started Jul 29 08:34:55 PM PDT 24
Finished Jul 29 08:39:02 PM PDT 24
Peak memory 618572 kb
Host smart-4270da73-9ea0-4355-b887-cdaf28a4907a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595664343 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.2595664343
Directory /workspace/2.chip_sw_spi_device_pinmux_sleep_retention/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_tpm.1854910040
Short name T39
Test name
Test status
Simulation time 2888483198 ps
CPU time 353.74 seconds
Started Jul 29 08:34:04 PM PDT 24
Finished Jul 29 08:39:58 PM PDT 24
Peak memory 617828 kb
Host smart-d82d9764-0946-498a-8f71-e61378655e7e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854910040 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.1854910040
Directory /workspace/2.chip_sw_spi_device_tpm/latest

Test location /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.105694134
Short name T34
Test name
Test status
Simulation time 2712710450 ps
CPU time 307.1 seconds
Started Jul 29 08:33:29 PM PDT 24
Finished Jul 29 08:38:37 PM PDT 24
Peak memory 610160 kb
Host smart-ba591a8f-d747-4775-9b4d-3e2ecc579ba9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105694134 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.105694134
Directory /workspace/2.chip_sw_spi_host_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3893462501
Short name T186
Test name
Test status
Simulation time 8183295879 ps
CPU time 788.59 seconds
Started Jul 29 08:38:42 PM PDT 24
Finished Jul 29 08:51:51 PM PDT 24
Peak memory 610456 kb
Host smart-13e411e8-7c11-40a4-8581-17aed051a4ee
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893462501 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.3893462501
Directory /workspace/2.chip_sw_sram_ctrl_execution_main/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3757030480
Short name T289
Test name
Test status
Simulation time 4679396484 ps
CPU time 632.71 seconds
Started Jul 29 08:35:46 PM PDT 24
Finished Jul 29 08:46:19 PM PDT 24
Peak memory 610872 kb
Host smart-4218023e-7dc4-48ff-8800-77d1bb5d502c
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757030480 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr
l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw
_sram_ctrl_scrambled_access.3757030480
Directory /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1198013741
Short name T290
Test name
Test status
Simulation time 4804673557 ps
CPU time 555.28 seconds
Started Jul 29 08:42:43 PM PDT 24
Finished Jul 29 08:51:59 PM PDT 24
Peak memory 610972 kb
Host smart-676dce96-9621-4ae5-ac4e-e0aed2747abd
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s
w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198013741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1198013741
Directory /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1719774973
Short name T185
Test name
Test status
Simulation time 5353955618 ps
CPU time 596.23 seconds
Started Jul 29 08:39:40 PM PDT 24
Finished Jul 29 08:49:36 PM PDT 24
Peak memory 611120 kb
Host smart-9305318f-be0b-4d7d-b4fd-bba3ccc41dd5
User root
Command /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk
_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719774973 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1719774973
Directory /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3239123733
Short name T1349
Test name
Test status
Simulation time 2831226840 ps
CPU time 266.25 seconds
Started Jul 29 08:42:20 PM PDT 24
Finished Jul 29 08:46:47 PM PDT 24
Peak memory 609532 kb
Host smart-b304e755-b6a1-495d-ac1c-04bfda6d28f7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239123733 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.3239123733
Directory /workspace/2.chip_sw_sram_ctrl_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.519603701
Short name T22
Test name
Test status
Simulation time 20414937241 ps
CPU time 2697.68 seconds
Started Jul 29 08:36:04 PM PDT 24
Finished Jul 29 09:21:03 PM PDT 24
Peak memory 610836 kb
Host smart-e6578860-a020-420e-a429-c7f4242a2ab1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519603701 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.519603701
Directory /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3694292605
Short name T1216
Test name
Test status
Simulation time 4476482823 ps
CPU time 575.27 seconds
Started Jul 29 08:32:46 PM PDT 24
Finished Jul 29 08:42:23 PM PDT 24
Peak memory 613752 kb
Host smart-c850dad2-3a8a-49fe-aaca-3f7604234888
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694292605 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.3694292605
Directory /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.4123959128
Short name T209
Test name
Test status
Simulation time 3399451186 ps
CPU time 419.56 seconds
Started Jul 29 08:35:52 PM PDT 24
Finished Jul 29 08:42:52 PM PDT 24
Peak memory 613396 kb
Host smart-fb2049b9-0d56-49bd-8a21-b395d638be1c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123959128 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.4123959128
Directory /workspace/2.chip_sw_sysrst_ctrl_inputs/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3934271840
Short name T222
Test name
Test status
Simulation time 3231139352 ps
CPU time 407.44 seconds
Started Jul 29 08:36:27 PM PDT 24
Finished Jul 29 08:43:15 PM PDT 24
Peak memory 609320 kb
Host smart-00bf6e1f-6bd9-47e2-bcd0-7a7b387a83be
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934271840 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.3934271840
Directory /workspace/2.chip_sw_sysrst_ctrl_outputs/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.360749305
Short name T1380
Test name
Test status
Simulation time 22172516088 ps
CPU time 1400.71 seconds
Started Jul 29 08:34:06 PM PDT 24
Finished Jul 29 08:57:27 PM PDT 24
Peak memory 614564 kb
Host smart-fd4fb320-a8e3-4441-b79d-24090c3323d5
User root
Command /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36074930
5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.360749305
Directory /workspace/2.chip_sw_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3752252286
Short name T36
Test name
Test status
Simulation time 5822407004 ps
CPU time 518.42 seconds
Started Jul 29 08:35:17 PM PDT 24
Finished Jul 29 08:43:55 PM PDT 24
Peak memory 610852 kb
Host smart-e01c9e96-5828-45ac-80ec-3c40a5d885e7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752252286 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3752252286
Directory /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3082273164
Short name T952
Test name
Test status
Simulation time 8599239336 ps
CPU time 1715.59 seconds
Started Jul 29 08:32:34 PM PDT 24
Finished Jul 29 09:01:10 PM PDT 24
Peak memory 623412 kb
Host smart-9733ec37-c0a0-42cc-aaa5-9dea476ad51b
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3082273164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.3082273164
Directory /workspace/2.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/2.chip_sw_uart_smoketest.2884828798
Short name T1004
Test name
Test status
Simulation time 3672722878 ps
CPU time 384.46 seconds
Started Jul 29 08:43:14 PM PDT 24
Finished Jul 29 08:49:39 PM PDT 24
Peak memory 614864 kb
Host smart-6af4849b-47ff-4cd6-813b-2beee7a408c8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884828798 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_sw_uart_smoketest.2884828798
Directory /workspace/2.chip_sw_uart_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx.3225963422
Short name T1279
Test name
Test status
Simulation time 3973717820 ps
CPU time 590.29 seconds
Started Jul 29 08:33:00 PM PDT 24
Finished Jul 29 08:42:51 PM PDT 24
Peak memory 623876 kb
Host smart-23e5ee67-92a6-402d-9445-77e6118f8641
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225963422 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.3225963422
Directory /workspace/2.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1819300011
Short name T425
Test name
Test status
Simulation time 8178739033 ps
CPU time 1660.85 seconds
Started Jul 29 08:34:11 PM PDT 24
Finished Jul 29 09:01:53 PM PDT 24
Peak memory 623564 kb
Host smart-ed7c5788-ccec-4c79-a2c3-420f30c2c1ae
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819300011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx
_alt_clk_freq.1819300011
Directory /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.671937902
Short name T15
Test name
Test status
Simulation time 3916066160 ps
CPU time 448.31 seconds
Started Jul 29 08:32:53 PM PDT 24
Finished Jul 29 08:40:23 PM PDT 24
Peak memory 622304 kb
Host smart-14952639-44b6-435b-94be-fb98c4ee1103
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671937902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba
udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_
alt_clk_freq_low_speed.671937902
Directory /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.708511704
Short name T1097
Test name
Test status
Simulation time 4720712916 ps
CPU time 455.88 seconds
Started Jul 29 08:31:11 PM PDT 24
Finished Jul 29 08:38:47 PM PDT 24
Peak memory 623932 kb
Host smart-5c054a6e-2716-4493-8702-a1e589e1b209
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708511704 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.708511704
Directory /workspace/2.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2727940240
Short name T1244
Test name
Test status
Simulation time 4301539384 ps
CPU time 591.28 seconds
Started Jul 29 08:31:14 PM PDT 24
Finished Jul 29 08:41:06 PM PDT 24
Peak memory 624148 kb
Host smart-e60a5c0d-ad14-4121-8f66-ea911ad13e6b
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727940240 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.2727940240
Directory /workspace/2.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2474054364
Short name T446
Test name
Test status
Simulation time 4699785700 ps
CPU time 753.69 seconds
Started Jul 29 08:31:54 PM PDT 24
Finished Jul 29 08:44:29 PM PDT 24
Peak memory 624172 kb
Host smart-13a18d13-032a-4d58-a98d-66322dd8d19d
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474054364 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.2474054364
Directory /workspace/2.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/2.chip_tap_straps_dev.2742152196
Short name T719
Test name
Test status
Simulation time 16169435034 ps
CPU time 1831.54 seconds
Started Jul 29 08:38:07 PM PDT 24
Finished Jul 29 09:08:40 PM PDT 24
Peak memory 624528 kb
Host smart-f2542bd5-56d9-47cf-8780-e2df52c5f298
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2742152196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.2742152196
Directory /workspace/2.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/2.chip_tap_straps_prod.3738691364
Short name T1065
Test name
Test status
Simulation time 7950270952 ps
CPU time 814.15 seconds
Started Jul 29 08:39:01 PM PDT 24
Finished Jul 29 08:52:36 PM PDT 24
Peak memory 632732 kb
Host smart-6469e6fb-eff9-4b63-823b-b71d0076e413
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3738691364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.3738691364
Directory /workspace/2.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/2.chip_tap_straps_testunlock0.3565598547
Short name T1255
Test name
Test status
Simulation time 2469901674 ps
CPU time 150.66 seconds
Started Jul 29 08:40:15 PM PDT 24
Finished Jul 29 08:42:46 PM PDT 24
Peak memory 623908 kb
Host smart-1b9cd29c-01e5-4880-8891-fd95a96c35dc
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565598547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.3565598547
Directory /workspace/2.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_dev.1451203356
Short name T1159
Test name
Test status
Simulation time 16301011666 ps
CPU time 3587.37 seconds
Started Jul 29 08:46:02 PM PDT 24
Finished Jul 29 09:45:51 PM PDT 24
Peak memory 610140 kb
Host smart-ace10b06-052c-458b-a71c-47312d6caf17
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451203356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rom_e2e_asm_init_dev.1451203356
Directory /workspace/2.rom_e2e_asm_init_dev/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_prod.1285980295
Short name T1202
Test name
Test status
Simulation time 15832386287 ps
CPU time 3198.25 seconds
Started Jul 29 08:43:33 PM PDT 24
Finished Jul 29 09:36:52 PM PDT 24
Peak memory 610224 kb
Host smart-338e8cb3-e24b-4740-ac33-79a018fd9528
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285980295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_
SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rom_e2e_asm_init_prod.1285980295
Directory /workspace/2.rom_e2e_asm_init_prod/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3730268761
Short name T984
Test name
Test status
Simulation time 14775478568 ps
CPU time 3410.57 seconds
Started Jul 29 08:44:36 PM PDT 24
Finished Jul 29 09:41:27 PM PDT 24
Peak memory 610508 kb
Host smart-832b62a4-82d7-4bdd-87bf-5087e1bd8ca1
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730268761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_e2e_asm_init_prod_end.3730268761
Directory /workspace/2.rom_e2e_asm_init_prod_end/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_rma.677621060
Short name T189
Test name
Test status
Simulation time 14938961540 ps
CPU time 3171.3 seconds
Started Jul 29 08:44:12 PM PDT 24
Finished Jul 29 09:37:04 PM PDT 24
Peak memory 610068 kb
Host smart-486b344d-78fd-4955-b962-4fff22a88d2b
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677621060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rom_e2e_asm_init_rma.677621060
Directory /workspace/2.rom_e2e_asm_init_rma/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2465062012
Short name T939
Test name
Test status
Simulation time 11007200085 ps
CPU time 2689.25 seconds
Started Jul 29 08:44:34 PM PDT 24
Finished Jul 29 09:29:24 PM PDT 24
Peak memory 610544 kb
Host smart-d8d499de-f57c-41d8-b3fd-c68037c4aef1
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465062012 -assert nopostproc +UVM_TESTNAME=chip_base_te
st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.rom_e2e_asm_init_test_unlocked0.2465062012
Directory /workspace/2.rom_e2e_asm_init_test_unlocked0/latest

Test location /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.862104399
Short name T914
Test name
Test status
Simulation time 15271445752 ps
CPU time 3867.34 seconds
Started Jul 29 08:44:41 PM PDT 24
Finished Jul 29 09:49:09 PM PDT 24
Peak memory 610096 kb
Host smart-6a0fff96-164d-405c-a076-f4ea930960ff
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid
_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862104399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_ini
t_rom_ext_invalid_meas.862104399
Directory /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2896126715
Short name T1262
Test name
Test status
Simulation time 15238922926 ps
CPU time 3157.01 seconds
Started Jul 29 08:42:33 PM PDT 24
Finished Jul 29 09:35:11 PM PDT 24
Peak memory 609960 kb
Host smart-36593177-224d-4c14-b46b-9748b684aab0
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:
new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896126715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.2896126715
Directory /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2330141076
Short name T44
Test name
Test status
Simulation time 14943821586 ps
CPU time 3654.81 seconds
Started Jul 29 08:42:57 PM PDT 24
Finished Jul 29 09:43:52 PM PDT 24
Peak memory 610164 kb
Host smart-d89c2f75-1e1c-4818-bc1c-7c639e65f696
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas
:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330141076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext
_no_meas.2330141076
Directory /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location /workspace/coverage/default/2.rom_e2e_self_hash.2030692894
Short name T961
Test name
Test status
Simulation time 26051661750 ps
CPU time 5504.69 seconds
Started Jul 29 08:46:02 PM PDT 24
Finished Jul 29 10:17:47 PM PDT 24
Peak memory 609832 kb
Host smart-714aa6be-ad69-4fa9-a01e-6beb7e85b719
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r
ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030692894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.2030692894
Directory /workspace/2.rom_e2e_self_hash/latest

Test location /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3882783634
Short name T1270
Test name
Test status
Simulation time 13967534774 ps
CPU time 2974.87 seconds
Started Jul 29 08:42:49 PM PDT 24
Finished Jul 29 09:32:24 PM PDT 24
Peak memory 611612 kb
Host smart-ef4da974-ab8c-4dcd-bd65-681426f77f1c
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne
w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882783634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu
tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_
shutdown_exception_c.3882783634
Directory /workspace/2.rom_e2e_shutdown_exception_c/latest

Test location /workspace/coverage/default/2.rom_e2e_shutdown_output.2244831350
Short name T43
Test name
Test status
Simulation time 23380402265 ps
CPU time 3273.39 seconds
Started Jul 29 08:46:19 PM PDT 24
Finished Jul 29 09:40:53 PM PDT 24
Peak memory 611472 kb
Host smart-5d17f3b1-bb4d-4a05-b8ed-f01d53e57c83
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f
lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244831350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rom_e2e_shutdown_output.2244831350
Directory /workspace/2.rom_e2e_shutdown_output/latest

Test location /workspace/coverage/default/2.rom_e2e_smoke.745395525
Short name T1282
Test name
Test status
Simulation time 15215114810 ps
CPU time 3577.03 seconds
Started Jul 29 08:46:04 PM PDT 24
Finished Jul 29 09:45:41 PM PDT 24
Peak memory 610152 kb
Host smart-5ac8ab61-fa08-4fff-a7af-97c1f29f1614
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img
_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to
p/hw/dv/tools/sim.tcl +ntb_random_seed=745395525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.745395525
Directory /workspace/2.rom_e2e_smoke/latest

Test location /workspace/coverage/default/2.rom_e2e_static_critical.955942870
Short name T1064
Test name
Test status
Simulation time 16470961100 ps
CPU time 4484.04 seconds
Started Jul 29 08:43:26 PM PDT 24
Finished Jul 29 09:58:11 PM PDT 24
Peak memory 610128 kb
Host smart-b272d5cb-ca54-48d9-9819-b893d9a60397
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul
es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955942870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.955942870
Directory /workspace/2.rom_e2e_static_critical/latest

Test location /workspace/coverage/default/2.rom_keymgr_functest.2340038604
Short name T923
Test name
Test status
Simulation time 4718178856 ps
CPU time 710.35 seconds
Started Jul 29 08:40:14 PM PDT 24
Finished Jul 29 08:52:05 PM PDT 24
Peak memory 610272 kb
Host smart-62c619b2-1d10-4f25-a31f-cfdcada69a0c
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340038604 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.2340038604
Directory /workspace/2.rom_keymgr_functest/latest

Test location /workspace/coverage/default/2.rom_raw_unlock.473309868
Short name T154
Test name
Test status
Simulation time 5076501744 ps
CPU time 250.4 seconds
Started Jul 29 08:39:30 PM PDT 24
Finished Jul 29 08:43:41 PM PDT 24
Peak memory 619940 kb
Host smart-aa3593b0-f639-4f59-a953-469ae639a9ed
User root
Command /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE
xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=473309868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.473309868
Directory /workspace/2.rom_raw_unlock/latest

Test location /workspace/coverage/default/2.rom_volatile_raw_unlock.4004740569
Short name T298
Test name
Test status
Simulation time 2211441909 ps
CPU time 132.33 seconds
Started Jul 29 08:40:51 PM PDT 24
Finished Jul 29 08:43:04 PM PDT 24
Peak memory 616976 kb
Host smart-1292d2af-e265-4b71-86d2-8a46a6a68097
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1
+sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004740569 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.4004740569
Directory /workspace/2.rom_volatile_raw_unlock/latest

Test location /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1956632833
Short name T1263
Test name
Test status
Simulation time 3409762036 ps
CPU time 343.98 seconds
Started Jul 29 08:45:01 PM PDT 24
Finished Jul 29 08:50:45 PM PDT 24
Peak memory 618880 kb
Host smart-ffe9f225-0f9d-422a-b6c4-29326112bf5e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956632833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1956632833
Directory /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/23.chip_sw_all_escalation_resets.1118680456
Short name T740
Test name
Test status
Simulation time 5181426804 ps
CPU time 682.46 seconds
Started Jul 29 08:46:00 PM PDT 24
Finished Jul 29 08:57:23 PM PDT 24
Peak memory 650284 kb
Host smart-78a8934a-44ea-4177-848a-e602e653d58c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1118680456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.1118680456
Directory /workspace/23.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2350310207
Short name T80
Test name
Test status
Simulation time 3412474234 ps
CPU time 413.88 seconds
Started Jul 29 08:45:29 PM PDT 24
Finished Jul 29 08:52:24 PM PDT 24
Peak memory 649244 kb
Host smart-c8ec2f8f-d7e1-47fa-95af-4f6e18dca2ab
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350310207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2350310207
Directory /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.680688396
Short name T808
Test name
Test status
Simulation time 4178578242 ps
CPU time 468.03 seconds
Started Jul 29 08:45:30 PM PDT 24
Finished Jul 29 08:53:18 PM PDT 24
Peak memory 648760 kb
Host smart-f1599ea3-e55a-4b35-b023-a3224c3cad25
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680688396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_s
w_alert_handler_lpg_sleep_mode_alerts.680688396
Directory /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1351320989
Short name T369
Test name
Test status
Simulation time 4600810080 ps
CPU time 455.6 seconds
Started Jul 29 08:45:53 PM PDT 24
Finished Jul 29 08:53:29 PM PDT 24
Peak memory 649416 kb
Host smart-137fd83b-be65-402a-8c5c-0adec8926d42
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351320989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1351320989
Directory /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/27.chip_sw_all_escalation_resets.113098525
Short name T793
Test name
Test status
Simulation time 4734945396 ps
CPU time 532.53 seconds
Started Jul 29 08:44:46 PM PDT 24
Finished Jul 29 08:53:39 PM PDT 24
Peak memory 650896 kb
Host smart-d0234ed2-fdfe-42a5-b8cd-0ab9e84d8fd6
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
113098525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.113098525
Directory /workspace/27.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3410613076
Short name T789
Test name
Test status
Simulation time 3745119008 ps
CPU time 429.01 seconds
Started Jul 29 08:47:36 PM PDT 24
Finished Jul 29 08:54:45 PM PDT 24
Peak memory 649176 kb
Host smart-7a7550b7-b7d4-4df4-b000-79efbf29f2ae
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410613076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3410613076
Directory /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/29.chip_sw_all_escalation_resets.178616137
Short name T724
Test name
Test status
Simulation time 4746174750 ps
CPU time 557.86 seconds
Started Jul 29 08:45:45 PM PDT 24
Finished Jul 29 08:55:03 PM PDT 24
Peak memory 611040 kb
Host smart-5ef82369-370d-444c-9c81-f9051ba33fd7
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
178616137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.178616137
Directory /workspace/29.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2302411684
Short name T296
Test name
Test status
Simulation time 7015917336 ps
CPU time 388.06 seconds
Started Jul 29 08:40:16 PM PDT 24
Finished Jul 29 08:46:44 PM PDT 24
Peak memory 609088 kb
Host smart-3359428f-e974-4aa7-9fa0-8a4495710a1a
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2302411684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2302411684
Directory /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1991396723
Short name T1379
Test name
Test status
Simulation time 20704366184 ps
CPU time 4103.86 seconds
Started Jul 29 08:42:01 PM PDT 24
Finished Jul 29 09:50:26 PM PDT 24
Peak memory 609372 kb
Host smart-4eabaec6-5216-4389-9f25-6abdc2cdf9ba
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991396723 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.1991396723
Directory /workspace/3.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/3.chip_sw_data_integrity_escalation.1183850811
Short name T292
Test name
Test status
Simulation time 5419170034 ps
CPU time 719.39 seconds
Started Jul 29 08:43:21 PM PDT 24
Finished Jul 29 08:55:21 PM PDT 24
Peak memory 611132 kb
Host smart-119afd58-1a93-46f1-8bd1-697f9a1e4853
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1183850811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.1183850811
Directory /workspace/3.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3214703348
Short name T1321
Test name
Test status
Simulation time 7621649182 ps
CPU time 766.52 seconds
Started Jul 29 08:40:24 PM PDT 24
Finished Jul 29 08:53:10 PM PDT 24
Peak memory 624696 kb
Host smart-6c2edbf9-9b92-40d6-a20d-61c6c5e719c9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214703348 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.3214703348
Directory /workspace/3.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3333129319
Short name T133
Test name
Test status
Simulation time 9996025336 ps
CPU time 1160.51 seconds
Started Jul 29 08:41:10 PM PDT 24
Finished Jul 29 09:00:30 PM PDT 24
Peak memory 610548 kb
Host smart-444913f5-019d-4d4f-b551-fa9563fe07bc
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33331293
19 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.3333129319
Directory /workspace/3.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.37801991
Short name T445
Test name
Test status
Simulation time 4673158968 ps
CPU time 648.62 seconds
Started Jul 29 08:41:09 PM PDT 24
Finished Jul 29 08:51:58 PM PDT 24
Peak memory 623240 kb
Host smart-80d5ee99-11da-409f-bf2b-b1aa74779f9c
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=37801991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.37801991
Directory /workspace/3.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx.1260378735
Short name T373
Test name
Test status
Simulation time 4445597252 ps
CPU time 573.15 seconds
Started Jul 29 08:40:41 PM PDT 24
Finished Jul 29 08:50:15 PM PDT 24
Peak memory 623912 kb
Host smart-da1740b8-27b3-4148-9c24-5d9556067f85
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260378735 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.1260378735
Directory /workspace/3.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2536772773
Short name T1120
Test name
Test status
Simulation time 3644163936 ps
CPU time 451.12 seconds
Started Jul 29 08:40:23 PM PDT 24
Finished Jul 29 08:47:55 PM PDT 24
Peak memory 624528 kb
Host smart-dd7687b2-a6f6-4907-83b9-f9d580d9a63d
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536772773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx
_alt_clk_freq.2536772773
Directory /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.263911034
Short name T1337
Test name
Test status
Simulation time 8767991155 ps
CPU time 1071.89 seconds
Started Jul 29 08:40:17 PM PDT 24
Finished Jul 29 08:58:09 PM PDT 24
Peak memory 624552 kb
Host smart-6a55139f-b2ff-4617-b95a-f1df202f585b
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263911034 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba
udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_
alt_clk_freq_low_speed.263911034
Directory /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2066687747
Short name T1236
Test name
Test status
Simulation time 4754411146 ps
CPU time 665.48 seconds
Started Jul 29 08:40:04 PM PDT 24
Finished Jul 29 08:51:10 PM PDT 24
Peak memory 624044 kb
Host smart-e62d6f8d-5823-436e-84c3-25847b9cc9d5
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066687747 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.2066687747
Directory /workspace/3.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2638032851
Short name T1277
Test name
Test status
Simulation time 3939234068 ps
CPU time 603.78 seconds
Started Jul 29 08:39:30 PM PDT 24
Finished Jul 29 08:49:34 PM PDT 24
Peak memory 623948 kb
Host smart-b20c7acc-4831-442e-863b-e6f6d0289cc9
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638032851 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.2638032851
Directory /workspace/3.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2063444436
Short name T1114
Test name
Test status
Simulation time 4562999808 ps
CPU time 661.7 seconds
Started Jul 29 08:40:51 PM PDT 24
Finished Jul 29 08:51:53 PM PDT 24
Peak memory 624184 kb
Host smart-052314be-bf9c-41de-859f-f7229ad5af5d
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063444436 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.2063444436
Directory /workspace/3.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/3.chip_tap_straps_dev.3468408650
Short name T1259
Test name
Test status
Simulation time 3326845121 ps
CPU time 167.66 seconds
Started Jul 29 08:40:28 PM PDT 24
Finished Jul 29 08:43:17 PM PDT 24
Peak memory 622532 kb
Host smart-a8c1554a-38c2-4b3b-bb37-0d8912f26ce6
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3468408650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.3468408650
Directory /workspace/3.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/3.chip_tap_straps_prod.3945362838
Short name T1295
Test name
Test status
Simulation time 2774326070 ps
CPU time 168.93 seconds
Started Jul 29 08:40:42 PM PDT 24
Finished Jul 29 08:43:31 PM PDT 24
Peak memory 623800 kb
Host smart-070dbcbb-033f-4852-b9dc-1598af05a64d
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3945362838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.3945362838
Directory /workspace/3.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/3.chip_tap_straps_rma.2648494140
Short name T70
Test name
Test status
Simulation time 5828382419 ps
CPU time 541 seconds
Started Jul 29 08:40:29 PM PDT 24
Finished Jul 29 08:49:30 PM PDT 24
Peak memory 621032 kb
Host smart-7a2b0bdb-e50a-4cbd-a704-26d07610916f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648494140 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.2648494140
Directory /workspace/3.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/3.chip_tap_straps_testunlock0.1354374531
Short name T63
Test name
Test status
Simulation time 4134242032 ps
CPU time 252.38 seconds
Started Jul 29 08:40:03 PM PDT 24
Finished Jul 29 08:44:15 PM PDT 24
Peak memory 624468 kb
Host smart-4781217f-457b-4e32-9a25-ecbf774605f4
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354374531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.1354374531
Directory /workspace/3.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.325697372
Short name T164
Test name
Test status
Simulation time 3909722424 ps
CPU time 376.9 seconds
Started Jul 29 08:44:53 PM PDT 24
Finished Jul 29 08:51:10 PM PDT 24
Peak memory 618908 kb
Host smart-a8276c7f-3493-43fb-b0db-42bbde331408
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325697372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_s
w_alert_handler_lpg_sleep_mode_alerts.325697372
Directory /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/30.chip_sw_all_escalation_resets.986305697
Short name T213
Test name
Test status
Simulation time 5696741300 ps
CPU time 632.89 seconds
Started Jul 29 08:45:12 PM PDT 24
Finished Jul 29 08:55:45 PM PDT 24
Peak memory 650288 kb
Host smart-54f0e3ec-b85a-4260-a83e-ecc17f43b06f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
986305697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.986305697
Directory /workspace/30.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3867962090
Short name T763
Test name
Test status
Simulation time 3570318364 ps
CPU time 451.57 seconds
Started Jul 29 08:46:35 PM PDT 24
Finished Jul 29 08:54:07 PM PDT 24
Peak memory 649076 kb
Host smart-4d0e5836-4fd7-449d-994b-d5419337957c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867962090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3867962090
Directory /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/33.chip_sw_all_escalation_resets.2338547683
Short name T1200
Test name
Test status
Simulation time 5403099834 ps
CPU time 852.66 seconds
Started Jul 29 08:46:26 PM PDT 24
Finished Jul 29 09:00:39 PM PDT 24
Peak memory 650332 kb
Host smart-b0b79e8e-ac73-436c-996c-b7681ec99d03
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2338547683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.2338547683
Directory /workspace/33.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3668072328
Short name T765
Test name
Test status
Simulation time 3223222016 ps
CPU time 407.5 seconds
Started Jul 29 08:46:38 PM PDT 24
Finished Jul 29 08:53:27 PM PDT 24
Peak memory 649136 kb
Host smart-d1224787-8479-4dbb-8987-5b3711bcce8d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668072328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3668072328
Directory /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2808949841
Short name T1299
Test name
Test status
Simulation time 3686627814 ps
CPU time 441.53 seconds
Started Jul 29 08:47:58 PM PDT 24
Finished Jul 29 08:55:20 PM PDT 24
Peak memory 649128 kb
Host smart-52045a2d-d799-4c10-b315-a0a02126320a
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808949841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2808949841
Directory /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/35.chip_sw_all_escalation_resets.2627441739
Short name T62
Test name
Test status
Simulation time 5126194924 ps
CPU time 546.63 seconds
Started Jul 29 08:46:16 PM PDT 24
Finished Jul 29 08:55:22 PM PDT 24
Peak memory 650448 kb
Host smart-f81dd7df-7181-477a-9f68-893a528c00b1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2627441739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.2627441739
Directory /workspace/35.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2679585797
Short name T776
Test name
Test status
Simulation time 3889147166 ps
CPU time 433.94 seconds
Started Jul 29 08:46:42 PM PDT 24
Finished Jul 29 08:53:56 PM PDT 24
Peak memory 648920 kb
Host smart-a730028b-48df-4783-8fa8-2be4afd869e8
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679585797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2679585797
Directory /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.161825928
Short name T1160
Test name
Test status
Simulation time 4308943616 ps
CPU time 438.75 seconds
Started Jul 29 08:45:30 PM PDT 24
Finished Jul 29 08:52:49 PM PDT 24
Peak memory 619264 kb
Host smart-dfa221bb-ca5e-4f51-bd46-014bb6cbec7a
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161825928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_s
w_alert_handler_lpg_sleep_mode_alerts.161825928
Directory /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3574704721
Short name T1058
Test name
Test status
Simulation time 3319747096 ps
CPU time 484.46 seconds
Started Jul 29 08:46:58 PM PDT 24
Finished Jul 29 08:55:03 PM PDT 24
Peak memory 649008 kb
Host smart-c6056781-cc1b-421d-8fc6-f705a78e78e2
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574704721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3574704721
Directory /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/39.chip_sw_all_escalation_resets.1557404777
Short name T174
Test name
Test status
Simulation time 5178537340 ps
CPU time 629.02 seconds
Started Jul 29 08:47:18 PM PDT 24
Finished Jul 29 08:57:47 PM PDT 24
Peak memory 619900 kb
Host smart-5d140810-3468-4ad5-8212-e85485219900
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1557404777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.1557404777
Directory /workspace/39.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.716124672
Short name T312
Test name
Test status
Simulation time 3521571468 ps
CPU time 366.07 seconds
Started Jul 29 08:42:48 PM PDT 24
Finished Jul 29 08:48:54 PM PDT 24
Peak memory 649180 kb
Host smart-854b446a-6215-414a-a409-12f6d331dfb3
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716124672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw
_alert_handler_lpg_sleep_mode_alerts.716124672
Directory /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/4.chip_sw_all_escalation_resets.3529560316
Short name T1115
Test name
Test status
Simulation time 5129773240 ps
CPU time 568.86 seconds
Started Jul 29 08:40:54 PM PDT 24
Finished Jul 29 08:50:23 PM PDT 24
Peak memory 649988 kb
Host smart-857a1bca-df27-45c1-a0ac-478eb1cdb665
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3529560316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.3529560316
Directory /workspace/4.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1801838435
Short name T1309
Test name
Test status
Simulation time 6907057776 ps
CPU time 306.27 seconds
Started Jul 29 08:41:14 PM PDT 24
Finished Jul 29 08:46:20 PM PDT 24
Peak memory 610504 kb
Host smart-9b1fdd1b-1066-4060-9f6e-973200d8841f
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1801838435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1801838435
Directory /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3197210163
Short name T1051
Test name
Test status
Simulation time 23728921176 ps
CPU time 5181.71 seconds
Started Jul 29 08:47:33 PM PDT 24
Finished Jul 29 10:13:56 PM PDT 24
Peak memory 610388 kb
Host smart-fede1d6c-e19f-4f43-bb6e-739b11a0f11e
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197210163 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.3197210163
Directory /workspace/4.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/4.chip_sw_data_integrity_escalation.1620752248
Short name T279
Test name
Test status
Simulation time 5313177800 ps
CPU time 1068.4 seconds
Started Jul 29 08:40:46 PM PDT 24
Finished Jul 29 08:58:34 PM PDT 24
Peak memory 610748 kb
Host smart-bc7eaca9-9999-4188-a70b-98347714b44a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1620752248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.1620752248
Directory /workspace/4.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.263464635
Short name T1381
Test name
Test status
Simulation time 5312794694 ps
CPU time 465.56 seconds
Started Jul 29 08:46:28 PM PDT 24
Finished Jul 29 08:54:13 PM PDT 24
Peak memory 624752 kb
Host smart-b4f06fbd-3252-425a-84d6-9003fbc42307
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263464635 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.263464635
Directory /workspace/4.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4000789328
Short name T1132
Test name
Test status
Simulation time 7486799654 ps
CPU time 888.88 seconds
Started Jul 29 08:42:27 PM PDT 24
Finished Jul 29 08:57:17 PM PDT 24
Peak memory 610584 kb
Host smart-ebf98de0-8eb5-4a15-add6-e6908e593299
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40007893
28 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.4000789328
Directory /workspace/4.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2842409329
Short name T1223
Test name
Test status
Simulation time 8810210632 ps
CPU time 1445.16 seconds
Started Jul 29 08:41:50 PM PDT 24
Finished Jul 29 09:05:55 PM PDT 24
Peak memory 623388 kb
Host smart-06659552-faa3-4c18-acf4-457170bcfae6
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2842409329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.2842409329
Directory /workspace/4.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx.3833860187
Short name T108
Test name
Test status
Simulation time 4963219110 ps
CPU time 792.54 seconds
Started Jul 29 08:41:18 PM PDT 24
Finished Jul 29 08:54:31 PM PDT 24
Peak memory 623932 kb
Host smart-465d5ba1-4dfd-4ec2-a7db-d028e41cb055
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833860187 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.3833860187
Directory /workspace/4.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.891177693
Short name T913
Test name
Test status
Simulation time 4418836367 ps
CPU time 789.34 seconds
Started Jul 29 08:41:45 PM PDT 24
Finished Jul 29 08:54:56 PM PDT 24
Peak memory 618788 kb
Host smart-73755e0d-cc1a-4546-9227-fab5b41fcf0b
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891177693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba
udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_
alt_clk_freq.891177693
Directory /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.112584855
Short name T145
Test name
Test status
Simulation time 13571404769 ps
CPU time 1600.9 seconds
Started Jul 29 08:42:29 PM PDT 24
Finished Jul 29 09:09:11 PM PDT 24
Peak memory 624456 kb
Host smart-f4401dd0-073c-44c4-9cdb-6a146e363011
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112584855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba
udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_
alt_clk_freq_low_speed.112584855
Directory /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2237440988
Short name T1252
Test name
Test status
Simulation time 3904666224 ps
CPU time 646.71 seconds
Started Jul 29 08:41:16 PM PDT 24
Finished Jul 29 08:52:03 PM PDT 24
Peak memory 623844 kb
Host smart-e0cb6b54-7ae4-4ed8-83cf-3feb11359989
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237440988 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.2237440988
Directory /workspace/4.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1343493884
Short name T333
Test name
Test status
Simulation time 4000697432 ps
CPU time 772.68 seconds
Started Jul 29 08:42:25 PM PDT 24
Finished Jul 29 08:55:18 PM PDT 24
Peak memory 623540 kb
Host smart-6f3f57d5-b607-41f7-9e8a-7fafa148f637
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343493884 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.1343493884
Directory /workspace/4.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1708724290
Short name T1209
Test name
Test status
Simulation time 4717284770 ps
CPU time 626.18 seconds
Started Jul 29 08:41:09 PM PDT 24
Finished Jul 29 08:51:35 PM PDT 24
Peak memory 624224 kb
Host smart-6e527744-8d6f-489d-919b-3aebe70d4141
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708724290 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.1708724290
Directory /workspace/4.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/4.chip_tap_straps_dev.819727649
Short name T71
Test name
Test status
Simulation time 12355030881 ps
CPU time 1256.96 seconds
Started Jul 29 08:41:00 PM PDT 24
Finished Jul 29 09:01:57 PM PDT 24
Peak memory 621100 kb
Host smart-9cb6ccff-2b49-4777-88e4-94ea87b74886
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=819727649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.819727649
Directory /workspace/4.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/4.chip_tap_straps_prod.2987307190
Short name T930
Test name
Test status
Simulation time 9951815623 ps
CPU time 1142.93 seconds
Started Jul 29 08:41:34 PM PDT 24
Finished Jul 29 09:00:37 PM PDT 24
Peak memory 621076 kb
Host smart-b8d1ca64-099f-44ad-9e5f-2a76e0458ec7
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2987307190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.2987307190
Directory /workspace/4.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/40.chip_sw_all_escalation_resets.25993849
Short name T356
Test name
Test status
Simulation time 5301180510 ps
CPU time 543.99 seconds
Started Jul 29 08:45:30 PM PDT 24
Finished Jul 29 08:54:34 PM PDT 24
Peak memory 650436 kb
Host smart-31475f3e-c4e8-4c0a-9692-c8acb6b97c48
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
25993849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.25993849
Directory /workspace/40.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.140258410
Short name T253
Test name
Test status
Simulation time 4330640872 ps
CPU time 418.86 seconds
Started Jul 29 08:45:52 PM PDT 24
Finished Jul 29 08:52:51 PM PDT 24
Peak memory 649352 kb
Host smart-7166df08-1145-42eb-a957-57b32cab83bb
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140258410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_s
w_alert_handler_lpg_sleep_mode_alerts.140258410
Directory /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/41.chip_sw_all_escalation_resets.2506354209
Short name T1347
Test name
Test status
Simulation time 4365150632 ps
CPU time 527.74 seconds
Started Jul 29 08:47:03 PM PDT 24
Finished Jul 29 08:55:51 PM PDT 24
Peak memory 650436 kb
Host smart-48731e1c-64b6-41c7-b9fa-aecb2d55ea6e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2506354209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.2506354209
Directory /workspace/41.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2028154277
Short name T1133
Test name
Test status
Simulation time 3639693800 ps
CPU time 337.9 seconds
Started Jul 29 08:46:31 PM PDT 24
Finished Jul 29 08:52:09 PM PDT 24
Peak memory 649024 kb
Host smart-912634fd-62ff-4b42-b6f6-95e927463883
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028154277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2028154277
Directory /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.976892866
Short name T810
Test name
Test status
Simulation time 3015949110 ps
CPU time 367.67 seconds
Started Jul 29 08:47:53 PM PDT 24
Finished Jul 29 08:54:01 PM PDT 24
Peak memory 649064 kb
Host smart-a38aa8a6-b251-4f71-a75f-e3f44c6e75b6
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976892866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_s
w_alert_handler_lpg_sleep_mode_alerts.976892866
Directory /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3989939909
Short name T313
Test name
Test status
Simulation time 3643170730 ps
CPU time 344.83 seconds
Started Jul 29 08:46:59 PM PDT 24
Finished Jul 29 08:52:44 PM PDT 24
Peak memory 648968 kb
Host smart-41a45bf2-f733-4c63-9f5e-83dba69a720c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989939909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3989939909
Directory /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/44.chip_sw_all_escalation_resets.185883129
Short name T370
Test name
Test status
Simulation time 4918435976 ps
CPU time 475.69 seconds
Started Jul 29 08:46:14 PM PDT 24
Finished Jul 29 08:54:10 PM PDT 24
Peak memory 650320 kb
Host smart-4c2929e6-a83a-4d34-8a44-a3d8d571a22b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
185883129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.185883129
Directory /workspace/44.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/45.chip_sw_all_escalation_resets.3523734499
Short name T821
Test name
Test status
Simulation time 5594259942 ps
CPU time 748.91 seconds
Started Jul 29 08:46:51 PM PDT 24
Finished Jul 29 08:59:20 PM PDT 24
Peak memory 650256 kb
Host smart-fbdd7c7c-f5a9-4bca-87ac-5cc1cbd93962
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3523734499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.3523734499
Directory /workspace/45.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.208116025
Short name T736
Test name
Test status
Simulation time 3630538178 ps
CPU time 408.99 seconds
Started Jul 29 08:47:00 PM PDT 24
Finished Jul 29 08:53:49 PM PDT 24
Peak memory 649084 kb
Host smart-357116db-7864-46e8-a057-acda1ad75eda
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208116025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_s
w_alert_handler_lpg_sleep_mode_alerts.208116025
Directory /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/46.chip_sw_all_escalation_resets.69019131
Short name T833
Test name
Test status
Simulation time 5754900308 ps
CPU time 636.88 seconds
Started Jul 29 08:46:41 PM PDT 24
Finished Jul 29 08:57:18 PM PDT 24
Peak memory 649968 kb
Host smart-81cf77bd-a50c-42bf-a542-35da40c44060
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
69019131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.69019131
Directory /workspace/46.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2658446476
Short name T799
Test name
Test status
Simulation time 3780865600 ps
CPU time 297.46 seconds
Started Jul 29 08:46:45 PM PDT 24
Finished Jul 29 08:51:42 PM PDT 24
Peak memory 649140 kb
Host smart-886e7211-d9a5-4d9b-a374-da873f084f91
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658446476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2658446476
Directory /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/47.chip_sw_all_escalation_resets.1535974047
Short name T1173
Test name
Test status
Simulation time 6066053672 ps
CPU time 536.36 seconds
Started Jul 29 08:46:38 PM PDT 24
Finished Jul 29 08:55:34 PM PDT 24
Peak memory 650180 kb
Host smart-384a104e-c754-4a98-acf0-ca2910cb6bc8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1535974047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.1535974047
Directory /workspace/47.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/48.chip_sw_all_escalation_resets.2808259138
Short name T1178
Test name
Test status
Simulation time 4722666630 ps
CPU time 645.46 seconds
Started Jul 29 08:49:34 PM PDT 24
Finished Jul 29 09:00:20 PM PDT 24
Peak memory 650400 kb
Host smart-03d6111f-6856-4e7c-b880-069e3db39e85
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2808259138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.2808259138
Directory /workspace/48.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3802737293
Short name T815
Test name
Test status
Simulation time 4370272954 ps
CPU time 416.57 seconds
Started Jul 29 08:46:49 PM PDT 24
Finished Jul 29 08:53:45 PM PDT 24
Peak memory 649616 kb
Host smart-819e7ac8-ca9e-4a69-84e8-0c0ceabb5446
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802737293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3802737293
Directory /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/49.chip_sw_all_escalation_resets.3781579668
Short name T795
Test name
Test status
Simulation time 5249314768 ps
CPU time 878.05 seconds
Started Jul 29 08:47:43 PM PDT 24
Finished Jul 29 09:02:21 PM PDT 24
Peak memory 650444 kb
Host smart-15f43d34-a79b-48e9-be44-21d6f1171d53
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3781579668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.3781579668
Directory /workspace/49.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.775436552
Short name T834
Test name
Test status
Simulation time 4205741144 ps
CPU time 422.81 seconds
Started Jul 29 08:42:16 PM PDT 24
Finished Jul 29 08:49:19 PM PDT 24
Peak memory 648984 kb
Host smart-d850d2d1-b190-400a-8f7a-91433b9e019c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775436552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw
_alert_handler_lpg_sleep_mode_alerts.775436552
Directory /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/5.chip_sw_all_escalation_resets.1052144262
Short name T770
Test name
Test status
Simulation time 4442793354 ps
CPU time 584.28 seconds
Started Jul 29 08:47:18 PM PDT 24
Finished Jul 29 08:57:03 PM PDT 24
Peak memory 650360 kb
Host smart-059ce1fe-08bf-42f8-89f6-b00d5e13a950
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1052144262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.1052144262
Directory /workspace/5.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1487343964
Short name T1145
Test name
Test status
Simulation time 18797701464 ps
CPU time 4526.13 seconds
Started Jul 29 08:44:28 PM PDT 24
Finished Jul 29 09:59:55 PM PDT 24
Peak memory 610516 kb
Host smart-706caba0-3771-418a-9214-47a61bb8bdff
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487343964 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.1487343964
Directory /workspace/5.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/5.chip_sw_data_integrity_escalation.1077594077
Short name T1302
Test name
Test status
Simulation time 6006909240 ps
CPU time 625.92 seconds
Started Jul 29 08:42:42 PM PDT 24
Finished Jul 29 08:53:09 PM PDT 24
Peak memory 611120 kb
Host smart-2d371a13-5214-483b-a403-51cb52fe2d3c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1077594077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.1077594077
Directory /workspace/5.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.444838089
Short name T311
Test name
Test status
Simulation time 13374780083 ps
CPU time 1013.27 seconds
Started Jul 29 08:43:06 PM PDT 24
Finished Jul 29 08:59:59 PM PDT 24
Peak memory 620452 kb
Host smart-127d2d8b-11d8-4871-ba21-f6cb244033e8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444838089 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.444838089
Directory /workspace/5.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.224591916
Short name T218
Test name
Test status
Simulation time 8322961096 ps
CPU time 1543.06 seconds
Started Jul 29 08:42:42 PM PDT 24
Finished Jul 29 09:08:25 PM PDT 24
Peak memory 624400 kb
Host smart-d4204418-172c-4947-964e-fb2020b0a634
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=224591916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.224591916
Directory /workspace/5.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.334189987
Short name T1250
Test name
Test status
Simulation time 3182632304 ps
CPU time 336.86 seconds
Started Jul 29 08:51:15 PM PDT 24
Finished Jul 29 08:56:52 PM PDT 24
Peak memory 649144 kb
Host smart-5c5e44ce-0efa-424e-8eff-b78fb720eea7
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334189987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_s
w_alert_handler_lpg_sleep_mode_alerts.334189987
Directory /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/50.chip_sw_all_escalation_resets.3337392439
Short name T818
Test name
Test status
Simulation time 5385595384 ps
CPU time 566.79 seconds
Started Jul 29 08:47:09 PM PDT 24
Finished Jul 29 08:56:36 PM PDT 24
Peak memory 650336 kb
Host smart-b38cf033-b7b0-490e-9fed-bb7f91ef15f6
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3337392439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.3337392439
Directory /workspace/50.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1096193336
Short name T315
Test name
Test status
Simulation time 3436772120 ps
CPU time 366.26 seconds
Started Jul 29 08:46:56 PM PDT 24
Finished Jul 29 08:53:02 PM PDT 24
Peak memory 649268 kb
Host smart-b6e4e1ed-d7e5-4835-b709-eadada3139c5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096193336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1096193336
Directory /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/53.chip_sw_all_escalation_resets.2800556305
Short name T773
Test name
Test status
Simulation time 4991811022 ps
CPU time 569.64 seconds
Started Jul 29 08:47:11 PM PDT 24
Finished Jul 29 08:56:41 PM PDT 24
Peak memory 650496 kb
Host smart-32e913bf-4b98-409b-89f7-60c6874bd0c0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2800556305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.2800556305
Directory /workspace/53.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/54.chip_sw_all_escalation_resets.3809760488
Short name T358
Test name
Test status
Simulation time 5267165194 ps
CPU time 588.12 seconds
Started Jul 29 08:48:00 PM PDT 24
Finished Jul 29 08:57:48 PM PDT 24
Peak memory 650424 kb
Host smart-e1129f8d-2fe2-4d18-9c8b-ceb4bff1111a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3809760488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.3809760488
Directory /workspace/54.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.734380528
Short name T389
Test name
Test status
Simulation time 4086937220 ps
CPU time 314.75 seconds
Started Jul 29 08:47:18 PM PDT 24
Finished Jul 29 08:52:33 PM PDT 24
Peak memory 649084 kb
Host smart-7e9aa3a3-011d-4d48-84d1-23344517214f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734380528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_s
w_alert_handler_lpg_sleep_mode_alerts.734380528
Directory /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1563647056
Short name T759
Test name
Test status
Simulation time 3684338088 ps
CPU time 502.07 seconds
Started Jul 29 08:47:55 PM PDT 24
Finished Jul 29 08:56:18 PM PDT 24
Peak memory 648756 kb
Host smart-270777cd-a800-48f5-bb68-806a688af8d8
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563647056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1563647056
Directory /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3034643931
Short name T1235
Test name
Test status
Simulation time 4548248946 ps
CPU time 366.44 seconds
Started Jul 29 08:48:10 PM PDT 24
Finished Jul 29 08:54:16 PM PDT 24
Peak memory 649440 kb
Host smart-ba44fa29-4403-47e3-b0f8-750398b6f1ed
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034643931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3034643931
Directory /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/58.chip_sw_all_escalation_resets.837047774
Short name T710
Test name
Test status
Simulation time 5933383838 ps
CPU time 525.91 seconds
Started Jul 29 08:48:09 PM PDT 24
Finished Jul 29 08:56:55 PM PDT 24
Peak memory 650392 kb
Host smart-033f9cdb-50e8-4017-b8d1-ef1faf59c557
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
837047774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.837047774
Directory /workspace/58.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2313694061
Short name T1291
Test name
Test status
Simulation time 3061651800 ps
CPU time 385.7 seconds
Started Jul 29 08:51:18 PM PDT 24
Finished Jul 29 08:57:43 PM PDT 24
Peak memory 649168 kb
Host smart-f73384dd-bda2-4180-bd53-05ac113e546f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313694061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2313694061
Directory /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1702347872
Short name T751
Test name
Test status
Simulation time 4031551568 ps
CPU time 437.97 seconds
Started Jul 29 08:42:14 PM PDT 24
Finished Jul 29 08:49:32 PM PDT 24
Peak memory 649040 kb
Host smart-73d47991-6671-4a81-abaf-b036039973f3
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702347872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s
w_alert_handler_lpg_sleep_mode_alerts.1702347872
Directory /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.226778161
Short name T1197
Test name
Test status
Simulation time 22174020590 ps
CPU time 4445.34 seconds
Started Jul 29 08:42:26 PM PDT 24
Finished Jul 29 09:56:32 PM PDT 24
Peak memory 609404 kb
Host smart-08e26a7b-708c-450b-9d07-e27b446a7755
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226778161 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.226778161
Directory /workspace/6.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3180124092
Short name T920
Test name
Test status
Simulation time 6636251420 ps
CPU time 561.16 seconds
Started Jul 29 08:42:02 PM PDT 24
Finished Jul 29 08:51:24 PM PDT 24
Peak memory 620488 kb
Host smart-26070b02-a781-4e5c-a429-b061b6884175
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180124092 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.3180124092
Directory /workspace/6.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.4267107061
Short name T109
Test name
Test status
Simulation time 13116583960 ps
CPU time 2502.15 seconds
Started Jul 29 08:42:16 PM PDT 24
Finished Jul 29 09:23:58 PM PDT 24
Peak memory 623216 kb
Host smart-802a8c31-cf44-4da7-8cde-163db83b8e12
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=4267107061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.4267107061
Directory /workspace/6.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1199336264
Short name T820
Test name
Test status
Simulation time 3843661218 ps
CPU time 373.92 seconds
Started Jul 29 08:48:24 PM PDT 24
Finished Jul 29 08:54:38 PM PDT 24
Peak memory 649024 kb
Host smart-41183260-d47a-4aeb-82d2-95faf8288890
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199336264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1199336264
Directory /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/60.chip_sw_all_escalation_resets.2416249193
Short name T1315
Test name
Test status
Simulation time 4983913270 ps
CPU time 525.65 seconds
Started Jul 29 08:47:59 PM PDT 24
Finished Jul 29 08:56:45 PM PDT 24
Peak memory 617036 kb
Host smart-d0c5a247-3f28-4208-997b-45c848ffbfa5
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2416249193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.2416249193
Directory /workspace/60.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3749259220
Short name T819
Test name
Test status
Simulation time 4037657524 ps
CPU time 316.06 seconds
Started Jul 29 08:51:25 PM PDT 24
Finished Jul 29 08:56:41 PM PDT 24
Peak memory 649196 kb
Host smart-790f4f8f-e3ec-4f79-9221-40aedc183199
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749259220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3749259220
Directory /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/61.chip_sw_all_escalation_resets.3780042578
Short name T826
Test name
Test status
Simulation time 5911447272 ps
CPU time 625.68 seconds
Started Jul 29 08:47:55 PM PDT 24
Finished Jul 29 08:58:21 PM PDT 24
Peak memory 650464 kb
Host smart-f652672c-ad98-4bc8-a610-5051028d453d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3780042578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.3780042578
Directory /workspace/61.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3386266725
Short name T283
Test name
Test status
Simulation time 3722727480 ps
CPU time 332.93 seconds
Started Jul 29 08:48:29 PM PDT 24
Finished Jul 29 08:54:03 PM PDT 24
Peak memory 618928 kb
Host smart-8978fc27-3c31-4602-8d82-4484973c66ed
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386266725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3386266725
Directory /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/62.chip_sw_all_escalation_resets.1516032767
Short name T314
Test name
Test status
Simulation time 4683085802 ps
CPU time 561.62 seconds
Started Jul 29 08:47:11 PM PDT 24
Finished Jul 29 08:56:33 PM PDT 24
Peak memory 650484 kb
Host smart-f0a10de4-df70-4031-a256-751714ed098d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1516032767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.1516032767
Directory /workspace/62.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3241732684
Short name T1331
Test name
Test status
Simulation time 3431990670 ps
CPU time 450.6 seconds
Started Jul 29 08:47:47 PM PDT 24
Finished Jul 29 08:55:18 PM PDT 24
Peak memory 649008 kb
Host smart-d6175959-7129-47ec-87e3-7682b03a87f7
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241732684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3241732684
Directory /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.155821697
Short name T772
Test name
Test status
Simulation time 4024774664 ps
CPU time 384.01 seconds
Started Jul 29 08:51:12 PM PDT 24
Finished Jul 29 08:57:36 PM PDT 24
Peak memory 648968 kb
Host smart-2eecb5da-edbb-4a8b-a2b2-2e04ea8abdf4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155821697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_s
w_alert_handler_lpg_sleep_mode_alerts.155821697
Directory /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/64.chip_sw_all_escalation_resets.810658942
Short name T359
Test name
Test status
Simulation time 4683679760 ps
CPU time 566.8 seconds
Started Jul 29 08:48:01 PM PDT 24
Finished Jul 29 08:57:29 PM PDT 24
Peak memory 650416 kb
Host smart-091023ba-9461-4570-982b-eacf80be1221
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
810658942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.810658942
Directory /workspace/64.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.848202023
Short name T107
Test name
Test status
Simulation time 3782984216 ps
CPU time 399.4 seconds
Started Jul 29 08:51:32 PM PDT 24
Finished Jul 29 08:58:12 PM PDT 24
Peak memory 649172 kb
Host smart-f42c6bcb-26b1-4a60-936c-2b8e893002c6
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848202023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_s
w_alert_handler_lpg_sleep_mode_alerts.848202023
Directory /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1529311979
Short name T827
Test name
Test status
Simulation time 3329299238 ps
CPU time 381.6 seconds
Started Jul 29 08:49:08 PM PDT 24
Finished Jul 29 08:55:29 PM PDT 24
Peak memory 648876 kb
Host smart-8b95907e-4df2-4681-9c80-0492a52af0cb
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529311979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1529311979
Directory /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/66.chip_sw_all_escalation_resets.2786697193
Short name T539
Test name
Test status
Simulation time 5839110184 ps
CPU time 651.79 seconds
Started Jul 29 08:48:22 PM PDT 24
Finished Jul 29 08:59:14 PM PDT 24
Peak memory 650044 kb
Host smart-9a4ad031-4b37-4e3d-9eb7-519f2e77a778
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2786697193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.2786697193
Directory /workspace/66.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/68.chip_sw_all_escalation_resets.2073785600
Short name T723
Test name
Test status
Simulation time 4945246650 ps
CPU time 604.31 seconds
Started Jul 29 08:50:12 PM PDT 24
Finished Jul 29 09:00:16 PM PDT 24
Peak memory 610720 kb
Host smart-836d8de1-a390-4694-ae9f-38da7909ab7f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2073785600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.2073785600
Directory /workspace/68.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.595861436
Short name T212
Test name
Test status
Simulation time 3989664912 ps
CPU time 342.97 seconds
Started Jul 29 08:49:57 PM PDT 24
Finished Jul 29 08:55:40 PM PDT 24
Peak memory 648756 kb
Host smart-da43ed5a-1057-4598-b996-e1ddd7984edc
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595861436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_s
w_alert_handler_lpg_sleep_mode_alerts.595861436
Directory /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/69.chip_sw_all_escalation_resets.249185900
Short name T1176
Test name
Test status
Simulation time 4600162120 ps
CPU time 476.94 seconds
Started Jul 29 08:48:44 PM PDT 24
Finished Jul 29 08:56:41 PM PDT 24
Peak memory 650416 kb
Host smart-91783764-5f75-4663-adc1-a57791198fa1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
249185900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.249185900
Directory /workspace/69.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2110195758
Short name T753
Test name
Test status
Simulation time 3633595624 ps
CPU time 354.63 seconds
Started Jul 29 08:47:53 PM PDT 24
Finished Jul 29 08:53:48 PM PDT 24
Peak memory 648768 kb
Host smart-4f3320b1-0ef6-4724-b4de-94c30ebac15e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110195758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s
w_alert_handler_lpg_sleep_mode_alerts.2110195758
Directory /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/7.chip_sw_all_escalation_resets.2005763001
Short name T175
Test name
Test status
Simulation time 5780078020 ps
CPU time 588.18 seconds
Started Jul 29 08:43:21 PM PDT 24
Finished Jul 29 08:53:10 PM PDT 24
Peak memory 616968 kb
Host smart-e179851d-b2be-4d3a-b046-a7ac6fa876ab
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2005763001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.2005763001
Directory /workspace/7.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1250055651
Short name T700
Test name
Test status
Simulation time 15989035700 ps
CPU time 3151.11 seconds
Started Jul 29 08:42:28 PM PDT 24
Finished Jul 29 09:34:59 PM PDT 24
Peak memory 610460 kb
Host smart-216a0050-d99d-4755-bae1-5ca842689c50
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250055651 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.1250055651
Directory /workspace/7.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2419516606
Short name T957
Test name
Test status
Simulation time 14522691502 ps
CPU time 1052.35 seconds
Started Jul 29 08:42:21 PM PDT 24
Finished Jul 29 08:59:54 PM PDT 24
Peak memory 620524 kb
Host smart-6549681a-a35f-40b9-95ee-9f886a39a02d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419516606 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.2419516606
Directory /workspace/7.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3773014612
Short name T1091
Test name
Test status
Simulation time 3846601580 ps
CPU time 501.72 seconds
Started Jul 29 08:44:19 PM PDT 24
Finished Jul 29 08:52:41 PM PDT 24
Peak memory 624384 kb
Host smart-a1806ce0-5d67-4dc8-b9cf-0c8dc450a786
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3773014612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.3773014612
Directory /workspace/7.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3495092355
Short name T1049
Test name
Test status
Simulation time 3513208330 ps
CPU time 331.42 seconds
Started Jul 29 08:49:16 PM PDT 24
Finished Jul 29 08:54:47 PM PDT 24
Peak memory 649136 kb
Host smart-dd324911-3f96-44e6-be6d-bf7fff127a50
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495092355 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3495092355
Directory /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/70.chip_sw_all_escalation_resets.2353963324
Short name T308
Test name
Test status
Simulation time 5179838308 ps
CPU time 514.46 seconds
Started Jul 29 08:48:25 PM PDT 24
Finished Jul 29 08:57:00 PM PDT 24
Peak memory 650396 kb
Host smart-99cb44d1-369f-460d-8501-031d005473ce
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2353963324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.2353963324
Directory /workspace/70.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3943232170
Short name T704
Test name
Test status
Simulation time 3863961820 ps
CPU time 377.06 seconds
Started Jul 29 08:49:54 PM PDT 24
Finished Jul 29 08:56:12 PM PDT 24
Peak memory 649136 kb
Host smart-be2f3b73-2f0d-406a-afda-e7816a573048
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943232170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3943232170
Directory /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/71.chip_sw_all_escalation_resets.3015498694
Short name T813
Test name
Test status
Simulation time 5153786692 ps
CPU time 530.69 seconds
Started Jul 29 08:49:56 PM PDT 24
Finished Jul 29 08:58:47 PM PDT 24
Peak memory 649992 kb
Host smart-5ec62a7a-0106-477f-8faa-662f66ddef34
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3015498694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.3015498694
Directory /workspace/71.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2031632924
Short name T825
Test name
Test status
Simulation time 3918667290 ps
CPU time 379.27 seconds
Started Jul 29 08:49:02 PM PDT 24
Finished Jul 29 08:55:22 PM PDT 24
Peak memory 649116 kb
Host smart-e2b1ee80-eec8-4e43-adb2-811e011d1a07
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031632924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2031632924
Directory /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.251114537
Short name T1135
Test name
Test status
Simulation time 3416146748 ps
CPU time 351.07 seconds
Started Jul 29 08:49:13 PM PDT 24
Finished Jul 29 08:55:04 PM PDT 24
Peak memory 648992 kb
Host smart-35397a56-bc9a-46ff-a930-84076d1b5969
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251114537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_s
w_alert_handler_lpg_sleep_mode_alerts.251114537
Directory /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/74.chip_sw_all_escalation_resets.18419879
Short name T783
Test name
Test status
Simulation time 5900311480 ps
CPU time 533.98 seconds
Started Jul 29 08:50:13 PM PDT 24
Finished Jul 29 08:59:07 PM PDT 24
Peak memory 650392 kb
Host smart-fca0370f-7b32-4047-8f74-e5a8634e5ee6
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
18419879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.18419879
Directory /workspace/74.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3173553991
Short name T1257
Test name
Test status
Simulation time 3830690494 ps
CPU time 323.43 seconds
Started Jul 29 08:49:03 PM PDT 24
Finished Jul 29 08:54:27 PM PDT 24
Peak memory 649160 kb
Host smart-e5f0a11f-14c0-4b96-82e3-816eab0d3f8f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173553991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3173553991
Directory /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/75.chip_sw_all_escalation_resets.187839845
Short name T393
Test name
Test status
Simulation time 5469665640 ps
CPU time 550.02 seconds
Started Jul 29 08:50:13 PM PDT 24
Finished Jul 29 08:59:23 PM PDT 24
Peak memory 650808 kb
Host smart-a9030292-4ac1-4581-b12d-b12762d0b6e1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
187839845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.187839845
Directory /workspace/75.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2442919015
Short name T165
Test name
Test status
Simulation time 3103623400 ps
CPU time 334.25 seconds
Started Jul 29 08:50:40 PM PDT 24
Finished Jul 29 08:56:14 PM PDT 24
Peak memory 648784 kb
Host smart-c1cbd9a4-b6a5-491c-8544-ab37b846c62f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442919015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2442919015
Directory /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3014371432
Short name T1211
Test name
Test status
Simulation time 3870194720 ps
CPU time 326.1 seconds
Started Jul 29 08:49:42 PM PDT 24
Finished Jul 29 08:55:08 PM PDT 24
Peak memory 648764 kb
Host smart-29b6887f-575c-4a30-b256-28de0c0cbeed
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014371432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3014371432
Directory /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/77.chip_sw_all_escalation_resets.3578939573
Short name T444
Test name
Test status
Simulation time 5224705908 ps
CPU time 599.26 seconds
Started Jul 29 08:48:27 PM PDT 24
Finished Jul 29 08:58:27 PM PDT 24
Peak memory 650196 kb
Host smart-528792f7-57b2-4fad-a2ad-2a1c5b74e897
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3578939573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.3578939573
Directory /workspace/77.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.506967579
Short name T801
Test name
Test status
Simulation time 3299611880 ps
CPU time 503.21 seconds
Started Jul 29 08:49:49 PM PDT 24
Finished Jul 29 08:58:12 PM PDT 24
Peak memory 648716 kb
Host smart-b88b0379-c9c0-48d4-986b-b3001db511b0
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506967579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_s
w_alert_handler_lpg_sleep_mode_alerts.506967579
Directory /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/79.chip_sw_all_escalation_resets.2693363761
Short name T830
Test name
Test status
Simulation time 4735766514 ps
CPU time 521.29 seconds
Started Jul 29 08:49:26 PM PDT 24
Finished Jul 29 08:58:07 PM PDT 24
Peak memory 650048 kb
Host smart-e2b31402-d92d-4ef3-bbf4-1ca751718fe1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2693363761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.2693363761
Directory /workspace/79.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4185958062
Short name T824
Test name
Test status
Simulation time 3341776620 ps
CPU time 387.33 seconds
Started Jul 29 08:43:01 PM PDT 24
Finished Jul 29 08:49:28 PM PDT 24
Peak memory 649180 kb
Host smart-f7701a66-22e5-4d19-aea2-cbcbc2c58597
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185958062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s
w_alert_handler_lpg_sleep_mode_alerts.4185958062
Directory /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.621885967
Short name T1036
Test name
Test status
Simulation time 20425757156 ps
CPU time 4662.17 seconds
Started Jul 29 08:43:58 PM PDT 24
Finished Jul 29 10:01:41 PM PDT 24
Peak memory 610376 kb
Host smart-d6c398cf-1aea-4de7-8696-9034504c3f3d
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621885967 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.621885967
Directory /workspace/8.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3799705880
Short name T1123
Test name
Test status
Simulation time 5794009980 ps
CPU time 629.56 seconds
Started Jul 29 08:42:25 PM PDT 24
Finished Jul 29 08:52:55 PM PDT 24
Peak memory 620524 kb
Host smart-75abf767-8566-4637-8956-c824e3c23f2a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799705880 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.3799705880
Directory /workspace/8.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3467783514
Short name T353
Test name
Test status
Simulation time 4403373640 ps
CPU time 587.55 seconds
Started Jul 29 08:41:59 PM PDT 24
Finished Jul 29 08:51:47 PM PDT 24
Peak memory 624432 kb
Host smart-3177ca0e-40cc-424e-b3e8-d54f06a158a1
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3467783514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.3467783514
Directory /workspace/8.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.846051642
Short name T231
Test name
Test status
Simulation time 3055613050 ps
CPU time 337.35 seconds
Started Jul 29 08:50:02 PM PDT 24
Finished Jul 29 08:55:40 PM PDT 24
Peak memory 649196 kb
Host smart-21af8ead-9799-4e10-acb4-1448b184ac10
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846051642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_s
w_alert_handler_lpg_sleep_mode_alerts.846051642
Directory /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/80.chip_sw_all_escalation_resets.2471063928
Short name T823
Test name
Test status
Simulation time 5384609010 ps
CPU time 727.72 seconds
Started Jul 29 08:49:22 PM PDT 24
Finished Jul 29 09:01:29 PM PDT 24
Peak memory 649984 kb
Host smart-dc2993a8-65ad-443c-a64e-7966c4f44935
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2471063928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.2471063928
Directory /workspace/80.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2817406521
Short name T91
Test name
Test status
Simulation time 3988791800 ps
CPU time 461.8 seconds
Started Jul 29 08:51:52 PM PDT 24
Finished Jul 29 08:59:35 PM PDT 24
Peak memory 649292 kb
Host smart-0966fb3f-b972-4ac6-97dd-9666224da5ab
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817406521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2817406521
Directory /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/81.chip_sw_all_escalation_resets.2994569686
Short name T757
Test name
Test status
Simulation time 4691266032 ps
CPU time 579.96 seconds
Started Jul 29 08:49:30 PM PDT 24
Finished Jul 29 08:59:10 PM PDT 24
Peak memory 650124 kb
Host smart-fec6dd0c-3196-46fe-8788-6f268d2415bc
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2994569686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.2994569686
Directory /workspace/81.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1350857388
Short name T816
Test name
Test status
Simulation time 3903458700 ps
CPU time 402.4 seconds
Started Jul 29 08:50:46 PM PDT 24
Finished Jul 29 08:57:28 PM PDT 24
Peak memory 649008 kb
Host smart-14c5c0f0-5ae6-47c1-9286-121f8172fb31
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350857388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1350857388
Directory /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/82.chip_sw_all_escalation_resets.1492307165
Short name T760
Test name
Test status
Simulation time 4955396404 ps
CPU time 509.6 seconds
Started Jul 29 08:51:04 PM PDT 24
Finished Jul 29 08:59:34 PM PDT 24
Peak memory 650308 kb
Host smart-c9b7d890-5f7b-4120-bf51-d5b7dc0bf8b3
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1492307165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.1492307165
Directory /workspace/82.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1427749158
Short name T265
Test name
Test status
Simulation time 3681363232 ps
CPU time 345.44 seconds
Started Jul 29 08:53:39 PM PDT 24
Finished Jul 29 08:59:24 PM PDT 24
Peak memory 649104 kb
Host smart-b79ef31f-5d72-4907-a846-b705507142c0
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427749158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1427749158
Directory /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.4242899853
Short name T811
Test name
Test status
Simulation time 2970435514 ps
CPU time 367.39 seconds
Started Jul 29 08:50:21 PM PDT 24
Finished Jul 29 08:56:28 PM PDT 24
Peak memory 649140 kb
Host smart-81b7cac0-a9ea-41fb-89ba-d60959262ffb
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242899853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4242899853
Directory /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/84.chip_sw_all_escalation_resets.69338031
Short name T780
Test name
Test status
Simulation time 4832516290 ps
CPU time 503.09 seconds
Started Jul 29 08:50:11 PM PDT 24
Finished Jul 29 08:58:34 PM PDT 24
Peak memory 650116 kb
Host smart-78db76c9-2522-4bbc-9df4-d65e4e5d8dde
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
69338031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.69338031
Directory /workspace/84.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4187009083
Short name T295
Test name
Test status
Simulation time 4035254528 ps
CPU time 439.84 seconds
Started Jul 29 08:51:09 PM PDT 24
Finished Jul 29 08:58:29 PM PDT 24
Peak memory 649124 kb
Host smart-7888a8f3-4bc9-4755-a4fc-b2ec20764b6b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187009083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4187009083
Directory /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/85.chip_sw_all_escalation_resets.2097671339
Short name T822
Test name
Test status
Simulation time 5963738624 ps
CPU time 507.09 seconds
Started Jul 29 08:49:34 PM PDT 24
Finished Jul 29 08:58:01 PM PDT 24
Peak memory 649956 kb
Host smart-9ee45501-b021-4bce-a25f-5bcfaf7aabd7
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2097671339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.2097671339
Directory /workspace/85.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1821685493
Short name T828
Test name
Test status
Simulation time 3628740510 ps
CPU time 390.28 seconds
Started Jul 29 08:52:02 PM PDT 24
Finished Jul 29 08:58:32 PM PDT 24
Peak memory 649224 kb
Host smart-f6df8025-3a32-4d84-bb55-10c6b3a8bd54
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821685493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1821685493
Directory /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/86.chip_sw_all_escalation_resets.4050109277
Short name T540
Test name
Test status
Simulation time 6335115350 ps
CPU time 537.4 seconds
Started Jul 29 08:50:50 PM PDT 24
Finished Jul 29 08:59:48 PM PDT 24
Peak memory 650360 kb
Host smart-287eade1-83a5-4728-9a28-e18f2b2424fa
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4050109277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.4050109277
Directory /workspace/86.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2291284811
Short name T768
Test name
Test status
Simulation time 3633831392 ps
CPU time 410.5 seconds
Started Jul 29 08:50:33 PM PDT 24
Finished Jul 29 08:57:23 PM PDT 24
Peak memory 649100 kb
Host smart-63f62156-67ca-41e4-ad1a-12b34b42560a
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291284811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2291284811
Directory /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/87.chip_sw_all_escalation_resets.399796692
Short name T767
Test name
Test status
Simulation time 4638155916 ps
CPU time 543.79 seconds
Started Jul 29 08:49:37 PM PDT 24
Finished Jul 29 08:58:40 PM PDT 24
Peak memory 650040 kb
Host smart-1387b793-7ce9-4767-a9ff-d7ca649da1bb
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
399796692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.399796692
Directory /workspace/87.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1144006275
Short name T829
Test name
Test status
Simulation time 4009061904 ps
CPU time 366.14 seconds
Started Jul 29 08:51:06 PM PDT 24
Finished Jul 29 08:57:12 PM PDT 24
Peak memory 649144 kb
Host smart-134b7b1d-a1d5-49ec-9c94-4388bf662b23
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144006275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1144006275
Directory /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/88.chip_sw_all_escalation_resets.3127588729
Short name T357
Test name
Test status
Simulation time 5354195604 ps
CPU time 544.16 seconds
Started Jul 29 08:52:16 PM PDT 24
Finished Jul 29 09:01:20 PM PDT 24
Peak memory 650460 kb
Host smart-7ab1b66c-7797-4160-8e91-771804e04f1e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3127588729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.3127588729
Directory /workspace/88.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4066767090
Short name T405
Test name
Test status
Simulation time 3279928570 ps
CPU time 413.94 seconds
Started Jul 29 08:51:11 PM PDT 24
Finished Jul 29 08:58:05 PM PDT 24
Peak memory 649172 kb
Host smart-7a912753-b41b-4d50-b808-e3103c234dfe
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066767090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4066767090
Directory /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/89.chip_sw_all_escalation_resets.1569234356
Short name T806
Test name
Test status
Simulation time 5493153948 ps
CPU time 570.43 seconds
Started Jul 29 08:51:13 PM PDT 24
Finished Jul 29 09:00:43 PM PDT 24
Peak memory 650460 kb
Host smart-8233f716-eba9-44dd-bf05-2ea320e659eb
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1569234356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.1569234356
Directory /workspace/89.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1674674414
Short name T941
Test name
Test status
Simulation time 3556743904 ps
CPU time 387.84 seconds
Started Jul 29 08:44:01 PM PDT 24
Finished Jul 29 08:50:31 PM PDT 24
Peak memory 649172 kb
Host smart-34c1ec6b-3424-4f08-8637-f9094c40c425
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674674414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s
w_alert_handler_lpg_sleep_mode_alerts.1674674414
Directory /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/9.chip_sw_all_escalation_resets.346648701
Short name T1003
Test name
Test status
Simulation time 4441888968 ps
CPU time 596.15 seconds
Started Jul 29 08:44:38 PM PDT 24
Finished Jul 29 08:54:34 PM PDT 24
Peak memory 650376 kb
Host smart-0cd2f654-7bd3-496e-b75f-ecda532ba24c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
346648701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.346648701
Directory /workspace/9.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.4144383232
Short name T706
Test name
Test status
Simulation time 24128158660 ps
CPU time 4970.62 seconds
Started Jul 29 08:48:21 PM PDT 24
Finished Jul 29 10:11:13 PM PDT 24
Peak memory 610348 kb
Host smart-8940ee67-5ab3-4a03-b651-7875a736ade6
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144383232 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.4144383232
Directory /workspace/9.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1152346252
Short name T1007
Test name
Test status
Simulation time 9176229011 ps
CPU time 747.2 seconds
Started Jul 29 08:42:54 PM PDT 24
Finished Jul 29 08:55:21 PM PDT 24
Peak memory 624820 kb
Host smart-785dc55f-c46a-4da8-bfe9-18aec67662a3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152346252 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.1152346252
Directory /workspace/9.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1257059285
Short name T219
Test name
Test status
Simulation time 8169127404 ps
CPU time 1226.31 seconds
Started Jul 29 08:44:41 PM PDT 24
Finished Jul 29 09:05:08 PM PDT 24
Peak memory 624512 kb
Host smart-beb22705-20f0-4a84-a9fe-c28a3ab196ec
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1257059285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.1257059285
Directory /workspace/9.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/90.chip_sw_all_escalation_resets.3328216774
Short name T1070
Test name
Test status
Simulation time 5606778022 ps
CPU time 433.22 seconds
Started Jul 29 08:49:35 PM PDT 24
Finished Jul 29 08:56:48 PM PDT 24
Peak memory 650392 kb
Host smart-ac242c43-02c7-4e47-8703-dac8273f4b7e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3328216774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.3328216774
Directory /workspace/90.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/91.chip_sw_all_escalation_resets.1873890759
Short name T831
Test name
Test status
Simulation time 4175012746 ps
CPU time 528.51 seconds
Started Jul 29 08:49:24 PM PDT 24
Finished Jul 29 08:58:13 PM PDT 24
Peak memory 649952 kb
Host smart-5f61f98d-b219-4eb2-8ba3-fb7466c28f89
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1873890759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.1873890759
Directory /workspace/91.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/92.chip_sw_all_escalation_resets.1943869828
Short name T796
Test name
Test status
Simulation time 5355512902 ps
CPU time 629.57 seconds
Started Jul 29 08:50:26 PM PDT 24
Finished Jul 29 09:00:55 PM PDT 24
Peak memory 650512 kb
Host smart-82a2aaea-2a4e-4a62-844b-945eeeea9694
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1943869828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.1943869828
Directory /workspace/92.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/93.chip_sw_all_escalation_resets.1644014470
Short name T792
Test name
Test status
Simulation time 5006907476 ps
CPU time 691.95 seconds
Started Jul 29 08:49:41 PM PDT 24
Finished Jul 29 09:01:13 PM PDT 24
Peak memory 650760 kb
Host smart-9400e602-fa21-4644-b26b-173b82226106
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1644014470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.1644014470
Directory /workspace/93.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/94.chip_sw_all_escalation_resets.3758875387
Short name T1323
Test name
Test status
Simulation time 5452770120 ps
CPU time 503.36 seconds
Started Jul 29 08:50:08 PM PDT 24
Finished Jul 29 08:58:31 PM PDT 24
Peak memory 650360 kb
Host smart-9cbff88a-7d6d-4eaf-988f-af3ff2e86088
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3758875387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.3758875387
Directory /workspace/94.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/95.chip_sw_all_escalation_resets.1788479260
Short name T788
Test name
Test status
Simulation time 5549961972 ps
CPU time 586.34 seconds
Started Jul 29 08:50:24 PM PDT 24
Finished Jul 29 09:00:11 PM PDT 24
Peak memory 650676 kb
Host smart-7cfd927b-6594-4c84-bff2-8458ff1478d6
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1788479260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.1788479260
Directory /workspace/95.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/96.chip_sw_all_escalation_resets.212657544
Short name T803
Test name
Test status
Simulation time 5232625528 ps
CPU time 505.02 seconds
Started Jul 29 08:50:33 PM PDT 24
Finished Jul 29 08:58:59 PM PDT 24
Peak memory 650320 kb
Host smart-e62e5c41-54a9-4cf2-902d-2d68d858f995
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
212657544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.212657544
Directory /workspace/96.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/97.chip_sw_all_escalation_resets.1092582839
Short name T81
Test name
Test status
Simulation time 4367457008 ps
CPU time 653.81 seconds
Started Jul 29 08:51:30 PM PDT 24
Finished Jul 29 09:02:24 PM PDT 24
Peak memory 650672 kb
Host smart-2086ae60-6000-49f3-ab95-0fc744e8b5b9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1092582839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.1092582839
Directory /workspace/97.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/98.chip_sw_all_escalation_resets.931961741
Short name T232
Test name
Test status
Simulation time 5404634156 ps
CPU time 682.74 seconds
Started Jul 29 08:51:35 PM PDT 24
Finished Jul 29 09:02:58 PM PDT 24
Peak memory 650484 kb
Host smart-4de9ce6a-739e-4e0b-9a44-30127b00c1d6
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
931961741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.931961741
Directory /workspace/98.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/99.chip_sw_all_escalation_resets.2961985067
Short name T709
Test name
Test status
Simulation time 6146927876 ps
CPU time 612.12 seconds
Started Jul 29 08:51:03 PM PDT 24
Finished Jul 29 09:01:15 PM PDT 24
Peak memory 650612 kb
Host smart-05f39095-ec38-448b-8f11-76069977f82d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2961985067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.2961985067
Directory /workspace/99.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.844645455
Short name T198
Test name
Test status
Simulation time 4203935520 ps
CPU time 176.48 seconds
Started Jul 29 08:06:38 PM PDT 24
Finished Jul 29 08:09:34 PM PDT 24
Peak memory 641012 kb
Host smart-8ce69526-25ab-44d3-9ba1-2ff2fe51594f
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844645455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n
ull -cm_name 0.chip_padctrl_attributes.844645455
Directory /workspace/0.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1082255899
Short name T197
Test name
Test status
Simulation time 5391203353 ps
CPU time 226.14 seconds
Started Jul 29 08:06:33 PM PDT 24
Finished Jul 29 08:10:19 PM PDT 24
Peak memory 655892 kb
Host smart-09da23c0-c6ac-4a2b-9f1f-59bf85d3cd57
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082255899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 2.chip_padctrl_attributes.1082255899
Directory /workspace/2.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2800884042
Short name T200
Test name
Test status
Simulation time 5530342130 ps
CPU time 229.98 seconds
Started Jul 29 08:06:37 PM PDT 24
Finished Jul 29 08:10:28 PM PDT 24
Peak memory 640948 kb
Host smart-22430863-e638-456e-9f0e-549a7ecad6d8
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800884042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 3.chip_padctrl_attributes.2800884042
Directory /workspace/3.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3703515113
Short name T202
Test name
Test status
Simulation time 4654653534 ps
CPU time 220.26 seconds
Started Jul 29 08:06:38 PM PDT 24
Finished Jul 29 08:10:18 PM PDT 24
Peak memory 641000 kb
Host smart-8e7b911d-85f5-4eea-adae-18a697dcb8c0
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703515113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 5.chip_padctrl_attributes.3703515113
Directory /workspace/5.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.527295222
Short name T199
Test name
Test status
Simulation time 5554854026 ps
CPU time 297.39 seconds
Started Jul 29 08:06:34 PM PDT 24
Finished Jul 29 08:11:31 PM PDT 24
Peak memory 649160 kb
Host smart-7c884705-3a0f-43f9-962c-e5e72bcf48fd
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527295222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n
ull -cm_name 6.chip_padctrl_attributes.527295222
Directory /workspace/6.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3078172574
Short name T30
Test name
Test status
Simulation time 4563916600 ps
CPU time 270.9 seconds
Started Jul 29 08:06:33 PM PDT 24
Finished Jul 29 08:11:05 PM PDT 24
Peak memory 643140 kb
Host smart-f8896beb-feb9-4b57-9ff5-fcd3de36d185
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078172574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 7.chip_padctrl_attributes.3078172574
Directory /workspace/7.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4140628318
Short name T196
Test name
Test status
Simulation time 5242627544 ps
CPU time 237.83 seconds
Started Jul 29 08:06:32 PM PDT 24
Finished Jul 29 08:10:30 PM PDT 24
Peak memory 657288 kb
Host smart-4d5be0a9-5008-4778-bdd1-0b4fd3f4e896
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140628318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 8.chip_padctrl_attributes.4140628318
Directory /workspace/8.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3148296577
Short name T31
Test name
Test status
Simulation time 4708383250 ps
CPU time 199.83 seconds
Started Jul 29 08:06:34 PM PDT 24
Finished Jul 29 08:09:54 PM PDT 24
Peak memory 640968 kb
Host smart-2b5455ad-dfec-408c-b8e9-c99d3a2b2a6b
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148296577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 9.chip_padctrl_attributes.3148296577
Directory /workspace/9.chip_padctrl_attributes/latest
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