| T1198 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.1983621610 |
|
|
Jul 29 08:28:33 PM PDT 24 |
Jul 29 09:29:15 PM PDT 24 |
15597506928 ps |
| T140 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1407055544 |
|
|
Jul 29 08:37:49 PM PDT 24 |
Jul 29 09:16:06 PM PDT 24 |
19594039085 ps |
| T1199 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.891158185 |
|
|
Jul 29 08:33:44 PM PDT 24 |
Jul 29 09:26:50 PM PDT 24 |
17259960280 ps |
| T829 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1144006275 |
|
|
Jul 29 08:51:06 PM PDT 24 |
Jul 29 08:57:12 PM PDT 24 |
4009061904 ps |
| T85 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3907767090 |
|
|
Jul 29 08:30:49 PM PDT 24 |
Jul 29 11:33:51 PM PDT 24 |
255999701268 ps |
| T1200 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.2338547683 |
|
|
Jul 29 08:46:26 PM PDT 24 |
Jul 29 09:00:39 PM PDT 24 |
5403099834 ps |
| T1201 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1788083397 |
|
|
Jul 29 08:17:11 PM PDT 24 |
Jul 29 08:51:42 PM PDT 24 |
12418271211 ps |
| T1202 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.1285980295 |
|
|
Jul 29 08:43:33 PM PDT 24 |
Jul 29 09:36:52 PM PDT 24 |
15832386287 ps |
| T1203 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2572247544 |
|
|
Jul 29 08:30:20 PM PDT 24 |
Jul 29 08:41:30 PM PDT 24 |
3649546360 ps |
| T810 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.976892866 |
|
|
Jul 29 08:47:53 PM PDT 24 |
Jul 29 08:54:01 PM PDT 24 |
3015949110 ps |
| T195 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1593524479 |
|
|
Jul 29 08:14:14 PM PDT 24 |
Jul 29 08:22:33 PM PDT 24 |
4629174658 ps |
| T782 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.3572622674 |
|
|
Jul 29 08:13:55 PM PDT 24 |
Jul 29 08:26:39 PM PDT 24 |
5432243024 ps |
| T806 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1569234356 |
|
|
Jul 29 08:51:13 PM PDT 24 |
Jul 29 09:00:43 PM PDT 24 |
5493153948 ps |
| T279 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1620752248 |
|
|
Jul 29 08:40:46 PM PDT 24 |
Jul 29 08:58:34 PM PDT 24 |
5313177800 ps |
| T1204 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.4098722105 |
|
|
Jul 29 08:31:06 PM PDT 24 |
Jul 29 08:44:16 PM PDT 24 |
4754198088 ps |
| T1205 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2941477965 |
|
|
Jul 29 08:32:28 PM PDT 24 |
Jul 29 08:45:35 PM PDT 24 |
6391172056 ps |
| T1206 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.211213376 |
|
|
Jul 29 08:35:19 PM PDT 24 |
Jul 29 08:58:21 PM PDT 24 |
7402696568 ps |
| T1207 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2973528835 |
|
|
Jul 29 08:26:48 PM PDT 24 |
Jul 29 08:45:35 PM PDT 24 |
7880222180 ps |
| T1208 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1703343760 |
|
|
Jul 29 08:29:43 PM PDT 24 |
Jul 29 08:35:09 PM PDT 24 |
3521872498 ps |
| T533 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.317803180 |
|
|
Jul 29 08:39:51 PM PDT 24 |
Jul 29 08:52:23 PM PDT 24 |
4855308848 ps |
| T1209 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1708724290 |
|
|
Jul 29 08:41:09 PM PDT 24 |
Jul 29 08:51:35 PM PDT 24 |
4717284770 ps |
| T39 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.1854910040 |
|
|
Jul 29 08:34:04 PM PDT 24 |
Jul 29 08:39:58 PM PDT 24 |
2888483198 ps |
| T784 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.2853245153 |
|
|
Jul 29 08:50:42 PM PDT 24 |
Jul 29 09:03:38 PM PDT 24 |
6136312154 ps |
| T1210 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1060282828 |
|
|
Jul 29 08:31:14 PM PDT 24 |
Jul 29 09:24:32 PM PDT 24 |
15005263306 ps |
| T1211 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3014371432 |
|
|
Jul 29 08:49:42 PM PDT 24 |
Jul 29 08:55:08 PM PDT 24 |
3870194720 ps |
| T1212 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2693810015 |
|
|
Jul 29 08:13:41 PM PDT 24 |
Jul 29 08:15:49 PM PDT 24 |
3256423224 ps |
| T1213 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3522830752 |
|
|
Jul 29 08:17:45 PM PDT 24 |
Jul 29 08:28:03 PM PDT 24 |
3855436588 ps |
| T808 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.680688396 |
|
|
Jul 29 08:45:30 PM PDT 24 |
Jul 29 08:53:18 PM PDT 24 |
4178578242 ps |
| T1214 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.4022281472 |
|
|
Jul 29 08:28:31 PM PDT 24 |
Jul 29 09:26:54 PM PDT 24 |
15461399880 ps |
| T1215 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2598733153 |
|
|
Jul 29 08:35:35 PM PDT 24 |
Jul 29 09:19:16 PM PDT 24 |
12212106892 ps |
| T1216 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3694292605 |
|
|
Jul 29 08:32:46 PM PDT 24 |
Jul 29 08:42:23 PM PDT 24 |
4476482823 ps |
| T245 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.348669964 |
|
|
Jul 29 08:28:01 PM PDT 24 |
Jul 29 10:00:00 PM PDT 24 |
49928307812 ps |
| T1217 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2271520891 |
|
|
Jul 29 08:32:40 PM PDT 24 |
Jul 29 08:40:40 PM PDT 24 |
3072753548 ps |
| T1218 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2100722478 |
|
|
Jul 29 08:34:14 PM PDT 24 |
Jul 29 10:08:37 PM PDT 24 |
47565210168 ps |
| T1219 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2213829211 |
|
|
Jul 29 08:32:40 PM PDT 24 |
Jul 29 08:54:35 PM PDT 24 |
8176008164 ps |
| T1220 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1343276425 |
|
|
Jul 29 08:15:18 PM PDT 24 |
Jul 29 08:33:03 PM PDT 24 |
6478734480 ps |
| T1221 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1438975377 |
|
|
Jul 29 08:26:23 PM PDT 24 |
Jul 29 09:08:38 PM PDT 24 |
12032982680 ps |
| T1222 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2822962116 |
|
|
Jul 29 08:26:54 PM PDT 24 |
Jul 29 08:36:09 PM PDT 24 |
5429644432 ps |
| T1223 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2842409329 |
|
|
Jul 29 08:41:50 PM PDT 24 |
Jul 29 09:05:55 PM PDT 24 |
8810210632 ps |
| T1224 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.1135682756 |
|
|
Jul 29 08:14:42 PM PDT 24 |
Jul 29 08:30:32 PM PDT 24 |
6010880108 ps |
| T1225 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.4281189351 |
|
|
Jul 29 08:16:48 PM PDT 24 |
Jul 29 08:28:18 PM PDT 24 |
4281790015 ps |
| T1226 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3182091015 |
|
|
Jul 29 08:32:05 PM PDT 24 |
Jul 29 08:35:44 PM PDT 24 |
2792242091 ps |
| T1227 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.638090866 |
|
|
Jul 29 08:30:03 PM PDT 24 |
Jul 29 08:35:33 PM PDT 24 |
3202303369 ps |
| T534 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.383905938 |
|
|
Jul 29 08:27:59 PM PDT 24 |
Jul 29 08:43:41 PM PDT 24 |
4365783160 ps |
| T1228 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2734033400 |
|
|
Jul 29 08:15:25 PM PDT 24 |
Jul 29 08:25:40 PM PDT 24 |
3902897742 ps |
| T1229 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3577763258 |
|
|
Jul 29 08:37:36 PM PDT 24 |
Jul 29 08:43:01 PM PDT 24 |
2968766389 ps |
| T1230 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2492116105 |
|
|
Jul 29 08:28:36 PM PDT 24 |
Jul 29 09:18:06 PM PDT 24 |
14245635644 ps |
| T1231 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2875328538 |
|
|
Jul 29 08:40:40 PM PDT 24 |
Jul 29 08:48:23 PM PDT 24 |
6507539568 ps |
| T1232 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3573545912 |
|
|
Jul 29 08:26:46 PM PDT 24 |
Jul 29 08:34:51 PM PDT 24 |
4540309320 ps |
| T769 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.705133462 |
|
|
Jul 29 08:45:10 PM PDT 24 |
Jul 29 08:54:27 PM PDT 24 |
5646105680 ps |
| T161 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.985793019 |
|
|
Jul 29 08:34:02 PM PDT 24 |
Jul 29 08:38:55 PM PDT 24 |
3366166787 ps |
| T1233 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1261678129 |
|
|
Jul 29 08:15:54 PM PDT 24 |
Jul 29 09:49:43 PM PDT 24 |
50873652632 ps |
| T1234 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3781254148 |
|
|
Jul 29 08:17:30 PM PDT 24 |
Jul 29 08:21:01 PM PDT 24 |
3000936520 ps |
| T1235 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3034643931 |
|
|
Jul 29 08:48:10 PM PDT 24 |
Jul 29 08:54:16 PM PDT 24 |
4548248946 ps |
| T411 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3837925621 |
|
|
Jul 29 08:36:35 PM PDT 24 |
Jul 29 09:01:50 PM PDT 24 |
20355487064 ps |
| T826 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.3780042578 |
|
|
Jul 29 08:47:55 PM PDT 24 |
Jul 29 08:58:21 PM PDT 24 |
5911447272 ps |
| T1236 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2066687747 |
|
|
Jul 29 08:40:04 PM PDT 24 |
Jul 29 08:51:10 PM PDT 24 |
4754411146 ps |
| T1237 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.470969605 |
|
|
Jul 29 08:38:15 PM PDT 24 |
Jul 29 08:43:22 PM PDT 24 |
3589740184 ps |
| T54 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.552381266 |
|
|
Jul 29 08:30:53 PM PDT 24 |
Jul 29 08:36:23 PM PDT 24 |
4368843780 ps |
| T1238 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2181958301 |
|
|
Jul 29 08:32:25 PM PDT 24 |
Jul 29 08:44:42 PM PDT 24 |
7900882206 ps |
| T1239 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3794553317 |
|
|
Jul 29 08:15:31 PM PDT 24 |
Jul 29 08:18:11 PM PDT 24 |
2870110497 ps |
| T1240 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1353493325 |
|
|
Jul 29 08:31:44 PM PDT 24 |
Jul 29 08:54:47 PM PDT 24 |
11277533932 ps |
| T1241 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.3603152597 |
|
|
Jul 29 08:26:51 PM PDT 24 |
Jul 29 08:37:57 PM PDT 24 |
6207886816 ps |
| T78 |
/workspace/coverage/default/2.chip_jtag_mem_access.1191973994 |
|
|
Jul 29 08:29:44 PM PDT 24 |
Jul 29 08:59:09 PM PDT 24 |
13226359272 ps |
| T1242 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.892659749 |
|
|
Jul 29 08:16:47 PM PDT 24 |
Jul 29 08:54:14 PM PDT 24 |
11112375976 ps |
| T1243 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1956386903 |
|
|
Jul 29 08:29:30 PM PDT 24 |
Jul 29 09:20:34 PM PDT 24 |
15367436090 ps |
| T1244 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2727940240 |
|
|
Jul 29 08:31:14 PM PDT 24 |
Jul 29 08:41:06 PM PDT 24 |
4301539384 ps |
| T1245 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.372721125 |
|
|
Jul 29 08:16:52 PM PDT 24 |
Jul 29 08:23:16 PM PDT 24 |
3160737512 ps |
| T1246 |
/workspace/coverage/default/0.chip_sw_aes_idle.70569571 |
|
|
Jul 29 08:14:50 PM PDT 24 |
Jul 29 08:18:49 PM PDT 24 |
2301161320 ps |
| T816 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1350857388 |
|
|
Jul 29 08:50:46 PM PDT 24 |
Jul 29 08:57:28 PM PDT 24 |
3903458700 ps |
| T40 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.3157542868 |
|
|
Jul 29 08:28:12 PM PDT 24 |
Jul 29 08:34:42 PM PDT 24 |
2782087729 ps |
| T1247 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3901178310 |
|
|
Jul 29 08:27:23 PM PDT 24 |
Jul 29 08:37:57 PM PDT 24 |
4376737709 ps |
| T1248 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3038620748 |
|
|
Jul 29 08:15:42 PM PDT 24 |
Jul 29 08:29:13 PM PDT 24 |
5504191885 ps |
| T1249 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1054623874 |
|
|
Jul 29 08:38:59 PM PDT 24 |
Jul 29 08:45:01 PM PDT 24 |
3681968414 ps |
| T305 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2188500860 |
|
|
Jul 29 08:17:45 PM PDT 24 |
Jul 29 08:26:04 PM PDT 24 |
5882381664 ps |
| T1250 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.334189987 |
|
|
Jul 29 08:51:15 PM PDT 24 |
Jul 29 08:56:52 PM PDT 24 |
3182632304 ps |
| T342 |
/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2629609584 |
|
|
Jul 29 08:27:47 PM PDT 24 |
Jul 29 08:36:21 PM PDT 24 |
3894331924 ps |
| T1251 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2588480890 |
|
|
Jul 29 08:13:49 PM PDT 24 |
Jul 29 08:22:32 PM PDT 24 |
5325212711 ps |
| T1252 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2237440988 |
|
|
Jul 29 08:41:16 PM PDT 24 |
Jul 29 08:52:03 PM PDT 24 |
3904666224 ps |
| T1253 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4088064298 |
|
|
Jul 29 08:15:17 PM PDT 24 |
Jul 29 08:25:46 PM PDT 24 |
7264247392 ps |
| T1254 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.3796485070 |
|
|
Jul 29 08:45:24 PM PDT 24 |
Jul 29 08:55:36 PM PDT 24 |
5212976474 ps |
| T1255 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.3565598547 |
|
|
Jul 29 08:40:15 PM PDT 24 |
Jul 29 08:42:46 PM PDT 24 |
2469901674 ps |
| T1256 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1851874119 |
|
|
Jul 29 08:32:08 PM PDT 24 |
Jul 29 08:41:22 PM PDT 24 |
5528769512 ps |
| T367 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.359740932 |
|
|
Jul 29 08:16:05 PM PDT 24 |
Jul 29 08:22:30 PM PDT 24 |
6521752650 ps |
| T1257 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3173553991 |
|
|
Jul 29 08:49:03 PM PDT 24 |
Jul 29 08:54:27 PM PDT 24 |
3830690494 ps |
| T1258 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3658479424 |
|
|
Jul 29 08:25:40 PM PDT 24 |
Jul 29 08:29:18 PM PDT 24 |
3142865040 ps |
| T1259 |
/workspace/coverage/default/3.chip_tap_straps_dev.3468408650 |
|
|
Jul 29 08:40:28 PM PDT 24 |
Jul 29 08:43:17 PM PDT 24 |
3326845121 ps |
| T1260 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.2333307912 |
|
|
Jul 29 08:26:35 PM PDT 24 |
Jul 29 08:30:24 PM PDT 24 |
2419560784 ps |
| T1261 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3524991459 |
|
|
Jul 29 08:40:55 PM PDT 24 |
Jul 29 08:45:03 PM PDT 24 |
2813788900 ps |
| T130 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1096439921 |
|
|
Jul 29 08:18:59 PM PDT 24 |
Jul 29 08:25:48 PM PDT 24 |
5629791940 ps |
| T246 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1653520699 |
|
|
Jul 29 08:36:39 PM PDT 24 |
Jul 29 10:06:54 PM PDT 24 |
51736991696 ps |
| T1262 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2896126715 |
|
|
Jul 29 08:42:33 PM PDT 24 |
Jul 29 09:35:11 PM PDT 24 |
15238922926 ps |
| T323 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.3179928986 |
|
|
Jul 29 08:18:16 PM PDT 24 |
Jul 29 08:31:10 PM PDT 24 |
5375057760 ps |
| T1263 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1956632833 |
|
|
Jul 29 08:45:01 PM PDT 24 |
Jul 29 08:50:45 PM PDT 24 |
3409762036 ps |
| T1264 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2951111819 |
|
|
Jul 29 08:25:20 PM PDT 24 |
Jul 29 08:38:05 PM PDT 24 |
5624461920 ps |
| T800 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2697342020 |
|
|
Jul 29 08:49:25 PM PDT 24 |
Jul 29 08:58:05 PM PDT 24 |
4327608550 ps |
| T91 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2817406521 |
|
|
Jul 29 08:51:52 PM PDT 24 |
Jul 29 08:59:35 PM PDT 24 |
3988791800 ps |
| T1265 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.505985229 |
|
|
Jul 29 08:17:39 PM PDT 24 |
Jul 29 08:29:28 PM PDT 24 |
7159422180 ps |
| T1266 |
/workspace/coverage/default/1.chip_sw_hmac_enc.1124414121 |
|
|
Jul 29 08:29:21 PM PDT 24 |
Jul 29 08:34:30 PM PDT 24 |
2453690072 ps |
| T1267 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1323496807 |
|
|
Jul 29 08:28:50 PM PDT 24 |
Jul 29 09:20:34 PM PDT 24 |
11154474144 ps |
| T795 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.3781579668 |
|
|
Jul 29 08:47:43 PM PDT 24 |
Jul 29 09:02:21 PM PDT 24 |
5249314768 ps |
| T208 |
/workspace/coverage/default/1.chip_jtag_mem_access.1354964948 |
|
|
Jul 29 08:19:15 PM PDT 24 |
Jul 29 08:51:00 PM PDT 24 |
13621978000 ps |
| T34 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.105694134 |
|
|
Jul 29 08:33:29 PM PDT 24 |
Jul 29 08:38:37 PM PDT 24 |
2712710450 ps |
| T804 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.604162141 |
|
|
Jul 29 08:46:16 PM PDT 24 |
Jul 29 08:56:59 PM PDT 24 |
5541108620 ps |
| T1268 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2180320783 |
|
|
Jul 29 08:17:42 PM PDT 24 |
Jul 29 09:36:47 PM PDT 24 |
20521349400 ps |
| T1269 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3580435551 |
|
|
Jul 29 08:15:35 PM PDT 24 |
Jul 29 08:25:52 PM PDT 24 |
7681498876 ps |
| T1270 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3882783634 |
|
|
Jul 29 08:42:49 PM PDT 24 |
Jul 29 09:32:24 PM PDT 24 |
13967534774 ps |
| T1271 |
/workspace/coverage/default/1.chip_sw_power_idle_load.264862644 |
|
|
Jul 29 08:28:51 PM PDT 24 |
Jul 29 08:40:22 PM PDT 24 |
4801043940 ps |
| T1272 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1331040829 |
|
|
Jul 29 08:32:13 PM PDT 24 |
Jul 29 08:40:26 PM PDT 24 |
3646768892 ps |
| T766 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.3044870943 |
|
|
Jul 29 08:45:17 PM PDT 24 |
Jul 29 08:55:41 PM PDT 24 |
6315766388 ps |
| T304 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3470747750 |
|
|
Jul 29 08:16:59 PM PDT 24 |
Jul 29 08:32:01 PM PDT 24 |
10525785090 ps |
| T1273 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1423968646 |
|
|
Jul 29 08:14:41 PM PDT 24 |
Jul 29 08:21:28 PM PDT 24 |
3657721298 ps |
| T820 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1199336264 |
|
|
Jul 29 08:48:24 PM PDT 24 |
Jul 29 08:54:38 PM PDT 24 |
3843661218 ps |
| T1274 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1533808696 |
|
|
Jul 29 08:33:38 PM PDT 24 |
Jul 29 08:37:24 PM PDT 24 |
2830507724 ps |
| T1275 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.908642625 |
|
|
Jul 29 08:30:31 PM PDT 24 |
Jul 29 11:29:08 PM PDT 24 |
65200284893 ps |
| T1276 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.3324504053 |
|
|
Jul 29 08:30:52 PM PDT 24 |
Jul 29 08:36:26 PM PDT 24 |
3105469470 ps |
| T1277 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2638032851 |
|
|
Jul 29 08:39:30 PM PDT 24 |
Jul 29 08:49:34 PM PDT 24 |
3939234068 ps |
| T1278 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.3132579625 |
|
|
Jul 29 08:26:41 PM PDT 24 |
Jul 29 08:31:00 PM PDT 24 |
2353189390 ps |
| T802 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.937246609 |
|
|
Jul 29 08:45:02 PM PDT 24 |
Jul 29 08:52:01 PM PDT 24 |
3834731992 ps |
| T1279 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.3225963422 |
|
|
Jul 29 08:33:00 PM PDT 24 |
Jul 29 08:42:51 PM PDT 24 |
3973717820 ps |
| T1280 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.763071539 |
|
|
Jul 29 08:24:28 PM PDT 24 |
Jul 29 08:29:24 PM PDT 24 |
2560462816 ps |
| T1281 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3551569878 |
|
|
Jul 29 08:36:53 PM PDT 24 |
Jul 29 08:43:06 PM PDT 24 |
6277275980 ps |
| T1282 |
/workspace/coverage/default/2.rom_e2e_smoke.745395525 |
|
|
Jul 29 08:46:04 PM PDT 24 |
Jul 29 09:45:41 PM PDT 24 |
15215114810 ps |
| T1283 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.336318750 |
|
|
Jul 29 08:33:26 PM PDT 24 |
Jul 29 08:38:49 PM PDT 24 |
4868865200 ps |
| T823 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2471063928 |
|
|
Jul 29 08:49:22 PM PDT 24 |
Jul 29 09:01:29 PM PDT 24 |
5384609010 ps |
| T1284 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1167131871 |
|
|
Jul 29 08:18:51 PM PDT 24 |
Jul 29 08:22:56 PM PDT 24 |
2796494460 ps |
| T1285 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3219260820 |
|
|
Jul 29 08:44:55 PM PDT 24 |
Jul 29 09:00:17 PM PDT 24 |
12986751137 ps |
| T817 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2655967303 |
|
|
Jul 29 08:48:09 PM PDT 24 |
Jul 29 08:54:21 PM PDT 24 |
3935351536 ps |
| T306 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1132066228 |
|
|
Jul 29 08:39:10 PM PDT 24 |
Jul 29 08:46:10 PM PDT 24 |
3987431166 ps |
| T86 |
/workspace/coverage/default/2.chip_jtag_csr_rw.1473220927 |
|
|
Jul 29 08:30:04 PM PDT 24 |
Jul 29 08:55:56 PM PDT 24 |
11989827347 ps |
| T1286 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1974292490 |
|
|
Jul 29 08:35:23 PM PDT 24 |
Jul 29 08:41:18 PM PDT 24 |
3118340715 ps |
| T1287 |
/workspace/coverage/default/0.chip_tap_straps_rma.1073786890 |
|
|
Jul 29 08:14:34 PM PDT 24 |
Jul 29 08:20:06 PM PDT 24 |
4271939273 ps |
| T1288 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.501302880 |
|
|
Jul 29 08:37:22 PM PDT 24 |
Jul 29 09:03:21 PM PDT 24 |
10787158292 ps |
| T1289 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2751574245 |
|
|
Jul 29 08:14:46 PM PDT 24 |
Jul 29 08:31:56 PM PDT 24 |
10130877888 ps |
| T1290 |
/workspace/coverage/default/1.rom_e2e_smoke.3643504503 |
|
|
Jul 29 08:37:02 PM PDT 24 |
Jul 29 09:34:58 PM PDT 24 |
15498258804 ps |
| T1291 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2313694061 |
|
|
Jul 29 08:51:18 PM PDT 24 |
Jul 29 08:57:43 PM PDT 24 |
3061651800 ps |
| T812 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.1223056698 |
|
|
Jul 29 08:45:50 PM PDT 24 |
Jul 29 08:55:22 PM PDT 24 |
5449751744 ps |
| T1292 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2011575544 |
|
|
Jul 29 08:27:04 PM PDT 24 |
Jul 29 08:33:52 PM PDT 24 |
18005019780 ps |
| T1293 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.4248814848 |
|
|
Jul 29 08:39:55 PM PDT 24 |
Jul 29 08:44:57 PM PDT 24 |
3473566372 ps |
| T141 |
/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.551772071 |
|
|
Jul 29 08:16:45 PM PDT 24 |
Jul 29 09:10:45 PM PDT 24 |
19730723130 ps |
| T1294 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.893418483 |
|
|
Jul 29 08:15:26 PM PDT 24 |
Jul 29 08:52:16 PM PDT 24 |
23874252500 ps |
| T192 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3756958022 |
|
|
Jul 29 08:13:52 PM PDT 24 |
Jul 29 09:43:18 PM PDT 24 |
45135174180 ps |
| T1295 |
/workspace/coverage/default/3.chip_tap_straps_prod.3945362838 |
|
|
Jul 29 08:40:42 PM PDT 24 |
Jul 29 08:43:31 PM PDT 24 |
2774326070 ps |
| T1296 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1583256083 |
|
|
Jul 29 08:40:34 PM PDT 24 |
Jul 29 08:44:02 PM PDT 24 |
3540413098 ps |
| T1297 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.3205659959 |
|
|
Jul 29 08:13:45 PM PDT 24 |
Jul 29 08:16:55 PM PDT 24 |
2730348900 ps |
| T1298 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.589753138 |
|
|
Jul 29 08:35:42 PM PDT 24 |
Jul 29 08:43:26 PM PDT 24 |
7223757671 ps |
| T1299 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2808949841 |
|
|
Jul 29 08:47:58 PM PDT 24 |
Jul 29 08:55:20 PM PDT 24 |
3686627814 ps |
| T1300 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2690798210 |
|
|
Jul 29 08:30:14 PM PDT 24 |
Jul 29 10:04:09 PM PDT 24 |
23651369382 ps |
| T1301 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3683697385 |
|
|
Jul 29 08:38:03 PM PDT 24 |
Jul 29 08:51:02 PM PDT 24 |
8109881736 ps |
| T1302 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1077594077 |
|
|
Jul 29 08:42:42 PM PDT 24 |
Jul 29 08:53:09 PM PDT 24 |
6006909240 ps |
| T302 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3647198102 |
|
|
Jul 29 08:19:11 PM PDT 24 |
Jul 29 08:23:55 PM PDT 24 |
3470165506 ps |
| T1303 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2408343517 |
|
|
Jul 29 08:17:01 PM PDT 24 |
Jul 29 08:27:58 PM PDT 24 |
5259121492 ps |
| T1304 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3049344837 |
|
|
Jul 29 08:29:43 PM PDT 24 |
Jul 29 09:31:49 PM PDT 24 |
14978301214 ps |
| T1305 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.4037682145 |
|
|
Jul 29 08:17:36 PM PDT 24 |
Jul 29 08:21:29 PM PDT 24 |
3005241569 ps |
| T1306 |
/workspace/coverage/default/0.chip_sw_aes_entropy.139635649 |
|
|
Jul 29 08:13:53 PM PDT 24 |
Jul 29 08:17:43 PM PDT 24 |
3034306268 ps |
| T1307 |
/workspace/coverage/default/1.chip_sw_example_concurrency.2244235761 |
|
|
Jul 29 08:28:00 PM PDT 24 |
Jul 29 08:31:51 PM PDT 24 |
2327941448 ps |
| T1308 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.4110822035 |
|
|
Jul 29 08:25:17 PM PDT 24 |
Jul 29 08:37:10 PM PDT 24 |
4384550156 ps |
| T1309 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1801838435 |
|
|
Jul 29 08:41:14 PM PDT 24 |
Jul 29 08:46:20 PM PDT 24 |
6907057776 ps |
| T28 |
/workspace/coverage/default/2.chip_sw_gpio.3438498021 |
|
|
Jul 29 08:34:24 PM PDT 24 |
Jul 29 08:42:36 PM PDT 24 |
4156308686 ps |
| T1310 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2979186039 |
|
|
Jul 29 08:27:39 PM PDT 24 |
Jul 29 08:38:51 PM PDT 24 |
4000317580 ps |
| T1311 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.3606164653 |
|
|
Jul 29 08:44:58 PM PDT 24 |
Jul 29 08:54:41 PM PDT 24 |
5146535836 ps |
| T1312 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.19140388 |
|
|
Jul 29 08:26:39 PM PDT 24 |
Jul 29 08:44:34 PM PDT 24 |
5448859747 ps |
| T1313 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1663117749 |
|
|
Jul 29 08:16:06 PM PDT 24 |
Jul 29 08:24:05 PM PDT 24 |
18449043760 ps |
| T803 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.212657544 |
|
|
Jul 29 08:50:33 PM PDT 24 |
Jul 29 08:58:59 PM PDT 24 |
5232625528 ps |
| T1314 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.464694629 |
|
|
Jul 29 08:35:17 PM PDT 24 |
Jul 29 09:10:03 PM PDT 24 |
13677824650 ps |
| T1315 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2416249193 |
|
|
Jul 29 08:47:59 PM PDT 24 |
Jul 29 08:56:45 PM PDT 24 |
4983913270 ps |
| T1316 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.3748925659 |
|
|
Jul 29 08:16:59 PM PDT 24 |
Jul 29 08:23:18 PM PDT 24 |
3460081966 ps |
| T1317 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2948903240 |
|
|
Jul 29 08:27:44 PM PDT 24 |
Jul 29 08:37:52 PM PDT 24 |
5204632553 ps |
| T1318 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2321308748 |
|
|
Jul 29 08:14:25 PM PDT 24 |
Jul 29 09:22:56 PM PDT 24 |
16720717946 ps |
| T1319 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.3046961008 |
|
|
Jul 29 08:40:10 PM PDT 24 |
Jul 29 08:44:01 PM PDT 24 |
2779853114 ps |
| T1320 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3246795038 |
|
|
Jul 29 08:25:42 PM PDT 24 |
Jul 29 08:28:43 PM PDT 24 |
2588584926 ps |
| T1321 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3214703348 |
|
|
Jul 29 08:40:24 PM PDT 24 |
Jul 29 08:53:10 PM PDT 24 |
7621649182 ps |
| T1322 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.2692596261 |
|
|
Jul 29 08:15:44 PM PDT 24 |
Jul 29 08:19:09 PM PDT 24 |
2636215790 ps |
| T1323 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3758875387 |
|
|
Jul 29 08:50:08 PM PDT 24 |
Jul 29 08:58:31 PM PDT 24 |
5452770120 ps |
| T785 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2645299729 |
|
|
Jul 29 08:47:07 PM PDT 24 |
Jul 29 08:53:14 PM PDT 24 |
3875039800 ps |
| T329 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.735879007 |
|
|
Jul 29 08:27:47 PM PDT 24 |
Jul 29 09:00:55 PM PDT 24 |
13160918816 ps |
| T55 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3013573730 |
|
|
Jul 29 08:14:00 PM PDT 24 |
Jul 29 08:18:30 PM PDT 24 |
3915944224 ps |
| T1324 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.1297438720 |
|
|
Jul 29 08:16:21 PM PDT 24 |
Jul 29 08:28:49 PM PDT 24 |
4427994256 ps |
| T1325 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2100532760 |
|
|
Jul 29 08:28:15 PM PDT 24 |
Jul 29 08:51:30 PM PDT 24 |
8993794097 ps |
| T790 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.2656295275 |
|
|
Jul 29 08:44:00 PM PDT 24 |
Jul 29 08:53:33 PM PDT 24 |
5536315532 ps |
| T788 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1788479260 |
|
|
Jul 29 08:50:24 PM PDT 24 |
Jul 29 09:00:11 PM PDT 24 |
5549961972 ps |
| T1326 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2445027426 |
|
|
Jul 29 08:15:54 PM PDT 24 |
Jul 29 08:24:37 PM PDT 24 |
3802731104 ps |
| T1327 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.65611489 |
|
|
Jul 29 08:17:46 PM PDT 24 |
Jul 29 08:25:37 PM PDT 24 |
4452984360 ps |
| T1328 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.2480736348 |
|
|
Jul 29 08:37:53 PM PDT 24 |
Jul 29 08:46:57 PM PDT 24 |
4146432600 ps |
| T1329 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3434201770 |
|
|
Jul 29 08:31:14 PM PDT 24 |
Jul 29 08:52:32 PM PDT 24 |
9603510608 ps |
| T1330 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3604234224 |
|
|
Jul 29 08:18:43 PM PDT 24 |
Jul 29 08:21:28 PM PDT 24 |
3251519072 ps |
| T801 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.506967579 |
|
|
Jul 29 08:49:49 PM PDT 24 |
Jul 29 08:58:12 PM PDT 24 |
3299611880 ps |
| T821 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.3523734499 |
|
|
Jul 29 08:46:51 PM PDT 24 |
Jul 29 08:59:20 PM PDT 24 |
5594259942 ps |
| T1331 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3241732684 |
|
|
Jul 29 08:47:47 PM PDT 24 |
Jul 29 08:55:18 PM PDT 24 |
3431990670 ps |
| T139 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1293033010 |
|
|
Jul 29 08:35:06 PM PDT 24 |
Jul 29 08:44:38 PM PDT 24 |
6083357480 ps |
| T1332 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.4231895554 |
|
|
Jul 29 08:38:02 PM PDT 24 |
Jul 29 08:46:25 PM PDT 24 |
6091302508 ps |
| T1333 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2254657266 |
|
|
Jul 29 08:29:21 PM PDT 24 |
Jul 29 10:10:16 PM PDT 24 |
24564936520 ps |
| T1334 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.752114501 |
|
|
Jul 29 08:29:10 PM PDT 24 |
Jul 29 09:40:03 PM PDT 24 |
15572808188 ps |
| T113 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1657767790 |
|
|
Jul 29 08:38:47 PM PDT 24 |
Jul 29 09:00:31 PM PDT 24 |
23684628392 ps |
| T1335 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1974748759 |
|
|
Jul 29 08:26:40 PM PDT 24 |
Jul 29 08:56:27 PM PDT 24 |
18627475915 ps |
| T266 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.2356793588 |
|
|
Jul 29 08:43:19 PM PDT 24 |
Jul 29 08:53:32 PM PDT 24 |
4724664924 ps |
| T1336 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3068009744 |
|
|
Jul 29 08:40:52 PM PDT 24 |
Jul 29 08:51:56 PM PDT 24 |
3715763880 ps |
| T746 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2179098780 |
|
|
Jul 29 08:15:46 PM PDT 24 |
Jul 29 08:29:39 PM PDT 24 |
4840045924 ps |
| T1337 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.263911034 |
|
|
Jul 29 08:40:17 PM PDT 24 |
Jul 29 08:58:09 PM PDT 24 |
8767991155 ps |
| T352 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.609453519 |
|
|
Jul 29 08:27:18 PM PDT 24 |
Jul 29 08:39:08 PM PDT 24 |
4517084762 ps |
| T1338 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3114615621 |
|
|
Jul 29 08:27:29 PM PDT 24 |
Jul 29 08:42:50 PM PDT 24 |
4834498960 ps |
| T431 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3979905104 |
|
|
Jul 29 08:27:23 PM PDT 24 |
Jul 29 09:01:31 PM PDT 24 |
21644322878 ps |
| T267 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1675788104 |
|
|
Jul 29 08:15:47 PM PDT 24 |
Jul 29 08:30:25 PM PDT 24 |
6811377520 ps |
| T1339 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2488100171 |
|
|
Jul 29 08:13:29 PM PDT 24 |
Jul 29 09:16:55 PM PDT 24 |
20345388053 ps |
| T791 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.3516688921 |
|
|
Jul 29 08:44:01 PM PDT 24 |
Jul 29 08:52:42 PM PDT 24 |
4683663896 ps |
| T1340 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2951853891 |
|
|
Jul 29 08:34:22 PM PDT 24 |
Jul 29 08:40:05 PM PDT 24 |
3468407430 ps |
| T1341 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3847232692 |
|
|
Jul 29 08:26:40 PM PDT 24 |
Jul 29 08:47:51 PM PDT 24 |
6531891570 ps |
| T1342 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.426823383 |
|
|
Jul 29 08:29:15 PM PDT 24 |
Jul 29 08:36:19 PM PDT 24 |
3495360384 ps |
| T1343 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.1421397394 |
|
|
Jul 29 08:16:53 PM PDT 24 |
Jul 29 08:36:39 PM PDT 24 |
4317031960 ps |
| T362 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.1048145236 |
|
|
Jul 29 08:14:44 PM PDT 24 |
Jul 29 08:21:32 PM PDT 24 |
3556614720 ps |
| T1344 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2489926898 |
|
|
Jul 29 08:30:21 PM PDT 24 |
Jul 29 10:11:48 PM PDT 24 |
23571409226 ps |
| T1345 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.2510116051 |
|
|
Jul 29 08:29:36 PM PDT 24 |
Jul 29 08:34:06 PM PDT 24 |
3584138391 ps |
| T1346 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3730574386 |
|
|
Jul 29 08:14:13 PM PDT 24 |
Jul 29 08:15:58 PM PDT 24 |
2197909707 ps |
| T1347 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2506354209 |
|
|
Jul 29 08:47:03 PM PDT 24 |
Jul 29 08:55:51 PM PDT 24 |
4365150632 ps |
| T1348 |
/workspace/coverage/default/1.chip_sival_flash_info_access.3070137611 |
|
|
Jul 29 08:26:58 PM PDT 24 |
Jul 29 08:32:48 PM PDT 24 |
2465603112 ps |
| T1349 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3239123733 |
|
|
Jul 29 08:42:20 PM PDT 24 |
Jul 29 08:46:47 PM PDT 24 |
2831226840 ps |
| T1350 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2887652814 |
|
|
Jul 29 08:27:44 PM PDT 24 |
Jul 29 08:40:14 PM PDT 24 |
12146819077 ps |
| T1351 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.117321193 |
|
|
Jul 29 08:25:37 PM PDT 24 |
Jul 29 08:36:50 PM PDT 24 |
3801875332 ps |
| T317 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.275561928 |
|
|
Jul 29 08:48:36 PM PDT 24 |
Jul 29 08:58:40 PM PDT 24 |
4720587848 ps |
| T1352 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.211677347 |
|
|
Jul 29 08:34:13 PM PDT 24 |
Jul 29 08:41:55 PM PDT 24 |
6714399048 ps |
| T1353 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1801627019 |
|
|
Jul 29 08:17:11 PM PDT 24 |
Jul 29 08:20:31 PM PDT 24 |
3055968933 ps |
| T1354 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2782021219 |
|
|
Jul 29 08:28:16 PM PDT 24 |
Jul 29 09:02:53 PM PDT 24 |
27014225694 ps |
| T348 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.74544617 |
|
|
Jul 29 08:32:18 PM PDT 24 |
Jul 29 08:40:19 PM PDT 24 |
3392817736 ps |
| T794 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1448303239 |
|
|
Jul 29 08:45:12 PM PDT 24 |
Jul 29 08:52:07 PM PDT 24 |
4016331960 ps |
| T1355 |
/workspace/coverage/default/2.chip_sw_flash_init.2302711839 |
|
|
Jul 29 08:33:24 PM PDT 24 |
Jul 29 09:06:24 PM PDT 24 |
23559288012 ps |
| T1356 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.967754676 |
|
|
Jul 29 08:30:36 PM PDT 24 |
Jul 29 08:35:11 PM PDT 24 |
2521961237 ps |
| T1357 |
/workspace/coverage/default/0.chip_sw_flash_init.2428714403 |
|
|
Jul 29 08:14:43 PM PDT 24 |
Jul 29 08:53:50 PM PDT 24 |
16978771014 ps |
| T1358 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1630837365 |
|
|
Jul 29 08:32:34 PM PDT 24 |
Jul 29 08:36:45 PM PDT 24 |
3829918971 ps |
| T827 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1529311979 |
|
|
Jul 29 08:49:08 PM PDT 24 |
Jul 29 08:55:29 PM PDT 24 |
3329299238 ps |
| T1359 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2099907825 |
|
|
Jul 29 08:15:59 PM PDT 24 |
Jul 29 08:19:04 PM PDT 24 |
2827522678 ps |
| T159 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.44039742 |
|
|
Jul 29 08:32:00 PM PDT 24 |
Jul 29 08:44:06 PM PDT 24 |
3808245384 ps |
| T371 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2106885075 |
|
|
Jul 29 08:48:51 PM PDT 24 |
Jul 29 08:53:59 PM PDT 24 |
3335775618 ps |
| T1360 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.766177212 |
|
|
Jul 29 08:32:27 PM PDT 24 |
Jul 29 08:36:55 PM PDT 24 |
2749406160 ps |
| T1361 |
/workspace/coverage/default/1.chip_tap_straps_dev.820853631 |
|
|
Jul 29 08:29:44 PM PDT 24 |
Jul 29 08:34:52 PM PDT 24 |
3872409344 ps |
| T49 |
/workspace/coverage/default/0.chip_jtag_csr_rw.1980270906 |
|
|
Jul 29 08:08:42 PM PDT 24 |
Jul 29 08:26:20 PM PDT 24 |
11370079889 ps |
| T1362 |
/workspace/coverage/default/0.chip_sw_example_rom.4218414084 |
|
|
Jul 29 08:12:39 PM PDT 24 |
Jul 29 08:14:38 PM PDT 24 |
2625754292 ps |
| T1363 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3411632889 |
|
|
Jul 29 08:27:46 PM PDT 24 |
Jul 29 08:50:05 PM PDT 24 |
6646369272 ps |
| T1364 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.4029580894 |
|
|
Jul 29 08:37:02 PM PDT 24 |
Jul 29 08:47:38 PM PDT 24 |
3946136964 ps |
| T1365 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.284092253 |
|
|
Jul 29 08:37:20 PM PDT 24 |
Jul 29 08:50:18 PM PDT 24 |
7771490870 ps |
| T1366 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1549967759 |
|
|
Jul 29 08:15:33 PM PDT 24 |
Jul 29 08:25:48 PM PDT 24 |
8483029547 ps |
| T341 |
/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2006873462 |
|
|
Jul 29 08:38:25 PM PDT 24 |
Jul 29 08:46:37 PM PDT 24 |
3485855332 ps |
| T1367 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1010472438 |
|
|
Jul 29 08:33:45 PM PDT 24 |
Jul 29 08:45:19 PM PDT 24 |
4244372972 ps |
| T52 |
/workspace/coverage/default/2.chip_sw_alert_test.2855677046 |
|
|
Jul 29 08:33:24 PM PDT 24 |
Jul 29 08:38:47 PM PDT 24 |
2674067420 ps |
| T1368 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1316062768 |
|
|
Jul 29 08:25:46 PM PDT 24 |
Jul 29 08:30:13 PM PDT 24 |
3254620072 ps |
| T1369 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.136000346 |
|
|
Jul 29 08:16:14 PM PDT 24 |
Jul 29 08:33:46 PM PDT 24 |
5588677733 ps |
| T1370 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.3659357698 |
|
|
Jul 29 08:32:04 PM PDT 24 |
Jul 29 08:37:08 PM PDT 24 |
2894067660 ps |
| T1371 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3091373140 |
|
|
Jul 29 08:13:52 PM PDT 24 |
Jul 29 08:23:05 PM PDT 24 |
4434706380 ps |
| T724 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.178616137 |
|
|
Jul 29 08:45:45 PM PDT 24 |
Jul 29 08:55:03 PM PDT 24 |
4746174750 ps |
| T1372 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.59064141 |
|
|
Jul 29 08:15:01 PM PDT 24 |
Jul 29 08:46:41 PM PDT 24 |
16580155844 ps |
| T1373 |
/workspace/coverage/default/0.chip_sw_hmac_oneshot.1229520051 |
|
|
Jul 29 08:16:43 PM PDT 24 |
Jul 29 08:21:13 PM PDT 24 |
2782978696 ps |