| T56 |
/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.195485443 |
|
|
Jul 29 08:14:54 PM PDT 24 |
Jul 29 08:19:58 PM PDT 24 |
3940776371 ps |
| T1065 |
/workspace/coverage/default/2.chip_tap_straps_prod.3738691364 |
|
|
Jul 29 08:39:01 PM PDT 24 |
Jul 29 08:52:36 PM PDT 24 |
7950270952 ps |
| T1066 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.1111818628 |
|
|
Jul 29 08:25:49 PM PDT 24 |
Jul 29 08:30:37 PM PDT 24 |
2656013630 ps |
| T1067 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.2336643699 |
|
|
Jul 29 08:39:14 PM PDT 24 |
Jul 29 08:54:56 PM PDT 24 |
5685347766 ps |
| T1068 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3912291924 |
|
|
Jul 29 08:17:35 PM PDT 24 |
Jul 29 08:28:08 PM PDT 24 |
7516482120 ps |
| T278 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.605965988 |
|
|
Jul 29 08:27:59 PM PDT 24 |
Jul 29 08:42:14 PM PDT 24 |
6070912792 ps |
| T280 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.2123875640 |
|
|
Jul 29 08:27:15 PM PDT 24 |
Jul 29 08:34:12 PM PDT 24 |
4079704446 ps |
| T281 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.535340302 |
|
|
Jul 29 08:17:57 PM PDT 24 |
Jul 29 08:24:37 PM PDT 24 |
3550444240 ps |
| T282 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3332128960 |
|
|
Jul 29 08:15:37 PM PDT 24 |
Jul 29 08:25:02 PM PDT 24 |
6974893784 ps |
| T283 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3386266725 |
|
|
Jul 29 08:48:29 PM PDT 24 |
Jul 29 08:54:03 PM PDT 24 |
3722727480 ps |
| T284 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1517914749 |
|
|
Jul 29 08:18:32 PM PDT 24 |
Jul 29 08:26:14 PM PDT 24 |
6652336320 ps |
| T285 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.1929401953 |
|
|
Jul 29 08:44:45 PM PDT 24 |
Jul 29 08:54:57 PM PDT 24 |
5238625352 ps |
| T286 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3230293285 |
|
|
Jul 29 08:44:53 PM PDT 24 |
Jul 29 08:50:48 PM PDT 24 |
4318108230 ps |
| T287 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.1883371999 |
|
|
Jul 29 08:36:30 PM PDT 24 |
Jul 29 08:53:45 PM PDT 24 |
6284861600 ps |
| T288 |
/workspace/coverage/default/0.chip_sw_hmac_enc.2237207193 |
|
|
Jul 29 08:22:29 PM PDT 24 |
Jul 29 08:28:19 PM PDT 24 |
3002535078 ps |
| T1069 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.3454303761 |
|
|
Jul 29 08:39:50 PM PDT 24 |
Jul 29 09:52:23 PM PDT 24 |
15139410900 ps |
| T222 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3934271840 |
|
|
Jul 29 08:36:27 PM PDT 24 |
Jul 29 08:43:15 PM PDT 24 |
3231139352 ps |
| T1070 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3328216774 |
|
|
Jul 29 08:49:35 PM PDT 24 |
Jul 29 08:56:48 PM PDT 24 |
5606778022 ps |
| T1071 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.756646250 |
|
|
Jul 29 08:41:30 PM PDT 24 |
Jul 29 08:45:43 PM PDT 24 |
2702872206 ps |
| T1072 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2405747964 |
|
|
Jul 29 08:34:50 PM PDT 24 |
Jul 29 09:12:49 PM PDT 24 |
30616047592 ps |
| T1073 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1623456616 |
|
|
Jul 29 08:36:57 PM PDT 24 |
Jul 29 08:43:39 PM PDT 24 |
3312637016 ps |
| T1074 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3957382197 |
|
|
Jul 29 08:13:31 PM PDT 24 |
Jul 29 08:36:50 PM PDT 24 |
9102732528 ps |
| T799 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2658446476 |
|
|
Jul 29 08:46:45 PM PDT 24 |
Jul 29 08:51:42 PM PDT 24 |
3780865600 ps |
| T1075 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2703477912 |
|
|
Jul 29 08:29:48 PM PDT 24 |
Jul 29 09:36:38 PM PDT 24 |
15310600216 ps |
| T251 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.935686419 |
|
|
Jul 29 08:38:12 PM PDT 24 |
Jul 29 08:52:33 PM PDT 24 |
6940666532 ps |
| T351 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3257861103 |
|
|
Jul 29 08:29:03 PM PDT 24 |
Jul 29 08:41:01 PM PDT 24 |
4136000176 ps |
| T264 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.1662996137 |
|
|
Jul 29 08:44:58 PM PDT 24 |
Jul 29 08:56:54 PM PDT 24 |
5812332400 ps |
| T1076 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.2077419726 |
|
|
Jul 29 08:30:26 PM PDT 24 |
Jul 29 09:32:38 PM PDT 24 |
15455424448 ps |
| T1077 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1588092430 |
|
|
Jul 29 08:32:27 PM PDT 24 |
Jul 29 08:41:42 PM PDT 24 |
3954437864 ps |
| T167 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1252010825 |
|
|
Jul 29 08:32:40 PM PDT 24 |
Jul 29 08:36:52 PM PDT 24 |
2975173501 ps |
| T133 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3333129319 |
|
|
Jul 29 08:41:10 PM PDT 24 |
Jul 29 09:00:30 PM PDT 24 |
9996025336 ps |
| T365 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.1540890110 |
|
|
Jul 29 08:13:58 PM PDT 24 |
Jul 29 11:31:39 PM PDT 24 |
64809108728 ps |
| T1078 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1466482110 |
|
|
Jul 29 08:28:17 PM PDT 24 |
Jul 29 08:41:02 PM PDT 24 |
5112250552 ps |
| T205 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3351165775 |
|
|
Jul 29 08:14:26 PM PDT 24 |
Jul 29 08:22:08 PM PDT 24 |
4590895747 ps |
| T1079 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.817354818 |
|
|
Jul 29 08:27:47 PM PDT 24 |
Jul 29 08:43:02 PM PDT 24 |
8725478588 ps |
| T1080 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1382462770 |
|
|
Jul 29 08:44:12 PM PDT 24 |
Jul 29 09:14:10 PM PDT 24 |
8481035548 ps |
| T194 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3487410502 |
|
|
Jul 29 08:30:37 PM PDT 24 |
Jul 29 08:37:13 PM PDT 24 |
4611458408 ps |
| T405 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4066767090 |
|
|
Jul 29 08:51:11 PM PDT 24 |
Jul 29 08:58:05 PM PDT 24 |
3279928570 ps |
| T238 |
/workspace/coverage/default/1.chip_sw_flash_init.1703034110 |
|
|
Jul 29 08:26:01 PM PDT 24 |
Jul 29 08:58:14 PM PDT 24 |
22177592254 ps |
| T355 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.4127883895 |
|
|
Jul 29 08:14:42 PM PDT 24 |
Jul 29 08:19:04 PM PDT 24 |
3682847256 ps |
| T1081 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1494679196 |
|
|
Jul 29 08:32:58 PM PDT 24 |
Jul 29 08:54:57 PM PDT 24 |
9161712314 ps |
| T1082 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1995296870 |
|
|
Jul 29 08:35:01 PM PDT 24 |
Jul 29 08:44:06 PM PDT 24 |
4773174298 ps |
| T1083 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3933515737 |
|
|
Jul 29 08:29:20 PM PDT 24 |
Jul 29 08:40:01 PM PDT 24 |
6952925120 ps |
| T9 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3561653312 |
|
|
Jul 29 08:24:46 PM PDT 24 |
Jul 29 08:29:42 PM PDT 24 |
3337474017 ps |
| T1084 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.96675710 |
|
|
Jul 29 08:28:10 PM PDT 24 |
Jul 29 09:01:02 PM PDT 24 |
8826543812 ps |
| T836 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3953548000 |
|
|
Jul 29 08:49:43 PM PDT 24 |
Jul 29 08:55:07 PM PDT 24 |
3678348560 ps |
| T1085 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3529903818 |
|
|
Jul 29 08:29:30 PM PDT 24 |
Jul 29 09:22:40 PM PDT 24 |
20321783053 ps |
| T703 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.4087564990 |
|
|
Jul 29 08:28:54 PM PDT 24 |
Jul 29 08:33:00 PM PDT 24 |
2470397162 ps |
| T1086 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1243940829 |
|
|
Jul 29 08:15:26 PM PDT 24 |
Jul 29 08:25:01 PM PDT 24 |
5596087928 ps |
| T1087 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1636263188 |
|
|
Jul 29 08:29:18 PM PDT 24 |
Jul 29 08:48:56 PM PDT 24 |
6921853400 ps |
| T1088 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2603319484 |
|
|
Jul 29 08:15:44 PM PDT 24 |
Jul 29 08:44:25 PM PDT 24 |
10994918676 ps |
| T1089 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2983659700 |
|
|
Jul 29 08:16:06 PM PDT 24 |
Jul 29 08:22:24 PM PDT 24 |
4245485520 ps |
| T1090 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.2944166904 |
|
|
Jul 29 08:30:53 PM PDT 24 |
Jul 29 08:55:22 PM PDT 24 |
6924005972 ps |
| T1091 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3773014612 |
|
|
Jul 29 08:44:19 PM PDT 24 |
Jul 29 08:52:41 PM PDT 24 |
3846601580 ps |
| T1092 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.1280542368 |
|
|
Jul 29 08:39:30 PM PDT 24 |
Jul 29 08:44:10 PM PDT 24 |
2459256450 ps |
| T1093 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.2770743335 |
|
|
Jul 29 08:29:32 PM PDT 24 |
Jul 29 08:48:14 PM PDT 24 |
6017991000 ps |
| T1094 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.3396767516 |
|
|
Jul 29 08:30:19 PM PDT 24 |
Jul 29 08:34:36 PM PDT 24 |
3035114526 ps |
| T1095 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1735597388 |
|
|
Jul 29 08:40:32 PM PDT 24 |
Jul 29 08:44:27 PM PDT 24 |
2496179618 ps |
| T459 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.2734880058 |
|
|
Jul 29 08:46:09 PM PDT 24 |
Jul 29 08:54:26 PM PDT 24 |
5441498158 ps |
| T1096 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.137381846 |
|
|
Jul 29 08:30:18 PM PDT 24 |
Jul 29 08:47:56 PM PDT 24 |
8768947444 ps |
| T1097 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.708511704 |
|
|
Jul 29 08:31:11 PM PDT 24 |
Jul 29 08:38:47 PM PDT 24 |
4720712916 ps |
| T51 |
/workspace/coverage/default/0.chip_sw_alert_test.3795770270 |
|
|
Jul 29 08:16:27 PM PDT 24 |
Jul 29 08:21:57 PM PDT 24 |
3262216200 ps |
| T247 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1165371775 |
|
|
Jul 29 08:15:03 PM PDT 24 |
Jul 29 11:28:49 PM PDT 24 |
256338147744 ps |
| T1098 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.980329603 |
|
|
Jul 29 08:29:23 PM PDT 24 |
Jul 29 08:40:35 PM PDT 24 |
4177654932 ps |
| T1099 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.55110645 |
|
|
Jul 29 08:37:20 PM PDT 24 |
Jul 29 08:44:01 PM PDT 24 |
3258006760 ps |
| T787 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.180186534 |
|
|
Jul 29 08:46:42 PM PDT 24 |
Jul 29 08:53:53 PM PDT 24 |
4170019214 ps |
| T1100 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2505026131 |
|
|
Jul 29 08:32:18 PM PDT 24 |
Jul 29 08:39:50 PM PDT 24 |
6014325440 ps |
| T1101 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.2950353179 |
|
|
Jul 29 08:17:55 PM PDT 24 |
Jul 29 08:49:50 PM PDT 24 |
8417093098 ps |
| T291 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2934939920 |
|
|
Jul 29 08:15:14 PM PDT 24 |
Jul 29 08:26:18 PM PDT 24 |
6146595192 ps |
| T233 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.137325844 |
|
|
Jul 29 08:15:21 PM PDT 24 |
Jul 29 09:03:52 PM PDT 24 |
11330291774 ps |
| T314 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1516032767 |
|
|
Jul 29 08:47:11 PM PDT 24 |
Jul 29 08:56:33 PM PDT 24 |
4683085802 ps |
| T1102 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.444139423 |
|
|
Jul 29 08:39:00 PM PDT 24 |
Jul 29 08:56:26 PM PDT 24 |
5561413700 ps |
| T1103 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2058227826 |
|
|
Jul 29 08:29:23 PM PDT 24 |
Jul 29 09:18:53 PM PDT 24 |
22931416260 ps |
| T370 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.185883129 |
|
|
Jul 29 08:46:14 PM PDT 24 |
Jul 29 08:54:10 PM PDT 24 |
4918435976 ps |
| T1104 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.4103670114 |
|
|
Jul 29 08:25:13 PM PDT 24 |
Jul 29 11:35:06 PM PDT 24 |
64738263108 ps |
| T77 |
/workspace/coverage/default/1.chip_jtag_csr_rw.2179773112 |
|
|
Jul 29 08:19:17 PM PDT 24 |
Jul 29 08:44:50 PM PDT 24 |
13954971875 ps |
| T1105 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3976430012 |
|
|
Jul 29 08:16:31 PM PDT 24 |
Jul 29 08:39:44 PM PDT 24 |
7080240139 ps |
| T1106 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3977958094 |
|
|
Jul 29 08:27:42 PM PDT 24 |
Jul 29 08:42:32 PM PDT 24 |
5441884434 ps |
| T1107 |
/workspace/coverage/default/0.chip_sw_edn_kat.3508928033 |
|
|
Jul 29 08:16:52 PM PDT 24 |
Jul 29 08:25:59 PM PDT 24 |
3092292344 ps |
| T818 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.3337392439 |
|
|
Jul 29 08:47:09 PM PDT 24 |
Jul 29 08:56:36 PM PDT 24 |
5385595384 ps |
| T1108 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.4084417630 |
|
|
Jul 29 08:30:12 PM PDT 24 |
Jul 29 08:50:21 PM PDT 24 |
7945941004 ps |
| T1109 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.928945527 |
|
|
Jul 29 08:14:17 PM PDT 24 |
Jul 29 08:24:27 PM PDT 24 |
4340455630 ps |
| T206 |
/workspace/coverage/default/2.chip_sw_power_virus.4059853124 |
|
|
Jul 29 08:41:47 PM PDT 24 |
Jul 29 09:02:21 PM PDT 24 |
5505548574 ps |
| T1110 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3761551887 |
|
|
Jul 29 08:28:05 PM PDT 24 |
Jul 30 12:05:45 AM PDT 24 |
77600435630 ps |
| T773 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.2800556305 |
|
|
Jul 29 08:47:11 PM PDT 24 |
Jul 29 08:56:41 PM PDT 24 |
4991811022 ps |
| T1111 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1906457349 |
|
|
Jul 29 08:37:04 PM PDT 24 |
Jul 29 08:48:27 PM PDT 24 |
4479736612 ps |
| T758 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3993273516 |
|
|
Jul 29 08:14:46 PM PDT 24 |
Jul 29 08:24:47 PM PDT 24 |
4729146307 ps |
| T1112 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.3564127071 |
|
|
Jul 29 08:15:14 PM PDT 24 |
Jul 29 09:21:58 PM PDT 24 |
18526462204 ps |
| T90 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2600784783 |
|
|
Jul 29 08:43:39 PM PDT 24 |
Jul 29 08:51:46 PM PDT 24 |
3615584808 ps |
| T1113 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1630895757 |
|
|
Jul 29 08:33:58 PM PDT 24 |
Jul 29 08:48:48 PM PDT 24 |
7542903665 ps |
| T1114 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2063444436 |
|
|
Jul 29 08:40:51 PM PDT 24 |
Jul 29 08:51:53 PM PDT 24 |
4562999808 ps |
| T315 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1096193336 |
|
|
Jul 29 08:46:56 PM PDT 24 |
Jul 29 08:53:02 PM PDT 24 |
3436772120 ps |
| T82 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.4038205711 |
|
|
Jul 29 08:14:55 PM PDT 24 |
Jul 29 08:32:31 PM PDT 24 |
9629433496 ps |
| T1115 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.3529560316 |
|
|
Jul 29 08:40:54 PM PDT 24 |
Jul 29 08:50:23 PM PDT 24 |
5129773240 ps |
| T1116 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.4202408562 |
|
|
Jul 29 08:28:23 PM PDT 24 |
Jul 29 08:33:20 PM PDT 24 |
2988633431 ps |
| T1117 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.2330793536 |
|
|
Jul 29 08:29:47 PM PDT 24 |
Jul 29 08:35:11 PM PDT 24 |
3696238170 ps |
| T824 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4185958062 |
|
|
Jul 29 08:43:01 PM PDT 24 |
Jul 29 08:49:28 PM PDT 24 |
3341776620 ps |
| T1118 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1006467904 |
|
|
Jul 29 08:15:25 PM PDT 24 |
Jul 29 11:11:43 PM PDT 24 |
59986417820 ps |
| T1119 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3024389864 |
|
|
Jul 29 08:46:02 PM PDT 24 |
Jul 29 09:22:34 PM PDT 24 |
13414844036 ps |
| T1120 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2536772773 |
|
|
Jul 29 08:40:23 PM PDT 24 |
Jul 29 08:47:55 PM PDT 24 |
3644163936 ps |
| T1121 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3800957022 |
|
|
Jul 29 08:34:29 PM PDT 24 |
Jul 29 08:50:08 PM PDT 24 |
6303303143 ps |
| T822 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2097671339 |
|
|
Jul 29 08:49:34 PM PDT 24 |
Jul 29 08:58:01 PM PDT 24 |
5963738624 ps |
| T1122 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.3205553893 |
|
|
Jul 29 08:33:55 PM PDT 24 |
Jul 29 08:40:18 PM PDT 24 |
3846344168 ps |
| T1123 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3799705880 |
|
|
Jul 29 08:42:25 PM PDT 24 |
Jul 29 08:52:55 PM PDT 24 |
5794009980 ps |
| T1124 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1853822443 |
|
|
Jul 29 08:16:33 PM PDT 24 |
Jul 29 08:38:08 PM PDT 24 |
5640401672 ps |
| T324 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.36132480 |
|
|
Jul 29 08:16:15 PM PDT 24 |
Jul 29 08:35:57 PM PDT 24 |
5593698864 ps |
| T1125 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2891150392 |
|
|
Jul 29 08:43:04 PM PDT 24 |
Jul 29 08:59:31 PM PDT 24 |
12131881571 ps |
| T10 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1604604462 |
|
|
Jul 29 08:13:38 PM PDT 24 |
Jul 29 08:18:58 PM PDT 24 |
3055040344 ps |
| T1126 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3351711863 |
|
|
Jul 29 08:40:54 PM PDT 24 |
Jul 29 08:44:25 PM PDT 24 |
2576630056 ps |
| T813 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3015498694 |
|
|
Jul 29 08:49:56 PM PDT 24 |
Jul 29 08:58:47 PM PDT 24 |
5153786692 ps |
| T764 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1000680610 |
|
|
Jul 29 08:48:37 PM PDT 24 |
Jul 29 08:59:19 PM PDT 24 |
6552905128 ps |
| T1127 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.789218572 |
|
|
Jul 29 08:29:50 PM PDT 24 |
Jul 29 08:39:04 PM PDT 24 |
5572492948 ps |
| T789 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3410613076 |
|
|
Jul 29 08:47:36 PM PDT 24 |
Jul 29 08:54:45 PM PDT 24 |
3745119008 ps |
| T1128 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.3389471299 |
|
|
Jul 29 08:40:31 PM PDT 24 |
Jul 29 08:48:29 PM PDT 24 |
11351484840 ps |
| T409 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.220602239 |
|
|
Jul 29 08:27:45 PM PDT 24 |
Jul 29 08:35:29 PM PDT 24 |
3503003680 ps |
| T252 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.4113185334 |
|
|
Jul 29 08:26:59 PM PDT 24 |
Jul 29 08:39:32 PM PDT 24 |
7069336236 ps |
| T1129 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.707175538 |
|
|
Jul 29 08:18:05 PM PDT 24 |
Jul 29 08:27:18 PM PDT 24 |
6445414448 ps |
| T303 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3053931570 |
|
|
Jul 29 08:29:01 PM PDT 24 |
Jul 29 08:40:33 PM PDT 24 |
6590554064 ps |
| T1130 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1943360356 |
|
|
Jul 29 08:39:48 PM PDT 24 |
Jul 29 09:33:13 PM PDT 24 |
24684036949 ps |
| T1131 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.4080390233 |
|
|
Jul 29 08:38:24 PM PDT 24 |
Jul 29 08:42:18 PM PDT 24 |
2680678980 ps |
| T1132 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4000789328 |
|
|
Jul 29 08:42:27 PM PDT 24 |
Jul 29 08:57:17 PM PDT 24 |
7486799654 ps |
| T1133 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2028154277 |
|
|
Jul 29 08:46:31 PM PDT 24 |
Jul 29 08:52:09 PM PDT 24 |
3639693800 ps |
| T1134 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3985937706 |
|
|
Jul 29 08:39:16 PM PDT 24 |
Jul 29 08:43:34 PM PDT 24 |
3309650883 ps |
| T1135 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.251114537 |
|
|
Jul 29 08:49:13 PM PDT 24 |
Jul 29 08:55:04 PM PDT 24 |
3416146748 ps |
| T1136 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3586475743 |
|
|
Jul 29 08:30:07 PM PDT 24 |
Jul 29 09:38:22 PM PDT 24 |
15098722078 ps |
| T747 |
/workspace/coverage/default/1.rom_raw_unlock.2340526837 |
|
|
Jul 29 08:30:34 PM PDT 24 |
Jul 29 08:35:27 PM PDT 24 |
5893989688 ps |
| T1137 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3793055415 |
|
|
Jul 29 08:29:20 PM PDT 24 |
Jul 29 08:56:24 PM PDT 24 |
8111582816 ps |
| T292 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1183850811 |
|
|
Jul 29 08:43:21 PM PDT 24 |
Jul 29 08:55:21 PM PDT 24 |
5419170034 ps |
| T1138 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3434991735 |
|
|
Jul 29 08:18:33 PM PDT 24 |
Jul 29 08:27:59 PM PDT 24 |
3419113240 ps |
| T1139 |
/workspace/coverage/default/1.rom_e2e_self_hash.955969391 |
|
|
Jul 29 08:31:49 PM PDT 24 |
Jul 29 10:04:30 PM PDT 24 |
26572804180 ps |
| T723 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.2073785600 |
|
|
Jul 29 08:50:12 PM PDT 24 |
Jul 29 09:00:16 PM PDT 24 |
4945246650 ps |
| T1140 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3181499239 |
|
|
Jul 29 08:33:26 PM PDT 24 |
Jul 29 08:46:26 PM PDT 24 |
5080694737 ps |
| T748 |
/workspace/coverage/default/0.rom_raw_unlock.1116272698 |
|
|
Jul 29 08:25:50 PM PDT 24 |
Jul 29 08:30:37 PM PDT 24 |
6195176593 ps |
| T699 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.826935120 |
|
|
Jul 29 08:35:27 PM PDT 24 |
Jul 29 08:45:19 PM PDT 24 |
3050427200 ps |
| T1141 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.3602120353 |
|
|
Jul 29 08:32:52 PM PDT 24 |
Jul 29 08:38:58 PM PDT 24 |
3040095040 ps |
| T1142 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.190442558 |
|
|
Jul 29 08:31:57 PM PDT 24 |
Jul 29 10:15:55 PM PDT 24 |
24687726688 ps |
| T1143 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.534903839 |
|
|
Jul 29 08:18:05 PM PDT 24 |
Jul 29 08:23:50 PM PDT 24 |
2977648066 ps |
| T83 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2732350795 |
|
|
Jul 29 08:35:41 PM PDT 24 |
Jul 29 09:00:00 PM PDT 24 |
12573238298 ps |
| T805 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3731385780 |
|
|
Jul 29 08:44:24 PM PDT 24 |
Jul 29 08:50:02 PM PDT 24 |
3590848140 ps |
| T1144 |
/workspace/coverage/default/0.rom_e2e_static_critical.3147428138 |
|
|
Jul 29 08:29:16 PM PDT 24 |
Jul 29 09:35:35 PM PDT 24 |
17027931210 ps |
| T815 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3802737293 |
|
|
Jul 29 08:46:49 PM PDT 24 |
Jul 29 08:53:45 PM PDT 24 |
4370272954 ps |
| T84 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.2431185671 |
|
|
Jul 29 08:29:56 PM PDT 24 |
Jul 29 08:34:44 PM PDT 24 |
3468561657 ps |
| T1145 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1487343964 |
|
|
Jul 29 08:44:28 PM PDT 24 |
Jul 29 09:59:55 PM PDT 24 |
18797701464 ps |
| T1146 |
/workspace/coverage/default/1.rom_keymgr_functest.458760506 |
|
|
Jul 29 08:31:17 PM PDT 24 |
Jul 29 08:41:31 PM PDT 24 |
3749427140 ps |
| T701 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.2774195302 |
|
|
Jul 29 08:16:33 PM PDT 24 |
Jul 29 08:24:56 PM PDT 24 |
2781796960 ps |
| T1147 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.272564730 |
|
|
Jul 29 08:37:23 PM PDT 24 |
Jul 29 08:55:19 PM PDT 24 |
7710652815 ps |
| T786 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1047449921 |
|
|
Jul 29 08:45:26 PM PDT 24 |
Jul 29 08:51:48 PM PDT 24 |
3796160312 ps |
| T243 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1974961147 |
|
|
Jul 29 08:33:10 PM PDT 24 |
Jul 29 08:42:37 PM PDT 24 |
4651059740 ps |
| T1148 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2463503124 |
|
|
Jul 29 08:16:26 PM PDT 24 |
Jul 29 08:21:17 PM PDT 24 |
3568154648 ps |
| T1149 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.528834138 |
|
|
Jul 29 08:43:18 PM PDT 24 |
Jul 29 08:52:37 PM PDT 24 |
7344458247 ps |
| T1150 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.323179940 |
|
|
Jul 29 08:25:34 PM PDT 24 |
Jul 29 08:32:19 PM PDT 24 |
3351379298 ps |
| T207 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1392616855 |
|
|
Jul 29 08:32:40 PM PDT 24 |
Jul 29 08:41:02 PM PDT 24 |
4778696764 ps |
| T1151 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3865901933 |
|
|
Jul 29 08:34:08 PM PDT 24 |
Jul 29 08:40:29 PM PDT 24 |
3234148268 ps |
| T1152 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.4168335735 |
|
|
Jul 29 08:34:26 PM PDT 24 |
Jul 29 08:56:54 PM PDT 24 |
7387271790 ps |
| T1153 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.4045644831 |
|
|
Jul 29 08:31:00 PM PDT 24 |
Jul 29 09:54:23 PM PDT 24 |
18172498777 ps |
| T1154 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.305482150 |
|
|
Jul 29 08:16:14 PM PDT 24 |
Jul 29 08:25:43 PM PDT 24 |
5277457772 ps |
| T293 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3347512730 |
|
|
Jul 29 08:16:19 PM PDT 24 |
Jul 29 08:25:50 PM PDT 24 |
5263058579 ps |
| T1155 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.4117789775 |
|
|
Jul 29 08:15:40 PM PDT 24 |
Jul 29 08:28:04 PM PDT 24 |
4864848040 ps |
| T37 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2807376498 |
|
|
Jul 29 08:15:47 PM PDT 24 |
Jul 29 08:25:34 PM PDT 24 |
5705416768 ps |
| T722 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3661373711 |
|
|
Jul 29 08:16:39 PM PDT 24 |
Jul 29 08:18:12 PM PDT 24 |
1878785023 ps |
| T1156 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.686108954 |
|
|
Jul 29 08:27:45 PM PDT 24 |
Jul 29 08:38:17 PM PDT 24 |
3718949300 ps |
| T1157 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.196879276 |
|
|
Jul 29 08:29:04 PM PDT 24 |
Jul 29 09:15:24 PM PDT 24 |
14657435828 ps |
| T1158 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1262672912 |
|
|
Jul 29 08:43:51 PM PDT 24 |
Jul 29 09:24:28 PM PDT 24 |
13473894100 ps |
| T1159 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.1451203356 |
|
|
Jul 29 08:46:02 PM PDT 24 |
Jul 29 09:45:51 PM PDT 24 |
16301011666 ps |
| T1160 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.161825928 |
|
|
Jul 29 08:45:30 PM PDT 24 |
Jul 29 08:52:49 PM PDT 24 |
4308943616 ps |
| T1161 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.3955856622 |
|
|
Jul 29 08:33:56 PM PDT 24 |
Jul 29 09:05:31 PM PDT 24 |
9613330958 ps |
| T115 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2743851592 |
|
|
Jul 29 08:17:54 PM PDT 24 |
Jul 29 08:21:26 PM PDT 24 |
2847434271 ps |
| T1162 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3680022256 |
|
|
Jul 29 08:28:31 PM PDT 24 |
Jul 29 08:33:43 PM PDT 24 |
3130033232 ps |
| T1163 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.2914265650 |
|
|
Jul 29 08:34:52 PM PDT 24 |
Jul 29 08:51:43 PM PDT 24 |
5684525246 ps |
| T1164 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2521785929 |
|
|
Jul 29 08:39:57 PM PDT 24 |
Jul 29 09:51:08 PM PDT 24 |
14891849992 ps |
| T235 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.33218441 |
|
|
Jul 29 08:15:12 PM PDT 24 |
Jul 29 09:24:09 PM PDT 24 |
17059426520 ps |
| T347 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1538064222 |
|
|
Jul 29 08:14:56 PM PDT 24 |
Jul 29 08:26:39 PM PDT 24 |
4648319600 ps |
| T339 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3544699050 |
|
|
Jul 29 08:15:40 PM PDT 24 |
Jul 29 08:24:48 PM PDT 24 |
4076787816 ps |
| T1165 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2138787457 |
|
|
Jul 29 08:36:46 PM PDT 24 |
Jul 29 08:46:06 PM PDT 24 |
3787317026 ps |
| T183 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1620573081 |
|
|
Jul 29 08:27:13 PM PDT 24 |
Jul 29 08:31:02 PM PDT 24 |
3604772766 ps |
| T1166 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1900950783 |
|
|
Jul 29 08:29:10 PM PDT 24 |
Jul 29 08:39:38 PM PDT 24 |
8236969728 ps |
| T1167 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.4021867415 |
|
|
Jul 29 08:39:14 PM PDT 24 |
Jul 29 08:44:27 PM PDT 24 |
2981336356 ps |
| T1168 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1934060980 |
|
|
Jul 29 08:29:05 PM PDT 24 |
Jul 29 08:35:16 PM PDT 24 |
2836313624 ps |
| T1169 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3064933536 |
|
|
Jul 29 08:17:57 PM PDT 24 |
Jul 29 08:22:45 PM PDT 24 |
3655088394 ps |
| T241 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.4179568163 |
|
|
Jul 29 08:16:42 PM PDT 24 |
Jul 29 08:48:17 PM PDT 24 |
23716096934 ps |
| T64 |
/workspace/coverage/default/1.chip_tap_straps_rma.1273579143 |
|
|
Jul 29 08:27:39 PM PDT 24 |
Jul 29 08:42:17 PM PDT 24 |
6730711355 ps |
| T1170 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2916638388 |
|
|
Jul 29 08:19:28 PM PDT 24 |
Jul 29 08:26:05 PM PDT 24 |
3461446520 ps |
| T234 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.410334821 |
|
|
Jul 29 08:30:06 PM PDT 24 |
Jul 29 08:56:30 PM PDT 24 |
7611152520 ps |
| T322 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.1892703764 |
|
|
Jul 29 08:36:30 PM PDT 24 |
Jul 29 08:52:11 PM PDT 24 |
5460571808 ps |
| T168 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2844649311 |
|
|
Jul 29 08:27:01 PM PDT 24 |
Jul 29 08:31:42 PM PDT 24 |
3256385718 ps |
| T239 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2743339847 |
|
|
Jul 29 08:14:21 PM PDT 24 |
Jul 29 09:42:58 PM PDT 24 |
44772392936 ps |
| T244 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1366717260 |
|
|
Jul 29 08:26:57 PM PDT 24 |
Jul 29 09:58:53 PM PDT 24 |
47526801230 ps |
| T404 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.2569938491 |
|
|
Jul 29 08:44:58 PM PDT 24 |
Jul 29 08:53:27 PM PDT 24 |
5096509688 ps |
| T169 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.178919140 |
|
|
Jul 29 08:16:16 PM PDT 24 |
Jul 29 08:18:14 PM PDT 24 |
2572534475 ps |
| T340 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1457657487 |
|
|
Jul 29 08:15:30 PM PDT 24 |
Jul 29 08:20:33 PM PDT 24 |
3175025498 ps |
| T1171 |
/workspace/coverage/default/1.chip_sw_kmac_idle.4181743711 |
|
|
Jul 29 08:30:28 PM PDT 24 |
Jul 29 08:33:19 PM PDT 24 |
2948028196 ps |
| T1172 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3632726304 |
|
|
Jul 29 08:31:25 PM PDT 24 |
Jul 29 08:38:36 PM PDT 24 |
3874366044 ps |
| T1173 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.1535974047 |
|
|
Jul 29 08:46:38 PM PDT 24 |
Jul 29 08:55:34 PM PDT 24 |
6066053672 ps |
| T809 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2248972566 |
|
|
Jul 29 08:45:33 PM PDT 24 |
Jul 29 08:50:25 PM PDT 24 |
4021121456 ps |
| T1174 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3634419989 |
|
|
Jul 29 08:39:48 PM PDT 24 |
Jul 29 08:48:19 PM PDT 24 |
6078221204 ps |
| T1175 |
/workspace/coverage/default/0.chip_sw_hmac_multistream.1820115856 |
|
|
Jul 29 08:19:05 PM PDT 24 |
Jul 29 08:52:14 PM PDT 24 |
8604494960 ps |
| T410 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3896687418 |
|
|
Jul 29 08:16:13 PM PDT 24 |
Jul 29 08:21:26 PM PDT 24 |
7130396168 ps |
| T294 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1686504137 |
|
|
Jul 29 08:29:14 PM PDT 24 |
Jul 29 08:42:39 PM PDT 24 |
4695656828 ps |
| T1176 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.249185900 |
|
|
Jul 29 08:48:44 PM PDT 24 |
Jul 29 08:56:41 PM PDT 24 |
4600162120 ps |
| T832 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.513039641 |
|
|
Jul 29 08:44:34 PM PDT 24 |
Jul 29 08:53:03 PM PDT 24 |
5760634328 ps |
| T536 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2469098588 |
|
|
Jul 29 08:14:17 PM PDT 24 |
Jul 29 08:41:09 PM PDT 24 |
13866484357 ps |
| T1177 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1999067165 |
|
|
Jul 29 08:36:40 PM PDT 24 |
Jul 29 08:40:04 PM PDT 24 |
2118690436 ps |
| T807 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.2891606658 |
|
|
Jul 29 08:43:50 PM PDT 24 |
Jul 29 08:53:49 PM PDT 24 |
5854807224 ps |
| T1178 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2808259138 |
|
|
Jul 29 08:49:34 PM PDT 24 |
Jul 29 09:00:20 PM PDT 24 |
4722666630 ps |
| T1179 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2698794483 |
|
|
Jul 29 08:31:18 PM PDT 24 |
Jul 29 08:38:01 PM PDT 24 |
3179849531 ps |
| T316 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2832952162 |
|
|
Jul 29 08:31:37 PM PDT 24 |
Jul 29 08:40:49 PM PDT 24 |
4138348038 ps |
| T38 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.1810122259 |
|
|
Jul 29 08:15:41 PM PDT 24 |
Jul 29 08:22:38 PM PDT 24 |
3719769579 ps |
| T58 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.269272942 |
|
|
Jul 29 08:36:19 PM PDT 24 |
Jul 29 08:45:22 PM PDT 24 |
5684300218 ps |
| T420 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1778561399 |
|
|
Jul 29 08:21:16 PM PDT 24 |
Jul 29 08:34:02 PM PDT 24 |
9896045628 ps |
| T421 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3625540875 |
|
|
Jul 29 08:27:03 PM PDT 24 |
Jul 29 08:28:59 PM PDT 24 |
2899490970 ps |
| T422 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.1881045670 |
|
|
Jul 29 08:16:32 PM PDT 24 |
Jul 29 08:24:52 PM PDT 24 |
10384984700 ps |
| T423 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.2561789718 |
|
|
Jul 29 08:43:44 PM PDT 24 |
Jul 29 08:55:35 PM PDT 24 |
5534852792 ps |
| T424 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.166948072 |
|
|
Jul 29 08:34:35 PM PDT 24 |
Jul 29 08:54:46 PM PDT 24 |
5618514670 ps |
| T425 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1819300011 |
|
|
Jul 29 08:34:11 PM PDT 24 |
Jul 29 09:01:53 PM PDT 24 |
8178739033 ps |
| T426 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.4079762151 |
|
|
Jul 29 08:35:23 PM PDT 24 |
Jul 29 09:52:16 PM PDT 24 |
16780241020 ps |
| T427 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1426168947 |
|
|
Jul 29 08:44:37 PM PDT 24 |
Jul 29 08:51:00 PM PDT 24 |
3599887520 ps |
| T428 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.57825709 |
|
|
Jul 29 08:29:45 PM PDT 24 |
Jul 29 09:42:09 PM PDT 24 |
14618852717 ps |
| T112 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.662756844 |
|
|
Jul 29 08:16:04 PM PDT 24 |
Jul 29 08:24:17 PM PDT 24 |
4902349030 ps |
| T442 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2175815405 |
|
|
Jul 29 08:25:14 PM PDT 24 |
Jul 29 08:28:56 PM PDT 24 |
3061714880 ps |
| T443 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.1061292296 |
|
|
Jul 29 08:26:50 PM PDT 24 |
Jul 29 08:31:40 PM PDT 24 |
2590977546 ps |
| T444 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3578939573 |
|
|
Jul 29 08:48:27 PM PDT 24 |
Jul 29 08:58:27 PM PDT 24 |
5224705908 ps |
| T445 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.37801991 |
|
|
Jul 29 08:41:09 PM PDT 24 |
Jul 29 08:51:58 PM PDT 24 |
4673158968 ps |
| T446 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2474054364 |
|
|
Jul 29 08:31:54 PM PDT 24 |
Jul 29 08:44:29 PM PDT 24 |
4699785700 ps |
| T447 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.395135689 |
|
|
Jul 29 08:33:14 PM PDT 24 |
Jul 29 08:42:59 PM PDT 24 |
4759661112 ps |
| T65 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.3260821298 |
|
|
Jul 29 08:26:47 PM PDT 24 |
Jul 29 08:32:06 PM PDT 24 |
3817954500 ps |
| T448 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1307026881 |
|
|
Jul 29 08:35:48 PM PDT 24 |
Jul 29 08:39:18 PM PDT 24 |
2463543910 ps |
| T449 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.1808898292 |
|
|
Jul 29 08:33:18 PM PDT 24 |
Jul 29 08:38:04 PM PDT 24 |
2980360881 ps |
| T1180 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2451084358 |
|
|
Jul 29 08:36:30 PM PDT 24 |
Jul 29 08:41:52 PM PDT 24 |
3371263811 ps |
| T1181 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.933022242 |
|
|
Jul 29 08:26:23 PM PDT 24 |
Jul 29 08:53:42 PM PDT 24 |
8431758345 ps |
| T1182 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.237318204 |
|
|
Jul 29 08:17:42 PM PDT 24 |
Jul 29 08:36:30 PM PDT 24 |
11951114071 ps |
| T1183 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2794968980 |
|
|
Jul 29 08:30:55 PM PDT 24 |
Jul 29 08:41:10 PM PDT 24 |
5931156800 ps |
| T1184 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.688321479 |
|
|
Jul 29 08:31:09 PM PDT 24 |
Jul 29 09:40:02 PM PDT 24 |
15231095910 ps |
| T1185 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2550947162 |
|
|
Jul 29 08:33:59 PM PDT 24 |
Jul 29 08:41:08 PM PDT 24 |
3387695010 ps |
| T1186 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3727721009 |
|
|
Jul 29 08:35:46 PM PDT 24 |
Jul 29 08:58:34 PM PDT 24 |
12476376162 ps |
| T1187 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3214054993 |
|
|
Jul 29 08:16:55 PM PDT 24 |
Jul 29 08:23:37 PM PDT 24 |
3104830756 ps |
| T1188 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.4208684826 |
|
|
Jul 29 08:27:21 PM PDT 24 |
Jul 29 08:39:14 PM PDT 24 |
5705120554 ps |
| T793 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.113098525 |
|
|
Jul 29 08:44:46 PM PDT 24 |
Jul 29 08:53:39 PM PDT 24 |
4734945396 ps |
| T1189 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.1053988271 |
|
|
Jul 29 08:41:21 PM PDT 24 |
Jul 29 08:47:41 PM PDT 24 |
3627164248 ps |
| T1190 |
/workspace/coverage/default/0.chip_sw_aes_enc.2434356485 |
|
|
Jul 29 08:14:14 PM PDT 24 |
Jul 29 08:18:08 PM PDT 24 |
2734898646 ps |
| T814 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.174194737 |
|
|
Jul 29 08:46:57 PM PDT 24 |
Jul 29 08:59:15 PM PDT 24 |
3998225600 ps |
| T338 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3611252911 |
|
|
Jul 29 08:26:11 PM PDT 24 |
Jul 29 08:35:36 PM PDT 24 |
4382422824 ps |
| T236 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2137862752 |
|
|
Jul 29 08:31:48 PM PDT 24 |
Jul 29 09:33:50 PM PDT 24 |
17976973860 ps |
| T1191 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.2059419440 |
|
|
Jul 29 08:45:33 PM PDT 24 |
Jul 29 08:54:15 PM PDT 24 |
5341201836 ps |
| T1192 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.427837008 |
|
|
Jul 29 08:28:54 PM PDT 24 |
Jul 29 09:25:04 PM PDT 24 |
18937549077 ps |
| T1193 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.4292427414 |
|
|
Jul 29 08:31:03 PM PDT 24 |
Jul 29 08:42:01 PM PDT 24 |
8799407909 ps |
| T1194 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2657582699 |
|
|
Jul 29 08:30:29 PM PDT 24 |
Jul 29 08:35:01 PM PDT 24 |
3319010264 ps |
| T819 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3749259220 |
|
|
Jul 29 08:51:25 PM PDT 24 |
Jul 29 08:56:41 PM PDT 24 |
4037657524 ps |
| T1195 |
/workspace/coverage/default/1.chip_sw_aes_enc.4270955110 |
|
|
Jul 29 08:29:58 PM PDT 24 |
Jul 29 08:36:21 PM PDT 24 |
3330335732 ps |
| T1196 |
/workspace/coverage/default/2.chip_sw_hmac_enc.1723254297 |
|
|
Jul 29 08:36:29 PM PDT 24 |
Jul 29 08:42:03 PM PDT 24 |
3507220220 ps |
| T1197 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.226778161 |
|
|
Jul 29 08:42:26 PM PDT 24 |
Jul 29 09:56:32 PM PDT 24 |
22174020590 ps |