| T45 |
/workspace/coverage/default/1.chip_jtag_csr_rw.3079458556 |
|
|
Jul 30 07:57:28 PM PDT 24 |
Jul 30 08:27:54 PM PDT 24 |
17130966334 ps |
| T835 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.4194541135 |
|
|
Jul 30 08:30:49 PM PDT 24 |
Jul 30 08:41:39 PM PDT 24 |
6066596280 ps |
| T964 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.900412351 |
|
|
Jul 30 08:05:40 PM PDT 24 |
Jul 30 08:40:30 PM PDT 24 |
12418212210 ps |
| T965 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2321373310 |
|
|
Jul 30 08:01:41 PM PDT 24 |
Jul 30 08:11:42 PM PDT 24 |
7821829424 ps |
| T332 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.300962258 |
|
|
Jul 30 07:53:43 PM PDT 24 |
Jul 30 08:23:47 PM PDT 24 |
11082294544 ps |
| T966 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2132715442 |
|
|
Jul 30 07:54:14 PM PDT 24 |
Jul 30 07:58:41 PM PDT 24 |
3093997251 ps |
| T248 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.623764093 |
|
|
Jul 30 08:26:44 PM PDT 24 |
Jul 30 08:36:08 PM PDT 24 |
6104414528 ps |
| T787 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3637370788 |
|
|
Jul 30 08:16:30 PM PDT 24 |
Jul 30 08:25:24 PM PDT 24 |
4033311060 ps |
| T792 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.2792292936 |
|
|
Jul 30 08:00:05 PM PDT 24 |
Jul 30 08:03:55 PM PDT 24 |
2856399777 ps |
| T856 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.333050508 |
|
|
Jul 30 08:27:53 PM PDT 24 |
Jul 30 08:33:15 PM PDT 24 |
3720896086 ps |
| T22 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1461549216 |
|
|
Jul 30 08:11:46 PM PDT 24 |
Jul 30 08:43:18 PM PDT 24 |
25134722996 ps |
| T967 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.300732638 |
|
|
Jul 30 08:18:26 PM PDT 24 |
Jul 30 08:27:23 PM PDT 24 |
3376767578 ps |
| T759 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.1058672055 |
|
|
Jul 30 08:21:55 PM PDT 24 |
Jul 30 08:34:29 PM PDT 24 |
4399814424 ps |
| T763 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3458704702 |
|
|
Jul 30 08:21:20 PM PDT 24 |
Jul 30 08:27:43 PM PDT 24 |
3325339410 ps |
| T756 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2977126350 |
|
|
Jul 30 07:53:15 PM PDT 24 |
Jul 30 08:49:44 PM PDT 24 |
39405270838 ps |
| T968 |
/workspace/coverage/default/0.chip_sw_aes_idle.167354099 |
|
|
Jul 30 07:54:12 PM PDT 24 |
Jul 30 07:59:05 PM PDT 24 |
2373033736 ps |
| T969 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2636666422 |
|
|
Jul 30 08:21:20 PM PDT 24 |
Jul 30 08:51:48 PM PDT 24 |
8960412252 ps |
| T970 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2036679612 |
|
|
Jul 30 08:10:29 PM PDT 24 |
Jul 30 09:01:32 PM PDT 24 |
26721147736 ps |
| T798 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.64476643 |
|
|
Jul 30 08:26:38 PM PDT 24 |
Jul 30 08:35:03 PM PDT 24 |
5626382400 ps |
| T212 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3726209491 |
|
|
Jul 30 08:02:24 PM PDT 24 |
Jul 30 09:09:21 PM PDT 24 |
20539531820 ps |
| T167 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.3226343985 |
|
|
Jul 30 08:29:44 PM PDT 24 |
Jul 30 08:38:41 PM PDT 24 |
5118590074 ps |
| T265 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1798844433 |
|
|
Jul 30 07:57:02 PM PDT 24 |
Jul 30 08:36:51 PM PDT 24 |
34780255669 ps |
| T971 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1142464204 |
|
|
Jul 30 08:18:29 PM PDT 24 |
Jul 30 08:28:27 PM PDT 24 |
6981921474 ps |
| T761 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.3128415721 |
|
|
Jul 30 08:23:51 PM PDT 24 |
Jul 30 08:35:55 PM PDT 24 |
6144832908 ps |
| T180 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1813211646 |
|
|
Jul 30 08:15:41 PM PDT 24 |
Jul 30 08:19:21 PM PDT 24 |
3503118663 ps |
| T235 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2907280936 |
|
|
Jul 30 07:52:58 PM PDT 24 |
Jul 30 08:43:08 PM PDT 24 |
12232811120 ps |
| T972 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.625179977 |
|
|
Jul 30 08:20:08 PM PDT 24 |
Jul 30 08:27:32 PM PDT 24 |
4725606054 ps |
| T328 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1180142251 |
|
|
Jul 30 07:54:06 PM PDT 24 |
Jul 30 08:04:34 PM PDT 24 |
4703648240 ps |
| T793 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3366241962 |
|
|
Jul 30 08:30:17 PM PDT 24 |
Jul 30 08:36:54 PM PDT 24 |
3176275484 ps |
| T973 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1077298484 |
|
|
Jul 30 08:15:11 PM PDT 24 |
Jul 30 08:35:11 PM PDT 24 |
14117824854 ps |
| T974 |
/workspace/coverage/default/0.rom_e2e_static_critical.548441906 |
|
|
Jul 30 08:02:29 PM PDT 24 |
Jul 30 09:20:25 PM PDT 24 |
17667382504 ps |
| T279 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.414859392 |
|
|
Jul 30 08:11:34 PM PDT 24 |
Jul 30 09:12:48 PM PDT 24 |
15007875345 ps |
| T765 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.4015314726 |
|
|
Jul 30 08:23:19 PM PDT 24 |
Jul 30 08:33:35 PM PDT 24 |
6211844720 ps |
| T975 |
/workspace/coverage/default/0.rom_e2e_self_hash.2021004998 |
|
|
Jul 30 07:58:31 PM PDT 24 |
Jul 30 09:48:01 PM PDT 24 |
26006213516 ps |
| T976 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.3250338158 |
|
|
Jul 30 08:06:59 PM PDT 24 |
Jul 30 08:09:48 PM PDT 24 |
2386004200 ps |
| T783 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.4088475513 |
|
|
Jul 30 08:29:50 PM PDT 24 |
Jul 30 08:41:19 PM PDT 24 |
5478138264 ps |
| T727 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3551586194 |
|
|
Jul 30 08:10:48 PM PDT 24 |
Jul 30 08:12:44 PM PDT 24 |
2744277414 ps |
| T67 |
/workspace/coverage/default/0.chip_tap_straps_prod.3485700825 |
|
|
Jul 30 07:54:38 PM PDT 24 |
Jul 30 08:20:36 PM PDT 24 |
13459243176 ps |
| T977 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.4051037439 |
|
|
Jul 30 08:09:56 PM PDT 24 |
Jul 30 08:14:50 PM PDT 24 |
2867297872 ps |
| T978 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3309845348 |
|
|
Jul 30 08:04:40 PM PDT 24 |
Jul 30 08:36:09 PM PDT 24 |
7374567860 ps |
| T38 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.751897167 |
|
|
Jul 30 08:10:23 PM PDT 24 |
Jul 30 08:16:11 PM PDT 24 |
3381861263 ps |
| T849 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.4103132525 |
|
|
Jul 30 08:30:46 PM PDT 24 |
Jul 30 08:43:08 PM PDT 24 |
5484694766 ps |
| T550 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.280156832 |
|
|
Jul 30 08:01:57 PM PDT 24 |
Jul 30 08:16:22 PM PDT 24 |
4694722358 ps |
| T12 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2513613887 |
|
|
Jul 30 07:52:19 PM PDT 24 |
Jul 30 07:57:01 PM PDT 24 |
2784734190 ps |
| T859 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.37325494 |
|
|
Jul 30 08:30:13 PM PDT 24 |
Jul 30 08:40:27 PM PDT 24 |
4873035664 ps |
| T74 |
/workspace/coverage/default/1.chip_jtag_mem_access.4251839535 |
|
|
Jul 30 07:57:17 PM PDT 24 |
Jul 30 08:21:02 PM PDT 24 |
13393328760 ps |
| T979 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.35985228 |
|
|
Jul 30 08:01:55 PM PDT 24 |
Jul 30 08:40:04 PM PDT 24 |
12347828769 ps |
| T124 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2903492839 |
|
|
Jul 30 08:21:24 PM PDT 24 |
Jul 30 08:38:44 PM PDT 24 |
9051793528 ps |
| T980 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1692836849 |
|
|
Jul 30 07:51:45 PM PDT 24 |
Jul 30 08:05:46 PM PDT 24 |
6957475856 ps |
| T168 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.680885633 |
|
|
Jul 30 08:15:32 PM PDT 24 |
Jul 30 08:27:16 PM PDT 24 |
5228622172 ps |
| T981 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3825635383 |
|
|
Jul 30 08:17:42 PM PDT 24 |
Jul 30 08:22:28 PM PDT 24 |
3336759304 ps |
| T755 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1448843769 |
|
|
Jul 30 08:30:15 PM PDT 24 |
Jul 30 08:39:04 PM PDT 24 |
5360803520 ps |
| T786 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.18371093 |
|
|
Jul 30 08:28:31 PM PDT 24 |
Jul 30 08:36:53 PM PDT 24 |
4253772264 ps |
| T728 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1013559066 |
|
|
Jul 30 07:57:51 PM PDT 24 |
Jul 30 07:59:36 PM PDT 24 |
2606165718 ps |
| T788 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.260724673 |
|
|
Jul 30 08:04:06 PM PDT 24 |
Jul 30 08:12:17 PM PDT 24 |
4016534334 ps |
| T367 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.4245565323 |
|
|
Jul 30 08:27:09 PM PDT 24 |
Jul 30 08:40:49 PM PDT 24 |
6058605092 ps |
| T389 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1901983424 |
|
|
Jul 30 08:00:50 PM PDT 24 |
Jul 30 08:14:13 PM PDT 24 |
5897118060 ps |
| T291 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.929215446 |
|
|
Jul 30 08:21:19 PM PDT 24 |
Jul 30 08:32:49 PM PDT 24 |
5723935682 ps |
| T794 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1416504128 |
|
|
Jul 30 08:27:54 PM PDT 24 |
Jul 30 08:34:00 PM PDT 24 |
3857654558 ps |
| T982 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1113743397 |
|
|
Jul 30 08:21:43 PM PDT 24 |
Jul 30 08:30:33 PM PDT 24 |
7325273704 ps |
| T19 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1355589111 |
|
|
Jul 30 08:04:24 PM PDT 24 |
Jul 30 08:29:30 PM PDT 24 |
21997404400 ps |
| T266 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.812485780 |
|
|
Jul 30 07:56:31 PM PDT 24 |
Jul 30 08:36:26 PM PDT 24 |
11658218069 ps |
| T827 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3533887350 |
|
|
Jul 30 08:30:06 PM PDT 24 |
Jul 30 08:37:50 PM PDT 24 |
4301110600 ps |
| T983 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3642854033 |
|
|
Jul 30 08:21:43 PM PDT 24 |
Jul 30 10:02:00 PM PDT 24 |
22137107956 ps |
| T984 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2030758307 |
|
|
Jul 30 08:10:32 PM PDT 24 |
Jul 30 08:45:16 PM PDT 24 |
17545805588 ps |
| T985 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.208215428 |
|
|
Jul 30 07:58:18 PM PDT 24 |
Jul 30 08:17:01 PM PDT 24 |
6852822764 ps |
| T986 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.316364027 |
|
|
Jul 30 08:23:13 PM PDT 24 |
Jul 30 08:33:52 PM PDT 24 |
3908712350 ps |
| T58 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.3627146453 |
|
|
Jul 30 08:20:02 PM PDT 24 |
Jul 30 08:28:59 PM PDT 24 |
5702220131 ps |
| T342 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3819160477 |
|
|
Jul 30 08:09:18 PM PDT 24 |
Jul 30 08:16:38 PM PDT 24 |
3119641180 ps |
| T987 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1308144418 |
|
|
Jul 30 07:51:37 PM PDT 24 |
Jul 30 08:12:06 PM PDT 24 |
6219574216 ps |
| T988 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3561485118 |
|
|
Jul 30 07:53:28 PM PDT 24 |
Jul 30 08:04:13 PM PDT 24 |
4405563768 ps |
| T247 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.4181917992 |
|
|
Jul 30 08:19:25 PM PDT 24 |
Jul 30 08:25:52 PM PDT 24 |
3839297494 ps |
| T176 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2620959987 |
|
|
Jul 30 07:52:14 PM PDT 24 |
Jul 30 07:54:28 PM PDT 24 |
2616964857 ps |
| T989 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.931682456 |
|
|
Jul 30 07:54:43 PM PDT 24 |
Jul 30 08:02:09 PM PDT 24 |
6032201992 ps |
| T990 |
/workspace/coverage/default/2.chip_sw_example_concurrency.514017331 |
|
|
Jul 30 08:07:31 PM PDT 24 |
Jul 30 08:12:21 PM PDT 24 |
2591072160 ps |
| T292 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.802280383 |
|
|
Jul 30 08:08:37 PM PDT 24 |
Jul 30 08:20:18 PM PDT 24 |
6103955192 ps |
| T181 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2556291533 |
|
|
Jul 30 08:02:23 PM PDT 24 |
Jul 30 08:18:00 PM PDT 24 |
7148927342 ps |
| T729 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3688913782 |
|
|
Jul 30 07:51:48 PM PDT 24 |
Jul 30 07:54:00 PM PDT 24 |
2883379133 ps |
| T991 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3196368989 |
|
|
Jul 30 07:50:48 PM PDT 24 |
Jul 30 08:04:41 PM PDT 24 |
7965699914 ps |
| T293 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3788580904 |
|
|
Jul 30 08:11:46 PM PDT 24 |
Jul 30 08:20:18 PM PDT 24 |
3359221216 ps |
| T797 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.2987649249 |
|
|
Jul 30 08:25:07 PM PDT 24 |
Jul 30 08:35:43 PM PDT 24 |
5087384780 ps |
| T362 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1836306545 |
|
|
Jul 30 07:55:35 PM PDT 24 |
Jul 30 07:59:21 PM PDT 24 |
2483933455 ps |
| T992 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1978976432 |
|
|
Jul 30 08:09:58 PM PDT 24 |
Jul 30 09:05:03 PM PDT 24 |
12301142665 ps |
| T993 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.849777310 |
|
|
Jul 30 08:21:17 PM PDT 24 |
Jul 30 09:38:35 PM PDT 24 |
14985361587 ps |
| T459 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.508373180 |
|
|
Jul 30 08:29:19 PM PDT 24 |
Jul 30 08:35:26 PM PDT 24 |
3462058390 ps |
| T336 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1270750609 |
|
|
Jul 30 08:08:54 PM PDT 24 |
Jul 30 08:24:31 PM PDT 24 |
4988007720 ps |
| T59 |
/workspace/coverage/default/2.chip_tap_straps_rma.2999005800 |
|
|
Jul 30 08:15:40 PM PDT 24 |
Jul 30 08:19:19 PM PDT 24 |
2887765286 ps |
| T23 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.1226074485 |
|
|
Jul 30 07:52:20 PM PDT 24 |
Jul 30 08:39:38 PM PDT 24 |
11688911440 ps |
| T27 |
/workspace/coverage/default/1.chip_sw_gpio.4077689761 |
|
|
Jul 30 07:58:24 PM PDT 24 |
Jul 30 08:05:56 PM PDT 24 |
4225996420 ps |
| T13 |
/workspace/coverage/default/1.chip_sw_power_virus.2574255404 |
|
|
Jul 30 08:14:23 PM PDT 24 |
Jul 30 08:37:38 PM PDT 24 |
5695879380 ps |
| T994 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3978838597 |
|
|
Jul 30 08:22:48 PM PDT 24 |
Jul 30 08:30:38 PM PDT 24 |
6828804620 ps |
| T118 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1136586321 |
|
|
Jul 30 08:15:10 PM PDT 24 |
Jul 30 08:25:06 PM PDT 24 |
5105373236 ps |
| T724 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1288763491 |
|
|
Jul 30 08:28:48 PM PDT 24 |
Jul 30 08:40:28 PM PDT 24 |
5480862340 ps |
| T376 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.1010084297 |
|
|
Jul 30 08:24:52 PM PDT 24 |
Jul 30 08:40:05 PM PDT 24 |
5818380910 ps |
| T995 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2278568187 |
|
|
Jul 30 08:03:35 PM PDT 24 |
Jul 30 08:16:42 PM PDT 24 |
4731025536 ps |
| T996 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3372054871 |
|
|
Jul 30 08:11:57 PM PDT 24 |
Jul 30 08:16:02 PM PDT 24 |
3245935530 ps |
| T997 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1435304579 |
|
|
Jul 30 08:09:42 PM PDT 24 |
Jul 30 08:32:04 PM PDT 24 |
8761629020 ps |
| T257 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.550741887 |
|
|
Jul 30 07:53:21 PM PDT 24 |
Jul 30 07:59:44 PM PDT 24 |
3181550690 ps |
| T258 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.3893117934 |
|
|
Jul 30 08:15:30 PM PDT 24 |
Jul 30 08:20:19 PM PDT 24 |
2671274982 ps |
| T998 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3500553297 |
|
|
Jul 30 07:55:59 PM PDT 24 |
Jul 30 08:17:11 PM PDT 24 |
9248564005 ps |
| T999 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1287190758 |
|
|
Jul 30 08:00:12 PM PDT 24 |
Jul 30 09:05:08 PM PDT 24 |
14526398144 ps |
| T799 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2908743413 |
|
|
Jul 30 08:31:31 PM PDT 24 |
Jul 30 08:43:28 PM PDT 24 |
5921018340 ps |
| T1000 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2685865579 |
|
|
Jul 30 07:54:26 PM PDT 24 |
Jul 30 08:00:55 PM PDT 24 |
6067092872 ps |
| T1001 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3479105774 |
|
|
Jul 30 08:08:13 PM PDT 24 |
Jul 30 08:13:38 PM PDT 24 |
2941164600 ps |
| T1002 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.3249998288 |
|
|
Jul 30 08:12:22 PM PDT 24 |
Jul 30 08:40:03 PM PDT 24 |
6928568916 ps |
| T1003 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2316349462 |
|
|
Jul 30 07:56:42 PM PDT 24 |
Jul 30 08:15:11 PM PDT 24 |
6404732192 ps |
| T1004 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.45615203 |
|
|
Jul 30 08:04:14 PM PDT 24 |
Jul 30 08:13:46 PM PDT 24 |
5087940886 ps |
| T94 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3774328063 |
|
|
Jul 30 07:53:53 PM PDT 24 |
Jul 30 08:29:43 PM PDT 24 |
24919358480 ps |
| T1005 |
/workspace/coverage/default/2.chip_sw_hmac_oneshot.1142450045 |
|
|
Jul 30 08:12:38 PM PDT 24 |
Jul 30 08:17:01 PM PDT 24 |
3678974920 ps |
| T1006 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4095354644 |
|
|
Jul 30 07:56:26 PM PDT 24 |
Jul 30 08:18:59 PM PDT 24 |
7615827364 ps |
| T1007 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.631940387 |
|
|
Jul 30 08:00:21 PM PDT 24 |
Jul 30 08:51:18 PM PDT 24 |
10372923683 ps |
| T1008 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1726938920 |
|
|
Jul 30 07:58:06 PM PDT 24 |
Jul 30 08:02:58 PM PDT 24 |
2943070570 ps |
| T207 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1087224449 |
|
|
Jul 30 08:08:27 PM PDT 24 |
Jul 30 11:28:48 PM PDT 24 |
66527417273 ps |
| T721 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1341735153 |
|
|
Jul 30 08:07:36 PM PDT 24 |
Jul 30 09:09:20 PM PDT 24 |
24537032488 ps |
| T828 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.539694601 |
|
|
Jul 30 08:25:47 PM PDT 24 |
Jul 30 08:32:31 PM PDT 24 |
3976227642 ps |
| T169 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.1268521303 |
|
|
Jul 30 08:04:11 PM PDT 24 |
Jul 30 08:10:27 PM PDT 24 |
5223051864 ps |
| T838 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3985014818 |
|
|
Jul 30 08:30:02 PM PDT 24 |
Jul 30 08:36:42 PM PDT 24 |
4021294912 ps |
| T753 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.2581156162 |
|
|
Jul 30 08:30:07 PM PDT 24 |
Jul 30 08:37:54 PM PDT 24 |
5313067486 ps |
| T156 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.786742926 |
|
|
Jul 30 07:54:31 PM PDT 24 |
Jul 30 11:40:40 PM PDT 24 |
255381948386 ps |
| T1009 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.4228280580 |
|
|
Jul 30 08:07:23 PM PDT 24 |
Jul 30 08:12:25 PM PDT 24 |
3373631776 ps |
| T839 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.1407434064 |
|
|
Jul 30 07:55:55 PM PDT 24 |
Jul 30 08:07:57 PM PDT 24 |
5472107064 ps |
| T146 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.4167623964 |
|
|
Jul 30 08:07:48 PM PDT 24 |
Jul 30 11:03:53 PM PDT 24 |
58103824692 ps |
| T1010 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2993011020 |
|
|
Jul 30 08:11:19 PM PDT 24 |
Jul 30 09:06:11 PM PDT 24 |
15616408192 ps |
| T1011 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3262264707 |
|
|
Jul 30 08:03:04 PM PDT 24 |
Jul 30 08:39:42 PM PDT 24 |
24256460526 ps |
| T154 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.494377577 |
|
|
Jul 30 07:55:30 PM PDT 24 |
Jul 30 08:04:30 PM PDT 24 |
5134781038 ps |
| T1012 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1886571323 |
|
|
Jul 30 08:22:59 PM PDT 24 |
Jul 30 08:32:45 PM PDT 24 |
4586442256 ps |
| T261 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.4045675764 |
|
|
Jul 30 08:18:16 PM PDT 24 |
Jul 30 08:24:06 PM PDT 24 |
3464229888 ps |
| T735 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.295883009 |
|
|
Jul 30 08:31:37 PM PDT 24 |
Jul 30 08:41:43 PM PDT 24 |
5599469844 ps |
| T1013 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3828604840 |
|
|
Jul 30 07:52:51 PM PDT 24 |
Jul 30 08:55:26 PM PDT 24 |
21073494711 ps |
| T1014 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.370049148 |
|
|
Jul 30 07:54:26 PM PDT 24 |
Jul 30 08:03:28 PM PDT 24 |
5191002400 ps |
| T1015 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.795444504 |
|
|
Jul 30 07:59:29 PM PDT 24 |
Jul 30 08:05:49 PM PDT 24 |
2778017268 ps |
| T1016 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3955850988 |
|
|
Jul 30 08:22:14 PM PDT 24 |
Jul 30 08:32:08 PM PDT 24 |
4012430240 ps |
| T1017 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2034884501 |
|
|
Jul 30 08:11:18 PM PDT 24 |
Jul 30 08:28:52 PM PDT 24 |
5140359418 ps |
| T1018 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2103758477 |
|
|
Jul 30 07:51:17 PM PDT 24 |
Jul 30 08:03:59 PM PDT 24 |
12110541374 ps |
| T1019 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3547202321 |
|
|
Jul 30 08:22:59 PM PDT 24 |
Jul 30 09:18:52 PM PDT 24 |
15252954052 ps |
| T781 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.2799079396 |
|
|
Jul 30 08:21:09 PM PDT 24 |
Jul 30 08:30:43 PM PDT 24 |
6036028560 ps |
| T1020 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1991745093 |
|
|
Jul 30 07:55:53 PM PDT 24 |
Jul 30 08:10:54 PM PDT 24 |
8008352552 ps |
| T1021 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.218343861 |
|
|
Jul 30 07:58:37 PM PDT 24 |
Jul 30 08:52:19 PM PDT 24 |
11586748640 ps |
| T294 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.895452359 |
|
|
Jul 30 08:13:55 PM PDT 24 |
Jul 30 08:25:37 PM PDT 24 |
5046569308 ps |
| T79 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.1710198601 |
|
|
Jul 30 08:17:33 PM PDT 24 |
Jul 30 08:22:05 PM PDT 24 |
2083056829 ps |
| T461 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.206729005 |
|
|
Jul 30 08:00:46 PM PDT 24 |
Jul 30 08:18:46 PM PDT 24 |
5645240856 ps |
| T730 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.37222553 |
|
|
Jul 30 07:53:15 PM PDT 24 |
Jul 30 07:55:04 PM PDT 24 |
2712895279 ps |
| T823 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2819599858 |
|
|
Jul 30 08:27:43 PM PDT 24 |
Jul 30 08:37:07 PM PDT 24 |
4466021560 ps |
| T758 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.4017636297 |
|
|
Jul 30 07:59:20 PM PDT 24 |
Jul 30 08:19:58 PM PDT 24 |
8404718168 ps |
| T1022 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2113039048 |
|
|
Jul 30 07:57:47 PM PDT 24 |
Jul 30 08:00:47 PM PDT 24 |
2447616312 ps |
| T1023 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.121176601 |
|
|
Jul 30 08:28:34 PM PDT 24 |
Jul 30 08:35:49 PM PDT 24 |
3720438834 ps |
| T76 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.320781479 |
|
|
Jul 30 08:29:08 PM PDT 24 |
Jul 30 08:36:11 PM PDT 24 |
3365325632 ps |
| T85 |
/workspace/coverage/default/1.rom_e2e_self_hash.3407466497 |
|
|
Jul 30 08:11:34 PM PDT 24 |
Jul 30 09:49:52 PM PDT 24 |
26298498612 ps |
| T86 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.4145788139 |
|
|
Jul 30 08:16:31 PM PDT 24 |
Jul 30 08:20:21 PM PDT 24 |
3605598270 ps |
| T87 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3725163851 |
|
|
Jul 30 08:29:18 PM PDT 24 |
Jul 30 08:36:55 PM PDT 24 |
4432481370 ps |
| T88 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.580982227 |
|
|
Jul 30 08:04:32 PM PDT 24 |
Jul 30 08:10:33 PM PDT 24 |
3922430016 ps |
| T89 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1891473107 |
|
|
Jul 30 08:07:42 PM PDT 24 |
Jul 30 08:19:49 PM PDT 24 |
5267276596 ps |
| T90 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1097435761 |
|
|
Jul 30 07:59:36 PM PDT 24 |
Jul 30 08:24:21 PM PDT 24 |
6500014500 ps |
| T91 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.37243580 |
|
|
Jul 30 08:02:16 PM PDT 24 |
Jul 30 09:14:23 PM PDT 24 |
17132027836 ps |
| T92 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.1841219968 |
|
|
Jul 30 08:20:29 PM PDT 24 |
Jul 30 08:29:25 PM PDT 24 |
5243310548 ps |
| T93 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1250367766 |
|
|
Jul 30 07:54:23 PM PDT 24 |
Jul 30 08:02:33 PM PDT 24 |
5146134424 ps |
| T1024 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.3894046188 |
|
|
Jul 30 08:04:31 PM PDT 24 |
Jul 30 08:18:56 PM PDT 24 |
7755974130 ps |
| T775 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2738418821 |
|
|
Jul 30 08:26:26 PM PDT 24 |
Jul 30 08:32:52 PM PDT 24 |
3342264712 ps |
| T1025 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.819910483 |
|
|
Jul 30 08:00:07 PM PDT 24 |
Jul 30 09:18:52 PM PDT 24 |
15508646604 ps |
| T28 |
/workspace/coverage/default/0.chip_sw_gpio.1596265314 |
|
|
Jul 30 07:53:00 PM PDT 24 |
Jul 30 08:02:09 PM PDT 24 |
3973290806 ps |
| T1026 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3603880630 |
|
|
Jul 30 07:55:46 PM PDT 24 |
Jul 30 08:15:29 PM PDT 24 |
5504547488 ps |
| T39 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.2546209761 |
|
|
Jul 30 07:53:10 PM PDT 24 |
Jul 30 08:00:25 PM PDT 24 |
3500330520 ps |
| T1027 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3593047512 |
|
|
Jul 30 08:13:59 PM PDT 24 |
Jul 30 08:28:05 PM PDT 24 |
5600103094 ps |
| T857 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2483101804 |
|
|
Jul 30 08:28:06 PM PDT 24 |
Jul 30 08:35:56 PM PDT 24 |
4811271488 ps |
| T1028 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.4019947623 |
|
|
Jul 30 08:05:12 PM PDT 24 |
Jul 30 08:14:49 PM PDT 24 |
5412451190 ps |
| T769 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3277417032 |
|
|
Jul 30 08:00:52 PM PDT 24 |
Jul 30 08:19:51 PM PDT 24 |
7445200328 ps |
| T807 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.3985919407 |
|
|
Jul 30 08:22:57 PM PDT 24 |
Jul 30 08:30:55 PM PDT 24 |
4189211252 ps |
| T1029 |
/workspace/coverage/default/2.chip_sw_example_rom.2873811482 |
|
|
Jul 30 08:06:45 PM PDT 24 |
Jul 30 08:08:59 PM PDT 24 |
2334419034 ps |
| T352 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2539915412 |
|
|
Jul 30 08:06:40 PM PDT 24 |
Jul 30 08:17:53 PM PDT 24 |
5256062790 ps |
| T1030 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.273524452 |
|
|
Jul 30 08:07:54 PM PDT 24 |
Jul 30 08:11:40 PM PDT 24 |
2299996566 ps |
| T394 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1016737008 |
|
|
Jul 30 08:01:05 PM PDT 24 |
Jul 30 09:43:17 PM PDT 24 |
22828601712 ps |
| T1031 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.1740753166 |
|
|
Jul 30 08:10:48 PM PDT 24 |
Jul 30 08:16:04 PM PDT 24 |
3476551688 ps |
| T295 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4013617631 |
|
|
Jul 30 08:03:36 PM PDT 24 |
Jul 30 08:13:01 PM PDT 24 |
5310008778 ps |
| T1032 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.1945454695 |
|
|
Jul 30 07:52:04 PM PDT 24 |
Jul 30 07:55:39 PM PDT 24 |
2211188130 ps |
| T1033 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2631862859 |
|
|
Jul 30 07:52:09 PM PDT 24 |
Jul 30 08:01:01 PM PDT 24 |
5903166952 ps |
| T1034 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1028528801 |
|
|
Jul 30 08:14:38 PM PDT 24 |
Jul 30 08:19:36 PM PDT 24 |
2687246904 ps |
| T725 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4059363166 |
|
|
Jul 30 07:53:57 PM PDT 24 |
Jul 30 08:04:46 PM PDT 24 |
5400347771 ps |
| T236 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2944535728 |
|
|
Jul 30 08:03:05 PM PDT 24 |
Jul 30 08:44:08 PM PDT 24 |
11587950388 ps |
| T77 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1153984907 |
|
|
Jul 30 08:12:01 PM PDT 24 |
Jul 30 08:32:21 PM PDT 24 |
11603859390 ps |
| T318 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2315504720 |
|
|
Jul 30 08:15:24 PM PDT 24 |
Jul 30 08:32:00 PM PDT 24 |
9018300830 ps |
| T1035 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1834457721 |
|
|
Jul 30 08:18:36 PM PDT 24 |
Jul 30 08:26:01 PM PDT 24 |
3061469882 ps |
| T861 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1270568470 |
|
|
Jul 30 08:24:27 PM PDT 24 |
Jul 30 08:31:21 PM PDT 24 |
3725789056 ps |
| T1036 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3244541771 |
|
|
Jul 30 08:28:42 PM PDT 24 |
Jul 30 08:37:33 PM PDT 24 |
5124813944 ps |
| T1037 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1885089631 |
|
|
Jul 30 08:02:27 PM PDT 24 |
Jul 30 09:17:48 PM PDT 24 |
14817783664 ps |
| T1038 |
/workspace/coverage/default/2.chip_tap_straps_prod.908164370 |
|
|
Jul 30 08:15:35 PM PDT 24 |
Jul 30 08:18:19 PM PDT 24 |
2751708890 ps |
| T1039 |
/workspace/coverage/default/0.chip_sw_hmac_oneshot.718872106 |
|
|
Jul 30 07:53:30 PM PDT 24 |
Jul 30 07:58:34 PM PDT 24 |
3169952528 ps |
| T1040 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2211461060 |
|
|
Jul 30 08:07:36 PM PDT 24 |
Jul 30 08:18:32 PM PDT 24 |
7160320604 ps |
| T860 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3836051272 |
|
|
Jul 30 08:25:17 PM PDT 24 |
Jul 30 08:31:40 PM PDT 24 |
4032244832 ps |
| T390 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.3532492862 |
|
|
Jul 30 08:01:21 PM PDT 24 |
Jul 30 08:13:03 PM PDT 24 |
3197887540 ps |
| T82 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2150240364 |
|
|
Jul 30 08:27:57 PM PDT 24 |
Jul 30 08:35:01 PM PDT 24 |
3584704344 ps |
| T1041 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.4164698961 |
|
|
Jul 30 08:11:32 PM PDT 24 |
Jul 30 09:09:29 PM PDT 24 |
20514664964 ps |
| T1042 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.3597433967 |
|
|
Jul 30 08:25:23 PM PDT 24 |
Jul 30 08:36:27 PM PDT 24 |
4941528590 ps |
| T95 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.668237016 |
|
|
Jul 30 08:05:00 PM PDT 24 |
Jul 30 08:35:47 PM PDT 24 |
22281559178 ps |
| T1043 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.809907353 |
|
|
Jul 30 08:19:55 PM PDT 24 |
Jul 30 08:43:15 PM PDT 24 |
11611901829 ps |
| T251 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3260753606 |
|
|
Jul 30 08:29:25 PM PDT 24 |
Jul 30 08:36:47 PM PDT 24 |
4014779052 ps |
| T302 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.193739302 |
|
|
Jul 30 07:56:45 PM PDT 24 |
Jul 30 08:00:43 PM PDT 24 |
3142786740 ps |
| T32 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.818184903 |
|
|
Jul 30 08:08:58 PM PDT 24 |
Jul 30 08:13:25 PM PDT 24 |
2659152900 ps |
| T303 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.481662195 |
|
|
Jul 30 08:25:37 PM PDT 24 |
Jul 30 08:36:36 PM PDT 24 |
6209489308 ps |
| T182 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.849234000 |
|
|
Jul 30 08:17:36 PM PDT 24 |
Jul 30 08:22:44 PM PDT 24 |
3226900896 ps |
| T304 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2025463760 |
|
|
Jul 30 07:52:56 PM PDT 24 |
Jul 30 07:57:22 PM PDT 24 |
3529663810 ps |
| T305 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2595898498 |
|
|
Jul 30 07:53:55 PM PDT 24 |
Jul 30 08:01:43 PM PDT 24 |
5200272414 ps |
| T306 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2605974070 |
|
|
Jul 30 07:59:34 PM PDT 24 |
Jul 30 08:04:10 PM PDT 24 |
4346370302 ps |
| T307 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1779997224 |
|
|
Jul 30 08:04:08 PM PDT 24 |
Jul 30 08:17:46 PM PDT 24 |
4614563872 ps |
| T308 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.202814111 |
|
|
Jul 30 08:21:12 PM PDT 24 |
Jul 30 08:29:10 PM PDT 24 |
5533892522 ps |
| T1044 |
/workspace/coverage/default/4.chip_tap_straps_dev.2203845909 |
|
|
Jul 30 08:20:12 PM PDT 24 |
Jul 30 08:23:00 PM PDT 24 |
2796174937 ps |
| T1045 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.1332422226 |
|
|
Jul 30 07:55:58 PM PDT 24 |
Jul 30 08:02:03 PM PDT 24 |
3213029400 ps |
| T1046 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.389868583 |
|
|
Jul 30 08:00:05 PM PDT 24 |
Jul 30 10:04:17 PM PDT 24 |
24413979312 ps |
| T831 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.54885979 |
|
|
Jul 30 08:24:29 PM PDT 24 |
Jul 30 08:34:23 PM PDT 24 |
5746192500 ps |
| T1047 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1109949540 |
|
|
Jul 30 07:56:51 PM PDT 24 |
Jul 30 08:02:48 PM PDT 24 |
3813636966 ps |
| T210 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.4131743818 |
|
|
Jul 30 08:11:41 PM PDT 24 |
Jul 30 08:17:49 PM PDT 24 |
3827377552 ps |
| T731 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1308849695 |
|
|
Jul 30 07:52:23 PM PDT 24 |
Jul 30 07:55:08 PM PDT 24 |
3377971528 ps |
| T24 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.175503614 |
|
|
Jul 30 07:52:05 PM PDT 24 |
Jul 30 09:09:03 PM PDT 24 |
18720584328 ps |
| T796 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1370546594 |
|
|
Jul 30 08:23:00 PM PDT 24 |
Jul 30 08:31:07 PM PDT 24 |
4200297324 ps |
| T1048 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2966870769 |
|
|
Jul 30 08:19:33 PM PDT 24 |
Jul 30 08:49:48 PM PDT 24 |
8363861520 ps |
| T1049 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3166054414 |
|
|
Jul 30 08:20:19 PM PDT 24 |
Jul 30 08:31:09 PM PDT 24 |
3916971956 ps |
| T1050 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.618579872 |
|
|
Jul 30 08:04:36 PM PDT 24 |
Jul 30 08:20:45 PM PDT 24 |
8435893114 ps |
| T1051 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.4091471674 |
|
|
Jul 30 07:51:22 PM PDT 24 |
Jul 30 08:18:14 PM PDT 24 |
7430091238 ps |
| T1052 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3237333099 |
|
|
Jul 30 08:11:53 PM PDT 24 |
Jul 30 08:18:16 PM PDT 24 |
7232831256 ps |
| T369 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.3490130085 |
|
|
Jul 30 07:52:21 PM PDT 24 |
Jul 30 07:58:44 PM PDT 24 |
3948547696 ps |
| T1053 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.380075917 |
|
|
Jul 30 07:55:15 PM PDT 24 |
Jul 30 07:59:56 PM PDT 24 |
2322583912 ps |
| T1054 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.2025254075 |
|
|
Jul 30 07:51:49 PM PDT 24 |
Jul 30 07:55:52 PM PDT 24 |
2962194412 ps |
| T377 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1998503463 |
|
|
Jul 30 08:27:41 PM PDT 24 |
Jul 30 08:34:23 PM PDT 24 |
3149041064 ps |
| T46 |
/workspace/coverage/default/1.chip_sw_alert_test.3442341479 |
|
|
Jul 30 08:01:59 PM PDT 24 |
Jul 30 08:06:46 PM PDT 24 |
3495449840 ps |
| T1055 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3408061763 |
|
|
Jul 30 08:00:50 PM PDT 24 |
Jul 30 09:06:37 PM PDT 24 |
14639219443 ps |
| T1056 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.290022289 |
|
|
Jul 30 07:57:47 PM PDT 24 |
Jul 30 08:00:58 PM PDT 24 |
3101214179 ps |
| T359 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.362178176 |
|
|
Jul 30 07:59:49 PM PDT 24 |
Jul 30 08:08:05 PM PDT 24 |
19145660968 ps |
| T1057 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.524006951 |
|
|
Jul 30 08:02:02 PM PDT 24 |
Jul 30 09:10:20 PM PDT 24 |
17070512032 ps |
| T1058 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2978286435 |
|
|
Jul 30 07:51:30 PM PDT 24 |
Jul 30 08:44:00 PM PDT 24 |
28323167490 ps |
| T1059 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3030016911 |
|
|
Jul 30 08:04:58 PM PDT 24 |
Jul 30 08:29:04 PM PDT 24 |
10379179742 ps |
| T50 |
/workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2121024983 |
|
|
Jul 30 08:08:10 PM PDT 24 |
Jul 30 08:13:33 PM PDT 24 |
3642366369 ps |
| T1060 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.3067010386 |
|
|
Jul 30 08:28:11 PM PDT 24 |
Jul 30 08:40:08 PM PDT 24 |
5762650468 ps |
| T309 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2879825591 |
|
|
Jul 30 07:54:37 PM PDT 24 |
Jul 30 07:59:07 PM PDT 24 |
3063947966 ps |
| T1061 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1091670647 |
|
|
Jul 30 07:56:16 PM PDT 24 |
Jul 30 08:08:47 PM PDT 24 |
4809091408 ps |
| T802 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2601770559 |
|
|
Jul 30 08:21:53 PM PDT 24 |
Jul 30 08:31:32 PM PDT 24 |
4140197674 ps |
| T1062 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2853323979 |
|
|
Jul 30 08:06:49 PM PDT 24 |
Jul 30 08:10:20 PM PDT 24 |
2756042952 ps |
| T833 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1750090229 |
|
|
Jul 30 08:24:26 PM PDT 24 |
Jul 30 08:32:01 PM PDT 24 |
3509643090 ps |
| T346 |
/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.720367553 |
|
|
Jul 30 08:05:19 PM PDT 24 |
Jul 30 08:11:11 PM PDT 24 |
3705440870 ps |
| T1063 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1934542193 |
|
|
Jul 30 08:09:37 PM PDT 24 |
Jul 30 08:29:19 PM PDT 24 |
6796981116 ps |
| T1064 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.1359093280 |
|
|
Jul 30 08:02:15 PM PDT 24 |
Jul 30 08:32:44 PM PDT 24 |
8307112312 ps |
| T863 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2660994187 |
|
|
Jul 30 08:31:13 PM PDT 24 |
Jul 30 08:39:10 PM PDT 24 |
5336261880 ps |
| T791 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3313344054 |
|
|
Jul 30 08:29:06 PM PDT 24 |
Jul 30 08:36:48 PM PDT 24 |
4397380100 ps |
| T723 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.6116340 |
|
|
Jul 30 08:28:44 PM PDT 24 |
Jul 30 08:35:30 PM PDT 24 |
4025558354 ps |
| T451 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.971667427 |
|
|
Jul 30 07:57:17 PM PDT 24 |
Jul 30 08:58:02 PM PDT 24 |
31617237908 ps |
| T60 |
/workspace/coverage/default/4.chip_tap_straps_rma.424714946 |
|
|
Jul 30 08:19:43 PM PDT 24 |
Jul 30 08:22:47 PM PDT 24 |
2548982616 ps |
| T348 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2147980611 |
|
|
Jul 30 07:52:22 PM PDT 24 |
Jul 30 08:02:52 PM PDT 24 |
3908119812 ps |
| T1065 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1240783704 |
|
|
Jul 30 08:18:06 PM PDT 24 |
Jul 30 08:29:18 PM PDT 24 |
5384361800 ps |
| T237 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.253662008 |
|
|
Jul 30 08:13:39 PM PDT 24 |
Jul 30 09:38:40 PM PDT 24 |
16801646056 ps |
| T850 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3368539002 |
|
|
Jul 30 08:24:08 PM PDT 24 |
Jul 30 08:29:53 PM PDT 24 |
3556092700 ps |
| T1066 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3068855833 |
|
|
Jul 30 08:01:07 PM PDT 24 |
Jul 30 08:10:39 PM PDT 24 |
7242707994 ps |
| T1067 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.4038999783 |
|
|
Jul 30 07:52:08 PM PDT 24 |
Jul 30 07:56:07 PM PDT 24 |
2969008108 ps |