| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.07 | 95.52 | 93.83 | 95.38 | 94.55 | 97.53 | 99.61 |
| T2762 | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.2342133269 | Jul 30 08:47:41 PM PDT 24 | Jul 30 08:49:28 PM PDT 24 | 5925333966 ps | ||
| T2763 | /workspace/coverage/cover_reg_top/63.xbar_random.3464314004 | Jul 30 08:42:54 PM PDT 24 | Jul 30 08:43:43 PM PDT 24 | 575670075 ps | ||
| T2764 | /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.484062945 | Jul 30 08:31:01 PM PDT 24 | Jul 30 08:39:00 PM PDT 24 | 7074981104 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3801817580 | Jul 30 08:33:46 PM PDT 24 | Jul 30 08:34:17 PM PDT 24 | 285521394 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1238371853 | Jul 30 08:33:27 PM PDT 24 | Jul 30 08:33:59 PM PDT 24 | 645902576 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/13.xbar_random.1948804453 | Jul 30 08:32:22 PM PDT 24 | Jul 30 08:33:13 PM PDT 24 | 541334295 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/46.xbar_stress_all.1403478702 | Jul 30 08:40:11 PM PDT 24 | Jul 30 08:46:12 PM PDT 24 | 8052147776 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/67.xbar_error_random.3781696696 | Jul 30 08:43:40 PM PDT 24 | Jul 30 08:44:19 PM PDT 24 | 1058855930 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/44.xbar_random.1453579453 | Jul 30 08:39:35 PM PDT 24 | Jul 30 08:40:38 PM PDT 24 | 1709388895 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/91.xbar_error_random.2828856529 | Jul 30 08:47:48 PM PDT 24 | Jul 30 08:48:33 PM PDT 24 | 493088558 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.83852333 | Jul 30 08:38:16 PM PDT 24 | Jul 30 08:38:22 PM PDT 24 | 45520391 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.409686047 | Jul 30 08:48:06 PM PDT 24 | Jul 30 08:49:44 PM PDT 24 | 9225050818 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.668449483 | Jul 30 08:41:18 PM PDT 24 | Jul 30 08:43:30 PM PDT 24 | 2979725404 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/32.xbar_stress_all.4281511100 | Jul 30 08:37:26 PM PDT 24 | Jul 30 08:41:52 PM PDT 24 | 7565553399 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/73.xbar_stress_all.301620099 | Jul 30 08:44:45 PM PDT 24 | Jul 30 08:48:58 PM PDT 24 | 6220089216 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.1305957210 | Jul 30 08:35:45 PM PDT 24 | Jul 30 08:37:27 PM PDT 24 | 9787055139 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.587959310 | Jul 30 08:30:15 PM PDT 24 | Jul 30 08:44:58 PM PDT 24 | 87512260312 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1577127511 | Jul 30 08:48:37 PM PDT 24 | Jul 30 08:49:02 PM PDT 24 | 557661596 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.3210629959 | Jul 30 08:42:01 PM PDT 24 | Jul 30 08:45:52 PM PDT 24 | 709454258 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.218377401 | Jul 30 08:45:32 PM PDT 24 | Jul 30 08:52:06 PM PDT 24 | 2448420343 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/41.xbar_error_random.4224611248 | Jul 30 08:39:06 PM PDT 24 | Jul 30 08:39:19 PM PDT 24 | 307425179 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/13.xbar_same_source.2910296915 | Jul 30 08:32:25 PM PDT 24 | Jul 30 08:32:47 PM PDT 24 | 244874821 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/50.xbar_smoke.2850064364 | Jul 30 08:40:39 PM PDT 24 | Jul 30 08:40:46 PM PDT 24 | 41647797 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.2104409465 | Jul 30 08:48:50 PM PDT 24 | Jul 30 08:51:28 PM PDT 24 | 2114703562 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.345171232 | Jul 30 08:42:47 PM PDT 24 | Jul 30 08:42:53 PM PDT 24 | 39259560 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.1444660937 | Jul 30 08:34:18 PM PDT 24 | Jul 30 08:35:35 PM PDT 24 | 4411105846 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.2139983317 | Jul 30 08:48:29 PM PDT 24 | Jul 30 08:51:29 PM PDT 24 | 4917236758 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/97.xbar_same_source.2616358599 | Jul 30 08:48:49 PM PDT 24 | Jul 30 08:48:59 PM PDT 24 | 93171707 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.3429707047 | Jul 30 08:40:18 PM PDT 24 | Jul 30 08:41:48 PM PDT 24 | 8482760431 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.645183175 | Jul 30 08:41:50 PM PDT 24 | Jul 30 08:41:57 PM PDT 24 | 49880409 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/91.xbar_same_source.3908350250 | Jul 30 08:47:47 PM PDT 24 | Jul 30 08:48:33 PM PDT 24 | 562403671 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/19.xbar_stress_all.2854749068 | Jul 30 08:34:30 PM PDT 24 | Jul 30 08:35:10 PM PDT 24 | 404738288 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2262458474 | Jul 30 08:30:46 PM PDT 24 | Jul 30 08:52:40 PM PDT 24 | 71430773057 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/4.xbar_smoke.2132199155 | Jul 30 08:28:09 PM PDT 24 | Jul 30 08:28:15 PM PDT 24 | 44181606 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.3299272602 | Jul 30 08:47:16 PM PDT 24 | Jul 30 08:52:03 PM PDT 24 | 2047896219 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/9.chip_csr_rw.932883378 | Jul 30 08:30:55 PM PDT 24 | Jul 30 08:42:50 PM PDT 24 | 5794242231 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.4248645572 | Jul 30 08:45:07 PM PDT 24 | Jul 30 08:45:15 PM PDT 24 | 45561690 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.2183745279 | Jul 30 08:40:24 PM PDT 24 | Jul 30 08:40:48 PM PDT 24 | 224985261 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.761748692 | Jul 30 08:35:25 PM PDT 24 | Jul 30 08:36:59 PM PDT 24 | 5278168298 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.2531919371 | Jul 30 08:37:42 PM PDT 24 | Jul 30 08:38:25 PM PDT 24 | 2539453440 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.2725919125 | Jul 30 08:36:25 PM PDT 24 | Jul 30 08:36:44 PM PDT 24 | 151176832 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.1851894624 | Jul 30 08:47:13 PM PDT 24 | Jul 30 08:58:06 PM PDT 24 | 66005424358 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/12.xbar_smoke.3156432978 | Jul 30 08:31:58 PM PDT 24 | Jul 30 08:32:05 PM PDT 24 | 48858667 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.292690721 | Jul 30 08:27:32 PM PDT 24 | Jul 30 09:44:37 PM PDT 24 | 28925727110 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.1788818244 | Jul 30 08:46:23 PM PDT 24 | Jul 30 08:47:05 PM PDT 24 | 998331862 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/60.xbar_random.2653176949 | Jul 30 08:42:33 PM PDT 24 | Jul 30 08:43:04 PM PDT 24 | 806360975 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/6.xbar_random.2650658124 | Jul 30 08:29:20 PM PDT 24 | Jul 30 08:29:28 PM PDT 24 | 124691758 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.191501291 | Jul 30 08:39:49 PM PDT 24 | Jul 30 08:41:07 PM PDT 24 | 7378008934 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2162956069 | Jul 30 08:31:50 PM PDT 24 | Jul 30 08:42:39 PM PDT 24 | 14646967693 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.45489909 | Jul 30 08:40:37 PM PDT 24 | Jul 30 08:40:44 PM PDT 24 | 45182153 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.102044000 | Jul 30 08:37:38 PM PDT 24 | Jul 30 08:37:52 PM PDT 24 | 99963157 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.775102958 | Jul 30 08:47:45 PM PDT 24 | Jul 30 08:58:05 PM PDT 24 | 58875532130 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.2398299562 | Jul 30 08:33:29 PM PDT 24 | Jul 30 08:36:34 PM PDT 24 | 4871508511 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.1674049253 | Jul 30 08:36:52 PM PDT 24 | Jul 30 08:38:12 PM PDT 24 | 4598417675 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.3003479820 | Jul 30 08:41:24 PM PDT 24 | Jul 30 08:42:42 PM PDT 24 | 4520880178 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.1432008749 | Jul 30 08:45:08 PM PDT 24 | Jul 30 08:48:35 PM PDT 24 | 4594378330 ps | ||
| T913 | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.2342278629 | Jul 30 08:41:07 PM PDT 24 | Jul 30 08:46:57 PM PDT 24 | 2250692966 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.1320746722 | Jul 30 08:38:10 PM PDT 24 | Jul 30 08:56:49 PM PDT 24 | 64679537429 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/80.xbar_same_source.3322318256 | Jul 30 08:45:50 PM PDT 24 | Jul 30 08:47:17 PM PDT 24 | 2636418681 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/5.xbar_smoke.2687538693 | Jul 30 08:28:49 PM PDT 24 | Jul 30 08:28:56 PM PDT 24 | 46947690 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/2.xbar_same_source.3356131558 | Jul 30 08:27:00 PM PDT 24 | Jul 30 08:27:24 PM PDT 24 | 246283419 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/65.xbar_stress_all.1579793874 | Jul 30 08:43:22 PM PDT 24 | Jul 30 08:45:07 PM PDT 24 | 3560625723 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.1994182000 | Jul 30 08:38:45 PM PDT 24 | Jul 30 08:40:41 PM PDT 24 | 10309786414 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.960671572 | Jul 30 08:37:32 PM PDT 24 | Jul 30 08:39:14 PM PDT 24 | 5815993023 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.3802230500 | Jul 30 08:45:39 PM PDT 24 | Jul 30 08:45:47 PM PDT 24 | 57463427 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.2674026520 | Jul 30 08:46:38 PM PDT 24 | Jul 30 08:46:47 PM PDT 24 | 50175930 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.853844592 | Jul 30 08:32:40 PM PDT 24 | Jul 30 08:58:17 PM PDT 24 | 83861544710 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.2532871730 | Jul 30 08:41:25 PM PDT 24 | Jul 30 09:03:56 PM PDT 24 | 76133751013 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.177642068 | Jul 30 08:34:31 PM PDT 24 | Jul 30 08:35:25 PM PDT 24 | 1231519327 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.815517202 | Jul 30 08:32:54 PM PDT 24 | Jul 30 08:39:34 PM PDT 24 | 5311087532 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.2416915175 | Jul 30 08:48:31 PM PDT 24 | Jul 30 08:48:38 PM PDT 24 | 51945318 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/24.xbar_same_source.1593354428 | Jul 30 08:35:33 PM PDT 24 | Jul 30 08:35:55 PM PDT 24 | 273225586 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.4287410797 | Jul 30 08:46:49 PM PDT 24 | Jul 30 08:47:00 PM PDT 24 | 198316444 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.348163746 | Jul 30 08:40:00 PM PDT 24 | Jul 30 08:40:07 PM PDT 24 | 40564992 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.2467407785 | Jul 30 08:37:07 PM PDT 24 | Jul 30 08:40:44 PM PDT 24 | 11889323066 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/23.xbar_same_source.315408596 | Jul 30 08:35:22 PM PDT 24 | Jul 30 08:36:49 PM PDT 24 | 2448374619 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.2768346153 | Jul 30 08:44:50 PM PDT 24 | Jul 30 08:45:57 PM PDT 24 | 1502760611 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.792531801 | Jul 30 08:34:44 PM PDT 24 | Jul 30 08:38:46 PM PDT 24 | 1833169544 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.1261433477 | Jul 30 08:37:52 PM PDT 24 | Jul 30 08:39:27 PM PDT 24 | 5112529412 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/81.xbar_smoke.3029048071 | Jul 30 08:45:57 PM PDT 24 | Jul 30 08:46:07 PM PDT 24 | 209469375 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/34.xbar_stress_all.972803092 | Jul 30 08:37:46 PM PDT 24 | Jul 30 08:43:38 PM PDT 24 | 7983057738 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.3386431468 | Jul 30 08:39:12 PM PDT 24 | Jul 30 08:40:11 PM PDT 24 | 3467592383 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/94.xbar_stress_all.3350912059 | Jul 30 08:48:15 PM PDT 24 | Jul 30 08:52:27 PM PDT 24 | 3179368755 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/18.xbar_smoke.3321466870 | Jul 30 08:33:51 PM PDT 24 | Jul 30 08:34:03 PM PDT 24 | 241191450 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.3675854427 | Jul 30 08:27:44 PM PDT 24 | Jul 30 08:27:51 PM PDT 24 | 43446275 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.2134992872 | Jul 30 08:40:29 PM PDT 24 | Jul 30 08:42:11 PM PDT 24 | 9479109577 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.851162017 | Jul 30 08:37:26 PM PDT 24 | Jul 30 08:37:59 PM PDT 24 | 447893770 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.282080214 | Jul 30 08:42:15 PM PDT 24 | Jul 30 08:44:05 PM PDT 24 | 2257870220 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.4055046257 | Jul 30 08:46:31 PM PDT 24 | Jul 30 08:46:37 PM PDT 24 | 41803451 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.1076596520 | Jul 30 08:29:35 PM PDT 24 | Jul 30 08:36:56 PM PDT 24 | 6236110272 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/69.xbar_smoke.2792673332 | Jul 30 08:43:55 PM PDT 24 | Jul 30 08:44:01 PM PDT 24 | 42924332 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.3718926208 | Jul 30 08:34:49 PM PDT 24 | Jul 30 08:34:56 PM PDT 24 | 43686288 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/10.xbar_smoke.2865203438 | Jul 30 08:31:08 PM PDT 24 | Jul 30 08:31:17 PM PDT 24 | 164386866 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/31.xbar_same_source.1747454149 | Jul 30 08:37:11 PM PDT 24 | Jul 30 08:37:29 PM PDT 24 | 460642064 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.1634708981 | Jul 30 08:46:33 PM PDT 24 | Jul 30 08:56:13 PM PDT 24 | 52389368385 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/17.xbar_random.1689199502 | Jul 30 08:33:43 PM PDT 24 | Jul 30 08:34:23 PM PDT 24 | 423625029 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/90.xbar_error_random.171025705 | Jul 30 08:47:38 PM PDT 24 | Jul 30 08:48:22 PM PDT 24 | 492250711 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.4065218986 | Jul 30 08:47:38 PM PDT 24 | Jul 30 08:48:54 PM PDT 24 | 4147640014 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/16.chip_tl_errors.2069524649 | Jul 30 08:33:10 PM PDT 24 | Jul 30 08:36:06 PM PDT 24 | 3317895037 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1818029717 | Jul 30 08:34:11 PM PDT 24 | Jul 30 08:37:40 PM PDT 24 | 3236572120 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.687050171 | Jul 30 08:40:28 PM PDT 24 | Jul 30 08:42:34 PM PDT 24 | 1412946935 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.1616657508 | Jul 30 08:45:01 PM PDT 24 | Jul 30 08:50:14 PM PDT 24 | 27620418287 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/16.xbar_smoke.846724 | Jul 30 08:33:13 PM PDT 24 | Jul 30 08:33:23 PM PDT 24 | 220139442 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/5.chip_csr_rw.1732585002 | Jul 30 08:29:06 PM PDT 24 | Jul 30 08:34:11 PM PDT 24 | 3785238076 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.535273013 | Jul 30 08:37:31 PM PDT 24 | Jul 30 08:40:07 PM PDT 24 | 744699916 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/31.xbar_error_random.1554714587 | Jul 30 08:37:14 PM PDT 24 | Jul 30 08:39:01 PM PDT 24 | 2523795399 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/61.xbar_smoke.829810794 | Jul 30 08:42:32 PM PDT 24 | Jul 30 08:42:39 PM PDT 24 | 48472903 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1786147301 | Jul 30 08:31:40 PM PDT 24 | Jul 30 08:31:52 PM PDT 24 | 91496412 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.3029012294 | Jul 30 08:47:48 PM PDT 24 | Jul 30 08:48:38 PM PDT 24 | 1033218588 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1512108291 | Jul 30 08:49:12 PM PDT 24 | Jul 30 08:49:58 PM PDT 24 | 1113158476 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.11033257 | Jul 30 08:39:22 PM PDT 24 | Jul 30 08:39:55 PM PDT 24 | 279605681 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.996996047 | Jul 30 08:42:35 PM PDT 24 | Jul 30 08:51:29 PM PDT 24 | 47917632263 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.1272928069 | Jul 30 08:26:35 PM PDT 24 | Jul 30 08:28:03 PM PDT 24 | 8513408948 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.1197366672 | Jul 30 08:47:23 PM PDT 24 | Jul 30 08:48:16 PM PDT 24 | 3125244520 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.2615576652 | Jul 30 08:43:23 PM PDT 24 | Jul 30 09:00:27 PM PDT 24 | 57735680665 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.4191056599 | Jul 30 08:35:06 PM PDT 24 | Jul 30 08:35:19 PM PDT 24 | 105637113 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/83.xbar_stress_all.2331782372 | Jul 30 08:46:27 PM PDT 24 | Jul 30 08:48:33 PM PDT 24 | 1870750735 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.4153299129 | Jul 30 08:27:10 PM PDT 24 | Jul 30 08:27:54 PM PDT 24 | 322746131 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.864054533 | Jul 30 08:32:56 PM PDT 24 | Jul 30 09:07:46 PM PDT 24 | 16725302631 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.2099897112 | Jul 30 08:48:05 PM PDT 24 | Jul 30 08:49:27 PM PDT 24 | 893767826 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/52.xbar_stress_all.1156282160 | Jul 30 08:41:03 PM PDT 24 | Jul 30 08:47:11 PM PDT 24 | 8993788448 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.2130887742 | Jul 30 08:40:44 PM PDT 24 | Jul 30 09:08:58 PM PDT 24 | 99358698187 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/3.chip_csr_rw.1160429878 | Jul 30 08:28:06 PM PDT 24 | Jul 30 08:33:56 PM PDT 24 | 3809479052 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.4214110544 | Jul 30 08:45:17 PM PDT 24 | Jul 30 09:23:18 PM PDT 24 | 129022936229 ps | ||
| T2885 | /workspace/coverage/cover_reg_top/55.xbar_random.3275414985 | Jul 30 08:41:30 PM PDT 24 | Jul 30 08:42:04 PM PDT 24 | 387137362 ps | ||
| T2886 | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2714636744 | Jul 30 08:45:47 PM PDT 24 | Jul 30 08:45:54 PM PDT 24 | 49270083 ps | ||
| T2887 | /workspace/coverage/cover_reg_top/98.xbar_stress_all.266255680 | Jul 30 08:49:03 PM PDT 24 | Jul 30 08:53:30 PM PDT 24 | 3222577677 ps | ||
| T2888 | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3626045149 | Jul 30 08:45:10 PM PDT 24 | Jul 30 08:52:27 PM PDT 24 | 25307759760 ps | ||
| T2889 | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.3768175974 | Jul 30 08:30:57 PM PDT 24 | Jul 30 08:43:47 PM PDT 24 | 6916596392 ps | ||
| T2890 | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.3064106929 | Jul 30 08:36:46 PM PDT 24 | Jul 30 08:52:21 PM PDT 24 | 53120002035 ps | ||
| T2891 | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.4113989946 | Jul 30 08:41:22 PM PDT 24 | Jul 30 08:42:34 PM PDT 24 | 6751617713 ps | ||
| T2892 | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.1907468561 | Jul 30 08:39:39 PM PDT 24 | Jul 30 08:41:11 PM PDT 24 | 8980133520 ps | ||
| T2893 | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.3254720734 | Jul 30 08:34:36 PM PDT 24 | Jul 30 08:35:27 PM PDT 24 | 533636172 ps | ||
| T2894 | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.3702460659 | Jul 30 08:48:01 PM PDT 24 | Jul 30 08:48:56 PM PDT 24 | 5092730518 ps | ||
| T2895 | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.65503412 | Jul 30 08:38:40 PM PDT 24 | Jul 30 08:40:36 PM PDT 24 | 6594863372 ps | ||
| T2896 | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.2127047906 | Jul 30 08:37:05 PM PDT 24 | Jul 30 08:37:45 PM PDT 24 | 101378836 ps | ||
| T2897 | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.3337803281 | Jul 30 08:47:02 PM PDT 24 | Jul 30 08:47:56 PM PDT 24 | 515668972 ps | ||
| T2898 | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.3220754057 | Jul 30 08:37:08 PM PDT 24 | Jul 30 08:37:38 PM PDT 24 | 748423288 ps | ||
| T2899 | /workspace/coverage/cover_reg_top/2.chip_csr_rw.2856926238 | Jul 30 08:27:30 PM PDT 24 | Jul 30 08:34:04 PM PDT 24 | 4509137460 ps | ||
| T2900 | /workspace/coverage/cover_reg_top/83.xbar_smoke.2353194055 | Jul 30 08:46:24 PM PDT 24 | Jul 30 08:46:32 PM PDT 24 | 147452391 ps | ||
| T2901 | /workspace/coverage/cover_reg_top/21.xbar_same_source.3632008037 | Jul 30 08:34:52 PM PDT 24 | Jul 30 08:35:28 PM PDT 24 | 567960087 ps | ||
| T2902 | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.3214877804 | Jul 30 08:42:41 PM PDT 24 | Jul 30 08:58:23 PM PDT 24 | 55620017746 ps | ||
| T2903 | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.730480258 | Jul 30 08:34:21 PM PDT 24 | Jul 30 08:44:50 PM PDT 24 | 33781691092 ps | ||
| T2904 | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.2783934189 | Jul 30 08:28:51 PM PDT 24 | Jul 30 08:37:41 PM PDT 24 | 51543561220 ps | ||
| T2905 | /workspace/coverage/cover_reg_top/22.chip_tl_errors.1037934419 | Jul 30 08:34:59 PM PDT 24 | Jul 30 08:40:05 PM PDT 24 | 3679623080 ps | ||
| T2906 | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.64259462 | Jul 30 08:27:54 PM PDT 24 | Jul 30 08:28:31 PM PDT 24 | 278877539 ps | ||
| T2907 | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.2543403758 | Jul 30 08:42:28 PM PDT 24 | Jul 30 08:55:18 PM PDT 24 | 73178848824 ps | ||
| T2908 | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.988854515 | Jul 30 08:36:02 PM PDT 24 | Jul 30 08:36:42 PM PDT 24 | 169696306 ps | ||
| T2909 | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.419609474 | Jul 30 08:38:55 PM PDT 24 | Jul 30 08:39:22 PM PDT 24 | 610315308 ps | ||
| T2910 | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2596205978 | Jul 30 08:31:58 PM PDT 24 | Jul 30 08:32:04 PM PDT 24 | 35521119 ps | ||
| T2911 | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1821843435 | Jul 30 08:41:22 PM PDT 24 | Jul 30 08:41:30 PM PDT 24 | 59768456 ps | ||
| T2912 | /workspace/coverage/cover_reg_top/1.xbar_same_source.736562686 | Jul 30 08:26:15 PM PDT 24 | Jul 30 08:26:45 PM PDT 24 | 408486448 ps | ||
| T2913 | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.2567344314 | Jul 30 08:30:34 PM PDT 24 | Jul 30 08:32:10 PM PDT 24 | 8810924097 ps | ||
| T2914 | /workspace/coverage/cover_reg_top/74.xbar_error_random.3381344342 | Jul 30 08:44:57 PM PDT 24 | Jul 30 08:45:42 PM PDT 24 | 1016701733 ps | ||
| T2915 | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.2173170217 | Jul 30 08:46:31 PM PDT 24 | Jul 30 08:48:27 PM PDT 24 | 3064574950 ps | ||
| T2916 | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.3498006000 | Jul 30 08:42:06 PM PDT 24 | Jul 30 08:42:16 PM PDT 24 | 64818459 ps | ||
| T2917 | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.3587631113 | Jul 30 08:41:25 PM PDT 24 | Jul 30 08:41:52 PM PDT 24 | 253768152 ps | ||
| T2918 | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.738570626 | Jul 30 08:37:35 PM PDT 24 | Jul 30 08:38:41 PM PDT 24 | 6276990479 ps | ||
| T2919 | /workspace/coverage/cover_reg_top/28.xbar_smoke.473498678 | Jul 30 08:36:27 PM PDT 24 | Jul 30 08:36:35 PM PDT 24 | 190453462 ps | ||
| T2920 | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.3404875842 | Jul 30 08:34:44 PM PDT 24 | Jul 30 08:35:32 PM PDT 24 | 1429420515 ps | ||
| T2921 | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.3047563066 | Jul 30 08:33:11 PM PDT 24 | Jul 30 09:14:39 PM PDT 24 | 16982091721 ps | ||
| T2922 | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.2828299119 | Jul 30 08:36:05 PM PDT 24 | Jul 30 08:43:37 PM PDT 24 | 13207051516 ps | ||
| T2923 | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.3834777378 | Jul 30 08:37:56 PM PDT 24 | Jul 30 08:40:35 PM PDT 24 | 3662932013 ps | ||
| T2924 | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.1427908091 | Jul 30 08:44:05 PM PDT 24 | Jul 30 08:44:15 PM PDT 24 | 73542476 ps | ||
| T2925 | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.96474995 | Jul 30 08:29:04 PM PDT 24 | Jul 30 09:00:02 PM PDT 24 | 15314486669 ps | ||
| T2926 | /workspace/coverage/cover_reg_top/40.xbar_random.1244935884 | Jul 30 08:38:58 PM PDT 24 | Jul 30 08:39:19 PM PDT 24 | 192728570 ps | ||
| T2927 | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.3751658979 | Jul 30 08:43:28 PM PDT 24 | Jul 30 08:44:45 PM PDT 24 | 7221301472 ps | ||
| T2928 | /workspace/coverage/cover_reg_top/27.xbar_same_source.2130213427 | Jul 30 08:36:29 PM PDT 24 | Jul 30 08:37:02 PM PDT 24 | 1045209762 ps | ||
| T2929 | /workspace/coverage/cover_reg_top/4.xbar_same_source.1515944283 | Jul 30 08:28:19 PM PDT 24 | Jul 30 08:28:35 PM PDT 24 | 431497061 ps | ||
| T2930 | /workspace/coverage/cover_reg_top/36.xbar_random.3726400812 | Jul 30 08:38:05 PM PDT 24 | Jul 30 08:38:57 PM PDT 24 | 1346208059 ps | ||
| T2931 | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.149284072 | Jul 30 08:38:48 PM PDT 24 | Jul 30 08:42:23 PM PDT 24 | 910006027 ps | ||
| T2932 | /workspace/coverage/cover_reg_top/92.xbar_random.3296057817 | Jul 30 08:47:51 PM PDT 24 | Jul 30 08:48:33 PM PDT 24 | 423351990 ps | ||
| T2933 | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.1875235549 | Jul 30 08:26:07 PM PDT 24 | Jul 30 08:27:12 PM PDT 24 | 617381088 ps | ||
| T2934 | /workspace/coverage/cover_reg_top/82.xbar_random.3900664674 | Jul 30 08:46:11 PM PDT 24 | Jul 30 08:46:19 PM PDT 24 | 125326288 ps | ||
| T2935 | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.3750457166 | Jul 30 08:37:49 PM PDT 24 | Jul 30 08:41:57 PM PDT 24 | 24709836077 ps | ||
| T2936 | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.426435813 | Jul 30 08:38:06 PM PDT 24 | Jul 30 08:46:11 PM PDT 24 | 25922236072 ps | ||
| T2937 | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.4009758167 | Jul 30 08:46:38 PM PDT 24 | Jul 30 09:08:54 PM PDT 24 | 81543300463 ps | ||
| T29 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3564229094 | Jul 30 07:43:43 PM PDT 24 | Jul 30 07:47:25 PM PDT 24 | 4508521928 ps | ||
| T30 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.467042597 | Jul 30 07:43:38 PM PDT 24 | Jul 30 07:48:53 PM PDT 24 | 4442429169 ps | ||
| T31 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1147307075 | Jul 30 07:43:41 PM PDT 24 | Jul 30 07:47:30 PM PDT 24 | 4702167171 ps | ||
| T187 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3001041271 | Jul 30 07:43:43 PM PDT 24 | Jul 30 07:47:14 PM PDT 24 | 4563879156 ps | ||
| T188 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1069065890 | Jul 30 07:43:37 PM PDT 24 | Jul 30 07:47:55 PM PDT 24 | 4768234447 ps | ||
| T189 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1489889998 | Jul 30 07:43:38 PM PDT 24 | Jul 30 07:48:11 PM PDT 24 | 4541706749 ps | ||
| T190 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.161434762 | Jul 30 07:43:42 PM PDT 24 | Jul 30 07:47:16 PM PDT 24 | 5175637920 ps | ||
| T191 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1980298062 | Jul 30 07:43:41 PM PDT 24 | Jul 30 07:48:12 PM PDT 24 | 5039946950 ps | ||
| T192 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3350151470 | Jul 30 07:43:41 PM PDT 24 | Jul 30 07:46:31 PM PDT 24 | 4606708688 ps | ||
| T193 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2195269982 | Jul 30 07:43:38 PM PDT 24 | Jul 30 07:47:54 PM PDT 24 | 5365161392 ps |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1848970300 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 78032489220 ps |
| CPU time | 13099.5 seconds |
| Started | Jul 30 07:55:57 PM PDT 24 |
| Finished | Jul 30 11:34:18 PM PDT 24 |
| Peak memory | 633960 kb |
| Host | smart-143d92c9-08a7-48e2-80a7-38007b464281 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1848970300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.1848970300 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2198030863 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 28377907368 ps |
| CPU time | 3463.09 seconds |
| Started | Jul 30 08:31:53 PM PDT 24 |
| Finished | Jul 30 09:29:36 PM PDT 24 |
| Peak memory | 593300 kb |
| Host | smart-1b811534-aad7-4813-84f4-3953039e4764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198030863 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.2198030863 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2205432070 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 127145052532 ps |
| CPU time | 2309.51 seconds |
| Started | Jul 30 08:34:08 PM PDT 24 |
| Finished | Jul 30 09:12:37 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-de85f8c1-0f42-4a61-8c15-f5700a456339 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205432070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.2205432070 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.3460365095 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 6386814250 ps |
| CPU time | 1074.9 seconds |
| Started | Jul 30 08:05:56 PM PDT 24 |
| Finished | Jul 30 08:23:52 PM PDT 24 |
| Peak memory | 608836 kb |
| Host | smart-0c914e4c-e176-4c11-8327-e04d78b40682 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460365095 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.3460365095 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.3669075445 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 157343303646 ps |
| CPU time | 2845.63 seconds |
| Started | Jul 30 08:47:34 PM PDT 24 |
| Finished | Jul 30 09:35:00 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-f6f555f7-fda0-48a4-9b4a-8e93d9c6cdce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669075445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_ device_slow_rsp.3669075445 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3564229094 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4508521928 ps |
| CPU time | 221.7 seconds |
| Started | Jul 30 07:43:43 PM PDT 24 |
| Finished | Jul 30 07:47:25 PM PDT 24 |
| Peak memory | 649188 kb |
| Host | smart-ecaf9cd9-c13c-4f96-8046-872d70ecd63a |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564229094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.3564229094 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.18326251 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 1583887756 ps |
| CPU time | 128.96 seconds |
| Started | Jul 30 08:37:04 PM PDT 24 |
| Finished | Jul 30 08:39:13 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-1917d260-b700-44b6-b23e-66ff79b0cc81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18326251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.18326251 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.4131939149 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 8925640842 ps |
| CPU time | 1274.55 seconds |
| Started | Jul 30 07:58:28 PM PDT 24 |
| Finished | Jul 30 08:19:43 PM PDT 24 |
| Peak memory | 610988 kb |
| Host | smart-a9e9d1f6-d508-4bb8-a1fd-a2841564c9a5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=4131939149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.4131939149 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3074950577 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 13175741584 ps |
| CPU time | 4262.28 seconds |
| Started | Jul 30 07:54:13 PM PDT 24 |
| Finished | Jul 30 09:05:16 PM PDT 24 |
| Peak memory | 610836 kb |
| Host | smart-f726db45-9a21-4732-9d20-554ad51abf50 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30749 50577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.3074950577 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3812870269 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 152234126967 ps |
| CPU time | 2700.39 seconds |
| Started | Jul 30 08:48:07 PM PDT 24 |
| Finished | Jul 30 09:33:08 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-d2fa4459-1127-4f80-8386-aff41e858e72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812870269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.3812870269 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2967405698 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3361408059 ps |
| CPU time | 325.5 seconds |
| Started | Jul 30 07:59:32 PM PDT 24 |
| Finished | Jul 30 08:04:58 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-4952be01-879e-4481-b7c0-7f82187bc28f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967 405698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.2967405698 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3968767379 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 18093814881 ps |
| CPU time | 5769.6 seconds |
| Started | Jul 30 07:59:55 PM PDT 24 |
| Finished | Jul 30 09:36:05 PM PDT 24 |
| Peak memory | 609748 kb |
| Host | smart-15f22993-fa1e-4ca9-afa7-06ad9c0a3241 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3968767379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.3968767379 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3754294049 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 47512767104 ps |
| CPU time | 5584.56 seconds |
| Started | Jul 30 07:52:49 PM PDT 24 |
| Finished | Jul 30 09:25:56 PM PDT 24 |
| Peak memory | 619624 kb |
| Host | smart-402142c9-340d-4c18-8d01-6bfba7b59037 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754294049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.3754294049 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_virus.2574255404 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5695879380 ps |
| CPU time | 1393.25 seconds |
| Started | Jul 30 08:14:23 PM PDT 24 |
| Finished | Jul 30 08:37:38 PM PDT 24 |
| Peak memory | 624964 kb |
| Host | smart-cf731f32-44c3-42d6-83f2-51e495c55595 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2574255404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.2574255404 |
| Directory | /workspace/1.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.3613338559 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 138479798770 ps |
| CPU time | 2449.13 seconds |
| Started | Jul 30 08:39:27 PM PDT 24 |
| Finished | Jul 30 09:20:17 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-f4b85b7e-6711-4918-b1b8-0217f4d205c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613338559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.3613338559 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.482247357 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 7116053094 ps |
| CPU time | 450.64 seconds |
| Started | Jul 30 08:16:16 PM PDT 24 |
| Finished | Jul 30 08:23:47 PM PDT 24 |
| Peak memory | 610364 kb |
| Host | smart-fe407a4d-8db0-4a50-b5bf-2da71973644e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482247357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.482247357 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1835503700 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 3096232034 ps |
| CPU time | 280.81 seconds |
| Started | Jul 30 07:52:03 PM PDT 24 |
| Finished | Jul 30 07:56:44 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-d99ddf14-2891-41ed-90b2-832ee5152afc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1835503700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.1835503700 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3658008823 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 3918178140 ps |
| CPU time | 320.99 seconds |
| Started | Jul 30 08:29:55 PM PDT 24 |
| Finished | Jul 30 08:35:16 PM PDT 24 |
| Peak memory | 649100 kb |
| Host | smart-fb025e1b-155c-48b1-b4e7-aa07e47cb325 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658008823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3658008823 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.2459534467 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 5047847100 ps |
| CPU time | 932.4 seconds |
| Started | Jul 30 07:56:03 PM PDT 24 |
| Finished | Jul 30 08:11:37 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-c6a9712b-d65f-4e32-8eb5-a71cc28d0250 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459534467 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.2459534467 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.11432395 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 7381390470 ps |
| CPU time | 1361.95 seconds |
| Started | Jul 30 08:02:32 PM PDT 24 |
| Finished | Jul 30 08:25:15 PM PDT 24 |
| Peak memory | 610948 kb |
| Host | smart-92a90929-3586-45ba-920e-cb571e401edb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=11432395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.11432395 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.160298614 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 10856044312 ps |
| CPU time | 1127.63 seconds |
| Started | Jul 30 08:34:32 PM PDT 24 |
| Finished | Jul 30 08:53:20 PM PDT 24 |
| Peak memory | 644692 kb |
| Host | smart-c9271b48-cb57-4415-bdd2-c6b902d7e093 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160298614 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.160298614 |
| Directory | /workspace/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2966528526 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 51539195045 ps |
| CPU time | 919.84 seconds |
| Started | Jul 30 08:26:16 PM PDT 24 |
| Finished | Jul 30 08:41:36 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-b6601f46-3291-4506-b2a7-8a350b1efa24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966528526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.2966528526 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.2664933268 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 3466792330 ps |
| CPU time | 533.63 seconds |
| Started | Jul 30 07:53:20 PM PDT 24 |
| Finished | Jul 30 08:02:14 PM PDT 24 |
| Peak memory | 609768 kb |
| Host | smart-2390d7f1-2998-483f-8c72-1a8b69d5fcf2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664933268 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.2664933268 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.1523269658 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 58238830314 ps |
| CPU time | 1021.3 seconds |
| Started | Jul 30 08:36:20 PM PDT 24 |
| Finished | Jul 30 08:53:22 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-0b9ff00e-29a8-4d44-905e-2bf0bbad9df2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523269658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.1523269658 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2368172876 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 125516872073 ps |
| CPU time | 2163.45 seconds |
| Started | Jul 30 08:24:42 PM PDT 24 |
| Finished | Jul 30 09:00:45 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-86770066-178e-4c6b-872f-c5b482ac9d82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368172876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.2368172876 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.3079458556 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 17130966334 ps |
| CPU time | 1825.42 seconds |
| Started | Jul 30 07:57:28 PM PDT 24 |
| Finished | Jul 30 08:27:54 PM PDT 24 |
| Peak memory | 608040 kb |
| Host | smart-8bddb0c5-f469-417d-9726-0e2f05064d0a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079458556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.3079458556 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1153984907 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 11603859390 ps |
| CPU time | 1219.68 seconds |
| Started | Jul 30 08:12:01 PM PDT 24 |
| Finished | Jul 30 08:32:21 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-93a15ddd-8a96-4efd-bdb0-1f8020fcf146 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153984907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.1153984907 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.4072791286 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 44665380309 ps |
| CPU time | 4130.52 seconds |
| Started | Jul 30 07:53:26 PM PDT 24 |
| Finished | Jul 30 09:02:17 PM PDT 24 |
| Peak memory | 620860 kb |
| Host | smart-76b2fd15-c0b6-4196-968f-c8911d4b44a3 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4072791286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.4072791286 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.3683152780 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 5448173275 ps |
| CPU time | 458.48 seconds |
| Started | Jul 30 08:34:51 PM PDT 24 |
| Finished | Jul 30 08:42:30 PM PDT 24 |
| Peak memory | 598680 kb |
| Host | smart-8a778add-3be9-4afe-ab23-46417aaeb4cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683152780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.3683152780 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.2200747961 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2932440921 ps |
| CPU time | 124.12 seconds |
| Started | Jul 30 08:45:18 PM PDT 24 |
| Finished | Jul 30 08:47:22 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-1f992169-7a61-432f-90e8-b65d863a4b27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200747961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .2200747961 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.3786166046 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 99603422165 ps |
| CPU time | 973.61 seconds |
| Started | Jul 30 08:47:27 PM PDT 24 |
| Finished | Jul 30 09:03:40 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-2dfc0de2-d4f5-4894-b978-f4c597a79828 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786166046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.3786166046 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.4263671253 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 223945666 ps |
| CPU time | 61.48 seconds |
| Started | Jul 30 08:35:26 PM PDT 24 |
| Finished | Jul 30 08:36:27 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-681f3486-0686-4ee9-b4ee-a7e244b7cda7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263671253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.4263671253 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.2805266917 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 4025861628 ps |
| CPU time | 584.02 seconds |
| Started | Jul 30 08:08:58 PM PDT 24 |
| Finished | Jul 30 08:18:43 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-546c9daf-9ac7-4f1d-8741-9a016cdb8afb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805266917 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_gpio.2805266917 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2283778065 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 6219875688 ps |
| CPU time | 816.38 seconds |
| Started | Jul 30 08:19:26 PM PDT 24 |
| Finished | Jul 30 08:33:02 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-fd864c19-732b-4804-ae39-89207fec7aa1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22837780 65 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.2283778065 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.799284437 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3357825732 ps |
| CPU time | 381.71 seconds |
| Started | Jul 30 08:08:01 PM PDT 24 |
| Finished | Jul 30 08:14:23 PM PDT 24 |
| Peak memory | 609344 kb |
| Host | smart-59d23742-fed1-45b6-bdaf-e5f7087826ac |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7992 84437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.799284437 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1364530220 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 4702307056 ps |
| CPU time | 427.31 seconds |
| Started | Jul 30 07:52:04 PM PDT 24 |
| Finished | Jul 30 07:59:11 PM PDT 24 |
| Peak memory | 608644 kb |
| Host | smart-194bc783-e22c-4b0b-b0b6-8b28e52cae74 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13645302 20 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1364530220 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.715537131 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 5443549444 ps |
| CPU time | 439.14 seconds |
| Started | Jul 30 08:29:39 PM PDT 24 |
| Finished | Jul 30 08:36:58 PM PDT 24 |
| Peak memory | 650340 kb |
| Host | smart-e4eb167b-920c-4517-a81c-2c3a56e42559 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 715537131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.715537131 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.3738704093 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 20122083142 ps |
| CPU time | 2263.09 seconds |
| Started | Jul 30 08:07:59 PM PDT 24 |
| Finished | Jul 30 08:45:43 PM PDT 24 |
| Peak memory | 608076 kb |
| Host | smart-14fc052c-d404-41a4-a274-4bacef260124 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738704093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.3738704093 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.1630572402 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 16235608215 ps |
| CPU time | 608.63 seconds |
| Started | Jul 30 08:33:47 PM PDT 24 |
| Finished | Jul 30 08:43:56 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-9f252733-d961-4b5f-95bc-87c4fffd912c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630572402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1630572402 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3827595605 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 50977110084 ps |
| CPU time | 6781.98 seconds |
| Started | Jul 30 07:53:17 PM PDT 24 |
| Finished | Jul 30 09:46:22 PM PDT 24 |
| Peak memory | 620536 kb |
| Host | smart-38fa6d0d-d183-4b1a-a102-cd8fbb530a6b |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827595605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_dev.3827595605 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.66299733 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 3651866991 ps |
| CPU time | 154.33 seconds |
| Started | Jul 30 08:47:43 PM PDT 24 |
| Finished | Jul 30 08:50:18 PM PDT 24 |
| Peak memory | 576136 kb |
| Host | smart-762e800f-2150-4ca8-98d6-00918cc6dc33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66299733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device.66299733 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1663870970 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2658456332 ps |
| CPU time | 309.64 seconds |
| Started | Jul 30 07:51:14 PM PDT 24 |
| Finished | Jul 30 07:56:24 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-2abe2cf5-413e-4d09-b615-3084223e78a4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663 870970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.1663870970 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.3226343985 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 5118590074 ps |
| CPU time | 536.6 seconds |
| Started | Jul 30 08:29:44 PM PDT 24 |
| Finished | Jul 30 08:38:41 PM PDT 24 |
| Peak memory | 616936 kb |
| Host | smart-a6a09cdc-1443-46dc-a368-bf92cc305e89 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3226343985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.3226343985 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.331649416 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 4553655030 ps |
| CPU time | 401.73 seconds |
| Started | Jul 30 08:33:53 PM PDT 24 |
| Finished | Jul 30 08:40:34 PM PDT 24 |
| Peak memory | 603728 kb |
| Host | smart-64d62947-83a8-454f-b4b5-b4af213121d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331649416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.331649416 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2308463571 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 6192921434 ps |
| CPU time | 816.1 seconds |
| Started | Jul 30 08:19:12 PM PDT 24 |
| Finished | Jul 30 08:32:49 PM PDT 24 |
| Peak memory | 611064 kb |
| Host | smart-8bb19c03-878d-4e52-aabb-2c0b3a147ae6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2308463571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.2308463571 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3189413241 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 5018590910 ps |
| CPU time | 347.84 seconds |
| Started | Jul 30 08:10:12 PM PDT 24 |
| Finished | Jul 30 08:16:00 PM PDT 24 |
| Peak memory | 609648 kb |
| Host | smart-9e0acea7-df9b-4ae4-b703-28ced8439eaa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31 89413241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.3189413241 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.546196908 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 7411858068 ps |
| CPU time | 1794.33 seconds |
| Started | Jul 30 08:02:19 PM PDT 24 |
| Finished | Jul 30 08:32:14 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-7ee1d802-789e-42d5-9c49-4eec9bfa5c27 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=546196908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.546196908 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3680009205 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 2666718089 ps |
| CPU time | 297.9 seconds |
| Started | Jul 30 08:45:56 PM PDT 24 |
| Finished | Jul 30 08:50:54 PM PDT 24 |
| Peak memory | 576864 kb |
| Host | smart-03be29a7-7b19-40c6-b0b9-2319a8a91b2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680009205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.3680009205 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2920210079 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4255693872 ps |
| CPU time | 324.44 seconds |
| Started | Jul 30 07:51:59 PM PDT 24 |
| Finished | Jul 30 07:57:24 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-f237c7e5-0c65-45b8-b213-9de87e45bf2c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920210079 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.2920210079 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2009944538 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 22226111318 ps |
| CPU time | 1185.6 seconds |
| Started | Jul 30 08:01:18 PM PDT 24 |
| Finished | Jul 30 08:21:04 PM PDT 24 |
| Peak memory | 614776 kb |
| Host | smart-f033c214-c47d-42f4-a71b-39be110fb73d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20099445 38 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.2009944538 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.2154822940 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 749816407 ps |
| CPU time | 201.28 seconds |
| Started | Jul 30 08:38:26 PM PDT 24 |
| Finished | Jul 30 08:41:47 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-3a345e8e-03ab-4cc4-b3c3-07f7b4fec452 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154822940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.2154822940 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3327943765 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 44031866495 ps |
| CPU time | 5691.09 seconds |
| Started | Jul 30 07:55:24 PM PDT 24 |
| Finished | Jul 30 09:30:16 PM PDT 24 |
| Peak memory | 621072 kb |
| Host | smart-20a87501-a195-4640-8b1e-502ac2e8139b |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3327943765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.3327943765 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.3156438580 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 5428093182 ps |
| CPU time | 600.05 seconds |
| Started | Jul 30 08:31:31 PM PDT 24 |
| Finished | Jul 30 08:41:31 PM PDT 24 |
| Peak memory | 649980 kb |
| Host | smart-abaf31d5-0649-44f1-a0b0-9c5dfc6f2281 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3156438580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.3156438580 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.3382655008 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 4479213106 ps |
| CPU time | 641.79 seconds |
| Started | Jul 30 08:23:00 PM PDT 24 |
| Finished | Jul 30 08:33:42 PM PDT 24 |
| Peak memory | 650644 kb |
| Host | smart-a2f171ef-45e0-4f4a-a6b2-acfb76e4fd15 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3382655008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.3382655008 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.3411307158 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 4589335976 ps |
| CPU time | 656.58 seconds |
| Started | Jul 30 08:28:36 PM PDT 24 |
| Finished | Jul 30 08:39:34 PM PDT 24 |
| Peak memory | 650512 kb |
| Host | smart-fa976fa4-034d-485d-b144-3e3fc6adcb8e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3411307158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.3411307158 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3136401051 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 4292602462 ps |
| CPU time | 442.22 seconds |
| Started | Jul 30 08:25:04 PM PDT 24 |
| Finished | Jul 30 08:32:26 PM PDT 24 |
| Peak memory | 648704 kb |
| Host | smart-d45c97d4-d52c-4499-ba78-e0328320a2eb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136401051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3136401051 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.3442341479 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3495449840 ps |
| CPU time | 286.58 seconds |
| Started | Jul 30 08:01:59 PM PDT 24 |
| Finished | Jul 30 08:06:46 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-5766d13f-d67e-461f-8a4b-d4e335ec9d22 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442341479 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.3442341479 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3084077861 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 2559858894 ps |
| CPU time | 146.15 seconds |
| Started | Jul 30 08:09:40 PM PDT 24 |
| Finished | Jul 30 08:12:07 PM PDT 24 |
| Peak memory | 620036 kb |
| Host | smart-64e0e5a2-a9db-4d7a-8e49-78c7308c65ac |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30840778 61 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.3084077861 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.1401045205 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 5538586834 ps |
| CPU time | 522.71 seconds |
| Started | Jul 30 08:29:10 PM PDT 24 |
| Finished | Jul 30 08:37:52 PM PDT 24 |
| Peak memory | 598836 kb |
| Host | smart-9914e44b-cf1a-4388-b0e8-4f4fec054d04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401045205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.1401045205 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1524583029 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 6669280828 ps |
| CPU time | 844.46 seconds |
| Started | Jul 30 07:50:50 PM PDT 24 |
| Finished | Jul 30 08:04:55 PM PDT 24 |
| Peak memory | 610824 kb |
| Host | smart-85cedc16-4934-4253-9d52-ecd59b8fdb2c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1524583029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.1524583029 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_self_hash.4040918753 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 26553591204 ps |
| CPU time | 5794.89 seconds |
| Started | Jul 30 08:24:30 PM PDT 24 |
| Finished | Jul 30 10:01:06 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-c63faa39-cb72-473f-8ab2-76c6543eb438 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040918753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.4040918753 |
| Directory | /workspace/2.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.3203345745 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 6381796856 ps |
| CPU time | 1124.56 seconds |
| Started | Jul 30 07:53:45 PM PDT 24 |
| Finished | Jul 30 08:12:30 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-b53cff1f-9f05-454a-8907-6692d66a6758 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203345745 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.3203345745 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3098436734 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 6138866054 ps |
| CPU time | 381.47 seconds |
| Started | Jul 30 08:26:26 PM PDT 24 |
| Finished | Jul 30 08:32:48 PM PDT 24 |
| Peak memory | 662152 kb |
| Host | smart-6d1ea32a-f3be-4f35-a405-1a9002f87caa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098436734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.3098436734 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.3627146453 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 5702220131 ps |
| CPU time | 537 seconds |
| Started | Jul 30 08:20:02 PM PDT 24 |
| Finished | Jul 30 08:28:59 PM PDT 24 |
| Peak memory | 624584 kb |
| Host | smart-3be6514b-6457-4d0d-b6c6-af56f761c20b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3627146453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.3627146453 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.2308739566 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 10828397788 ps |
| CPU time | 642.97 seconds |
| Started | Jul 30 08:46:41 PM PDT 24 |
| Finished | Jul 30 08:57:24 PM PDT 24 |
| Peak memory | 576868 kb |
| Host | smart-a3b8b907-e45d-48c4-acf7-2f255285e2a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308739566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.2308739566 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.1570180852 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 3405114408 ps |
| CPU time | 278.36 seconds |
| Started | Jul 30 07:52:38 PM PDT 24 |
| Finished | Jul 30 07:57:17 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-0fecc11b-a4a8-4916-b64c-4e321d748bb0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570180852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.1570180852 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.4036765725 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 147105268 ps |
| CPU time | 14.54 seconds |
| Started | Jul 30 08:48:34 PM PDT 24 |
| Finished | Jul 30 08:48:49 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-c74481da-8440-4d01-b506-f4a5d5c8e50e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036765725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.4036765725 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3226735278 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 5837886718 ps |
| CPU time | 510.63 seconds |
| Started | Jul 30 07:55:32 PM PDT 24 |
| Finished | Jul 30 08:04:03 PM PDT 24 |
| Peak memory | 610596 kb |
| Host | smart-ffaf9cc6-e631-4c84-8111-f8cc8812a54f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226735278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.3226735278 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3301773490 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 5353443984 ps |
| CPU time | 407.04 seconds |
| Started | Jul 30 08:07:19 PM PDT 24 |
| Finished | Jul 30 08:14:06 PM PDT 24 |
| Peak memory | 610880 kb |
| Host | smart-06e93059-519f-4840-8497-9934d5f51135 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301773490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.3301773490 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3081111879 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3218311901 ps |
| CPU time | 268.96 seconds |
| Started | Jul 30 07:54:28 PM PDT 24 |
| Finished | Jul 30 07:58:58 PM PDT 24 |
| Peak memory | 617764 kb |
| Host | smart-81aa8ed0-fec1-4d29-8e0e-adc5c20cadaf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081111879 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.3081111879 |
| Directory | /workspace/0.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.1226074485 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11688911440 ps |
| CPU time | 2837 seconds |
| Started | Jul 30 07:52:20 PM PDT 24 |
| Finished | Jul 30 08:39:38 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-6cd032c6-83fb-4586-8738-40b42332ddd4 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1226074485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.1226074485 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.2706712038 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 3718106528 ps |
| CPU time | 555.71 seconds |
| Started | Jul 30 08:41:04 PM PDT 24 |
| Finished | Jul 30 08:50:19 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-75f32af0-f57f-4beb-a367-da661f815461 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706712038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_rand_reset.2706712038 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1901983424 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 5897118060 ps |
| CPU time | 802.61 seconds |
| Started | Jul 30 08:00:50 PM PDT 24 |
| Finished | Jul 30 08:14:13 PM PDT 24 |
| Peak memory | 611060 kb |
| Host | smart-0ea7b0fe-2ac0-4c37-bad4-140b2c43eb38 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901983424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.1901983424 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2384263140 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 3684233925 ps |
| CPU time | 506.66 seconds |
| Started | Jul 30 08:19:23 PM PDT 24 |
| Finished | Jul 30 08:27:51 PM PDT 24 |
| Peak memory | 624444 kb |
| Host | smart-d6627f89-102a-44c8-8d19-516d8b4544ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384263140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.2384263140 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1753187521 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 6555716376 ps |
| CPU time | 682.25 seconds |
| Started | Jul 30 07:52:53 PM PDT 24 |
| Finished | Jul 30 08:04:16 PM PDT 24 |
| Peak memory | 610580 kb |
| Host | smart-bfeb2214-4dda-47cb-adf5-ed76f7aec3a7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17531875 21 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.1753187521 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.3345849296 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 9418379918 ps |
| CPU time | 421.56 seconds |
| Started | Jul 30 08:42:38 PM PDT 24 |
| Finished | Jul 30 08:49:39 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-c9fca60e-7738-4a88-9d78-35f5c4c11d7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345849296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.3345849296 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2718963566 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 5339575510 ps |
| CPU time | 802.62 seconds |
| Started | Jul 30 07:52:59 PM PDT 24 |
| Finished | Jul 30 08:06:22 PM PDT 24 |
| Peak memory | 609864 kb |
| Host | smart-3146aab7-5d2f-448e-9b39-cefd96005527 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718963566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2718963566 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2609669087 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 4777777019 ps |
| CPU time | 609.01 seconds |
| Started | Jul 30 08:37:17 PM PDT 24 |
| Finished | Jul 30 08:47:26 PM PDT 24 |
| Peak memory | 576872 kb |
| Host | smart-df42a85e-011b-464a-a3eb-3a4fb5a19c56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609669087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.2609669087 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1293473035 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 28439920400 ps |
| CPU time | 3283.68 seconds |
| Started | Jul 30 08:32:16 PM PDT 24 |
| Finished | Jul 30 09:27:00 PM PDT 24 |
| Peak memory | 593348 kb |
| Host | smart-15869b8e-9d8e-4a5d-ad44-3c1a5649a9ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293473035 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.1293473035 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.554549210 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 4770923208 ps |
| CPU time | 836.19 seconds |
| Started | Jul 30 08:04:20 PM PDT 24 |
| Finished | Jul 30 08:18:16 PM PDT 24 |
| Peak memory | 608804 kb |
| Host | smart-66d0bc1a-8dbd-43d3-9a50-d87a89725671 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554549210 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_20.554549210 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.3501251696 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 15444252268 ps |
| CPU time | 2103.24 seconds |
| Started | Jul 30 07:56:44 PM PDT 24 |
| Finished | Jul 30 08:31:48 PM PDT 24 |
| Peak memory | 611048 kb |
| Host | smart-7a413f7a-723f-410f-93c2-9971044b4ffd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501251696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.3501251696 |
| Directory | /workspace/0.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.4219548991 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 9444924601 ps |
| CPU time | 567.92 seconds |
| Started | Jul 30 08:40:20 PM PDT 24 |
| Finished | Jul 30 08:49:48 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-f740c434-d7df-4a4c-ab2a-89c2db5cb0fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219548991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.4219548991 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3852102951 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 43177207404 ps |
| CPU time | 5328 seconds |
| Started | Jul 30 08:10:13 PM PDT 24 |
| Finished | Jul 30 09:39:03 PM PDT 24 |
| Peak memory | 621276 kb |
| Host | smart-7fd3ed8b-8675-4c27-a9d9-d9684c08ecd1 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3852102951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.3852102951 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1454499053 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5515086770 ps |
| CPU time | 441.03 seconds |
| Started | Jul 30 08:04:54 PM PDT 24 |
| Finished | Jul 30 08:12:15 PM PDT 24 |
| Peak memory | 620496 kb |
| Host | smart-3a0f4fa7-9678-4766-926c-0a7a338b59d7 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1454499053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.1454499053 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.2260992315 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 3915674424 ps |
| CPU time | 636.1 seconds |
| Started | Jul 30 08:03:45 PM PDT 24 |
| Finished | Jul 30 08:14:22 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-d79e7cf7-2fd9-4a29-b208-9f0cea2fb268 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260992315 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.2260992315 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.1176434830 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 6034597178 ps |
| CPU time | 1136.9 seconds |
| Started | Jul 30 08:13:26 PM PDT 24 |
| Finished | Jul 30 08:32:23 PM PDT 24 |
| Peak memory | 608880 kb |
| Host | smart-9365201f-20ab-40dd-8326-fd23313b9afb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176434830 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.1176434830 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.2465653165 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 6322303722 ps |
| CPU time | 1804.16 seconds |
| Started | Jul 30 08:01:25 PM PDT 24 |
| Finished | Jul 30 08:31:29 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-7e8125b4-4ec3-416f-acec-b62dbcf857db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465653165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.2465653165 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.534213020 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 8509955861 ps |
| CPU time | 551.54 seconds |
| Started | Jul 30 08:40:25 PM PDT 24 |
| Finished | Jul 30 08:49:37 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-004fcbe9-d16a-4d50-bb1d-5215a661d622 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534213020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_ with_rand_reset.534213020 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.3762015772 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 3171808157 ps |
| CPU time | 289.59 seconds |
| Started | Jul 30 08:33:37 PM PDT 24 |
| Finished | Jul 30 08:38:27 PM PDT 24 |
| Peak memory | 603772 kb |
| Host | smart-c10e77b6-55d7-48a7-9e71-671f70742cff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762015772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.3762015772 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2947778028 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2409101380 ps |
| CPU time | 93.01 seconds |
| Started | Jul 30 08:09:21 PM PDT 24 |
| Finished | Jul 30 08:10:55 PM PDT 24 |
| Peak memory | 623056 kb |
| Host | smart-e6614bb5-0ba8-40f7-b492-deea321cb591 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947778028 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.2947778028 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3680184128 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4261524824 ps |
| CPU time | 565.41 seconds |
| Started | Jul 30 07:51:35 PM PDT 24 |
| Finished | Jul 30 08:01:01 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-f9546273-7426-4e65-81af-b656ba78ad6d |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368018 4128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3680184128 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1151670528 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 4834736496 ps |
| CPU time | 548.71 seconds |
| Started | Jul 30 07:56:45 PM PDT 24 |
| Finished | Jul 30 08:05:55 PM PDT 24 |
| Peak memory | 619732 kb |
| Host | smart-fc34f785-5fb2-4f04-9fed-cb00cbee81be |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 151670528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.1151670528 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.804392423 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 4129529500 ps |
| CPU time | 555.68 seconds |
| Started | Jul 30 07:51:37 PM PDT 24 |
| Finished | Jul 30 08:00:54 PM PDT 24 |
| Peak memory | 623440 kb |
| Host | smart-c3c95a9f-1015-4f89-8909-df785c118802 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804392423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_ alt_clk_freq.804392423 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.3868613506 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 4052949432 ps |
| CPU time | 374.38 seconds |
| Started | Jul 30 08:39:40 PM PDT 24 |
| Finished | Jul 30 08:45:55 PM PDT 24 |
| Peak memory | 576820 kb |
| Host | smart-048a02ec-4204-4a2c-894f-7566156a5359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868613506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3868613506 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2944616726 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 13729940481 ps |
| CPU time | 800.38 seconds |
| Started | Jul 30 08:31:29 PM PDT 24 |
| Finished | Jul 30 08:44:49 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-1ef495c6-47dd-4384-a6af-16ca28476d41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944616726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.2944616726 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2599375401 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 622865206 ps |
| CPU time | 230.78 seconds |
| Started | Jul 30 08:32:26 PM PDT 24 |
| Finished | Jul 30 08:36:17 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-cd3b8def-fc51-47ad-9615-9cb043352f8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599375401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.2599375401 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.3093030752 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 4691957586 ps |
| CPU time | 411.81 seconds |
| Started | Jul 30 08:32:30 PM PDT 24 |
| Finished | Jul 30 08:39:21 PM PDT 24 |
| Peak memory | 603804 kb |
| Host | smart-53449590-315f-490a-b138-749c335e4c4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093030752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.3093030752 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1077351736 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 4120803406 ps |
| CPU time | 593.62 seconds |
| Started | Jul 30 07:54:19 PM PDT 24 |
| Finished | Jul 30 08:04:13 PM PDT 24 |
| Peak memory | 624416 kb |
| Host | smart-dd955007-dc1a-4740-ba8c-67c9006a2105 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1077351736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.1077351736 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3198309166 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 3740206616 ps |
| CPU time | 604.46 seconds |
| Started | Jul 30 07:54:50 PM PDT 24 |
| Finished | Jul 30 08:04:55 PM PDT 24 |
| Peak memory | 611960 kb |
| Host | smart-dcb6c15e-ab91-47b9-820a-dc08aec62f02 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198309166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3198309166 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.40715036 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 9685833756 ps |
| CPU time | 374.32 seconds |
| Started | Jul 30 08:33:32 PM PDT 24 |
| Finished | Jul 30 08:39:46 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-33317896-2279-4a8f-a876-768fc1f8f262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40715036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.40715036 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2147980611 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 3908119812 ps |
| CPU time | 629.1 seconds |
| Started | Jul 30 07:52:22 PM PDT 24 |
| Finished | Jul 30 08:02:52 PM PDT 24 |
| Peak memory | 609808 kb |
| Host | smart-ac3ae1f4-b28a-48e1-9ca3-cf6ed4b4de04 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147980611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.2147980611 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.467042597 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4442429169 ps |
| CPU time | 315.17 seconds |
| Started | Jul 30 07:43:38 PM PDT 24 |
| Finished | Jul 30 07:48:53 PM PDT 24 |
| Peak memory | 649264 kb |
| Host | smart-6b0f995a-e96c-46f9-848e-06f6a18d38e8 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467042597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 2.chip_padctrl_attributes.467042597 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3975650039 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 2860023813 ps |
| CPU time | 220.94 seconds |
| Started | Jul 30 08:39:56 PM PDT 24 |
| Finished | Jul 30 08:43:37 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-542c1fa7-6afa-4a7d-80c8-ed376bd304df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975650039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.3975650039 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.3824629043 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 9152689213 ps |
| CPU time | 532.46 seconds |
| Started | Jul 30 08:42:36 PM PDT 24 |
| Finished | Jul 30 08:51:28 PM PDT 24 |
| Peak memory | 576860 kb |
| Host | smart-2ef3bcbd-07cc-462f-b65f-10489a5f33cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824629043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_rand_reset.3824629043 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.543464817 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 5283895808 ps |
| CPU time | 605.26 seconds |
| Started | Jul 30 08:29:49 PM PDT 24 |
| Finished | Jul 30 08:39:54 PM PDT 24 |
| Peak memory | 650244 kb |
| Host | smart-c06e4e8d-643e-4e82-a43e-036f73628815 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 543464817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.543464817 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.3355989761 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 9418768974 ps |
| CPU time | 1025.27 seconds |
| Started | Jul 30 08:39:43 PM PDT 24 |
| Finished | Jul 30 08:56:49 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-3f4bfa42-6690-42cb-94c6-681807de4472 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355989761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.3355989761 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.955101992 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 4158622576 ps |
| CPU time | 853.16 seconds |
| Started | Jul 30 08:14:10 PM PDT 24 |
| Finished | Jul 30 08:28:24 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-979247b8-a127-44a5-b262-b5b6eb646d5d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955101992 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_20.955101992 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.2229703582 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 10242907151 ps |
| CPU time | 825.1 seconds |
| Started | Jul 30 08:33:28 PM PDT 24 |
| Finished | Jul 30 08:47:14 PM PDT 24 |
| Peak memory | 576880 kb |
| Host | smart-a05d0ad5-19ba-405d-a765-181bcc85f895 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229703582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_rand_reset.2229703582 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3935430879 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 25844048805 ps |
| CPU time | 2431.35 seconds |
| Started | Jul 30 07:53:45 PM PDT 24 |
| Finished | Jul 30 08:34:17 PM PDT 24 |
| Peak memory | 613440 kb |
| Host | smart-0cb3190b-17e4-4e5e-ae59-50dc1a9238a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3935430879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.3935430879 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1877482387 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 4663090720 ps |
| CPU time | 440.55 seconds |
| Started | Jul 30 07:52:45 PM PDT 24 |
| Finished | Jul 30 08:00:06 PM PDT 24 |
| Peak memory | 620420 kb |
| Host | smart-3eeb9541-fc70-47b9-9016-b1e23ea84ac6 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187748 2387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1877482387 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.838806262 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 8585004856 ps |
| CPU time | 552.96 seconds |
| Started | Jul 30 08:25:03 PM PDT 24 |
| Finished | Jul 30 08:34:16 PM PDT 24 |
| Peak memory | 661020 kb |
| Host | smart-da417bdb-a852-4017-833d-f75761e167c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838806262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_re set.838806262 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2516267011 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 2012320797 ps |
| CPU time | 96.06 seconds |
| Started | Jul 30 07:52:43 PM PDT 24 |
| Finished | Jul 30 07:54:19 PM PDT 24 |
| Peak memory | 621632 kb |
| Host | smart-58277676-f518-4b1f-8a09-1a7385ac10e0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516267011 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.2516267011 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.2531429585 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 3182505912 ps |
| CPU time | 176.52 seconds |
| Started | Jul 30 08:28:44 PM PDT 24 |
| Finished | Jul 30 08:31:40 PM PDT 24 |
| Peak memory | 603780 kb |
| Host | smart-6c3320f4-25bc-4ecb-8a70-3a24193afa7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531429585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.2531429585 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.1020655599 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 80007117584 ps |
| CPU time | 1328.99 seconds |
| Started | Jul 30 08:35:19 PM PDT 24 |
| Finished | Jul 30 08:57:28 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-bde6b1ae-ff09-4870-92be-152c7806958b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020655599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.1020655599 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.556356135 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 2699186608 ps |
| CPU time | 120.01 seconds |
| Started | Jul 30 08:40:06 PM PDT 24 |
| Finished | Jul 30 08:42:06 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-76655494-5b05-4767-8d4d-a8f4d4605618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556356135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device. 556356135 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.4056773795 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 80221182529 ps |
| CPU time | 1374.8 seconds |
| Started | Jul 30 08:41:03 PM PDT 24 |
| Finished | Jul 30 09:03:58 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-6c9afdc1-f89e-43d4-8fca-cd395ebb60ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056773795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.4056773795 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.1080294829 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 6006486472 ps |
| CPU time | 647.12 seconds |
| Started | Jul 30 08:26:42 PM PDT 24 |
| Finished | Jul 30 08:37:30 PM PDT 24 |
| Peak memory | 650584 kb |
| Host | smart-65dcd159-c7df-40fe-bd20-d852d39d7000 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1080294829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.1080294829 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1378257633 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3524327048 ps |
| CPU time | 429.65 seconds |
| Started | Jul 30 07:58:46 PM PDT 24 |
| Finished | Jul 30 08:05:56 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-81d7fb1f-421d-4ab6-9a26-c2604e6f52e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378257633 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.1378257633 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2515721021 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 1196466528 ps |
| CPU time | 339.55 seconds |
| Started | Jul 30 08:26:19 PM PDT 24 |
| Finished | Jul 30 08:31:58 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-bfeb6167-7a34-4aac-9419-f544b54bc4da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515721021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.2515721021 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1328787028 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 10009994201 ps |
| CPU time | 592.23 seconds |
| Started | Jul 30 08:32:35 PM PDT 24 |
| Finished | Jul 30 08:42:27 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-8c11707b-799d-40f9-94d1-cf4b4c184f39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328787028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.1328787028 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.2342278629 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 2250692966 ps |
| CPU time | 350.08 seconds |
| Started | Jul 30 08:41:07 PM PDT 24 |
| Finished | Jul 30 08:46:57 PM PDT 24 |
| Peak memory | 576832 kb |
| Host | smart-81c0ec3c-0224-48fa-ae77-2e006b00249e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342278629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.2342278629 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.3878284108 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 4338891444 ps |
| CPU time | 508.24 seconds |
| Started | Jul 30 07:50:42 PM PDT 24 |
| Finished | Jul 30 07:59:11 PM PDT 24 |
| Peak memory | 650504 kb |
| Host | smart-b43a7a85-9b53-47d7-801b-e3968f673dda |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3878284108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.3878284108 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3223249418 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 3247881020 ps |
| CPU time | 477.11 seconds |
| Started | Jul 30 08:02:25 PM PDT 24 |
| Finished | Jul 30 08:10:24 PM PDT 24 |
| Peak memory | 649052 kb |
| Host | smart-659ffaeb-a33d-4b61-8bb1-d6b141054780 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223249418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.3223249418 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.1407434064 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 5472107064 ps |
| CPU time | 721.78 seconds |
| Started | Jul 30 07:55:55 PM PDT 24 |
| Finished | Jul 30 08:07:57 PM PDT 24 |
| Peak memory | 649984 kb |
| Host | smart-a6415b4d-7011-4726-b789-f75459772095 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1407434064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.1407434064 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2177562323 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 4147002072 ps |
| CPU time | 414.9 seconds |
| Started | Jul 30 08:21:07 PM PDT 24 |
| Finished | Jul 30 08:28:02 PM PDT 24 |
| Peak memory | 649148 kb |
| Host | smart-5656f44f-a0cc-428b-be21-d02696d80380 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177562323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2177562323 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.1841219968 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 5243310548 ps |
| CPU time | 535.38 seconds |
| Started | Jul 30 08:20:29 PM PDT 24 |
| Finished | Jul 30 08:29:25 PM PDT 24 |
| Peak memory | 650120 kb |
| Host | smart-363a9a32-6a6a-4676-ab35-dd5e006f8963 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1841219968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.1841219968 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3990886439 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 3872996532 ps |
| CPU time | 427.66 seconds |
| Started | Jul 30 08:21:43 PM PDT 24 |
| Finished | Jul 30 08:28:51 PM PDT 24 |
| Peak memory | 649348 kb |
| Host | smart-ecc09bb1-b4e2-4e9c-8778-1ec905b9c02d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990886439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3990886439 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.2799079396 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 6036028560 ps |
| CPU time | 573.08 seconds |
| Started | Jul 30 08:21:09 PM PDT 24 |
| Finished | Jul 30 08:30:43 PM PDT 24 |
| Peak memory | 649964 kb |
| Host | smart-826619e0-abdf-41d3-9273-6a7ffc267d7d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2799079396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.2799079396 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.4272435802 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 4083302120 ps |
| CPU time | 402.06 seconds |
| Started | Jul 30 08:24:53 PM PDT 24 |
| Finished | Jul 30 08:31:35 PM PDT 24 |
| Peak memory | 649028 kb |
| Host | smart-ce1cce65-10b2-4fd1-90e8-e383d5f9ce72 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272435802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4272435802 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2651428590 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 3223179120 ps |
| CPU time | 391.6 seconds |
| Started | Jul 30 08:21:38 PM PDT 24 |
| Finished | Jul 30 08:28:10 PM PDT 24 |
| Peak memory | 648840 kb |
| Host | smart-d1222cbe-c913-4b55-8696-c7eebc6a83e4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651428590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2651428590 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.2836843969 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 5702924852 ps |
| CPU time | 694.27 seconds |
| Started | Jul 30 08:22:20 PM PDT 24 |
| Finished | Jul 30 08:33:55 PM PDT 24 |
| Peak memory | 650372 kb |
| Host | smart-2361f81d-28d3-4182-b514-e1d6543c6f40 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2836843969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.2836843969 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.403139839 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 3820633920 ps |
| CPU time | 453.13 seconds |
| Started | Jul 30 08:22:11 PM PDT 24 |
| Finished | Jul 30 08:29:44 PM PDT 24 |
| Peak memory | 649060 kb |
| Host | smart-80c93a1f-0c63-4a09-a1ce-22837291a41c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403139839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_s w_alert_handler_lpg_sleep_mode_alerts.403139839 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.2475675055 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 4937119920 ps |
| CPU time | 666.09 seconds |
| Started | Jul 30 08:22:58 PM PDT 24 |
| Finished | Jul 30 08:34:05 PM PDT 24 |
| Peak memory | 650260 kb |
| Host | smart-d5093352-728b-4bae-bc23-35ab9aca0f5a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2475675055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.2475675055 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.1058672055 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 4399814424 ps |
| CPU time | 753.26 seconds |
| Started | Jul 30 08:21:55 PM PDT 24 |
| Finished | Jul 30 08:34:29 PM PDT 24 |
| Peak memory | 650036 kb |
| Host | smart-820f20e5-a90e-4084-a050-552f74a7c614 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1058672055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.1058672055 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2828917455 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 3352931440 ps |
| CPU time | 457.49 seconds |
| Started | Jul 30 08:21:49 PM PDT 24 |
| Finished | Jul 30 08:29:26 PM PDT 24 |
| Peak memory | 649120 kb |
| Host | smart-591099cb-d751-4a81-bfff-df73f76591cf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828917455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2828917455 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.4015314726 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 6211844720 ps |
| CPU time | 615.85 seconds |
| Started | Jul 30 08:23:19 PM PDT 24 |
| Finished | Jul 30 08:33:35 PM PDT 24 |
| Peak memory | 650400 kb |
| Host | smart-674fd38f-0bd8-44e8-b9ba-61358ba48d1a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4015314726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.4015314726 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3517710226 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 4027968060 ps |
| CPU time | 395.24 seconds |
| Started | Jul 30 08:22:04 PM PDT 24 |
| Finished | Jul 30 08:28:40 PM PDT 24 |
| Peak memory | 649032 kb |
| Host | smart-290f957b-f0c0-4ed8-b5d5-78db3548c9ff |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517710226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3517710226 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.239502867 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 4609565064 ps |
| CPU time | 634.59 seconds |
| Started | Jul 30 08:22:19 PM PDT 24 |
| Finished | Jul 30 08:32:54 PM PDT 24 |
| Peak memory | 650164 kb |
| Host | smart-4695ab8f-4148-4797-9304-d3c6eb12a4fb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 239502867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.239502867 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.2539155727 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 4998876824 ps |
| CPU time | 553.78 seconds |
| Started | Jul 30 08:21:56 PM PDT 24 |
| Finished | Jul 30 08:31:10 PM PDT 24 |
| Peak memory | 650172 kb |
| Host | smart-a2f9d42d-0847-46a2-a72f-d94e0a1c7869 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2539155727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.2539155727 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.1491184202 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 4561026830 ps |
| CPU time | 751.53 seconds |
| Started | Jul 30 08:09:00 PM PDT 24 |
| Finished | Jul 30 08:21:32 PM PDT 24 |
| Peak memory | 650420 kb |
| Host | smart-52d18e30-3f67-4d98-8eda-c49e84896cea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1491184202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.1491184202 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1370546594 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 4200297324 ps |
| CPU time | 486.94 seconds |
| Started | Jul 30 08:23:00 PM PDT 24 |
| Finished | Jul 30 08:31:07 PM PDT 24 |
| Peak memory | 649012 kb |
| Host | smart-a392bc8a-6445-41d5-80ea-054f18a7440d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370546594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1370546594 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.139677139 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 3776537500 ps |
| CPU time | 326.03 seconds |
| Started | Jul 30 08:23:07 PM PDT 24 |
| Finished | Jul 30 08:28:33 PM PDT 24 |
| Peak memory | 649072 kb |
| Host | smart-fadcdf38-e502-4dc1-ae12-6bd80e73913e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139677139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_s w_alert_handler_lpg_sleep_mode_alerts.139677139 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.1688769777 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 5398210820 ps |
| CPU time | 528.4 seconds |
| Started | Jul 30 08:22:54 PM PDT 24 |
| Finished | Jul 30 08:31:42 PM PDT 24 |
| Peak memory | 650704 kb |
| Host | smart-c5e42e63-7caf-4117-976d-7df9c94ff6fb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1688769777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.1688769777 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.215366085 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 4923312632 ps |
| CPU time | 625.01 seconds |
| Started | Jul 30 08:22:29 PM PDT 24 |
| Finished | Jul 30 08:32:54 PM PDT 24 |
| Peak memory | 650540 kb |
| Host | smart-11fd4653-61a1-4da5-a555-72ee77a76e37 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 215366085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.215366085 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1382047005 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 3723787948 ps |
| CPU time | 404.97 seconds |
| Started | Jul 30 08:23:45 PM PDT 24 |
| Finished | Jul 30 08:30:31 PM PDT 24 |
| Peak memory | 649000 kb |
| Host | smart-1bf1a8fd-f3ad-4722-bebc-c0b88be91ac9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382047005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1382047005 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.3985919407 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 4189211252 ps |
| CPU time | 478.11 seconds |
| Started | Jul 30 08:22:57 PM PDT 24 |
| Finished | Jul 30 08:30:55 PM PDT 24 |
| Peak memory | 650240 kb |
| Host | smart-8c2433b5-22bd-4d94-9777-b5b554153686 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3985919407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.3985919407 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3368539002 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 3556092700 ps |
| CPU time | 344.23 seconds |
| Started | Jul 30 08:24:08 PM PDT 24 |
| Finished | Jul 30 08:29:53 PM PDT 24 |
| Peak memory | 649144 kb |
| Host | smart-f2b19df3-2f6f-4141-a674-e1d86956264c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368539002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3368539002 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.919093902 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 4515799878 ps |
| CPU time | 465.33 seconds |
| Started | Jul 30 08:24:12 PM PDT 24 |
| Finished | Jul 30 08:31:58 PM PDT 24 |
| Peak memory | 649352 kb |
| Host | smart-5de065b5-36fa-43f0-9c16-6fef36bfaa32 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919093902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_s w_alert_handler_lpg_sleep_mode_alerts.919093902 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.658076717 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 5448670366 ps |
| CPU time | 607.3 seconds |
| Started | Jul 30 08:26:35 PM PDT 24 |
| Finished | Jul 30 08:36:43 PM PDT 24 |
| Peak memory | 650284 kb |
| Host | smart-59222122-2061-4397-b9a6-d9925ec79851 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 658076717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.658076717 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1090568294 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 4270724964 ps |
| CPU time | 502.36 seconds |
| Started | Jul 30 08:26:53 PM PDT 24 |
| Finished | Jul 30 08:35:15 PM PDT 24 |
| Peak memory | 649092 kb |
| Host | smart-9b65f65e-b178-4959-81ce-527df2e10bee |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090568294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1090568294 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.162733299 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 6259112764 ps |
| CPU time | 572.55 seconds |
| Started | Jul 30 08:26:42 PM PDT 24 |
| Finished | Jul 30 08:36:15 PM PDT 24 |
| Peak memory | 650044 kb |
| Host | smart-d6baa0d5-dd01-44a8-9e73-5864bd81e675 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 162733299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.162733299 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.284311165 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 4073111100 ps |
| CPU time | 466.52 seconds |
| Started | Jul 30 08:23:35 PM PDT 24 |
| Finished | Jul 30 08:31:22 PM PDT 24 |
| Peak memory | 648708 kb |
| Host | smart-4dcece12-a5b7-4b37-ab2c-e811842b3c55 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284311165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_s w_alert_handler_lpg_sleep_mode_alerts.284311165 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.3683452387 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 6093384378 ps |
| CPU time | 915.86 seconds |
| Started | Jul 30 08:24:07 PM PDT 24 |
| Finished | Jul 30 08:39:23 PM PDT 24 |
| Peak memory | 650408 kb |
| Host | smart-796326d7-b6e7-4651-9494-d338d6074a8d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3683452387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.3683452387 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.643015153 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 3450897160 ps |
| CPU time | 460.1 seconds |
| Started | Jul 30 08:19:26 PM PDT 24 |
| Finished | Jul 30 08:27:06 PM PDT 24 |
| Peak memory | 648944 kb |
| Host | smart-fc917d9d-7fa4-4371-8df7-5cf27adb5be6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643015153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw _alert_handler_lpg_sleep_mode_alerts.643015153 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.1652776658 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 5849516372 ps |
| CPU time | 727.39 seconds |
| Started | Jul 30 08:20:04 PM PDT 24 |
| Finished | Jul 30 08:32:12 PM PDT 24 |
| Peak memory | 650364 kb |
| Host | smart-0a175d64-e85e-429c-910f-98a503855211 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1652776658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.1652776658 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1270568470 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 3725789056 ps |
| CPU time | 414.11 seconds |
| Started | Jul 30 08:24:27 PM PDT 24 |
| Finished | Jul 30 08:31:21 PM PDT 24 |
| Peak memory | 648712 kb |
| Host | smart-e0b4cca0-7f02-475c-af65-4bf974b9f38c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270568470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1270568470 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.102750837 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 4027313368 ps |
| CPU time | 449.49 seconds |
| Started | Jul 30 08:24:18 PM PDT 24 |
| Finished | Jul 30 08:31:48 PM PDT 24 |
| Peak memory | 649668 kb |
| Host | smart-708b40ea-d819-4715-8c30-39ffd54f5380 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102750837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_s w_alert_handler_lpg_sleep_mode_alerts.102750837 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.3128415721 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 6144832908 ps |
| CPU time | 723.7 seconds |
| Started | Jul 30 08:23:51 PM PDT 24 |
| Finished | Jul 30 08:35:55 PM PDT 24 |
| Peak memory | 650016 kb |
| Host | smart-2578b4c2-d893-4c5d-aaaf-6c146786542e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3128415721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.3128415721 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.54885979 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 5746192500 ps |
| CPU time | 594.48 seconds |
| Started | Jul 30 08:24:29 PM PDT 24 |
| Finished | Jul 30 08:34:23 PM PDT 24 |
| Peak memory | 650032 kb |
| Host | smart-01f3c27b-5385-4435-a5bd-8edc7cb91f46 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 54885979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.54885979 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1397009690 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 3456867408 ps |
| CPU time | 477.97 seconds |
| Started | Jul 30 08:24:17 PM PDT 24 |
| Finished | Jul 30 08:32:15 PM PDT 24 |
| Peak memory | 649100 kb |
| Host | smart-726dc7ef-c922-4aa9-8812-c0223c4c18af |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397009690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1397009690 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3215727559 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 3854755452 ps |
| CPU time | 411.67 seconds |
| Started | Jul 30 08:29:01 PM PDT 24 |
| Finished | Jul 30 08:35:52 PM PDT 24 |
| Peak memory | 649020 kb |
| Host | smart-fe9149b4-5e38-41df-b37d-5fcb4cacd3d6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215727559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3215727559 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.2500849457 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 4121353710 ps |
| CPU time | 525.37 seconds |
| Started | Jul 30 08:25:52 PM PDT 24 |
| Finished | Jul 30 08:34:37 PM PDT 24 |
| Peak memory | 649996 kb |
| Host | smart-9806f424-d359-41e8-b916-737e6e6ead7f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2500849457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.2500849457 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.315481843 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 4153925568 ps |
| CPU time | 363.98 seconds |
| Started | Jul 30 08:24:47 PM PDT 24 |
| Finished | Jul 30 08:30:51 PM PDT 24 |
| Peak memory | 648768 kb |
| Host | smart-051201f4-d957-4f6a-b7da-a1f16d22ab4c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315481843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_s w_alert_handler_lpg_sleep_mode_alerts.315481843 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1790193160 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 3729896130 ps |
| CPU time | 373.97 seconds |
| Started | Jul 30 08:21:11 PM PDT 24 |
| Finished | Jul 30 08:27:25 PM PDT 24 |
| Peak memory | 648972 kb |
| Host | smart-4b864706-dd51-44af-adb2-aab46129a049 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790193160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.1790193160 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3836051272 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 4032244832 ps |
| CPU time | 383.49 seconds |
| Started | Jul 30 08:25:17 PM PDT 24 |
| Finished | Jul 30 08:31:40 PM PDT 24 |
| Peak memory | 649008 kb |
| Host | smart-ffe865cf-a304-4f47-b389-b138f0ae6f9f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836051272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3836051272 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.3241790210 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 4461429384 ps |
| CPU time | 703.61 seconds |
| Started | Jul 30 08:26:27 PM PDT 24 |
| Finished | Jul 30 08:38:11 PM PDT 24 |
| Peak memory | 650260 kb |
| Host | smart-d20f63f3-258b-4a12-aa53-c85e380bfb17 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3241790210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.3241790210 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3596222846 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 3547327320 ps |
| CPU time | 377.59 seconds |
| Started | Jul 30 08:27:04 PM PDT 24 |
| Finished | Jul 30 08:33:22 PM PDT 24 |
| Peak memory | 648172 kb |
| Host | smart-29c8b45e-f308-4ab3-a63e-5b24d1357315 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596222846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3596222846 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.64476643 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 5626382400 ps |
| CPU time | 504.53 seconds |
| Started | Jul 30 08:26:38 PM PDT 24 |
| Finished | Jul 30 08:35:03 PM PDT 24 |
| Peak memory | 650360 kb |
| Host | smart-2b7c974b-4adf-4724-8908-d9173e1327ae |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 64476643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.64476643 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1972149571 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 4062105744 ps |
| CPU time | 440 seconds |
| Started | Jul 30 08:24:55 PM PDT 24 |
| Finished | Jul 30 08:32:15 PM PDT 24 |
| Peak memory | 649268 kb |
| Host | smart-4056389e-9d9b-4274-b5c5-1c6a2586c73f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972149571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1972149571 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.2987649249 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 5087384780 ps |
| CPU time | 635.63 seconds |
| Started | Jul 30 08:25:07 PM PDT 24 |
| Finished | Jul 30 08:35:43 PM PDT 24 |
| Peak memory | 650384 kb |
| Host | smart-f76189a9-0fae-4053-a41d-13e2e6c10c0d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2987649249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.2987649249 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.4257081564 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 3084902040 ps |
| CPU time | 429.01 seconds |
| Started | Jul 30 08:26:39 PM PDT 24 |
| Finished | Jul 30 08:33:48 PM PDT 24 |
| Peak memory | 649516 kb |
| Host | smart-8f0efdfb-95f1-41ec-85d4-5d23783f09e6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257081564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4257081564 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.3279563272 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 6561780838 ps |
| CPU time | 819.94 seconds |
| Started | Jul 30 08:27:10 PM PDT 24 |
| Finished | Jul 30 08:40:50 PM PDT 24 |
| Peak memory | 650408 kb |
| Host | smart-2f5899c0-556a-4ecc-a892-2016ee42677f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3279563272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.3279563272 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1101287815 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 3143818328 ps |
| CPU time | 319.64 seconds |
| Started | Jul 30 08:20:16 PM PDT 24 |
| Finished | Jul 30 08:25:36 PM PDT 24 |
| Peak memory | 648772 kb |
| Host | smart-ad8405e3-c9c2-441a-901a-0f06bd8b60fd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101287815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.1101287815 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.160402610 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 4823304412 ps |
| CPU time | 707.26 seconds |
| Started | Jul 30 08:27:27 PM PDT 24 |
| Finished | Jul 30 08:39:15 PM PDT 24 |
| Peak memory | 650356 kb |
| Host | smart-6cf605c8-e56d-45cb-8233-fb7f3d23e89d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 160402610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.160402610 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.1896722688 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 6369845992 ps |
| CPU time | 824.54 seconds |
| Started | Jul 30 08:27:06 PM PDT 24 |
| Finished | Jul 30 08:40:51 PM PDT 24 |
| Peak memory | 650324 kb |
| Host | smart-4b3612fb-c2c7-4d72-bf9c-fd4787b59e64 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1896722688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.1896722688 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3431718636 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 3876583736 ps |
| CPU time | 524.11 seconds |
| Started | Jul 30 08:27:46 PM PDT 24 |
| Finished | Jul 30 08:36:30 PM PDT 24 |
| Peak memory | 649104 kb |
| Host | smart-8a4356bb-01a0-4c4d-8de0-126cddb90c73 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431718636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3431718636 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1504094840 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 4197339528 ps |
| CPU time | 385.39 seconds |
| Started | Jul 30 08:26:28 PM PDT 24 |
| Finished | Jul 30 08:32:54 PM PDT 24 |
| Peak memory | 649056 kb |
| Host | smart-2adffc0d-345b-4f2b-9ead-c88ebd1d7ec2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504094840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1504094840 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.776780359 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 3959530712 ps |
| CPU time | 438.47 seconds |
| Started | Jul 30 08:28:35 PM PDT 24 |
| Finished | Jul 30 08:35:54 PM PDT 24 |
| Peak memory | 649104 kb |
| Host | smart-c985187f-a31a-42a7-b4e8-5e2573a2e1c8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776780359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_s w_alert_handler_lpg_sleep_mode_alerts.776780359 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.258621132 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 4142816872 ps |
| CPU time | 440.47 seconds |
| Started | Jul 30 08:26:47 PM PDT 24 |
| Finished | Jul 30 08:34:08 PM PDT 24 |
| Peak memory | 649124 kb |
| Host | smart-36ec6637-feef-4109-bc36-9dc5dbed4d2c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258621132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_s w_alert_handler_lpg_sleep_mode_alerts.258621132 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.1288763491 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 5480862340 ps |
| CPU time | 700 seconds |
| Started | Jul 30 08:28:48 PM PDT 24 |
| Finished | Jul 30 08:40:28 PM PDT 24 |
| Peak memory | 650636 kb |
| Host | smart-e7794c94-8ee9-4db4-b221-51b9887cfacc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1288763491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.1288763491 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.3500385895 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 6538233768 ps |
| CPU time | 564.5 seconds |
| Started | Jul 30 08:30:28 PM PDT 24 |
| Finished | Jul 30 08:39:52 PM PDT 24 |
| Peak memory | 649736 kb |
| Host | smart-78c83c52-0b73-4bbf-b565-ea0cf2e3d26a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3500385895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.3500385895 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.1906067226 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 5875468500 ps |
| CPU time | 643.58 seconds |
| Started | Jul 30 08:28:23 PM PDT 24 |
| Finished | Jul 30 08:39:06 PM PDT 24 |
| Peak memory | 650084 kb |
| Host | smart-09eb7a88-62cd-4d4f-86aa-c4e6d9ba4976 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1906067226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.1906067226 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3699404524 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 3855458700 ps |
| CPU time | 390.75 seconds |
| Started | Jul 30 08:20:20 PM PDT 24 |
| Finished | Jul 30 08:26:51 PM PDT 24 |
| Peak memory | 649024 kb |
| Host | smart-da70cd79-d2c7-44bb-a4ed-f5fb0b5d6af8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699404524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.3699404524 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.1983016217 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 6151838440 ps |
| CPU time | 661.65 seconds |
| Started | Jul 30 08:21:15 PM PDT 24 |
| Finished | Jul 30 08:32:17 PM PDT 24 |
| Peak memory | 650200 kb |
| Host | smart-6b79a3be-a62c-4c1b-9331-210428874d88 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1983016217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.1983016217 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3313344054 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 4397380100 ps |
| CPU time | 461.83 seconds |
| Started | Jul 30 08:29:06 PM PDT 24 |
| Finished | Jul 30 08:36:48 PM PDT 24 |
| Peak memory | 649552 kb |
| Host | smart-f8cc74ed-8b88-48b4-8db7-d2f8b0e7aeee |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313344054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3313344054 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.2660994187 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 5336261880 ps |
| CPU time | 477.51 seconds |
| Started | Jul 30 08:31:13 PM PDT 24 |
| Finished | Jul 30 08:39:10 PM PDT 24 |
| Peak memory | 649888 kb |
| Host | smart-75201f3d-067a-43e2-8b08-c087762fa16f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2660994187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.2660994187 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3642292067 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 4436728614 ps |
| CPU time | 437.88 seconds |
| Started | Jul 30 08:30:10 PM PDT 24 |
| Finished | Jul 30 08:37:28 PM PDT 24 |
| Peak memory | 649712 kb |
| Host | smart-488fe338-12d0-4ddd-840a-fa9fbfa64de6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642292067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3642292067 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1935947341 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 3723340240 ps |
| CPU time | 381.02 seconds |
| Started | Jul 30 08:29:48 PM PDT 24 |
| Finished | Jul 30 08:36:09 PM PDT 24 |
| Peak memory | 649024 kb |
| Host | smart-53bbd332-205e-4040-b588-34a1f5d63830 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935947341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1935947341 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3657137297 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 3615860468 ps |
| CPU time | 371.15 seconds |
| Started | Jul 30 08:32:02 PM PDT 24 |
| Finished | Jul 30 08:38:14 PM PDT 24 |
| Peak memory | 649000 kb |
| Host | smart-ebc961aa-b4cd-4133-9014-d45932526ae2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657137297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3657137297 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.958154765 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 3749142649 ps |
| CPU time | 289.22 seconds |
| Started | Jul 30 08:36:09 PM PDT 24 |
| Finished | Jul 30 08:40:58 PM PDT 24 |
| Peak memory | 603632 kb |
| Host | smart-d207b848-6373-4643-a63e-363ba8bc6f3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958154765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.958154765 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.1596265314 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3973290806 ps |
| CPU time | 548.11 seconds |
| Started | Jul 30 07:53:00 PM PDT 24 |
| Finished | Jul 30 08:02:09 PM PDT 24 |
| Peak memory | 609260 kb |
| Host | smart-38cc2ee5-08f3-46f9-860d-849cec1528b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596265314 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.1596265314 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2046641095 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 3966753526 ps |
| CPU time | 455.2 seconds |
| Started | Jul 30 07:54:44 PM PDT 24 |
| Finished | Jul 30 08:02:20 PM PDT 24 |
| Peak memory | 609440 kb |
| Host | smart-fe133e58-c00a-4ceb-9fec-e347e947bbe8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046641095 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.2046641095 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1252038379 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 5998779944 ps |
| CPU time | 350.62 seconds |
| Started | Jul 30 07:52:46 PM PDT 24 |
| Finished | Jul 30 07:58:37 PM PDT 24 |
| Peak memory | 611224 kb |
| Host | smart-5da31d6c-1d85-470c-a39c-50eadfade7b0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1252038379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.1252038379 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2224859267 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 4193025280 ps |
| CPU time | 783.87 seconds |
| Started | Jul 30 07:51:29 PM PDT 24 |
| Finished | Jul 30 08:04:33 PM PDT 24 |
| Peak memory | 623784 kb |
| Host | smart-d25d939c-155f-43fa-83bb-30fb1a5c5665 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224859267 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.2224859267 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.3171970849 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 3853118944 ps |
| CPU time | 517.06 seconds |
| Started | Jul 30 08:14:04 PM PDT 24 |
| Finished | Jul 30 08:22:41 PM PDT 24 |
| Peak memory | 609752 kb |
| Host | smart-e01187c7-15f9-4b41-bc6c-a43a5cf59222 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171970849 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.3171970849 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.2938604204 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 5625018490 ps |
| CPU time | 568.16 seconds |
| Started | Jul 30 08:26:21 PM PDT 24 |
| Finished | Jul 30 08:35:50 PM PDT 24 |
| Peak memory | 610996 kb |
| Host | smart-fb196b1b-cda1-4c24-a669-e83f960c59a3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2938604204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.2938604204 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2103758477 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 12110541374 ps |
| CPU time | 761.32 seconds |
| Started | Jul 30 07:51:17 PM PDT 24 |
| Finished | Jul 30 08:03:59 PM PDT 24 |
| Peak memory | 620492 kb |
| Host | smart-d1240aee-c32b-46dc-aafd-9d4617ca07aa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103758477 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.2103758477 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2951073979 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 8184903694 ps |
| CPU time | 531.03 seconds |
| Started | Jul 30 07:51:16 PM PDT 24 |
| Finished | Jul 30 08:00:07 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-3da65b4c-b802-4b2d-9b5c-70835c69cc99 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951073979 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.2951073979 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.550741887 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 3181550690 ps |
| CPU time | 382.24 seconds |
| Started | Jul 30 07:53:21 PM PDT 24 |
| Finished | Jul 30 07:59:44 PM PDT 24 |
| Peak memory | 609548 kb |
| Host | smart-f28b9c6b-2920-4e0f-80a7-e30c6b867438 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550741887 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_plic_sw_irq.550741887 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2542761602 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 2418137712 ps |
| CPU time | 177.66 seconds |
| Started | Jul 30 07:55:12 PM PDT 24 |
| Finished | Jul 30 07:58:10 PM PDT 24 |
| Peak memory | 641996 kb |
| Host | smart-d0846732-590c-4a03-81cb-0e58a9bf83a6 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542761602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.2542761602 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3774328063 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 24919358480 ps |
| CPU time | 2149.91 seconds |
| Started | Jul 30 07:53:53 PM PDT 24 |
| Finished | Jul 30 08:29:43 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-13d0fdf1-3fd9-4e49-a988-c3db34d6ca0d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3774328063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3774328063 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4059363166 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 5400347771 ps |
| CPU time | 648.82 seconds |
| Started | Jul 30 07:53:57 PM PDT 24 |
| Finished | Jul 30 08:04:46 PM PDT 24 |
| Peak memory | 624424 kb |
| Host | smart-2b24c55e-8593-490a-a1b6-1c7f07894279 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059363166 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.4059363166 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.3099269673 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 3342572893 ps |
| CPU time | 164.05 seconds |
| Started | Jul 30 08:32:19 PM PDT 24 |
| Finished | Jul 30 08:35:04 PM PDT 24 |
| Peak memory | 603792 kb |
| Host | smart-3b900f9a-7c04-48cf-be72-a629e8e346ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099269673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.3099269673 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.2604567717 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 2243364191 ps |
| CPU time | 219.72 seconds |
| Started | Jul 30 08:43:54 PM PDT 24 |
| Finished | Jul 30 08:47:34 PM PDT 24 |
| Peak memory | 576848 kb |
| Host | smart-7cf0a8c5-262f-4f38-bfc5-b3fcba6bd4dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604567717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.2604567717 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.1545327391 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 4993577404 ps |
| CPU time | 241.53 seconds |
| Started | Jul 30 08:28:08 PM PDT 24 |
| Finished | Jul 30 08:32:09 PM PDT 24 |
| Peak memory | 663716 kb |
| Host | smart-10a26bb7-b9be-4827-90b1-0cb5f66c90c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545327391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.1545327391 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.782235425 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 18074443100 ps |
| CPU time | 648.08 seconds |
| Started | Jul 30 07:53:32 PM PDT 24 |
| Finished | Jul 30 08:04:21 PM PDT 24 |
| Peak memory | 619300 kb |
| Host | smart-271cce0d-45af-45f7-b008-04cfa11e4d46 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=782235425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.782235425 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.163627864 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 6611090046 ps |
| CPU time | 577.92 seconds |
| Started | Jul 30 08:32:31 PM PDT 24 |
| Finished | Jul 30 08:42:09 PM PDT 24 |
| Peak memory | 637568 kb |
| Host | smart-a8e85e08-5d11-4530-9155-f99e81c4ea7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163627864 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.163627864 |
| Directory | /workspace/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2907280936 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 12232811120 ps |
| CPU time | 3009.44 seconds |
| Started | Jul 30 07:52:58 PM PDT 24 |
| Finished | Jul 30 08:43:08 PM PDT 24 |
| Peak memory | 611132 kb |
| Host | smart-07faaa8d-c551-4273-9510-ed111d643d37 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290728 0936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.2907280936 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1944088546 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 4377807502 ps |
| CPU time | 469.01 seconds |
| Started | Jul 30 07:53:33 PM PDT 24 |
| Finished | Jul 30 08:01:22 PM PDT 24 |
| Peak memory | 611100 kb |
| Host | smart-26788759-f89c-4602-bf76-423bcad95137 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1944088546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.1944088546 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.20268768 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 48170607882 ps |
| CPU time | 5832.03 seconds |
| Started | Jul 30 07:53:21 PM PDT 24 |
| Finished | Jul 30 09:30:35 PM PDT 24 |
| Peak memory | 620332 kb |
| Host | smart-e02ee4d9-d4ea-40ae-aa73-762c44f6e50f |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20268768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_lc_walkthrough_prod.20268768 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1499470937 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 24517391852 ps |
| CPU time | 3682.07 seconds |
| Started | Jul 30 07:56:33 PM PDT 24 |
| Finished | Jul 30 08:57:56 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-8ac32774-2193-4562-a250-36f681348a89 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499470937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.1499470937 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.415934361 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 8376421612 ps |
| CPU time | 536.85 seconds |
| Started | Jul 30 07:51:02 PM PDT 24 |
| Finished | Jul 30 07:59:59 PM PDT 24 |
| Peak memory | 616688 kb |
| Host | smart-97f6b0fb-29ef-47ac-8bc1-2e28a2ecd8a7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=415934361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.415934361 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.348094576 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 2739016866 ps |
| CPU time | 258 seconds |
| Started | Jul 30 07:57:33 PM PDT 24 |
| Finished | Jul 30 08:01:51 PM PDT 24 |
| Peak memory | 623892 kb |
| Host | smart-a63e432b-993e-497d-8fb2-080b550c8a3d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348094576 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.348094576 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.4112069172 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 4214777460 ps |
| CPU time | 397.6 seconds |
| Started | Jul 30 08:31:05 PM PDT 24 |
| Finished | Jul 30 08:37:43 PM PDT 24 |
| Peak memory | 598776 kb |
| Host | smart-19e44cd5-5097-4473-b6f0-21c02ed70645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112069172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.4112069172 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.4017126016 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 6182044715 ps |
| CPU time | 347.12 seconds |
| Started | Jul 30 08:41:28 PM PDT 24 |
| Finished | Jul 30 08:47:15 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-38b93c5f-1970-4aea-85ae-61498f3935f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017126016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.4017126016 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.3976226935 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 1518366933 ps |
| CPU time | 65.94 seconds |
| Started | Jul 30 08:43:05 PM PDT 24 |
| Finished | Jul 30 08:44:11 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-c7bcbe60-7773-4cc9-8e00-ea96b5ca40aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976226935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.3976226935 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.4190580276 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 16649910222 ps |
| CPU time | 605.96 seconds |
| Started | Jul 30 08:45:25 PM PDT 24 |
| Finished | Jul 30 08:55:31 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-2064ac1b-82a3-46ee-9b42-98329a20b0d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190580276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.4190580276 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.1485820929 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3319575588 ps |
| CPU time | 233.06 seconds |
| Started | Jul 30 08:30:56 PM PDT 24 |
| Finished | Jul 30 08:34:49 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-b9039a1b-de0b-4018-b0b4-189c7ed0aafd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485820929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1485820929 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.2571091280 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 1935958253 ps |
| CPU time | 72.88 seconds |
| Started | Jul 30 08:47:55 PM PDT 24 |
| Finished | Jul 30 08:49:08 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-d3f8e601-1688-4337-80b1-fc71305135f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571091280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.2571091280 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.520726696 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 9196584351 ps |
| CPU time | 361.2 seconds |
| Started | Jul 30 08:48:13 PM PDT 24 |
| Finished | Jul 30 08:54:14 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-4337baaf-3f5d-45ac-8031-d4c26ee33791 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520726696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.520726696 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1836306545 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 2483933455 ps |
| CPU time | 225.99 seconds |
| Started | Jul 30 07:55:35 PM PDT 24 |
| Finished | Jul 30 07:59:21 PM PDT 24 |
| Peak memory | 609712 kb |
| Host | smart-fc7eb183-c209-4704-9e29-713b4541d869 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836306545 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.1836306545 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2386179642 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 4027157556 ps |
| CPU time | 637.69 seconds |
| Started | Jul 30 07:54:15 PM PDT 24 |
| Finished | Jul 30 08:04:55 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-a91bb869-eae9-41ea-833a-8bd12553e35c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386179642 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.2386179642 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.300962258 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 11082294544 ps |
| CPU time | 1802.4 seconds |
| Started | Jul 30 07:53:43 PM PDT 24 |
| Finished | Jul 30 08:23:47 PM PDT 24 |
| Peak memory | 610968 kb |
| Host | smart-4acbbdb5-c419-4a31-80be-35a2ddda0ff5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=300962258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.300962258 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1092757251 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 5130896168 ps |
| CPU time | 791.82 seconds |
| Started | Jul 30 07:52:46 PM PDT 24 |
| Finished | Jul 30 08:05:58 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-da855cca-6f80-4295-b7f3-a1d5cfbe8092 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10927 57251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.1092757251 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.827645951 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 3909000529 ps |
| CPU time | 468.68 seconds |
| Started | Jul 30 07:54:33 PM PDT 24 |
| Finished | Jul 30 08:02:23 PM PDT 24 |
| Peak memory | 624832 kb |
| Host | smart-c778a37e-687b-4e09-aa18-59da5ee0735c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827645951 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.827645951 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.720367553 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3705440870 ps |
| CPU time | 350.69 seconds |
| Started | Jul 30 08:05:19 PM PDT 24 |
| Finished | Jul 30 08:11:11 PM PDT 24 |
| Peak memory | 609676 kb |
| Host | smart-07da2a81-f797-48a0-bd34-e76df82c49b3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720367553 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.720367553 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.823841988 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 9701690405 ps |
| CPU time | 449.37 seconds |
| Started | Jul 30 08:24:10 PM PDT 24 |
| Finished | Jul 30 08:31:40 PM PDT 24 |
| Peak memory | 592328 kb |
| Host | smart-c04436fd-b6b3-4f86-a43f-f1782b6f3ecf |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823841988 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.chip_rv_dm_lc_disabled.823841988 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.471702525 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 3216715320 ps |
| CPU time | 250.39 seconds |
| Started | Jul 30 07:52:01 PM PDT 24 |
| Finished | Jul 30 07:56:12 PM PDT 24 |
| Peak memory | 609440 kb |
| Host | smart-b0a96557-6a2a-4445-8ad0-d0ff28fc3669 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471702525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.471702525 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.516957575 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 8423305570 ps |
| CPU time | 1228.58 seconds |
| Started | Jul 30 07:52:25 PM PDT 24 |
| Finished | Jul 30 08:12:54 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-ee155030-af82-4af1-a38c-ecf25750a71d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=516957575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.516957575 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.5353360 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 3183805000 ps |
| CPU time | 487.24 seconds |
| Started | Jul 30 07:52:14 PM PDT 24 |
| Finished | Jul 30 08:00:21 PM PDT 24 |
| Peak memory | 609996 kb |
| Host | smart-a77a1716-1091-48db-bc3b-4c06a3369302 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5353360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_boo t_mode.5353360 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2514183003 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 29451113284 ps |
| CPU time | 6745.12 seconds |
| Started | Jul 30 08:20:49 PM PDT 24 |
| Finished | Jul 30 10:13:15 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-01ffb458-7db8-4922-a81b-45d2694410f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514183003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.2514183003 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.389868583 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 24413979312 ps |
| CPU time | 7451.14 seconds |
| Started | Jul 30 08:00:05 PM PDT 24 |
| Finished | Jul 30 10:04:17 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-6a2380d9-e277-4b84-a30e-4655965d8e8c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=389868583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.389868583 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2051277323 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 3131407688 ps |
| CPU time | 308.83 seconds |
| Started | Jul 30 08:05:57 PM PDT 24 |
| Finished | Jul 30 08:11:06 PM PDT 24 |
| Peak memory | 640040 kb |
| Host | smart-dd5624fc-fcbf-4972-bf12-cc31494708f7 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051277323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.2051277323 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1646984451 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 28231599857 ps |
| CPU time | 4839.69 seconds |
| Started | Jul 30 08:24:01 PM PDT 24 |
| Finished | Jul 30 09:44:42 PM PDT 24 |
| Peak memory | 594172 kb |
| Host | smart-37299328-19f7-4337-87ec-198fa452ca85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646984451 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.chip_csr_aliasing.1646984451 |
| Directory | /workspace/0.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2598253781 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 6210224522 ps |
| CPU time | 643.9 seconds |
| Started | Jul 30 08:24:08 PM PDT 24 |
| Finished | Jul 30 08:34:52 PM PDT 24 |
| Peak memory | 590484 kb |
| Host | smart-3394490b-57a4-4b97-b981-2658fec5564d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598253781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.2598253781 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1473243216 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 7990643310 ps |
| CPU time | 601.35 seconds |
| Started | Jul 30 08:25:21 PM PDT 24 |
| Finished | Jul 30 08:35:23 PM PDT 24 |
| Peak memory | 638676 kb |
| Host | smart-a3e57f04-4445-4d02-b2da-625c17203c1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473243216 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.1473243216 |
| Directory | /workspace/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.3715005785 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 4291850000 ps |
| CPU time | 376.87 seconds |
| Started | Jul 30 08:25:09 PM PDT 24 |
| Finished | Jul 30 08:31:26 PM PDT 24 |
| Peak memory | 598180 kb |
| Host | smart-568f572f-3666-4c89-8b2b-aeb33c7fbbd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715005785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.3715005785 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3731031737 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 14363153696 ps |
| CPU time | 661.02 seconds |
| Started | Jul 30 08:24:12 PM PDT 24 |
| Finished | Jul 30 08:35:13 PM PDT 24 |
| Peak memory | 590652 kb |
| Host | smart-4c340ac2-eaab-4387-a203-d228cf3c4f83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731031737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.3731031737 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.546214277 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 16035744172 ps |
| CPU time | 2022.5 seconds |
| Started | Jul 30 08:24:07 PM PDT 24 |
| Finished | Jul 30 08:57:50 PM PDT 24 |
| Peak memory | 593416 kb |
| Host | smart-2e3d4d38-8486-4811-abd8-f166e8a6ff0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546214277 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.chip_same_csr_outstanding.546214277 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.580254611 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 4693781240 ps |
| CPU time | 414.65 seconds |
| Started | Jul 30 08:24:09 PM PDT 24 |
| Finished | Jul 30 08:31:04 PM PDT 24 |
| Peak memory | 603792 kb |
| Host | smart-806dc89f-d7b0-4e74-b645-281710f1c61d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580254611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.580254611 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.203878283 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 788873841 ps |
| CPU time | 40.4 seconds |
| Started | Jul 30 08:24:34 PM PDT 24 |
| Finished | Jul 30 08:25:14 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-b438e49b-da14-4e68-bb22-8e4b7f0d6bcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203878283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.203878283 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3673068866 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 305416682 ps |
| CPU time | 32.97 seconds |
| Started | Jul 30 08:24:47 PM PDT 24 |
| Finished | Jul 30 08:25:20 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-6d91df08-72e4-4d5f-9fae-74be303f3488 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673068866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .3673068866 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.3733524248 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 568371986 ps |
| CPU time | 53.88 seconds |
| Started | Jul 30 08:24:59 PM PDT 24 |
| Finished | Jul 30 08:25:53 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-8de55206-9ca8-4d87-9c84-ee049c80e990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733524248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3733524248 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.401441471 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 427338094 ps |
| CPU time | 43.83 seconds |
| Started | Jul 30 08:24:24 PM PDT 24 |
| Finished | Jul 30 08:25:08 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-62a3a846-6b7f-404e-a9d3-8507891d559a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401441471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.401441471 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3765341393 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 86770652487 ps |
| CPU time | 977.93 seconds |
| Started | Jul 30 08:24:26 PM PDT 24 |
| Finished | Jul 30 08:40:44 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-752095db-08c4-49b4-89d3-ce4d3b137d49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765341393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3765341393 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3184031636 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 44915210864 ps |
| CPU time | 713.87 seconds |
| Started | Jul 30 08:24:52 PM PDT 24 |
| Finished | Jul 30 08:36:46 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-7016219f-8c83-4039-8eb6-2a2cd941a6d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184031636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3184031636 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2734945339 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 481887423 ps |
| CPU time | 51.07 seconds |
| Started | Jul 30 08:24:36 PM PDT 24 |
| Finished | Jul 30 08:25:28 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-30ff8e2f-379a-404d-b324-68ef61771597 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734945339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.2734945339 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.1196616608 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 2103684588 ps |
| CPU time | 68.32 seconds |
| Started | Jul 30 08:24:40 PM PDT 24 |
| Finished | Jul 30 08:25:48 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-c4229f16-d2e7-425e-bab7-a2f9ee668bfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196616608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1196616608 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.1358161733 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 238608946 ps |
| CPU time | 10.93 seconds |
| Started | Jul 30 08:24:12 PM PDT 24 |
| Finished | Jul 30 08:24:23 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-3f42334d-7701-41b6-a7ad-65e9c9ace2e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358161733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1358161733 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.458211567 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 7597088071 ps |
| CPU time | 84.05 seconds |
| Started | Jul 30 08:24:16 PM PDT 24 |
| Finished | Jul 30 08:25:40 PM PDT 24 |
| Peak memory | 573908 kb |
| Host | smart-b3f74baa-ebf6-4c76-9798-ed6652c6d0c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458211567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.458211567 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.844269865 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 5548269592 ps |
| CPU time | 113.78 seconds |
| Started | Jul 30 08:24:25 PM PDT 24 |
| Finished | Jul 30 08:26:19 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-406c52f0-9d62-4fd9-be88-a5a06eb37631 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844269865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.844269865 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3588862194 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 49089055 ps |
| CPU time | 7.51 seconds |
| Started | Jul 30 08:24:21 PM PDT 24 |
| Finished | Jul 30 08:24:29 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-7d99e9ec-6939-48fe-ae56-ffc4f40a7820 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588862194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .3588862194 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.2739622230 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 3828838297 ps |
| CPU time | 137.13 seconds |
| Started | Jul 30 08:24:47 PM PDT 24 |
| Finished | Jul 30 08:27:04 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-a0494eb8-c2fd-44c5-9c7d-27de409a4ed4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739622230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2739622230 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3658439615 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 3365080348 ps |
| CPU time | 247.87 seconds |
| Started | Jul 30 08:24:58 PM PDT 24 |
| Finished | Jul 30 08:29:06 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-7faa65ba-fc81-4294-a9a5-bb3f12d5753e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658439615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3658439615 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2795964599 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 210950026 ps |
| CPU time | 81.28 seconds |
| Started | Jul 30 08:24:50 PM PDT 24 |
| Finished | Jul 30 08:26:11 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-323b2334-2c5e-4289-a50e-6ee944c9ac72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795964599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.2795964599 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2901966754 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 231152397 ps |
| CPU time | 90.05 seconds |
| Started | Jul 30 08:25:01 PM PDT 24 |
| Finished | Jul 30 08:26:31 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-e7b4a10f-6f34-412e-8bfc-9700c7f7734d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901966754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.2901966754 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3221112515 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 318320423 ps |
| CPU time | 36.66 seconds |
| Started | Jul 30 08:24:44 PM PDT 24 |
| Finished | Jul 30 08:25:21 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-50ce7b20-5c26-4754-884a-db3067de9376 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221112515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3221112515 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2236172462 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 30107703900 ps |
| CPU time | 3281.97 seconds |
| Started | Jul 30 08:25:20 PM PDT 24 |
| Finished | Jul 30 09:20:03 PM PDT 24 |
| Peak memory | 593896 kb |
| Host | smart-11e63f08-3c41-4f48-a65b-693dd00d8a68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236172462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.2236172462 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.2735063795 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 6561418368 ps |
| CPU time | 464.73 seconds |
| Started | Jul 30 08:26:28 PM PDT 24 |
| Finished | Jul 30 08:34:13 PM PDT 24 |
| Peak memory | 641736 kb |
| Host | smart-ecfab73a-de23-46d5-88bd-af1e9eb66ead |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735063795 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.2735063795 |
| Directory | /workspace/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.2553164524 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 4530406712 ps |
| CPU time | 332.75 seconds |
| Started | Jul 30 08:26:29 PM PDT 24 |
| Finished | Jul 30 08:32:02 PM PDT 24 |
| Peak memory | 598440 kb |
| Host | smart-06b49b67-1f07-4a67-8e57-554c202960b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553164524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.2553164524 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1573734826 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 7833065190 ps |
| CPU time | 324.69 seconds |
| Started | Jul 30 08:25:26 PM PDT 24 |
| Finished | Jul 30 08:30:51 PM PDT 24 |
| Peak memory | 591524 kb |
| Host | smart-6e683210-d953-4b1d-a708-acf4351b5200 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573734826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.1573734826 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3302138831 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 8536313543 ps |
| CPU time | 451.41 seconds |
| Started | Jul 30 08:25:24 PM PDT 24 |
| Finished | Jul 30 08:32:55 PM PDT 24 |
| Peak memory | 591516 kb |
| Host | smart-f821432f-688f-4f6f-9eb1-6977145d5402 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302138831 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.3302138831 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2560091458 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 16216217282 ps |
| CPU time | 1960.95 seconds |
| Started | Jul 30 08:25:21 PM PDT 24 |
| Finished | Jul 30 08:58:02 PM PDT 24 |
| Peak memory | 593352 kb |
| Host | smart-c810cbe3-ff1d-49f7-aba8-623b369d0cbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560091458 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.2560091458 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.2766028376 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 4134815976 ps |
| CPU time | 245.53 seconds |
| Started | Jul 30 08:25:32 PM PDT 24 |
| Finished | Jul 30 08:29:38 PM PDT 24 |
| Peak memory | 598696 kb |
| Host | smart-cafbd280-cb6a-457a-b960-b65e546cd7da |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766028376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.2766028376 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.1875235549 |
| Short name | T2933 |
| Test name | |
| Test status | |
| Simulation time | 617381088 ps |
| CPU time | 65.04 seconds |
| Started | Jul 30 08:26:07 PM PDT 24 |
| Finished | Jul 30 08:27:12 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-65283ff0-3634-418f-86f6-bd79d9f156c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875235549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 1875235549 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.707124857 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 153257801 ps |
| CPU time | 19.08 seconds |
| Started | Jul 30 08:26:18 PM PDT 24 |
| Finished | Jul 30 08:26:37 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-4a4f720d-0afc-428f-b41b-28e076d49589 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707124857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr. 707124857 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.182352020 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 1136920715 ps |
| CPU time | 43.2 seconds |
| Started | Jul 30 08:26:32 PM PDT 24 |
| Finished | Jul 30 08:27:15 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-bfe2e434-7d9b-4bee-97ac-63924e54ed11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182352020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.182352020 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.288010138 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 670596836 ps |
| CPU time | 26.86 seconds |
| Started | Jul 30 08:25:44 PM PDT 24 |
| Finished | Jul 30 08:26:11 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-7d8c2369-6a67-4f63-9c50-d6172031cd4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288010138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.288010138 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2275808889 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 8895033175 ps |
| CPU time | 101.23 seconds |
| Started | Jul 30 08:26:04 PM PDT 24 |
| Finished | Jul 30 08:27:45 PM PDT 24 |
| Peak memory | 573968 kb |
| Host | smart-4173e37d-850f-43d8-84cb-140433054e2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275808889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2275808889 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2774165963 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 52825007622 ps |
| CPU time | 920.17 seconds |
| Started | Jul 30 08:26:03 PM PDT 24 |
| Finished | Jul 30 08:41:24 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-244a132b-5dab-4b8a-bc11-260c3ecd076c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774165963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2774165963 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3264715562 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 250375438 ps |
| CPU time | 27.32 seconds |
| Started | Jul 30 08:25:52 PM PDT 24 |
| Finished | Jul 30 08:26:19 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-be4df1f7-4827-4844-901c-27fdc04b4537 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264715562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.3264715562 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.736562686 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 408486448 ps |
| CPU time | 30.69 seconds |
| Started | Jul 30 08:26:15 PM PDT 24 |
| Finished | Jul 30 08:26:45 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-73ba6616-07b1-43a9-873c-3c36b571dffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736562686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.736562686 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.193501096 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 47954966 ps |
| CPU time | 6.68 seconds |
| Started | Jul 30 08:25:28 PM PDT 24 |
| Finished | Jul 30 08:25:35 PM PDT 24 |
| Peak memory | 573780 kb |
| Host | smart-686a7fef-0bb9-4f48-b29c-3231ca4eefb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193501096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.193501096 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3477284158 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 6506193687 ps |
| CPU time | 68.37 seconds |
| Started | Jul 30 08:25:29 PM PDT 24 |
| Finished | Jul 30 08:26:38 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-8c7621c8-7e7e-41f9-8572-b8bd1fab160b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477284158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3477284158 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3338350387 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 5403295094 ps |
| CPU time | 99.84 seconds |
| Started | Jul 30 08:25:31 PM PDT 24 |
| Finished | Jul 30 08:27:11 PM PDT 24 |
| Peak memory | 573908 kb |
| Host | smart-7559d570-f7a4-4e6b-a28c-6170c907a990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338350387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3338350387 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2045823947 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 43178186 ps |
| CPU time | 6.44 seconds |
| Started | Jul 30 08:25:28 PM PDT 24 |
| Finished | Jul 30 08:25:34 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-e24f778d-4c0a-4912-9a42-fe117ccaa028 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045823947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays .2045823947 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.2421993970 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 3221051757 ps |
| CPU time | 286.64 seconds |
| Started | Jul 30 08:26:25 PM PDT 24 |
| Finished | Jul 30 08:31:11 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-446aed66-af47-498f-a4e9-43a8d29a8e1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421993970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2421993970 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.12985334 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 345401614 ps |
| CPU time | 26.61 seconds |
| Started | Jul 30 08:26:57 PM PDT 24 |
| Finished | Jul 30 08:27:23 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-e8bd219e-a58a-4f97-98f1-1f82d0410bd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12985334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.12985334 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.4036525245 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 119026641 ps |
| CPU time | 22.3 seconds |
| Started | Jul 30 08:26:23 PM PDT 24 |
| Finished | Jul 30 08:26:45 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-88ac2419-709f-4204-93a7-fd3904097639 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036525245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all _with_reset_error.4036525245 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3161653406 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 153090827 ps |
| CPU time | 21.17 seconds |
| Started | Jul 30 08:26:15 PM PDT 24 |
| Finished | Jul 30 08:26:36 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-00e5baa8-0160-412d-9bc3-8656b842d433 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161653406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3161653406 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.2013400639 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 6985303852 ps |
| CPU time | 552.07 seconds |
| Started | Jul 30 08:31:30 PM PDT 24 |
| Finished | Jul 30 08:40:43 PM PDT 24 |
| Peak memory | 643464 kb |
| Host | smart-2b280e54-995e-4377-a37f-0ea02451bcab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013400639 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.2013400639 |
| Directory | /workspace/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.2476956402 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 3586435811 ps |
| CPU time | 360.27 seconds |
| Started | Jul 30 08:31:29 PM PDT 24 |
| Finished | Jul 30 08:37:30 PM PDT 24 |
| Peak memory | 598536 kb |
| Host | smart-f577ba07-1c53-4bb4-84e7-09fa750c4a90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476956402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.2476956402 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.4079224822 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 16740614326 ps |
| CPU time | 1857.1 seconds |
| Started | Jul 30 08:31:02 PM PDT 24 |
| Finished | Jul 30 09:02:00 PM PDT 24 |
| Peak memory | 593056 kb |
| Host | smart-04e14c77-095f-47eb-9103-20ba9ef3c42e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079224822 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.4079224822 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.3041123946 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 3680595758 ps |
| CPU time | 177.88 seconds |
| Started | Jul 30 08:31:13 PM PDT 24 |
| Finished | Jul 30 08:34:11 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-451dbb30-c98e-4f08-82f3-b9af616da569 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041123946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .3041123946 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3150924087 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 72192752606 ps |
| CPU time | 1290.24 seconds |
| Started | Jul 30 08:31:12 PM PDT 24 |
| Finished | Jul 30 08:52:42 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-c082786b-6af2-4740-9789-febeaa558757 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150924087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.3150924087 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1850790818 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 335807688 ps |
| CPU time | 41.97 seconds |
| Started | Jul 30 08:31:20 PM PDT 24 |
| Finished | Jul 30 08:32:02 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-feff2c48-c4a1-4faa-8a79-9e4a1225f755 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850790818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.1850790818 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.3193750733 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 39465571 ps |
| CPU time | 6.7 seconds |
| Started | Jul 30 08:31:17 PM PDT 24 |
| Finished | Jul 30 08:31:23 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-9010f438-a155-4879-a817-04ff3259d5fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193750733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3193750733 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.2496803418 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 2254652860 ps |
| CPU time | 80.45 seconds |
| Started | Jul 30 08:31:09 PM PDT 24 |
| Finished | Jul 30 08:32:29 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-b0afecda-5f43-450a-94e1-b367c0f72664 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496803418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.2496803418 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.645773641 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 90609208456 ps |
| CPU time | 963.89 seconds |
| Started | Jul 30 08:31:09 PM PDT 24 |
| Finished | Jul 30 08:47:13 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-a3556912-b76d-45a6-afd9-f7993803ee9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645773641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.645773641 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3671651671 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 47353451776 ps |
| CPU time | 823.51 seconds |
| Started | Jul 30 08:31:11 PM PDT 24 |
| Finished | Jul 30 08:44:55 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-06509257-4659-48f8-b24f-4071ea58e5a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671651671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3671651671 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1350812080 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 136947564 ps |
| CPU time | 15.04 seconds |
| Started | Jul 30 08:31:08 PM PDT 24 |
| Finished | Jul 30 08:31:23 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-db8e1d60-fb46-423f-8b6f-dfa1e2cb4cda |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350812080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del ays.1350812080 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.450522444 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 91801256 ps |
| CPU time | 9.86 seconds |
| Started | Jul 30 08:31:16 PM PDT 24 |
| Finished | Jul 30 08:31:26 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-221e2859-ed42-4f16-8c56-b4be14a0bd5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450522444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.450522444 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.2865203438 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 164386866 ps |
| CPU time | 9.01 seconds |
| Started | Jul 30 08:31:08 PM PDT 24 |
| Finished | Jul 30 08:31:17 PM PDT 24 |
| Peak memory | 573884 kb |
| Host | smart-2bccd9fb-8268-43c3-a3da-df52ef791f09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865203438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2865203438 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.569174337 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 8299316156 ps |
| CPU time | 88.78 seconds |
| Started | Jul 30 08:31:08 PM PDT 24 |
| Finished | Jul 30 08:32:37 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-796c40e4-40ee-493f-b85d-1654303a2bb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569174337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.569174337 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2722550974 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 5203840488 ps |
| CPU time | 92.66 seconds |
| Started | Jul 30 08:31:09 PM PDT 24 |
| Finished | Jul 30 08:32:41 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-a1d25b3f-67c7-4b23-8549-089a760cf804 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722550974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2722550974 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.4120239713 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 41387375 ps |
| CPU time | 6.55 seconds |
| Started | Jul 30 08:31:04 PM PDT 24 |
| Finished | Jul 30 08:31:10 PM PDT 24 |
| Peak memory | 573884 kb |
| Host | smart-854450ea-9ae7-48fb-bd5c-adc1212ed9d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120239713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.4120239713 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.2162190155 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 3536640280 ps |
| CPU time | 301.25 seconds |
| Started | Jul 30 08:31:27 PM PDT 24 |
| Finished | Jul 30 08:36:29 PM PDT 24 |
| Peak memory | 576860 kb |
| Host | smart-082f0ecd-3f20-4aac-a654-e962e97d7e49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162190155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2162190155 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3557587557 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 4553996072 ps |
| CPU time | 191.26 seconds |
| Started | Jul 30 08:31:27 PM PDT 24 |
| Finished | Jul 30 08:34:39 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-c8702b33-72b9-406f-907c-a529f4f64482 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557587557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3557587557 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2861297154 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 6656680105 ps |
| CPU time | 424.06 seconds |
| Started | Jul 30 08:31:25 PM PDT 24 |
| Finished | Jul 30 08:38:30 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-c5ed2924-a1fc-49ea-a528-defc01ad15de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861297154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.2861297154 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1767062294 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 368601820 ps |
| CPU time | 20.52 seconds |
| Started | Jul 30 08:31:16 PM PDT 24 |
| Finished | Jul 30 08:31:36 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-0139334d-5034-48df-918e-f4f12f6b3c17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767062294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1767062294 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.3769213089 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 5864334742 ps |
| CPU time | 388.86 seconds |
| Started | Jul 30 08:31:53 PM PDT 24 |
| Finished | Jul 30 08:38:22 PM PDT 24 |
| Peak memory | 642824 kb |
| Host | smart-af6b477a-6756-41ec-8b57-6bd5a543a200 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769213089 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.3769213089 |
| Directory | /workspace/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.3457028815 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 3632699832 ps |
| CPU time | 437.56 seconds |
| Started | Jul 30 08:31:54 PM PDT 24 |
| Finished | Jul 30 08:39:12 PM PDT 24 |
| Peak memory | 598812 kb |
| Host | smart-bcbf8697-3dc2-4ea5-a7d5-38685435f691 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457028815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.3457028815 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.778347415 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 27823151123 ps |
| CPU time | 3149.5 seconds |
| Started | Jul 30 08:31:31 PM PDT 24 |
| Finished | Jul 30 09:24:01 PM PDT 24 |
| Peak memory | 593504 kb |
| Host | smart-7a8f236c-5280-4031-9848-b8674fb9c400 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778347415 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 11.chip_same_csr_outstanding.778347415 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.989251221 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 3461825832 ps |
| CPU time | 275.13 seconds |
| Started | Jul 30 08:31:38 PM PDT 24 |
| Finished | Jul 30 08:36:13 PM PDT 24 |
| Peak memory | 598732 kb |
| Host | smart-df1bf5a6-4a71-4dd3-a60d-4892475325bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989251221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.989251221 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.4098140421 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 1182522207 ps |
| CPU time | 91.44 seconds |
| Started | Jul 30 08:31:38 PM PDT 24 |
| Finished | Jul 30 08:33:10 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-26383ea7-b5f0-46db-b6c4-57a2269027f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098140421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .4098140421 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.4092252135 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 85723356022 ps |
| CPU time | 1545.22 seconds |
| Started | Jul 30 08:31:45 PM PDT 24 |
| Finished | Jul 30 08:57:31 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-ce2e31fe-bc9f-4cb4-8490-1de04d31ace2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092252135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.4092252135 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2460493470 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 36079986 ps |
| CPU time | 7.9 seconds |
| Started | Jul 30 08:31:47 PM PDT 24 |
| Finished | Jul 30 08:31:55 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-24061076-45fe-4a75-a7d9-d074792fbd86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460493470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.2460493470 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.3213742018 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 761234118 ps |
| CPU time | 31.59 seconds |
| Started | Jul 30 08:31:45 PM PDT 24 |
| Finished | Jul 30 08:32:16 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-031a974f-d8c1-44a4-bc19-403c3af2bc78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213742018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3213742018 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.1293268101 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 39950187 ps |
| CPU time | 6.54 seconds |
| Started | Jul 30 08:31:39 PM PDT 24 |
| Finished | Jul 30 08:31:46 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-fc51004d-9df3-44b1-b632-d6cb65d22842 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293268101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.1293268101 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.4170385330 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 19739889718 ps |
| CPU time | 207.69 seconds |
| Started | Jul 30 08:31:40 PM PDT 24 |
| Finished | Jul 30 08:35:08 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-9e0c1d0e-a097-4577-8dbd-6e98c1ad1bf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170385330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.4170385330 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2856915340 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 50331950409 ps |
| CPU time | 927.93 seconds |
| Started | Jul 30 08:31:39 PM PDT 24 |
| Finished | Jul 30 08:47:07 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-b15ffe2c-a871-4976-996d-ba9471dba320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856915340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2856915340 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1786147301 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 91496412 ps |
| CPU time | 11.53 seconds |
| Started | Jul 30 08:31:40 PM PDT 24 |
| Finished | Jul 30 08:31:52 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-6518214e-c419-4fef-9771-7af730ce5345 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786147301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.1786147301 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.2165207986 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 299101912 ps |
| CPU time | 23.92 seconds |
| Started | Jul 30 08:31:44 PM PDT 24 |
| Finished | Jul 30 08:32:08 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-969f5df4-e69d-4ed0-8830-4fcd15d7c043 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165207986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2165207986 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.691816064 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 44469346 ps |
| CPU time | 6.48 seconds |
| Started | Jul 30 08:31:32 PM PDT 24 |
| Finished | Jul 30 08:31:39 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-6b7e51f7-3b1c-428b-ae7f-3fc1a76d199e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691816064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.691816064 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2348925267 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 6755112170 ps |
| CPU time | 71.8 seconds |
| Started | Jul 30 08:31:34 PM PDT 24 |
| Finished | Jul 30 08:32:46 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-e7cc2fa3-0040-45dd-89ed-2f9744c46ec2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348925267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2348925267 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3008098293 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 4952844463 ps |
| CPU time | 87.19 seconds |
| Started | Jul 30 08:31:39 PM PDT 24 |
| Finished | Jul 30 08:33:06 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-951a0dce-f842-402e-9796-0f9cceb14f9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008098293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3008098293 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3073931146 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 47834979 ps |
| CPU time | 6.7 seconds |
| Started | Jul 30 08:32:05 PM PDT 24 |
| Finished | Jul 30 08:32:12 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-ee3f3657-1073-41fd-8b74-7c1adba0e3fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073931146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.3073931146 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.2109767623 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 2287131157 ps |
| CPU time | 198.49 seconds |
| Started | Jul 30 08:31:47 PM PDT 24 |
| Finished | Jul 30 08:35:05 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-93727a45-c100-46b7-9185-f9a177641b4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109767623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2109767623 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.908455807 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 206473227 ps |
| CPU time | 17.24 seconds |
| Started | Jul 30 08:31:50 PM PDT 24 |
| Finished | Jul 30 08:32:07 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-f57d7127-6f92-41e7-9727-87569e539a7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908455807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.908455807 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.226205195 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 482490438 ps |
| CPU time | 159.12 seconds |
| Started | Jul 30 08:31:50 PM PDT 24 |
| Finished | Jul 30 08:34:29 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-18c88098-af1b-459f-a9a5-0e57b5064173 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226205195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_ with_rand_reset.226205195 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2162956069 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 14646967693 ps |
| CPU time | 648.89 seconds |
| Started | Jul 30 08:31:50 PM PDT 24 |
| Finished | Jul 30 08:42:39 PM PDT 24 |
| Peak memory | 576872 kb |
| Host | smart-3763e110-7fd0-4fe6-a697-853cf69b2037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162956069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.2162956069 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3212246534 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 763617954 ps |
| CPU time | 39.3 seconds |
| Started | Jul 30 08:31:46 PM PDT 24 |
| Finished | Jul 30 08:32:26 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-ef0c9666-fcd3-42d2-a7f1-0ac0a0461e7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212246534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3212246534 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3686038220 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 6748011110 ps |
| CPU time | 479.35 seconds |
| Started | Jul 30 08:32:17 PM PDT 24 |
| Finished | Jul 30 08:40:16 PM PDT 24 |
| Peak memory | 640808 kb |
| Host | smart-17a93ca1-41b7-4664-b47d-8026dcff7901 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686038220 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.3686038220 |
| Directory | /workspace/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.567818331 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 3602315292 ps |
| CPU time | 330.89 seconds |
| Started | Jul 30 08:32:22 PM PDT 24 |
| Finished | Jul 30 08:37:53 PM PDT 24 |
| Peak memory | 598516 kb |
| Host | smart-2e02a2a6-cd3c-474f-8435-a263c45074ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567818331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.567818331 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.1115959978 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 3581550992 ps |
| CPU time | 184.92 seconds |
| Started | Jul 30 08:31:57 PM PDT 24 |
| Finished | Jul 30 08:35:02 PM PDT 24 |
| Peak memory | 598700 kb |
| Host | smart-cf158642-bb68-424e-8fd9-9d50330bb0f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115959978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.1115959978 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.732726515 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 710492801 ps |
| CPU time | 54.99 seconds |
| Started | Jul 30 08:32:04 PM PDT 24 |
| Finished | Jul 30 08:32:59 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-4a352a9d-63d9-4293-a079-56ec0db98eb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732726515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device. 732726515 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.747697621 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 45934139220 ps |
| CPU time | 768.93 seconds |
| Started | Jul 30 08:32:18 PM PDT 24 |
| Finished | Jul 30 08:45:07 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-248ef9e1-2d86-46a2-8f47-c2437cdfe9d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747697621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_d evice_slow_rsp.747697621 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.186666100 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 1034170027 ps |
| CPU time | 39.6 seconds |
| Started | Jul 30 08:32:20 PM PDT 24 |
| Finished | Jul 30 08:33:00 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-fa97b7ac-4886-4b59-9bf5-93295b9a5005 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186666100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr .186666100 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.1423604309 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 1406852706 ps |
| CPU time | 59.39 seconds |
| Started | Jul 30 08:32:06 PM PDT 24 |
| Finished | Jul 30 08:33:05 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-6effd1af-bc1a-43fa-b1fa-cf90fa5aa24f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423604309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1423604309 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.237788850 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 1983404704 ps |
| CPU time | 75.3 seconds |
| Started | Jul 30 08:32:07 PM PDT 24 |
| Finished | Jul 30 08:33:22 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-0ed92886-532c-450e-aa2e-f6259b16e77b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237788850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.237788850 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.412758903 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 19512210008 ps |
| CPU time | 201.97 seconds |
| Started | Jul 30 08:32:19 PM PDT 24 |
| Finished | Jul 30 08:35:41 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-5c23e283-bd00-46eb-9606-308ead14c9df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412758903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.412758903 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.311473908 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 60475128398 ps |
| CPU time | 938.51 seconds |
| Started | Jul 30 08:32:06 PM PDT 24 |
| Finished | Jul 30 08:47:44 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-60997c4e-5938-4ff9-bc44-5cdb0a9c2002 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311473908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.311473908 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2401937597 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 401243365 ps |
| CPU time | 33.78 seconds |
| Started | Jul 30 08:32:19 PM PDT 24 |
| Finished | Jul 30 08:32:53 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-3fa66148-c353-46c2-b63f-e8fc8b587a2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401937597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.2401937597 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.557266756 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 209255522 ps |
| CPU time | 16.45 seconds |
| Started | Jul 30 08:32:18 PM PDT 24 |
| Finished | Jul 30 08:32:35 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-0fd2a093-e50d-4ac3-a6e4-291a2d7132b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557266756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.557266756 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.3156432978 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 48858667 ps |
| CPU time | 7.18 seconds |
| Started | Jul 30 08:31:58 PM PDT 24 |
| Finished | Jul 30 08:32:05 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-9c910fb7-9b75-4454-b5ae-2b9f1db6b389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156432978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3156432978 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3941789048 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 9005953286 ps |
| CPU time | 97.94 seconds |
| Started | Jul 30 08:32:02 PM PDT 24 |
| Finished | Jul 30 08:33:40 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-f031e665-51a9-4653-bcdc-1698f09051d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941789048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3941789048 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3385735402 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 7034913528 ps |
| CPU time | 117.9 seconds |
| Started | Jul 30 08:32:01 PM PDT 24 |
| Finished | Jul 30 08:33:59 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-48333b66-ac7e-4760-9711-eb50be6241d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385735402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3385735402 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2596205978 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 35521119 ps |
| CPU time | 6.01 seconds |
| Started | Jul 30 08:31:58 PM PDT 24 |
| Finished | Jul 30 08:32:04 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-e3af8dbe-ab44-4a42-8713-8b671f6a0397 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596205978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.2596205978 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.2711243655 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1794294537 ps |
| CPU time | 160.99 seconds |
| Started | Jul 30 08:32:10 PM PDT 24 |
| Finished | Jul 30 08:34:51 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-41f025c8-52ac-4283-8b51-49c8e7846acf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711243655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2711243655 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.204420089 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 10712237130 ps |
| CPU time | 393.79 seconds |
| Started | Jul 30 08:32:12 PM PDT 24 |
| Finished | Jul 30 08:38:46 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-cf60e81b-7f54-4d2b-b0f8-e3ecee58bfb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204420089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.204420089 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3637868892 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 31167057 ps |
| CPU time | 14.58 seconds |
| Started | Jul 30 08:32:16 PM PDT 24 |
| Finished | Jul 30 08:32:31 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-4c79966f-261f-4660-85bc-6b64bc209814 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637868892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.3637868892 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2402720214 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 99862126 ps |
| CPU time | 16.16 seconds |
| Started | Jul 30 08:32:10 PM PDT 24 |
| Finished | Jul 30 08:32:26 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-68705a66-bec0-4917-986e-dd2a7f369404 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402720214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2402720214 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.3073064105 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 5239114557 ps |
| CPU time | 624.6 seconds |
| Started | Jul 30 08:32:33 PM PDT 24 |
| Finished | Jul 30 08:42:58 PM PDT 24 |
| Peak memory | 599216 kb |
| Host | smart-060b7f4f-9cb7-4f45-88c1-47e5f999b560 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073064105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.3073064105 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.4009617904 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1965240328 ps |
| CPU time | 72.05 seconds |
| Started | Jul 30 08:32:30 PM PDT 24 |
| Finished | Jul 30 08:33:42 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-95dc5044-f8fe-4864-a9f7-36a65d0d6f5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009617904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .4009617904 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.415942235 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 35119910874 ps |
| CPU time | 551.98 seconds |
| Started | Jul 30 08:32:30 PM PDT 24 |
| Finished | Jul 30 08:41:42 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-1f987f37-cf99-4e5d-8ba3-8d5850ae9dbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415942235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_d evice_slow_rsp.415942235 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3424963869 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 159617395 ps |
| CPU time | 20.63 seconds |
| Started | Jul 30 08:32:23 PM PDT 24 |
| Finished | Jul 30 08:32:44 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-6fda422c-9850-4674-a670-24f6f6e1da50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424963869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.3424963869 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.646093702 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 440299370 ps |
| CPU time | 45.24 seconds |
| Started | Jul 30 08:32:24 PM PDT 24 |
| Finished | Jul 30 08:33:09 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-c46b8736-a6bb-4714-907e-62d84a6db2b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646093702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.646093702 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.1948804453 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 541334295 ps |
| CPU time | 50.97 seconds |
| Started | Jul 30 08:32:22 PM PDT 24 |
| Finished | Jul 30 08:33:13 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-9294f1f4-3b94-4e27-9be3-d6c0a6b3efe4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948804453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.1948804453 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.609502344 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 11334099481 ps |
| CPU time | 120.36 seconds |
| Started | Jul 30 08:32:22 PM PDT 24 |
| Finished | Jul 30 08:34:23 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-610ebc77-fcd5-4a83-a35f-6fef399549c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609502344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.609502344 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3707520527 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 56259906081 ps |
| CPU time | 998.64 seconds |
| Started | Jul 30 08:32:27 PM PDT 24 |
| Finished | Jul 30 08:49:06 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-95fd9f13-845c-4dc8-9ed7-e31fd633ac50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707520527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3707520527 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.960054397 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 233193080 ps |
| CPU time | 22.77 seconds |
| Started | Jul 30 08:32:22 PM PDT 24 |
| Finished | Jul 30 08:32:45 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-810e2d6d-49d4-48d1-8f38-27de95894b56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960054397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_dela ys.960054397 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.2910296915 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 244874821 ps |
| CPU time | 22.37 seconds |
| Started | Jul 30 08:32:25 PM PDT 24 |
| Finished | Jul 30 08:32:47 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-da8b080b-d1d5-4b7e-aef8-4af942119b58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910296915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2910296915 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.4285178512 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 247723977 ps |
| CPU time | 10.63 seconds |
| Started | Jul 30 08:32:17 PM PDT 24 |
| Finished | Jul 30 08:32:28 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-8fece27f-4231-4201-9898-dff9bc1e1add |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285178512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.4285178512 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3299435233 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 9065128612 ps |
| CPU time | 100.51 seconds |
| Started | Jul 30 08:32:25 PM PDT 24 |
| Finished | Jul 30 08:34:05 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-f2e86c0b-d83e-4005-bb17-4ab1c5d6d5b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299435233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3299435233 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.180912437 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 4212890530 ps |
| CPU time | 71.24 seconds |
| Started | Jul 30 08:32:22 PM PDT 24 |
| Finished | Jul 30 08:33:34 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-2de814d8-3dee-451d-939a-33a71bf6cb4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180912437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.180912437 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3309863866 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 35502957 ps |
| CPU time | 5.9 seconds |
| Started | Jul 30 08:32:20 PM PDT 24 |
| Finished | Jul 30 08:32:26 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-42f6ef7d-0175-4982-9640-76a8284a54f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309863866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.3309863866 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.1179797117 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 7358720313 ps |
| CPU time | 342.2 seconds |
| Started | Jul 30 08:32:29 PM PDT 24 |
| Finished | Jul 30 08:38:11 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-8b117ca1-482d-4119-bfec-acbc53c91166 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179797117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1179797117 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2345070669 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 1500943305 ps |
| CPU time | 44.53 seconds |
| Started | Jul 30 08:32:37 PM PDT 24 |
| Finished | Jul 30 08:33:21 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-7cf18687-7744-4da1-888a-3ba5dfdde0d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345070669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2345070669 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2108789014 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 8136647814 ps |
| CPU time | 417.74 seconds |
| Started | Jul 30 08:32:29 PM PDT 24 |
| Finished | Jul 30 08:39:26 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-b13bc6ab-f2c7-44af-962a-c4ba096775b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108789014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.2108789014 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.3058088630 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 706912943 ps |
| CPU time | 39 seconds |
| Started | Jul 30 08:32:25 PM PDT 24 |
| Finished | Jul 30 08:33:04 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-1b9ef325-e93e-4192-bcb0-20f1b7cea865 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058088630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3058088630 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.815517202 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 5311087532 ps |
| CPU time | 399.52 seconds |
| Started | Jul 30 08:32:54 PM PDT 24 |
| Finished | Jul 30 08:39:34 PM PDT 24 |
| Peak memory | 640668 kb |
| Host | smart-cf63b9ed-841b-44b5-8344-1259c5ca0f12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815517202 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.815517202 |
| Directory | /workspace/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.2086769271 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 6162685867 ps |
| CPU time | 681.02 seconds |
| Started | Jul 30 08:32:54 PM PDT 24 |
| Finished | Jul 30 08:44:15 PM PDT 24 |
| Peak memory | 598444 kb |
| Host | smart-628cf29a-75b3-44eb-ac24-9d7f931ef893 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086769271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.2086769271 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3200054994 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 16332866422 ps |
| CPU time | 1981.21 seconds |
| Started | Jul 30 08:32:31 PM PDT 24 |
| Finished | Jul 30 09:05:33 PM PDT 24 |
| Peak memory | 593352 kb |
| Host | smart-96e7cc1b-2355-4326-ac3f-68d7c8c33a1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200054994 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.3200054994 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.3795636031 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 2275305122 ps |
| CPU time | 109.33 seconds |
| Started | Jul 30 08:32:37 PM PDT 24 |
| Finished | Jul 30 08:34:26 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-3dbe45b2-a159-48d4-a9d9-dd154df30c1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795636031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .3795636031 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.853844592 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 83861544710 ps |
| CPU time | 1536.61 seconds |
| Started | Jul 30 08:32:40 PM PDT 24 |
| Finished | Jul 30 08:58:17 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-510f5f03-14d0-4514-8422-e30b5959e939 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853844592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_d evice_slow_rsp.853844592 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.368445345 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 711847557 ps |
| CPU time | 31.72 seconds |
| Started | Jul 30 08:32:48 PM PDT 24 |
| Finished | Jul 30 08:33:20 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-0f8ac433-bf97-481b-87d0-377f74860d66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368445345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr .368445345 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.3292863410 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 1663865470 ps |
| CPU time | 60.69 seconds |
| Started | Jul 30 08:32:44 PM PDT 24 |
| Finished | Jul 30 08:33:45 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-747a7b57-ec61-4d3f-85e5-9180ed6d9c7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292863410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3292863410 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.665383265 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1985366325 ps |
| CPU time | 64.69 seconds |
| Started | Jul 30 08:32:46 PM PDT 24 |
| Finished | Jul 30 08:33:51 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-89c3589c-de67-42d5-977d-bf4fbc34326e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665383265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.665383265 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.700571003 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 59912929973 ps |
| CPU time | 536.99 seconds |
| Started | Jul 30 08:32:47 PM PDT 24 |
| Finished | Jul 30 08:41:44 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-03e25ef9-d87d-40c2-bc89-38f93e667a2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700571003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.700571003 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.3086926913 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 9341592274 ps |
| CPU time | 157.92 seconds |
| Started | Jul 30 08:32:34 PM PDT 24 |
| Finished | Jul 30 08:35:12 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-346bf98a-6c7b-40cd-b103-31de918dea03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086926913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3086926913 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.1619743656 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 94296411 ps |
| CPU time | 12.3 seconds |
| Started | Jul 30 08:32:37 PM PDT 24 |
| Finished | Jul 30 08:32:49 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-7d86a75e-d617-48a3-859f-f06cd27c0e92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619743656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del ays.1619743656 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.1749037431 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 2371994567 ps |
| CPU time | 79.21 seconds |
| Started | Jul 30 08:32:40 PM PDT 24 |
| Finished | Jul 30 08:33:59 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-fb870f02-97f6-457b-8513-4d5384d45b11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749037431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1749037431 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.1767838063 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 175534577 ps |
| CPU time | 8.69 seconds |
| Started | Jul 30 08:32:34 PM PDT 24 |
| Finished | Jul 30 08:32:43 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-42d0bf8a-c4e4-4dcb-87c2-54cd9884f8fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767838063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1767838063 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3115071594 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 8107788927 ps |
| CPU time | 80.32 seconds |
| Started | Jul 30 08:32:47 PM PDT 24 |
| Finished | Jul 30 08:34:07 PM PDT 24 |
| Peak memory | 573908 kb |
| Host | smart-4f50657a-5da8-492f-a49d-cfadb27c7560 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115071594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3115071594 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1538088436 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 5370988447 ps |
| CPU time | 87.29 seconds |
| Started | Jul 30 08:32:47 PM PDT 24 |
| Finished | Jul 30 08:34:14 PM PDT 24 |
| Peak memory | 573884 kb |
| Host | smart-2161e917-1e78-4db1-8191-70cbf56b53ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538088436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1538088436 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.1680471501 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 50382792 ps |
| CPU time | 6.65 seconds |
| Started | Jul 30 08:32:46 PM PDT 24 |
| Finished | Jul 30 08:32:53 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-3e62a82f-098b-445a-9d3f-abbf91c29815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680471501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.1680471501 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.3238753020 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 1916566945 ps |
| CPU time | 168.33 seconds |
| Started | Jul 30 08:32:46 PM PDT 24 |
| Finished | Jul 30 08:35:34 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-bf06e7fa-a23c-4d53-beed-1c3527dc3d43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238753020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3238753020 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.439428618 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 3617682741 ps |
| CPU time | 138.76 seconds |
| Started | Jul 30 08:32:51 PM PDT 24 |
| Finished | Jul 30 08:35:09 PM PDT 24 |
| Peak memory | 576160 kb |
| Host | smart-1c046fe8-0513-47a4-ac70-e8840e879c4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439428618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.439428618 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2868366976 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 11917040401 ps |
| CPU time | 775.16 seconds |
| Started | Jul 30 08:32:47 PM PDT 24 |
| Finished | Jul 30 08:45:42 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-da8e927c-4b8a-4562-bfc0-621039b22721 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868366976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.2868366976 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.935941500 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 2275935276 ps |
| CPU time | 359.24 seconds |
| Started | Jul 30 08:32:50 PM PDT 24 |
| Finished | Jul 30 08:38:49 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-6dd41d33-94a5-4b5f-95d1-0f56f59ffb64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935941500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_reset_error.935941500 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.4288885435 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 711362162 ps |
| CPU time | 34.26 seconds |
| Started | Jul 30 08:32:46 PM PDT 24 |
| Finished | Jul 30 08:33:21 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-5abcaa98-21f9-48e8-9838-acb0febadcf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288885435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.4288885435 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.3897046157 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 7281442820 ps |
| CPU time | 513.47 seconds |
| Started | Jul 30 08:33:09 PM PDT 24 |
| Finished | Jul 30 08:41:43 PM PDT 24 |
| Peak memory | 638708 kb |
| Host | smart-367e6c52-1a3a-41f9-b822-fc90f007a1d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897046157 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.3897046157 |
| Directory | /workspace/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.3639384840 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 5514834754 ps |
| CPU time | 552.72 seconds |
| Started | Jul 30 08:33:11 PM PDT 24 |
| Finished | Jul 30 08:42:23 PM PDT 24 |
| Peak memory | 598848 kb |
| Host | smart-c3fadb8f-512c-4ed4-bb4d-d9b7e85c03da |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639384840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.3639384840 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.864054533 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 16725302631 ps |
| CPU time | 2088.9 seconds |
| Started | Jul 30 08:32:56 PM PDT 24 |
| Finished | Jul 30 09:07:46 PM PDT 24 |
| Peak memory | 592992 kb |
| Host | smart-3e6fc88e-4988-46ff-817c-08014eaeb453 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864054533 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 15.chip_same_csr_outstanding.864054533 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.3882884113 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 3883836725 ps |
| CPU time | 222.97 seconds |
| Started | Jul 30 08:32:54 PM PDT 24 |
| Finished | Jul 30 08:36:37 PM PDT 24 |
| Peak memory | 603696 kb |
| Host | smart-0bc60fc1-aa3f-4b68-8992-a9dad024eea5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882884113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.3882884113 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.4166397233 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 1558263556 ps |
| CPU time | 75.87 seconds |
| Started | Jul 30 08:33:02 PM PDT 24 |
| Finished | Jul 30 08:34:17 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-6bd2c210-f044-4c14-b79c-b7c21c24400a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166397233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .4166397233 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3368533991 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 116688758997 ps |
| CPU time | 2042.08 seconds |
| Started | Jul 30 08:33:03 PM PDT 24 |
| Finished | Jul 30 09:07:05 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-d5a2cba1-3f67-4c6f-a580-20a99cd64a8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368533991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.3368533991 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2315327407 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 275209065 ps |
| CPU time | 34.77 seconds |
| Started | Jul 30 08:33:06 PM PDT 24 |
| Finished | Jul 30 08:33:41 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-716364ce-4b24-4e5a-bd78-073a76bd3d76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315327407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.2315327407 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.1037054072 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 314301675 ps |
| CPU time | 29.61 seconds |
| Started | Jul 30 08:33:07 PM PDT 24 |
| Finished | Jul 30 08:33:36 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-211bba84-6d2e-4f99-91fa-98f135c8a87d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037054072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1037054072 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.1904619947 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 1776004316 ps |
| CPU time | 76.81 seconds |
| Started | Jul 30 08:33:02 PM PDT 24 |
| Finished | Jul 30 08:34:18 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-fac13db1-5aa6-4dab-ab51-bda845be388a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904619947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.1904619947 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.4171858851 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 50905404219 ps |
| CPU time | 541.17 seconds |
| Started | Jul 30 08:33:02 PM PDT 24 |
| Finished | Jul 30 08:42:03 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-be0ceb08-989a-4c35-be45-b0e551f652ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171858851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.4171858851 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.1816518694 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 26250356295 ps |
| CPU time | 475.04 seconds |
| Started | Jul 30 08:33:04 PM PDT 24 |
| Finished | Jul 30 08:40:59 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-01af00b1-acc3-4f97-bf7b-9e9b9f6a7a91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816518694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1816518694 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.1477728130 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 314611969 ps |
| CPU time | 35.69 seconds |
| Started | Jul 30 08:33:01 PM PDT 24 |
| Finished | Jul 30 08:33:37 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-d8d712c0-1582-42f9-aa4f-e14736ddd024 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477728130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.1477728130 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.1769368413 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 1602004874 ps |
| CPU time | 55.3 seconds |
| Started | Jul 30 08:33:01 PM PDT 24 |
| Finished | Jul 30 08:33:57 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-766cd43d-170b-4878-a53b-74983e7880b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769368413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1769368413 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.3293005946 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 213106631 ps |
| CPU time | 10.52 seconds |
| Started | Jul 30 08:32:57 PM PDT 24 |
| Finished | Jul 30 08:33:08 PM PDT 24 |
| Peak memory | 573884 kb |
| Host | smart-3675016f-9f42-4309-b2e0-54e69fe5dcca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293005946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3293005946 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.3057455410 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 8035753129 ps |
| CPU time | 91.96 seconds |
| Started | Jul 30 08:33:01 PM PDT 24 |
| Finished | Jul 30 08:34:33 PM PDT 24 |
| Peak memory | 573908 kb |
| Host | smart-297ff67c-573f-40b8-96a6-56b87fd2e171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057455410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3057455410 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3655310522 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 3997574452 ps |
| CPU time | 71.11 seconds |
| Started | Jul 30 08:32:58 PM PDT 24 |
| Finished | Jul 30 08:34:09 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-03ab513d-4947-4361-815d-fa187f8d2436 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655310522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3655310522 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.1623590500 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 43490776 ps |
| CPU time | 6.43 seconds |
| Started | Jul 30 08:32:59 PM PDT 24 |
| Finished | Jul 30 08:33:05 PM PDT 24 |
| Peak memory | 573876 kb |
| Host | smart-e2b10774-6aab-4e19-b834-0ba56ff89418 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623590500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.1623590500 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.2443167488 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 6138512658 ps |
| CPU time | 273.84 seconds |
| Started | Jul 30 08:33:06 PM PDT 24 |
| Finished | Jul 30 08:37:40 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-1dc270c8-a678-456e-a80e-de08c911612c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443167488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2443167488 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.752394202 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 363274545 ps |
| CPU time | 24.84 seconds |
| Started | Jul 30 08:33:04 PM PDT 24 |
| Finished | Jul 30 08:33:29 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-44177d4d-11d5-4daa-9543-f8d80f5b2e25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752394202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.752394202 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1842298938 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 87012939 ps |
| CPU time | 49.3 seconds |
| Started | Jul 30 08:33:05 PM PDT 24 |
| Finished | Jul 30 08:33:54 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-61fa6604-65b4-4588-b4b8-5abe03001e0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842298938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.1842298938 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1250284321 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 2058563198 ps |
| CPU time | 137.18 seconds |
| Started | Jul 30 08:33:06 PM PDT 24 |
| Finished | Jul 30 08:35:23 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-de29cda4-9fee-48f3-8c81-e9f47e324997 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250284321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.1250284321 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.2818355738 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 693269787 ps |
| CPU time | 30.28 seconds |
| Started | Jul 30 08:33:04 PM PDT 24 |
| Finished | Jul 30 08:33:35 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-49436cd3-b9fc-4459-9ea3-85031adc5a9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818355738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2818355738 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.151886003 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 10419304295 ps |
| CPU time | 738.16 seconds |
| Started | Jul 30 08:33:37 PM PDT 24 |
| Finished | Jul 30 08:45:55 PM PDT 24 |
| Peak memory | 653076 kb |
| Host | smart-2a7d5a59-9308-4191-af55-65292b617a2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151886003 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.151886003 |
| Directory | /workspace/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.3280519063 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 5974695365 ps |
| CPU time | 643.14 seconds |
| Started | Jul 30 08:33:34 PM PDT 24 |
| Finished | Jul 30 08:44:17 PM PDT 24 |
| Peak memory | 597964 kb |
| Host | smart-21642463-0976-4ce1-8738-cbccea7a3ec2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280519063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.3280519063 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.3047563066 |
| Short name | T2921 |
| Test name | |
| Test status | |
| Simulation time | 16982091721 ps |
| CPU time | 2488.52 seconds |
| Started | Jul 30 08:33:11 PM PDT 24 |
| Finished | Jul 30 09:14:39 PM PDT 24 |
| Peak memory | 593280 kb |
| Host | smart-745257b5-f79b-4c0b-984c-d73acc3129a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047563066 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.3047563066 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.2069524649 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 3317895037 ps |
| CPU time | 175.97 seconds |
| Started | Jul 30 08:33:10 PM PDT 24 |
| Finished | Jul 30 08:36:06 PM PDT 24 |
| Peak memory | 603796 kb |
| Host | smart-460d75ae-5cc2-40d5-bd75-de7f6873bf75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069524649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.2069524649 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.3964948325 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 603827621 ps |
| CPU time | 49.64 seconds |
| Started | Jul 30 08:33:30 PM PDT 24 |
| Finished | Jul 30 08:34:20 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-bb85a381-e7a7-406d-abff-970a90a9702e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964948325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .3964948325 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.3324721284 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 111772492353 ps |
| CPU time | 1808.89 seconds |
| Started | Jul 30 08:33:20 PM PDT 24 |
| Finished | Jul 30 09:03:29 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-dc444323-f41b-495d-b5ff-923dec592481 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324721284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.3324721284 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1238371853 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 645902576 ps |
| CPU time | 31.77 seconds |
| Started | Jul 30 08:33:27 PM PDT 24 |
| Finished | Jul 30 08:33:59 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-68d188be-cc65-4cc4-97e1-39717b84b3e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238371853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.1238371853 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.1655031402 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 297216670 ps |
| CPU time | 27.68 seconds |
| Started | Jul 30 08:33:26 PM PDT 24 |
| Finished | Jul 30 08:33:54 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-1843e7ce-0489-47be-8ae2-d79b93e13c8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655031402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1655031402 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.2893124822 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 235995075 ps |
| CPU time | 25.46 seconds |
| Started | Jul 30 08:33:15 PM PDT 24 |
| Finished | Jul 30 08:33:41 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-ed30b560-5848-4852-b5b6-7fa139357871 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893124822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.2893124822 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.3829463293 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 56184151916 ps |
| CPU time | 609.46 seconds |
| Started | Jul 30 08:33:25 PM PDT 24 |
| Finished | Jul 30 08:43:34 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-7512752c-79ee-4fbd-a810-4eb95935c3bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829463293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3829463293 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.2992661909 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 56644874944 ps |
| CPU time | 1044.98 seconds |
| Started | Jul 30 08:33:21 PM PDT 24 |
| Finished | Jul 30 08:50:46 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-e7906012-fb98-4f0f-b08d-414f6b4ca3b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992661909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2992661909 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.343004405 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 225902582 ps |
| CPU time | 22.73 seconds |
| Started | Jul 30 08:33:21 PM PDT 24 |
| Finished | Jul 30 08:33:44 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-5b772c7d-f244-46ad-bb4b-5b01d7fdc097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343004405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_dela ys.343004405 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.2000645836 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 1684240328 ps |
| CPU time | 53.78 seconds |
| Started | Jul 30 08:33:32 PM PDT 24 |
| Finished | Jul 30 08:34:26 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-38268799-d634-4b3e-b131-70585ee2c662 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000645836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2000645836 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.846724 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 220139442 ps |
| CPU time | 10.16 seconds |
| Started | Jul 30 08:33:13 PM PDT 24 |
| Finished | Jul 30 08:33:23 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-7617f027-2dff-491a-8cb0-b7f4422c7e10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.846724 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.990119469 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 6316056355 ps |
| CPU time | 70.51 seconds |
| Started | Jul 30 08:33:13 PM PDT 24 |
| Finished | Jul 30 08:34:23 PM PDT 24 |
| Peak memory | 573968 kb |
| Host | smart-7e825aff-9cc0-4dd1-97d7-0098fe8356b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990119469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.990119469 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1244609081 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 6155002325 ps |
| CPU time | 107.46 seconds |
| Started | Jul 30 08:33:17 PM PDT 24 |
| Finished | Jul 30 08:35:05 PM PDT 24 |
| Peak memory | 573780 kb |
| Host | smart-3f2e85b0-f85a-4d88-9805-e98bc30984aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244609081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1244609081 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.723678987 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 54970063 ps |
| CPU time | 7.24 seconds |
| Started | Jul 30 08:33:13 PM PDT 24 |
| Finished | Jul 30 08:33:20 PM PDT 24 |
| Peak memory | 573876 kb |
| Host | smart-411051ac-192e-4350-997d-21f846b9f400 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723678987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays .723678987 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.2398299562 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 4871508511 ps |
| CPU time | 184.92 seconds |
| Started | Jul 30 08:33:29 PM PDT 24 |
| Finished | Jul 30 08:36:34 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-adc60b50-7bad-4094-ba66-0a252ca05fe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398299562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2398299562 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.253278249 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 3352534538 ps |
| CPU time | 252.01 seconds |
| Started | Jul 30 08:33:34 PM PDT 24 |
| Finished | Jul 30 08:37:46 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-8cc54295-3add-461a-9499-59df0183a4c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253278249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_reset_error.253278249 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.3416832980 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 284606071 ps |
| CPU time | 16.91 seconds |
| Started | Jul 30 08:33:32 PM PDT 24 |
| Finished | Jul 30 08:33:49 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-858deba4-21d4-4faf-9601-9b76fb40c538 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416832980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3416832980 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.580302525 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 11932358637 ps |
| CPU time | 1068.41 seconds |
| Started | Jul 30 08:33:48 PM PDT 24 |
| Finished | Jul 30 08:51:37 PM PDT 24 |
| Peak memory | 647872 kb |
| Host | smart-b9138650-72a1-4f03-86eb-fe486b11a50d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580302525 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.580302525 |
| Directory | /workspace/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.1225255237 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 5919344760 ps |
| CPU time | 616.38 seconds |
| Started | Jul 30 08:33:52 PM PDT 24 |
| Finished | Jul 30 08:44:09 PM PDT 24 |
| Peak memory | 598084 kb |
| Host | smart-b98c574e-af1e-4f99-b501-9d6deaf8c3ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225255237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.1225255237 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.1907466383 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 28993694426 ps |
| CPU time | 3272.56 seconds |
| Started | Jul 30 08:33:36 PM PDT 24 |
| Finished | Jul 30 09:28:08 PM PDT 24 |
| Peak memory | 592984 kb |
| Host | smart-369a2965-31c5-4a3e-a850-084bc70207dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907466383 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.1907466383 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.3343984151 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 228220163 ps |
| CPU time | 22.41 seconds |
| Started | Jul 30 08:33:43 PM PDT 24 |
| Finished | Jul 30 08:34:06 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-a98a7d50-b91d-4b91-8c32-29f544f60758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343984151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .3343984151 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.2433088154 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 134000012630 ps |
| CPU time | 2538.04 seconds |
| Started | Jul 30 08:33:43 PM PDT 24 |
| Finished | Jul 30 09:16:02 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-6a6ff2c4-a2bb-4e1b-83ab-a79bce3b887c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433088154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.2433088154 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3801817580 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 285521394 ps |
| CPU time | 31.05 seconds |
| Started | Jul 30 08:33:46 PM PDT 24 |
| Finished | Jul 30 08:34:17 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-c1bdeadd-6230-4563-bda1-7de40eb842e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801817580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.3801817580 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.1534907341 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 390322459 ps |
| CPU time | 35.02 seconds |
| Started | Jul 30 08:33:50 PM PDT 24 |
| Finished | Jul 30 08:34:25 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-ad16fcba-d7da-4c11-bac5-8205b9828d95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534907341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1534907341 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.1689199502 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 423625029 ps |
| CPU time | 39.88 seconds |
| Started | Jul 30 08:33:43 PM PDT 24 |
| Finished | Jul 30 08:34:23 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-3aeff918-24f3-459a-865f-e41d3fb39a80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689199502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.1689199502 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.3873215735 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 88093236775 ps |
| CPU time | 911.07 seconds |
| Started | Jul 30 08:33:41 PM PDT 24 |
| Finished | Jul 30 08:48:52 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-ce7abbab-8574-43be-919b-5e7b1b1535d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873215735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3873215735 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.3643285879 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 69779582202 ps |
| CPU time | 1313.2 seconds |
| Started | Jul 30 08:33:44 PM PDT 24 |
| Finished | Jul 30 08:55:37 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-51a6c593-b0c2-4e39-bd6f-01e52fedd326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643285879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3643285879 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.2703517857 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 544527189 ps |
| CPU time | 49.82 seconds |
| Started | Jul 30 08:33:40 PM PDT 24 |
| Finished | Jul 30 08:34:31 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-b1727729-9139-4e8c-9e8e-f650bec69d38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703517857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.2703517857 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.3717473485 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 2357485916 ps |
| CPU time | 69.06 seconds |
| Started | Jul 30 08:33:50 PM PDT 24 |
| Finished | Jul 30 08:34:59 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-0c681196-7488-44e1-a35b-e8d4241f95c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717473485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3717473485 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.3966365038 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 256789427 ps |
| CPU time | 11.15 seconds |
| Started | Jul 30 08:33:36 PM PDT 24 |
| Finished | Jul 30 08:33:47 PM PDT 24 |
| Peak memory | 573844 kb |
| Host | smart-67c13922-ab9c-48b1-b09a-498b87f539e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966365038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3966365038 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.1600461668 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 7049933874 ps |
| CPU time | 75.69 seconds |
| Started | Jul 30 08:33:45 PM PDT 24 |
| Finished | Jul 30 08:35:00 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-c024a3e9-4ac1-4ce9-b21b-a22d9f7ea945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600461668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1600461668 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.154522534 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 4275532470 ps |
| CPU time | 76.26 seconds |
| Started | Jul 30 08:33:46 PM PDT 24 |
| Finished | Jul 30 08:35:02 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-1837f852-6a04-43d5-abb3-2ef2c6a225b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154522534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.154522534 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.326834280 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 49389259 ps |
| CPU time | 6.88 seconds |
| Started | Jul 30 08:33:46 PM PDT 24 |
| Finished | Jul 30 08:33:53 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-080001cd-65dc-4906-92fd-2b1d80775bb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326834280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays .326834280 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.2701083320 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 3060469248 ps |
| CPU time | 220.94 seconds |
| Started | Jul 30 08:33:46 PM PDT 24 |
| Finished | Jul 30 08:37:27 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-e5d26131-af6c-4a96-a040-a4f322f5355d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701083320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2701083320 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.2624529740 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 289591920 ps |
| CPU time | 132.22 seconds |
| Started | Jul 30 08:33:48 PM PDT 24 |
| Finished | Jul 30 08:36:00 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-43d9d4d2-fe21-4aa2-b350-6da93985026a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624529740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.2624529740 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.437267611 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 159883676 ps |
| CPU time | 79.31 seconds |
| Started | Jul 30 08:33:49 PM PDT 24 |
| Finished | Jul 30 08:35:08 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-8d37f6d7-bcbb-4374-a854-cc06acb7a40d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437267611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_reset_error.437267611 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.3572663979 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 1111083847 ps |
| CPU time | 50.61 seconds |
| Started | Jul 30 08:33:44 PM PDT 24 |
| Finished | Jul 30 08:34:35 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-9622574d-c499-45be-adc6-aad94c8b6a1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572663979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3572663979 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.811778755 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 5943104720 ps |
| CPU time | 607.66 seconds |
| Started | Jul 30 08:34:10 PM PDT 24 |
| Finished | Jul 30 08:44:17 PM PDT 24 |
| Peak memory | 638664 kb |
| Host | smart-4242866c-e804-414b-9867-218b3743865f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811778755 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.811778755 |
| Directory | /workspace/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.3023764668 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 4420795364 ps |
| CPU time | 286.21 seconds |
| Started | Jul 30 08:34:11 PM PDT 24 |
| Finished | Jul 30 08:38:57 PM PDT 24 |
| Peak memory | 597636 kb |
| Host | smart-8a19363b-e226-41aa-9b62-78311efc1d38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023764668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.3023764668 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.3183592494 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 16709792012 ps |
| CPU time | 2322.63 seconds |
| Started | Jul 30 08:33:49 PM PDT 24 |
| Finished | Jul 30 09:12:32 PM PDT 24 |
| Peak memory | 593456 kb |
| Host | smart-0c28ae44-d5b1-45f6-92d0-e06a704f4dbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183592494 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.3183592494 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.3484793608 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 129209679 ps |
| CPU time | 10.49 seconds |
| Started | Jul 30 08:34:05 PM PDT 24 |
| Finished | Jul 30 08:34:15 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-adf3ff6c-8533-4a66-8bfe-70b415513e9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484793608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .3484793608 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2539216223 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 452444025 ps |
| CPU time | 22.68 seconds |
| Started | Jul 30 08:34:08 PM PDT 24 |
| Finished | Jul 30 08:34:31 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-ebbbee82-8add-43c2-b3e7-b0941fda3af1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539216223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.2539216223 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.1863658971 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1061447672 ps |
| CPU time | 40.98 seconds |
| Started | Jul 30 08:34:08 PM PDT 24 |
| Finished | Jul 30 08:34:49 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-6ed2c722-5375-45ca-b8a8-da1d4cb9891d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863658971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1863658971 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.1961065565 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 330053058 ps |
| CPU time | 30.84 seconds |
| Started | Jul 30 08:34:00 PM PDT 24 |
| Finished | Jul 30 08:34:31 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-464e137e-3b02-425c-aa64-da3ae2d357e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961065565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.1961065565 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.2532414875 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 32627526785 ps |
| CPU time | 329.66 seconds |
| Started | Jul 30 08:33:59 PM PDT 24 |
| Finished | Jul 30 08:39:29 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-3a78ceaf-afcb-4df8-b92c-cc60bd87a061 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532414875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2532414875 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.3107749690 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 67565376677 ps |
| CPU time | 1006.37 seconds |
| Started | Jul 30 08:33:59 PM PDT 24 |
| Finished | Jul 30 08:50:46 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-63e8b2ed-dfe8-45e8-bbea-b6d5968d8aaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107749690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3107749690 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.297260134 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 602028168 ps |
| CPU time | 46.73 seconds |
| Started | Jul 30 08:34:01 PM PDT 24 |
| Finished | Jul 30 08:34:47 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-6be2c01b-17a2-4a9b-8db5-2a049e060af6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297260134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_dela ys.297260134 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.3702077846 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 67302926 ps |
| CPU time | 8.9 seconds |
| Started | Jul 30 08:34:03 PM PDT 24 |
| Finished | Jul 30 08:34:12 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-bb11af46-c02e-4bf8-81f1-82e9d37a6ad9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702077846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3702077846 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.3321466870 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 241191450 ps |
| CPU time | 11.55 seconds |
| Started | Jul 30 08:33:51 PM PDT 24 |
| Finished | Jul 30 08:34:03 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-4c3f6b98-2e86-47af-8ab8-5883b7ae68a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321466870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3321466870 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.4209537930 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 7489878807 ps |
| CPU time | 78.49 seconds |
| Started | Jul 30 08:33:54 PM PDT 24 |
| Finished | Jul 30 08:35:12 PM PDT 24 |
| Peak memory | 573864 kb |
| Host | smart-421fc4c2-88de-4dbe-97c6-af849d92ee5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209537930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.4209537930 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3796688182 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 4872010413 ps |
| CPU time | 80.59 seconds |
| Started | Jul 30 08:33:59 PM PDT 24 |
| Finished | Jul 30 08:35:20 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-a1eb7101-3586-4f35-b932-7de8ddec461f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796688182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3796688182 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.2741680885 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 45938354 ps |
| CPU time | 6.16 seconds |
| Started | Jul 30 08:33:57 PM PDT 24 |
| Finished | Jul 30 08:34:04 PM PDT 24 |
| Peak memory | 573820 kb |
| Host | smart-712f04c4-a989-4fb9-a13a-109ccac6057f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741680885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.2741680885 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.1255633982 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 3117930222 ps |
| CPU time | 123.05 seconds |
| Started | Jul 30 08:34:09 PM PDT 24 |
| Finished | Jul 30 08:36:12 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-67ee6ca8-c42d-449a-b301-bfa3e655dabf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255633982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1255633982 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.3885939562 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 15848106295 ps |
| CPU time | 612.4 seconds |
| Started | Jul 30 08:34:12 PM PDT 24 |
| Finished | Jul 30 08:44:24 PM PDT 24 |
| Peak memory | 576156 kb |
| Host | smart-51e6845b-b65b-4a88-a4a4-d17de9365a35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885939562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3885939562 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.856424250 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 266202163 ps |
| CPU time | 89.04 seconds |
| Started | Jul 30 08:34:12 PM PDT 24 |
| Finished | Jul 30 08:35:41 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-55a9ff9c-65b7-4685-8ecb-108a1de64099 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856424250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_ with_rand_reset.856424250 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1818029717 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 3236572120 ps |
| CPU time | 208.64 seconds |
| Started | Jul 30 08:34:11 PM PDT 24 |
| Finished | Jul 30 08:37:40 PM PDT 24 |
| Peak memory | 576992 kb |
| Host | smart-35879541-929f-43b7-ba57-2533c2971039 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818029717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.1818029717 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.9981222 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 69039223 ps |
| CPU time | 6.45 seconds |
| Started | Jul 30 08:34:03 PM PDT 24 |
| Finished | Jul 30 08:34:10 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-260e4a02-93b7-47cb-adfa-213697bec07d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9981222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.9981222 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.1507234894 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 4710440255 ps |
| CPU time | 359.69 seconds |
| Started | Jul 30 08:34:33 PM PDT 24 |
| Finished | Jul 30 08:40:33 PM PDT 24 |
| Peak memory | 598192 kb |
| Host | smart-325fc6e8-5e7d-4b63-9c1e-f1f19f5e9672 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507234894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.1507234894 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.840028779 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 15724762886 ps |
| CPU time | 2063.99 seconds |
| Started | Jul 30 08:34:14 PM PDT 24 |
| Finished | Jul 30 09:08:38 PM PDT 24 |
| Peak memory | 593024 kb |
| Host | smart-805a297e-d5f2-43d7-9f2d-d9f8261155df |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840028779 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 19.chip_same_csr_outstanding.840028779 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.1394769508 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 4266604995 ps |
| CPU time | 431.54 seconds |
| Started | Jul 30 08:34:15 PM PDT 24 |
| Finished | Jul 30 08:41:26 PM PDT 24 |
| Peak memory | 603696 kb |
| Host | smart-8123661e-94de-42ac-9366-6741e94d5092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394769508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.1394769508 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.926119342 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 1245308465 ps |
| CPU time | 94.45 seconds |
| Started | Jul 30 08:34:17 PM PDT 24 |
| Finished | Jul 30 08:35:52 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-29b03007-36c0-4ba7-a6b9-9e90a6ee0de5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926119342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device. 926119342 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.730480258 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 33781691092 ps |
| CPU time | 628.47 seconds |
| Started | Jul 30 08:34:21 PM PDT 24 |
| Finished | Jul 30 08:44:50 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-ee49e726-30ef-46ed-9a5e-2ac2d555497c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730480258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_d evice_slow_rsp.730480258 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1068792593 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 1043283980 ps |
| CPU time | 45.06 seconds |
| Started | Jul 30 08:34:31 PM PDT 24 |
| Finished | Jul 30 08:35:16 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-47cfc659-52d0-4375-88e0-f5933a6d14c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068792593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.1068792593 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.4289642010 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 595270081 ps |
| CPU time | 51.16 seconds |
| Started | Jul 30 08:34:25 PM PDT 24 |
| Finished | Jul 30 08:35:17 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-affd221f-baee-4b3c-98d8-206f5812cd52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289642010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.4289642010 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.3522107834 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 2785865133 ps |
| CPU time | 119.31 seconds |
| Started | Jul 30 08:34:18 PM PDT 24 |
| Finished | Jul 30 08:36:17 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-a09bf136-3696-4c5d-9da8-9c4af29f452c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522107834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.3522107834 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.3142298423 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 98216334926 ps |
| CPU time | 1012.99 seconds |
| Started | Jul 30 08:34:18 PM PDT 24 |
| Finished | Jul 30 08:51:11 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-17bd3f97-d14c-4360-982c-3ecbdeb7027a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142298423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3142298423 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.138520887 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 11002958470 ps |
| CPU time | 187.17 seconds |
| Started | Jul 30 08:34:21 PM PDT 24 |
| Finished | Jul 30 08:37:28 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-fb0ce958-12de-4d9c-8160-4890d68fa30c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138520887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.138520887 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.3185047260 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 89067857 ps |
| CPU time | 10.53 seconds |
| Started | Jul 30 08:34:18 PM PDT 24 |
| Finished | Jul 30 08:34:29 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-48afcb4c-3b74-4f53-8e01-acb3ca352ad4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185047260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.3185047260 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.3462463366 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 194617778 ps |
| CPU time | 16.56 seconds |
| Started | Jul 30 08:34:22 PM PDT 24 |
| Finished | Jul 30 08:34:39 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-18d9e652-fb3c-4fef-a154-0942840b8781 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462463366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3462463366 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.3186642916 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 233262906 ps |
| CPU time | 10.68 seconds |
| Started | Jul 30 08:34:12 PM PDT 24 |
| Finished | Jul 30 08:34:23 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-8a26edd2-6f0e-4164-a5a5-a96211c36d4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186642916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3186642916 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.1745181463 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 8730375609 ps |
| CPU time | 91.08 seconds |
| Started | Jul 30 08:34:14 PM PDT 24 |
| Finished | Jul 30 08:35:46 PM PDT 24 |
| Peak memory | 573924 kb |
| Host | smart-1a1b4124-08f6-4cae-ad28-16c6a9c75b50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745181463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1745181463 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.1444660937 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 4411105846 ps |
| CPU time | 77.36 seconds |
| Started | Jul 30 08:34:18 PM PDT 24 |
| Finished | Jul 30 08:35:35 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-ecf6b469-9c0a-4be5-abd8-4f66c4cf7107 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444660937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1444660937 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.1327037617 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 46381294 ps |
| CPU time | 6.44 seconds |
| Started | Jul 30 08:34:14 PM PDT 24 |
| Finished | Jul 30 08:34:20 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-a99253d3-66fa-4551-afc4-0cfd53e028bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327037617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.1327037617 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.2854749068 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 404738288 ps |
| CPU time | 40.38 seconds |
| Started | Jul 30 08:34:30 PM PDT 24 |
| Finished | Jul 30 08:35:10 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-0714544f-5a21-4566-98fb-a1945d14d394 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854749068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2854749068 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.2398947992 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 3764460515 ps |
| CPU time | 161.41 seconds |
| Started | Jul 30 08:34:29 PM PDT 24 |
| Finished | Jul 30 08:37:11 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-5841794f-ae6e-44b8-893e-01175dd35873 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398947992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2398947992 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2254632559 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 676455602 ps |
| CPU time | 321.71 seconds |
| Started | Jul 30 08:34:32 PM PDT 24 |
| Finished | Jul 30 08:39:54 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-4d942d20-6681-4b1e-a5d4-4d2e6ec6aeea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254632559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_rand_reset.2254632559 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.2104054121 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 10240578396 ps |
| CPU time | 505.49 seconds |
| Started | Jul 30 08:34:35 PM PDT 24 |
| Finished | Jul 30 08:43:01 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-e6bf3f85-de94-458e-a7e6-cfff590bd9de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104054121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.2104054121 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.177642068 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 1231519327 ps |
| CPU time | 54.35 seconds |
| Started | Jul 30 08:34:31 PM PDT 24 |
| Finished | Jul 30 08:35:25 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-27fc7611-7d19-4b39-8245-3e6d6375e9c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177642068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.177642068 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.67812771 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 6191589483 ps |
| CPU time | 701.62 seconds |
| Started | Jul 30 08:26:30 PM PDT 24 |
| Finished | Jul 30 08:38:12 PM PDT 24 |
| Peak memory | 592736 kb |
| Host | smart-4af7bb48-3eba-441c-af45-d828dd371bb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67812771 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.67812771 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1253939250 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 7156552328 ps |
| CPU time | 377.52 seconds |
| Started | Jul 30 08:27:19 PM PDT 24 |
| Finished | Jul 30 08:33:37 PM PDT 24 |
| Peak memory | 662168 kb |
| Host | smart-54b48498-17c1-4796-bc41-31c748d21f44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253939250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.1253939250 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.2524181755 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 6970535710 ps |
| CPU time | 507.55 seconds |
| Started | Jul 30 08:27:29 PM PDT 24 |
| Finished | Jul 30 08:35:56 PM PDT 24 |
| Peak memory | 638980 kb |
| Host | smart-594f6007-f3b3-4fd5-93af-23eae685b802 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524181755 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.2524181755 |
| Directory | /workspace/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.2856926238 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 4509137460 ps |
| CPU time | 393.9 seconds |
| Started | Jul 30 08:27:30 PM PDT 24 |
| Finished | Jul 30 08:34:04 PM PDT 24 |
| Peak memory | 597464 kb |
| Host | smart-79157e18-2987-4a3d-b6c2-06394b0ca984 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856926238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.2856926238 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.3854871407 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 9514732962 ps |
| CPU time | 472.64 seconds |
| Started | Jul 30 08:26:36 PM PDT 24 |
| Finished | Jul 30 08:34:29 PM PDT 24 |
| Peak memory | 590088 kb |
| Host | smart-18664556-68b8-45ba-9063-2fe6bd5944c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854871407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.3854871407 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.3325428986 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 20277609670 ps |
| CPU time | 965.89 seconds |
| Started | Jul 30 08:27:11 PM PDT 24 |
| Finished | Jul 30 08:43:17 PM PDT 24 |
| Peak memory | 591272 kb |
| Host | smart-792926e5-f8f1-4556-8f87-28b37f413787 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325428986 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.3325428986 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.1541407630 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 16245453795 ps |
| CPU time | 1830.29 seconds |
| Started | Jul 30 08:26:34 PM PDT 24 |
| Finished | Jul 30 08:57:04 PM PDT 24 |
| Peak memory | 593000 kb |
| Host | smart-4b51439b-72f4-477a-9121-8359a1f49445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541407630 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.1541407630 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.3268382845 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 3571658600 ps |
| CPU time | 184.38 seconds |
| Started | Jul 30 08:26:35 PM PDT 24 |
| Finished | Jul 30 08:29:40 PM PDT 24 |
| Peak memory | 598856 kb |
| Host | smart-64f600d0-473b-4315-baaa-96b32f2b0f93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268382845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.3268382845 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.444896241 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 2338342286 ps |
| CPU time | 104.52 seconds |
| Started | Jul 30 08:26:53 PM PDT 24 |
| Finished | Jul 30 08:28:37 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-334e3a57-3613-4145-b80f-ae9a2ba7bce5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444896241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.444896241 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2243455441 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 103513885133 ps |
| CPU time | 1925.42 seconds |
| Started | Jul 30 08:26:54 PM PDT 24 |
| Finished | Jul 30 08:59:00 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-eef929a5-0c98-4dda-aeaf-b2609b99acd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243455441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.2243455441 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.4153299129 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 322746131 ps |
| CPU time | 44 seconds |
| Started | Jul 30 08:27:10 PM PDT 24 |
| Finished | Jul 30 08:27:54 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-d889e68e-4eca-46ef-bd71-dbcc4e66d7d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153299129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .4153299129 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.4073289848 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 264849411 ps |
| CPU time | 25.8 seconds |
| Started | Jul 30 08:27:05 PM PDT 24 |
| Finished | Jul 30 08:27:31 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-b1a787fc-3283-4fca-9f66-af0a33d47dfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073289848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.4073289848 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.2472611398 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 1804581425 ps |
| CPU time | 83.45 seconds |
| Started | Jul 30 08:27:22 PM PDT 24 |
| Finished | Jul 30 08:28:46 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-e56abe4b-305c-4d45-a933-457e26287fce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472611398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.2472611398 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.1583672972 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 79834242691 ps |
| CPU time | 848.74 seconds |
| Started | Jul 30 08:26:48 PM PDT 24 |
| Finished | Jul 30 08:40:57 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-1cb78447-2c64-4bb0-98c8-b4b56debaf3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583672972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1583672972 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.2838749838 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 13911787153 ps |
| CPU time | 247.49 seconds |
| Started | Jul 30 08:26:55 PM PDT 24 |
| Finished | Jul 30 08:31:03 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-959405e8-d68f-45cf-a39c-e234045869df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838749838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2838749838 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.600387735 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 219954622 ps |
| CPU time | 24.67 seconds |
| Started | Jul 30 08:26:52 PM PDT 24 |
| Finished | Jul 30 08:27:17 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-9e0265cc-b899-400d-ad8c-35158ee49fdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600387735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delay s.600387735 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.3356131558 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 246283419 ps |
| CPU time | 23.88 seconds |
| Started | Jul 30 08:27:00 PM PDT 24 |
| Finished | Jul 30 08:27:24 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-a106560e-4687-4f30-8ee0-0b9422aa98b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356131558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3356131558 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.3306585965 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 172317452 ps |
| CPU time | 8.68 seconds |
| Started | Jul 30 08:26:32 PM PDT 24 |
| Finished | Jul 30 08:26:41 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-104fbbb8-e4ea-4cb6-990b-fa161bae34dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306585965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3306585965 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.1272928069 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 8513408948 ps |
| CPU time | 87.8 seconds |
| Started | Jul 30 08:26:35 PM PDT 24 |
| Finished | Jul 30 08:28:03 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-cc97c279-9cd1-44ae-9555-ed971f6da427 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272928069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1272928069 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.432674899 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 3566511881 ps |
| CPU time | 60.78 seconds |
| Started | Jul 30 08:26:40 PM PDT 24 |
| Finished | Jul 30 08:27:41 PM PDT 24 |
| Peak memory | 574576 kb |
| Host | smart-d5927ea8-62e9-44b7-8bfb-a41a13ab4e8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432674899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.432674899 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2254335658 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 43815035 ps |
| CPU time | 6.15 seconds |
| Started | Jul 30 08:26:36 PM PDT 24 |
| Finished | Jul 30 08:26:42 PM PDT 24 |
| Peak memory | 573864 kb |
| Host | smart-1b94979c-7f2f-4374-9451-dbd41b85bda7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254335658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .2254335658 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.117460685 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 19133998918 ps |
| CPU time | 866.61 seconds |
| Started | Jul 30 08:27:11 PM PDT 24 |
| Finished | Jul 30 08:41:38 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-48f26af2-f1ac-4a66-973d-7d528c03fe8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117460685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.117460685 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.2136117173 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 6396302300 ps |
| CPU time | 249.18 seconds |
| Started | Jul 30 08:27:16 PM PDT 24 |
| Finished | Jul 30 08:31:26 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-e8736772-8c35-4aae-9a14-c44bdee113d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136117173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.2136117173 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.2157322194 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 3536500602 ps |
| CPU time | 434.98 seconds |
| Started | Jul 30 08:27:14 PM PDT 24 |
| Finished | Jul 30 08:34:29 PM PDT 24 |
| Peak memory | 576160 kb |
| Host | smart-5b197c57-ddfb-48ee-8ee6-1f038c1989f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157322194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.2157322194 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.2812961432 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 187240838 ps |
| CPU time | 68.91 seconds |
| Started | Jul 30 08:27:16 PM PDT 24 |
| Finished | Jul 30 08:28:25 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-c2612651-1f80-4456-8cd4-fc72ca9a1b69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812961432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.2812961432 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.3563122067 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 1389755539 ps |
| CPU time | 61.39 seconds |
| Started | Jul 30 08:27:05 PM PDT 24 |
| Finished | Jul 30 08:28:06 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-f1de700d-1033-4f25-bcf8-33e12bbf3f12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563122067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3563122067 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.3043026722 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 4453621189 ps |
| CPU time | 317.88 seconds |
| Started | Jul 30 08:34:33 PM PDT 24 |
| Finished | Jul 30 08:39:51 PM PDT 24 |
| Peak memory | 598616 kb |
| Host | smart-035abdbb-9fcd-45de-a12e-419a908191e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043026722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.3043026722 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.1972968706 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 2063669751 ps |
| CPU time | 106.51 seconds |
| Started | Jul 30 08:34:36 PM PDT 24 |
| Finished | Jul 30 08:36:22 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-3ffc9009-8a69-4cb0-90a5-9a434b4233be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972968706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .1972968706 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.205001110 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 88272015182 ps |
| CPU time | 1505.1 seconds |
| Started | Jul 30 08:34:43 PM PDT 24 |
| Finished | Jul 30 08:59:48 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-0fe6f6ae-ae57-417f-ad29-3c901787bc10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205001110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_d evice_slow_rsp.205001110 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.3404875842 |
| Short name | T2920 |
| Test name | |
| Test status | |
| Simulation time | 1429420515 ps |
| CPU time | 48.04 seconds |
| Started | Jul 30 08:34:44 PM PDT 24 |
| Finished | Jul 30 08:35:32 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-ea995bd1-2f80-4de7-be64-f1bc61ec2c6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404875842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.3404875842 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.2285289976 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 133746050 ps |
| CPU time | 13.96 seconds |
| Started | Jul 30 08:34:41 PM PDT 24 |
| Finished | Jul 30 08:34:55 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-6837d1b0-3cdf-4637-bebe-64f38d02899c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285289976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2285289976 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.1915618580 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 109904331 ps |
| CPU time | 7.08 seconds |
| Started | Jul 30 08:34:37 PM PDT 24 |
| Finished | Jul 30 08:34:44 PM PDT 24 |
| Peak memory | 573896 kb |
| Host | smart-c8d6708f-6048-49fe-95b4-32355c7b35ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915618580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.1915618580 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.3195597642 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 41246558003 ps |
| CPU time | 457.43 seconds |
| Started | Jul 30 08:34:37 PM PDT 24 |
| Finished | Jul 30 08:42:15 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-397bfc02-342d-4b98-bf79-bbd645a5b1ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195597642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3195597642 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.2373799602 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 17739855520 ps |
| CPU time | 316.08 seconds |
| Started | Jul 30 08:34:38 PM PDT 24 |
| Finished | Jul 30 08:39:54 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-9abe32cd-88ee-40bc-82b1-fbfc50da4677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373799602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.2373799602 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.3254720734 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 533636172 ps |
| CPU time | 51.44 seconds |
| Started | Jul 30 08:34:36 PM PDT 24 |
| Finished | Jul 30 08:35:27 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-52d77282-f84d-443a-81c5-0f66458a7e0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254720734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.3254720734 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.4171050172 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 2691644155 ps |
| CPU time | 85.47 seconds |
| Started | Jul 30 08:34:40 PM PDT 24 |
| Finished | Jul 30 08:36:06 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-47458470-7815-448e-b724-145eed7eb52c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171050172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.4171050172 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.2899358359 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 162985131 ps |
| CPU time | 8.2 seconds |
| Started | Jul 30 08:34:34 PM PDT 24 |
| Finished | Jul 30 08:34:42 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-fbad1c64-a84a-440a-ba7b-37a95f11dd7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899358359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2899358359 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.4006218299 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 8857260204 ps |
| CPU time | 94.45 seconds |
| Started | Jul 30 08:34:33 PM PDT 24 |
| Finished | Jul 30 08:36:07 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-7d8c8f2b-718a-4737-8c9b-b1cc2b807847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006218299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.4006218299 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.644429258 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 6079321899 ps |
| CPU time | 98.55 seconds |
| Started | Jul 30 08:34:35 PM PDT 24 |
| Finished | Jul 30 08:36:14 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-a2c42d19-76f7-4168-8996-6dca0f35dced |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644429258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.644429258 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.3770619133 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 44819820 ps |
| CPU time | 6.63 seconds |
| Started | Jul 30 08:34:33 PM PDT 24 |
| Finished | Jul 30 08:34:39 PM PDT 24 |
| Peak memory | 573852 kb |
| Host | smart-d1e846da-9dbc-4650-9d5d-ae5ef9eb6433 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770619133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.3770619133 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.4182831631 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 1549943091 ps |
| CPU time | 59.18 seconds |
| Started | Jul 30 08:34:44 PM PDT 24 |
| Finished | Jul 30 08:35:43 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-6ee395a0-9d32-426a-b027-5b114fa954c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182831631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.4182831631 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.1036875450 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 879771891 ps |
| CPU time | 72.99 seconds |
| Started | Jul 30 08:34:43 PM PDT 24 |
| Finished | Jul 30 08:35:56 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-fffac216-59c2-4433-bf2d-b24549c697dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036875450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1036875450 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.792531801 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 1833169544 ps |
| CPU time | 242.87 seconds |
| Started | Jul 30 08:34:44 PM PDT 24 |
| Finished | Jul 30 08:38:46 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-da643bfa-e2f0-430b-92d1-8df9633d665d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792531801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_ with_rand_reset.792531801 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.3020782663 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 16410568252 ps |
| CPU time | 771.94 seconds |
| Started | Jul 30 08:34:46 PM PDT 24 |
| Finished | Jul 30 08:47:38 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-419984d1-05f1-4e30-94ea-56b609910341 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020782663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al l_with_reset_error.3020782663 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.3516510031 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 37258403 ps |
| CPU time | 7.5 seconds |
| Started | Jul 30 08:34:41 PM PDT 24 |
| Finished | Jul 30 08:34:49 PM PDT 24 |
| Peak memory | 573884 kb |
| Host | smart-2c0262bf-c60e-4e75-b711-0509e93009d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516510031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3516510031 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.673708474 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 2073308811 ps |
| CPU time | 99.81 seconds |
| Started | Jul 30 08:34:51 PM PDT 24 |
| Finished | Jul 30 08:36:31 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-3d229dec-cc78-4481-a7c2-be2bb8a072aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673708474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device. 673708474 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.2758947188 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 139627914683 ps |
| CPU time | 2360.17 seconds |
| Started | Jul 30 08:34:54 PM PDT 24 |
| Finished | Jul 30 09:14:15 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-b5a749d1-6be9-48a5-8c13-ddad68fa6ddf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758947188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.2758947188 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.2399000274 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 330794681 ps |
| CPU time | 41.46 seconds |
| Started | Jul 30 08:34:55 PM PDT 24 |
| Finished | Jul 30 08:35:37 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-e092d35e-4d72-4f8a-8652-810757d350bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399000274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.2399000274 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.2513914094 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 281475711 ps |
| CPU time | 25.64 seconds |
| Started | Jul 30 08:35:00 PM PDT 24 |
| Finished | Jul 30 08:35:26 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-5f51e522-4233-441c-95ef-2a73b9d2e487 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513914094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2513914094 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.1151551691 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 597356192 ps |
| CPU time | 22.26 seconds |
| Started | Jul 30 08:34:48 PM PDT 24 |
| Finished | Jul 30 08:35:10 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-07c05769-26e2-48f2-99cf-a4176f50ad7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151551691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.1151551691 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.3340238040 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 32640117699 ps |
| CPU time | 344.34 seconds |
| Started | Jul 30 08:34:51 PM PDT 24 |
| Finished | Jul 30 08:40:35 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-b14345bf-8eca-40fa-8fb3-0d0a33b28505 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340238040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3340238040 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.1072491723 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 44433389497 ps |
| CPU time | 796.1 seconds |
| Started | Jul 30 08:34:52 PM PDT 24 |
| Finished | Jul 30 08:48:08 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-7a6d778d-b993-4d16-9a1e-5a4f2f195e25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072491723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1072491723 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.4027465746 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 460985278 ps |
| CPU time | 46.86 seconds |
| Started | Jul 30 08:34:50 PM PDT 24 |
| Finished | Jul 30 08:35:37 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-b06f6305-10aa-424d-b24f-8e88ce58ef91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027465746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.4027465746 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.3632008037 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 567960087 ps |
| CPU time | 35.96 seconds |
| Started | Jul 30 08:34:52 PM PDT 24 |
| Finished | Jul 30 08:35:28 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-5f548676-6fde-4113-b8ff-e64f32b21bd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632008037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3632008037 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.4174721670 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 193878557 ps |
| CPU time | 9.37 seconds |
| Started | Jul 30 08:34:49 PM PDT 24 |
| Finished | Jul 30 08:34:59 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-9eb98a28-1a22-4025-b68d-d8471bf31311 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174721670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.4174721670 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.221064656 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 9930435236 ps |
| CPU time | 105.39 seconds |
| Started | Jul 30 08:34:47 PM PDT 24 |
| Finished | Jul 30 08:36:33 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-8653a5da-83a2-4573-8990-ae7bc79f9abf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221064656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.221064656 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.2319784420 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 5200520591 ps |
| CPU time | 80.76 seconds |
| Started | Jul 30 08:34:52 PM PDT 24 |
| Finished | Jul 30 08:36:13 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-e93c4595-4751-4b5d-ba98-d2b9164b1276 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319784420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2319784420 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.3718926208 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 43686288 ps |
| CPU time | 6.53 seconds |
| Started | Jul 30 08:34:49 PM PDT 24 |
| Finished | Jul 30 08:34:56 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-ece43e90-9518-4834-adda-3450df5b75db |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718926208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.3718926208 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.2697628473 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 1461291890 ps |
| CPU time | 136.24 seconds |
| Started | Jul 30 08:34:55 PM PDT 24 |
| Finished | Jul 30 08:37:12 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-15752968-0f6a-4bc0-b9ef-1358ba055b01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697628473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.2697628473 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.2339102896 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 4808038558 ps |
| CPU time | 191.41 seconds |
| Started | Jul 30 08:35:00 PM PDT 24 |
| Finished | Jul 30 08:38:12 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-d3614357-1ed4-48b6-aab7-026803dbfda8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339102896 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2339102896 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.2355258556 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1703684020 ps |
| CPU time | 567.57 seconds |
| Started | Jul 30 08:35:02 PM PDT 24 |
| Finished | Jul 30 08:44:29 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-88226470-c9dc-4224-841d-01d8df6c6d28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355258556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.2355258556 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.2074009726 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 1116163088 ps |
| CPU time | 178.27 seconds |
| Started | Jul 30 08:35:01 PM PDT 24 |
| Finished | Jul 30 08:37:59 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-5b267d6f-581f-4157-bf8b-5f9bf79de7ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074009726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.2074009726 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.722003686 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 712978057 ps |
| CPU time | 29.68 seconds |
| Started | Jul 30 08:35:00 PM PDT 24 |
| Finished | Jul 30 08:35:30 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-cbb1d258-5b80-46e5-853c-5a82843fcf22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722003686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.722003686 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.1037934419 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 3679623080 ps |
| CPU time | 306.47 seconds |
| Started | Jul 30 08:34:59 PM PDT 24 |
| Finished | Jul 30 08:40:05 PM PDT 24 |
| Peak memory | 598820 kb |
| Host | smart-057e7454-a300-46d8-9752-79017beb936d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037934419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.1037934419 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.839226011 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 26039152 ps |
| CPU time | 10.77 seconds |
| Started | Jul 30 08:35:06 PM PDT 24 |
| Finished | Jul 30 08:35:17 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-9a88a7e5-e669-417c-af15-52248377f40c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839226011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device. 839226011 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.1657799438 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 55091248693 ps |
| CPU time | 999.23 seconds |
| Started | Jul 30 08:35:07 PM PDT 24 |
| Finished | Jul 30 08:51:46 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-a691affb-7905-4c12-9185-9f13235e13ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657799438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.1657799438 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.2876408623 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 491937144 ps |
| CPU time | 22.5 seconds |
| Started | Jul 30 08:35:12 PM PDT 24 |
| Finished | Jul 30 08:35:34 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-d8394ba7-c844-473f-a457-ea9de0bb8433 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876408623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.2876408623 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.4131639169 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 255137380 ps |
| CPU time | 13.35 seconds |
| Started | Jul 30 08:35:08 PM PDT 24 |
| Finished | Jul 30 08:35:21 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-c87c8919-4827-4a0b-9655-51cfa198c042 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131639169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.4131639169 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.2464632071 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 35911670 ps |
| CPU time | 6.81 seconds |
| Started | Jul 30 08:35:03 PM PDT 24 |
| Finished | Jul 30 08:35:10 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-54a0d38c-d27b-45c4-8181-8f39cb082063 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464632071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.2464632071 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.3284338588 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 68470802364 ps |
| CPU time | 689.4 seconds |
| Started | Jul 30 08:35:04 PM PDT 24 |
| Finished | Jul 30 08:46:33 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-82e10736-3459-492c-a63f-e5b2015a594a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284338588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3284338588 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.1711259346 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 47374625909 ps |
| CPU time | 837.17 seconds |
| Started | Jul 30 08:35:03 PM PDT 24 |
| Finished | Jul 30 08:49:00 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-efc17604-2262-454a-ba1f-1eb8729f74a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711259346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1711259346 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.4191056599 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 105637113 ps |
| CPU time | 13.06 seconds |
| Started | Jul 30 08:35:06 PM PDT 24 |
| Finished | Jul 30 08:35:19 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-b384f356-595c-4067-93f6-eac0c10b77b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191056599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.4191056599 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.3791046057 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 247207282 ps |
| CPU time | 22.71 seconds |
| Started | Jul 30 08:35:08 PM PDT 24 |
| Finished | Jul 30 08:35:31 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-f81c886f-f982-4be1-961a-7f8d91e2869e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791046057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3791046057 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.798087119 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 194163388 ps |
| CPU time | 9.14 seconds |
| Started | Jul 30 08:35:00 PM PDT 24 |
| Finished | Jul 30 08:35:09 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-71886d60-94a9-4bed-b89b-c439f9f442c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798087119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.798087119 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.3565245964 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 8745509222 ps |
| CPU time | 93.37 seconds |
| Started | Jul 30 08:35:01 PM PDT 24 |
| Finished | Jul 30 08:36:35 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-1652843a-f5c6-4011-b8da-269621b069d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565245964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.3565245964 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.385920813 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 6212050119 ps |
| CPU time | 107.71 seconds |
| Started | Jul 30 08:35:04 PM PDT 24 |
| Finished | Jul 30 08:36:51 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-183596b9-10d1-4bce-9f66-59b64489e29d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385920813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.385920813 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.2670988529 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 42198168 ps |
| CPU time | 6.79 seconds |
| Started | Jul 30 08:34:59 PM PDT 24 |
| Finished | Jul 30 08:35:06 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-2bfa7f6c-2c57-4335-b405-57895b2eb6b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670988529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.2670988529 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.2160138227 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 6574235304 ps |
| CPU time | 273.6 seconds |
| Started | Jul 30 08:35:09 PM PDT 24 |
| Finished | Jul 30 08:39:42 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-8ead2dc6-cc24-4870-87c4-95ea270e451e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160138227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2160138227 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.1209203769 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 13655795651 ps |
| CPU time | 522.43 seconds |
| Started | Jul 30 08:35:12 PM PDT 24 |
| Finished | Jul 30 08:43:55 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-43396999-6be0-4c4b-91b4-9d87969237e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209203769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1209203769 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.512828555 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 6479749241 ps |
| CPU time | 479.86 seconds |
| Started | Jul 30 08:35:09 PM PDT 24 |
| Finished | Jul 30 08:43:09 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-1334db91-fec1-4030-a00b-037aa7db456c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512828555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_ with_rand_reset.512828555 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3138536282 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 11777647919 ps |
| CPU time | 561.91 seconds |
| Started | Jul 30 08:35:13 PM PDT 24 |
| Finished | Jul 30 08:44:35 PM PDT 24 |
| Peak memory | 576868 kb |
| Host | smart-ba4dcd81-8b4f-4b38-aa78-2783da23443f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138536282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.3138536282 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.1418817745 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 625266542 ps |
| CPU time | 25.96 seconds |
| Started | Jul 30 08:35:06 PM PDT 24 |
| Finished | Jul 30 08:35:32 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-f8e02ed0-75f1-4182-8619-27f0cb5ef192 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418817745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1418817745 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.3319847862 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 2927784350 ps |
| CPU time | 278.86 seconds |
| Started | Jul 30 08:35:14 PM PDT 24 |
| Finished | Jul 30 08:39:53 PM PDT 24 |
| Peak memory | 598700 kb |
| Host | smart-f3551808-af07-4c5a-990e-19ed48726d65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319847862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.3319847862 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.386044537 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 200397578 ps |
| CPU time | 19.65 seconds |
| Started | Jul 30 08:35:17 PM PDT 24 |
| Finished | Jul 30 08:35:37 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-d40d00d7-4832-458c-b74c-a9fab8928b21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386044537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device. 386044537 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.894547078 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 1134983768 ps |
| CPU time | 46.29 seconds |
| Started | Jul 30 08:35:21 PM PDT 24 |
| Finished | Jul 30 08:36:07 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-a121a932-ba4e-407e-bcb3-a2b1cc3919fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894547078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr .894547078 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.3345413785 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 138374136 ps |
| CPU time | 13.98 seconds |
| Started | Jul 30 08:35:23 PM PDT 24 |
| Finished | Jul 30 08:35:37 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-ccae8119-b34b-4b97-a72a-647b2d9d9afc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345413785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3345413785 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.2246896681 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 39452154 ps |
| CPU time | 7.16 seconds |
| Started | Jul 30 08:35:19 PM PDT 24 |
| Finished | Jul 30 08:35:26 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-86f876a9-2a16-4168-8ed9-ec22c6b19ea9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246896681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.2246896681 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.2886198629 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 99741956528 ps |
| CPU time | 1075.82 seconds |
| Started | Jul 30 08:35:18 PM PDT 24 |
| Finished | Jul 30 08:53:14 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-4b6e2921-4e26-4ff3-90df-5566781f05c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886198629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2886198629 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.2858251308 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 62283006627 ps |
| CPU time | 1137.55 seconds |
| Started | Jul 30 08:35:18 PM PDT 24 |
| Finished | Jul 30 08:54:16 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-1f1cbd73-6bba-4307-bd00-e14a96264f74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858251308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2858251308 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.2804190046 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 461147020 ps |
| CPU time | 41.36 seconds |
| Started | Jul 30 08:35:19 PM PDT 24 |
| Finished | Jul 30 08:36:01 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-e1c0ac8e-2679-4be3-9e18-e81951312742 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804190046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.2804190046 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.315408596 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 2448374619 ps |
| CPU time | 87.06 seconds |
| Started | Jul 30 08:35:22 PM PDT 24 |
| Finished | Jul 30 08:36:49 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-d5b6c040-6ea4-421b-a6c5-a174aa43ca5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315408596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.315408596 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.183062632 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 203653923 ps |
| CPU time | 9.59 seconds |
| Started | Jul 30 08:35:18 PM PDT 24 |
| Finished | Jul 30 08:35:27 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-d90d154f-61ab-4f07-b929-873e9e2535f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183062632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.183062632 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.616595449 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 6771624684 ps |
| CPU time | 74.28 seconds |
| Started | Jul 30 08:35:17 PM PDT 24 |
| Finished | Jul 30 08:36:31 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-9d18f55d-c220-405c-b465-85bb97b75435 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616595449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.616595449 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.2803946920 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 3783354022 ps |
| CPU time | 68.16 seconds |
| Started | Jul 30 08:35:17 PM PDT 24 |
| Finished | Jul 30 08:36:25 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-d22ea55f-d141-438b-9734-c7c560255ed6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803946920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2803946920 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.890942371 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 45766407 ps |
| CPU time | 6.79 seconds |
| Started | Jul 30 08:35:14 PM PDT 24 |
| Finished | Jul 30 08:35:21 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-04bcebd3-2fb1-4323-8ba2-1dab1c63ee3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890942371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays .890942371 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.3655370742 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 6800770 ps |
| CPU time | 3.69 seconds |
| Started | Jul 30 08:35:21 PM PDT 24 |
| Finished | Jul 30 08:35:24 PM PDT 24 |
| Peak memory | 566180 kb |
| Host | smart-a74740d2-c9e5-4cb0-a73a-93653bb3b67b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655370742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3655370742 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.4059139029 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 785039576 ps |
| CPU time | 67.2 seconds |
| Started | Jul 30 08:35:24 PM PDT 24 |
| Finished | Jul 30 08:36:32 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-d114b923-e5cb-4139-a576-f7ce12176410 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059139029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.4059139029 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.584676226 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 10903393752 ps |
| CPU time | 1129.89 seconds |
| Started | Jul 30 08:35:22 PM PDT 24 |
| Finished | Jul 30 08:54:12 PM PDT 24 |
| Peak memory | 577872 kb |
| Host | smart-8d778d71-4552-4b03-9663-177d3db2a6ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584676226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_ with_rand_reset.584676226 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.226953398 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 144838781 ps |
| CPU time | 16.85 seconds |
| Started | Jul 30 08:35:20 PM PDT 24 |
| Finished | Jul 30 08:35:37 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-bc112c95-3141-4eb7-9702-1db8c33b4d3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226953398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.226953398 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.1028472700 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 3386974534 ps |
| CPU time | 165.33 seconds |
| Started | Jul 30 08:35:28 PM PDT 24 |
| Finished | Jul 30 08:38:14 PM PDT 24 |
| Peak memory | 598680 kb |
| Host | smart-332deb5a-f95c-44d3-b98e-82d79eda5539 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028472700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.1028472700 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.2576753938 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 571499657 ps |
| CPU time | 43.58 seconds |
| Started | Jul 30 08:35:30 PM PDT 24 |
| Finished | Jul 30 08:36:14 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-44d5e5bd-d271-4e17-a40e-c3f3a8ab2b30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576753938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .2576753938 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.2581195687 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 10035157727 ps |
| CPU time | 186.32 seconds |
| Started | Jul 30 08:35:30 PM PDT 24 |
| Finished | Jul 30 08:38:36 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-1391d8f0-7e1d-4715-bd13-f12ceec34bc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581195687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.2581195687 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.2300513027 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 252960974 ps |
| CPU time | 29.47 seconds |
| Started | Jul 30 08:35:34 PM PDT 24 |
| Finished | Jul 30 08:36:04 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-660604d1-63a0-4b01-ae2f-fb7ae05054ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300513027 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.2300513027 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.1031303890 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 1885425212 ps |
| CPU time | 72.19 seconds |
| Started | Jul 30 08:35:34 PM PDT 24 |
| Finished | Jul 30 08:36:46 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-a5c66a19-4544-424a-8afa-21e1b7f5b080 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031303890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1031303890 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.3827142689 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 1967683122 ps |
| CPU time | 82.1 seconds |
| Started | Jul 30 08:35:25 PM PDT 24 |
| Finished | Jul 30 08:36:47 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-cad3c018-4d01-4d68-8c07-9ab61e514c77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827142689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.3827142689 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.2300202022 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 59539080532 ps |
| CPU time | 643.06 seconds |
| Started | Jul 30 08:35:31 PM PDT 24 |
| Finished | Jul 30 08:46:15 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-4faaffe2-f20f-49dd-9cde-9a0e24ce62d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300202022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2300202022 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.2192680790 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 29416221121 ps |
| CPU time | 516.12 seconds |
| Started | Jul 30 08:35:30 PM PDT 24 |
| Finished | Jul 30 08:44:06 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-4161f7db-c24f-4a94-a820-8d3b45a7ec2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192680790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2192680790 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.3045838884 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 308986648 ps |
| CPU time | 34.75 seconds |
| Started | Jul 30 08:35:26 PM PDT 24 |
| Finished | Jul 30 08:36:01 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-8f7402b1-df3b-48d1-93ba-3bd95f7f974f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045838884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.3045838884 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.1593354428 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 273225586 ps |
| CPU time | 22.75 seconds |
| Started | Jul 30 08:35:33 PM PDT 24 |
| Finished | Jul 30 08:35:55 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-b3e2a191-5438-4c9f-894b-3f25d70d990d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593354428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1593354428 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.3600921455 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 173551225 ps |
| CPU time | 8.28 seconds |
| Started | Jul 30 08:35:28 PM PDT 24 |
| Finished | Jul 30 08:35:36 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-679aefc5-e383-4677-ae1f-ac17e01beb02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600921455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3600921455 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.3612781304 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 9520762134 ps |
| CPU time | 107.43 seconds |
| Started | Jul 30 08:35:27 PM PDT 24 |
| Finished | Jul 30 08:37:15 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-2cd4246a-21a9-4685-80db-4961f136f806 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612781304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3612781304 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.761748692 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 5278168298 ps |
| CPU time | 93.26 seconds |
| Started | Jul 30 08:35:25 PM PDT 24 |
| Finished | Jul 30 08:36:59 PM PDT 24 |
| Peak memory | 573960 kb |
| Host | smart-1c9a6f11-57b1-408d-9b3b-14ee1b0bd18c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761748692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.761748692 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.2476411181 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 43358689 ps |
| CPU time | 6.95 seconds |
| Started | Jul 30 08:35:27 PM PDT 24 |
| Finished | Jul 30 08:35:34 PM PDT 24 |
| Peak memory | 573844 kb |
| Host | smart-31e29a58-6a9a-4816-a9bf-25cb253d8421 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476411181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delay s.2476411181 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.228645756 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 13486045189 ps |
| CPU time | 536.72 seconds |
| Started | Jul 30 08:35:37 PM PDT 24 |
| Finished | Jul 30 08:44:34 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-d26ce673-1b8d-4dfa-8b3d-6785564a3653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228645756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.228645756 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.1314881731 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 11948468124 ps |
| CPU time | 406.05 seconds |
| Started | Jul 30 08:35:41 PM PDT 24 |
| Finished | Jul 30 08:42:27 PM PDT 24 |
| Peak memory | 576820 kb |
| Host | smart-53d19a92-ce59-4f51-913e-ad5641fdcc70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314881731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1314881731 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.3334668619 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 2173381532 ps |
| CPU time | 249.55 seconds |
| Started | Jul 30 08:35:41 PM PDT 24 |
| Finished | Jul 30 08:39:51 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-4a654dc6-19b5-47ae-bc70-7ba73c5d465f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334668619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.3334668619 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.1999044793 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 1735163281 ps |
| CPU time | 216.29 seconds |
| Started | Jul 30 08:35:38 PM PDT 24 |
| Finished | Jul 30 08:39:15 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-2deb85c7-c227-4db4-aa39-0663b266085f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999044793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al l_with_reset_error.1999044793 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.2258047481 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 627957944 ps |
| CPU time | 29.29 seconds |
| Started | Jul 30 08:35:34 PM PDT 24 |
| Finished | Jul 30 08:36:03 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-1faa1ba9-9242-406d-88fb-a6e97bd616a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258047481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2258047481 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.224380986 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3820894432 ps |
| CPU time | 438.89 seconds |
| Started | Jul 30 08:35:45 PM PDT 24 |
| Finished | Jul 30 08:43:04 PM PDT 24 |
| Peak memory | 598612 kb |
| Host | smart-85e07431-969d-4138-8f0c-62ad622f04cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224380986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.224380986 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.2016710536 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 2426301090 ps |
| CPU time | 90.46 seconds |
| Started | Jul 30 08:35:52 PM PDT 24 |
| Finished | Jul 30 08:37:23 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-4439946e-8493-467f-94aa-884bae559fc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016710536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .2016710536 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.655578444 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 34280199258 ps |
| CPU time | 628.94 seconds |
| Started | Jul 30 08:35:57 PM PDT 24 |
| Finished | Jul 30 08:46:26 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-2b052cd0-0c64-4085-8118-46a48990c697 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655578444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_d evice_slow_rsp.655578444 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.2343939361 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 432175298 ps |
| CPU time | 21.54 seconds |
| Started | Jul 30 08:36:02 PM PDT 24 |
| Finished | Jul 30 08:36:23 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-ea410c11-ca7b-4132-8c74-d34b8b15bd2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343939361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.2343939361 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.542931493 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 1322630495 ps |
| CPU time | 51.03 seconds |
| Started | Jul 30 08:35:56 PM PDT 24 |
| Finished | Jul 30 08:36:47 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-177b6918-ff39-4d38-96e6-da0905cb301d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542931493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.542931493 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.3659115782 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 422774714 ps |
| CPU time | 20.05 seconds |
| Started | Jul 30 08:35:51 PM PDT 24 |
| Finished | Jul 30 08:36:11 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-7a635b5c-adb4-4851-98b7-b79402979afe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659115782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.3659115782 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.2311321160 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 12764933702 ps |
| CPU time | 131.99 seconds |
| Started | Jul 30 08:35:48 PM PDT 24 |
| Finished | Jul 30 08:38:00 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-cccaf527-43b6-49ef-8adc-af76bfa801b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311321160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2311321160 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.3912386713 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 46018878373 ps |
| CPU time | 782.89 seconds |
| Started | Jul 30 08:35:53 PM PDT 24 |
| Finished | Jul 30 08:48:56 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-84c13c8d-2e47-48fe-b757-4900a5aad910 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912386713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3912386713 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.127012618 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 256387102 ps |
| CPU time | 26.26 seconds |
| Started | Jul 30 08:35:49 PM PDT 24 |
| Finished | Jul 30 08:36:16 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-aeb299cc-a4bd-4850-aaab-68f66a241f0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127012618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_dela ys.127012618 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.611347696 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 492511474 ps |
| CPU time | 19.38 seconds |
| Started | Jul 30 08:36:02 PM PDT 24 |
| Finished | Jul 30 08:36:21 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-7438898a-ddba-4a4b-b5be-cb6900585b73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611347696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.611347696 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.387049050 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 191366591 ps |
| CPU time | 9.72 seconds |
| Started | Jul 30 08:35:46 PM PDT 24 |
| Finished | Jul 30 08:35:56 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-785b57db-56ec-4ba6-a899-18a585b3b594 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387049050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.387049050 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.1305957210 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 9787055139 ps |
| CPU time | 101.84 seconds |
| Started | Jul 30 08:35:45 PM PDT 24 |
| Finished | Jul 30 08:37:27 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-27a621ba-a0b2-43ec-a1f0-3efbb5cd38c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305957210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1305957210 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.2410291495 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 6149807841 ps |
| CPU time | 108.98 seconds |
| Started | Jul 30 08:35:53 PM PDT 24 |
| Finished | Jul 30 08:37:42 PM PDT 24 |
| Peak memory | 573964 kb |
| Host | smart-bf46e96b-82cb-48a9-8be7-61bf77417367 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410291495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2410291495 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.2008572114 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 54777047 ps |
| CPU time | 7.47 seconds |
| Started | Jul 30 08:35:45 PM PDT 24 |
| Finished | Jul 30 08:35:53 PM PDT 24 |
| Peak memory | 573848 kb |
| Host | smart-7059fb2b-0d0e-49a5-9bb3-e67a2b03927f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008572114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.2008572114 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.3953877347 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 2469091105 ps |
| CPU time | 92.53 seconds |
| Started | Jul 30 08:36:01 PM PDT 24 |
| Finished | Jul 30 08:37:33 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-85d8d236-bbe0-4fdf-9f24-4291f716dea0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953877347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3953877347 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.2828299119 |
| Short name | T2922 |
| Test name | |
| Test status | |
| Simulation time | 13207051516 ps |
| CPU time | 451.81 seconds |
| Started | Jul 30 08:36:05 PM PDT 24 |
| Finished | Jul 30 08:43:37 PM PDT 24 |
| Peak memory | 576820 kb |
| Host | smart-df337766-54ce-4f98-a146-327901bb92c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828299119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2828299119 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.4293964007 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 112516667 ps |
| CPU time | 73.75 seconds |
| Started | Jul 30 08:35:58 PM PDT 24 |
| Finished | Jul 30 08:37:12 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-6da7ab9e-5335-4e4a-bc64-d805a1613c64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293964007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.4293964007 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.988854515 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 169696306 ps |
| CPU time | 40.44 seconds |
| Started | Jul 30 08:36:02 PM PDT 24 |
| Finished | Jul 30 08:36:42 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-a0e39e34-f963-492e-8e81-6ce24da512ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988854515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_reset_error.988854515 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.806271267 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 1034850697 ps |
| CPU time | 47.38 seconds |
| Started | Jul 30 08:35:56 PM PDT 24 |
| Finished | Jul 30 08:36:43 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-e43162b6-1dc0-4da1-854e-a994e156f8fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806271267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.806271267 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.325806950 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 2983969550 ps |
| CPU time | 138.21 seconds |
| Started | Jul 30 08:36:04 PM PDT 24 |
| Finished | Jul 30 08:38:23 PM PDT 24 |
| Peak memory | 603632 kb |
| Host | smart-00066ac6-7272-473b-9e15-a978286a67b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325806950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.325806950 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.17875631 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 3812612473 ps |
| CPU time | 156.34 seconds |
| Started | Jul 30 08:36:10 PM PDT 24 |
| Finished | Jul 30 08:38:46 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-d189dc4a-ab19-40ca-ab59-ff2241e3c2a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17875631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.17875631 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.3062642899 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 63617833915 ps |
| CPU time | 1124.78 seconds |
| Started | Jul 30 08:36:08 PM PDT 24 |
| Finished | Jul 30 08:54:53 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-727cdbfa-08cf-42f8-a17b-c92095abee74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062642899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.3062642899 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.2864950211 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 1406188159 ps |
| CPU time | 55.79 seconds |
| Started | Jul 30 08:36:08 PM PDT 24 |
| Finished | Jul 30 08:37:04 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-bda6c12a-a931-4693-a7e7-1ef0fb2e49b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864950211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.2864950211 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.2261865914 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 690893039 ps |
| CPU time | 27.21 seconds |
| Started | Jul 30 08:36:07 PM PDT 24 |
| Finished | Jul 30 08:36:34 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-d2af5a24-6653-4d21-ac92-8e2f1055cdf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261865914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2261865914 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.1465726887 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 1041506998 ps |
| CPU time | 39.35 seconds |
| Started | Jul 30 08:36:03 PM PDT 24 |
| Finished | Jul 30 08:36:42 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-6457a56b-7ff3-496b-b273-384ace013b47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465726887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.1465726887 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.1998099157 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 88801263209 ps |
| CPU time | 957.17 seconds |
| Started | Jul 30 08:36:05 PM PDT 24 |
| Finished | Jul 30 08:52:03 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-867af6f7-f6dc-4b6c-b062-a1d044535c89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998099157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1998099157 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.2501988142 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 46494025454 ps |
| CPU time | 831.06 seconds |
| Started | Jul 30 08:36:03 PM PDT 24 |
| Finished | Jul 30 08:49:54 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-688a2c3a-8038-40aa-8206-25d5464b38e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501988142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2501988142 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.4032687892 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 217051162 ps |
| CPU time | 23.53 seconds |
| Started | Jul 30 08:36:04 PM PDT 24 |
| Finished | Jul 30 08:36:28 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-8cba7f23-4e28-490b-a166-cabe9dd43a20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032687892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.4032687892 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.1936506201 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 2229951376 ps |
| CPU time | 80.33 seconds |
| Started | Jul 30 08:36:08 PM PDT 24 |
| Finished | Jul 30 08:37:29 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-be24cf2a-ca1d-42f0-ab4f-16ef270db9e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936506201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1936506201 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.1789616123 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 188121260 ps |
| CPU time | 10.04 seconds |
| Started | Jul 30 08:36:01 PM PDT 24 |
| Finished | Jul 30 08:36:11 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-e620f7f7-b03f-4f4b-9e6a-b5998bd27971 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789616123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1789616123 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.2861778781 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 6138641681 ps |
| CPU time | 64.07 seconds |
| Started | Jul 30 08:36:04 PM PDT 24 |
| Finished | Jul 30 08:37:08 PM PDT 24 |
| Peak memory | 573924 kb |
| Host | smart-f7eadf4c-067f-4139-b495-3cd9c0ebc9e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861778781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2861778781 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.341878178 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 5990715560 ps |
| CPU time | 106.48 seconds |
| Started | Jul 30 08:36:03 PM PDT 24 |
| Finished | Jul 30 08:37:49 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-02002f45-bfa3-4824-8ca0-f2300be57ec0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341878178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.341878178 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.3881140648 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 40759509 ps |
| CPU time | 6.39 seconds |
| Started | Jul 30 08:36:05 PM PDT 24 |
| Finished | Jul 30 08:36:12 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-d78db2df-9cca-4f3b-ba0e-794ad208f743 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881140648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.3881140648 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.1344018225 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 785979818 ps |
| CPU time | 26.46 seconds |
| Started | Jul 30 08:36:07 PM PDT 24 |
| Finished | Jul 30 08:36:33 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-eb09e3c3-db12-471e-b428-6791986bd3d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344018225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1344018225 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.3521882543 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 5978244 ps |
| CPU time | 3.84 seconds |
| Started | Jul 30 08:36:15 PM PDT 24 |
| Finished | Jul 30 08:36:19 PM PDT 24 |
| Peak memory | 566152 kb |
| Host | smart-3f2c3653-9298-42c2-b888-61714a18615d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521882543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3521882543 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2715419252 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 677577872 ps |
| CPU time | 306.72 seconds |
| Started | Jul 30 08:36:12 PM PDT 24 |
| Finished | Jul 30 08:41:19 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-e2b9126d-c37b-4525-ab01-853e89f3a5dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715419252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.2715419252 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.290006947 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 28451078 ps |
| CPU time | 28.3 seconds |
| Started | Jul 30 08:36:12 PM PDT 24 |
| Finished | Jul 30 08:36:41 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-b5be5dce-8ce5-45a4-9b35-2c86bea5b138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290006947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_reset_error.290006947 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.2668635575 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 177091030 ps |
| CPU time | 10.82 seconds |
| Started | Jul 30 08:36:06 PM PDT 24 |
| Finished | Jul 30 08:36:17 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-4d9b7abf-647f-41c0-9843-4a77d0a2b238 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668635575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2668635575 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.1753630292 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 555398709 ps |
| CPU time | 52.95 seconds |
| Started | Jul 30 08:36:26 PM PDT 24 |
| Finished | Jul 30 08:37:19 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-c4c4083d-1d6e-4f25-8cce-495fb350799e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753630292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .1753630292 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.1586609887 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 232191166 ps |
| CPU time | 29.46 seconds |
| Started | Jul 30 08:36:23 PM PDT 24 |
| Finished | Jul 30 08:36:53 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-6ff3fb73-e0e0-4488-b384-e09fcb866e6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586609887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.1586609887 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.3508671696 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 395136608 ps |
| CPU time | 36.73 seconds |
| Started | Jul 30 08:36:20 PM PDT 24 |
| Finished | Jul 30 08:36:57 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-6c92458c-8b28-4d6b-9465-222ac6e78501 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508671696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3508671696 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.1215721724 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 160927813 ps |
| CPU time | 19.86 seconds |
| Started | Jul 30 08:36:14 PM PDT 24 |
| Finished | Jul 30 08:36:34 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-4d604675-e9f4-4803-8123-f6e3028e6436 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215721724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.1215721724 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.3934173200 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 66865268929 ps |
| CPU time | 696.86 seconds |
| Started | Jul 30 08:36:18 PM PDT 24 |
| Finished | Jul 30 08:47:55 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-707dfdc5-767d-4aa9-8829-a6c56e1e1bb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934173200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3934173200 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.1816525659 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 13874085755 ps |
| CPU time | 237.19 seconds |
| Started | Jul 30 08:36:17 PM PDT 24 |
| Finished | Jul 30 08:40:14 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-2f8349ef-3218-4d32-8584-15d1ac485f99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816525659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1816525659 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.1238917057 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 251082929 ps |
| CPU time | 24.62 seconds |
| Started | Jul 30 08:36:20 PM PDT 24 |
| Finished | Jul 30 08:36:45 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-e0a33354-d101-4aad-b44b-654e74d88a8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238917057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.1238917057 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.2130213427 |
| Short name | T2928 |
| Test name | |
| Test status | |
| Simulation time | 1045209762 ps |
| CPU time | 32.24 seconds |
| Started | Jul 30 08:36:29 PM PDT 24 |
| Finished | Jul 30 08:37:02 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-5220f66b-14be-4687-8bcf-cf5654e7184c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130213427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2130213427 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.2357392293 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 40944002 ps |
| CPU time | 6.79 seconds |
| Started | Jul 30 08:36:12 PM PDT 24 |
| Finished | Jul 30 08:36:19 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-c3ba6261-d87b-4669-bc38-3bcf49afd6a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357392293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2357392293 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.1581330591 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 8515096519 ps |
| CPU time | 97.62 seconds |
| Started | Jul 30 08:36:16 PM PDT 24 |
| Finished | Jul 30 08:37:54 PM PDT 24 |
| Peak memory | 573968 kb |
| Host | smart-a2bca630-4498-4f37-b8fa-cc3bc7a58580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581330591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1581330591 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.4269915991 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 4878869068 ps |
| CPU time | 84.1 seconds |
| Started | Jul 30 08:36:30 PM PDT 24 |
| Finished | Jul 30 08:37:54 PM PDT 24 |
| Peak memory | 573968 kb |
| Host | smart-2fedca45-64a7-41bd-a1a9-06d1403e93ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269915991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.4269915991 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.2609165657 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 44859749 ps |
| CPU time | 6.11 seconds |
| Started | Jul 30 08:36:11 PM PDT 24 |
| Finished | Jul 30 08:36:17 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-70b9faa5-c45a-4549-b21f-ea59f51b0f59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609165657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.2609165657 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.3419919222 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 5175394574 ps |
| CPU time | 191.56 seconds |
| Started | Jul 30 08:36:25 PM PDT 24 |
| Finished | Jul 30 08:39:37 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-52946c13-b21e-47de-9d93-6575b54ff9d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419919222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3419919222 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.621359055 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 4269510351 ps |
| CPU time | 336.68 seconds |
| Started | Jul 30 08:36:28 PM PDT 24 |
| Finished | Jul 30 08:42:05 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-38055934-7faa-44cd-b4f2-02227767c0ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621359055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.621359055 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.2780578144 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 1867886971 ps |
| CPU time | 271.82 seconds |
| Started | Jul 30 08:36:24 PM PDT 24 |
| Finished | Jul 30 08:40:56 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-3c727f1d-9dee-4c13-85c3-28243b3013a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780578144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.2780578144 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.1590370421 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 10514134491 ps |
| CPU time | 489.25 seconds |
| Started | Jul 30 08:36:24 PM PDT 24 |
| Finished | Jul 30 08:44:33 PM PDT 24 |
| Peak memory | 576864 kb |
| Host | smart-dcbdd09e-b1bc-4e4e-ae8e-2b08af904a04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590370421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.1590370421 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.2725919125 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 151176832 ps |
| CPU time | 18.79 seconds |
| Started | Jul 30 08:36:25 PM PDT 24 |
| Finished | Jul 30 08:36:44 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-9049ad1d-ede6-4d23-acff-d9bb503f3a1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725919125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2725919125 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.474308974 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 3840915936 ps |
| CPU time | 192.82 seconds |
| Started | Jul 30 08:36:26 PM PDT 24 |
| Finished | Jul 30 08:39:39 PM PDT 24 |
| Peak memory | 598712 kb |
| Host | smart-87af0e42-2c2b-4d8b-8875-7f155f2b8f99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474308974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.474308974 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.1745404663 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 630343255 ps |
| CPU time | 46.47 seconds |
| Started | Jul 30 08:36:28 PM PDT 24 |
| Finished | Jul 30 08:37:15 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-f52b43a2-0ee5-462c-81bc-4d8f66813f05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745404663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .1745404663 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.1631221247 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 29926963425 ps |
| CPU time | 544.11 seconds |
| Started | Jul 30 08:36:44 PM PDT 24 |
| Finished | Jul 30 08:45:48 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-d9fdc04f-6350-424a-b164-ea85a3096659 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631221247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.1631221247 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.1640291203 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 321795315 ps |
| CPU time | 39.62 seconds |
| Started | Jul 30 08:36:37 PM PDT 24 |
| Finished | Jul 30 08:37:17 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-6cd70a8a-fb92-4e83-add9-74a66ad9cc68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640291203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.1640291203 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.886585412 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 281390663 ps |
| CPU time | 24.72 seconds |
| Started | Jul 30 08:36:37 PM PDT 24 |
| Finished | Jul 30 08:37:01 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-4faa24eb-4d81-4c8f-bce9-2d734758e4cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886585412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.886585412 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.3275696593 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 324819585 ps |
| CPU time | 16.76 seconds |
| Started | Jul 30 08:36:30 PM PDT 24 |
| Finished | Jul 30 08:36:47 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-3c5a8f49-c147-459b-8421-7251aa3317ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275696593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.3275696593 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.63356853 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 14487204540 ps |
| CPU time | 158.9 seconds |
| Started | Jul 30 08:36:30 PM PDT 24 |
| Finished | Jul 30 08:39:09 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-59f2c08a-55fd-4ce1-b0a8-6056f2f2c53b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63356853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.63356853 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.3081553388 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 35230578877 ps |
| CPU time | 629.48 seconds |
| Started | Jul 30 08:36:31 PM PDT 24 |
| Finished | Jul 30 08:47:00 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-8ccbb8a0-98c3-4816-a381-652fcbb7ff9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081553388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3081553388 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.803163384 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 97029530 ps |
| CPU time | 11.73 seconds |
| Started | Jul 30 08:36:30 PM PDT 24 |
| Finished | Jul 30 08:36:42 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-bb9ce371-8d0c-46dd-a560-e02f0ffb90ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803163384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_dela ys.803163384 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.2747662415 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 1378856899 ps |
| CPU time | 46.1 seconds |
| Started | Jul 30 08:36:37 PM PDT 24 |
| Finished | Jul 30 08:37:24 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-72593baa-a269-43af-bb67-0e67f0e0e90d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747662415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2747662415 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.473498678 |
| Short name | T2919 |
| Test name | |
| Test status | |
| Simulation time | 190453462 ps |
| CPU time | 8.58 seconds |
| Started | Jul 30 08:36:27 PM PDT 24 |
| Finished | Jul 30 08:36:35 PM PDT 24 |
| Peak memory | 573876 kb |
| Host | smart-25fb2470-d549-45ae-99e7-5f9e17823cef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473498678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.473498678 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.2532898290 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 7035300370 ps |
| CPU time | 75.05 seconds |
| Started | Jul 30 08:36:27 PM PDT 24 |
| Finished | Jul 30 08:37:42 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-2db7467b-ce96-4836-ac89-40d6861d23f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532898290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2532898290 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3141578898 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 5721143969 ps |
| CPU time | 102.28 seconds |
| Started | Jul 30 08:36:30 PM PDT 24 |
| Finished | Jul 30 08:38:12 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-a51b0660-9f67-4117-9dbe-ff34e718932b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141578898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3141578898 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1507848952 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 42807942 ps |
| CPU time | 6.01 seconds |
| Started | Jul 30 08:36:29 PM PDT 24 |
| Finished | Jul 30 08:36:35 PM PDT 24 |
| Peak memory | 573864 kb |
| Host | smart-7c244c31-4328-4620-a55b-62a327a71257 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507848952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.1507848952 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.1910739381 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 2352660318 ps |
| CPU time | 193.64 seconds |
| Started | Jul 30 08:36:42 PM PDT 24 |
| Finished | Jul 30 08:39:55 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-d1f7efbb-74ae-4d8b-8bc7-5827d7169001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910739381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1910739381 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.1312377153 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 3333837721 ps |
| CPU time | 124.16 seconds |
| Started | Jul 30 08:36:40 PM PDT 24 |
| Finished | Jul 30 08:38:44 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-065aa221-0d41-422b-908c-38204b54844c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312377153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1312377153 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.3449013563 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 653191925 ps |
| CPU time | 420.19 seconds |
| Started | Jul 30 08:36:36 PM PDT 24 |
| Finished | Jul 30 08:43:36 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-ecf7900e-69cf-41a3-b758-5d5cb48b6902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449013563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.3449013563 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.166544352 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 13111711400 ps |
| CPU time | 451.04 seconds |
| Started | Jul 30 08:36:37 PM PDT 24 |
| Finished | Jul 30 08:44:08 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-61eb2bbb-2e67-4618-b15e-f8f393536525 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166544352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_reset_error.166544352 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.3876199616 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 152193739 ps |
| CPU time | 21.35 seconds |
| Started | Jul 30 08:36:37 PM PDT 24 |
| Finished | Jul 30 08:36:59 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-867d7169-6631-4c1c-874d-e957dcf35e1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876199616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3876199616 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.1660040440 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 3484684670 ps |
| CPU time | 221.83 seconds |
| Started | Jul 30 08:36:44 PM PDT 24 |
| Finished | Jul 30 08:40:26 PM PDT 24 |
| Peak memory | 598708 kb |
| Host | smart-e9e26d7c-67e2-469d-ae88-b12175842c91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660040440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.1660040440 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.2648296599 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 711617970 ps |
| CPU time | 75 seconds |
| Started | Jul 30 08:36:42 PM PDT 24 |
| Finished | Jul 30 08:37:57 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-1a3a1ac7-b771-4517-aada-efb0fbde52a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648296599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .2648296599 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.985625424 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 52786827015 ps |
| CPU time | 953.5 seconds |
| Started | Jul 30 08:36:47 PM PDT 24 |
| Finished | Jul 30 08:52:41 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-28cfe181-0317-4185-a4c4-c4520a961e12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985625424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_d evice_slow_rsp.985625424 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2899164437 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 439387186 ps |
| CPU time | 22.42 seconds |
| Started | Jul 30 08:36:48 PM PDT 24 |
| Finished | Jul 30 08:37:10 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-4343711f-0d47-4740-8db5-0086d3236c01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899164437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.2899164437 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.2179037019 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 321303750 ps |
| CPU time | 27.48 seconds |
| Started | Jul 30 08:36:50 PM PDT 24 |
| Finished | Jul 30 08:37:18 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-f381695d-3d4c-4718-a3df-e501efdec748 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179037019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2179037019 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.4091154740 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 1106544551 ps |
| CPU time | 44.39 seconds |
| Started | Jul 30 08:36:44 PM PDT 24 |
| Finished | Jul 30 08:37:28 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-701666d4-9d61-4484-b813-58a3893ee5ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091154740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.4091154740 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.3060107874 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 91126556161 ps |
| CPU time | 942.65 seconds |
| Started | Jul 30 08:36:43 PM PDT 24 |
| Finished | Jul 30 08:52:25 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-463f2e60-4870-4997-ac74-28073149a797 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060107874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3060107874 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.3064106929 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 53120002035 ps |
| CPU time | 935.39 seconds |
| Started | Jul 30 08:36:46 PM PDT 24 |
| Finished | Jul 30 08:52:21 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-dd5326d5-2287-49dc-a08f-d4f2b166be7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064106929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3064106929 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.2341220416 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 282218747 ps |
| CPU time | 29.31 seconds |
| Started | Jul 30 08:36:45 PM PDT 24 |
| Finished | Jul 30 08:37:14 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-95bd7b96-5a70-4de7-92b1-53e7be15ddd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341220416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.2341220416 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.3307546614 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 494205490 ps |
| CPU time | 18.12 seconds |
| Started | Jul 30 08:36:49 PM PDT 24 |
| Finished | Jul 30 08:37:07 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-018baf22-3acb-4e0d-881f-d5c483395a23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307546614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3307546614 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.2032607440 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 175251826 ps |
| CPU time | 8.47 seconds |
| Started | Jul 30 08:36:37 PM PDT 24 |
| Finished | Jul 30 08:36:46 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-cf89072f-d655-44bd-b1b4-d91350ba63ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032607440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2032607440 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.856473147 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 7617634311 ps |
| CPU time | 85.42 seconds |
| Started | Jul 30 08:36:43 PM PDT 24 |
| Finished | Jul 30 08:38:09 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-663a6452-afc6-43ec-a596-a61438969b17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856473147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.856473147 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.1504323397 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 5101283782 ps |
| CPU time | 91.87 seconds |
| Started | Jul 30 08:36:40 PM PDT 24 |
| Finished | Jul 30 08:38:11 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-a5d604c2-1123-4761-85e2-edec52cb72d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504323397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1504323397 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.2645449558 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 46815769 ps |
| CPU time | 6.76 seconds |
| Started | Jul 30 08:36:44 PM PDT 24 |
| Finished | Jul 30 08:36:51 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-626255ec-1de4-41a7-b4e4-7f842b9326a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645449558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.2645449558 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.4056301363 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 1814055712 ps |
| CPU time | 186.2 seconds |
| Started | Jul 30 08:37:00 PM PDT 24 |
| Finished | Jul 30 08:40:07 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-45d8bac3-a8b9-4efb-824d-1bf7e4c1f31e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056301363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.4056301363 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.1783755576 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 1703793832 ps |
| CPU time | 112.11 seconds |
| Started | Jul 30 08:36:53 PM PDT 24 |
| Finished | Jul 30 08:38:45 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-755a2b42-42ab-4fff-bcaf-ebb50de0fdbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783755576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1783755576 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2066208401 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 9667372525 ps |
| CPU time | 425.33 seconds |
| Started | Jul 30 08:37:02 PM PDT 24 |
| Finished | Jul 30 08:44:07 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-743c041b-0d83-41bf-a4b9-83d21b1f938a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066208401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.2066208401 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.3203997329 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 652831061 ps |
| CPU time | 219.04 seconds |
| Started | Jul 30 08:36:53 PM PDT 24 |
| Finished | Jul 30 08:40:33 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-ecdeee09-528a-4508-b347-c7ea5cd1f5f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203997329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.3203997329 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.2457761798 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 1346699271 ps |
| CPU time | 60.42 seconds |
| Started | Jul 30 08:36:49 PM PDT 24 |
| Finished | Jul 30 08:37:49 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-d01638e9-0434-44c9-b29e-175cd5deb86d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457761798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2457761798 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.292690721 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 28925727110 ps |
| CPU time | 4624.59 seconds |
| Started | Jul 30 08:27:32 PM PDT 24 |
| Finished | Jul 30 09:44:37 PM PDT 24 |
| Peak memory | 594364 kb |
| Host | smart-4b4fa29b-6cec-4336-8cad-63fd381b8a36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292690721 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 3.chip_csr_aliasing.292690721 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.3166842569 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 5519907302 ps |
| CPU time | 639.87 seconds |
| Started | Jul 30 08:27:35 PM PDT 24 |
| Finished | Jul 30 08:38:15 PM PDT 24 |
| Peak memory | 592900 kb |
| Host | smart-d7d367bf-f5dd-4f5a-82d9-b4469d25ce0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166842569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.3166842569 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.2683070734 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 5918110582 ps |
| CPU time | 459 seconds |
| Started | Jul 30 08:28:08 PM PDT 24 |
| Finished | Jul 30 08:35:48 PM PDT 24 |
| Peak memory | 637640 kb |
| Host | smart-4d6e18e0-5c93-4cf1-b554-66d40aec71ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683070734 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.2683070734 |
| Directory | /workspace/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.1160429878 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 3809479052 ps |
| CPU time | 349.68 seconds |
| Started | Jul 30 08:28:06 PM PDT 24 |
| Finished | Jul 30 08:33:56 PM PDT 24 |
| Peak memory | 597368 kb |
| Host | smart-653b76f9-6c24-45b7-b531-20d13320be51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160429878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.1160429878 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1918556835 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 30422701615 ps |
| CPU time | 4637.51 seconds |
| Started | Jul 30 08:27:39 PM PDT 24 |
| Finished | Jul 30 09:44:57 PM PDT 24 |
| Peak memory | 593300 kb |
| Host | smart-2f3eab71-be1d-4355-babc-60529836ba82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918556835 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.1918556835 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.2698428379 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 3224949266 ps |
| CPU time | 205.02 seconds |
| Started | Jul 30 08:27:43 PM PDT 24 |
| Finished | Jul 30 08:31:08 PM PDT 24 |
| Peak memory | 598628 kb |
| Host | smart-77b8d41a-5741-4273-9d2d-7150e7b102c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698428379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.2698428379 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.757290106 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 689788577 ps |
| CPU time | 68.1 seconds |
| Started | Jul 30 08:27:52 PM PDT 24 |
| Finished | Jul 30 08:29:00 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-335113c2-0d12-4c17-9fcd-afcba9c10755 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757290106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.757290106 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3381172103 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 112165086293 ps |
| CPU time | 1965.68 seconds |
| Started | Jul 30 08:27:55 PM PDT 24 |
| Finished | Jul 30 09:00:41 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-ed250574-65ef-4ed7-93a6-ac4e5edbdda0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381172103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.3381172103 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.2172043181 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 253062656 ps |
| CPU time | 30.39 seconds |
| Started | Jul 30 08:27:56 PM PDT 24 |
| Finished | Jul 30 08:28:27 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-25834508-246d-4ca3-9092-cbdb240c58d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172043181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .2172043181 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.544093247 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 415276782 ps |
| CPU time | 36.45 seconds |
| Started | Jul 30 08:27:52 PM PDT 24 |
| Finished | Jul 30 08:28:29 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-7eafad9a-c7ca-460c-8194-1ae39fe48bcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544093247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.544093247 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.4164140035 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 1927174584 ps |
| CPU time | 81.82 seconds |
| Started | Jul 30 08:27:42 PM PDT 24 |
| Finished | Jul 30 08:29:04 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-18fced6d-6836-481b-ada7-a2a41540f2d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164140035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.4164140035 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.3507403136 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 54524996106 ps |
| CPU time | 574.66 seconds |
| Started | Jul 30 08:27:45 PM PDT 24 |
| Finished | Jul 30 08:37:19 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-74d0373c-e989-451b-b007-03721344dc83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507403136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3507403136 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.3725958268 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 60434011098 ps |
| CPU time | 1111.21 seconds |
| Started | Jul 30 08:27:50 PM PDT 24 |
| Finished | Jul 30 08:46:21 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-a5383b59-8238-45b5-bca5-70724e7a5c86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725958268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3725958268 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.33149019 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 422916226 ps |
| CPU time | 38.97 seconds |
| Started | Jul 30 08:27:45 PM PDT 24 |
| Finished | Jul 30 08:28:24 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-5ae61a9f-bb70-4007-a0cc-3226eb668139 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33149019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays .33149019 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.1150265507 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 510867680 ps |
| CPU time | 18.97 seconds |
| Started | Jul 30 08:27:53 PM PDT 24 |
| Finished | Jul 30 08:28:12 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-e449fcab-4db7-4b3a-be01-9d3bb07926dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150265507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1150265507 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.3609895885 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 193463161 ps |
| CPU time | 9.12 seconds |
| Started | Jul 30 08:27:43 PM PDT 24 |
| Finished | Jul 30 08:27:52 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-eb97741f-3daa-42a5-9f7e-da2aec938151 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609895885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3609895885 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.1254369270 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 9137213304 ps |
| CPU time | 104.45 seconds |
| Started | Jul 30 08:27:44 PM PDT 24 |
| Finished | Jul 30 08:29:28 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-4b46407e-cbe5-4398-8ecb-2647b27db8eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254369270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1254369270 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.90478345 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 4782655624 ps |
| CPU time | 82.36 seconds |
| Started | Jul 30 08:27:39 PM PDT 24 |
| Finished | Jul 30 08:29:01 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-3185c89f-a85d-43b9-b769-87a78dc3d3e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90478345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.90478345 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.3675854427 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 43446275 ps |
| CPU time | 6.71 seconds |
| Started | Jul 30 08:27:44 PM PDT 24 |
| Finished | Jul 30 08:27:51 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-055cfcf4-2e79-4ae5-add8-331957855ada |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675854427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .3675854427 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.2410773267 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 1669468326 ps |
| CPU time | 161.47 seconds |
| Started | Jul 30 08:28:07 PM PDT 24 |
| Finished | Jul 30 08:30:48 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-f41b6b30-8ecc-4f01-a2db-00b22184ed68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410773267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2410773267 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.3503355651 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 2685336050 ps |
| CPU time | 97.05 seconds |
| Started | Jul 30 08:28:02 PM PDT 24 |
| Finished | Jul 30 08:29:39 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-9a26bf2a-7c3a-4f27-aef2-73cae65317fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503355651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3503355651 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.1428734101 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 451937574 ps |
| CPU time | 196.69 seconds |
| Started | Jul 30 08:28:02 PM PDT 24 |
| Finished | Jul 30 08:31:18 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-057e9fb3-344e-461c-921c-c2f198088a38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428734101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.1428734101 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.2893480464 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 413796476 ps |
| CPU time | 36.57 seconds |
| Started | Jul 30 08:28:01 PM PDT 24 |
| Finished | Jul 30 08:28:38 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-2d3be6f9-2beb-458e-86de-0d25fec885cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893480464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.2893480464 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.64259462 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 278877539 ps |
| CPU time | 36.97 seconds |
| Started | Jul 30 08:27:54 PM PDT 24 |
| Finished | Jul 30 08:28:31 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-df67edfa-0d74-4c73-9680-c0e31e858848 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64259462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.64259462 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.1014445064 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 2575156592 ps |
| CPU time | 115.48 seconds |
| Started | Jul 30 08:36:58 PM PDT 24 |
| Finished | Jul 30 08:38:54 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-3558249e-b524-47c2-8490-564551575d70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014445064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .1014445064 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2297612752 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 59700239828 ps |
| CPU time | 1013.77 seconds |
| Started | Jul 30 08:36:59 PM PDT 24 |
| Finished | Jul 30 08:53:53 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-bb521876-4639-4901-8025-441e357fb946 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297612752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.2297612752 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.3220754057 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 748423288 ps |
| CPU time | 30.8 seconds |
| Started | Jul 30 08:37:08 PM PDT 24 |
| Finished | Jul 30 08:37:38 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-cf6be467-48dc-4ed9-96d7-aae992e81274 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220754057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.3220754057 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.1982008630 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 763375958 ps |
| CPU time | 27.75 seconds |
| Started | Jul 30 08:37:04 PM PDT 24 |
| Finished | Jul 30 08:37:31 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-a6c4001d-a3af-4537-909a-5e82502de9ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982008630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1982008630 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.2838263786 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 217441134 ps |
| CPU time | 19.62 seconds |
| Started | Jul 30 08:37:01 PM PDT 24 |
| Finished | Jul 30 08:37:20 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-170c67b1-403a-4233-8435-1576e3d6f675 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838263786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.2838263786 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.2430096805 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 99665663631 ps |
| CPU time | 1088.38 seconds |
| Started | Jul 30 08:36:56 PM PDT 24 |
| Finished | Jul 30 08:55:05 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-810f9cca-3d06-4129-b90e-26425545c082 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430096805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2430096805 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.1705730571 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 21039735502 ps |
| CPU time | 368.14 seconds |
| Started | Jul 30 08:36:56 PM PDT 24 |
| Finished | Jul 30 08:43:04 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-febc3c69-f7ac-42b6-bd17-782c62df974b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705730571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1705730571 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.3826662816 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 322485105 ps |
| CPU time | 33.5 seconds |
| Started | Jul 30 08:36:57 PM PDT 24 |
| Finished | Jul 30 08:37:31 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-e7ac6a02-2516-4b6b-9349-5c091c778990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826662816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.3826662816 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.3389875763 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 167070533 ps |
| CPU time | 8.7 seconds |
| Started | Jul 30 08:37:00 PM PDT 24 |
| Finished | Jul 30 08:37:08 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-17515338-35fe-4b63-a5cd-865c2925bdb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389875763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3389875763 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.2031592537 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 50567310 ps |
| CPU time | 7.23 seconds |
| Started | Jul 30 08:37:01 PM PDT 24 |
| Finished | Jul 30 08:37:08 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-52a3c361-94f2-4e78-b93d-4ecbf0dfd845 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031592537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2031592537 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.610998747 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 9743584104 ps |
| CPU time | 111.08 seconds |
| Started | Jul 30 08:37:03 PM PDT 24 |
| Finished | Jul 30 08:38:54 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-fd4ed96c-94c1-450c-af8e-1acf4ba91937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610998747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.610998747 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.1674049253 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 4598417675 ps |
| CPU time | 79.53 seconds |
| Started | Jul 30 08:36:52 PM PDT 24 |
| Finished | Jul 30 08:38:12 PM PDT 24 |
| Peak memory | 573960 kb |
| Host | smart-7ad89f25-5e43-46c6-8f45-e5955cf07b33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674049253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1674049253 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.1630042277 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 46603148 ps |
| CPU time | 6.25 seconds |
| Started | Jul 30 08:36:50 PM PDT 24 |
| Finished | Jul 30 08:36:56 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-1831b180-bd9e-48ab-aee7-142d4d90f003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630042277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.1630042277 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.3535379515 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 3438041873 ps |
| CPU time | 127.32 seconds |
| Started | Jul 30 08:37:05 PM PDT 24 |
| Finished | Jul 30 08:39:12 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-1f288553-b69b-4be2-a3f5-56460c7cda70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535379515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3535379515 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.2127047906 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 101378836 ps |
| CPU time | 40.22 seconds |
| Started | Jul 30 08:37:05 PM PDT 24 |
| Finished | Jul 30 08:37:45 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-d759e713-b34f-434e-8afd-e01ecd7953f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127047906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.2127047906 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1074697546 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 1118232267 ps |
| CPU time | 291.76 seconds |
| Started | Jul 30 08:37:06 PM PDT 24 |
| Finished | Jul 30 08:41:58 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-cccf447c-437f-4b4d-ab29-6824635b84d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074697546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.1074697546 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.4092391320 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 95382430 ps |
| CPU time | 15.57 seconds |
| Started | Jul 30 08:37:02 PM PDT 24 |
| Finished | Jul 30 08:37:18 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-f51a8b89-4c8d-4b1a-994b-9474013fe8e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092391320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.4092391320 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.1821129445 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 1011454107 ps |
| CPU time | 77.4 seconds |
| Started | Jul 30 08:37:07 PM PDT 24 |
| Finished | Jul 30 08:38:24 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-0f1d503c-85c1-4762-9a06-eb28802b3b8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821129445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .1821129445 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.1215911459 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 57165922782 ps |
| CPU time | 1012.43 seconds |
| Started | Jul 30 08:37:11 PM PDT 24 |
| Finished | Jul 30 08:54:04 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-df49ce19-8588-481a-86e0-f0f8c825a66f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215911459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_ device_slow_rsp.1215911459 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3925113651 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 122436936 ps |
| CPU time | 14.84 seconds |
| Started | Jul 30 08:37:10 PM PDT 24 |
| Finished | Jul 30 08:37:25 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-6c4b02a0-31f5-4a27-a19f-4395edc49d59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925113651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.3925113651 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.1554714587 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 2523795399 ps |
| CPU time | 107.29 seconds |
| Started | Jul 30 08:37:14 PM PDT 24 |
| Finished | Jul 30 08:39:01 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-d603de6c-d80f-47b2-80f5-db96df05dc5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554714587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1554714587 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.950107119 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 1180102812 ps |
| CPU time | 53.32 seconds |
| Started | Jul 30 08:37:09 PM PDT 24 |
| Finished | Jul 30 08:38:02 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-35ebdb38-533a-456e-9185-e840081a3037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950107119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.950107119 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.1421406819 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 66318329814 ps |
| CPU time | 742.82 seconds |
| Started | Jul 30 08:37:06 PM PDT 24 |
| Finished | Jul 30 08:49:29 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-f1c9499d-d804-4567-a09d-8d7c9d3bf9cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421406819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1421406819 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.2467407785 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 11889323066 ps |
| CPU time | 216.86 seconds |
| Started | Jul 30 08:37:07 PM PDT 24 |
| Finished | Jul 30 08:40:44 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-a8fc3dc7-d8d5-4db3-8ddd-145b1590bd5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467407785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2467407785 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.269518231 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 564204716 ps |
| CPU time | 61.11 seconds |
| Started | Jul 30 08:37:08 PM PDT 24 |
| Finished | Jul 30 08:38:09 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-a611841a-e5f0-497d-8b2e-007c172ad86c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269518231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_dela ys.269518231 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.1747454149 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 460642064 ps |
| CPU time | 17.61 seconds |
| Started | Jul 30 08:37:11 PM PDT 24 |
| Finished | Jul 30 08:37:29 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-7df75d5e-5209-4376-9349-e1b7fa989f2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747454149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1747454149 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.1926425300 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 40199047 ps |
| CPU time | 6.17 seconds |
| Started | Jul 30 08:37:07 PM PDT 24 |
| Finished | Jul 30 08:37:13 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-7c2a207b-05e7-4d65-8f82-3c5fd7596b79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926425300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1926425300 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.2811822958 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 7468812991 ps |
| CPU time | 76.8 seconds |
| Started | Jul 30 08:37:08 PM PDT 24 |
| Finished | Jul 30 08:38:24 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-9f6da724-e11e-4672-97c5-ac968b94d2fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811822958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2811822958 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.3702016153 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 4519182703 ps |
| CPU time | 75.51 seconds |
| Started | Jul 30 08:37:13 PM PDT 24 |
| Finished | Jul 30 08:38:28 PM PDT 24 |
| Peak memory | 573908 kb |
| Host | smart-4cda81da-349b-4306-a2e9-ff42e68d5d69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702016153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3702016153 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.276852852 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 51741412 ps |
| CPU time | 6.92 seconds |
| Started | Jul 30 08:37:09 PM PDT 24 |
| Finished | Jul 30 08:37:16 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-51631f1e-b909-4e26-9130-dafccdd83b90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276852852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays .276852852 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.2168044573 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 1505505531 ps |
| CPU time | 50.47 seconds |
| Started | Jul 30 08:37:11 PM PDT 24 |
| Finished | Jul 30 08:38:02 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-63eac727-f556-4f18-beca-2d99bf6ba840 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168044573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2168044573 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.1939575755 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 153624058 ps |
| CPU time | 8.68 seconds |
| Started | Jul 30 08:37:16 PM PDT 24 |
| Finished | Jul 30 08:37:25 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-0364b704-c943-4f61-a54e-8e318982da40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939575755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1939575755 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.192183830 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 1818702376 ps |
| CPU time | 244.1 seconds |
| Started | Jul 30 08:37:17 PM PDT 24 |
| Finished | Jul 30 08:41:21 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-72604f5f-2743-47ab-aa82-b6366c2a9a62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192183830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_ with_rand_reset.192183830 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.356719872 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 342301365 ps |
| CPU time | 18.96 seconds |
| Started | Jul 30 08:37:11 PM PDT 24 |
| Finished | Jul 30 08:37:30 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-0269fb5d-5d7b-46f9-8ff0-ea5fcdacdab8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356719872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.356719872 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.851162017 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 447893770 ps |
| CPU time | 33.22 seconds |
| Started | Jul 30 08:37:26 PM PDT 24 |
| Finished | Jul 30 08:37:59 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-9d78fad0-6a55-4824-94a2-58e107ed007e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851162017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device. 851162017 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.1997567462 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 86235725432 ps |
| CPU time | 1490.41 seconds |
| Started | Jul 30 08:37:26 PM PDT 24 |
| Finished | Jul 30 09:02:16 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-5a1c4b07-4f52-482c-af99-72b6afc8c25c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997567462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_ device_slow_rsp.1997567462 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.168452595 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 786203010 ps |
| CPU time | 35.21 seconds |
| Started | Jul 30 08:37:26 PM PDT 24 |
| Finished | Jul 30 08:38:01 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-eaf866e3-144a-42f0-9cba-0efa31132ddb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168452595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr .168452595 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.1237986558 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 973261880 ps |
| CPU time | 37.54 seconds |
| Started | Jul 30 08:37:28 PM PDT 24 |
| Finished | Jul 30 08:38:05 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-761cdb39-5044-4e32-a228-b77811174cb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237986558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1237986558 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.1182824144 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 392408345 ps |
| CPU time | 18.74 seconds |
| Started | Jul 30 08:37:24 PM PDT 24 |
| Finished | Jul 30 08:37:42 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-47c892e6-cabc-4cc7-a90c-a4ba12cf61bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182824144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.1182824144 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.2454067449 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 38295093137 ps |
| CPU time | 398.56 seconds |
| Started | Jul 30 08:37:25 PM PDT 24 |
| Finished | Jul 30 08:44:04 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-a9d6d5f0-188e-45b1-ad40-26b19777d71a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454067449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2454067449 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.31406682 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 57028316865 ps |
| CPU time | 960.95 seconds |
| Started | Jul 30 08:37:23 PM PDT 24 |
| Finished | Jul 30 08:53:24 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-fd618176-8704-43b3-ad88-286ff6b8a6bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31406682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.31406682 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.451962428 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 276210933 ps |
| CPU time | 27.79 seconds |
| Started | Jul 30 08:37:23 PM PDT 24 |
| Finished | Jul 30 08:37:51 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-3cd382b8-1a02-45a3-94f8-b9e3bbd0f9b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451962428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_dela ys.451962428 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.3818016013 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 2168363920 ps |
| CPU time | 68.63 seconds |
| Started | Jul 30 08:37:22 PM PDT 24 |
| Finished | Jul 30 08:38:31 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-edbb2725-0481-4b5e-ae0f-d941ed517ae0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818016013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3818016013 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.3362807535 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 218917164 ps |
| CPU time | 10.43 seconds |
| Started | Jul 30 08:37:15 PM PDT 24 |
| Finished | Jul 30 08:37:25 PM PDT 24 |
| Peak memory | 574036 kb |
| Host | smart-73c94854-858e-43f1-8af3-b20ce39b9c21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362807535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3362807535 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.2549530935 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 6304385641 ps |
| CPU time | 67.32 seconds |
| Started | Jul 30 08:37:24 PM PDT 24 |
| Finished | Jul 30 08:38:31 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-88978370-ad8e-4bf9-96f1-9ab753f02d6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549530935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2549530935 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.960671572 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 5815993023 ps |
| CPU time | 101.5 seconds |
| Started | Jul 30 08:37:32 PM PDT 24 |
| Finished | Jul 30 08:39:14 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-4a208dd6-f52c-4a9b-9241-fb6e6cf25990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960671572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.960671572 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3381089345 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 46760135 ps |
| CPU time | 6.38 seconds |
| Started | Jul 30 08:37:22 PM PDT 24 |
| Finished | Jul 30 08:37:29 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-ac5e2e2b-8944-4585-a08d-11ab56cba635 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381089345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.3381089345 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.4281511100 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 7565553399 ps |
| CPU time | 266.37 seconds |
| Started | Jul 30 08:37:26 PM PDT 24 |
| Finished | Jul 30 08:41:52 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-058f8a26-8bde-47ab-936a-0dcbadc60125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281511100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.4281511100 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.2026674427 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 2152308407 ps |
| CPU time | 202.21 seconds |
| Started | Jul 30 08:37:25 PM PDT 24 |
| Finished | Jul 30 08:40:48 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-a93f77a2-f68d-4c39-acad-8a96d77b2a6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026674427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2026674427 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.3462539591 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 6387231201 ps |
| CPU time | 453.25 seconds |
| Started | Jul 30 08:37:27 PM PDT 24 |
| Finished | Jul 30 08:45:00 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-5301c8be-eac9-4632-a2c0-643c3d3de458 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462539591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.3462539591 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.535273013 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 744699916 ps |
| CPU time | 156.38 seconds |
| Started | Jul 30 08:37:31 PM PDT 24 |
| Finished | Jul 30 08:40:07 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-592c5ca1-3266-436a-9bdc-fbeb7de85588 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535273013 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_reset_error.535273013 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.4174147840 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 828460444 ps |
| CPU time | 37.95 seconds |
| Started | Jul 30 08:37:28 PM PDT 24 |
| Finished | Jul 30 08:38:06 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-47638b6f-e7f0-4ab8-b948-0c64598bdd70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174147840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.4174147840 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.1922883063 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 1974989457 ps |
| CPU time | 94.12 seconds |
| Started | Jul 30 08:37:34 PM PDT 24 |
| Finished | Jul 30 08:39:09 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-66c15841-d8ed-4aab-b191-e6071ee7a35f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922883063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .1922883063 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.378477706 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 110209913184 ps |
| CPU time | 1955.96 seconds |
| Started | Jul 30 08:37:34 PM PDT 24 |
| Finished | Jul 30 09:10:10 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-791b360c-ac7c-4c89-9866-f2818c6bf13d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378477706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_d evice_slow_rsp.378477706 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.2375908151 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 287653558 ps |
| CPU time | 31.9 seconds |
| Started | Jul 30 08:37:39 PM PDT 24 |
| Finished | Jul 30 08:38:11 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-21908918-2965-41ea-99dc-d64b053c7c8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375908151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.2375908151 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.3252891534 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 1523749434 ps |
| CPU time | 53.2 seconds |
| Started | Jul 30 08:37:38 PM PDT 24 |
| Finished | Jul 30 08:38:31 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-686b9c0e-6f32-44fb-a219-e77d2fc16c4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252891534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3252891534 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.189799567 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 1036921090 ps |
| CPU time | 37.03 seconds |
| Started | Jul 30 08:37:35 PM PDT 24 |
| Finished | Jul 30 08:38:12 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-bca59150-288b-44be-8c18-d5fe9d3dd585 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189799567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.189799567 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.2653608554 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 70587178233 ps |
| CPU time | 698.94 seconds |
| Started | Jul 30 08:37:33 PM PDT 24 |
| Finished | Jul 30 08:49:12 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-ab9205b5-7393-412a-bf50-4f1929d92a82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653608554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2653608554 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.1449966929 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 6181972561 ps |
| CPU time | 104.38 seconds |
| Started | Jul 30 08:37:33 PM PDT 24 |
| Finished | Jul 30 08:39:18 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-ddf7c16d-e8e8-46f1-8d55-22700ddfbbb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449966929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1449966929 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.3068587301 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 384080977 ps |
| CPU time | 36.91 seconds |
| Started | Jul 30 08:37:31 PM PDT 24 |
| Finished | Jul 30 08:38:08 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-f906f46d-ee19-47e4-b322-b85fd8020341 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068587301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.3068587301 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.2810138030 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 2538089933 ps |
| CPU time | 87.71 seconds |
| Started | Jul 30 08:37:37 PM PDT 24 |
| Finished | Jul 30 08:39:05 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-6b08da8c-65e1-4465-9c87-5fdd6bab282d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810138030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2810138030 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.456691428 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 42429267 ps |
| CPU time | 6.82 seconds |
| Started | Jul 30 08:37:31 PM PDT 24 |
| Finished | Jul 30 08:37:38 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-d3c87a62-5467-4c69-8d02-96116ad6c7a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456691428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.456691428 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.738570626 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 6276990479 ps |
| CPU time | 65.92 seconds |
| Started | Jul 30 08:37:35 PM PDT 24 |
| Finished | Jul 30 08:38:41 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-3038ee1c-6f39-4f62-9bf5-7969ea3cdd85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738570626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.738570626 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.4154607616 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 5090086086 ps |
| CPU time | 86.81 seconds |
| Started | Jul 30 08:37:34 PM PDT 24 |
| Finished | Jul 30 08:39:01 PM PDT 24 |
| Peak memory | 573964 kb |
| Host | smart-0e82e14e-6123-4142-901b-edfc8a2b48c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154607616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.4154607616 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.234405150 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 49252285 ps |
| CPU time | 7.47 seconds |
| Started | Jul 30 08:37:29 PM PDT 24 |
| Finished | Jul 30 08:37:37 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-a992e6f1-c9fa-4190-9448-8d103436e9d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234405150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays .234405150 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.2407794973 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 8418247315 ps |
| CPU time | 327.82 seconds |
| Started | Jul 30 08:37:38 PM PDT 24 |
| Finished | Jul 30 08:43:06 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-b812951f-537d-41de-b0d5-456bd56d06f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407794973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2407794973 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.4223744729 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 4361250125 ps |
| CPU time | 153.76 seconds |
| Started | Jul 30 08:37:39 PM PDT 24 |
| Finished | Jul 30 08:40:13 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-a7f03a30-6fad-4601-a8d9-cb6a3fd4eae3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223744729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.4223744729 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3617426711 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 2430619084 ps |
| CPU time | 244.98 seconds |
| Started | Jul 30 08:37:39 PM PDT 24 |
| Finished | Jul 30 08:41:44 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-2281bb46-82ff-40f9-b97c-207a92af032c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617426711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.3617426711 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.3626332754 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 4498584703 ps |
| CPU time | 341.82 seconds |
| Started | Jul 30 08:37:39 PM PDT 24 |
| Finished | Jul 30 08:43:21 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-d62c4d87-3f42-4827-9136-276791309585 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626332754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.3626332754 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.102044000 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 99963157 ps |
| CPU time | 13.62 seconds |
| Started | Jul 30 08:37:38 PM PDT 24 |
| Finished | Jul 30 08:37:52 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-84206bda-a291-4363-acbb-689fbc5ad919 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102044000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.102044000 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.266518384 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 2955022077 ps |
| CPU time | 128.96 seconds |
| Started | Jul 30 08:37:45 PM PDT 24 |
| Finished | Jul 30 08:39:54 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-5671ba55-405b-4f4a-86f1-02fc227a1d84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266518384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device. 266518384 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.946133021 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 119094375047 ps |
| CPU time | 2153.81 seconds |
| Started | Jul 30 08:37:44 PM PDT 24 |
| Finished | Jul 30 09:13:38 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-4bb842fe-4e35-497a-87e6-a2462bae0be7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946133021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_d evice_slow_rsp.946133021 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.2746316837 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 100642425 ps |
| CPU time | 7.93 seconds |
| Started | Jul 30 08:37:45 PM PDT 24 |
| Finished | Jul 30 08:37:53 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-4cfbc5ce-c38f-4d6b-9270-1197db491612 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746316837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.2746316837 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.2942109743 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 2223437321 ps |
| CPU time | 85.82 seconds |
| Started | Jul 30 08:37:44 PM PDT 24 |
| Finished | Jul 30 08:39:10 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-e26475fc-118b-4d79-a5e9-1fc8e6f262ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942109743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2942109743 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.1397481375 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 95855410 ps |
| CPU time | 11.36 seconds |
| Started | Jul 30 08:37:48 PM PDT 24 |
| Finished | Jul 30 08:38:00 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-be3d2ff6-9e9d-4705-8e35-87ad1459d748 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397481375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.1397481375 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.3750457166 |
| Short name | T2935 |
| Test name | |
| Test status | |
| Simulation time | 24709836077 ps |
| CPU time | 248.2 seconds |
| Started | Jul 30 08:37:49 PM PDT 24 |
| Finished | Jul 30 08:41:57 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-9b69ae87-7c05-476a-a420-7336822fe754 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750457166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3750457166 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.1259234538 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 15462949734 ps |
| CPU time | 272.09 seconds |
| Started | Jul 30 08:37:45 PM PDT 24 |
| Finished | Jul 30 08:42:17 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-0391de6e-01f4-46b7-b6a9-2a19fef59249 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259234538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1259234538 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.644903019 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 398625283 ps |
| CPU time | 36.23 seconds |
| Started | Jul 30 08:37:48 PM PDT 24 |
| Finished | Jul 30 08:38:24 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-4a74bed8-e6e8-4d42-90d4-1ab4269ed992 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644903019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_dela ys.644903019 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.1103688193 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 1009990518 ps |
| CPU time | 31.5 seconds |
| Started | Jul 30 08:37:39 PM PDT 24 |
| Finished | Jul 30 08:38:11 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-091976ad-eae5-4252-825f-784e133ca287 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103688193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1103688193 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.3173598620 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 235646077 ps |
| CPU time | 10.06 seconds |
| Started | Jul 30 08:37:37 PM PDT 24 |
| Finished | Jul 30 08:37:47 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-aca41a8a-1b67-46b5-9623-4e6808d66e62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173598620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3173598620 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.3759589428 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 9665386887 ps |
| CPU time | 108.66 seconds |
| Started | Jul 30 08:37:43 PM PDT 24 |
| Finished | Jul 30 08:39:31 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-20fea069-f694-4fbf-81cb-a1a26bff48b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759589428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3759589428 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.2531919371 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 2539453440 ps |
| CPU time | 42.04 seconds |
| Started | Jul 30 08:37:42 PM PDT 24 |
| Finished | Jul 30 08:38:25 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-9517ca82-7df0-4935-8d99-f9983e15558f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531919371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2531919371 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.3037085601 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 40000249 ps |
| CPU time | 6.39 seconds |
| Started | Jul 30 08:37:41 PM PDT 24 |
| Finished | Jul 30 08:37:47 PM PDT 24 |
| Peak memory | 573784 kb |
| Host | smart-803fe8c2-ff60-406f-9f2d-ff75598d5809 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037085601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.3037085601 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.972803092 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 7983057738 ps |
| CPU time | 351.58 seconds |
| Started | Jul 30 08:37:46 PM PDT 24 |
| Finished | Jul 30 08:43:38 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-5fa03e85-d566-44da-81e7-866b02900897 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972803092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.972803092 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.2455715235 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 4121527887 ps |
| CPU time | 164.38 seconds |
| Started | Jul 30 08:37:50 PM PDT 24 |
| Finished | Jul 30 08:40:34 PM PDT 24 |
| Peak memory | 576180 kb |
| Host | smart-926c707f-5ee4-4483-b399-98559df41ebb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455715235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2455715235 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.2673220485 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 841491863 ps |
| CPU time | 353.14 seconds |
| Started | Jul 30 08:37:51 PM PDT 24 |
| Finished | Jul 30 08:43:44 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-8cd7a286-25aa-4477-b21f-d2b3ec7de99e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673220485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.2673220485 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.468591510 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 16422892159 ps |
| CPU time | 697.38 seconds |
| Started | Jul 30 08:37:49 PM PDT 24 |
| Finished | Jul 30 08:49:27 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-ac37e787-af55-4bf1-a54c-a46d6de9a711 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468591510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_reset_error.468591510 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.1917002103 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 1215164355 ps |
| CPU time | 58.56 seconds |
| Started | Jul 30 08:37:45 PM PDT 24 |
| Finished | Jul 30 08:38:44 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-84720439-8bb4-487a-bba9-e8f5b254212c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917002103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.1917002103 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.3834777378 |
| Short name | T2923 |
| Test name | |
| Test status | |
| Simulation time | 3662932013 ps |
| CPU time | 158.75 seconds |
| Started | Jul 30 08:37:56 PM PDT 24 |
| Finished | Jul 30 08:40:35 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-17f74282-62c8-4f3d-8aa7-fc7f21ddd0fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834777378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .3834777378 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.2526880033 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 46784564463 ps |
| CPU time | 840.97 seconds |
| Started | Jul 30 08:37:52 PM PDT 24 |
| Finished | Jul 30 08:51:53 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-bc0d80e2-2bae-4215-bcd9-6664c4f35bcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526880033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_ device_slow_rsp.2526880033 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.2908797555 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 762189866 ps |
| CPU time | 34.92 seconds |
| Started | Jul 30 08:37:58 PM PDT 24 |
| Finished | Jul 30 08:38:33 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-6a26cfc8-f2c2-4803-b2d0-40738e6f9a9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908797555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.2908797555 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.1848511864 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 204772290 ps |
| CPU time | 18.32 seconds |
| Started | Jul 30 08:37:56 PM PDT 24 |
| Finished | Jul 30 08:38:15 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-09c55b47-d173-4afd-bb4e-4b8d00169f8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848511864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1848511864 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.91622256 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 206316894 ps |
| CPU time | 21.07 seconds |
| Started | Jul 30 08:37:56 PM PDT 24 |
| Finished | Jul 30 08:38:17 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-f2b92a34-668d-417f-89e1-d7485a398a4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91622256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.91622256 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.3846045928 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 6601504585 ps |
| CPU time | 71 seconds |
| Started | Jul 30 08:37:53 PM PDT 24 |
| Finished | Jul 30 08:39:04 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-2a475bcf-3c61-4c22-999d-a479eb48cdfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846045928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3846045928 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.2690862206 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 54438757966 ps |
| CPU time | 977.88 seconds |
| Started | Jul 30 08:37:51 PM PDT 24 |
| Finished | Jul 30 08:54:09 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-f58ed2d8-5da1-4077-ad74-4906d1a04026 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690862206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2690862206 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.2937608967 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 415491556 ps |
| CPU time | 45.05 seconds |
| Started | Jul 30 08:37:52 PM PDT 24 |
| Finished | Jul 30 08:38:38 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-da63d09d-9bad-4321-bd53-ba3f5787d033 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937608967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del ays.2937608967 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.1010653038 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 162978058 ps |
| CPU time | 15.41 seconds |
| Started | Jul 30 08:37:56 PM PDT 24 |
| Finished | Jul 30 08:38:12 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-b2aa8970-7a33-415b-8d07-05e1880c8f43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010653038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1010653038 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.2657920840 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 154298857 ps |
| CPU time | 7.92 seconds |
| Started | Jul 30 08:37:50 PM PDT 24 |
| Finished | Jul 30 08:37:58 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-b751f3b4-6603-4653-ac1a-4af34e4a2011 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657920840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2657920840 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.3830610693 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 8224634678 ps |
| CPU time | 86.94 seconds |
| Started | Jul 30 08:37:50 PM PDT 24 |
| Finished | Jul 30 08:39:17 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-d3405455-c039-45d7-9f5b-c8adec6499e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830610693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3830610693 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.1261433477 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 5112529412 ps |
| CPU time | 95.65 seconds |
| Started | Jul 30 08:37:52 PM PDT 24 |
| Finished | Jul 30 08:39:27 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-3d6e1830-c1fa-44a2-90a7-3cb793bd0092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261433477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1261433477 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.1807152509 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 52884533 ps |
| CPU time | 7.55 seconds |
| Started | Jul 30 08:37:52 PM PDT 24 |
| Finished | Jul 30 08:38:00 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-bc3fe8d4-fa87-418a-944d-4ef00b13d83b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807152509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.1807152509 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.752699252 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 11554244073 ps |
| CPU time | 500.64 seconds |
| Started | Jul 30 08:38:01 PM PDT 24 |
| Finished | Jul 30 08:46:22 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-2ceb940f-ae17-4a47-b8ff-d0f1a119ce10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752699252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.752699252 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.3915813657 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 1460538107 ps |
| CPU time | 111.13 seconds |
| Started | Jul 30 08:38:06 PM PDT 24 |
| Finished | Jul 30 08:39:57 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-fa92b124-e4c8-4631-9a51-0e386a5c0867 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915813657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3915813657 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.3084390841 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 8129371850 ps |
| CPU time | 856.21 seconds |
| Started | Jul 30 08:38:03 PM PDT 24 |
| Finished | Jul 30 08:52:19 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-e3e85e40-d2a9-44d9-b725-0610b712f55f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084390841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.3084390841 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.2452824763 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 242087232 ps |
| CPU time | 82.71 seconds |
| Started | Jul 30 08:38:05 PM PDT 24 |
| Finished | Jul 30 08:39:27 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-8364174e-0e2a-47e6-821c-a0109cb76ca8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452824763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.2452824763 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.1043430997 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 1201472989 ps |
| CPU time | 51.91 seconds |
| Started | Jul 30 08:37:57 PM PDT 24 |
| Finished | Jul 30 08:38:49 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-490be96b-fe08-4009-b672-e1ac423f06cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043430997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1043430997 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.249558612 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 1111261184 ps |
| CPU time | 45.64 seconds |
| Started | Jul 30 08:38:11 PM PDT 24 |
| Finished | Jul 30 08:38:56 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-b285d8f0-3580-4c5d-bb76-39d1687d7ba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249558612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device. 249558612 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.1320746722 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 64679537429 ps |
| CPU time | 1118.75 seconds |
| Started | Jul 30 08:38:10 PM PDT 24 |
| Finished | Jul 30 08:56:49 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-8eb0f2fe-ccfb-4709-983c-3dcf4a91e10d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320746722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.1320746722 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3834596897 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 168379599 ps |
| CPU time | 9.87 seconds |
| Started | Jul 30 08:38:10 PM PDT 24 |
| Finished | Jul 30 08:38:20 PM PDT 24 |
| Peak memory | 573968 kb |
| Host | smart-cb10e0ed-2e86-41fc-8638-3d23a0f42663 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834596897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.3834596897 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.3193302867 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 517530695 ps |
| CPU time | 46.87 seconds |
| Started | Jul 30 08:38:12 PM PDT 24 |
| Finished | Jul 30 08:38:59 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-3d7045f3-b9af-448e-b0f4-46ee8ec4276e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193302867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3193302867 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.3726400812 |
| Short name | T2930 |
| Test name | |
| Test status | |
| Simulation time | 1346208059 ps |
| CPU time | 52.28 seconds |
| Started | Jul 30 08:38:05 PM PDT 24 |
| Finished | Jul 30 08:38:57 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-36655d78-b84b-450e-9b8b-8c111736e557 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726400812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.3726400812 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.3610033661 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 53457704314 ps |
| CPU time | 617.17 seconds |
| Started | Jul 30 08:38:06 PM PDT 24 |
| Finished | Jul 30 08:48:24 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-bb35b787-a696-431b-9cc0-5a613e192daf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610033661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3610033661 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.426435813 |
| Short name | T2936 |
| Test name | |
| Test status | |
| Simulation time | 25922236072 ps |
| CPU time | 485.11 seconds |
| Started | Jul 30 08:38:06 PM PDT 24 |
| Finished | Jul 30 08:46:11 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-03eb3815-d3f8-456a-b2c9-bd7524e3e2d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426435813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.426435813 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.1640841210 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 159069512 ps |
| CPU time | 16.56 seconds |
| Started | Jul 30 08:38:08 PM PDT 24 |
| Finished | Jul 30 08:38:25 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-d04a183a-229d-4a21-9f24-387304872979 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640841210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.1640841210 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.2475802120 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 305845660 ps |
| CPU time | 27.09 seconds |
| Started | Jul 30 08:38:13 PM PDT 24 |
| Finished | Jul 30 08:38:40 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-ea3f73a3-58cd-43d9-bda1-5e85d9a37b00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475802120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2475802120 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.3720735872 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 179050298 ps |
| CPU time | 9.27 seconds |
| Started | Jul 30 08:38:04 PM PDT 24 |
| Finished | Jul 30 08:38:14 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-ef2d8af2-6c30-4a16-8488-f2aa0b7cd1b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720735872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3720735872 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.1767207522 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 5603398342 ps |
| CPU time | 63.29 seconds |
| Started | Jul 30 08:38:04 PM PDT 24 |
| Finished | Jul 30 08:39:07 PM PDT 24 |
| Peak memory | 573924 kb |
| Host | smart-e3ceb55b-76a3-431a-836a-a361f2a2b805 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767207522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1767207522 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.4113827569 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 4588433464 ps |
| CPU time | 80.94 seconds |
| Started | Jul 30 08:38:05 PM PDT 24 |
| Finished | Jul 30 08:39:26 PM PDT 24 |
| Peak memory | 574632 kb |
| Host | smart-55ecc503-4d24-4ba4-a8cc-753a9aef2300 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113827569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.4113827569 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.671335692 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 43555655 ps |
| CPU time | 6.7 seconds |
| Started | Jul 30 08:38:06 PM PDT 24 |
| Finished | Jul 30 08:38:13 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-3e0efb8e-1bbd-4a00-9f16-151fb66f7274 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671335692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays .671335692 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.2299277933 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 339769096 ps |
| CPU time | 46.93 seconds |
| Started | Jul 30 08:38:10 PM PDT 24 |
| Finished | Jul 30 08:38:57 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-c3709cc0-9f9c-4de6-acf7-0a95fce7e77c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299277933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2299277933 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.3352397497 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 1999618068 ps |
| CPU time | 87.97 seconds |
| Started | Jul 30 08:38:14 PM PDT 24 |
| Finished | Jul 30 08:39:42 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-500f4c0c-0c3f-4a71-9e0d-1de50e57c2f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352397497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3352397497 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.1849268836 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 3409276684 ps |
| CPU time | 434.94 seconds |
| Started | Jul 30 08:38:15 PM PDT 24 |
| Finished | Jul 30 08:45:30 PM PDT 24 |
| Peak memory | 576872 kb |
| Host | smart-e64af93e-58c1-42c7-aaf3-30187d9052c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849268836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.1849268836 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.3806151067 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 107668395 ps |
| CPU time | 32.89 seconds |
| Started | Jul 30 08:38:14 PM PDT 24 |
| Finished | Jul 30 08:38:47 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-5cbf5ae1-4322-4683-b0cb-130702882b49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806151067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.3806151067 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.1390679809 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 287901658 ps |
| CPU time | 37.68 seconds |
| Started | Jul 30 08:38:12 PM PDT 24 |
| Finished | Jul 30 08:38:50 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-6d96a984-68be-4cf6-8f1f-d4041194cc02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390679809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1390679809 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.2252299371 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 143383918 ps |
| CPU time | 14.12 seconds |
| Started | Jul 30 08:38:25 PM PDT 24 |
| Finished | Jul 30 08:38:39 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-ad0bbea9-2698-43f9-b727-79c87a2d06e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252299371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .2252299371 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.1754135392 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 138245710662 ps |
| CPU time | 2377.57 seconds |
| Started | Jul 30 08:38:27 PM PDT 24 |
| Finished | Jul 30 09:18:05 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-807a0f00-0d43-424e-b219-22e1026e229c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754135392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.1754135392 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.1159240753 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 286238161 ps |
| CPU time | 37.42 seconds |
| Started | Jul 30 08:38:27 PM PDT 24 |
| Finished | Jul 30 08:39:05 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-f60cdb8e-e86c-4ea1-987d-d4658e514758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159240753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.1159240753 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.3728851724 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 2014786024 ps |
| CPU time | 68.8 seconds |
| Started | Jul 30 08:38:21 PM PDT 24 |
| Finished | Jul 30 08:39:30 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-bb1d8a7b-5815-46b9-b625-076d0f885423 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728851724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3728851724 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.2202033816 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 1413895568 ps |
| CPU time | 50.87 seconds |
| Started | Jul 30 08:38:14 PM PDT 24 |
| Finished | Jul 30 08:39:05 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-c447708d-c25f-476d-9d34-3c1333f8bd34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202033816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.2202033816 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.2387560184 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 67614407973 ps |
| CPU time | 748.94 seconds |
| Started | Jul 30 08:38:17 PM PDT 24 |
| Finished | Jul 30 08:50:46 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-7a9c92f0-cb73-4385-83f6-c961aae8f654 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387560184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2387560184 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.3303125387 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 65089363565 ps |
| CPU time | 1163.96 seconds |
| Started | Jul 30 08:38:18 PM PDT 24 |
| Finished | Jul 30 08:57:42 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-d188fa28-a6c0-459b-9d13-ba32673898f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303125387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3303125387 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.265836900 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 136628208 ps |
| CPU time | 16.86 seconds |
| Started | Jul 30 08:38:18 PM PDT 24 |
| Finished | Jul 30 08:38:35 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-3607051d-9953-48a2-911f-cab0a61cdb4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265836900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_dela ys.265836900 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.656006008 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 179016386 ps |
| CPU time | 8.6 seconds |
| Started | Jul 30 08:38:24 PM PDT 24 |
| Finished | Jul 30 08:38:32 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-596783bd-d5b8-414e-9e57-7384e1ab9ca5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656006008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.656006008 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.2318086958 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 175186398 ps |
| CPU time | 9.21 seconds |
| Started | Jul 30 08:38:15 PM PDT 24 |
| Finished | Jul 30 08:38:25 PM PDT 24 |
| Peak memory | 573876 kb |
| Host | smart-56668b4d-4675-42f6-b176-cbf54cde5bfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318086958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2318086958 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.4245921479 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 8969974146 ps |
| CPU time | 95.1 seconds |
| Started | Jul 30 08:38:15 PM PDT 24 |
| Finished | Jul 30 08:39:50 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-52e12048-bb8d-4ed7-b75e-df84175445d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245921479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.4245921479 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.3054730464 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 6302923106 ps |
| CPU time | 106.28 seconds |
| Started | Jul 30 08:38:13 PM PDT 24 |
| Finished | Jul 30 08:40:00 PM PDT 24 |
| Peak memory | 573896 kb |
| Host | smart-d2937f3f-ba63-40fb-8b7f-e73ca9f6c79d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054730464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3054730464 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.83852333 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 45520391 ps |
| CPU time | 6.85 seconds |
| Started | Jul 30 08:38:16 PM PDT 24 |
| Finished | Jul 30 08:38:22 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-ac38c4c2-088c-436e-b8ca-cf4a49b9ceb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83852333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.83852333 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.1813144849 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 120569680 ps |
| CPU time | 8.75 seconds |
| Started | Jul 30 08:38:26 PM PDT 24 |
| Finished | Jul 30 08:38:35 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-142d10d1-9703-467a-8c5f-215d7f86609f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813144849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1813144849 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.2808161683 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 576419195 ps |
| CPU time | 49.64 seconds |
| Started | Jul 30 08:38:25 PM PDT 24 |
| Finished | Jul 30 08:39:15 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-a07b7fc9-3b71-4ab9-815a-136fec39b283 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808161683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2808161683 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.507566596 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 155756448 ps |
| CPU time | 53.84 seconds |
| Started | Jul 30 08:38:27 PM PDT 24 |
| Finished | Jul 30 08:39:21 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-0ebaba06-a57f-4d24-a7c9-6d2bf85d8698 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507566596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_ with_rand_reset.507566596 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.2436213810 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 1561454041 ps |
| CPU time | 73.2 seconds |
| Started | Jul 30 08:38:24 PM PDT 24 |
| Finished | Jul 30 08:39:38 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-8e8ff8de-cac3-4078-8d8c-8c5aa28eeb5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436213810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2436213810 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.3156058017 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 201050688 ps |
| CPU time | 23.92 seconds |
| Started | Jul 30 08:38:33 PM PDT 24 |
| Finished | Jul 30 08:38:57 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-d7033095-9030-49d1-aefe-e547fa564d46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156058017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .3156058017 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2725043096 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 128466200277 ps |
| CPU time | 2179.55 seconds |
| Started | Jul 30 08:38:33 PM PDT 24 |
| Finished | Jul 30 09:14:53 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-95705e3a-ae8d-461a-930f-1b356efe419a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725043096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.2725043096 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.343693683 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 177353198 ps |
| CPU time | 10.61 seconds |
| Started | Jul 30 08:38:40 PM PDT 24 |
| Finished | Jul 30 08:38:50 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-3cda6fbe-4875-46eb-9932-564d73305320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343693683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr .343693683 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.356660870 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 1181799055 ps |
| CPU time | 43.36 seconds |
| Started | Jul 30 08:38:32 PM PDT 24 |
| Finished | Jul 30 08:39:15 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-723d0f50-cfff-4263-a6f1-6502b6cc43a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356660870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.356660870 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.3043800933 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 96477138 ps |
| CPU time | 11.76 seconds |
| Started | Jul 30 08:38:27 PM PDT 24 |
| Finished | Jul 30 08:38:39 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-d2cc6fcf-186a-481e-8fca-ed4bc297479f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043800933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.3043800933 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.3790507500 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 38030905985 ps |
| CPU time | 404.88 seconds |
| Started | Jul 30 08:38:31 PM PDT 24 |
| Finished | Jul 30 08:45:16 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-ee435880-e24f-42d3-9c7e-6e2de984f3ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790507500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3790507500 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.222227382 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 7550737101 ps |
| CPU time | 136.57 seconds |
| Started | Jul 30 08:38:33 PM PDT 24 |
| Finished | Jul 30 08:40:49 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-9a9f7160-0898-4633-8e48-624014a6b994 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222227382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.222227382 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.1780077297 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 50998472 ps |
| CPU time | 8.78 seconds |
| Started | Jul 30 08:38:26 PM PDT 24 |
| Finished | Jul 30 08:38:35 PM PDT 24 |
| Peak memory | 573780 kb |
| Host | smart-9ac43793-b008-4158-9cb5-f29e0dffa649 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780077297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.1780077297 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.1747051584 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 2747777451 ps |
| CPU time | 81.17 seconds |
| Started | Jul 30 08:38:31 PM PDT 24 |
| Finished | Jul 30 08:39:53 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-e378092d-9627-4cdf-80d4-4ebb1d7f4077 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747051584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1747051584 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.1353924864 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 204123134 ps |
| CPU time | 8.98 seconds |
| Started | Jul 30 08:38:28 PM PDT 24 |
| Finished | Jul 30 08:38:37 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-52398618-d65a-42f3-b8ab-b9bf29e36874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353924864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1353924864 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.3847857227 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 7755741135 ps |
| CPU time | 78.78 seconds |
| Started | Jul 30 08:38:28 PM PDT 24 |
| Finished | Jul 30 08:39:47 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-4068ea64-39c3-489d-a51e-f1d87cbd87d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847857227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3847857227 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.82396812 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 4585860622 ps |
| CPU time | 75.68 seconds |
| Started | Jul 30 08:38:26 PM PDT 24 |
| Finished | Jul 30 08:39:42 PM PDT 24 |
| Peak memory | 573896 kb |
| Host | smart-a7b147bb-3cee-4828-ab37-907507e82150 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82396812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.82396812 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.2234908151 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 45297043 ps |
| CPU time | 5.88 seconds |
| Started | Jul 30 08:38:26 PM PDT 24 |
| Finished | Jul 30 08:38:32 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-1df01067-c0d9-47b6-8cd9-9e87c9d675b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234908151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.2234908151 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.1253325530 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 3725935361 ps |
| CPU time | 349.26 seconds |
| Started | Jul 30 08:38:42 PM PDT 24 |
| Finished | Jul 30 08:44:32 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-d8a6dd37-e323-4965-9221-b090f3469c4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253325530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1253325530 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.3512488223 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 1424257467 ps |
| CPU time | 55.37 seconds |
| Started | Jul 30 08:38:38 PM PDT 24 |
| Finished | Jul 30 08:39:33 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-dc90e461-8b90-499f-95be-8a5b7eb9ae27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512488223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3512488223 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1983481957 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 5910059675 ps |
| CPU time | 391.73 seconds |
| Started | Jul 30 08:38:38 PM PDT 24 |
| Finished | Jul 30 08:45:10 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-e43ecbca-94dd-4162-81c1-e96011ce0533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983481957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.1983481957 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2662992836 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 175963885 ps |
| CPU time | 47.37 seconds |
| Started | Jul 30 08:38:39 PM PDT 24 |
| Finished | Jul 30 08:39:26 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-9d978c1e-a7eb-4a35-9d33-316e451d544a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662992836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.2662992836 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.2450067079 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 62174307 ps |
| CPU time | 6.68 seconds |
| Started | Jul 30 08:38:36 PM PDT 24 |
| Finished | Jul 30 08:38:43 PM PDT 24 |
| Peak memory | 573948 kb |
| Host | smart-931380dc-f50b-4e84-93bd-3be5829727bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450067079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2450067079 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.938654349 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 866945731 ps |
| CPU time | 42.93 seconds |
| Started | Jul 30 08:38:45 PM PDT 24 |
| Finished | Jul 30 08:39:28 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-8e8036c6-021c-4a30-9d77-009a0db0a21f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938654349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device. 938654349 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.3065531636 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 105163013308 ps |
| CPU time | 1832.76 seconds |
| Started | Jul 30 08:38:44 PM PDT 24 |
| Finished | Jul 30 09:09:17 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-c782d756-b295-4736-b760-ad2d15694cde |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065531636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_ device_slow_rsp.3065531636 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.1022955133 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 325239971 ps |
| CPU time | 38.03 seconds |
| Started | Jul 30 08:38:49 PM PDT 24 |
| Finished | Jul 30 08:39:27 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-d3903a1d-8228-44b8-b98b-339c1177a1d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022955133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.1022955133 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.1373777740 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 1997186308 ps |
| CPU time | 70.3 seconds |
| Started | Jul 30 08:38:46 PM PDT 24 |
| Finished | Jul 30 08:39:56 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-8bb77720-deff-4ecc-bd2a-eb92ae43ba5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373777740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1373777740 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.1636389950 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 373164195 ps |
| CPU time | 40.82 seconds |
| Started | Jul 30 08:38:44 PM PDT 24 |
| Finished | Jul 30 08:39:24 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-05c260ca-87ab-4e35-90d1-e75aadac851e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636389950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.1636389950 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.86072767 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 94869052520 ps |
| CPU time | 930.76 seconds |
| Started | Jul 30 08:38:47 PM PDT 24 |
| Finished | Jul 30 08:54:18 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-6091f445-2b0a-4236-961a-4d64e3247147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86072767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.86072767 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.3088754290 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 14291746611 ps |
| CPU time | 249.5 seconds |
| Started | Jul 30 08:38:47 PM PDT 24 |
| Finished | Jul 30 08:42:57 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-62268648-7850-430f-a99e-4f317c34ee71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088754290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3088754290 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.3547903919 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 533932619 ps |
| CPU time | 47.21 seconds |
| Started | Jul 30 08:38:43 PM PDT 24 |
| Finished | Jul 30 08:39:31 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-cef1de60-04b5-4853-9dcd-5a6892721a1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547903919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del ays.3547903919 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.1650642803 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 2002065273 ps |
| CPU time | 63.43 seconds |
| Started | Jul 30 08:38:44 PM PDT 24 |
| Finished | Jul 30 08:39:47 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-4fae1021-29dc-469e-af88-3fb34c37fc93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650642803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1650642803 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.2700276835 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 54125024 ps |
| CPU time | 7.61 seconds |
| Started | Jul 30 08:38:37 PM PDT 24 |
| Finished | Jul 30 08:38:45 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-a9ada99f-d651-4842-9b8a-70752cbef336 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700276835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2700276835 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.1994182000 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 10309786414 ps |
| CPU time | 115.13 seconds |
| Started | Jul 30 08:38:45 PM PDT 24 |
| Finished | Jul 30 08:40:41 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-20dc7db7-bd95-452c-be4f-daa39c023341 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994182000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1994182000 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.65503412 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 6594863372 ps |
| CPU time | 115.28 seconds |
| Started | Jul 30 08:38:40 PM PDT 24 |
| Finished | Jul 30 08:40:36 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-69208010-7dc9-4024-a4e2-fab3456d4bd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65503412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.65503412 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.2580113231 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 37642297 ps |
| CPU time | 6.82 seconds |
| Started | Jul 30 08:38:36 PM PDT 24 |
| Finished | Jul 30 08:38:43 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-dfe6b3dc-3080-4af2-b4ed-f5a60beb6aac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580113231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.2580113231 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.693741426 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 5964288165 ps |
| CPU time | 248.59 seconds |
| Started | Jul 30 08:38:47 PM PDT 24 |
| Finished | Jul 30 08:42:56 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-70f30281-8b50-4604-8856-65b2280d30be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693741426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.693741426 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.9845922 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 19346923102 ps |
| CPU time | 771.24 seconds |
| Started | Jul 30 08:38:47 PM PDT 24 |
| Finished | Jul 30 08:51:39 PM PDT 24 |
| Peak memory | 576828 kb |
| Host | smart-c8dd0029-33c4-41b2-af3d-d35c3abd0016 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9845922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.9845922 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.149284072 |
| Short name | T2931 |
| Test name | |
| Test status | |
| Simulation time | 910006027 ps |
| CPU time | 215.31 seconds |
| Started | Jul 30 08:38:48 PM PDT 24 |
| Finished | Jul 30 08:42:23 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-56704a43-c3ac-4533-9e24-0ec5ff1a45fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149284072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_ with_rand_reset.149284072 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.3206526810 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 5605531908 ps |
| CPU time | 330.07 seconds |
| Started | Jul 30 08:38:51 PM PDT 24 |
| Finished | Jul 30 08:44:22 PM PDT 24 |
| Peak memory | 576848 kb |
| Host | smart-bd5a72c0-e29d-450a-aa78-b47f00a22367 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206526810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.3206526810 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.419320408 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 613783409 ps |
| CPU time | 27.95 seconds |
| Started | Jul 30 08:38:49 PM PDT 24 |
| Finished | Jul 30 08:39:17 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-74784dd3-fac5-4ec5-9148-477a0dd6f7a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419320408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.419320408 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.1884124506 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 66765148720 ps |
| CPU time | 9002.58 seconds |
| Started | Jul 30 08:28:05 PM PDT 24 |
| Finished | Jul 30 10:58:09 PM PDT 24 |
| Peak memory | 634076 kb |
| Host | smart-2d1c7019-1c26-434d-872d-d5d2ef39cd70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884124506 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.chip_csr_aliasing.1884124506 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.1664629256 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 34342722574 ps |
| CPU time | 3521.75 seconds |
| Started | Jul 30 08:28:10 PM PDT 24 |
| Finished | Jul 30 09:26:52 PM PDT 24 |
| Peak memory | 592712 kb |
| Host | smart-88b0d903-e2b0-44e4-ae65-1bbf9e39e23f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664629256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.1664629256 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3677914368 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 5312657000 ps |
| CPU time | 301.1 seconds |
| Started | Jul 30 08:28:36 PM PDT 24 |
| Finished | Jul 30 08:33:37 PM PDT 24 |
| Peak memory | 661724 kb |
| Host | smart-d695627c-ae8a-41e3-b5d9-291cc28bdf83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677914368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.3677914368 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.1865401606 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 7263148352 ps |
| CPU time | 548.56 seconds |
| Started | Jul 30 08:28:40 PM PDT 24 |
| Finished | Jul 30 08:37:49 PM PDT 24 |
| Peak memory | 637668 kb |
| Host | smart-18614db6-16b9-477b-8bc6-8b9f8d3b51d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865401606 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.1865401606 |
| Directory | /workspace/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.2091396085 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 6115947192 ps |
| CPU time | 710.25 seconds |
| Started | Jul 30 08:28:38 PM PDT 24 |
| Finished | Jul 30 08:40:28 PM PDT 24 |
| Peak memory | 598888 kb |
| Host | smart-29f43e3a-7c94-4508-accd-f09c5aa1b333 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091396085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.2091396085 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.1626670695 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 16603221518 ps |
| CPU time | 2149.16 seconds |
| Started | Jul 30 08:28:04 PM PDT 24 |
| Finished | Jul 30 09:03:54 PM PDT 24 |
| Peak memory | 593228 kb |
| Host | smart-f51cea88-4500-458d-8a83-2615b399e845 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626670695 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.1626670695 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.266440688 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 3115802781 ps |
| CPU time | 276.18 seconds |
| Started | Jul 30 08:28:10 PM PDT 24 |
| Finished | Jul 30 08:32:46 PM PDT 24 |
| Peak memory | 598692 kb |
| Host | smart-40793fc3-50f2-4b98-ba33-973984772a83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266440688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.266440688 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.423046232 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 620477754 ps |
| CPU time | 28.49 seconds |
| Started | Jul 30 08:28:21 PM PDT 24 |
| Finished | Jul 30 08:28:49 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-96f14877-7789-4f52-9588-60cfd328c899 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423046232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.423046232 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.416245241 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 90318939005 ps |
| CPU time | 1647.02 seconds |
| Started | Jul 30 08:28:26 PM PDT 24 |
| Finished | Jul 30 08:55:53 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-f76bb305-4551-4714-91c6-3a7f0ca0f49a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416245241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_de vice_slow_rsp.416245241 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.2363971276 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 97067024 ps |
| CPU time | 12.8 seconds |
| Started | Jul 30 08:28:23 PM PDT 24 |
| Finished | Jul 30 08:28:35 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-93d59699-ba99-4c53-9cd1-2a2231a4b542 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363971276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .2363971276 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.4076114698 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 1060278364 ps |
| CPU time | 39.01 seconds |
| Started | Jul 30 08:28:28 PM PDT 24 |
| Finished | Jul 30 08:29:07 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-de27ca31-215a-49bd-8e5f-aa4683ac2bb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076114698 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.4076114698 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.3557337433 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 1143529577 ps |
| CPU time | 45.82 seconds |
| Started | Jul 30 08:28:42 PM PDT 24 |
| Finished | Jul 30 08:29:28 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-0a55b7d2-a071-4d02-a2e9-ca61fb00cc6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557337433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.3557337433 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.1272506677 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 66830978517 ps |
| CPU time | 797.27 seconds |
| Started | Jul 30 08:28:21 PM PDT 24 |
| Finished | Jul 30 08:41:38 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-0baaa01d-1780-47b0-aee4-b6b0dca5c3e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272506677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1272506677 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.783524014 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 62394777219 ps |
| CPU time | 1116.7 seconds |
| Started | Jul 30 08:28:19 PM PDT 24 |
| Finished | Jul 30 08:46:56 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-9af3c12d-f5a4-4f75-876b-460dd40fbbbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783524014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.783524014 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.1700436221 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 81352162 ps |
| CPU time | 10.84 seconds |
| Started | Jul 30 08:28:20 PM PDT 24 |
| Finished | Jul 30 08:28:31 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-90cc6b50-0d59-48a7-aca5-22726e6eb898 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700436221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.1700436221 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.1515944283 |
| Short name | T2929 |
| Test name | |
| Test status | |
| Simulation time | 431497061 ps |
| CPU time | 16.14 seconds |
| Started | Jul 30 08:28:19 PM PDT 24 |
| Finished | Jul 30 08:28:35 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-e3367920-673f-4b51-9391-548894f09af0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515944283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1515944283 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.2132199155 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 44181606 ps |
| CPU time | 6.5 seconds |
| Started | Jul 30 08:28:09 PM PDT 24 |
| Finished | Jul 30 08:28:15 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-d37c56b0-ebb7-4d57-aa6b-ef89c421b166 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132199155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2132199155 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.811992119 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 7061162808 ps |
| CPU time | 71.51 seconds |
| Started | Jul 30 08:28:12 PM PDT 24 |
| Finished | Jul 30 08:29:24 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-caeaa854-a615-4c87-accb-a21d0e345543 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811992119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.811992119 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.1510157980 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 5164928653 ps |
| CPU time | 91.38 seconds |
| Started | Jul 30 08:28:11 PM PDT 24 |
| Finished | Jul 30 08:29:43 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-781bbd80-38f5-472d-a381-80225a61474e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510157980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1510157980 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.4247504646 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 59601987 ps |
| CPU time | 7.22 seconds |
| Started | Jul 30 08:28:08 PM PDT 24 |
| Finished | Jul 30 08:28:16 PM PDT 24 |
| Peak memory | 573832 kb |
| Host | smart-9131ad79-4ef7-4293-b374-8b717e5d2a04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247504646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays .4247504646 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.2346663764 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 12676263920 ps |
| CPU time | 483.75 seconds |
| Started | Jul 30 08:28:29 PM PDT 24 |
| Finished | Jul 30 08:36:32 PM PDT 24 |
| Peak memory | 576860 kb |
| Host | smart-4f6e9da8-d948-49a1-9ceb-854f5af122c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346663764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2346663764 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.1711284925 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 17642949462 ps |
| CPU time | 727.19 seconds |
| Started | Jul 30 08:28:31 PM PDT 24 |
| Finished | Jul 30 08:40:39 PM PDT 24 |
| Peak memory | 576172 kb |
| Host | smart-9a3e1534-5207-44e6-9cef-e4b8fe23d52c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711284925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1711284925 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2930412382 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 2243197746 ps |
| CPU time | 337.18 seconds |
| Started | Jul 30 08:28:27 PM PDT 24 |
| Finished | Jul 30 08:34:05 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-0efb735d-1195-46e2-9430-0930ab831f78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930412382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.2930412382 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1329305856 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 483618044 ps |
| CPU time | 123.34 seconds |
| Started | Jul 30 08:28:36 PM PDT 24 |
| Finished | Jul 30 08:30:39 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-651f65b6-415e-4112-a352-813c619bade3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329305856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.1329305856 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.3686761929 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 688738925 ps |
| CPU time | 33.64 seconds |
| Started | Jul 30 08:28:54 PM PDT 24 |
| Finished | Jul 30 08:29:28 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-5b1faf6c-d683-4e94-8e31-4c192efe6cce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686761929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3686761929 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.419609474 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 610315308 ps |
| CPU time | 27.19 seconds |
| Started | Jul 30 08:38:55 PM PDT 24 |
| Finished | Jul 30 08:39:22 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-9575e054-66a1-4d99-acda-6b157f8f0148 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419609474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device. 419609474 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.315598317 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 111874848500 ps |
| CPU time | 1951.26 seconds |
| Started | Jul 30 08:38:54 PM PDT 24 |
| Finished | Jul 30 09:11:26 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-7ee5839b-7214-4b10-b50f-1e9c5ae14b75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315598317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_d evice_slow_rsp.315598317 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.1130424716 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 68847366 ps |
| CPU time | 12.37 seconds |
| Started | Jul 30 08:39:02 PM PDT 24 |
| Finished | Jul 30 08:39:14 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-a6681667-0a16-4505-b57e-14e549cc884b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130424716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.1130424716 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.520456735 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 1669609697 ps |
| CPU time | 55.43 seconds |
| Started | Jul 30 08:38:55 PM PDT 24 |
| Finished | Jul 30 08:39:50 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-ea5c5e08-6cd6-4d62-9ac1-f3781d65cbd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520456735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.520456735 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.1244935884 |
| Short name | T2926 |
| Test name | |
| Test status | |
| Simulation time | 192728570 ps |
| CPU time | 21.6 seconds |
| Started | Jul 30 08:38:58 PM PDT 24 |
| Finished | Jul 30 08:39:19 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-03cf58ce-5adb-4ccf-a5fe-70f57fb04169 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244935884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.1244935884 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.2051955498 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 30873970296 ps |
| CPU time | 320.59 seconds |
| Started | Jul 30 08:38:54 PM PDT 24 |
| Finished | Jul 30 08:44:15 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-88e26a4e-a9e8-4125-9768-d6a7a2cd4a62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051955498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2051955498 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.872790591 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 48515693131 ps |
| CPU time | 801.54 seconds |
| Started | Jul 30 08:38:58 PM PDT 24 |
| Finished | Jul 30 08:52:19 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-ec711ff4-c445-4f12-85ee-d2e31b7a35d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872790591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.872790591 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.25058662 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 553216145 ps |
| CPU time | 56.69 seconds |
| Started | Jul 30 08:38:57 PM PDT 24 |
| Finished | Jul 30 08:39:54 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-73ccbcd3-483e-49bb-87ee-659590943a02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25058662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delay s.25058662 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.4241703416 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 294531742 ps |
| CPU time | 26.65 seconds |
| Started | Jul 30 08:38:55 PM PDT 24 |
| Finished | Jul 30 08:39:22 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-10ef309d-d45c-4dfe-994a-c424fbfa07ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241703416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.4241703416 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.3216891092 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 46682279 ps |
| CPU time | 6.64 seconds |
| Started | Jul 30 08:38:52 PM PDT 24 |
| Finished | Jul 30 08:38:59 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-8baec037-7b8d-44a2-bd65-32535d3af0cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216891092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3216891092 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.1769167659 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 5765578383 ps |
| CPU time | 60.06 seconds |
| Started | Jul 30 08:38:55 PM PDT 24 |
| Finished | Jul 30 08:39:55 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-71ff1741-9b26-4cf1-82b6-32285643da80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769167659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1769167659 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.1411345696 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 5080024960 ps |
| CPU time | 96.58 seconds |
| Started | Jul 30 08:38:54 PM PDT 24 |
| Finished | Jul 30 08:40:30 PM PDT 24 |
| Peak memory | 573960 kb |
| Host | smart-da71fcfd-0988-4b7f-a9a9-b3577c3664c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411345696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1411345696 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.4114690959 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 45997738 ps |
| CPU time | 6.92 seconds |
| Started | Jul 30 08:38:52 PM PDT 24 |
| Finished | Jul 30 08:38:59 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-179d96f1-cfd4-4c29-ab43-8ad835694ecd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114690959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.4114690959 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.1965023820 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1157780843 ps |
| CPU time | 114.66 seconds |
| Started | Jul 30 08:39:02 PM PDT 24 |
| Finished | Jul 30 08:40:57 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-23e2dafd-9301-43a7-8160-2f9cee6819de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965023820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1965023820 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.1349863217 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 6022644744 ps |
| CPU time | 238.96 seconds |
| Started | Jul 30 08:39:01 PM PDT 24 |
| Finished | Jul 30 08:43:00 PM PDT 24 |
| Peak memory | 576136 kb |
| Host | smart-35c3c413-6506-48cd-b688-130fff6b08c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349863217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1349863217 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.1497363977 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 19405833696 ps |
| CPU time | 1065.57 seconds |
| Started | Jul 30 08:39:04 PM PDT 24 |
| Finished | Jul 30 08:56:50 PM PDT 24 |
| Peak memory | 576832 kb |
| Host | smart-64317e30-edc6-43b6-b2ae-848d0a86a294 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497363977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_rand_reset.1497363977 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3036962381 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 223150417 ps |
| CPU time | 45.43 seconds |
| Started | Jul 30 08:39:03 PM PDT 24 |
| Finished | Jul 30 08:39:48 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-e553180d-9b2b-41e9-8e1c-d8073e5c3a08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036962381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.3036962381 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.2517535296 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 148302890 ps |
| CPU time | 9.57 seconds |
| Started | Jul 30 08:38:59 PM PDT 24 |
| Finished | Jul 30 08:39:09 PM PDT 24 |
| Peak memory | 574768 kb |
| Host | smart-39241694-3247-4422-b5f6-2408724567e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517535296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2517535296 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.2910473929 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 2562165029 ps |
| CPU time | 117.53 seconds |
| Started | Jul 30 08:39:08 PM PDT 24 |
| Finished | Jul 30 08:41:05 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-b8064fa8-012d-4e80-afad-92d44f571953 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910473929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .2910473929 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.69318754 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 30081595749 ps |
| CPU time | 532.28 seconds |
| Started | Jul 30 08:39:10 PM PDT 24 |
| Finished | Jul 30 08:48:03 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-5a59a6ae-fdf2-4b37-a333-f83b0f08d165 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69318754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_de vice_slow_rsp.69318754 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.1731468031 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 152240382 ps |
| CPU time | 9.61 seconds |
| Started | Jul 30 08:39:09 PM PDT 24 |
| Finished | Jul 30 08:39:19 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-aa8738da-47da-44cf-8015-c24b7b586769 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731468031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.1731468031 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.4224611248 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 307425179 ps |
| CPU time | 12.56 seconds |
| Started | Jul 30 08:39:06 PM PDT 24 |
| Finished | Jul 30 08:39:19 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-ad084584-7ba2-4868-aedd-38615f56b128 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224611248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.4224611248 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.2399730181 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 582308869 ps |
| CPU time | 54.43 seconds |
| Started | Jul 30 08:39:08 PM PDT 24 |
| Finished | Jul 30 08:40:02 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-ccc18dd5-a0dc-49ab-a601-07c03a7bcdff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399730181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.2399730181 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.2645278392 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 88396612869 ps |
| CPU time | 947.08 seconds |
| Started | Jul 30 08:39:07 PM PDT 24 |
| Finished | Jul 30 08:54:55 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-9b86e94e-76fe-44f1-9712-3f83a55f2f00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645278392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2645278392 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.677586216 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 14931274583 ps |
| CPU time | 263.86 seconds |
| Started | Jul 30 08:39:04 PM PDT 24 |
| Finished | Jul 30 08:43:28 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-fefc1aed-6e3b-4a42-80c7-061d35b5a5a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677586216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.677586216 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.1325421892 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 358947589 ps |
| CPU time | 31.66 seconds |
| Started | Jul 30 08:39:11 PM PDT 24 |
| Finished | Jul 30 08:39:43 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-8f073fa4-fae7-4be8-bb11-d85f5368e566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325421892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.1325421892 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.57198397 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 255420068 ps |
| CPU time | 22.39 seconds |
| Started | Jul 30 08:39:07 PM PDT 24 |
| Finished | Jul 30 08:39:29 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-1d1fc0e8-2510-4da7-be7c-47a6d530e0df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57198397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.57198397 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.1425354510 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 219780233 ps |
| CPU time | 9.79 seconds |
| Started | Jul 30 08:39:06 PM PDT 24 |
| Finished | Jul 30 08:39:16 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-50202bf9-a32f-48eb-954b-2aa78aeaa398 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425354510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1425354510 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.728166712 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 8291450731 ps |
| CPU time | 86.36 seconds |
| Started | Jul 30 08:39:07 PM PDT 24 |
| Finished | Jul 30 08:40:33 PM PDT 24 |
| Peak memory | 573948 kb |
| Host | smart-289422d9-7bfd-4b38-9b1d-7545c4decdf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728166712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.728166712 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.1714843846 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 4675992319 ps |
| CPU time | 83.26 seconds |
| Started | Jul 30 08:39:10 PM PDT 24 |
| Finished | Jul 30 08:40:34 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-9414ad31-627a-4590-94a3-536bf7f79f40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714843846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1714843846 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2868397399 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 42857337 ps |
| CPU time | 6.28 seconds |
| Started | Jul 30 08:39:10 PM PDT 24 |
| Finished | Jul 30 08:39:17 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-333b37ad-8e07-44a2-ad5f-78ae03a6376f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868397399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.2868397399 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.3061091662 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 9714071985 ps |
| CPU time | 419.8 seconds |
| Started | Jul 30 08:39:10 PM PDT 24 |
| Finished | Jul 30 08:46:10 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-fdb5bcd3-7e2f-4ef4-b5ab-cc9b42b200cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061091662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3061091662 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.4153097511 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 7844817549 ps |
| CPU time | 271.12 seconds |
| Started | Jul 30 08:39:10 PM PDT 24 |
| Finished | Jul 30 08:43:42 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-2fa3d12c-dc4d-4a4e-a8cd-46aacb168c00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153097511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.4153097511 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.4262581973 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 951644709 ps |
| CPU time | 302.68 seconds |
| Started | Jul 30 08:39:10 PM PDT 24 |
| Finished | Jul 30 08:44:13 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-68677b5f-d3f6-48cf-ba94-5eef22e598da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262581973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.4262581973 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.523844827 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 265014617 ps |
| CPU time | 95.82 seconds |
| Started | Jul 30 08:39:10 PM PDT 24 |
| Finished | Jul 30 08:40:46 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-e59a268a-4199-455b-9d1e-ca4fd42bb5c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523844827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_reset_error.523844827 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.1692356969 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 196554727 ps |
| CPU time | 25 seconds |
| Started | Jul 30 08:39:08 PM PDT 24 |
| Finished | Jul 30 08:39:33 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-0dbafe2e-04f6-4575-8f52-16672ba1b25b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692356969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1692356969 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.83346768 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 2314634815 ps |
| CPU time | 103.97 seconds |
| Started | Jul 30 08:39:24 PM PDT 24 |
| Finished | Jul 30 08:41:08 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-0b432e33-af5d-43d9-8cde-c9d8ceb225c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83346768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.83346768 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.4182305583 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 94556373547 ps |
| CPU time | 1694.74 seconds |
| Started | Jul 30 08:39:17 PM PDT 24 |
| Finished | Jul 30 09:07:32 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-7b09e2eb-342a-436f-9eb5-09c50ef63c8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182305583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_ device_slow_rsp.4182305583 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.2003922641 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 777899737 ps |
| CPU time | 33.24 seconds |
| Started | Jul 30 08:39:25 PM PDT 24 |
| Finished | Jul 30 08:39:58 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-5d474f6f-67b5-4126-bb9e-62d6672ebf50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003922641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.2003922641 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.40532664 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 538521315 ps |
| CPU time | 20.94 seconds |
| Started | Jul 30 08:39:20 PM PDT 24 |
| Finished | Jul 30 08:39:41 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-bd7ff0db-63e2-4938-9f6b-05197046dd9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40532664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.40532664 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.2096199632 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 117069209 ps |
| CPU time | 7.95 seconds |
| Started | Jul 30 08:39:12 PM PDT 24 |
| Finished | Jul 30 08:39:20 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-c7128eb5-4c21-479d-8f8a-abc195712441 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096199632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.2096199632 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.1055293170 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 47464511037 ps |
| CPU time | 501.33 seconds |
| Started | Jul 30 08:39:17 PM PDT 24 |
| Finished | Jul 30 08:47:39 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-ff4a57fc-356a-4e5a-90a0-18138b24b887 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055293170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1055293170 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.823021748 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 23534637449 ps |
| CPU time | 439.42 seconds |
| Started | Jul 30 08:39:16 PM PDT 24 |
| Finished | Jul 30 08:46:35 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-9282adec-7b84-492a-9bf5-c29812cbc027 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823021748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.823021748 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.2365900751 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 623144225 ps |
| CPU time | 57.9 seconds |
| Started | Jul 30 08:39:13 PM PDT 24 |
| Finished | Jul 30 08:40:11 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-86816824-6b6f-4966-960a-2c99453fa8fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365900751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del ays.2365900751 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.336841004 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 1029570022 ps |
| CPU time | 33.5 seconds |
| Started | Jul 30 08:39:20 PM PDT 24 |
| Finished | Jul 30 08:39:54 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-a73f28f9-cb3c-4cfd-9730-2852781b019e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336841004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.336841004 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.2725406597 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 172013645 ps |
| CPU time | 8.9 seconds |
| Started | Jul 30 08:39:10 PM PDT 24 |
| Finished | Jul 30 08:39:19 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-f2bc5d33-218c-4b27-8880-c0e84743d2b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725406597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2725406597 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.1520317931 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 7607965391 ps |
| CPU time | 78.57 seconds |
| Started | Jul 30 08:39:13 PM PDT 24 |
| Finished | Jul 30 08:40:32 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-c3ce6416-b78e-4359-b06d-65676b34aa2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520317931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1520317931 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.3386431468 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 3467592383 ps |
| CPU time | 58.67 seconds |
| Started | Jul 30 08:39:12 PM PDT 24 |
| Finished | Jul 30 08:40:11 PM PDT 24 |
| Peak memory | 573924 kb |
| Host | smart-2394fafe-e87c-4fd3-b54c-9386eeb008e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386431468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3386431468 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.1486007414 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 41819208 ps |
| CPU time | 6.39 seconds |
| Started | Jul 30 08:39:12 PM PDT 24 |
| Finished | Jul 30 08:39:19 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-01dd1a08-f093-442a-a441-1fbff2e94bff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486007414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay s.1486007414 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.3677533111 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 696182884 ps |
| CPU time | 57.01 seconds |
| Started | Jul 30 08:39:28 PM PDT 24 |
| Finished | Jul 30 08:40:25 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-2cd10d43-9532-4ac9-b5c2-a0237ade036e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677533111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3677533111 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.3851332540 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 9678666794 ps |
| CPU time | 366.28 seconds |
| Started | Jul 30 08:39:25 PM PDT 24 |
| Finished | Jul 30 08:45:32 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-4aadb49a-1ead-4e59-9ecd-75d367043ff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851332540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3851332540 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2442471144 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 3595196866 ps |
| CPU time | 412.72 seconds |
| Started | Jul 30 08:39:21 PM PDT 24 |
| Finished | Jul 30 08:46:14 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-0c5d4f5c-30ea-4dff-998a-d3165a88b0ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442471144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.2442471144 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.153188222 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 283199098 ps |
| CPU time | 83.62 seconds |
| Started | Jul 30 08:39:22 PM PDT 24 |
| Finished | Jul 30 08:40:45 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-658291cb-7eea-479f-9e23-bb7a7bc4218d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153188222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_reset_error.153188222 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.11033257 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 279605681 ps |
| CPU time | 33.15 seconds |
| Started | Jul 30 08:39:22 PM PDT 24 |
| Finished | Jul 30 08:39:55 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-336a3297-e379-4952-bf29-1717b7efca9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11033257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.11033257 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.2856169521 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 3439488051 ps |
| CPU time | 143.96 seconds |
| Started | Jul 30 08:39:29 PM PDT 24 |
| Finished | Jul 30 08:41:53 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-27e5294f-7da3-46ff-8e9e-bf76906c1923 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856169521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device .2856169521 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.420971224 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 144649595 ps |
| CPU time | 9.45 seconds |
| Started | Jul 30 08:39:38 PM PDT 24 |
| Finished | Jul 30 08:39:47 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-8c883958-5a82-43bd-aa4c-fc6808de3c7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420971224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr .420971224 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.1927662400 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 376157680 ps |
| CPU time | 34.39 seconds |
| Started | Jul 30 08:39:36 PM PDT 24 |
| Finished | Jul 30 08:40:11 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-b879586f-025a-4577-bde8-dbe622d54d98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927662400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1927662400 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.1610173615 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 267082835 ps |
| CPU time | 28.43 seconds |
| Started | Jul 30 08:39:25 PM PDT 24 |
| Finished | Jul 30 08:39:53 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-361791e7-5d15-4057-ac09-3d0ca567aa74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610173615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.1610173615 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.3232247330 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 53726316086 ps |
| CPU time | 529.45 seconds |
| Started | Jul 30 08:39:27 PM PDT 24 |
| Finished | Jul 30 08:48:16 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-c79fd4ac-bfb5-4b45-9cb1-099153cc6626 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232247330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3232247330 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.12418657 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 26346450314 ps |
| CPU time | 464.28 seconds |
| Started | Jul 30 08:39:37 PM PDT 24 |
| Finished | Jul 30 08:47:21 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-36c80a23-a69a-4d33-bf3e-f22e96688387 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12418657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.12418657 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.3578416892 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 78081137 ps |
| CPU time | 10.67 seconds |
| Started | Jul 30 08:39:23 PM PDT 24 |
| Finished | Jul 30 08:39:34 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-7d9dcc2f-461c-4535-a664-43db2e18a4b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578416892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.3578416892 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.2462587865 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 1636841100 ps |
| CPU time | 48.26 seconds |
| Started | Jul 30 08:39:28 PM PDT 24 |
| Finished | Jul 30 08:40:16 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-a3c4cfc8-fc79-4d3c-a256-bfcba8f2feda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462587865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2462587865 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.1808896645 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 169184482 ps |
| CPU time | 8.49 seconds |
| Started | Jul 30 08:39:28 PM PDT 24 |
| Finished | Jul 30 08:39:37 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-ba97fdcb-0a43-4d94-983e-219341eadc4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808896645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1808896645 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.249564148 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 8678275805 ps |
| CPU time | 95.49 seconds |
| Started | Jul 30 08:39:27 PM PDT 24 |
| Finished | Jul 30 08:41:02 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-f3a32e40-c61c-4dd8-a573-0a70002a4fea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249564148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.249564148 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.1353911832 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 5592982248 ps |
| CPU time | 95.79 seconds |
| Started | Jul 30 08:39:26 PM PDT 24 |
| Finished | Jul 30 08:41:02 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-0c6e26dd-b297-409f-9640-4f73fdd5bd89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353911832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1353911832 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2743150830 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 38149728 ps |
| CPU time | 5.96 seconds |
| Started | Jul 30 08:39:26 PM PDT 24 |
| Finished | Jul 30 08:39:32 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-b5b00839-1fe3-41ea-92fc-cff5111ed47a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743150830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.2743150830 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.4037702957 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 12791639993 ps |
| CPU time | 523.75 seconds |
| Started | Jul 30 08:39:32 PM PDT 24 |
| Finished | Jul 30 08:48:16 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-b76aefd9-f37c-4b1d-8e7b-72e127ceacf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037702957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.4037702957 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.1191458376 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 15531392410 ps |
| CPU time | 614.41 seconds |
| Started | Jul 30 08:39:32 PM PDT 24 |
| Finished | Jul 30 08:49:47 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-db581507-389b-4d9f-93f3-5527b7b96731 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191458376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1191458376 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.3326837305 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 324176284 ps |
| CPU time | 125.37 seconds |
| Started | Jul 30 08:39:32 PM PDT 24 |
| Finished | Jul 30 08:41:38 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-5098a753-1dd9-4055-a994-d6c890cf92c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326837305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.3326837305 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.2058727356 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 423358998 ps |
| CPU time | 153.52 seconds |
| Started | Jul 30 08:39:35 PM PDT 24 |
| Finished | Jul 30 08:42:09 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-1fb673f3-37bd-4b37-bac8-7058e2a9d554 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058727356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.2058727356 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.750253222 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 123340338 ps |
| CPU time | 17.14 seconds |
| Started | Jul 30 08:39:29 PM PDT 24 |
| Finished | Jul 30 08:39:46 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-60a8dfd2-635c-410a-84d5-d833751b93c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750253222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.750253222 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.2577055738 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 182822703 ps |
| CPU time | 23.3 seconds |
| Started | Jul 30 08:39:40 PM PDT 24 |
| Finished | Jul 30 08:40:03 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-28db9a68-1b69-4955-ad00-cc893624e479 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577055738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .2577055738 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.2005960020 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 128916149879 ps |
| CPU time | 2248.08 seconds |
| Started | Jul 30 08:39:40 PM PDT 24 |
| Finished | Jul 30 09:17:08 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-d5ee1141-daed-4a5f-9f00-ee6dae730601 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005960020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.2005960020 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.4292354474 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 954237862 ps |
| CPU time | 37.63 seconds |
| Started | Jul 30 08:39:41 PM PDT 24 |
| Finished | Jul 30 08:40:18 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-836cd1a8-a48d-4a86-9136-ed6e60a43f2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292354474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.4292354474 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.3777008597 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 244205794 ps |
| CPU time | 25.08 seconds |
| Started | Jul 30 08:39:42 PM PDT 24 |
| Finished | Jul 30 08:40:07 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-8e627f2a-b2b0-4b95-abe4-9a9413e8e6d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777008597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3777008597 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.1453579453 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 1709388895 ps |
| CPU time | 62.6 seconds |
| Started | Jul 30 08:39:35 PM PDT 24 |
| Finished | Jul 30 08:40:38 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-7fe2b1ea-a156-40e9-81c4-a200a04ccdde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453579453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.1453579453 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.452718989 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 5378508804 ps |
| CPU time | 61.55 seconds |
| Started | Jul 30 08:39:41 PM PDT 24 |
| Finished | Jul 30 08:40:43 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-03a06521-95a7-47c8-923c-0e4e84a643a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452718989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.452718989 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.2401349478 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 65134141672 ps |
| CPU time | 1085.13 seconds |
| Started | Jul 30 08:39:43 PM PDT 24 |
| Finished | Jul 30 08:57:48 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-8d7b9328-5711-4f0f-8c59-2a1c25172da8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401349478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2401349478 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.1862987000 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 126953342 ps |
| CPU time | 15.03 seconds |
| Started | Jul 30 08:39:43 PM PDT 24 |
| Finished | Jul 30 08:39:58 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-64d0fb2a-e425-4844-8e21-8dd069820aad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862987000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.1862987000 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.3166501636 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 302094160 ps |
| CPU time | 28 seconds |
| Started | Jul 30 08:39:39 PM PDT 24 |
| Finished | Jul 30 08:40:07 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-c9f962e2-e588-45b5-bf77-f4514db9b8b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166501636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3166501636 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.3312611994 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 202284045 ps |
| CPU time | 9.76 seconds |
| Started | Jul 30 08:39:32 PM PDT 24 |
| Finished | Jul 30 08:39:42 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-f532db79-4225-49da-ba0f-4866a42d035b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312611994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3312611994 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.1907468561 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 8980133520 ps |
| CPU time | 92.01 seconds |
| Started | Jul 30 08:39:39 PM PDT 24 |
| Finished | Jul 30 08:41:11 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-df3dccdf-b1f9-42a6-95a7-596287342c22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907468561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1907468561 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.113395781 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 5174495882 ps |
| CPU time | 92.53 seconds |
| Started | Jul 30 08:39:36 PM PDT 24 |
| Finished | Jul 30 08:41:08 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-1974aa04-53b4-4a92-9041-0b78841c9faa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113395781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.113395781 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.2530240029 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 57578415 ps |
| CPU time | 7.14 seconds |
| Started | Jul 30 08:39:32 PM PDT 24 |
| Finished | Jul 30 08:39:40 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-a35816f1-2b0f-4c6b-8453-6721fc8dd243 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530240029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.2530240029 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.1371702874 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 8833048836 ps |
| CPU time | 337.65 seconds |
| Started | Jul 30 08:39:44 PM PDT 24 |
| Finished | Jul 30 08:45:22 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-c6e39ca6-6e9c-4060-bd55-519c19fcfaa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371702874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1371702874 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.1694775982 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 4759086463 ps |
| CPU time | 275.23 seconds |
| Started | Jul 30 08:39:45 PM PDT 24 |
| Finished | Jul 30 08:44:20 PM PDT 24 |
| Peak memory | 576872 kb |
| Host | smart-e147160b-4bba-47be-8e09-b512bd81a12a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694775982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.1694775982 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.3781932309 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 23734568 ps |
| CPU time | 6.02 seconds |
| Started | Jul 30 08:39:41 PM PDT 24 |
| Finished | Jul 30 08:39:47 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-8e45c9ea-2148-4af0-ac86-0fb2ff1b310d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781932309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3781932309 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.3290099833 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 409316396 ps |
| CPU time | 33.82 seconds |
| Started | Jul 30 08:39:52 PM PDT 24 |
| Finished | Jul 30 08:40:26 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-71df203d-c1f1-4278-8317-815ffd3ef247 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290099833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .3290099833 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.826984370 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 114786941189 ps |
| CPU time | 2035.78 seconds |
| Started | Jul 30 08:39:54 PM PDT 24 |
| Finished | Jul 30 09:13:50 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-28f84da3-f376-4ad8-86db-707418771574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826984370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_d evice_slow_rsp.826984370 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2445804975 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 153835818 ps |
| CPU time | 19.15 seconds |
| Started | Jul 30 08:39:56 PM PDT 24 |
| Finished | Jul 30 08:40:15 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-22f14128-58bd-4b4f-a2e8-1ad166214a61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445804975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.2445804975 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.2399169551 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 1169212565 ps |
| CPU time | 38.03 seconds |
| Started | Jul 30 08:39:52 PM PDT 24 |
| Finished | Jul 30 08:40:30 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-7b3e6704-ae82-448d-81b3-ecd75e51d05c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399169551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2399169551 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.684129113 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 421564125 ps |
| CPU time | 37.81 seconds |
| Started | Jul 30 08:39:52 PM PDT 24 |
| Finished | Jul 30 08:40:30 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-f71272a4-c2b1-49a4-8ef6-1b396be2e6a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684129113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.684129113 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.118493194 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 9418755706 ps |
| CPU time | 100.93 seconds |
| Started | Jul 30 08:39:54 PM PDT 24 |
| Finished | Jul 30 08:41:35 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-cfb1b011-3ff8-4a45-b1c0-fbe41ca09160 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118493194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.118493194 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.1461587217 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 59418223129 ps |
| CPU time | 1028.86 seconds |
| Started | Jul 30 08:39:55 PM PDT 24 |
| Finished | Jul 30 08:57:04 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-0f6b603f-e076-4cdb-a712-2e2e30965c57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461587217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1461587217 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.837499598 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 372600110 ps |
| CPU time | 37.55 seconds |
| Started | Jul 30 08:39:54 PM PDT 24 |
| Finished | Jul 30 08:40:31 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-32a494b9-7f9d-4c2c-b97a-bb828c29cc17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837499598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_dela ys.837499598 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.3539440101 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 420697190 ps |
| CPU time | 31.76 seconds |
| Started | Jul 30 08:39:52 PM PDT 24 |
| Finished | Jul 30 08:40:24 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-6b2ef88b-9671-4287-a581-630253507770 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539440101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3539440101 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.3029281061 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 214061402 ps |
| CPU time | 10.39 seconds |
| Started | Jul 30 08:39:44 PM PDT 24 |
| Finished | Jul 30 08:39:55 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-0a2fdd66-1969-44db-b255-20ccf8c5c7a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029281061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3029281061 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.191501291 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 7378008934 ps |
| CPU time | 77.28 seconds |
| Started | Jul 30 08:39:49 PM PDT 24 |
| Finished | Jul 30 08:41:07 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-586d58de-229f-4738-9921-98dab7e55d2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191501291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.191501291 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.2478946584 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 5152962780 ps |
| CPU time | 98.61 seconds |
| Started | Jul 30 08:39:51 PM PDT 24 |
| Finished | Jul 30 08:41:30 PM PDT 24 |
| Peak memory | 574660 kb |
| Host | smart-7c1b8ce0-5f0f-4e9a-ba7e-164d33ce3902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478946584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.2478946584 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.555123977 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 58659510 ps |
| CPU time | 7.5 seconds |
| Started | Jul 30 08:39:44 PM PDT 24 |
| Finished | Jul 30 08:39:52 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-e3f33e12-ac5d-44a7-b5c6-b6e778f86ea3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555123977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays .555123977 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.2032486601 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 1096077057 ps |
| CPU time | 81.26 seconds |
| Started | Jul 30 08:39:58 PM PDT 24 |
| Finished | Jul 30 08:41:19 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-e37bbf4a-121d-4957-9761-51b15dfc3ab2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032486601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.2032486601 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.2064997775 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 824959349 ps |
| CPU time | 68.35 seconds |
| Started | Jul 30 08:39:56 PM PDT 24 |
| Finished | Jul 30 08:41:04 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-3291e78d-d762-4180-b811-6438f45286c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064997775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2064997775 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.3373834354 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 2663647158 ps |
| CPU time | 360.38 seconds |
| Started | Jul 30 08:40:01 PM PDT 24 |
| Finished | Jul 30 08:46:01 PM PDT 24 |
| Peak memory | 576856 kb |
| Host | smart-7ba7086e-2e0f-4096-a636-aa87838805e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373834354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.3373834354 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.1126676355 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 231991758 ps |
| CPU time | 30.04 seconds |
| Started | Jul 30 08:39:53 PM PDT 24 |
| Finished | Jul 30 08:40:23 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-90078639-cd9e-4433-8a8b-c32ffc1dc714 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126676355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1126676355 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.2974147984 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 106389058255 ps |
| CPU time | 1745.37 seconds |
| Started | Jul 30 08:40:04 PM PDT 24 |
| Finished | Jul 30 09:09:09 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-f7a3cdab-7a7c-4fcd-ba6a-b7a90ab09af6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974147984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.2974147984 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.1811501678 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 370130074 ps |
| CPU time | 37.87 seconds |
| Started | Jul 30 08:40:10 PM PDT 24 |
| Finished | Jul 30 08:40:48 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-6f2a9378-6a95-44b3-9443-3653f3264d73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811501678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.1811501678 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.786789509 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 2248345203 ps |
| CPU time | 76.22 seconds |
| Started | Jul 30 08:40:05 PM PDT 24 |
| Finished | Jul 30 08:41:21 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-880e653d-8e47-4145-b7b6-681a00b942c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786789509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.786789509 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.683692217 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 297503442 ps |
| CPU time | 13.75 seconds |
| Started | Jul 30 08:40:02 PM PDT 24 |
| Finished | Jul 30 08:40:16 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-8bfee91b-7f7a-4bc8-9bbf-bca7438d5dc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683692217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.683692217 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.992838002 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 75917269226 ps |
| CPU time | 845.74 seconds |
| Started | Jul 30 08:40:04 PM PDT 24 |
| Finished | Jul 30 08:54:10 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-03faba47-12a0-4172-8d41-40c7e7270d4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992838002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.992838002 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.1268832094 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 29245154651 ps |
| CPU time | 523.22 seconds |
| Started | Jul 30 08:40:06 PM PDT 24 |
| Finished | Jul 30 08:48:49 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-dadb5012-8c4a-4ed3-8d88-fcd1ab9d208b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268832094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1268832094 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.348163746 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 40564992 ps |
| CPU time | 6.96 seconds |
| Started | Jul 30 08:40:00 PM PDT 24 |
| Finished | Jul 30 08:40:07 PM PDT 24 |
| Peak memory | 573864 kb |
| Host | smart-69863713-cf5d-4b8f-b0fc-90f2595852d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348163746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_dela ys.348163746 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.3868332342 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 278358596 ps |
| CPU time | 21.56 seconds |
| Started | Jul 30 08:40:04 PM PDT 24 |
| Finished | Jul 30 08:40:26 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-36ad93df-ebbb-486b-a701-ad585b2ae0b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868332342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3868332342 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.333997638 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 36884448 ps |
| CPU time | 6.11 seconds |
| Started | Jul 30 08:40:01 PM PDT 24 |
| Finished | Jul 30 08:40:07 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-d752f4c5-61c1-492b-a3fc-6d9f5ee0192a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333997638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.333997638 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.3889180888 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 6278757002 ps |
| CPU time | 71.24 seconds |
| Started | Jul 30 08:40:02 PM PDT 24 |
| Finished | Jul 30 08:41:13 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-72e48842-b853-49a0-b2fd-8673c3ac1e02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889180888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3889180888 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.218544593 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 5464406603 ps |
| CPU time | 101.43 seconds |
| Started | Jul 30 08:40:00 PM PDT 24 |
| Finished | Jul 30 08:41:41 PM PDT 24 |
| Peak memory | 573968 kb |
| Host | smart-d2c920f0-136f-4664-8750-7153779edfcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218544593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.218544593 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.2084908120 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 51155574 ps |
| CPU time | 6.75 seconds |
| Started | Jul 30 08:40:01 PM PDT 24 |
| Finished | Jul 30 08:40:08 PM PDT 24 |
| Peak memory | 573804 kb |
| Host | smart-149c7621-8742-430f-a7a4-5d81ad797212 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084908120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.2084908120 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.1403478702 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 8052147776 ps |
| CPU time | 360.84 seconds |
| Started | Jul 30 08:40:11 PM PDT 24 |
| Finished | Jul 30 08:46:12 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-200baa82-9d99-4b85-b351-8788fde35bb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403478702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1403478702 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.2126968728 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 4492619161 ps |
| CPU time | 184.07 seconds |
| Started | Jul 30 08:40:11 PM PDT 24 |
| Finished | Jul 30 08:43:15 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-71fa8ad7-3842-464a-bfa1-310c4d46e28a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126968728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2126968728 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.216100868 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 9348980570 ps |
| CPU time | 441.45 seconds |
| Started | Jul 30 08:40:10 PM PDT 24 |
| Finished | Jul 30 08:47:32 PM PDT 24 |
| Peak memory | 577000 kb |
| Host | smart-f15c5500-a811-4dd1-a653-a7088b08911c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216100868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_ with_rand_reset.216100868 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.3358490380 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 204663929 ps |
| CPU time | 50.07 seconds |
| Started | Jul 30 08:40:11 PM PDT 24 |
| Finished | Jul 30 08:41:01 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-525f09a6-b7b8-4a5f-8c41-7a1b9de5859a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358490380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.3358490380 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.3101397474 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 500874026 ps |
| CPU time | 25.06 seconds |
| Started | Jul 30 08:40:11 PM PDT 24 |
| Finished | Jul 30 08:40:37 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-7971bd5e-af0a-4ec9-901d-c8000e9106bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101397474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3101397474 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.600477472 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 1840672922 ps |
| CPU time | 69.72 seconds |
| Started | Jul 30 08:40:20 PM PDT 24 |
| Finished | Jul 30 08:41:30 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-4a953948-5800-47fa-8e3d-140d55d25f6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600477472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device. 600477472 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.1716305550 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 41826526682 ps |
| CPU time | 774.86 seconds |
| Started | Jul 30 08:40:21 PM PDT 24 |
| Finished | Jul 30 08:53:16 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-3d5f7d70-8ad3-45c7-a0ce-39aade651ad2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716305550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.1716305550 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.34036165 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 86422182 ps |
| CPU time | 6.77 seconds |
| Started | Jul 30 08:40:15 PM PDT 24 |
| Finished | Jul 30 08:40:22 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-8248773b-3672-43b9-8402-b221e31de710 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34036165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.34036165 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.3164570365 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1124370038 ps |
| CPU time | 43.12 seconds |
| Started | Jul 30 08:40:21 PM PDT 24 |
| Finished | Jul 30 08:41:04 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-56fc4ada-ab3d-4346-8897-43810a6bebda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164570365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3164570365 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.1036250350 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 36607832 ps |
| CPU time | 6.4 seconds |
| Started | Jul 30 08:40:17 PM PDT 24 |
| Finished | Jul 30 08:40:24 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-878eee98-bf74-4b5c-ab1e-8019d6d6f40e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036250350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.1036250350 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.115290792 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 18737067306 ps |
| CPU time | 208.75 seconds |
| Started | Jul 30 08:40:21 PM PDT 24 |
| Finished | Jul 30 08:43:50 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-499e7df1-816a-4fd9-9d1a-0c28144d433a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115290792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.115290792 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.2486899484 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 39019514367 ps |
| CPU time | 686.22 seconds |
| Started | Jul 30 08:40:12 PM PDT 24 |
| Finished | Jul 30 08:51:39 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-aa5c79a9-8939-425a-ad36-d55df78a7ef2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486899484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2486899484 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.406526001 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 341571917 ps |
| CPU time | 29.02 seconds |
| Started | Jul 30 08:40:18 PM PDT 24 |
| Finished | Jul 30 08:40:47 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-5fbd035b-bc28-4ec4-a00c-38d2cde4317c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406526001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_dela ys.406526001 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.3393889382 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 307552546 ps |
| CPU time | 25.68 seconds |
| Started | Jul 30 08:40:12 PM PDT 24 |
| Finished | Jul 30 08:40:38 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-fff4f6ce-c621-4561-bf08-e2b18e338dea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393889382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3393889382 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.2130863363 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 42743848 ps |
| CPU time | 6.38 seconds |
| Started | Jul 30 08:40:12 PM PDT 24 |
| Finished | Jul 30 08:40:19 PM PDT 24 |
| Peak memory | 573832 kb |
| Host | smart-2cb6c831-fc1d-4030-ada5-e08140fb142a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130863363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2130863363 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.525113405 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 9656901295 ps |
| CPU time | 105.41 seconds |
| Started | Jul 30 08:40:13 PM PDT 24 |
| Finished | Jul 30 08:41:59 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-c4dc6b6b-b0b0-4a5b-96a9-a9fe01cfed2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525113405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.525113405 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1531752575 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 6293118196 ps |
| CPU time | 103.33 seconds |
| Started | Jul 30 08:40:17 PM PDT 24 |
| Finished | Jul 30 08:42:00 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-a341061a-f987-4270-93f4-07c028efc3ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531752575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1531752575 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.3094074214 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 43366213 ps |
| CPU time | 6.46 seconds |
| Started | Jul 30 08:40:09 PM PDT 24 |
| Finished | Jul 30 08:40:15 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-ef5147e7-80f4-4ed9-bcf1-ddd667101e81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094074214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.3094074214 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.1156999753 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 16442180718 ps |
| CPU time | 665.85 seconds |
| Started | Jul 30 08:40:18 PM PDT 24 |
| Finished | Jul 30 08:51:24 PM PDT 24 |
| Peak memory | 576860 kb |
| Host | smart-c0b7dfe1-cde1-4052-9e57-99b741b66281 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156999753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1156999753 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.2789572321 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 3268077178 ps |
| CPU time | 111.52 seconds |
| Started | Jul 30 08:40:19 PM PDT 24 |
| Finished | Jul 30 08:42:11 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-35fd7a95-e8cb-491b-b845-1516874dd8e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789572321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2789572321 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.687001382 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 6514297695 ps |
| CPU time | 363.38 seconds |
| Started | Jul 30 08:40:17 PM PDT 24 |
| Finished | Jul 30 08:46:20 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-3e9bb2e1-9140-43a6-a64e-f84f747e4195 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687001382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_ with_rand_reset.687001382 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.979197186 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 318825419 ps |
| CPU time | 46.13 seconds |
| Started | Jul 30 08:40:14 PM PDT 24 |
| Finished | Jul 30 08:41:01 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-573fbdc4-05cf-4067-9f28-cde7d75e90e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979197186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.979197186 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.1016734600 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 998381107 ps |
| CPU time | 69.35 seconds |
| Started | Jul 30 08:40:22 PM PDT 24 |
| Finished | Jul 30 08:41:31 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-42d8160c-147b-4d8e-bf2c-eef8a74d0aec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016734600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .1016734600 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.3469288395 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 81945256619 ps |
| CPU time | 1503.06 seconds |
| Started | Jul 30 08:40:21 PM PDT 24 |
| Finished | Jul 30 09:05:24 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-1525ab46-4725-4433-b0ea-a316baeef2f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469288395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.3469288395 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.2183745279 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 224985261 ps |
| CPU time | 24.2 seconds |
| Started | Jul 30 08:40:24 PM PDT 24 |
| Finished | Jul 30 08:40:48 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-b9be51b6-3799-48e3-9a2a-e653322d9a8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183745279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.2183745279 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.611879998 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 2336394211 ps |
| CPU time | 80.42 seconds |
| Started | Jul 30 08:40:29 PM PDT 24 |
| Finished | Jul 30 08:41:50 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-00a002d7-137e-4052-9476-908bac2947a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611879998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.611879998 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.3730374464 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 350022403 ps |
| CPU time | 39.15 seconds |
| Started | Jul 30 08:40:20 PM PDT 24 |
| Finished | Jul 30 08:40:59 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-a8d1dbf9-a8fe-4915-aee5-77e7b4af1320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730374464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.3730374464 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.291793679 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 55967855158 ps |
| CPU time | 602.65 seconds |
| Started | Jul 30 08:40:21 PM PDT 24 |
| Finished | Jul 30 08:50:24 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-afba60ee-5dcb-4c51-ad2d-c194eaa9fc53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291793679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.291793679 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.93318287 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 30525492551 ps |
| CPU time | 509.26 seconds |
| Started | Jul 30 08:40:23 PM PDT 24 |
| Finished | Jul 30 08:48:52 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-3a89e971-aec4-43db-af90-210e50682068 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93318287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.93318287 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.639257846 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 311727522 ps |
| CPU time | 32.35 seconds |
| Started | Jul 30 08:40:22 PM PDT 24 |
| Finished | Jul 30 08:40:54 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-9e415109-7032-49fa-a57c-e8d55a769a22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639257846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_dela ys.639257846 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.1142171263 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 549405829 ps |
| CPU time | 18.22 seconds |
| Started | Jul 30 08:40:23 PM PDT 24 |
| Finished | Jul 30 08:40:42 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-e0230248-fa19-44b2-88eb-5d9a4362c04b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142171263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1142171263 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.62736154 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 150934625 ps |
| CPU time | 8.34 seconds |
| Started | Jul 30 08:40:21 PM PDT 24 |
| Finished | Jul 30 08:40:30 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-8ebd2f2a-16c1-43b3-a66d-d1510b03f743 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62736154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.62736154 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.3429707047 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 8482760431 ps |
| CPU time | 89.82 seconds |
| Started | Jul 30 08:40:18 PM PDT 24 |
| Finished | Jul 30 08:41:48 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-657229df-87e6-4a5e-8c13-799501a6c110 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429707047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3429707047 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3975946972 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 5487185790 ps |
| CPU time | 97.21 seconds |
| Started | Jul 30 08:40:17 PM PDT 24 |
| Finished | Jul 30 08:41:54 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-c8631919-6557-4ae8-a19f-a228dfde01e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975946972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3975946972 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.2173584564 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 54519424 ps |
| CPU time | 6.94 seconds |
| Started | Jul 30 08:40:21 PM PDT 24 |
| Finished | Jul 30 08:40:28 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-b768aa35-aed0-40d1-ae34-50bdf75629c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173584564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay s.2173584564 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.3251966841 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 3793445511 ps |
| CPU time | 140.46 seconds |
| Started | Jul 30 08:40:25 PM PDT 24 |
| Finished | Jul 30 08:42:46 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-84d6b2cc-cbab-4396-a93b-e946cd6f0f47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251966841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3251966841 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.687050171 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 1412946935 ps |
| CPU time | 125.49 seconds |
| Started | Jul 30 08:40:28 PM PDT 24 |
| Finished | Jul 30 08:42:34 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-32aa28d0-83a2-4c27-915e-34438a3da2c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687050171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.687050171 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.2523365640 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 137167552 ps |
| CPU time | 45.88 seconds |
| Started | Jul 30 08:40:27 PM PDT 24 |
| Finished | Jul 30 08:41:13 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-9b4aea95-5a66-49cd-99f1-c740b645c964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523365640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.2523365640 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.1016176315 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 544804856 ps |
| CPU time | 26.15 seconds |
| Started | Jul 30 08:40:27 PM PDT 24 |
| Finished | Jul 30 08:40:53 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-92e785a7-de4f-4cb2-a51e-f0ffc070c14f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016176315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1016176315 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.3863248610 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 4073418261 ps |
| CPU time | 162.79 seconds |
| Started | Jul 30 08:40:32 PM PDT 24 |
| Finished | Jul 30 08:43:15 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-6eefbe49-2838-4474-9b00-de7a0fe0d9f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863248610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .3863248610 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.1529174841 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 59191114468 ps |
| CPU time | 1079.39 seconds |
| Started | Jul 30 08:40:34 PM PDT 24 |
| Finished | Jul 30 08:58:33 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-575dc2e3-227f-47a5-97e7-4d5b2690388f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529174841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.1529174841 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.4157932621 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 873553060 ps |
| CPU time | 40.05 seconds |
| Started | Jul 30 08:40:37 PM PDT 24 |
| Finished | Jul 30 08:41:17 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-74111356-3bd0-4f6c-8d66-537f174ba55c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157932621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.4157932621 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.3759231951 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 432455566 ps |
| CPU time | 36.68 seconds |
| Started | Jul 30 08:40:32 PM PDT 24 |
| Finished | Jul 30 08:41:09 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-477f9b13-a7eb-4664-8c95-473ee7b4cc82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759231951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3759231951 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.3475855825 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 500097593 ps |
| CPU time | 44.16 seconds |
| Started | Jul 30 08:40:27 PM PDT 24 |
| Finished | Jul 30 08:41:11 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-06630299-2e41-4374-95ed-64d8ad5a2dc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475855825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.3475855825 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.2233421706 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 15195826234 ps |
| CPU time | 158.41 seconds |
| Started | Jul 30 08:40:36 PM PDT 24 |
| Finished | Jul 30 08:43:14 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-c8a7e34a-b20f-41f2-99a4-b1bd180d7add |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233421706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2233421706 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.2862322989 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 14748913930 ps |
| CPU time | 261.38 seconds |
| Started | Jul 30 08:40:32 PM PDT 24 |
| Finished | Jul 30 08:44:54 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-b5faebc0-014a-4dfd-8934-e7ef4fed014b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862322989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2862322989 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.392703515 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 470164897 ps |
| CPU time | 46.85 seconds |
| Started | Jul 30 08:40:29 PM PDT 24 |
| Finished | Jul 30 08:41:16 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-efc5f3e6-a245-453f-affc-67d89b3092f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392703515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_dela ys.392703515 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.2812897194 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 2201676427 ps |
| CPU time | 73.36 seconds |
| Started | Jul 30 08:40:31 PM PDT 24 |
| Finished | Jul 30 08:41:45 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-4fce4c84-969f-41c6-91a6-5c986d1c0daa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812897194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2812897194 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.1212854358 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 190395283 ps |
| CPU time | 9.51 seconds |
| Started | Jul 30 08:40:30 PM PDT 24 |
| Finished | Jul 30 08:40:39 PM PDT 24 |
| Peak memory | 573828 kb |
| Host | smart-a0f6c349-b822-4b6f-8f57-e97b39e5db71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212854358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1212854358 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.2134992872 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 9479109577 ps |
| CPU time | 102.39 seconds |
| Started | Jul 30 08:40:29 PM PDT 24 |
| Finished | Jul 30 08:42:11 PM PDT 24 |
| Peak memory | 573964 kb |
| Host | smart-0b8412ba-bbdb-43a4-bce1-96fdd313948d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134992872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2134992872 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.2108542160 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 2951806125 ps |
| CPU time | 53.05 seconds |
| Started | Jul 30 08:40:31 PM PDT 24 |
| Finished | Jul 30 08:41:24 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-788abe79-07d9-48f4-9d3f-5eb0d55fab7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108542160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2108542160 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.1669684285 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 49792207 ps |
| CPU time | 6.72 seconds |
| Started | Jul 30 08:40:29 PM PDT 24 |
| Finished | Jul 30 08:40:36 PM PDT 24 |
| Peak memory | 573876 kb |
| Host | smart-efcf3efd-6378-4705-8035-a28ed2c7637a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669684285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.1669684285 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.2601111009 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 8549769035 ps |
| CPU time | 326.37 seconds |
| Started | Jul 30 08:40:37 PM PDT 24 |
| Finished | Jul 30 08:46:03 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-c8d30904-48cd-4bd3-8e4c-fe0b8782118a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601111009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2601111009 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.3189329600 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 1080009945 ps |
| CPU time | 107.63 seconds |
| Started | Jul 30 08:40:37 PM PDT 24 |
| Finished | Jul 30 08:42:24 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-59f5f0e8-ed21-47df-9cd0-f25316418eec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189329600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3189329600 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.2878299998 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 152644423 ps |
| CPU time | 87.06 seconds |
| Started | Jul 30 08:40:36 PM PDT 24 |
| Finished | Jul 30 08:42:03 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-23b69169-bc16-4d13-a486-4452c8d1f96f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878299998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_rand_reset.2878299998 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2652258908 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 47067771 ps |
| CPU time | 21.91 seconds |
| Started | Jul 30 08:40:37 PM PDT 24 |
| Finished | Jul 30 08:40:59 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-1d531ea2-2ca8-45a7-bf8b-9970986c422e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652258908 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.2652258908 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.3415672271 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 1174738118 ps |
| CPU time | 51.98 seconds |
| Started | Jul 30 08:40:36 PM PDT 24 |
| Finished | Jul 30 08:41:28 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-3af16ab5-e412-47c5-8aa4-c82abf01ad31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415672271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3415672271 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.4150063472 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 11991765937 ps |
| CPU time | 1085.73 seconds |
| Started | Jul 30 08:29:04 PM PDT 24 |
| Finished | Jul 30 08:47:10 PM PDT 24 |
| Peak memory | 653116 kb |
| Host | smart-0b4160b5-c443-4711-8fbf-f57256b645ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150063472 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.4150063472 |
| Directory | /workspace/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.1732585002 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 3785238076 ps |
| CPU time | 305.65 seconds |
| Started | Jul 30 08:29:06 PM PDT 24 |
| Finished | Jul 30 08:34:11 PM PDT 24 |
| Peak memory | 598352 kb |
| Host | smart-13d81326-1ebd-4ac6-bc74-9b6fb8e62a26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732585002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.1732585002 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.3095680447 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 15614150110 ps |
| CPU time | 2092.01 seconds |
| Started | Jul 30 08:28:47 PM PDT 24 |
| Finished | Jul 30 09:03:40 PM PDT 24 |
| Peak memory | 593240 kb |
| Host | smart-a61bf3e4-54a1-41a8-9391-8c48b3677acc |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095680447 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.3095680447 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.1940677861 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 780682810 ps |
| CPU time | 43.74 seconds |
| Started | Jul 30 08:28:53 PM PDT 24 |
| Finished | Jul 30 08:29:37 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-1fe34d71-4c83-4c3b-b21d-5bb298eba73c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940677861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 1940677861 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.2260546794 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 49556946585 ps |
| CPU time | 866.75 seconds |
| Started | Jul 30 08:28:51 PM PDT 24 |
| Finished | Jul 30 08:43:17 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-2e620375-2f77-47f2-be76-55fe0a8e0502 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260546794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d evice_slow_rsp.2260546794 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1171981829 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 54636976 ps |
| CPU time | 9.58 seconds |
| Started | Jul 30 08:28:58 PM PDT 24 |
| Finished | Jul 30 08:29:07 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-ccb2d278-97a2-430c-a20c-145161004a76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171981829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .1171981829 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.2800887749 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 1910362323 ps |
| CPU time | 69.38 seconds |
| Started | Jul 30 08:28:58 PM PDT 24 |
| Finished | Jul 30 08:30:08 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-48a00181-bea4-47ba-84e1-55bdc2711bb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800887749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2800887749 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.3941306611 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 229316019 ps |
| CPU time | 11.55 seconds |
| Started | Jul 30 08:28:46 PM PDT 24 |
| Finished | Jul 30 08:28:57 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-bbe99915-1eba-45aa-b6b8-1f79d08a5b98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941306611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.3941306611 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.2783934189 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 51543561220 ps |
| CPU time | 529.62 seconds |
| Started | Jul 30 08:28:51 PM PDT 24 |
| Finished | Jul 30 08:37:41 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-98aebf29-90a5-4939-9d69-05f584a1ed81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783934189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2783934189 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.2811780148 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 53047646040 ps |
| CPU time | 919.72 seconds |
| Started | Jul 30 08:28:52 PM PDT 24 |
| Finished | Jul 30 08:44:12 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-96c389e8-6055-4153-83ce-bc9ccf6211a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811780148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2811780148 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.2359661580 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 60304370 ps |
| CPU time | 9.4 seconds |
| Started | Jul 30 08:28:52 PM PDT 24 |
| Finished | Jul 30 08:29:01 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-6706d31a-2067-431f-806f-4180dd1e26db |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359661580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.2359661580 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.4008899719 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 487038967 ps |
| CPU time | 39.1 seconds |
| Started | Jul 30 08:28:53 PM PDT 24 |
| Finished | Jul 30 08:29:33 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-787ca723-c540-410b-b916-3c4e130bf1e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008899719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.4008899719 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.2687538693 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 46947690 ps |
| CPU time | 6.81 seconds |
| Started | Jul 30 08:28:49 PM PDT 24 |
| Finished | Jul 30 08:28:56 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-a653b325-aa9f-4adc-898f-e8205bca96a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687538693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2687538693 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.2644166138 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 9295184134 ps |
| CPU time | 102.46 seconds |
| Started | Jul 30 08:28:51 PM PDT 24 |
| Finished | Jul 30 08:30:33 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-8b8f25cd-d25c-4850-8a6a-078afdd9c682 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644166138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2644166138 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1920577049 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 4934060278 ps |
| CPU time | 82.7 seconds |
| Started | Jul 30 08:28:45 PM PDT 24 |
| Finished | Jul 30 08:30:08 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-e18320b8-cbc7-430c-bd60-edfa906044bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920577049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1920577049 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.4071980398 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 44986223 ps |
| CPU time | 6.27 seconds |
| Started | Jul 30 08:28:47 PM PDT 24 |
| Finished | Jul 30 08:28:53 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-125eb8b1-7dca-44c3-9b01-2153a5ae35f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071980398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .4071980398 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.3736693743 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 8794619308 ps |
| CPU time | 415.3 seconds |
| Started | Jul 30 08:28:58 PM PDT 24 |
| Finished | Jul 30 08:35:53 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-9b04af1f-07c1-441a-b354-4b3555923b71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736693743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3736693743 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.3833423139 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 14442788440 ps |
| CPU time | 572.97 seconds |
| Started | Jul 30 08:29:02 PM PDT 24 |
| Finished | Jul 30 08:38:35 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-13257249-b3f5-48be-963b-a0267e6f8c21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833423139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3833423139 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.552201984 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 135274760 ps |
| CPU time | 50.8 seconds |
| Started | Jul 30 08:29:00 PM PDT 24 |
| Finished | Jul 30 08:29:51 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-ecbc6fd0-4d88-4a6c-8f64-a0255b2e2d78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552201984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_w ith_rand_reset.552201984 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1474447509 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 230766470 ps |
| CPU time | 72.55 seconds |
| Started | Jul 30 08:29:03 PM PDT 24 |
| Finished | Jul 30 08:30:15 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-3bbbac92-7119-4c6c-9dde-cdb5f0336282 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474447509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.1474447509 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.2968255293 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 783748796 ps |
| CPU time | 35.52 seconds |
| Started | Jul 30 08:28:56 PM PDT 24 |
| Finished | Jul 30 08:29:32 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-85364604-d45f-4e08-9660-f73a5beffcf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968255293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2968255293 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.1859915604 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 852266576 ps |
| CPU time | 39.88 seconds |
| Started | Jul 30 08:40:44 PM PDT 24 |
| Finished | Jul 30 08:41:24 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-6e970aad-e3f4-4b28-a423-f656f5b3388f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859915604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .1859915604 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.2130887742 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 99358698187 ps |
| CPU time | 1694.12 seconds |
| Started | Jul 30 08:40:44 PM PDT 24 |
| Finished | Jul 30 09:08:58 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-c8e37d69-35eb-4d8f-bab7-5b958ae93eaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130887742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.2130887742 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.1605366877 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 153856905 ps |
| CPU time | 9.04 seconds |
| Started | Jul 30 08:40:55 PM PDT 24 |
| Finished | Jul 30 08:41:04 PM PDT 24 |
| Peak memory | 573960 kb |
| Host | smart-5674609e-4105-4f2e-9b2d-ae5c63f9db64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605366877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.1605366877 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.972967294 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 2339400365 ps |
| CPU time | 85.57 seconds |
| Started | Jul 30 08:40:45 PM PDT 24 |
| Finished | Jul 30 08:42:11 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-a3c435af-d7c8-4c4c-9542-56f30a59c8a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972967294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.972967294 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.1935506950 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 2334105389 ps |
| CPU time | 87.81 seconds |
| Started | Jul 30 08:40:39 PM PDT 24 |
| Finished | Jul 30 08:42:07 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-a1ccf7c8-8ad4-4e6f-89ad-a106c0041453 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935506950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.1935506950 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.3713500877 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 67261182179 ps |
| CPU time | 760.45 seconds |
| Started | Jul 30 08:40:44 PM PDT 24 |
| Finished | Jul 30 08:53:25 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-333ecef1-4cad-40d9-918b-252f8b50b609 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713500877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.3713500877 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.2828417295 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 46237959759 ps |
| CPU time | 812.59 seconds |
| Started | Jul 30 08:40:45 PM PDT 24 |
| Finished | Jul 30 08:54:17 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-bd5d4b42-072f-4159-b770-cbd6c0ab656a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828417295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.2828417295 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.1841058579 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 584459238 ps |
| CPU time | 61.59 seconds |
| Started | Jul 30 08:40:44 PM PDT 24 |
| Finished | Jul 30 08:41:46 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-716a970d-26c5-4f18-9ad8-a82b1f9201e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841058579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.1841058579 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.1193753320 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 56083685 ps |
| CPU time | 7.37 seconds |
| Started | Jul 30 08:40:44 PM PDT 24 |
| Finished | Jul 30 08:40:51 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-d3e1cb43-c743-45ac-a96c-e094a5f0ecc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193753320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.1193753320 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.2850064364 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 41647797 ps |
| CPU time | 6.59 seconds |
| Started | Jul 30 08:40:39 PM PDT 24 |
| Finished | Jul 30 08:40:46 PM PDT 24 |
| Peak memory | 573820 kb |
| Host | smart-053918b8-2255-436a-a652-7a5a5a25b728 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850064364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.2850064364 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.4070482895 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 7209837299 ps |
| CPU time | 76.64 seconds |
| Started | Jul 30 08:40:39 PM PDT 24 |
| Finished | Jul 30 08:41:56 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-75d98293-2042-41b4-b850-e72846219db4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070482895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.4070482895 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.2361008971 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 4905942071 ps |
| CPU time | 84.62 seconds |
| Started | Jul 30 08:40:41 PM PDT 24 |
| Finished | Jul 30 08:42:06 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-7b5f376f-5e0c-48e5-a547-a3b6f3c92271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361008971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.2361008971 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.45489909 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 45182153 ps |
| CPU time | 6.86 seconds |
| Started | Jul 30 08:40:37 PM PDT 24 |
| Finished | Jul 30 08:40:44 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-9045a32b-cbf6-4e05-a9c6-e29607aa511a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45489909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delays.45489909 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.1063078219 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 426721302 ps |
| CPU time | 39.45 seconds |
| Started | Jul 30 08:40:48 PM PDT 24 |
| Finished | Jul 30 08:41:28 PM PDT 24 |
| Peak memory | 576200 kb |
| Host | smart-66cc0c4a-aaa0-45ec-a593-bfd50ba33db0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063078219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.1063078219 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.1833796965 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 2596775086 ps |
| CPU time | 101.14 seconds |
| Started | Jul 30 08:40:49 PM PDT 24 |
| Finished | Jul 30 08:42:30 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-08084f9d-2fc8-4102-a3b6-f3f2f233d9c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833796965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.1833796965 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.1607597059 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 3535736361 ps |
| CPU time | 589.79 seconds |
| Started | Jul 30 08:40:49 PM PDT 24 |
| Finished | Jul 30 08:50:39 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-e3a04171-117b-4590-b9f1-28b766a06001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607597059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.1607597059 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.3330578472 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 317017784 ps |
| CPU time | 96.82 seconds |
| Started | Jul 30 08:40:55 PM PDT 24 |
| Finished | Jul 30 08:42:32 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-1d568603-b3e8-43a3-a333-e40e4578e9af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330578472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al l_with_reset_error.3330578472 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.922512184 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 1046608235 ps |
| CPU time | 51.32 seconds |
| Started | Jul 30 08:40:46 PM PDT 24 |
| Finished | Jul 30 08:41:37 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-addca15b-475a-4c9d-8253-5ac551e0e433 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922512184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.922512184 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.1000006616 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 2036660515 ps |
| CPU time | 96.42 seconds |
| Started | Jul 30 08:40:48 PM PDT 24 |
| Finished | Jul 30 08:42:24 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-dcc990d1-6360-4d0b-b7de-95d8c455d664 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000006616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .1000006616 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.614844038 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 28864618520 ps |
| CPU time | 512.5 seconds |
| Started | Jul 30 08:40:50 PM PDT 24 |
| Finished | Jul 30 08:49:23 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-47109f59-8c5a-460f-8230-ea836f449773 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614844038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_d evice_slow_rsp.614844038 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.317306077 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 704081896 ps |
| CPU time | 27.51 seconds |
| Started | Jul 30 08:40:59 PM PDT 24 |
| Finished | Jul 30 08:41:27 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-9531ecaf-c345-4364-b268-86750674d8f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317306077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_addr .317306077 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.2790267180 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 232097769 ps |
| CPU time | 11.74 seconds |
| Started | Jul 30 08:40:53 PM PDT 24 |
| Finished | Jul 30 08:41:05 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-521fda50-bac8-4ee5-9edb-7eac21a767dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790267180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.2790267180 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.1750592668 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 456369781 ps |
| CPU time | 19.09 seconds |
| Started | Jul 30 08:40:55 PM PDT 24 |
| Finished | Jul 30 08:41:14 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-7d8b26d8-f566-4d15-b2cc-93ae5084e3c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750592668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.1750592668 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.1804520748 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 56841982071 ps |
| CPU time | 628.08 seconds |
| Started | Jul 30 08:40:52 PM PDT 24 |
| Finished | Jul 30 08:51:20 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-3416d753-72a2-49de-8c5d-fee2a4342509 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804520748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.1804520748 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.1856764262 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 24096402387 ps |
| CPU time | 453.27 seconds |
| Started | Jul 30 08:40:49 PM PDT 24 |
| Finished | Jul 30 08:48:22 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-6ed503b9-8ea3-4aa2-906f-2c128430fa0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856764262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.1856764262 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.3387497198 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 435983905 ps |
| CPU time | 40.98 seconds |
| Started | Jul 30 08:40:51 PM PDT 24 |
| Finished | Jul 30 08:41:32 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-e73db7fa-df63-453d-8fdf-72890c6cf66b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387497198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.3387497198 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.845761152 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 499126935 ps |
| CPU time | 33.55 seconds |
| Started | Jul 30 08:40:53 PM PDT 24 |
| Finished | Jul 30 08:41:26 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-557cc20b-f544-478f-97b4-cc2bc43590c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845761152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.845761152 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.1420140860 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 52094653 ps |
| CPU time | 6.66 seconds |
| Started | Jul 30 08:40:59 PM PDT 24 |
| Finished | Jul 30 08:41:06 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-6429a800-c5f6-47b5-9c6a-2dea3ddf76a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420140860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.1420140860 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.2526813804 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 5932512781 ps |
| CPU time | 61.39 seconds |
| Started | Jul 30 08:40:56 PM PDT 24 |
| Finished | Jul 30 08:41:57 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-fd2bb06b-e823-4a65-a27f-603966865322 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526813804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.2526813804 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.3137297398 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 3815913216 ps |
| CPU time | 69.26 seconds |
| Started | Jul 30 08:40:48 PM PDT 24 |
| Finished | Jul 30 08:41:57 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-aaf085ac-4482-484a-ab22-532544664342 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137297398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.3137297398 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.2128617596 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 48821900 ps |
| CPU time | 6.87 seconds |
| Started | Jul 30 08:40:48 PM PDT 24 |
| Finished | Jul 30 08:40:55 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-084dd703-b7b8-4128-bf5d-0823766bfc02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128617596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.2128617596 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.4108618744 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 3988254183 ps |
| CPU time | 310.47 seconds |
| Started | Jul 30 08:40:59 PM PDT 24 |
| Finished | Jul 30 08:46:10 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-563b0936-d60e-4f97-9d6c-755fcf5cb602 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108618744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.4108618744 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.4229895523 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 8147243588 ps |
| CPU time | 336.02 seconds |
| Started | Jul 30 08:40:53 PM PDT 24 |
| Finished | Jul 30 08:46:29 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-88ffe9a7-0db0-4334-8979-302988f3ddfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229895523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.4229895523 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.643714776 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 6379785551 ps |
| CPU time | 376.01 seconds |
| Started | Jul 30 08:40:50 PM PDT 24 |
| Finished | Jul 30 08:47:06 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-940d6b34-bd7e-4141-a296-74e894195f25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643714776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_ with_rand_reset.643714776 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.3907868614 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 1742927773 ps |
| CPU time | 192.06 seconds |
| Started | Jul 30 08:40:59 PM PDT 24 |
| Finished | Jul 30 08:44:11 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-5d417f8b-233f-48a3-b247-c2da4e245ac0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907868614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.3907868614 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.4034563537 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 140395966 ps |
| CPU time | 20.44 seconds |
| Started | Jul 30 08:40:54 PM PDT 24 |
| Finished | Jul 30 08:41:14 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-6555e574-cbe6-474c-badf-375df30df260 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034563537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.4034563537 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.2624264469 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 1799327149 ps |
| CPU time | 75.35 seconds |
| Started | Jul 30 08:41:04 PM PDT 24 |
| Finished | Jul 30 08:42:19 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-a45138e1-6146-41b8-95b7-40baeaf9bb8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624264469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device .2624264469 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.3728320623 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 928269470 ps |
| CPU time | 36.74 seconds |
| Started | Jul 30 08:41:02 PM PDT 24 |
| Finished | Jul 30 08:41:39 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-81abd921-f6a3-4598-9237-275b2dee9b93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728320623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.3728320623 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.676624942 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 398020397 ps |
| CPU time | 34.23 seconds |
| Started | Jul 30 08:41:01 PM PDT 24 |
| Finished | Jul 30 08:41:35 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-a7d447aa-53d3-4d3a-9650-05c239f3ce43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676624942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.676624942 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.1255684823 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 1422417147 ps |
| CPU time | 48.8 seconds |
| Started | Jul 30 08:41:00 PM PDT 24 |
| Finished | Jul 30 08:41:48 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-37dfa805-a2bd-4021-9b9e-ffe045ce8d77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255684823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.1255684823 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.2676127274 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 55832224363 ps |
| CPU time | 615.93 seconds |
| Started | Jul 30 08:41:01 PM PDT 24 |
| Finished | Jul 30 08:51:17 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-4cc7d8fe-edb7-4bf5-9395-601c6dacb3cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676127274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.2676127274 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.1746997633 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 3661165976 ps |
| CPU time | 67.82 seconds |
| Started | Jul 30 08:40:58 PM PDT 24 |
| Finished | Jul 30 08:42:06 PM PDT 24 |
| Peak memory | 573960 kb |
| Host | smart-0a26671f-1883-4d9b-b91a-1397fd8d46b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746997633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.1746997633 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.2410106554 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 169408645 ps |
| CPU time | 19.4 seconds |
| Started | Jul 30 08:41:00 PM PDT 24 |
| Finished | Jul 30 08:41:19 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-396fe9d4-e6af-41b0-87da-0316687fdbbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410106554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.2410106554 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.1508428410 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 1807028000 ps |
| CPU time | 52.96 seconds |
| Started | Jul 30 08:41:03 PM PDT 24 |
| Finished | Jul 30 08:41:56 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-a03e4738-8cbc-4c53-8072-4131b87e47fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508428410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.1508428410 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.1031008203 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 43489170 ps |
| CPU time | 6.56 seconds |
| Started | Jul 30 08:40:56 PM PDT 24 |
| Finished | Jul 30 08:41:03 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-27adb01c-0c51-43a7-9402-fae006f0b49e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031008203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.1031008203 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.3448448994 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 8437208318 ps |
| CPU time | 91.12 seconds |
| Started | Jul 30 08:40:56 PM PDT 24 |
| Finished | Jul 30 08:42:27 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-8baf7786-09f7-4cbb-94bc-f3a4057b6414 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448448994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.3448448994 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.791609476 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 5509622213 ps |
| CPU time | 94.32 seconds |
| Started | Jul 30 08:41:01 PM PDT 24 |
| Finished | Jul 30 08:42:35 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-2304a0d7-9b48-4e3a-addc-0e68b8269ab3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791609476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.791609476 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.2581411666 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 41907208 ps |
| CPU time | 6.25 seconds |
| Started | Jul 30 08:40:56 PM PDT 24 |
| Finished | Jul 30 08:41:02 PM PDT 24 |
| Peak memory | 573780 kb |
| Host | smart-f5e9311a-1b30-4971-bea6-42e3a7e009ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581411666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.2581411666 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.1156282160 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 8993788448 ps |
| CPU time | 367.51 seconds |
| Started | Jul 30 08:41:03 PM PDT 24 |
| Finished | Jul 30 08:47:11 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-5fb20519-83dd-4ba9-ae87-98b89ea2df88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156282160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.1156282160 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.2873540558 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 5020982120 ps |
| CPU time | 181.98 seconds |
| Started | Jul 30 08:41:08 PM PDT 24 |
| Finished | Jul 30 08:44:10 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-927224fd-29b6-4593-84fb-30e4af3e3061 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873540558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.2873540558 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.78212148 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 206608398 ps |
| CPU time | 28.52 seconds |
| Started | Jul 30 08:41:04 PM PDT 24 |
| Finished | Jul 30 08:41:33 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-aafe478a-d762-4eab-97b7-761766f34d6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78212148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.78212148 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.668449483 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 2979725404 ps |
| CPU time | 132.49 seconds |
| Started | Jul 30 08:41:18 PM PDT 24 |
| Finished | Jul 30 08:43:30 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-45850b1d-da95-4107-9fc0-fa7279c1936a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668449483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device. 668449483 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.2028702437 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 142073037451 ps |
| CPU time | 2404.11 seconds |
| Started | Jul 30 08:41:13 PM PDT 24 |
| Finished | Jul 30 09:21:17 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-3c915225-998d-4ab6-baf9-955087a2141a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028702437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.2028702437 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.3164132211 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 1073241648 ps |
| CPU time | 44.78 seconds |
| Started | Jul 30 08:41:19 PM PDT 24 |
| Finished | Jul 30 08:42:03 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-4bfbcd49-c9ab-45cc-b060-29f1484f6c8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164132211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.3164132211 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.2199364756 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 1260647743 ps |
| CPU time | 44.18 seconds |
| Started | Jul 30 08:41:19 PM PDT 24 |
| Finished | Jul 30 08:42:03 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-8cbb221e-15ce-4b70-bd34-14e810636f3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199364756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.2199364756 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.3737317217 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 95788350 ps |
| CPU time | 12.1 seconds |
| Started | Jul 30 08:41:13 PM PDT 24 |
| Finished | Jul 30 08:41:25 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-c915cebd-52b8-4581-95b9-900ee74567e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737317217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.3737317217 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.159743781 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 44232705445 ps |
| CPU time | 487.39 seconds |
| Started | Jul 30 08:41:11 PM PDT 24 |
| Finished | Jul 30 08:49:18 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-fee7a0d8-8994-4938-bd56-014c7189fd1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159743781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.159743781 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.310855691 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 53083371637 ps |
| CPU time | 986.86 seconds |
| Started | Jul 30 08:41:12 PM PDT 24 |
| Finished | Jul 30 08:57:39 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-bdc01f09-d32f-4329-bb87-0518ea0d4460 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310855691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.310855691 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.2710191449 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 367901287 ps |
| CPU time | 34.05 seconds |
| Started | Jul 30 08:41:13 PM PDT 24 |
| Finished | Jul 30 08:41:47 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-69bf7bfb-3f0c-42e6-9dd8-0a82f75d63af |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710191449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.2710191449 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.2087070395 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 857305058 ps |
| CPU time | 28.23 seconds |
| Started | Jul 30 08:41:14 PM PDT 24 |
| Finished | Jul 30 08:41:43 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-72a41487-c943-4653-96bf-7c31697cd1f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087070395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.2087070395 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.446512317 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 55237701 ps |
| CPU time | 7.32 seconds |
| Started | Jul 30 08:41:06 PM PDT 24 |
| Finished | Jul 30 08:41:13 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-866c0b4d-3751-46c0-ad24-28e66208e15a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446512317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.446512317 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.551275599 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 6052892437 ps |
| CPU time | 64.01 seconds |
| Started | Jul 30 08:41:11 PM PDT 24 |
| Finished | Jul 30 08:42:15 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-81829171-692a-4b73-b739-6a78f34ef369 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551275599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.551275599 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.2489569453 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 5250366112 ps |
| CPU time | 92.18 seconds |
| Started | Jul 30 08:41:12 PM PDT 24 |
| Finished | Jul 30 08:42:44 PM PDT 24 |
| Peak memory | 573908 kb |
| Host | smart-e148fbb9-eedd-4a77-a9da-dd269ad1ae1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489569453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.2489569453 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.963298421 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 48202124 ps |
| CPU time | 6.71 seconds |
| Started | Jul 30 08:41:06 PM PDT 24 |
| Finished | Jul 30 08:41:13 PM PDT 24 |
| Peak memory | 573776 kb |
| Host | smart-e375e6d7-997f-4925-85df-d8715d14388e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963298421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delays .963298421 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.2523023368 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 4889752386 ps |
| CPU time | 224.35 seconds |
| Started | Jul 30 08:41:21 PM PDT 24 |
| Finished | Jul 30 08:45:05 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-d466d8c5-a8aa-4a18-85cd-0ca365ff49c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523023368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.2523023368 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.1559900101 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 9440237526 ps |
| CPU time | 330.46 seconds |
| Started | Jul 30 08:41:21 PM PDT 24 |
| Finished | Jul 30 08:46:51 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-4f440bf5-abf5-457c-904e-7ee9143d9fe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559900101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.1559900101 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.3807593752 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 11412021468 ps |
| CPU time | 672.46 seconds |
| Started | Jul 30 08:41:17 PM PDT 24 |
| Finished | Jul 30 08:52:29 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-5394b8d5-d3bd-47e5-ab8e-868b8a326e6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807593752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.3807593752 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2156324768 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 371334779 ps |
| CPU time | 158.08 seconds |
| Started | Jul 30 08:41:21 PM PDT 24 |
| Finished | Jul 30 08:44:00 PM PDT 24 |
| Peak memory | 576796 kb |
| Host | smart-049226a4-3176-4474-8a89-4bda1a698618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156324768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.2156324768 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.1137367988 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 246535850 ps |
| CPU time | 31.09 seconds |
| Started | Jul 30 08:41:17 PM PDT 24 |
| Finished | Jul 30 08:41:48 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-af92e76f-510e-4108-866e-3c472e94d384 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137367988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.1137367988 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.1155657352 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 1324929899 ps |
| CPU time | 57.56 seconds |
| Started | Jul 30 08:41:28 PM PDT 24 |
| Finished | Jul 30 08:42:26 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-15d3abdf-2b0b-4ad2-9db8-f5be23e2e831 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155657352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .1155657352 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.942085911 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 93704832567 ps |
| CPU time | 1536.71 seconds |
| Started | Jul 30 08:41:23 PM PDT 24 |
| Finished | Jul 30 09:07:00 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-4d2e8da4-a3e7-4ca5-8c8d-a5fd772814ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942085911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_d evice_slow_rsp.942085911 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.3266251733 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 632374020 ps |
| CPU time | 31.03 seconds |
| Started | Jul 30 08:41:27 PM PDT 24 |
| Finished | Jul 30 08:41:58 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-6de2cd28-c74d-4835-ab83-e68fc465b62b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266251733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.3266251733 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.3941018923 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 491218147 ps |
| CPU time | 44.97 seconds |
| Started | Jul 30 08:41:23 PM PDT 24 |
| Finished | Jul 30 08:42:08 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-7f2e0db5-3019-43db-8265-d17333b0ed69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941018923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.3941018923 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.339124389 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 857246409 ps |
| CPU time | 34.09 seconds |
| Started | Jul 30 08:41:23 PM PDT 24 |
| Finished | Jul 30 08:41:57 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-0f1e742c-507d-4b61-8cb9-002dfcdf4674 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339124389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.339124389 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.2732451930 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 45064810102 ps |
| CPU time | 513.47 seconds |
| Started | Jul 30 08:41:25 PM PDT 24 |
| Finished | Jul 30 08:49:59 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-71b86ce6-0ae6-4f54-8bd7-6f9f62b531f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732451930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.2732451930 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.2532871730 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 76133751013 ps |
| CPU time | 1351.07 seconds |
| Started | Jul 30 08:41:25 PM PDT 24 |
| Finished | Jul 30 09:03:56 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-ab9db903-f2ae-4343-9371-8c4cacc11b39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532871730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.2532871730 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.3587631113 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 253768152 ps |
| CPU time | 27.1 seconds |
| Started | Jul 30 08:41:25 PM PDT 24 |
| Finished | Jul 30 08:41:52 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-465eaf8c-17a1-45c9-b44c-5961f4ce89fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587631113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.3587631113 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.2881276175 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 1812570753 ps |
| CPU time | 47.28 seconds |
| Started | Jul 30 08:41:23 PM PDT 24 |
| Finished | Jul 30 08:42:10 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-825470ce-4229-4a84-afde-a6e035462297 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881276175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.2881276175 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.3803618751 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 56659353 ps |
| CPU time | 7.12 seconds |
| Started | Jul 30 08:41:24 PM PDT 24 |
| Finished | Jul 30 08:41:31 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-1b769794-6fa1-468b-ac62-88c00b027df9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803618751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.3803618751 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.4113989946 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 6751617713 ps |
| CPU time | 71.93 seconds |
| Started | Jul 30 08:41:22 PM PDT 24 |
| Finished | Jul 30 08:42:34 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-3f84e7a2-481d-4417-bfd6-7a91b95bda81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113989946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.4113989946 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.3003479820 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 4520880178 ps |
| CPU time | 77.87 seconds |
| Started | Jul 30 08:41:24 PM PDT 24 |
| Finished | Jul 30 08:42:42 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-f2c55506-39d6-49e2-a7e1-d1dc703abcf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003479820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.3003479820 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1821843435 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 59768456 ps |
| CPU time | 7.51 seconds |
| Started | Jul 30 08:41:22 PM PDT 24 |
| Finished | Jul 30 08:41:30 PM PDT 24 |
| Peak memory | 573876 kb |
| Host | smart-de8e86bd-1790-44cc-9680-35794b6253b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821843435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.1821843435 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.3359811389 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 4513418225 ps |
| CPU time | 161.69 seconds |
| Started | Jul 30 08:41:26 PM PDT 24 |
| Finished | Jul 30 08:44:08 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-9b25b68d-389c-4f8d-9815-6a6d0f534275 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359811389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.3359811389 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.4011699658 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 2033632497 ps |
| CPU time | 139.74 seconds |
| Started | Jul 30 08:41:30 PM PDT 24 |
| Finished | Jul 30 08:43:50 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-3fb16cbe-8ae6-4913-9fea-5d633434b089 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011699658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.4011699658 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3654225048 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 116262971 ps |
| CPU time | 38.67 seconds |
| Started | Jul 30 08:41:30 PM PDT 24 |
| Finished | Jul 30 08:42:08 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-1ee2b464-f367-47a0-952b-406e01593669 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654225048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_rand_reset.3654225048 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.3514496870 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 67667772 ps |
| CPU time | 10.8 seconds |
| Started | Jul 30 08:41:26 PM PDT 24 |
| Finished | Jul 30 08:41:37 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-285e9532-61f4-49db-b5f1-00034d0970e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514496870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.3514496870 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.4179857677 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 741628794 ps |
| CPU time | 68.79 seconds |
| Started | Jul 30 08:41:31 PM PDT 24 |
| Finished | Jul 30 08:42:40 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-7e8e227d-0c4c-4b96-bd91-d122ba992ac0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179857677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .4179857677 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.2861277997 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 58559557376 ps |
| CPU time | 993.19 seconds |
| Started | Jul 30 08:41:33 PM PDT 24 |
| Finished | Jul 30 08:58:06 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-9b77ba9d-185a-403f-a5ba-dada3f60c2da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861277997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.2861277997 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.1261691391 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 696808512 ps |
| CPU time | 29.68 seconds |
| Started | Jul 30 08:41:35 PM PDT 24 |
| Finished | Jul 30 08:42:05 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-5eba1596-625e-4ccc-b4c1-9d9d7f48d357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261691391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add r.1261691391 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.3630650559 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 629956703 ps |
| CPU time | 56.75 seconds |
| Started | Jul 30 08:41:38 PM PDT 24 |
| Finished | Jul 30 08:42:35 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-5b57b150-40b2-4ef2-a689-4ab00c489cce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630650559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.3630650559 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.3275414985 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 387137362 ps |
| CPU time | 34.34 seconds |
| Started | Jul 30 08:41:30 PM PDT 24 |
| Finished | Jul 30 08:42:04 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-76464768-8b3a-4515-b3b8-dd9495e2e59e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275414985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.3275414985 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.2291320612 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 108278634263 ps |
| CPU time | 1111.18 seconds |
| Started | Jul 30 08:41:32 PM PDT 24 |
| Finished | Jul 30 09:00:03 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-0c6935b4-2447-44cf-9d69-ed5d01f31d79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291320612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.2291320612 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.254559727 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 31193190872 ps |
| CPU time | 553.09 seconds |
| Started | Jul 30 08:41:32 PM PDT 24 |
| Finished | Jul 30 08:50:45 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-4915f7eb-1230-4085-95a9-4adf11c09546 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254559727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.254559727 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.2639911978 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 345859693 ps |
| CPU time | 32.22 seconds |
| Started | Jul 30 08:41:32 PM PDT 24 |
| Finished | Jul 30 08:42:04 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-2f9d6094-3c0f-4a5a-a039-2d0d75c2edc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639911978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.2639911978 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.2151932323 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 39819138 ps |
| CPU time | 6.46 seconds |
| Started | Jul 30 08:41:39 PM PDT 24 |
| Finished | Jul 30 08:41:46 PM PDT 24 |
| Peak memory | 573876 kb |
| Host | smart-6df753a0-5fc6-4148-a16a-4958477bfda1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151932323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.2151932323 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.1273475976 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 52386015 ps |
| CPU time | 6.84 seconds |
| Started | Jul 30 08:41:30 PM PDT 24 |
| Finished | Jul 30 08:41:37 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-720b3255-21b3-48ea-95f8-0c97fa120706 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273475976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.1273475976 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.4247590383 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 8481674453 ps |
| CPU time | 92.17 seconds |
| Started | Jul 30 08:41:30 PM PDT 24 |
| Finished | Jul 30 08:43:02 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-562959ed-52a5-45dc-b7b4-3317e25a0d70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247590383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.4247590383 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.3193048105 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 4849621065 ps |
| CPU time | 83.72 seconds |
| Started | Jul 30 08:41:33 PM PDT 24 |
| Finished | Jul 30 08:42:56 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-22ea9cdd-f84d-45aa-9342-ac56ba7c4f53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193048105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.3193048105 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.3197501421 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 50339793 ps |
| CPU time | 6.97 seconds |
| Started | Jul 30 08:41:29 PM PDT 24 |
| Finished | Jul 30 08:41:36 PM PDT 24 |
| Peak memory | 573832 kb |
| Host | smart-a2d26bb6-4de1-46f5-a0f6-0df78947be5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197501421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.3197501421 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.311992436 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 9028365638 ps |
| CPU time | 394.43 seconds |
| Started | Jul 30 08:41:39 PM PDT 24 |
| Finished | Jul 30 08:48:14 PM PDT 24 |
| Peak memory | 576848 kb |
| Host | smart-f3b60fe7-51fd-4976-a498-0cfc506e2a0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311992436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.311992436 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.2374998447 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 15243623141 ps |
| CPU time | 642.81 seconds |
| Started | Jul 30 08:41:38 PM PDT 24 |
| Finished | Jul 30 08:52:21 PM PDT 24 |
| Peak memory | 576828 kb |
| Host | smart-10085099-2b99-4018-9187-945ae7497077 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374998447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.2374998447 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3942979401 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 7112169840 ps |
| CPU time | 445.42 seconds |
| Started | Jul 30 08:41:40 PM PDT 24 |
| Finished | Jul 30 08:49:06 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-5895b571-5f51-42da-b12c-5e116960651b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942979401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.3942979401 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.2984984151 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 750845470 ps |
| CPU time | 210.28 seconds |
| Started | Jul 30 08:41:39 PM PDT 24 |
| Finished | Jul 30 08:45:10 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-ee9bbc27-aaa2-4ed1-8ff0-2556652aeaac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984984151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al l_with_reset_error.2984984151 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.2967910181 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 1135194364 ps |
| CPU time | 52.47 seconds |
| Started | Jul 30 08:41:34 PM PDT 24 |
| Finished | Jul 30 08:42:27 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-015ac8d3-f61c-4871-9825-15f48d61e468 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967910181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.2967910181 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.1617623044 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 141766319 ps |
| CPU time | 9.79 seconds |
| Started | Jul 30 08:41:41 PM PDT 24 |
| Finished | Jul 30 08:41:51 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-7b871dc8-e97d-4d5c-8da8-8aad9c61cbcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617623044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .1617623044 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1331152913 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 54950896192 ps |
| CPU time | 974.11 seconds |
| Started | Jul 30 08:41:42 PM PDT 24 |
| Finished | Jul 30 08:57:56 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-9a9abcb4-a585-4029-9be1-0e7b7079e353 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331152913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.1331152913 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.2960527205 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 255963658 ps |
| CPU time | 32.11 seconds |
| Started | Jul 30 08:41:48 PM PDT 24 |
| Finished | Jul 30 08:42:21 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-196b221d-5562-4468-b6a3-577dc490c748 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960527205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.2960527205 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.2433251883 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 209976499 ps |
| CPU time | 17.86 seconds |
| Started | Jul 30 08:41:44 PM PDT 24 |
| Finished | Jul 30 08:42:02 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-b7abd628-c552-48af-95e0-d7e6550ba787 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433251883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.2433251883 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.1530839624 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 426707580 ps |
| CPU time | 35.88 seconds |
| Started | Jul 30 08:41:41 PM PDT 24 |
| Finished | Jul 30 08:42:17 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-e8287a4d-546b-4344-aa10-7b4fa9c77f75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530839624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.1530839624 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.3352731695 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 83222564616 ps |
| CPU time | 889.21 seconds |
| Started | Jul 30 08:41:42 PM PDT 24 |
| Finished | Jul 30 08:56:32 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-cdfbbdb2-4f83-4c1f-ab3f-71b91d3d6239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352731695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.3352731695 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.274228837 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 34504901702 ps |
| CPU time | 607.11 seconds |
| Started | Jul 30 08:41:44 PM PDT 24 |
| Finished | Jul 30 08:51:51 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-c7fc6961-f8db-455a-b9cd-56fc7cd40686 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274228837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.274228837 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.1431910480 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 131445962 ps |
| CPU time | 16.18 seconds |
| Started | Jul 30 08:41:41 PM PDT 24 |
| Finished | Jul 30 08:41:58 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-8906f8c6-5ca1-40c1-9ecf-a6f68ac125dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431910480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.1431910480 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.3998016700 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 227483228 ps |
| CPU time | 21.74 seconds |
| Started | Jul 30 08:41:47 PM PDT 24 |
| Finished | Jul 30 08:42:09 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-3584b1cc-7b43-410d-82aa-3cb1d2fa8392 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998016700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.3998016700 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.73845548 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 169862403 ps |
| CPU time | 8.83 seconds |
| Started | Jul 30 08:41:39 PM PDT 24 |
| Finished | Jul 30 08:41:48 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-666af321-95c5-4207-bab5-436336e95cd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73845548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.73845548 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.791884780 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 8595218616 ps |
| CPU time | 92.84 seconds |
| Started | Jul 30 08:41:40 PM PDT 24 |
| Finished | Jul 30 08:43:12 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-0d41a202-d894-411a-bbe2-15d5d091e751 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791884780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.791884780 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.944095621 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 3274773690 ps |
| CPU time | 58.02 seconds |
| Started | Jul 30 08:41:42 PM PDT 24 |
| Finished | Jul 30 08:42:40 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-64229843-6fc1-4529-a8d1-668a421025ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944095621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.944095621 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.3826947735 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 49069059 ps |
| CPU time | 6.61 seconds |
| Started | Jul 30 08:41:38 PM PDT 24 |
| Finished | Jul 30 08:41:45 PM PDT 24 |
| Peak memory | 573828 kb |
| Host | smart-7f06d765-4b21-4459-9120-fcaddbae3243 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826947735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.3826947735 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.4256581900 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 6750492975 ps |
| CPU time | 288.54 seconds |
| Started | Jul 30 08:41:49 PM PDT 24 |
| Finished | Jul 30 08:46:38 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-6a3be2df-3de9-482b-8132-0644242c1bfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256581900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.4256581900 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.3355702239 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 3352568692 ps |
| CPU time | 315.33 seconds |
| Started | Jul 30 08:41:52 PM PDT 24 |
| Finished | Jul 30 08:47:08 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-6e05b801-05e3-4bb4-be53-0dd343850ec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355702239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.3355702239 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.873774377 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 291859410 ps |
| CPU time | 105.03 seconds |
| Started | Jul 30 08:41:48 PM PDT 24 |
| Finished | Jul 30 08:43:33 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-60e98849-eee9-48d8-898f-19496a7ce3d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873774377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_ with_rand_reset.873774377 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.82050180 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 55907793 ps |
| CPU time | 19.25 seconds |
| Started | Jul 30 08:41:52 PM PDT 24 |
| Finished | Jul 30 08:42:11 PM PDT 24 |
| Peak memory | 576348 kb |
| Host | smart-f0f86959-f8ca-45ce-ba5a-b389c098c3f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82050180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_ with_reset_error.82050180 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.3017886389 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 772358994 ps |
| CPU time | 33.32 seconds |
| Started | Jul 30 08:41:45 PM PDT 24 |
| Finished | Jul 30 08:42:18 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-4ccb9693-aef4-4ea5-bfe1-25a9c4bb0e43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017886389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.3017886389 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.2564329918 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 523589546 ps |
| CPU time | 46.96 seconds |
| Started | Jul 30 08:41:58 PM PDT 24 |
| Finished | Jul 30 08:42:45 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-16f6a16c-8f1f-465d-87a9-48cd0d1daa6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564329918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .2564329918 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.2625216832 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 47398840386 ps |
| CPU time | 823.4 seconds |
| Started | Jul 30 08:41:58 PM PDT 24 |
| Finished | Jul 30 08:55:41 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-f8b8fcac-2bec-4288-b09a-89a6886939ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625216832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.2625216832 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.251093748 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 180612394 ps |
| CPU time | 23.88 seconds |
| Started | Jul 30 08:41:57 PM PDT 24 |
| Finished | Jul 30 08:42:21 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-599d822f-b034-492d-ac8c-76bd8a33b233 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251093748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_addr .251093748 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.4263488006 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 2613077497 ps |
| CPU time | 94.47 seconds |
| Started | Jul 30 08:42:01 PM PDT 24 |
| Finished | Jul 30 08:43:36 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-adb0852e-81e7-4f5b-a936-535acdb89515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263488006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.4263488006 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.1910738485 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 513128714 ps |
| CPU time | 45.66 seconds |
| Started | Jul 30 08:42:02 PM PDT 24 |
| Finished | Jul 30 08:42:48 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-a84a2181-ed61-44e7-8cab-5ec68a3fce4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910738485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.1910738485 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.2946952178 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 3099264192 ps |
| CPU time | 34.83 seconds |
| Started | Jul 30 08:41:54 PM PDT 24 |
| Finished | Jul 30 08:42:29 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-4fac2095-ba51-494f-a9b8-6da7222a0a41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946952178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.2946952178 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.1935520773 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 46168237485 ps |
| CPU time | 813.4 seconds |
| Started | Jul 30 08:41:56 PM PDT 24 |
| Finished | Jul 30 08:55:29 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-1ecaa852-a02b-40fb-9322-c5a22ef7d410 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935520773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.1935520773 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.2081357516 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 471511705 ps |
| CPU time | 48.94 seconds |
| Started | Jul 30 08:41:54 PM PDT 24 |
| Finished | Jul 30 08:42:43 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-3df0f138-1b64-472d-bc57-068405c818ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081357516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.2081357516 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.2371492865 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 340375634 ps |
| CPU time | 26.7 seconds |
| Started | Jul 30 08:41:58 PM PDT 24 |
| Finished | Jul 30 08:42:25 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-c4670dbe-0588-4dec-b2f7-afa596a8489e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371492865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.2371492865 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.4209239551 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 194355052 ps |
| CPU time | 8.92 seconds |
| Started | Jul 30 08:41:52 PM PDT 24 |
| Finished | Jul 30 08:42:01 PM PDT 24 |
| Peak memory | 573864 kb |
| Host | smart-75f43220-d59e-4a68-bb61-f2cfe1f51d50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209239551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.4209239551 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.1074326983 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 10016922200 ps |
| CPU time | 99.69 seconds |
| Started | Jul 30 08:41:54 PM PDT 24 |
| Finished | Jul 30 08:43:34 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-cb0f08bc-ad15-4fd3-bafc-f48d49fa0555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074326983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.1074326983 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.2615102115 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 5637535869 ps |
| CPU time | 98.47 seconds |
| Started | Jul 30 08:41:55 PM PDT 24 |
| Finished | Jul 30 08:43:33 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-e337d294-2f00-47dc-960b-88bda5f76cdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615102115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.2615102115 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.645183175 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 49880409 ps |
| CPU time | 6.29 seconds |
| Started | Jul 30 08:41:50 PM PDT 24 |
| Finished | Jul 30 08:41:57 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-c03f44e8-1de8-40d5-bf0e-bdf3fc19edca |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645183175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delays .645183175 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.2560935236 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 5857821931 ps |
| CPU time | 511.87 seconds |
| Started | Jul 30 08:42:01 PM PDT 24 |
| Finished | Jul 30 08:50:33 PM PDT 24 |
| Peak memory | 576864 kb |
| Host | smart-45fbf5ee-ffa5-4bcd-acde-aaeb9039590c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560935236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.2560935236 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.397400677 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 921479690 ps |
| CPU time | 76.24 seconds |
| Started | Jul 30 08:42:03 PM PDT 24 |
| Finished | Jul 30 08:43:19 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-28b5580e-4559-48c0-ad3a-1db64cbb122a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397400677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.397400677 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.1011372266 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 6394115746 ps |
| CPU time | 367.4 seconds |
| Started | Jul 30 08:42:05 PM PDT 24 |
| Finished | Jul 30 08:48:12 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-2d0fca11-37d2-47d0-b430-04dea1feeffd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011372266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.1011372266 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.3210629959 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 709454258 ps |
| CPU time | 230.7 seconds |
| Started | Jul 30 08:42:01 PM PDT 24 |
| Finished | Jul 30 08:45:52 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-f4bdf53a-e666-4fbc-9bdc-ff487b2e279d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210629959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.3210629959 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.2369250965 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 178741849 ps |
| CPU time | 26 seconds |
| Started | Jul 30 08:41:57 PM PDT 24 |
| Finished | Jul 30 08:42:23 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-7613f46d-762f-4a97-9e5c-1fa875bfce03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369250965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.2369250965 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.205349426 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 927397826 ps |
| CPU time | 67.52 seconds |
| Started | Jul 30 08:42:12 PM PDT 24 |
| Finished | Jul 30 08:43:19 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-256dfcdb-070c-47cb-9585-ca92db7f9182 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205349426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device. 205349426 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3838116969 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 108900290502 ps |
| CPU time | 1969.91 seconds |
| Started | Jul 30 08:42:17 PM PDT 24 |
| Finished | Jul 30 09:15:07 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-74b82e6b-a013-43f8-8713-3ecb44f81fe3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838116969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.3838116969 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3488132251 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 703236059 ps |
| CPU time | 29.46 seconds |
| Started | Jul 30 08:42:13 PM PDT 24 |
| Finished | Jul 30 08:42:43 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-fe209d6c-0c2c-4593-92e3-f2b65642f559 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488132251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.3488132251 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.2731660196 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 1075425828 ps |
| CPU time | 43.47 seconds |
| Started | Jul 30 08:42:14 PM PDT 24 |
| Finished | Jul 30 08:42:57 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-ae0acaa5-1c59-45b3-b679-32daee4515b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731660196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.2731660196 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.1758591297 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 126058260 ps |
| CPU time | 13.91 seconds |
| Started | Jul 30 08:42:09 PM PDT 24 |
| Finished | Jul 30 08:42:23 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-afb85c97-62ed-4fcf-b9a9-e10406b87a78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758591297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.1758591297 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.2629398846 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 30875364341 ps |
| CPU time | 350.39 seconds |
| Started | Jul 30 08:42:07 PM PDT 24 |
| Finished | Jul 30 08:47:58 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-cfd7397e-ddce-44d3-a9c1-7cf3348a1377 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629398846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.2629398846 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.1731468275 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 70823779535 ps |
| CPU time | 1185.11 seconds |
| Started | Jul 30 08:42:07 PM PDT 24 |
| Finished | Jul 30 09:01:52 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-12439d30-e454-4321-8cd7-aeb70e1a6038 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731468275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.1731468275 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.3498006000 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 64818459 ps |
| CPU time | 10.07 seconds |
| Started | Jul 30 08:42:06 PM PDT 24 |
| Finished | Jul 30 08:42:16 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-0b0aaaed-9f18-4a06-a97b-4be17f07f44d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498006000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.3498006000 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.2511432495 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 247236838 ps |
| CPU time | 11.68 seconds |
| Started | Jul 30 08:42:17 PM PDT 24 |
| Finished | Jul 30 08:42:28 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-12862ec0-0548-4284-b2d5-5ff5089dd7bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511432495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.2511432495 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.764606140 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 49504209 ps |
| CPU time | 6.68 seconds |
| Started | Jul 30 08:42:04 PM PDT 24 |
| Finished | Jul 30 08:42:11 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-8fbb491e-d2ea-449b-9328-411a99a8f729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764606140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.764606140 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.2277381285 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 7292214624 ps |
| CPU time | 77.24 seconds |
| Started | Jul 30 08:42:04 PM PDT 24 |
| Finished | Jul 30 08:43:21 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-3d03ab9b-bcea-45c1-8a5d-9ce9615e0573 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277381285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.2277381285 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.486434629 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 5645528337 ps |
| CPU time | 95.75 seconds |
| Started | Jul 30 08:42:07 PM PDT 24 |
| Finished | Jul 30 08:43:43 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-47b065c4-bf5e-46e3-b416-f6f78ae779bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486434629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.486434629 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.3289589262 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 48785105 ps |
| CPU time | 6.61 seconds |
| Started | Jul 30 08:42:04 PM PDT 24 |
| Finished | Jul 30 08:42:11 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-ee6c1a48-e6ff-42b2-89f7-28209f97b298 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289589262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.3289589262 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.3334756779 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 1392163362 ps |
| CPU time | 126.07 seconds |
| Started | Jul 30 08:42:17 PM PDT 24 |
| Finished | Jul 30 08:44:23 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-a9289061-6ee7-4c7b-bdd8-c4a93a2ed587 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334756779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.3334756779 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.282080214 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 2257870220 ps |
| CPU time | 110.67 seconds |
| Started | Jul 30 08:42:15 PM PDT 24 |
| Finished | Jul 30 08:44:05 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-009852dd-ee2d-4860-8ed6-d3bd69fb0c1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282080214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.282080214 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.642163217 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 523014258 ps |
| CPU time | 257.44 seconds |
| Started | Jul 30 08:42:12 PM PDT 24 |
| Finished | Jul 30 08:46:29 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-7d7a2099-b10f-4262-9273-77a5495cdd7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642163217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_ with_rand_reset.642163217 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.3695847215 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 181128209 ps |
| CPU time | 66.27 seconds |
| Started | Jul 30 08:42:19 PM PDT 24 |
| Finished | Jul 30 08:43:25 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-af285a45-d919-49bf-91bf-79cc12bf347a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695847215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.3695847215 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.762558355 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 165861375 ps |
| CPU time | 10.26 seconds |
| Started | Jul 30 08:42:12 PM PDT 24 |
| Finished | Jul 30 08:42:22 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-1a7c54bf-3bb0-4f5a-bd9d-5230a4e3d308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762558355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.762558355 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.4250133929 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 160080681 ps |
| CPU time | 12.22 seconds |
| Started | Jul 30 08:42:18 PM PDT 24 |
| Finished | Jul 30 08:42:31 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-c4b36fa1-3e18-4779-aea8-8d62cef328af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250133929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .4250133929 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.1775869744 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 44977520206 ps |
| CPU time | 816.49 seconds |
| Started | Jul 30 08:42:21 PM PDT 24 |
| Finished | Jul 30 08:55:57 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-c9b97573-b301-4684-b110-39b3a487abfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775869744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.1775869744 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.1268475059 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 777961180 ps |
| CPU time | 32.43 seconds |
| Started | Jul 30 08:42:20 PM PDT 24 |
| Finished | Jul 30 08:42:52 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-8979f123-45c1-4060-9076-ced55bd69409 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268475059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.1268475059 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.279611565 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 69807511 ps |
| CPU time | 9.34 seconds |
| Started | Jul 30 08:42:20 PM PDT 24 |
| Finished | Jul 30 08:42:30 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-1f01cc7e-2681-45f8-9818-2399671a7073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279611565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.279611565 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.556109788 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 291311796 ps |
| CPU time | 26.72 seconds |
| Started | Jul 30 08:42:15 PM PDT 24 |
| Finished | Jul 30 08:42:41 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-f8bd13e2-45a9-4a7f-bad6-17274371fb40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556109788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.556109788 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.529786526 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 20592612259 ps |
| CPU time | 222.01 seconds |
| Started | Jul 30 08:42:18 PM PDT 24 |
| Finished | Jul 30 08:46:00 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-499fa31e-bd53-4a6e-a187-743958f2fb1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529786526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.529786526 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.1814297161 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 37276181375 ps |
| CPU time | 670.75 seconds |
| Started | Jul 30 08:42:17 PM PDT 24 |
| Finished | Jul 30 08:53:28 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-151b24f8-dec8-44f4-9c5b-27f18e263b5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814297161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.1814297161 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.2742760057 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 557221389 ps |
| CPU time | 52.28 seconds |
| Started | Jul 30 08:42:16 PM PDT 24 |
| Finished | Jul 30 08:43:09 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-c687c56e-d1e4-4d06-b147-d64d4e629fef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742760057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del ays.2742760057 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.1218042340 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 656887947 ps |
| CPU time | 22.85 seconds |
| Started | Jul 30 08:42:20 PM PDT 24 |
| Finished | Jul 30 08:42:43 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-b00ce7a4-297c-4c63-a4be-2a06d88df8ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218042340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.1218042340 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.292867233 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 159080725 ps |
| CPU time | 8.53 seconds |
| Started | Jul 30 08:42:12 PM PDT 24 |
| Finished | Jul 30 08:42:21 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-05d2d8ec-47bb-42ff-bbb1-cb22b1b986bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292867233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.292867233 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.2667374252 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 6751903361 ps |
| CPU time | 69.52 seconds |
| Started | Jul 30 08:42:14 PM PDT 24 |
| Finished | Jul 30 08:43:23 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-db13566a-8b14-4051-8611-8dbd6ea686e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667374252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.2667374252 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.3456605375 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 5834213930 ps |
| CPU time | 96.61 seconds |
| Started | Jul 30 08:42:13 PM PDT 24 |
| Finished | Jul 30 08:43:50 PM PDT 24 |
| Peak memory | 573948 kb |
| Host | smart-cad6241f-1228-4f04-947f-b5b4aea718ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456605375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.3456605375 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.2330370872 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 54402465 ps |
| CPU time | 7.39 seconds |
| Started | Jul 30 08:42:15 PM PDT 24 |
| Finished | Jul 30 08:42:22 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-17a4e6f2-4770-484e-aa75-479e8123e7a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330370872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.2330370872 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.3098768559 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 14062388485 ps |
| CPU time | 506.15 seconds |
| Started | Jul 30 08:42:19 PM PDT 24 |
| Finished | Jul 30 08:50:45 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-6d6465e5-7aed-4abf-ad5e-1cf9d5b738e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098768559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.3098768559 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.1154472035 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 2826893761 ps |
| CPU time | 254.83 seconds |
| Started | Jul 30 08:42:21 PM PDT 24 |
| Finished | Jul 30 08:46:35 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-3236e5e6-04b1-476d-ac95-ec7632e22183 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154472035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.1154472035 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3358813773 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 248392113 ps |
| CPU time | 122.42 seconds |
| Started | Jul 30 08:42:19 PM PDT 24 |
| Finished | Jul 30 08:44:22 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-9a61b34a-d194-4980-8eab-0509f3598ca5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358813773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.3358813773 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.3183638963 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 564585223 ps |
| CPU time | 191.98 seconds |
| Started | Jul 30 08:42:24 PM PDT 24 |
| Finished | Jul 30 08:45:36 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-b755ef33-e461-4967-b749-1d21babc17a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183638963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.3183638963 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.3942470976 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 375954684 ps |
| CPU time | 18.72 seconds |
| Started | Jul 30 08:42:20 PM PDT 24 |
| Finished | Jul 30 08:42:39 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-42351995-34fb-44b3-9b73-831e0ffba2b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942470976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.3942470976 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.1076596520 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 6236110272 ps |
| CPU time | 440.97 seconds |
| Started | Jul 30 08:29:35 PM PDT 24 |
| Finished | Jul 30 08:36:56 PM PDT 24 |
| Peak memory | 648292 kb |
| Host | smart-62bc58d4-88cb-4d88-acc0-67890e8780e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076596520 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.1076596520 |
| Directory | /workspace/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.814290056 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 3847375360 ps |
| CPU time | 297.2 seconds |
| Started | Jul 30 08:29:36 PM PDT 24 |
| Finished | Jul 30 08:34:33 PM PDT 24 |
| Peak memory | 597264 kb |
| Host | smart-74140f61-4680-429b-844d-e4d2dc6e113c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814290056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.814290056 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.96474995 |
| Short name | T2925 |
| Test name | |
| Test status | |
| Simulation time | 15314486669 ps |
| CPU time | 1857.75 seconds |
| Started | Jul 30 08:29:04 PM PDT 24 |
| Finished | Jul 30 09:00:02 PM PDT 24 |
| Peak memory | 593312 kb |
| Host | smart-33608789-4706-47c8-9c6a-e8e412fa60e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96474995 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.chip_same_csr_outstanding.96474995 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.3040020008 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 95301514 ps |
| CPU time | 9.92 seconds |
| Started | Jul 30 08:29:25 PM PDT 24 |
| Finished | Jul 30 08:29:35 PM PDT 24 |
| Peak memory | 573776 kb |
| Host | smart-ad0c47e5-08d0-4190-8f05-d63acd720efc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040020008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 3040020008 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.2979669753 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 58549714238 ps |
| CPU time | 1051.58 seconds |
| Started | Jul 30 08:29:23 PM PDT 24 |
| Finished | Jul 30 08:46:54 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-c8ca684a-610c-4e7b-b716-be05995dd111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979669753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.2979669753 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3469080111 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 587557156 ps |
| CPU time | 25.82 seconds |
| Started | Jul 30 08:29:28 PM PDT 24 |
| Finished | Jul 30 08:29:54 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-a29eb1bb-2be8-4d23-864a-398d0cc01e30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469080111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .3469080111 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.2697650586 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 385035902 ps |
| CPU time | 34.54 seconds |
| Started | Jul 30 08:29:29 PM PDT 24 |
| Finished | Jul 30 08:30:03 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-47d06c11-96ea-40d7-9d4b-39497d1c99ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697650586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2697650586 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.2650658124 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 124691758 ps |
| CPU time | 7.95 seconds |
| Started | Jul 30 08:29:20 PM PDT 24 |
| Finished | Jul 30 08:29:28 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-d3449c86-d08c-4bb8-acb9-4e45877d4658 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650658124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.2650658124 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.189669088 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 64928171748 ps |
| CPU time | 720.53 seconds |
| Started | Jul 30 08:29:20 PM PDT 24 |
| Finished | Jul 30 08:41:21 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-b14a9254-e9db-4e16-a161-de6bfa11e781 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189669088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.189669088 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.4084629115 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 10471809626 ps |
| CPU time | 186.12 seconds |
| Started | Jul 30 08:29:26 PM PDT 24 |
| Finished | Jul 30 08:32:32 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-abda3846-2948-415c-bc0c-a9d71ac8095c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084629115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.4084629115 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.1709809666 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 317642543 ps |
| CPU time | 32.45 seconds |
| Started | Jul 30 08:29:20 PM PDT 24 |
| Finished | Jul 30 08:29:53 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-b2c08449-b220-4d45-a75c-393bd651e66f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709809666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.1709809666 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.1161677534 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 372669240 ps |
| CPU time | 30.92 seconds |
| Started | Jul 30 08:29:24 PM PDT 24 |
| Finished | Jul 30 08:29:55 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-0c3bec66-4379-47ec-9b8b-900a2b546995 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161677534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1161677534 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.4022167350 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 224884199 ps |
| CPU time | 10.41 seconds |
| Started | Jul 30 08:29:09 PM PDT 24 |
| Finished | Jul 30 08:29:20 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-00a18d71-5d10-4034-85e5-c975936ae9fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022167350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.4022167350 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.2950592554 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 5606923867 ps |
| CPU time | 61.69 seconds |
| Started | Jul 30 08:29:13 PM PDT 24 |
| Finished | Jul 30 08:30:14 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-9eddf08c-35f6-4647-a0ec-3e7211f649c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950592554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2950592554 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.1812568324 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 5337951262 ps |
| CPU time | 95.78 seconds |
| Started | Jul 30 08:29:19 PM PDT 24 |
| Finished | Jul 30 08:30:55 PM PDT 24 |
| Peak memory | 573960 kb |
| Host | smart-61fd6d5e-88c7-4a7f-8a09-9b8bcab664db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812568324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1812568324 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.3606296735 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 38803799 ps |
| CPU time | 6.3 seconds |
| Started | Jul 30 08:29:18 PM PDT 24 |
| Finished | Jul 30 08:29:25 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-4dc111d0-2d81-4958-b970-6db4dd29930c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606296735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .3606296735 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.2279961670 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 2275668079 ps |
| CPU time | 229.5 seconds |
| Started | Jul 30 08:29:28 PM PDT 24 |
| Finished | Jul 30 08:33:18 PM PDT 24 |
| Peak memory | 576132 kb |
| Host | smart-4891de40-5487-4567-a71f-fd53f98fe9bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279961670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2279961670 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.3699441221 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 6577664732 ps |
| CPU time | 240.32 seconds |
| Started | Jul 30 08:29:32 PM PDT 24 |
| Finished | Jul 30 08:33:32 PM PDT 24 |
| Peak memory | 576492 kb |
| Host | smart-098306a1-8154-4717-b527-06acaa30af3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699441221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3699441221 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.3621202507 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 154487821 ps |
| CPU time | 42.74 seconds |
| Started | Jul 30 08:29:32 PM PDT 24 |
| Finished | Jul 30 08:30:15 PM PDT 24 |
| Peak memory | 576368 kb |
| Host | smart-eebd9ee8-4dc4-49e2-a6f7-7a5f17b9edf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621202507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.3621202507 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3944080138 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 853872789 ps |
| CPU time | 257.51 seconds |
| Started | Jul 30 08:29:31 PM PDT 24 |
| Finished | Jul 30 08:33:49 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-e723fd14-3b94-403a-b007-bd7685fdb4e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944080138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.3944080138 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.2268543343 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 19355098 ps |
| CPU time | 5.84 seconds |
| Started | Jul 30 08:29:29 PM PDT 24 |
| Finished | Jul 30 08:29:35 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-fb4db8b3-6ad2-4136-97bf-4241dee8655f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268543343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2268543343 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.639617291 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 202944473 ps |
| CPU time | 16.23 seconds |
| Started | Jul 30 08:42:28 PM PDT 24 |
| Finished | Jul 30 08:42:45 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-2eeedb12-dc2e-4860-b2dd-3523113d438f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639617291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device. 639617291 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.1264398378 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 26964846425 ps |
| CPU time | 467.66 seconds |
| Started | Jul 30 08:42:28 PM PDT 24 |
| Finished | Jul 30 08:50:16 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-59aa37a2-fb55-435f-b239-41f019d7fbfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264398378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.1264398378 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.2496601720 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 561863071 ps |
| CPU time | 22.31 seconds |
| Started | Jul 30 08:42:40 PM PDT 24 |
| Finished | Jul 30 08:43:02 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-e0da9bd5-1806-4bb9-9a65-449efe724e0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496601720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.2496601720 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.2808976089 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 589254183 ps |
| CPU time | 22.99 seconds |
| Started | Jul 30 08:42:32 PM PDT 24 |
| Finished | Jul 30 08:42:55 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-7f1cfa7c-2353-4925-a719-deaacfbe808c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808976089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.2808976089 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.2653176949 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 806360975 ps |
| CPU time | 30.67 seconds |
| Started | Jul 30 08:42:33 PM PDT 24 |
| Finished | Jul 30 08:43:04 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-31701320-a042-4148-bfc3-1d9db55444ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653176949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.2653176949 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.2543403758 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 73178848824 ps |
| CPU time | 770.35 seconds |
| Started | Jul 30 08:42:28 PM PDT 24 |
| Finished | Jul 30 08:55:18 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-9bc12bac-aeb8-4de4-a590-e391ed4dd5d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543403758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.2543403758 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.3812637448 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 42991286344 ps |
| CPU time | 780.46 seconds |
| Started | Jul 30 08:42:28 PM PDT 24 |
| Finished | Jul 30 08:55:28 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-41f3ee52-172c-4f05-91f2-77cdd13ae4f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812637448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.3812637448 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.597470419 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 406213027 ps |
| CPU time | 41.41 seconds |
| Started | Jul 30 08:42:24 PM PDT 24 |
| Finished | Jul 30 08:43:05 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-5cc8fd8e-e83a-470f-aa79-604466f194c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597470419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_dela ys.597470419 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.236336098 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 545219753 ps |
| CPU time | 34.75 seconds |
| Started | Jul 30 08:42:26 PM PDT 24 |
| Finished | Jul 30 08:43:01 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-e74c167e-6288-49f4-b672-595f8e04e9f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236336098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.236336098 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.2826636903 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 262297549 ps |
| CPU time | 10.3 seconds |
| Started | Jul 30 08:42:33 PM PDT 24 |
| Finished | Jul 30 08:42:44 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-1e4f6e76-cace-4b58-aa68-b60b39846d2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826636903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.2826636903 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.2816272639 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 7355439343 ps |
| CPU time | 75.69 seconds |
| Started | Jul 30 08:42:24 PM PDT 24 |
| Finished | Jul 30 08:43:40 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-1f44a329-df42-4b13-8596-b9839d2289f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816272639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.2816272639 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.4162485041 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 3439221462 ps |
| CPU time | 62.7 seconds |
| Started | Jul 30 08:42:26 PM PDT 24 |
| Finished | Jul 30 08:43:29 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-230649d1-cabf-4003-9b27-3b9bdfcdffdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162485041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.4162485041 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2348204045 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 38937993 ps |
| CPU time | 5.73 seconds |
| Started | Jul 30 08:42:26 PM PDT 24 |
| Finished | Jul 30 08:42:32 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-cbd2428d-d8cc-4fea-9fb3-67acae6b1976 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348204045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.2348204045 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.4118578142 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1640215332 ps |
| CPU time | 154.15 seconds |
| Started | Jul 30 08:42:32 PM PDT 24 |
| Finished | Jul 30 08:45:07 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-1a76b050-605c-428e-b44f-f3612fd6c520 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118578142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.4118578142 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.3302378336 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 3125094770 ps |
| CPU time | 107.35 seconds |
| Started | Jul 30 08:42:31 PM PDT 24 |
| Finished | Jul 30 08:44:18 PM PDT 24 |
| Peak memory | 576160 kb |
| Host | smart-0d6b74a8-bcfc-4ef9-97b9-593e03517d0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302378336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.3302378336 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.126513736 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 3531503835 ps |
| CPU time | 133.69 seconds |
| Started | Jul 30 08:42:35 PM PDT 24 |
| Finished | Jul 30 08:44:49 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-42b292ce-2cb6-4335-ac50-7c6a058c7c2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126513736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_reset_error.126513736 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.895274095 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 193690232 ps |
| CPU time | 25.47 seconds |
| Started | Jul 30 08:42:33 PM PDT 24 |
| Finished | Jul 30 08:42:58 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-7ea5f148-c587-411d-9616-b698f3aad1fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895274095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.895274095 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.2437441668 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 2369977658 ps |
| CPU time | 113.57 seconds |
| Started | Jul 30 08:42:41 PM PDT 24 |
| Finished | Jul 30 08:44:34 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-05ee5c3f-f3b8-4d88-a786-7bec1b7080d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437441668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device .2437441668 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.3214877804 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 55620017746 ps |
| CPU time | 941.78 seconds |
| Started | Jul 30 08:42:41 PM PDT 24 |
| Finished | Jul 30 08:58:23 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-9b82c006-feb7-49db-9dfd-a3c231e3caf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214877804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.3214877804 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.2078987386 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 975134861 ps |
| CPU time | 39.59 seconds |
| Started | Jul 30 08:42:41 PM PDT 24 |
| Finished | Jul 30 08:43:21 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-7877deb9-5d23-419b-8ba5-533b5c67a581 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078987386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add r.2078987386 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.829625004 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 435932460 ps |
| CPU time | 39.32 seconds |
| Started | Jul 30 08:42:39 PM PDT 24 |
| Finished | Jul 30 08:43:18 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-64e5f9a5-90e4-4a0c-8e4f-540747e789cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829625004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.829625004 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.9370074 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 2024350028 ps |
| CPU time | 69.88 seconds |
| Started | Jul 30 08:42:36 PM PDT 24 |
| Finished | Jul 30 08:43:46 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-69a64da0-da60-4674-a940-f7fac14b67b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9370074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.9370074 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.996996047 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 47917632263 ps |
| CPU time | 533.52 seconds |
| Started | Jul 30 08:42:35 PM PDT 24 |
| Finished | Jul 30 08:51:29 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-64d80e7e-5c6d-4241-98f3-07b45f53593f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996996047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.996996047 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.1034824546 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 64380573361 ps |
| CPU time | 1163.51 seconds |
| Started | Jul 30 08:42:33 PM PDT 24 |
| Finished | Jul 30 09:01:57 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-6b592979-4ee5-4c05-b55c-3432a92d2d4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034824546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.1034824546 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.4245117368 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 252652588 ps |
| CPU time | 27.03 seconds |
| Started | Jul 30 08:42:40 PM PDT 24 |
| Finished | Jul 30 08:43:07 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-7bba152d-6605-4536-88ad-421ddf780823 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245117368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.4245117368 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.1945464634 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 257590657 ps |
| CPU time | 20.03 seconds |
| Started | Jul 30 08:42:42 PM PDT 24 |
| Finished | Jul 30 08:43:02 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-6fb8df75-e4e3-4d73-b700-7995e86f4f1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945464634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.1945464634 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.829810794 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 48472903 ps |
| CPU time | 6.35 seconds |
| Started | Jul 30 08:42:32 PM PDT 24 |
| Finished | Jul 30 08:42:39 PM PDT 24 |
| Peak memory | 573884 kb |
| Host | smart-c53d5f91-3362-49b6-9430-1991f58ea2f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829810794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.829810794 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.4138968951 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 8102336584 ps |
| CPU time | 88.88 seconds |
| Started | Jul 30 08:42:36 PM PDT 24 |
| Finished | Jul 30 08:44:05 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-0fcfe3fd-ca02-4c47-8153-54f5674a5f6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138968951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.4138968951 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1426499175 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 5400111813 ps |
| CPU time | 97.28 seconds |
| Started | Jul 30 08:42:35 PM PDT 24 |
| Finished | Jul 30 08:44:12 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-1b5a6654-90ee-4017-8e40-69ea601e9af8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426499175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.1426499175 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.3396365290 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 40490966 ps |
| CPU time | 6.14 seconds |
| Started | Jul 30 08:42:34 PM PDT 24 |
| Finished | Jul 30 08:42:40 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-c1239008-3e50-4680-b1f9-bf4124205c42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396365290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.3396365290 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.4097501771 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 4418806835 ps |
| CPU time | 338.58 seconds |
| Started | Jul 30 08:42:41 PM PDT 24 |
| Finished | Jul 30 08:48:20 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-decd731e-e6b0-43ef-a370-fa493dbabbbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097501771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.4097501771 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.1482447800 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 111216241 ps |
| CPU time | 67.05 seconds |
| Started | Jul 30 08:42:42 PM PDT 24 |
| Finished | Jul 30 08:43:49 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-31a05797-d29d-4d62-96e7-07c825957326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482447800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.1482447800 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.1033365464 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 142222898 ps |
| CPU time | 54.15 seconds |
| Started | Jul 30 08:42:44 PM PDT 24 |
| Finished | Jul 30 08:43:38 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-c84eb03e-6274-4c3b-9db6-5a21f2c9a59b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033365464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.1033365464 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.2012251444 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 420409889 ps |
| CPU time | 22.03 seconds |
| Started | Jul 30 08:42:42 PM PDT 24 |
| Finished | Jul 30 08:43:04 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-5c7db697-1ae2-44a7-b598-cd49f5f0dc4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012251444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.2012251444 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.1004770884 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 2455954846 ps |
| CPU time | 108.47 seconds |
| Started | Jul 30 08:42:48 PM PDT 24 |
| Finished | Jul 30 08:44:36 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-726fed1e-63c5-4817-b81a-7af8bb28cfab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004770884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device .1004770884 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.694641125 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 121165264691 ps |
| CPU time | 2105.04 seconds |
| Started | Jul 30 08:42:47 PM PDT 24 |
| Finished | Jul 30 09:17:52 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-eb73847d-514f-47cc-a4ea-d493ffbc1628 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694641125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_d evice_slow_rsp.694641125 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.462064580 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 21907166 ps |
| CPU time | 5.79 seconds |
| Started | Jul 30 08:42:55 PM PDT 24 |
| Finished | Jul 30 08:43:01 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-bd65f3ed-3914-4bf1-a628-eb6a8d9166ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462064580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_addr .462064580 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.2065641307 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 1984010858 ps |
| CPU time | 75.74 seconds |
| Started | Jul 30 08:42:50 PM PDT 24 |
| Finished | Jul 30 08:44:06 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-d8ee9eec-e8d9-4622-8d09-eceb8f89cbec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065641307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.2065641307 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.3576884532 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 989311269 ps |
| CPU time | 40.18 seconds |
| Started | Jul 30 08:42:44 PM PDT 24 |
| Finished | Jul 30 08:43:24 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-d22535d1-8c14-4650-b6b0-e9b614570ef6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576884532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.3576884532 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.1456382303 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 30962010502 ps |
| CPU time | 330.56 seconds |
| Started | Jul 30 08:42:48 PM PDT 24 |
| Finished | Jul 30 08:48:19 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-3b917c62-2ba8-4db5-b15e-559276adc06d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456382303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.1456382303 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.1460213431 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 18268464565 ps |
| CPU time | 314.86 seconds |
| Started | Jul 30 08:42:46 PM PDT 24 |
| Finished | Jul 30 08:48:01 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-d75795a6-aeb2-4ccf-8b8b-8b81f77be993 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460213431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.1460213431 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.2560676466 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 117325299 ps |
| CPU time | 12.79 seconds |
| Started | Jul 30 08:42:45 PM PDT 24 |
| Finished | Jul 30 08:42:58 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-0537cc66-926b-45ac-80be-c71bc7e8ee7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560676466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.2560676466 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.2935943092 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2060657169 ps |
| CPU time | 68.61 seconds |
| Started | Jul 30 08:42:46 PM PDT 24 |
| Finished | Jul 30 08:43:55 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-3c283e99-4f9f-4648-b12b-03eb69ddf2f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935943092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.2935943092 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.3192640394 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 42429681 ps |
| CPU time | 6.49 seconds |
| Started | Jul 30 08:42:43 PM PDT 24 |
| Finished | Jul 30 08:42:49 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-1f631860-36b7-4caa-bfcb-c9c0e35ccb0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192640394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.3192640394 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.4140495999 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 7956761489 ps |
| CPU time | 83.22 seconds |
| Started | Jul 30 08:42:45 PM PDT 24 |
| Finished | Jul 30 08:44:08 PM PDT 24 |
| Peak memory | 573896 kb |
| Host | smart-4654ff4b-dbe3-4cbe-ae7e-e77821201e6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140495999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.4140495999 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.482501831 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 5325056069 ps |
| CPU time | 94.23 seconds |
| Started | Jul 30 08:42:44 PM PDT 24 |
| Finished | Jul 30 08:44:18 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-77335419-fe20-4f92-a527-5a49156d60ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482501831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.482501831 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.345171232 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 39259560 ps |
| CPU time | 6.12 seconds |
| Started | Jul 30 08:42:47 PM PDT 24 |
| Finished | Jul 30 08:42:53 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-8a775649-847b-4a04-befb-7078c2162a7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345171232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delays .345171232 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.266373139 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 6304818 ps |
| CPU time | 3.84 seconds |
| Started | Jul 30 08:42:49 PM PDT 24 |
| Finished | Jul 30 08:42:53 PM PDT 24 |
| Peak memory | 565540 kb |
| Host | smart-01643bc7-46c2-4b2c-a9fc-186a2c9e078e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266373139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.266373139 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.1020584759 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 4197911470 ps |
| CPU time | 173.02 seconds |
| Started | Jul 30 08:42:49 PM PDT 24 |
| Finished | Jul 30 08:45:42 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-a3621f31-9a3f-4337-bbe8-963de898aad6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020584759 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.1020584759 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.2222663923 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 511566467 ps |
| CPU time | 243.42 seconds |
| Started | Jul 30 08:42:50 PM PDT 24 |
| Finished | Jul 30 08:46:53 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-9b37fa07-023e-4c45-929c-6099f823b34a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222663923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.2222663923 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.141212597 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 7638778438 ps |
| CPU time | 399.57 seconds |
| Started | Jul 30 08:42:56 PM PDT 24 |
| Finished | Jul 30 08:49:36 PM PDT 24 |
| Peak memory | 576888 kb |
| Host | smart-c46b59eb-8f41-4a10-ab6d-412bf252c199 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141212597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_reset_error.141212597 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.2091547978 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 1217545329 ps |
| CPU time | 50.98 seconds |
| Started | Jul 30 08:42:50 PM PDT 24 |
| Finished | Jul 30 08:43:41 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-a9cc96e0-05f5-4a3e-aa1c-5dddbcbae4fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091547978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.2091547978 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.3661074785 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 2230229724 ps |
| CPU time | 113.03 seconds |
| Started | Jul 30 08:42:58 PM PDT 24 |
| Finished | Jul 30 08:44:52 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-c2ea805d-4e68-4e14-a323-df6a84d09676 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661074785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .3661074785 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.3942300493 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 76903849827 ps |
| CPU time | 1407.38 seconds |
| Started | Jul 30 08:42:58 PM PDT 24 |
| Finished | Jul 30 09:06:25 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-86c5d600-258f-464c-9d0e-062ba3f85e38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942300493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.3942300493 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.2604497980 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 906180113 ps |
| CPU time | 40.99 seconds |
| Started | Jul 30 08:42:57 PM PDT 24 |
| Finished | Jul 30 08:43:38 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-e464ba54-2635-4783-9e5c-4c143eac6701 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604497980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.2604497980 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.1433889036 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 603577657 ps |
| CPU time | 56.21 seconds |
| Started | Jul 30 08:43:00 PM PDT 24 |
| Finished | Jul 30 08:43:56 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-db489f46-e5c0-49e5-88b8-aad74e85156b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433889036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.1433889036 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.3464314004 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 575670075 ps |
| CPU time | 48.98 seconds |
| Started | Jul 30 08:42:54 PM PDT 24 |
| Finished | Jul 30 08:43:43 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-4ac253e7-d896-46f5-8310-1e38e54c7b64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464314004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.3464314004 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.3017560502 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 11724239540 ps |
| CPU time | 128.69 seconds |
| Started | Jul 30 08:42:56 PM PDT 24 |
| Finished | Jul 30 08:45:04 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-d9c166f6-12b9-47df-bf56-cd29041d3fc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017560502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.3017560502 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.3561644074 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 23269593481 ps |
| CPU time | 400.14 seconds |
| Started | Jul 30 08:42:58 PM PDT 24 |
| Finished | Jul 30 08:49:38 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-8d682207-7911-44dc-8de4-2b4a3a0fcf08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561644074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.3561644074 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.1390911415 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 35003039 ps |
| CPU time | 6 seconds |
| Started | Jul 30 08:42:55 PM PDT 24 |
| Finished | Jul 30 08:43:01 PM PDT 24 |
| Peak memory | 573876 kb |
| Host | smart-c36249db-af9c-4ba1-939e-ae1ace7ea9ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390911415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del ays.1390911415 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.3350524016 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 416506754 ps |
| CPU time | 33.82 seconds |
| Started | Jul 30 08:43:06 PM PDT 24 |
| Finished | Jul 30 08:43:40 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-b6164b1b-58ac-4455-b91f-c6160d093671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350524016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.3350524016 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.1845163401 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 50893204 ps |
| CPU time | 6.96 seconds |
| Started | Jul 30 08:42:54 PM PDT 24 |
| Finished | Jul 30 08:43:01 PM PDT 24 |
| Peak memory | 573804 kb |
| Host | smart-7496a49e-5c82-4d52-81cf-0d0a2534650e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845163401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.1845163401 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.2441501559 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 9514794809 ps |
| CPU time | 99.42 seconds |
| Started | Jul 30 08:42:53 PM PDT 24 |
| Finished | Jul 30 08:44:32 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-4032e859-75f9-45ab-8e55-8b5314154ce5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441501559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.2441501559 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.310416394 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 4671051526 ps |
| CPU time | 84.65 seconds |
| Started | Jul 30 08:42:56 PM PDT 24 |
| Finished | Jul 30 08:44:20 PM PDT 24 |
| Peak memory | 573908 kb |
| Host | smart-487c5353-95a4-49d1-afe0-e0a11b98144b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310416394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.310416394 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.3189024729 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 54763351 ps |
| CPU time | 7.15 seconds |
| Started | Jul 30 08:42:55 PM PDT 24 |
| Finished | Jul 30 08:43:03 PM PDT 24 |
| Peak memory | 573844 kb |
| Host | smart-467e1748-a1c6-4a7f-8718-96f52aeb371f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189024729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay s.3189024729 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.2835670493 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 8542968159 ps |
| CPU time | 363.92 seconds |
| Started | Jul 30 08:42:59 PM PDT 24 |
| Finished | Jul 30 08:49:03 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-898fb3ac-b8d2-4cad-87cc-6e5b6a338895 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835670493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.2835670493 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.885494711 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 7280361867 ps |
| CPU time | 279.29 seconds |
| Started | Jul 30 08:43:02 PM PDT 24 |
| Finished | Jul 30 08:47:42 PM PDT 24 |
| Peak memory | 576348 kb |
| Host | smart-e9babb71-d018-450f-ad85-cab378e912b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885494711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.885494711 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.660253486 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 973172337 ps |
| CPU time | 398.6 seconds |
| Started | Jul 30 08:42:58 PM PDT 24 |
| Finished | Jul 30 08:49:36 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-6837fbfa-cf1a-4d07-b224-0b8455e2a382 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660253486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_ with_rand_reset.660253486 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.1827445768 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 1562048483 ps |
| CPU time | 308.76 seconds |
| Started | Jul 30 08:43:02 PM PDT 24 |
| Finished | Jul 30 08:48:11 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-c3d6f183-b820-4259-ae1e-cf119221ca3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827445768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.1827445768 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.4064402905 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 22231684 ps |
| CPU time | 5.85 seconds |
| Started | Jul 30 08:43:07 PM PDT 24 |
| Finished | Jul 30 08:43:13 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-b2c15e4c-6563-4509-bf1c-ed1d79e2e85c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064402905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.4064402905 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.4245692882 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 2646611764 ps |
| CPU time | 108.69 seconds |
| Started | Jul 30 08:43:12 PM PDT 24 |
| Finished | Jul 30 08:45:01 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-906aac3f-318f-45bd-a472-a99c2e4eb3bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245692882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .4245692882 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.2309448524 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 85601501219 ps |
| CPU time | 1506.7 seconds |
| Started | Jul 30 08:43:06 PM PDT 24 |
| Finished | Jul 30 09:08:12 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-f165e988-44f9-4fec-88d8-ea0fb32881ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309448524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_ device_slow_rsp.2309448524 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.2692498774 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 488420384 ps |
| CPU time | 25.39 seconds |
| Started | Jul 30 08:43:05 PM PDT 24 |
| Finished | Jul 30 08:43:30 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-7147347d-4c5e-4bf1-b1d3-d6ee1077762e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692498774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.2692498774 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.3088026927 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 126988242 ps |
| CPU time | 7.9 seconds |
| Started | Jul 30 08:43:10 PM PDT 24 |
| Finished | Jul 30 08:43:18 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-64fbbb80-3782-4adc-a62f-4f52789c2788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088026927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.3088026927 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.431656262 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 93851104263 ps |
| CPU time | 996.26 seconds |
| Started | Jul 30 08:43:04 PM PDT 24 |
| Finished | Jul 30 08:59:41 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-4df7c0ec-e24a-4278-8fed-1ba05b9b8d9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431656262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.431656262 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.1283317126 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 63388649858 ps |
| CPU time | 1137.9 seconds |
| Started | Jul 30 08:43:04 PM PDT 24 |
| Finished | Jul 30 09:02:02 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-aa7ca745-c2ec-48a0-85a4-2e9ad3d868d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283317126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.1283317126 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.3829102285 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 585561292 ps |
| CPU time | 46.47 seconds |
| Started | Jul 30 08:43:13 PM PDT 24 |
| Finished | Jul 30 08:43:59 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-5ea2b5c4-6b61-42cd-be86-dc01a7cacf01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829102285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.3829102285 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.2970032522 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 2084746632 ps |
| CPU time | 65.94 seconds |
| Started | Jul 30 08:43:06 PM PDT 24 |
| Finished | Jul 30 08:44:12 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-e7e4ff05-8902-42c0-b883-bfbe3b08aedc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970032522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.2970032522 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.76836831 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 195232706 ps |
| CPU time | 8.43 seconds |
| Started | Jul 30 08:43:09 PM PDT 24 |
| Finished | Jul 30 08:43:17 PM PDT 24 |
| Peak memory | 573884 kb |
| Host | smart-f0dd5c83-167a-4028-b5bf-6c7c841dbfa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76836831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.76836831 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.1238105641 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 6200217751 ps |
| CPU time | 64.59 seconds |
| Started | Jul 30 08:43:13 PM PDT 24 |
| Finished | Jul 30 08:44:17 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-b0f9ee0c-c2dc-4043-8fd4-de3a2e983b08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238105641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.1238105641 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.3372759136 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 4929559610 ps |
| CPU time | 83.41 seconds |
| Started | Jul 30 08:43:13 PM PDT 24 |
| Finished | Jul 30 08:44:37 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-cc593242-5355-45f5-bfe2-e138197cbe46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372759136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.3372759136 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.1940023818 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 44340597 ps |
| CPU time | 6.09 seconds |
| Started | Jul 30 08:43:01 PM PDT 24 |
| Finished | Jul 30 08:43:07 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-751b5b1f-7711-4138-85b7-850b232379c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940023818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay s.1940023818 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.576232663 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 3229748448 ps |
| CPU time | 272.23 seconds |
| Started | Jul 30 08:43:09 PM PDT 24 |
| Finished | Jul 30 08:47:42 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-64973232-a61d-448e-a14e-496c8c16a17a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576232663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.576232663 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.2056897239 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 614140371 ps |
| CPU time | 52.4 seconds |
| Started | Jul 30 08:43:04 PM PDT 24 |
| Finished | Jul 30 08:43:56 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-53b50b61-e34c-4736-98e8-ef2fdeb68cb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056897239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.2056897239 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.76888725 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 1254153609 ps |
| CPU time | 291.77 seconds |
| Started | Jul 30 08:43:06 PM PDT 24 |
| Finished | Jul 30 08:47:58 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-29bdf7ae-d494-492b-b98d-72ddfd4c4208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76888725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_w ith_rand_reset.76888725 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.2553848293 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 1748308683 ps |
| CPU time | 124.69 seconds |
| Started | Jul 30 08:43:13 PM PDT 24 |
| Finished | Jul 30 08:45:18 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-d7a7ba4e-82cc-4865-b5fa-7dff98648d93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553848293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.2553848293 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.1356950849 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 577941166 ps |
| CPU time | 27.82 seconds |
| Started | Jul 30 08:43:08 PM PDT 24 |
| Finished | Jul 30 08:43:36 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-35fcfa48-0865-4c25-bb9f-c9a0765f6485 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356950849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.1356950849 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.2615422610 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 1128656494 ps |
| CPU time | 60.04 seconds |
| Started | Jul 30 08:43:17 PM PDT 24 |
| Finished | Jul 30 08:44:17 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-76c2d9e8-0091-4e3f-9f5e-f538b813aa31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615422610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .2615422610 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.2629183351 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 52075485055 ps |
| CPU time | 919.46 seconds |
| Started | Jul 30 08:43:16 PM PDT 24 |
| Finished | Jul 30 08:58:36 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-7494682f-e757-43c7-8605-976a677cccfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629183351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.2629183351 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.2058923216 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 274456131 ps |
| CPU time | 12.4 seconds |
| Started | Jul 30 08:43:19 PM PDT 24 |
| Finished | Jul 30 08:43:31 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-732b0ac7-9e3f-4062-9537-8a01c5389913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058923216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add r.2058923216 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.1871927806 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 215439570 ps |
| CPU time | 21.85 seconds |
| Started | Jul 30 08:43:16 PM PDT 24 |
| Finished | Jul 30 08:43:38 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-15201aab-3428-4167-95ee-38cfffa6f793 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871927806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.1871927806 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.1428576902 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 643063145 ps |
| CPU time | 26.28 seconds |
| Started | Jul 30 08:43:14 PM PDT 24 |
| Finished | Jul 30 08:43:40 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-dbff7807-af85-4e1b-b446-b37730a11bbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428576902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.1428576902 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.232726328 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 82992736018 ps |
| CPU time | 845.51 seconds |
| Started | Jul 30 08:43:13 PM PDT 24 |
| Finished | Jul 30 08:57:19 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-8d5d19a0-a6ab-4de9-a29e-05690d1047a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232726328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.232726328 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.3390227241 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 23861944959 ps |
| CPU time | 414.41 seconds |
| Started | Jul 30 08:43:14 PM PDT 24 |
| Finished | Jul 30 08:50:08 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-ec0f592e-5582-49d7-a29f-d958241f66a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390227241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.3390227241 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.585865916 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 131333268 ps |
| CPU time | 13.78 seconds |
| Started | Jul 30 08:43:12 PM PDT 24 |
| Finished | Jul 30 08:43:25 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-344973a7-ce90-463b-bfe4-4025605fdff6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585865916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_dela ys.585865916 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.767466690 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 625703518 ps |
| CPU time | 20.98 seconds |
| Started | Jul 30 08:43:20 PM PDT 24 |
| Finished | Jul 30 08:43:41 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-7ccbe11d-faa2-4602-982e-3e03b64bd335 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767466690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.767466690 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.86259055 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 217067641 ps |
| CPU time | 9.72 seconds |
| Started | Jul 30 08:43:08 PM PDT 24 |
| Finished | Jul 30 08:43:18 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-cc6d5ed7-1b30-42c0-84d5-da4bdd6e913e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86259055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.86259055 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.3807128880 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 7399843093 ps |
| CPU time | 80.36 seconds |
| Started | Jul 30 08:43:14 PM PDT 24 |
| Finished | Jul 30 08:44:35 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-889f8d97-84c6-4630-aad4-24b6c446696c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807128880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.3807128880 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.1718607928 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 5119007086 ps |
| CPU time | 91.54 seconds |
| Started | Jul 30 08:43:12 PM PDT 24 |
| Finished | Jul 30 08:44:44 PM PDT 24 |
| Peak memory | 573924 kb |
| Host | smart-3d66f193-ebcf-4143-a962-1d359e703c36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718607928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.1718607928 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.1371019152 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 42556320 ps |
| CPU time | 7.03 seconds |
| Started | Jul 30 08:43:10 PM PDT 24 |
| Finished | Jul 30 08:43:17 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-23efa9cc-dddc-43cd-9c52-c77b6fd2ad7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371019152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.1371019152 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.1579793874 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 3560625723 ps |
| CPU time | 104.87 seconds |
| Started | Jul 30 08:43:22 PM PDT 24 |
| Finished | Jul 30 08:45:07 PM PDT 24 |
| Peak memory | 576136 kb |
| Host | smart-e1324582-fd4e-498f-96c9-1f19ad32639d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579793874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.1579793874 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.2965176645 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 1374329773 ps |
| CPU time | 52.33 seconds |
| Started | Jul 30 08:43:19 PM PDT 24 |
| Finished | Jul 30 08:44:11 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-aaae01ba-5370-4a78-986b-1b6248a3243a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965176645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.2965176645 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.2880540129 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 426003728 ps |
| CPU time | 154.5 seconds |
| Started | Jul 30 08:43:20 PM PDT 24 |
| Finished | Jul 30 08:45:54 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-1cf59a58-a04d-4d9d-90ee-e0a27b5175dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880540129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_rand_reset.2880540129 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.3838001038 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 3501582930 ps |
| CPU time | 182.56 seconds |
| Started | Jul 30 08:43:28 PM PDT 24 |
| Finished | Jul 30 08:46:31 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-ef17a1ce-9f46-4438-a4c9-d0b5ecdae037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838001038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.3838001038 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.3438293128 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 819425323 ps |
| CPU time | 35.98 seconds |
| Started | Jul 30 08:43:22 PM PDT 24 |
| Finished | Jul 30 08:43:59 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-d8c25263-1e87-42bf-a67b-5131ca7fa9b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438293128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.3438293128 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.2432618237 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 266765808 ps |
| CPU time | 12.36 seconds |
| Started | Jul 30 08:43:25 PM PDT 24 |
| Finished | Jul 30 08:43:38 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-a2b54a5c-e80a-4aae-aa02-2da2ec3595c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432618237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .2432618237 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.2615576652 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 57735680665 ps |
| CPU time | 1023.44 seconds |
| Started | Jul 30 08:43:23 PM PDT 24 |
| Finished | Jul 30 09:00:27 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-c109f8ee-7115-41e3-adf2-00d33a18b193 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615576652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_ device_slow_rsp.2615576652 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.3828889146 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 264315273 ps |
| CPU time | 31.35 seconds |
| Started | Jul 30 08:43:29 PM PDT 24 |
| Finished | Jul 30 08:44:00 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-d91191f2-3093-42c3-a29a-8d7cc446babd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828889146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.3828889146 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.3935698961 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 1408266230 ps |
| CPU time | 50.93 seconds |
| Started | Jul 30 08:43:27 PM PDT 24 |
| Finished | Jul 30 08:44:18 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-bb3f8295-e924-4f65-8385-8550b9f0e5a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935698961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.3935698961 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.3435464117 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 2311244126 ps |
| CPU time | 80.16 seconds |
| Started | Jul 30 08:43:22 PM PDT 24 |
| Finished | Jul 30 08:44:43 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-f8a3d9b2-76e3-47f7-8002-abef25779408 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435464117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.3435464117 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.2361853934 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 21643068959 ps |
| CPU time | 230.68 seconds |
| Started | Jul 30 08:43:21 PM PDT 24 |
| Finished | Jul 30 08:47:12 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-202e6b4b-50c2-4aa0-8b2d-9bb31bb42ecd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361853934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.2361853934 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.2693925626 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 51121677364 ps |
| CPU time | 886.72 seconds |
| Started | Jul 30 08:43:24 PM PDT 24 |
| Finished | Jul 30 08:58:11 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-22d41156-3d88-46d8-b68b-31fc8572d9fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693925626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.2693925626 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.3780495139 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 552431801 ps |
| CPU time | 53.15 seconds |
| Started | Jul 30 08:43:27 PM PDT 24 |
| Finished | Jul 30 08:44:20 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-63ab837f-c2c5-4e0f-949b-d28675c93adb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780495139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.3780495139 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.459637561 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2600686027 ps |
| CPU time | 88.63 seconds |
| Started | Jul 30 08:43:23 PM PDT 24 |
| Finished | Jul 30 08:44:52 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-1f87a8a7-674a-4c99-8ca3-f70cf49bd404 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459637561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.459637561 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.4008025481 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 57345841 ps |
| CPU time | 7.66 seconds |
| Started | Jul 30 08:43:29 PM PDT 24 |
| Finished | Jul 30 08:43:36 PM PDT 24 |
| Peak memory | 573908 kb |
| Host | smart-5d9e7b22-9427-4536-a145-f73092e72d05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008025481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.4008025481 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.3751658979 |
| Short name | T2927 |
| Test name | |
| Test status | |
| Simulation time | 7221301472 ps |
| CPU time | 77.15 seconds |
| Started | Jul 30 08:43:28 PM PDT 24 |
| Finished | Jul 30 08:44:45 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-67d6510a-4f38-41c4-8234-e0ca261863a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751658979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.3751658979 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.3429110399 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 4407565377 ps |
| CPU time | 80.13 seconds |
| Started | Jul 30 08:43:23 PM PDT 24 |
| Finished | Jul 30 08:44:43 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-0bea8114-b2a8-4dca-b116-c22a33bd3e31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429110399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.3429110399 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.2473796964 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 41315768 ps |
| CPU time | 6.19 seconds |
| Started | Jul 30 08:43:22 PM PDT 24 |
| Finished | Jul 30 08:43:28 PM PDT 24 |
| Peak memory | 573852 kb |
| Host | smart-e1f02bd4-4c50-468b-9a7f-30891fa12b15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473796964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay s.2473796964 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.90421174 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1118525569 ps |
| CPU time | 125.78 seconds |
| Started | Jul 30 08:43:29 PM PDT 24 |
| Finished | Jul 30 08:45:35 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-39840a7e-3999-4ed0-9e0a-42dbf4db4836 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90421174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.90421174 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.693298175 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 1219879080 ps |
| CPU time | 115.27 seconds |
| Started | Jul 30 08:43:28 PM PDT 24 |
| Finished | Jul 30 08:45:23 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-2398b2dd-d823-4cd2-bc2e-a046f6a6493a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693298175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.693298175 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.480455033 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 6689145346 ps |
| CPU time | 734.62 seconds |
| Started | Jul 30 08:43:29 PM PDT 24 |
| Finished | Jul 30 08:55:44 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-332ee309-9796-4ff7-b814-7ee1fabbf5ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480455033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_ with_rand_reset.480455033 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.559363395 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 355451717 ps |
| CPU time | 109.68 seconds |
| Started | Jul 30 08:43:30 PM PDT 24 |
| Finished | Jul 30 08:45:20 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-20f64437-9963-4479-a32f-5a5c01d12429 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559363395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_reset_error.559363395 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.4041439275 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 361429471 ps |
| CPU time | 21.42 seconds |
| Started | Jul 30 08:43:24 PM PDT 24 |
| Finished | Jul 30 08:43:46 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-571dfa7d-cb1a-4e73-a920-604599f2d6d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041439275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.4041439275 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.1610074086 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 1559122117 ps |
| CPU time | 65.81 seconds |
| Started | Jul 30 08:43:35 PM PDT 24 |
| Finished | Jul 30 08:44:41 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-1bb13603-0898-40c4-8294-75dd96f9a8d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610074086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .1610074086 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.4110146271 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 112854106250 ps |
| CPU time | 2060.89 seconds |
| Started | Jul 30 08:43:37 PM PDT 24 |
| Finished | Jul 30 09:17:58 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-255bb0d3-11ee-4769-9ea1-fb499342b990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110146271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.4110146271 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.116744793 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 78170953 ps |
| CPU time | 7.54 seconds |
| Started | Jul 30 08:43:42 PM PDT 24 |
| Finished | Jul 30 08:43:49 PM PDT 24 |
| Peak memory | 573876 kb |
| Host | smart-29213f6c-f2a3-45af-a3fd-968b55bc9e6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116744793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_addr .116744793 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.3781696696 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 1058855930 ps |
| CPU time | 39.28 seconds |
| Started | Jul 30 08:43:40 PM PDT 24 |
| Finished | Jul 30 08:44:19 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-4fb6c356-791b-4855-89f2-b388ba25977f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781696696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.3781696696 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.1640776572 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 1725348724 ps |
| CPU time | 68.63 seconds |
| Started | Jul 30 08:43:36 PM PDT 24 |
| Finished | Jul 30 08:44:45 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-89db62ed-6b28-454a-9d5a-dae57386ed6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640776572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.1640776572 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.9620779 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 17495218028 ps |
| CPU time | 184.43 seconds |
| Started | Jul 30 08:43:35 PM PDT 24 |
| Finished | Jul 30 08:46:40 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-2dec18fa-1f60-41ef-a055-18c44885eb11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9620779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.9620779 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.2656262861 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 24483270198 ps |
| CPU time | 375.54 seconds |
| Started | Jul 30 08:43:44 PM PDT 24 |
| Finished | Jul 30 08:49:59 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-5af6dc7c-e4a7-4e12-9e19-3442b672a134 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656262861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.2656262861 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.856645092 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 358718394 ps |
| CPU time | 36.5 seconds |
| Started | Jul 30 08:43:36 PM PDT 24 |
| Finished | Jul 30 08:44:12 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-9070d9d9-bec7-4247-b191-5e19db5bf464 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856645092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_dela ys.856645092 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.1674675157 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 196902360 ps |
| CPU time | 13.53 seconds |
| Started | Jul 30 08:43:44 PM PDT 24 |
| Finished | Jul 30 08:43:57 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-9ea4afc0-9e3e-42e1-a45e-1553fb46b364 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674675157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.1674675157 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.3832597066 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 44969612 ps |
| CPU time | 6.35 seconds |
| Started | Jul 30 08:43:30 PM PDT 24 |
| Finished | Jul 30 08:43:36 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-59e377b5-7341-4470-8abd-5ed43f4c99ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832597066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.3832597066 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.2152412522 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 9047092910 ps |
| CPU time | 92.12 seconds |
| Started | Jul 30 08:43:34 PM PDT 24 |
| Finished | Jul 30 08:45:06 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-99612f5d-b442-491d-9615-c1bbf9c3eaa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152412522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.2152412522 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.431507496 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 4367244395 ps |
| CPU time | 77.91 seconds |
| Started | Jul 30 08:43:36 PM PDT 24 |
| Finished | Jul 30 08:44:54 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-0bd59e0e-488d-4ea9-9534-a61e351bcce5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431507496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.431507496 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.739922559 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 46769901 ps |
| CPU time | 6.51 seconds |
| Started | Jul 30 08:43:31 PM PDT 24 |
| Finished | Jul 30 08:43:37 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-7220d44b-0a54-4654-9d2f-1f2719cfb8a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739922559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delays .739922559 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.994729306 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 1753970555 ps |
| CPU time | 147.31 seconds |
| Started | Jul 30 08:43:40 PM PDT 24 |
| Finished | Jul 30 08:46:08 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-15aff6fd-fb7d-4662-8237-c4159b79d9bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994729306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.994729306 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.3256672526 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 1237702529 ps |
| CPU time | 122.37 seconds |
| Started | Jul 30 08:43:42 PM PDT 24 |
| Finished | Jul 30 08:45:44 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-d8267989-2b3e-43fe-8fea-7175255c4eec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256672526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.3256672526 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2428330238 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 6775116159 ps |
| CPU time | 437.98 seconds |
| Started | Jul 30 08:43:38 PM PDT 24 |
| Finished | Jul 30 08:50:56 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-eadccf90-4a1a-4190-a6bd-66ac374ed9c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428330238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.2428330238 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.3942176736 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 808244608 ps |
| CPU time | 207.39 seconds |
| Started | Jul 30 08:43:38 PM PDT 24 |
| Finished | Jul 30 08:47:05 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-910c9e38-3218-493f-a8f0-636588857bfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942176736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.3942176736 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.3804584504 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 231192143 ps |
| CPU time | 27.53 seconds |
| Started | Jul 30 08:43:38 PM PDT 24 |
| Finished | Jul 30 08:44:06 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-9604a6ef-ac5e-493e-ad58-5daf5e4d1a28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804584504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.3804584504 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.445981380 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 1217833377 ps |
| CPU time | 92.04 seconds |
| Started | Jul 30 08:43:48 PM PDT 24 |
| Finished | Jul 30 08:45:20 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-247d6eb8-98fe-4c25-b1b6-ac6ff7a4717d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445981380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device. 445981380 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.1055188384 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 65455199705 ps |
| CPU time | 1014.42 seconds |
| Started | Jul 30 08:44:01 PM PDT 24 |
| Finished | Jul 30 09:00:55 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-86123266-9702-4138-bb4a-e948d7d9da42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055188384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.1055188384 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.2833324814 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 116408160 ps |
| CPU time | 14.31 seconds |
| Started | Jul 30 08:44:00 PM PDT 24 |
| Finished | Jul 30 08:44:14 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-56c4b91d-5b7a-49fd-bbf1-12d84662b86d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833324814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.2833324814 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.2062605961 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 1814160967 ps |
| CPU time | 54.59 seconds |
| Started | Jul 30 08:44:00 PM PDT 24 |
| Finished | Jul 30 08:44:55 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-451f8f97-c9be-44a0-a70a-59191d70588c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062605961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.2062605961 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.2395722677 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 2470667350 ps |
| CPU time | 81.46 seconds |
| Started | Jul 30 08:43:41 PM PDT 24 |
| Finished | Jul 30 08:45:02 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-3666bcb0-b049-4fc4-b8c6-6fe8268d9d5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395722677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.2395722677 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.210028780 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 90893414934 ps |
| CPU time | 971.49 seconds |
| Started | Jul 30 08:43:48 PM PDT 24 |
| Finished | Jul 30 08:59:59 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-faa7d222-5dd0-4b64-93a1-39263b8fca66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210028780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.210028780 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.127808723 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 40462072068 ps |
| CPU time | 741.56 seconds |
| Started | Jul 30 08:43:45 PM PDT 24 |
| Finished | Jul 30 08:56:07 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-74afd055-3e69-43b2-ae02-62e100a3b80a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127808723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.127808723 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.3798878887 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 546090713 ps |
| CPU time | 53.44 seconds |
| Started | Jul 30 08:43:43 PM PDT 24 |
| Finished | Jul 30 08:44:37 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-f5b74c7c-3c13-4820-9499-359cad62a382 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798878887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del ays.3798878887 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.2254829083 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 269988451 ps |
| CPU time | 23.54 seconds |
| Started | Jul 30 08:43:50 PM PDT 24 |
| Finished | Jul 30 08:44:14 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-a692b53e-c7da-4e29-9d5d-12b97bcdd293 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254829083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.2254829083 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.779382935 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 52532521 ps |
| CPU time | 7.27 seconds |
| Started | Jul 30 08:43:41 PM PDT 24 |
| Finished | Jul 30 08:43:48 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-1100ffb2-5943-4688-a3b3-70d8837c7acc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779382935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.779382935 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.3278513311 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 5986806494 ps |
| CPU time | 63.3 seconds |
| Started | Jul 30 08:43:42 PM PDT 24 |
| Finished | Jul 30 08:44:46 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-f583b288-fc99-429f-9b50-32081de4f0f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278513311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.3278513311 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.1946689364 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 3452744076 ps |
| CPU time | 61.9 seconds |
| Started | Jul 30 08:43:44 PM PDT 24 |
| Finished | Jul 30 08:44:46 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-960a8a6f-5188-40f0-9503-2a6548b7ba32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946689364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.1946689364 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.311375382 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 48006422 ps |
| CPU time | 7.32 seconds |
| Started | Jul 30 08:43:42 PM PDT 24 |
| Finished | Jul 30 08:43:49 PM PDT 24 |
| Peak memory | 573844 kb |
| Host | smart-89934dfe-379e-4a44-8b2d-37af1417f636 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311375382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delays .311375382 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.4242429926 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 3144061682 ps |
| CPU time | 121.89 seconds |
| Started | Jul 30 08:44:02 PM PDT 24 |
| Finished | Jul 30 08:46:03 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-163c5901-2afb-4675-b992-13258bf59eed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242429926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.4242429926 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.3466365040 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 2502932119 ps |
| CPU time | 163.01 seconds |
| Started | Jul 30 08:44:02 PM PDT 24 |
| Finished | Jul 30 08:46:45 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-dc09e694-b907-4f4e-b011-6da236b7d49e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466365040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.3466365040 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.2352219917 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 1157920589 ps |
| CPU time | 449.28 seconds |
| Started | Jul 30 08:43:55 PM PDT 24 |
| Finished | Jul 30 08:51:25 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-a33caf53-928a-4f98-9247-8d481e065780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352219917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.2352219917 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.1292777833 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 60762791 ps |
| CPU time | 11.22 seconds |
| Started | Jul 30 08:43:51 PM PDT 24 |
| Finished | Jul 30 08:44:02 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-9272a920-d345-4e00-b2c2-de412cd487d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292777833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.1292777833 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.3366125889 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 425607073 ps |
| CPU time | 32.7 seconds |
| Started | Jul 30 08:43:57 PM PDT 24 |
| Finished | Jul 30 08:44:29 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-77ad258c-614f-4875-8f76-732adfbfa320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366125889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .3366125889 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.3998098617 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 29701791101 ps |
| CPU time | 517.27 seconds |
| Started | Jul 30 08:43:56 PM PDT 24 |
| Finished | Jul 30 08:52:34 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-f69d8816-27e1-47a8-9296-8a7f7a60ffb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998098617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.3998098617 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.148731611 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 122298486 ps |
| CPU time | 14.04 seconds |
| Started | Jul 30 08:44:02 PM PDT 24 |
| Finished | Jul 30 08:44:16 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-149bc4e7-9071-4412-8e9b-3a6cdc2b4364 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148731611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_addr .148731611 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.2437758930 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 597617271 ps |
| CPU time | 52.05 seconds |
| Started | Jul 30 08:43:59 PM PDT 24 |
| Finished | Jul 30 08:44:51 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-95c95e78-49b6-4af5-a96f-1648791e2af9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437758930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.2437758930 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.804701485 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 330394812 ps |
| CPU time | 32.42 seconds |
| Started | Jul 30 08:44:02 PM PDT 24 |
| Finished | Jul 30 08:44:35 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-cd7ab641-e525-4ab2-9a3e-8c29b1eb5d1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804701485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.804701485 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.3030430427 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 72011053685 ps |
| CPU time | 765.9 seconds |
| Started | Jul 30 08:43:56 PM PDT 24 |
| Finished | Jul 30 08:56:42 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-a603abc7-fb96-44fd-848c-0f4e77b8ed04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030430427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.3030430427 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.1542494398 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 3072006599 ps |
| CPU time | 51.88 seconds |
| Started | Jul 30 08:44:03 PM PDT 24 |
| Finished | Jul 30 08:44:55 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-18dc2a81-b7de-48d9-9d28-263dec74515f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542494398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.1542494398 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.3328273995 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 271027779 ps |
| CPU time | 27.85 seconds |
| Started | Jul 30 08:44:03 PM PDT 24 |
| Finished | Jul 30 08:44:31 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-5ab05b0d-dc5c-46ee-a37a-6a527549a5a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328273995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.3328273995 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.1954938157 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 325925979 ps |
| CPU time | 28.51 seconds |
| Started | Jul 30 08:43:57 PM PDT 24 |
| Finished | Jul 30 08:44:26 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-e0d65651-4307-4b5c-b9ff-5af9c195bb3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954938157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.1954938157 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.2792673332 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 42924332 ps |
| CPU time | 6.07 seconds |
| Started | Jul 30 08:43:55 PM PDT 24 |
| Finished | Jul 30 08:44:01 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-9f0ea64a-3ced-48f5-8a4c-96d6ec050650 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792673332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.2792673332 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.3814465548 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 8498910738 ps |
| CPU time | 92.61 seconds |
| Started | Jul 30 08:43:54 PM PDT 24 |
| Finished | Jul 30 08:45:27 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-f9a48e01-afb9-4452-9671-3760d085faf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814465548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.3814465548 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.719012688 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 3911786169 ps |
| CPU time | 65.7 seconds |
| Started | Jul 30 08:43:57 PM PDT 24 |
| Finished | Jul 30 08:45:03 PM PDT 24 |
| Peak memory | 573940 kb |
| Host | smart-33e628c7-3c31-46d4-bf10-71aa5d7488a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719012688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.719012688 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.831651040 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 58385751 ps |
| CPU time | 7.27 seconds |
| Started | Jul 30 08:43:54 PM PDT 24 |
| Finished | Jul 30 08:44:02 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-e8f5a8dd-b8c3-4a85-acd0-52704d3dd320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831651040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delays .831651040 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.2737050257 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 7407547430 ps |
| CPU time | 260.37 seconds |
| Started | Jul 30 08:43:57 PM PDT 24 |
| Finished | Jul 30 08:48:17 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-25e4746c-7e75-4e60-94fa-1824b1bb5e86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737050257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.2737050257 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.1316232602 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 1990001394 ps |
| CPU time | 77.65 seconds |
| Started | Jul 30 08:44:02 PM PDT 24 |
| Finished | Jul 30 08:45:20 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-5ac8be11-b939-46bb-8b17-69cc1660510a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316232602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.1316232602 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3290069326 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 10915605702 ps |
| CPU time | 642.27 seconds |
| Started | Jul 30 08:44:01 PM PDT 24 |
| Finished | Jul 30 08:54:44 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-f71b6f3e-8293-4ce7-9a3e-47b3c6017d9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290069326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.3290069326 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.3265018348 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 586889708 ps |
| CPU time | 188.65 seconds |
| Started | Jul 30 08:44:04 PM PDT 24 |
| Finished | Jul 30 08:47:13 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-89af4fef-cc4e-4c03-91d5-15ca7c7572b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265018348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.3265018348 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.2333141903 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 361713295 ps |
| CPU time | 18.66 seconds |
| Started | Jul 30 08:43:57 PM PDT 24 |
| Finished | Jul 30 08:44:16 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-e9db01f1-c5dd-4d72-9969-fd4ccedc2d23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333141903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.2333141903 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.1728391502 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 9173628312 ps |
| CPU time | 1007.2 seconds |
| Started | Jul 30 08:30:10 PM PDT 24 |
| Finished | Jul 30 08:46:58 PM PDT 24 |
| Peak memory | 651960 kb |
| Host | smart-3fc0baa2-6143-49b1-b040-a664f9e4c37c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728391502 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.1728391502 |
| Directory | /workspace/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.812732246 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 6207806667 ps |
| CPU time | 640.74 seconds |
| Started | Jul 30 08:30:01 PM PDT 24 |
| Finished | Jul 30 08:40:42 PM PDT 24 |
| Peak memory | 598912 kb |
| Host | smart-edfab1d0-d4b0-46d9-8990-d147f24a4ee2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812732246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.812732246 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.1598888383 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 15548436637 ps |
| CPU time | 1750 seconds |
| Started | Jul 30 08:29:37 PM PDT 24 |
| Finished | Jul 30 08:58:48 PM PDT 24 |
| Peak memory | 593308 kb |
| Host | smart-a052a32e-41d6-4e5d-884b-bf4d4b1f99f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598888383 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.1598888383 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.2988302158 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 3436745581 ps |
| CPU time | 199.93 seconds |
| Started | Jul 30 08:29:35 PM PDT 24 |
| Finished | Jul 30 08:32:55 PM PDT 24 |
| Peak memory | 603804 kb |
| Host | smart-67d0758d-5780-4fd8-8d62-842578ffc68b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988302158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.2988302158 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.3729758979 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 1261104999 ps |
| CPU time | 96.33 seconds |
| Started | Jul 30 08:29:55 PM PDT 24 |
| Finished | Jul 30 08:31:32 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-d3762fd7-6ba6-4fc5-a190-ddebeb51cad7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729758979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 3729758979 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.3456695718 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 97340546379 ps |
| CPU time | 1735.58 seconds |
| Started | Jul 30 08:29:55 PM PDT 24 |
| Finished | Jul 30 08:58:51 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-2fce9b1c-2be5-4b36-9a80-8b6b1a84fa5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456695718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.3456695718 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.2588205410 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 1120096405 ps |
| CPU time | 45.3 seconds |
| Started | Jul 30 08:29:58 PM PDT 24 |
| Finished | Jul 30 08:30:44 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-85e20269-7b56-4dda-9fcf-296434643d4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588205410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .2588205410 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.17175111 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 1704182770 ps |
| CPU time | 75.53 seconds |
| Started | Jul 30 08:29:56 PM PDT 24 |
| Finished | Jul 30 08:31:11 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-15b9e717-8c27-41b6-a53e-93c02a51f2cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17175111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.17175111 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.3000767919 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 154736848 ps |
| CPU time | 21.63 seconds |
| Started | Jul 30 08:29:51 PM PDT 24 |
| Finished | Jul 30 08:30:13 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-d77ea94c-97ff-4daa-9da2-e245dd2389b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000767919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.3000767919 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.303568458 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 16807888653 ps |
| CPU time | 169.98 seconds |
| Started | Jul 30 08:29:49 PM PDT 24 |
| Finished | Jul 30 08:32:39 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-c5c11e13-cf8f-44b6-8222-5d3d7fa58e2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303568458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.303568458 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.3658090127 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 61413902898 ps |
| CPU time | 1133.27 seconds |
| Started | Jul 30 08:29:53 PM PDT 24 |
| Finished | Jul 30 08:48:47 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-03f2e403-89d2-4144-9947-a798628401c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658090127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3658090127 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.486394666 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 299211000 ps |
| CPU time | 29.29 seconds |
| Started | Jul 30 08:29:49 PM PDT 24 |
| Finished | Jul 30 08:30:18 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-20236e5a-7731-4c17-a6dd-1bebc86278a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486394666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delay s.486394666 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.2259155858 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 1683720929 ps |
| CPU time | 53.4 seconds |
| Started | Jul 30 08:29:59 PM PDT 24 |
| Finished | Jul 30 08:30:53 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-c58d04ed-3fac-4139-8f70-012a36e0c106 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259155858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2259155858 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.3748097510 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 213416720 ps |
| CPU time | 10.02 seconds |
| Started | Jul 30 08:29:45 PM PDT 24 |
| Finished | Jul 30 08:29:55 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-d931fe5a-c01b-4553-bfe0-41abcbf7841d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748097510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3748097510 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.1069984163 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 7820028703 ps |
| CPU time | 82.48 seconds |
| Started | Jul 30 08:29:46 PM PDT 24 |
| Finished | Jul 30 08:31:08 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-88d646c7-745c-4f3a-99e5-e824e77e3f5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069984163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1069984163 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.2273893375 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 5569274978 ps |
| CPU time | 103.34 seconds |
| Started | Jul 30 08:29:48 PM PDT 24 |
| Finished | Jul 30 08:31:31 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-580d53f3-340a-4237-8dfa-c50d01dfb9f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273893375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2273893375 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.1873021711 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 40702742 ps |
| CPU time | 6.15 seconds |
| Started | Jul 30 08:29:48 PM PDT 24 |
| Finished | Jul 30 08:29:54 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-fb7b699e-c1ff-4752-9eb6-a96b141c53a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873021711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays .1873021711 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.2217662054 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 16750376858 ps |
| CPU time | 714.89 seconds |
| Started | Jul 30 08:30:01 PM PDT 24 |
| Finished | Jul 30 08:41:56 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-e06af88a-b652-4fb2-a89b-1cb33b9eefbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217662054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2217662054 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.1225703903 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 11871627258 ps |
| CPU time | 494.32 seconds |
| Started | Jul 30 08:30:01 PM PDT 24 |
| Finished | Jul 30 08:38:15 PM PDT 24 |
| Peak memory | 576828 kb |
| Host | smart-19bfb751-f269-42ba-bbd7-feefe3ef5ba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225703903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1225703903 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.274775515 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 3640231572 ps |
| CPU time | 214.49 seconds |
| Started | Jul 30 08:30:04 PM PDT 24 |
| Finished | Jul 30 08:33:39 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-b66753ea-0a6d-4a25-bcb0-b19030efcf22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274775515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_w ith_rand_reset.274775515 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.1981129462 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 5767230795 ps |
| CPU time | 344.86 seconds |
| Started | Jul 30 08:30:04 PM PDT 24 |
| Finished | Jul 30 08:35:49 PM PDT 24 |
| Peak memory | 576848 kb |
| Host | smart-5a9273bc-54fd-4882-bc29-3e0d39963ea5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981129462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.1981129462 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.1146526298 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 164040742 ps |
| CPU time | 23.11 seconds |
| Started | Jul 30 08:29:58 PM PDT 24 |
| Finished | Jul 30 08:30:21 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-55438767-6dcb-448f-9f17-865cb917291e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146526298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1146526298 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.701661475 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 1628666504 ps |
| CPU time | 58.17 seconds |
| Started | Jul 30 08:44:09 PM PDT 24 |
| Finished | Jul 30 08:45:08 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-ff59b39c-441d-4a70-b6cb-aa2ec2c25820 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701661475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device. 701661475 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.2392125862 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 75476598243 ps |
| CPU time | 1405.04 seconds |
| Started | Jul 30 08:44:09 PM PDT 24 |
| Finished | Jul 30 09:07:34 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-5931e1d5-59af-4b3c-830b-27cc08912d03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392125862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.2392125862 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2522803796 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 278357037 ps |
| CPU time | 31.87 seconds |
| Started | Jul 30 08:44:20 PM PDT 24 |
| Finished | Jul 30 08:44:52 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-12482cba-cfb0-4f5c-b9cb-8abe405faf9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522803796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.2522803796 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.2537843437 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 225676256 ps |
| CPU time | 21.97 seconds |
| Started | Jul 30 08:44:19 PM PDT 24 |
| Finished | Jul 30 08:44:41 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-76eaa7d4-4b98-4a6a-8ea4-5bf309907d1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537843437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.2537843437 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.1595993430 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 1311325197 ps |
| CPU time | 47.97 seconds |
| Started | Jul 30 08:44:05 PM PDT 24 |
| Finished | Jul 30 08:44:53 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-ef6630f2-5426-4b9f-b37d-bf20f684ba5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595993430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.1595993430 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.1656131460 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 20292757524 ps |
| CPU time | 207.95 seconds |
| Started | Jul 30 08:44:11 PM PDT 24 |
| Finished | Jul 30 08:47:39 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-3da29166-2e32-4f91-94cc-cacdf43e814a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656131460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.1656131460 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.1943183508 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 8759487736 ps |
| CPU time | 159.7 seconds |
| Started | Jul 30 08:44:09 PM PDT 24 |
| Finished | Jul 30 08:46:48 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-b8192268-cbaa-436a-965c-d300252c321c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943183508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.1943183508 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.1427908091 |
| Short name | T2924 |
| Test name | |
| Test status | |
| Simulation time | 73542476 ps |
| CPU time | 10.48 seconds |
| Started | Jul 30 08:44:05 PM PDT 24 |
| Finished | Jul 30 08:44:15 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-e70a629c-6caa-42d7-a281-e8fcfa23679e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427908091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.1427908091 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.1216223303 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 121044950 ps |
| CPU time | 11.22 seconds |
| Started | Jul 30 08:44:18 PM PDT 24 |
| Finished | Jul 30 08:44:30 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-44e9f786-ba4c-41be-96e4-4136378557bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216223303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.1216223303 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.1313341610 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 45661869 ps |
| CPU time | 6.08 seconds |
| Started | Jul 30 08:44:04 PM PDT 24 |
| Finished | Jul 30 08:44:10 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-7da8e95b-54c7-49ee-b813-c99f49aaf0fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313341610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.1313341610 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.4224730074 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 10387795012 ps |
| CPU time | 112.69 seconds |
| Started | Jul 30 08:44:02 PM PDT 24 |
| Finished | Jul 30 08:45:55 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-cbc5aa01-022d-43fe-84f5-771d993a2f29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224730074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.4224730074 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.1240512763 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 4766172586 ps |
| CPU time | 83.42 seconds |
| Started | Jul 30 08:44:06 PM PDT 24 |
| Finished | Jul 30 08:45:30 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-8c0a35f7-6b52-4107-96de-8a6559febce0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240512763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.1240512763 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.1739061498 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 52396290 ps |
| CPU time | 6.88 seconds |
| Started | Jul 30 08:44:04 PM PDT 24 |
| Finished | Jul 30 08:44:11 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-0a01cf02-ca2f-47bd-b0e4-82cf86522840 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739061498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.1739061498 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.2563576750 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 1650956843 ps |
| CPU time | 66.76 seconds |
| Started | Jul 30 08:44:13 PM PDT 24 |
| Finished | Jul 30 08:45:20 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-d3309ebb-7148-46be-b38b-dd840e88cb8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563576750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.2563576750 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.2761914965 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 6371827118 ps |
| CPU time | 229.56 seconds |
| Started | Jul 30 08:44:11 PM PDT 24 |
| Finished | Jul 30 08:48:01 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-f16485ec-3801-4ff6-8779-c95a232b022e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761914965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.2761914965 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.1656239442 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 475215317 ps |
| CPU time | 245.57 seconds |
| Started | Jul 30 08:44:11 PM PDT 24 |
| Finished | Jul 30 08:48:17 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-b18a1a41-aa17-40e0-a55d-381cb3e66c4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656239442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.1656239442 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.3405523404 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 416670993 ps |
| CPU time | 139.39 seconds |
| Started | Jul 30 08:44:12 PM PDT 24 |
| Finished | Jul 30 08:46:32 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-c7c4262d-7e94-4d6e-bf37-32a63b96df79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405523404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.3405523404 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.1714478423 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 36179724 ps |
| CPU time | 7.39 seconds |
| Started | Jul 30 08:44:12 PM PDT 24 |
| Finished | Jul 30 08:44:19 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-abc52eff-6d50-4d3e-8c69-4ff9523fb87b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714478423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.1714478423 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.2938619689 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 941796886 ps |
| CPU time | 77.57 seconds |
| Started | Jul 30 08:44:17 PM PDT 24 |
| Finished | Jul 30 08:45:35 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-79d99491-c693-47f0-92b8-0044d4d4abc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938619689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .2938619689 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2729749512 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 100266754581 ps |
| CPU time | 1657.47 seconds |
| Started | Jul 30 08:44:16 PM PDT 24 |
| Finished | Jul 30 09:11:54 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-4289763b-c12b-43ae-bebe-8547d83437fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729749512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.2729749512 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2810281467 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 69521750 ps |
| CPU time | 6.45 seconds |
| Started | Jul 30 08:44:22 PM PDT 24 |
| Finished | Jul 30 08:44:29 PM PDT 24 |
| Peak memory | 573940 kb |
| Host | smart-45f3cb46-4985-4d67-bce7-92aee2ec8b13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810281467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.2810281467 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.3026028264 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 569863688 ps |
| CPU time | 55.21 seconds |
| Started | Jul 30 08:44:24 PM PDT 24 |
| Finished | Jul 30 08:45:19 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-790b4748-496d-4b7b-a5bb-6b57564e40a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026028264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.3026028264 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.4218686997 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 743693787 ps |
| CPU time | 29.17 seconds |
| Started | Jul 30 08:44:20 PM PDT 24 |
| Finished | Jul 30 08:44:50 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-1beb454c-a5ad-4bbc-b6d3-7fe4cf82843d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218686997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.4218686997 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.4172055571 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 33856556235 ps |
| CPU time | 344.51 seconds |
| Started | Jul 30 08:44:17 PM PDT 24 |
| Finished | Jul 30 08:50:01 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-79cb7135-d950-4945-b95a-af8b78b307e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172055571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.4172055571 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.151879309 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 34513673523 ps |
| CPU time | 589.6 seconds |
| Started | Jul 30 08:44:19 PM PDT 24 |
| Finished | Jul 30 08:54:09 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-bf0d57f1-ae3d-483e-91ac-3dec71b7a381 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151879309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.151879309 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.2764691779 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 145324356 ps |
| CPU time | 17.25 seconds |
| Started | Jul 30 08:44:20 PM PDT 24 |
| Finished | Jul 30 08:44:38 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-c82e98a2-e78f-4015-b200-3e3ad97d2d9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764691779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.2764691779 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.1926286504 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 1331911858 ps |
| CPU time | 39.29 seconds |
| Started | Jul 30 08:44:18 PM PDT 24 |
| Finished | Jul 30 08:44:58 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-a4496e62-c144-4125-86c3-f7eb8e2d9930 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926286504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.1926286504 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.3656956641 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 219691017 ps |
| CPU time | 9.8 seconds |
| Started | Jul 30 08:44:19 PM PDT 24 |
| Finished | Jul 30 08:44:29 PM PDT 24 |
| Peak memory | 573828 kb |
| Host | smart-41ad10d2-d770-4b3b-a093-7649c326bd40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656956641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.3656956641 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.591676448 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 7801030148 ps |
| CPU time | 81 seconds |
| Started | Jul 30 08:44:15 PM PDT 24 |
| Finished | Jul 30 08:45:36 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-17d21455-62c9-4da6-be64-b9970e71326c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591676448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.591676448 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.4275508644 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 6292819729 ps |
| CPU time | 107.62 seconds |
| Started | Jul 30 08:44:16 PM PDT 24 |
| Finished | Jul 30 08:46:04 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-33ef9c18-edb4-4d7d-b84f-23db28a72e7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275508644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.4275508644 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.1283714903 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 59112240 ps |
| CPU time | 6.91 seconds |
| Started | Jul 30 08:44:18 PM PDT 24 |
| Finished | Jul 30 08:44:25 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-9c68eb29-e93a-4a33-976b-363bcbdbe6c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283714903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.1283714903 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.168644485 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 1805040212 ps |
| CPU time | 154.61 seconds |
| Started | Jul 30 08:44:24 PM PDT 24 |
| Finished | Jul 30 08:46:59 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-81fa4a44-f185-41d8-a2ae-13ca00d5d9c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168644485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.168644485 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.3790011334 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 8324412820 ps |
| CPU time | 321.77 seconds |
| Started | Jul 30 08:44:25 PM PDT 24 |
| Finished | Jul 30 08:49:47 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-1f9bf6e7-7168-4ece-8e40-3b2ce36bc992 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790011334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.3790011334 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.4207826885 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 429408509 ps |
| CPU time | 221.84 seconds |
| Started | Jul 30 08:44:29 PM PDT 24 |
| Finished | Jul 30 08:48:11 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-fb0b82b5-fe07-45ef-9388-c5c3bef6bc74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207826885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.4207826885 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.47687010 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 516761067 ps |
| CPU time | 173.21 seconds |
| Started | Jul 30 08:44:26 PM PDT 24 |
| Finished | Jul 30 08:47:19 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-731fede5-9800-4946-a5a8-eed4d5a00d6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47687010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_ with_reset_error.47687010 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.1371347935 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 781799008 ps |
| CPU time | 33.43 seconds |
| Started | Jul 30 08:44:23 PM PDT 24 |
| Finished | Jul 30 08:44:56 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-accdcb7d-ff36-482c-828a-de330f370683 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371347935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.1371347935 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.654316556 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 255216803 ps |
| CPU time | 11.3 seconds |
| Started | Jul 30 08:44:39 PM PDT 24 |
| Finished | Jul 30 08:44:50 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-431cc6ef-e837-4b92-bc21-950fd09e399d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654316556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device. 654316556 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.768050253 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 136049625045 ps |
| CPU time | 2365.36 seconds |
| Started | Jul 30 08:44:29 PM PDT 24 |
| Finished | Jul 30 09:23:55 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-4fd376b1-356b-443a-918d-04f50a21e669 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768050253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_d evice_slow_rsp.768050253 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.3170185370 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 1396928318 ps |
| CPU time | 52.97 seconds |
| Started | Jul 30 08:44:39 PM PDT 24 |
| Finished | Jul 30 08:45:32 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-cbf8dfdf-a8ee-4540-8d85-44e3091e0ef7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170185370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.3170185370 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.1318258679 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 70248984 ps |
| CPU time | 9.46 seconds |
| Started | Jul 30 08:44:33 PM PDT 24 |
| Finished | Jul 30 08:44:43 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-9b5c47cf-ccd5-4e07-8745-a76a10e232c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318258679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.1318258679 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.435521899 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 2604623350 ps |
| CPU time | 97.63 seconds |
| Started | Jul 30 08:44:29 PM PDT 24 |
| Finished | Jul 30 08:46:07 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-392a2549-068e-4869-9546-68ee25eb9943 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435521899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.435521899 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.3454001046 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 45004558826 ps |
| CPU time | 496.3 seconds |
| Started | Jul 30 08:44:39 PM PDT 24 |
| Finished | Jul 30 08:52:56 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-58936f11-0259-445a-a763-e5875d84a9e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454001046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.3454001046 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.89396032 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 47405196327 ps |
| CPU time | 786.25 seconds |
| Started | Jul 30 08:44:30 PM PDT 24 |
| Finished | Jul 30 08:57:37 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-875bb8d9-2e34-4c38-b759-503779aac52b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89396032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.89396032 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.394451355 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 140621151 ps |
| CPU time | 16.53 seconds |
| Started | Jul 30 08:44:31 PM PDT 24 |
| Finished | Jul 30 08:44:48 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-33e8493f-e8fb-4739-97db-61284eb51908 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394451355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_dela ys.394451355 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.2391844610 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 407610858 ps |
| CPU time | 13.73 seconds |
| Started | Jul 30 08:44:35 PM PDT 24 |
| Finished | Jul 30 08:44:48 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-1eb55431-c413-42fe-b23f-151366974aba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391844610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.2391844610 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.3482773080 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 44631331 ps |
| CPU time | 6.22 seconds |
| Started | Jul 30 08:44:26 PM PDT 24 |
| Finished | Jul 30 08:44:32 PM PDT 24 |
| Peak memory | 573828 kb |
| Host | smart-8b3e430b-379d-48ec-a073-bd8d211a3262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482773080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.3482773080 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.3596337722 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 10277053089 ps |
| CPU time | 112.46 seconds |
| Started | Jul 30 08:44:29 PM PDT 24 |
| Finished | Jul 30 08:46:21 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-d996a277-c801-4d68-a5e2-9dc88aad08d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596337722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.3596337722 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.1812155845 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 4760290674 ps |
| CPU time | 79.89 seconds |
| Started | Jul 30 08:44:30 PM PDT 24 |
| Finished | Jul 30 08:45:50 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-59d49e93-6d8f-478c-86dd-dac3a2bf283d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812155845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.1812155845 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.759658724 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 46913055 ps |
| CPU time | 6.54 seconds |
| Started | Jul 30 08:44:32 PM PDT 24 |
| Finished | Jul 30 08:44:38 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-608a3dad-efae-4a33-bdab-ebf14a561c45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759658724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delays .759658724 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.410958496 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 3699208715 ps |
| CPU time | 282.01 seconds |
| Started | Jul 30 08:44:39 PM PDT 24 |
| Finished | Jul 30 08:49:22 PM PDT 24 |
| Peak memory | 576840 kb |
| Host | smart-8e70a610-bba3-4af2-bdb7-a3937ccbedac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410958496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.410958496 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.3719325502 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 2330731023 ps |
| CPU time | 176.27 seconds |
| Started | Jul 30 08:44:32 PM PDT 24 |
| Finished | Jul 30 08:47:28 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-805a0bdf-16d2-42cc-9f61-9b8ab6feb098 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719325502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.3719325502 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.2679066569 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 316057730 ps |
| CPU time | 161.33 seconds |
| Started | Jul 30 08:44:33 PM PDT 24 |
| Finished | Jul 30 08:47:14 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-bcc464f7-8185-4371-8326-58719ae60771 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679066569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.2679066569 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.39056890 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 156344393 ps |
| CPU time | 40.34 seconds |
| Started | Jul 30 08:44:39 PM PDT 24 |
| Finished | Jul 30 08:45:19 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-71939317-5fca-471c-a5f6-a4b4f6170cc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39056890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_ with_reset_error.39056890 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.363332532 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 779129103 ps |
| CPU time | 36.04 seconds |
| Started | Jul 30 08:44:35 PM PDT 24 |
| Finished | Jul 30 08:45:11 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-7268dc48-6de2-44e3-85ac-b3b7eb8337ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363332532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.363332532 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.4204953807 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 3039873365 ps |
| CPU time | 120.7 seconds |
| Started | Jul 30 08:44:39 PM PDT 24 |
| Finished | Jul 30 08:46:39 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-b366fdec-a464-45df-ad88-b502e6a6f066 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204953807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .4204953807 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.1849283940 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 51167146685 ps |
| CPU time | 922.25 seconds |
| Started | Jul 30 08:44:41 PM PDT 24 |
| Finished | Jul 30 09:00:03 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-a5221bb2-eb68-4852-90c3-632ce778c549 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849283940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.1849283940 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.539842545 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 639230290 ps |
| CPU time | 27.42 seconds |
| Started | Jul 30 08:44:44 PM PDT 24 |
| Finished | Jul 30 08:45:12 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-a59e06a6-4cb2-4aac-8b15-9176f82226ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539842545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_addr .539842545 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.808482965 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 399059905 ps |
| CPU time | 39.19 seconds |
| Started | Jul 30 08:44:41 PM PDT 24 |
| Finished | Jul 30 08:45:21 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-781c1db1-2db4-4ff4-a18f-cd1586bf33c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808482965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.808482965 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.3034739154 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 377056103 ps |
| CPU time | 32.69 seconds |
| Started | Jul 30 08:44:41 PM PDT 24 |
| Finished | Jul 30 08:45:14 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-bf96280f-71b6-4937-b3ce-15cc7cb136f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034739154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.3034739154 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.475560649 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 66211108286 ps |
| CPU time | 699.2 seconds |
| Started | Jul 30 08:44:37 PM PDT 24 |
| Finished | Jul 30 08:56:16 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-c22d3ef5-d7cf-4601-9c3c-d09109b7b388 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475560649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.475560649 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.3965160087 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 23936010813 ps |
| CPU time | 426.83 seconds |
| Started | Jul 30 08:44:35 PM PDT 24 |
| Finished | Jul 30 08:51:42 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-e4fdc25d-aed1-4a14-b0a7-12d7fdc4e1d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965160087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.3965160087 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.1008113582 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 424955831 ps |
| CPU time | 38.84 seconds |
| Started | Jul 30 08:44:39 PM PDT 24 |
| Finished | Jul 30 08:45:18 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-d006b703-a684-444c-b0bf-d3be6021f066 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008113582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.1008113582 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.3928367984 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 91723013 ps |
| CPU time | 10.2 seconds |
| Started | Jul 30 08:44:42 PM PDT 24 |
| Finished | Jul 30 08:44:53 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-ed2ea7ce-9264-43dd-a5cf-3fc491595d51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928367984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.3928367984 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.601079403 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 192462969 ps |
| CPU time | 9.23 seconds |
| Started | Jul 30 08:44:34 PM PDT 24 |
| Finished | Jul 30 08:44:43 PM PDT 24 |
| Peak memory | 574576 kb |
| Host | smart-9f313fb7-9ae3-4144-8855-fa51dcc2b63a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601079403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.601079403 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.4284473320 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 6616369261 ps |
| CPU time | 71.07 seconds |
| Started | Jul 30 08:44:38 PM PDT 24 |
| Finished | Jul 30 08:45:49 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-435b197e-2302-4f5c-994e-f85ed6f0279d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284473320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.4284473320 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1947083282 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 4708310513 ps |
| CPU time | 84.15 seconds |
| Started | Jul 30 08:44:39 PM PDT 24 |
| Finished | Jul 30 08:46:03 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-ac453afb-b01b-4fda-b485-8df114e17e0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947083282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.1947083282 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.2520123111 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 37988348 ps |
| CPU time | 5.71 seconds |
| Started | Jul 30 08:44:32 PM PDT 24 |
| Finished | Jul 30 08:44:38 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-2f6fab4d-9577-4e4e-b1be-2fb67a70e410 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520123111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.2520123111 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.301620099 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 6220089216 ps |
| CPU time | 252.34 seconds |
| Started | Jul 30 08:44:45 PM PDT 24 |
| Finished | Jul 30 08:48:58 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-f2e674f4-2c89-46e7-9831-ac71a008039f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301620099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.301620099 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.37851395 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 3338602738 ps |
| CPU time | 110.57 seconds |
| Started | Jul 30 08:44:50 PM PDT 24 |
| Finished | Jul 30 08:46:41 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-c534d026-7bc6-4d01-9860-25955eb0ffdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37851395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.37851395 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.1522701920 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 52079810 ps |
| CPU time | 56.94 seconds |
| Started | Jul 30 08:44:43 PM PDT 24 |
| Finished | Jul 30 08:45:41 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-2609029f-e17d-45bb-9ed7-7d28a0791737 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522701920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.1522701920 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.1936554384 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 8148841618 ps |
| CPU time | 495.06 seconds |
| Started | Jul 30 08:44:48 PM PDT 24 |
| Finished | Jul 30 08:53:03 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-c1be1326-4b4d-427f-b7be-23f303bef480 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936554384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.1936554384 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.1869055304 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 1029658670 ps |
| CPU time | 50.65 seconds |
| Started | Jul 30 08:44:40 PM PDT 24 |
| Finished | Jul 30 08:45:31 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-bf5d07d3-dd12-407f-8d65-67646666e48c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869055304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.1869055304 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.2768346153 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 1502760611 ps |
| CPU time | 66.77 seconds |
| Started | Jul 30 08:44:50 PM PDT 24 |
| Finished | Jul 30 08:45:57 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-c827f132-cb33-42a6-8f53-6107ff6cce9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768346153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .2768346153 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.3356375116 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 122102621059 ps |
| CPU time | 2192.19 seconds |
| Started | Jul 30 08:44:55 PM PDT 24 |
| Finished | Jul 30 09:21:27 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-39b2581a-a775-4ace-afe4-7e276d72bbbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356375116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.3356375116 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3958910297 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 973338554 ps |
| CPU time | 40.95 seconds |
| Started | Jul 30 08:44:55 PM PDT 24 |
| Finished | Jul 30 08:45:36 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-8a6411e7-6f85-4b6b-9458-097010d00c00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958910297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.3958910297 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.3381344342 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 1016701733 ps |
| CPU time | 44.11 seconds |
| Started | Jul 30 08:44:57 PM PDT 24 |
| Finished | Jul 30 08:45:42 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-3cf29774-41fe-476b-bf48-1e768e76bce1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381344342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.3381344342 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.1674151975 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 735767151 ps |
| CPU time | 29.58 seconds |
| Started | Jul 30 08:44:52 PM PDT 24 |
| Finished | Jul 30 08:45:21 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-b5313540-4d54-4cb2-a09f-1221d3cd9cd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674151975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.1674151975 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.2880913559 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 43659405828 ps |
| CPU time | 479.01 seconds |
| Started | Jul 30 08:44:51 PM PDT 24 |
| Finished | Jul 30 08:52:50 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-a66e1949-b406-4b66-be7e-092977f9edce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880913559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.2880913559 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.3551605028 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 23979333537 ps |
| CPU time | 420.7 seconds |
| Started | Jul 30 08:44:54 PM PDT 24 |
| Finished | Jul 30 08:51:55 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-65f9d556-d064-4dd9-b286-4a3f5338c937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551605028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.3551605028 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.1694163908 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 390845816 ps |
| CPU time | 36.64 seconds |
| Started | Jul 30 08:44:51 PM PDT 24 |
| Finished | Jul 30 08:45:28 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-85a6aef9-5435-43b5-9134-dd0d41caec11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694163908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.1694163908 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.643623680 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 1472879098 ps |
| CPU time | 53.16 seconds |
| Started | Jul 30 08:44:57 PM PDT 24 |
| Finished | Jul 30 08:45:50 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-abeecbad-9156-4e0c-95a5-f5be31c181ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643623680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.643623680 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.757326076 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 45368331 ps |
| CPU time | 5.98 seconds |
| Started | Jul 30 08:44:43 PM PDT 24 |
| Finished | Jul 30 08:44:49 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-d33f32ed-54c3-4ef9-893b-607b429c8dfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757326076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.757326076 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.2226890924 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 6053708586 ps |
| CPU time | 67.48 seconds |
| Started | Jul 30 08:44:47 PM PDT 24 |
| Finished | Jul 30 08:45:54 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-33ee08e5-35e4-46f2-9a1c-6d77d23cfafa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226890924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.2226890924 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.1653684379 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 5348891426 ps |
| CPU time | 93.14 seconds |
| Started | Jul 30 08:44:53 PM PDT 24 |
| Finished | Jul 30 08:46:26 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-d3d73d58-8d8d-4bf1-9dca-e8166821b02c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653684379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.1653684379 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.984236066 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 43735430 ps |
| CPU time | 6.67 seconds |
| Started | Jul 30 08:44:47 PM PDT 24 |
| Finished | Jul 30 08:44:53 PM PDT 24 |
| Peak memory | 573876 kb |
| Host | smart-1b7887d4-4345-4016-a28d-8e24c8ad6ca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984236066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delays .984236066 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.2394283020 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 6177045588 ps |
| CPU time | 253.33 seconds |
| Started | Jul 30 08:44:55 PM PDT 24 |
| Finished | Jul 30 08:49:08 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-c7a70757-0a01-473f-8236-9a802e468bea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394283020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.2394283020 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.1815199322 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 881672310 ps |
| CPU time | 28.91 seconds |
| Started | Jul 30 08:44:58 PM PDT 24 |
| Finished | Jul 30 08:45:27 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-5667b1db-53d6-4939-b21d-be06333af89b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815199322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.1815199322 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.4126369842 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 388138666 ps |
| CPU time | 119.43 seconds |
| Started | Jul 30 08:45:01 PM PDT 24 |
| Finished | Jul 30 08:47:01 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-c01a2451-74ae-4dec-a39b-301e8f10b1e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126369842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.4126369842 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.2747524043 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 3053593854 ps |
| CPU time | 428.65 seconds |
| Started | Jul 30 08:44:59 PM PDT 24 |
| Finished | Jul 30 08:52:08 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-e29eb65c-37c9-4a63-aec3-debfa2065c10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747524043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.2747524043 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.3393930094 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 30403447 ps |
| CPU time | 7.17 seconds |
| Started | Jul 30 08:44:55 PM PDT 24 |
| Finished | Jul 30 08:45:02 PM PDT 24 |
| Peak memory | 573964 kb |
| Host | smart-1c83f7be-d6bc-42b6-a2f6-65f73f4a5160 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393930094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.3393930094 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.683474105 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 759808162 ps |
| CPU time | 57.2 seconds |
| Started | Jul 30 08:45:02 PM PDT 24 |
| Finished | Jul 30 08:45:59 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-5676dc8f-ebff-4818-acee-c1494b306ea1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683474105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device. 683474105 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.4075056768 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 42157996739 ps |
| CPU time | 812.15 seconds |
| Started | Jul 30 08:45:03 PM PDT 24 |
| Finished | Jul 30 08:58:35 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-f9b2acf7-2f01-4159-a163-a7ee27cd1fca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075056768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.4075056768 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.2799848847 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 322350452 ps |
| CPU time | 32.5 seconds |
| Started | Jul 30 08:45:07 PM PDT 24 |
| Finished | Jul 30 08:45:40 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-1efab8cf-a248-48f3-9c34-ed0c76091772 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799848847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.2799848847 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.1883681329 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 360212138 ps |
| CPU time | 34.37 seconds |
| Started | Jul 30 08:45:02 PM PDT 24 |
| Finished | Jul 30 08:45:36 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-f344600f-a983-441b-8c24-a17a14f695a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883681329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.1883681329 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.681645366 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 292265194 ps |
| CPU time | 15.19 seconds |
| Started | Jul 30 08:45:01 PM PDT 24 |
| Finished | Jul 30 08:45:17 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-17d2da14-d009-4683-b046-e14dbee2776f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681645366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.681645366 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.1616657508 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 27620418287 ps |
| CPU time | 312.23 seconds |
| Started | Jul 30 08:45:01 PM PDT 24 |
| Finished | Jul 30 08:50:14 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-8c1bca94-4f8c-44da-8b3d-9f7720d3de5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616657508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.1616657508 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.225224239 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 6400188442 ps |
| CPU time | 108.09 seconds |
| Started | Jul 30 08:45:04 PM PDT 24 |
| Finished | Jul 30 08:46:52 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-b304b503-9994-4076-90bd-495738a96e7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225224239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.225224239 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.920749480 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 496910176 ps |
| CPU time | 42.99 seconds |
| Started | Jul 30 08:45:03 PM PDT 24 |
| Finished | Jul 30 08:45:46 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-f09f614a-ebb8-49d6-bd5c-a90eb9f4cc6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920749480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_dela ys.920749480 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.3496894594 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 2299041477 ps |
| CPU time | 71.29 seconds |
| Started | Jul 30 08:45:03 PM PDT 24 |
| Finished | Jul 30 08:46:15 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-7cd84153-096e-4793-8ca4-2590c1586dad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496894594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.3496894594 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.602588568 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 38273042 ps |
| CPU time | 6.1 seconds |
| Started | Jul 30 08:45:01 PM PDT 24 |
| Finished | Jul 30 08:45:07 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-037031a3-59b9-41ba-ae72-6b9079625595 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602588568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.602588568 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.624077428 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 8884399742 ps |
| CPU time | 95.24 seconds |
| Started | Jul 30 08:45:02 PM PDT 24 |
| Finished | Jul 30 08:46:37 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-67854cb6-eeed-4900-a18e-f3762c7e8a61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624077428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.624077428 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.335839549 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 5713793076 ps |
| CPU time | 102.82 seconds |
| Started | Jul 30 08:45:04 PM PDT 24 |
| Finished | Jul 30 08:46:46 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-10c7711a-9bbf-4f9c-9bb2-be8bbbeb9ab7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335839549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.335839549 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2973560787 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 44570264 ps |
| CPU time | 6.31 seconds |
| Started | Jul 30 08:45:04 PM PDT 24 |
| Finished | Jul 30 08:45:10 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-52778218-9c23-4ad5-bd78-7f6b1c9e5081 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973560787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.2973560787 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.2227014669 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 9571365392 ps |
| CPU time | 345.13 seconds |
| Started | Jul 30 08:45:05 PM PDT 24 |
| Finished | Jul 30 08:50:50 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-866fcbc5-befa-43c1-9568-8ea6ff2cc542 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227014669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.2227014669 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.750805215 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 1912009830 ps |
| CPU time | 160.72 seconds |
| Started | Jul 30 08:45:07 PM PDT 24 |
| Finished | Jul 30 08:47:48 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-4d46c25c-b2fb-4b03-af83-e2b5d42ed717 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750805215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.750805215 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.1432008749 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 4594378330 ps |
| CPU time | 206.61 seconds |
| Started | Jul 30 08:45:08 PM PDT 24 |
| Finished | Jul 30 08:48:35 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-16ee066b-1bbd-4ac2-884f-f81daa2c1830 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432008749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.1432008749 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.2409139998 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 105692471 ps |
| CPU time | 37.43 seconds |
| Started | Jul 30 08:45:04 PM PDT 24 |
| Finished | Jul 30 08:45:42 PM PDT 24 |
| Peak memory | 576140 kb |
| Host | smart-4c0cd215-64a0-48fb-8ff4-21a9bbbb38e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409139998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.2409139998 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.4248645572 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 45561690 ps |
| CPU time | 8.77 seconds |
| Started | Jul 30 08:45:07 PM PDT 24 |
| Finished | Jul 30 08:45:15 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-1e5f6d29-eb1e-40fd-8d62-0203c48fd1fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248645572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.4248645572 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.3448316219 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 449522478 ps |
| CPU time | 39.31 seconds |
| Started | Jul 30 08:45:14 PM PDT 24 |
| Finished | Jul 30 08:45:53 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-421c54ae-ac2a-47ec-a25f-76de8bbd7aa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448316219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .3448316219 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3626045149 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 25307759760 ps |
| CPU time | 437.52 seconds |
| Started | Jul 30 08:45:10 PM PDT 24 |
| Finished | Jul 30 08:52:27 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-8f04741d-62b8-4cf8-9031-a90396e92dd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626045149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.3626045149 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.1323923735 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 692488324 ps |
| CPU time | 33.32 seconds |
| Started | Jul 30 08:45:15 PM PDT 24 |
| Finished | Jul 30 08:45:48 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-610c6f4b-8cbd-43ec-96fd-0c7069bca617 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323923735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.1323923735 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.1563691536 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 194645481 ps |
| CPU time | 16.76 seconds |
| Started | Jul 30 08:45:14 PM PDT 24 |
| Finished | Jul 30 08:45:31 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-90763f96-d7a5-4962-b8a8-717c62f3f13e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563691536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.1563691536 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.106994917 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 1515286649 ps |
| CPU time | 59.79 seconds |
| Started | Jul 30 08:45:10 PM PDT 24 |
| Finished | Jul 30 08:46:10 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-0a9af7bc-f18b-4ef0-bb11-03fe62d13182 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106994917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.106994917 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.3428569686 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 5700176745 ps |
| CPU time | 59.3 seconds |
| Started | Jul 30 08:45:11 PM PDT 24 |
| Finished | Jul 30 08:46:10 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-314bdd1a-b65a-40d3-8511-ec91db5499d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428569686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.3428569686 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.145155978 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 30191543428 ps |
| CPU time | 507.71 seconds |
| Started | Jul 30 08:45:13 PM PDT 24 |
| Finished | Jul 30 08:53:41 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-dda89200-6fd6-40cf-ae19-e6ce306a6445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145155978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.145155978 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.3949346583 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 303347286 ps |
| CPU time | 33.44 seconds |
| Started | Jul 30 08:45:09 PM PDT 24 |
| Finished | Jul 30 08:45:42 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-f4e8a89a-1beb-4127-ae41-b2228418097f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949346583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del ays.3949346583 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.2602232884 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 772600535 ps |
| CPU time | 25.22 seconds |
| Started | Jul 30 08:45:08 PM PDT 24 |
| Finished | Jul 30 08:45:33 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-7a7c1895-1709-4d19-af68-f0dce0b8c270 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602232884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.2602232884 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.2570903525 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 197143713 ps |
| CPU time | 9.29 seconds |
| Started | Jul 30 08:45:07 PM PDT 24 |
| Finished | Jul 30 08:45:16 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-72abd0bd-475b-4696-9f02-77223ef2b59e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570903525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.2570903525 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.2486981430 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 8777245341 ps |
| CPU time | 94.68 seconds |
| Started | Jul 30 08:45:06 PM PDT 24 |
| Finished | Jul 30 08:46:41 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-384a8493-b926-40ec-a942-468cb969c214 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486981430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.2486981430 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.348469370 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 4227420785 ps |
| CPU time | 71.86 seconds |
| Started | Jul 30 08:45:06 PM PDT 24 |
| Finished | Jul 30 08:46:18 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-8f281a78-5ed2-4978-a645-0ae3219e627a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348469370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.348469370 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.399636964 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 40800038 ps |
| CPU time | 6.22 seconds |
| Started | Jul 30 08:45:06 PM PDT 24 |
| Finished | Jul 30 08:45:12 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-3bc158f4-1296-4e76-9cf4-46d325cd61ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399636964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays .399636964 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.3865933974 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 7366545428 ps |
| CPU time | 296.74 seconds |
| Started | Jul 30 08:45:14 PM PDT 24 |
| Finished | Jul 30 08:50:11 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-f6f5fbd4-a547-4a9f-b61d-f5e19bcb15b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865933974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.3865933974 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.3330623347 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 9147798017 ps |
| CPU time | 397.94 seconds |
| Started | Jul 30 08:45:13 PM PDT 24 |
| Finished | Jul 30 08:51:51 PM PDT 24 |
| Peak memory | 576136 kb |
| Host | smart-0227316b-5133-40c4-9ac1-562a4c4e34f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330623347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.3330623347 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.2138236383 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 6828985065 ps |
| CPU time | 429.86 seconds |
| Started | Jul 30 08:45:15 PM PDT 24 |
| Finished | Jul 30 08:52:24 PM PDT 24 |
| Peak memory | 576868 kb |
| Host | smart-ddb58a8e-cd1f-4dd6-b805-1bbb063f5068 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138236383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.2138236383 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.1982265976 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 118274630 ps |
| CPU time | 41.41 seconds |
| Started | Jul 30 08:45:13 PM PDT 24 |
| Finished | Jul 30 08:45:55 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-b814e80d-6e99-4a79-aa1c-f1895d3e88d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982265976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.1982265976 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.1360154889 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 522896850 ps |
| CPU time | 24.58 seconds |
| Started | Jul 30 08:45:13 PM PDT 24 |
| Finished | Jul 30 08:45:37 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-b5d016ea-c905-4a2d-8476-69b0291b97f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360154889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.1360154889 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.4214110544 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 129022936229 ps |
| CPU time | 2279.94 seconds |
| Started | Jul 30 08:45:17 PM PDT 24 |
| Finished | Jul 30 09:23:18 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-f1a6c7fe-82fb-4432-a17f-18a695b24c47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214110544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.4214110544 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.1098099914 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 248298512 ps |
| CPU time | 29.39 seconds |
| Started | Jul 30 08:45:27 PM PDT 24 |
| Finished | Jul 30 08:45:56 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-b3955ded-15b4-436f-9195-3133a7d7242c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098099914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.1098099914 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.1981849251 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 1146730712 ps |
| CPU time | 37.11 seconds |
| Started | Jul 30 08:45:20 PM PDT 24 |
| Finished | Jul 30 08:45:57 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-d15f7212-d4b4-4176-835e-f03fa9d8f73c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981849251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.1981849251 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.3299109504 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 510506057 ps |
| CPU time | 48.04 seconds |
| Started | Jul 30 08:45:18 PM PDT 24 |
| Finished | Jul 30 08:46:06 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-a06267de-2f75-4389-b39f-64983372d857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299109504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.3299109504 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.3016910742 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 66080791776 ps |
| CPU time | 657.24 seconds |
| Started | Jul 30 08:45:19 PM PDT 24 |
| Finished | Jul 30 08:56:16 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-13b69d13-0c65-42d5-946e-ee96cf1da2d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016910742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.3016910742 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.3132114552 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 7711713994 ps |
| CPU time | 129.8 seconds |
| Started | Jul 30 08:45:19 PM PDT 24 |
| Finished | Jul 30 08:47:29 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-c3c6c4da-c8a5-44cf-9f5f-9234352d0722 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132114552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.3132114552 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.1617789161 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 214633323 ps |
| CPU time | 22.02 seconds |
| Started | Jul 30 08:45:17 PM PDT 24 |
| Finished | Jul 30 08:45:40 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-078e8c34-f3fe-4137-9e76-25a013c2e599 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617789161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.1617789161 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.2220220448 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 2678448402 ps |
| CPU time | 80.58 seconds |
| Started | Jul 30 08:45:20 PM PDT 24 |
| Finished | Jul 30 08:46:41 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-730549b0-a60f-4d61-8d2d-9e13c60aef48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220220448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.2220220448 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.304906222 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 239451609 ps |
| CPU time | 9.15 seconds |
| Started | Jul 30 08:45:13 PM PDT 24 |
| Finished | Jul 30 08:45:22 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-783b9dd3-acb2-44e8-9fab-912de3a417d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304906222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.304906222 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.3508780055 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 10564455240 ps |
| CPU time | 107.92 seconds |
| Started | Jul 30 08:45:13 PM PDT 24 |
| Finished | Jul 30 08:47:01 PM PDT 24 |
| Peak memory | 573908 kb |
| Host | smart-eb8448c9-968d-484e-bf70-88c1552b14ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508780055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.3508780055 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1841581 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 5705278427 ps |
| CPU time | 101.35 seconds |
| Started | Jul 30 08:45:17 PM PDT 24 |
| Finished | Jul 30 08:46:58 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-56883b15-c9ec-49f8-84c7-4855f29ec2eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.1841581 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.232447552 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 38695440 ps |
| CPU time | 6.13 seconds |
| Started | Jul 30 08:45:14 PM PDT 24 |
| Finished | Jul 30 08:45:20 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-36460d5d-e5cd-4c05-94ed-67e669e3b65d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232447552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delays .232447552 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.325315879 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 8803119841 ps |
| CPU time | 347.45 seconds |
| Started | Jul 30 08:45:31 PM PDT 24 |
| Finished | Jul 30 08:51:19 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-8666dcab-8e34-4bd3-8429-dc45049ec712 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325315879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.325315879 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.294379169 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 369283888 ps |
| CPU time | 206.26 seconds |
| Started | Jul 30 08:45:27 PM PDT 24 |
| Finished | Jul 30 08:48:53 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-d1483f48-7262-4b31-be24-0c3e41efe017 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294379169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_ with_rand_reset.294379169 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.3647675821 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 187335682 ps |
| CPU time | 58.08 seconds |
| Started | Jul 30 08:45:24 PM PDT 24 |
| Finished | Jul 30 08:46:22 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-90929282-c902-44c2-8548-3b8dd35caa50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647675821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.3647675821 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.2206368194 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 186368926 ps |
| CPU time | 23.99 seconds |
| Started | Jul 30 08:45:20 PM PDT 24 |
| Finished | Jul 30 08:45:44 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-aa622278-647c-4945-86bd-e13114550f03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206368194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.2206368194 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.162419581 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 1546201817 ps |
| CPU time | 66.46 seconds |
| Started | Jul 30 08:45:37 PM PDT 24 |
| Finished | Jul 30 08:46:43 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-b9bf3e29-0e93-4057-bd42-419e017146cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162419581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device. 162419581 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2173201401 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 50489398848 ps |
| CPU time | 892.84 seconds |
| Started | Jul 30 08:45:32 PM PDT 24 |
| Finished | Jul 30 09:00:25 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-58c74c7a-f952-411d-8047-2db05e6deffd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173201401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.2173201401 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.4022708446 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 328988069 ps |
| CPU time | 33.2 seconds |
| Started | Jul 30 08:45:32 PM PDT 24 |
| Finished | Jul 30 08:46:05 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-d3030e58-e950-443d-bdc4-b1fac538777d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022708446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.4022708446 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.50306555 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 378498814 ps |
| CPU time | 15.92 seconds |
| Started | Jul 30 08:45:33 PM PDT 24 |
| Finished | Jul 30 08:45:49 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-0cbdb598-69d5-45d3-91a8-d5254e490b7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50306555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.50306555 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.3319643926 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 2651053608 ps |
| CPU time | 115.1 seconds |
| Started | Jul 30 08:45:32 PM PDT 24 |
| Finished | Jul 30 08:47:27 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-f0283d89-bbc8-4d64-94c3-03aa94ee2b43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319643926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.3319643926 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.1366935401 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 99848725804 ps |
| CPU time | 1074.37 seconds |
| Started | Jul 30 08:45:30 PM PDT 24 |
| Finished | Jul 30 09:03:25 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-54f7bb49-9558-4fe2-9b7a-07f06ca8612f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366935401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.1366935401 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.1263183185 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 42203057601 ps |
| CPU time | 725.19 seconds |
| Started | Jul 30 08:45:34 PM PDT 24 |
| Finished | Jul 30 08:57:39 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-c7360d6a-9027-490d-87a2-937a04f57485 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263183185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.1263183185 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.1020269123 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 382979938 ps |
| CPU time | 34.53 seconds |
| Started | Jul 30 08:45:26 PM PDT 24 |
| Finished | Jul 30 08:46:01 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-eb504dce-6263-4ab2-8f22-2840d5a3e8c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020269123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.1020269123 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.1213388334 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 428814588 ps |
| CPU time | 35.83 seconds |
| Started | Jul 30 08:45:31 PM PDT 24 |
| Finished | Jul 30 08:46:07 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-eb49f251-7496-412d-a296-2015836fd622 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213388334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.1213388334 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.3078980288 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 47620347 ps |
| CPU time | 7.11 seconds |
| Started | Jul 30 08:45:31 PM PDT 24 |
| Finished | Jul 30 08:45:38 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-230ad9b1-7efd-4fdb-8c23-0cab2b239478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078980288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.3078980288 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.1607505252 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 6369169028 ps |
| CPU time | 69.49 seconds |
| Started | Jul 30 08:45:27 PM PDT 24 |
| Finished | Jul 30 08:46:36 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-56b5b26d-5c3f-4534-ac7b-34123e3f3b24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607505252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.1607505252 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.3365930840 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 6486801703 ps |
| CPU time | 110.01 seconds |
| Started | Jul 30 08:45:28 PM PDT 24 |
| Finished | Jul 30 08:47:18 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-fa13d9bf-0b4b-4010-9c12-df70bda3bd38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365930840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.3365930840 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.2488145591 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 56583087 ps |
| CPU time | 7.11 seconds |
| Started | Jul 30 08:45:24 PM PDT 24 |
| Finished | Jul 30 08:45:31 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-ccf3efcf-c4a4-4968-8608-f314c545f17c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488145591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.2488145591 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.1550722032 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 12745049491 ps |
| CPU time | 471.63 seconds |
| Started | Jul 30 08:45:32 PM PDT 24 |
| Finished | Jul 30 08:53:23 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-e97f5149-8eb4-4dff-8bdf-e4133242b2e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550722032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.1550722032 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.365425108 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 9315621758 ps |
| CPU time | 320.41 seconds |
| Started | Jul 30 08:45:33 PM PDT 24 |
| Finished | Jul 30 08:50:54 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-9e265ea2-2dea-4032-bbde-51ba009b982d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365425108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.365425108 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.218377401 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 2448420343 ps |
| CPU time | 394.26 seconds |
| Started | Jul 30 08:45:32 PM PDT 24 |
| Finished | Jul 30 08:52:06 PM PDT 24 |
| Peak memory | 576848 kb |
| Host | smart-c22f05bc-f092-4800-8639-5d553e878e3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218377401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_ with_rand_reset.218377401 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.3751682334 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 250737507 ps |
| CPU time | 92.54 seconds |
| Started | Jul 30 08:45:37 PM PDT 24 |
| Finished | Jul 30 08:47:10 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-bbee75b7-f209-465d-ac16-7d083e472103 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751682334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.3751682334 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.3137806140 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 228510533 ps |
| CPU time | 26.12 seconds |
| Started | Jul 30 08:45:31 PM PDT 24 |
| Finished | Jul 30 08:45:58 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-bc9bda8b-3ffd-40b4-8bb9-97959d06de4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137806140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.3137806140 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.4039642609 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 195037887 ps |
| CPU time | 23.25 seconds |
| Started | Jul 30 08:45:46 PM PDT 24 |
| Finished | Jul 30 08:46:09 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-a77e2b5f-4f69-41e2-90e4-a0618e45bc6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039642609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .4039642609 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.3148241240 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 25759183661 ps |
| CPU time | 442.54 seconds |
| Started | Jul 30 08:45:44 PM PDT 24 |
| Finished | Jul 30 08:53:07 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-2d45253b-534f-4977-be97-a23eaed7c560 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148241240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.3148241240 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3178085785 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 265287881 ps |
| CPU time | 28.47 seconds |
| Started | Jul 30 08:45:46 PM PDT 24 |
| Finished | Jul 30 08:46:15 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-265855d0-6600-4acb-9626-ae85f040e656 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178085785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.3178085785 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.295480127 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 594427483 ps |
| CPU time | 48.62 seconds |
| Started | Jul 30 08:45:44 PM PDT 24 |
| Finished | Jul 30 08:46:33 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-26219a8c-1dcf-4a6c-ab63-34f9afaabd16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295480127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.295480127 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.4063897208 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 1588003619 ps |
| CPU time | 58.98 seconds |
| Started | Jul 30 08:45:41 PM PDT 24 |
| Finished | Jul 30 08:46:40 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-c4548def-9a72-4bdf-9037-6176b41b0cd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063897208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.4063897208 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.1069206119 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 106773866242 ps |
| CPU time | 1137.05 seconds |
| Started | Jul 30 08:45:42 PM PDT 24 |
| Finished | Jul 30 09:04:40 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-6ef7901d-b74c-4249-be65-40a8ea888888 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069206119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.1069206119 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.2755064118 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 57546776542 ps |
| CPU time | 947.28 seconds |
| Started | Jul 30 08:45:44 PM PDT 24 |
| Finished | Jul 30 09:01:32 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-dbdeb606-fdc6-473d-80f5-0ef1deda82b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755064118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.2755064118 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.2017411171 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 416015073 ps |
| CPU time | 34.62 seconds |
| Started | Jul 30 08:45:40 PM PDT 24 |
| Finished | Jul 30 08:46:15 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-ebf8e26d-49d5-47a1-b4c7-a8e127872fef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017411171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.2017411171 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.3736159520 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 184764921 ps |
| CPU time | 8.82 seconds |
| Started | Jul 30 08:45:44 PM PDT 24 |
| Finished | Jul 30 08:45:53 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-fcc44239-55f2-477b-8515-cf40bb2b63c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736159520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.3736159520 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.2549348119 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 49694094 ps |
| CPU time | 6.34 seconds |
| Started | Jul 30 08:45:34 PM PDT 24 |
| Finished | Jul 30 08:45:40 PM PDT 24 |
| Peak memory | 573740 kb |
| Host | smart-ce692717-fe48-46e0-b783-89a52745091d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549348119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.2549348119 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.1962094647 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 7575163743 ps |
| CPU time | 83.97 seconds |
| Started | Jul 30 08:45:41 PM PDT 24 |
| Finished | Jul 30 08:47:05 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-12f7c4a7-b44d-459b-8dac-0d95f6392aba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962094647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.1962094647 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.1503454478 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 5254744857 ps |
| CPU time | 89.8 seconds |
| Started | Jul 30 08:45:41 PM PDT 24 |
| Finished | Jul 30 08:47:11 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-938398df-6278-4b8d-a5c9-931b7cbed4c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503454478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.1503454478 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.3802230500 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 57463427 ps |
| CPU time | 6.92 seconds |
| Started | Jul 30 08:45:39 PM PDT 24 |
| Finished | Jul 30 08:45:47 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-98881fc7-3b98-465b-978c-191d6ce49107 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802230500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.3802230500 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.2245425039 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 1468964573 ps |
| CPU time | 56.04 seconds |
| Started | Jul 30 08:45:48 PM PDT 24 |
| Finished | Jul 30 08:46:44 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-bc4a9d51-6f3e-40a0-89a5-94c3f37a25a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245425039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.2245425039 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.281408702 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 991500494 ps |
| CPU time | 93.83 seconds |
| Started | Jul 30 08:45:46 PM PDT 24 |
| Finished | Jul 30 08:47:20 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-1cb491eb-8589-4201-aafd-33576d532ee8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281408702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.281408702 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.574052463 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 1691551854 ps |
| CPU time | 136.55 seconds |
| Started | Jul 30 08:45:50 PM PDT 24 |
| Finished | Jul 30 08:48:07 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-6b6840a8-adc2-4d3b-baa0-c4b40305d1f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574052463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_ with_rand_reset.574052463 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.2168812008 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 19834680774 ps |
| CPU time | 915.12 seconds |
| Started | Jul 30 08:45:46 PM PDT 24 |
| Finished | Jul 30 09:01:02 PM PDT 24 |
| Peak memory | 581908 kb |
| Host | smart-a09e85f1-8c59-45d8-9ac4-b4605d5424df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168812008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.2168812008 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.90977871 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 377489793 ps |
| CPU time | 19.38 seconds |
| Started | Jul 30 08:45:44 PM PDT 24 |
| Finished | Jul 30 08:46:03 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-caef73e8-5499-4910-8bb6-763f7a1fd0f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90977871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.90977871 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.2308618095 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 13445456425 ps |
| CPU time | 1008.03 seconds |
| Started | Jul 30 08:30:28 PM PDT 24 |
| Finished | Jul 30 08:47:17 PM PDT 24 |
| Peak memory | 641752 kb |
| Host | smart-67be7d7d-5f12-41a9-8c74-af5dfca3d343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308618095 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.2308618095 |
| Directory | /workspace/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.2397644558 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 5057301880 ps |
| CPU time | 588.05 seconds |
| Started | Jul 30 08:30:32 PM PDT 24 |
| Finished | Jul 30 08:40:20 PM PDT 24 |
| Peak memory | 598948 kb |
| Host | smart-b359f82b-8115-4859-a43f-ec2432506683 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397644558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.2397644558 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.1776549274 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 29521844325 ps |
| CPU time | 3411.29 seconds |
| Started | Jul 30 08:30:07 PM PDT 24 |
| Finished | Jul 30 09:26:59 PM PDT 24 |
| Peak memory | 593348 kb |
| Host | smart-c443fc38-802f-45d7-99d9-83c436046732 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776549274 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.1776549274 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.1968600414 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 3461239568 ps |
| CPU time | 240.73 seconds |
| Started | Jul 30 08:30:05 PM PDT 24 |
| Finished | Jul 30 08:34:06 PM PDT 24 |
| Peak memory | 603828 kb |
| Host | smart-8ed53326-6af8-47b8-8804-117f482411f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968600414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.1968600414 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.2003174374 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 113815474 ps |
| CPU time | 15.31 seconds |
| Started | Jul 30 08:30:19 PM PDT 24 |
| Finished | Jul 30 08:30:35 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-ce6521a8-89cd-447a-9edf-2eea28b1371c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003174374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 2003174374 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.1714742808 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 50350179278 ps |
| CPU time | 935.73 seconds |
| Started | Jul 30 08:30:20 PM PDT 24 |
| Finished | Jul 30 08:45:56 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-86c6baa9-5670-456e-8c93-a00f4e358460 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714742808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d evice_slow_rsp.1714742808 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.2421697918 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 547291160 ps |
| CPU time | 25.43 seconds |
| Started | Jul 30 08:30:23 PM PDT 24 |
| Finished | Jul 30 08:30:49 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-1afe6ac5-89fb-4b50-befc-a03807115c26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421697918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .2421697918 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.2234246077 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 883338373 ps |
| CPU time | 36.15 seconds |
| Started | Jul 30 08:30:24 PM PDT 24 |
| Finished | Jul 30 08:31:00 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-119a7b24-d3ff-40e6-a97f-a8d2e5e59541 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234246077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2234246077 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.1263914255 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 1729183626 ps |
| CPU time | 68.17 seconds |
| Started | Jul 30 08:30:11 PM PDT 24 |
| Finished | Jul 30 08:31:19 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-b16f42ec-15ec-4136-a9eb-71fde53d98d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263914255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.1263914255 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.587959310 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 87512260312 ps |
| CPU time | 882.51 seconds |
| Started | Jul 30 08:30:15 PM PDT 24 |
| Finished | Jul 30 08:44:58 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-fd22a60a-2e5c-428f-becf-120342e7bbe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587959310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.587959310 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.1273264127 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 3633441701 ps |
| CPU time | 65 seconds |
| Started | Jul 30 08:30:24 PM PDT 24 |
| Finished | Jul 30 08:31:29 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-fcade5f8-a99e-4604-af5e-c4b9f6c4ddc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273264127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1273264127 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.1314133077 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 459220818 ps |
| CPU time | 41.55 seconds |
| Started | Jul 30 08:30:15 PM PDT 24 |
| Finished | Jul 30 08:30:57 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-35748eda-fbdf-4a3b-9030-3bf2bf49e036 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314133077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.1314133077 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.32418499 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 404777354 ps |
| CPU time | 33.49 seconds |
| Started | Jul 30 08:30:25 PM PDT 24 |
| Finished | Jul 30 08:30:59 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-7a6345f7-0f80-4e8b-8c5e-a5f8385e5605 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32418499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.32418499 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.1120212243 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 173171888 ps |
| CPU time | 9.01 seconds |
| Started | Jul 30 08:30:05 PM PDT 24 |
| Finished | Jul 30 08:30:14 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-45e6b658-83cb-4bb9-9ca8-7e1bd4dcbf07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120212243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1120212243 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.3314857324 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 7456536922 ps |
| CPU time | 75.19 seconds |
| Started | Jul 30 08:30:14 PM PDT 24 |
| Finished | Jul 30 08:31:29 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-51428094-7f4f-4afd-84d3-fa3f1db27fd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314857324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3314857324 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3862962804 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 6236482470 ps |
| CPU time | 109.91 seconds |
| Started | Jul 30 08:30:11 PM PDT 24 |
| Finished | Jul 30 08:32:01 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-4953bd17-be69-45ff-bf26-af8df8725a4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862962804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3862962804 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3771424963 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 47244566 ps |
| CPU time | 6.64 seconds |
| Started | Jul 30 08:30:12 PM PDT 24 |
| Finished | Jul 30 08:30:19 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-1830a3fb-de46-4d0c-ab4c-b7c015ac4f14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771424963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .3771424963 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.2761713227 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 2523051743 ps |
| CPU time | 105.72 seconds |
| Started | Jul 30 08:30:25 PM PDT 24 |
| Finished | Jul 30 08:32:11 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-9af402c7-ee69-4ed0-8801-4952a5defb25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761713227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2761713227 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.2536073054 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 896473084 ps |
| CPU time | 67.95 seconds |
| Started | Jul 30 08:30:33 PM PDT 24 |
| Finished | Jul 30 08:31:41 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-1db7ec9f-25e9-4ea9-93b8-37391da41cb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536073054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2536073054 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.414566390 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 624476604 ps |
| CPU time | 246.29 seconds |
| Started | Jul 30 08:30:28 PM PDT 24 |
| Finished | Jul 30 08:34:34 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-f2f88c45-894d-44f4-a6f7-d9772dea0f69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414566390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_w ith_rand_reset.414566390 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.1391993486 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 621372907 ps |
| CPU time | 208.05 seconds |
| Started | Jul 30 08:30:31 PM PDT 24 |
| Finished | Jul 30 08:33:59 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-bf8e47aa-4ee0-4508-bd88-e459ed23d94c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391993486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.1391993486 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.776062279 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 68935238 ps |
| CPU time | 11.15 seconds |
| Started | Jul 30 08:30:22 PM PDT 24 |
| Finished | Jul 30 08:30:34 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-2d5f0e59-6092-4e44-a5fd-d69d63842384 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776062279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.776062279 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.717423266 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 1373046494 ps |
| CPU time | 48.96 seconds |
| Started | Jul 30 08:45:49 PM PDT 24 |
| Finished | Jul 30 08:46:38 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-65f3ebe0-fb7c-4e5c-ac7c-cdc45c6630ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717423266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device. 717423266 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.1614602821 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 60898351534 ps |
| CPU time | 1026.67 seconds |
| Started | Jul 30 08:45:49 PM PDT 24 |
| Finished | Jul 30 09:02:56 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-54e218a1-8b5e-4397-980a-47b64c24631e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614602821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.1614602821 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.3340850524 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 153299433 ps |
| CPU time | 10.59 seconds |
| Started | Jul 30 08:45:52 PM PDT 24 |
| Finished | Jul 30 08:46:03 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-803769f5-8a2b-485b-96f1-71dc9e407bf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340850524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add r.3340850524 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.2570582789 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 1492677674 ps |
| CPU time | 52.69 seconds |
| Started | Jul 30 08:45:51 PM PDT 24 |
| Finished | Jul 30 08:46:43 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-60b5184e-ddf7-4e0f-82b3-2d5644f21fcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570582789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.2570582789 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.988669784 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 474437616 ps |
| CPU time | 45.78 seconds |
| Started | Jul 30 08:45:48 PM PDT 24 |
| Finished | Jul 30 08:46:34 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-a957d13b-382d-47c3-a94a-ccdaa2fe4887 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988669784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.988669784 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.3782898243 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 13966523080 ps |
| CPU time | 152.75 seconds |
| Started | Jul 30 08:45:56 PM PDT 24 |
| Finished | Jul 30 08:48:28 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-f839edf3-9ccd-40ca-aa99-b6c9ceb4e1e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782898243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.3782898243 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.3207707298 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 33758398903 ps |
| CPU time | 599.11 seconds |
| Started | Jul 30 08:45:48 PM PDT 24 |
| Finished | Jul 30 08:55:48 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-5cfca392-eae5-4024-a122-d44fec624bcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207707298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.3207707298 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.2108948487 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 419275424 ps |
| CPU time | 35.18 seconds |
| Started | Jul 30 08:45:50 PM PDT 24 |
| Finished | Jul 30 08:46:25 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-ef23fc9d-6178-41c5-95f6-ce31f47646e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108948487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.2108948487 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.3322318256 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 2636418681 ps |
| CPU time | 86.09 seconds |
| Started | Jul 30 08:45:50 PM PDT 24 |
| Finished | Jul 30 08:47:17 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-ebf55f02-6b46-420f-8658-8e27047731b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322318256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.3322318256 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.3435778254 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 159432792 ps |
| CPU time | 8.12 seconds |
| Started | Jul 30 08:45:44 PM PDT 24 |
| Finished | Jul 30 08:45:52 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-33f8e104-35f6-480a-a817-cca71e924291 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435778254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.3435778254 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.1375977755 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 7932467627 ps |
| CPU time | 83.13 seconds |
| Started | Jul 30 08:45:50 PM PDT 24 |
| Finished | Jul 30 08:47:13 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-2f8614d4-5c38-4a03-bbd3-2e7933689809 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375977755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.1375977755 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.2896463656 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 5754682393 ps |
| CPU time | 102.07 seconds |
| Started | Jul 30 08:45:46 PM PDT 24 |
| Finished | Jul 30 08:47:28 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-e187aa55-4772-4d69-8d01-d605237bfce5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896463656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.2896463656 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2714636744 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 49270083 ps |
| CPU time | 6.92 seconds |
| Started | Jul 30 08:45:47 PM PDT 24 |
| Finished | Jul 30 08:45:54 PM PDT 24 |
| Peak memory | 573848 kb |
| Host | smart-dac16fed-ce74-4e51-9957-d2f2e11dff18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714636744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.2714636744 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.3586133181 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 11981503196 ps |
| CPU time | 500.74 seconds |
| Started | Jul 30 08:45:55 PM PDT 24 |
| Finished | Jul 30 08:54:15 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-26fc31f3-12d5-41c0-bcbe-3047b673b630 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586133181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.3586133181 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.1345779133 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 4205216782 ps |
| CPU time | 345.63 seconds |
| Started | Jul 30 08:45:58 PM PDT 24 |
| Finished | Jul 30 08:51:44 PM PDT 24 |
| Peak memory | 576832 kb |
| Host | smart-382f27a1-2a2d-453a-884f-b2e1afbad99e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345779133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.1345779133 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.1455332023 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 3265523995 ps |
| CPU time | 528.43 seconds |
| Started | Jul 30 08:45:55 PM PDT 24 |
| Finished | Jul 30 08:54:44 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-f8911a2e-4fe5-4de4-8f45-b87d0e9cccf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455332023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.1455332023 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.3086803021 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 535785976 ps |
| CPU time | 26.33 seconds |
| Started | Jul 30 08:45:56 PM PDT 24 |
| Finished | Jul 30 08:46:23 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-c81bb714-44d2-4e0e-81c6-498c955cf180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086803021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.3086803021 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.1236423009 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 2185620120 ps |
| CPU time | 87.99 seconds |
| Started | Jul 30 08:46:26 PM PDT 24 |
| Finished | Jul 30 08:47:54 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-ac160fd4-073b-46f9-9cf6-a35801783dfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236423009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .1236423009 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.3046051945 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 83002474773 ps |
| CPU time | 1436.26 seconds |
| Started | Jul 30 08:46:03 PM PDT 24 |
| Finished | Jul 30 09:10:00 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-df1fb73a-6670-4294-b6fe-719a100455e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046051945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.3046051945 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.1638264941 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 176132195 ps |
| CPU time | 11.03 seconds |
| Started | Jul 30 08:46:06 PM PDT 24 |
| Finished | Jul 30 08:46:17 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-48578b56-5a55-4b34-a25e-f9f09eb9d70d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638264941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.1638264941 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.679852439 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 28992075 ps |
| CPU time | 5.52 seconds |
| Started | Jul 30 08:46:06 PM PDT 24 |
| Finished | Jul 30 08:46:11 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-6fa77cdb-b5cc-4c1b-a5e0-cb06215d4f79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679852439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.679852439 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.684345337 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 628645246 ps |
| CPU time | 25.91 seconds |
| Started | Jul 30 08:46:01 PM PDT 24 |
| Finished | Jul 30 08:46:27 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-2912a3c7-0d3f-4054-b0b3-75c293083e4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684345337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.684345337 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.1271527141 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 68367997086 ps |
| CPU time | 677.82 seconds |
| Started | Jul 30 08:46:00 PM PDT 24 |
| Finished | Jul 30 08:57:18 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-d9c818bb-c505-4343-805d-4a7fb80c50a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271527141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.1271527141 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.3206609493 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 46335312216 ps |
| CPU time | 784.71 seconds |
| Started | Jul 30 08:46:01 PM PDT 24 |
| Finished | Jul 30 08:59:05 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-f4f9134a-ed93-406d-8bbc-08723afecd50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206609493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.3206609493 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.1236949138 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 284171865 ps |
| CPU time | 26.38 seconds |
| Started | Jul 30 08:46:00 PM PDT 24 |
| Finished | Jul 30 08:46:26 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-66f27299-2573-42f9-a7f7-b719756fa4fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236949138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.1236949138 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.2749622523 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 2285631913 ps |
| CPU time | 62.69 seconds |
| Started | Jul 30 08:46:01 PM PDT 24 |
| Finished | Jul 30 08:47:04 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-77268fb6-c64f-4206-ac73-80713004e0b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749622523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.2749622523 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.3029048071 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 209469375 ps |
| CPU time | 9.22 seconds |
| Started | Jul 30 08:45:57 PM PDT 24 |
| Finished | Jul 30 08:46:07 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-a75d9d46-a132-4ed5-a0ea-3acd069eb2ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029048071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.3029048071 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.100162732 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 8107570138 ps |
| CPU time | 84.32 seconds |
| Started | Jul 30 08:45:58 PM PDT 24 |
| Finished | Jul 30 08:47:22 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-ab71a5c0-ba5e-408c-87e5-02ae2ec2262b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100162732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.100162732 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.2850166862 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 5343618808 ps |
| CPU time | 93.32 seconds |
| Started | Jul 30 08:45:57 PM PDT 24 |
| Finished | Jul 30 08:47:30 PM PDT 24 |
| Peak memory | 573908 kb |
| Host | smart-d37f4b01-da92-4b2e-9280-1fdd2ed50906 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850166862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.2850166862 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.2942420634 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 57461381 ps |
| CPU time | 7.28 seconds |
| Started | Jul 30 08:45:56 PM PDT 24 |
| Finished | Jul 30 08:46:03 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-b80ae104-ce2e-4092-8276-29036ace647e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942420634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.2942420634 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.1289661455 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 18177315363 ps |
| CPU time | 632.49 seconds |
| Started | Jul 30 08:46:05 PM PDT 24 |
| Finished | Jul 30 08:56:38 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-6b89952c-e2ff-4ab5-a64c-c5666b4e2abf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289661455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.1289661455 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.2960394623 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 2205967906 ps |
| CPU time | 159.57 seconds |
| Started | Jul 30 08:46:07 PM PDT 24 |
| Finished | Jul 30 08:48:46 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-19731c14-25f4-4183-9df6-8290f7390d36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960394623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.2960394623 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.2533224007 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 636115782 ps |
| CPU time | 204.67 seconds |
| Started | Jul 30 08:46:03 PM PDT 24 |
| Finished | Jul 30 08:49:27 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-44a7e7c0-7b75-4c6f-841c-cf1409bdd89b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533224007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.2533224007 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.759570355 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 8328319822 ps |
| CPU time | 748.8 seconds |
| Started | Jul 30 08:46:09 PM PDT 24 |
| Finished | Jul 30 08:58:38 PM PDT 24 |
| Peak memory | 582936 kb |
| Host | smart-4b5b368c-01bd-45ca-aace-36c162ce9364 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759570355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_reset_error.759570355 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.1383312220 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 114420893 ps |
| CPU time | 14.62 seconds |
| Started | Jul 30 08:46:02 PM PDT 24 |
| Finished | Jul 30 08:46:17 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-a51f768d-7150-4a12-952c-61b6528328b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383312220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.1383312220 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.807922404 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 1761301810 ps |
| CPU time | 70.72 seconds |
| Started | Jul 30 08:46:13 PM PDT 24 |
| Finished | Jul 30 08:47:23 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-17be625b-61ee-4abf-ad9c-8e2efb04e03f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807922404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device. 807922404 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.299277515 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 51259316572 ps |
| CPU time | 944.2 seconds |
| Started | Jul 30 08:46:16 PM PDT 24 |
| Finished | Jul 30 09:02:01 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-f6c65a2e-097f-4df3-889e-6716851020e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299277515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_d evice_slow_rsp.299277515 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.1788818244 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 998331862 ps |
| CPU time | 42.19 seconds |
| Started | Jul 30 08:46:23 PM PDT 24 |
| Finished | Jul 30 08:47:05 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-6787a5f4-52d4-4f69-a971-e5b69185363c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788818244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.1788818244 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.3944090328 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 250425291 ps |
| CPU time | 22.19 seconds |
| Started | Jul 30 08:46:22 PM PDT 24 |
| Finished | Jul 30 08:46:44 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-7f55bfee-3310-4571-9391-1b3111a757ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944090328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.3944090328 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.3900664674 |
| Short name | T2934 |
| Test name | |
| Test status | |
| Simulation time | 125326288 ps |
| CPU time | 8.5 seconds |
| Started | Jul 30 08:46:11 PM PDT 24 |
| Finished | Jul 30 08:46:19 PM PDT 24 |
| Peak memory | 573832 kb |
| Host | smart-d34925b6-3d43-4261-b247-9e5e06b53cb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900664674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.3900664674 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.2973819447 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 47291302672 ps |
| CPU time | 500.97 seconds |
| Started | Jul 30 08:46:11 PM PDT 24 |
| Finished | Jul 30 08:54:32 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-302b8731-858c-4c83-87ae-74c148af8cb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973819447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.2973819447 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.1657676141 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 4271177026 ps |
| CPU time | 73.94 seconds |
| Started | Jul 30 08:46:11 PM PDT 24 |
| Finished | Jul 30 08:47:25 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-37a61a2e-a844-4587-9f0c-d49c85159596 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657676141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.1657676141 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.1865241431 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 149504751 ps |
| CPU time | 15.98 seconds |
| Started | Jul 30 08:46:12 PM PDT 24 |
| Finished | Jul 30 08:46:28 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-cf5f35cb-6a9b-489b-83ef-398b5f44bf35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865241431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del ays.1865241431 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.1579100660 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 332192964 ps |
| CPU time | 27.1 seconds |
| Started | Jul 30 08:46:15 PM PDT 24 |
| Finished | Jul 30 08:46:42 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-6f39d326-642a-41b0-a6d5-299d7cbb53dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579100660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.1579100660 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.1149291191 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 223251737 ps |
| CPU time | 9.55 seconds |
| Started | Jul 30 08:46:09 PM PDT 24 |
| Finished | Jul 30 08:46:19 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-601fb8ae-4e6c-4952-92db-b30b6a4e2c6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149291191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.1149291191 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.1670214881 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 9551539890 ps |
| CPU time | 106.57 seconds |
| Started | Jul 30 08:46:09 PM PDT 24 |
| Finished | Jul 30 08:47:56 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-7cae243c-db79-4baf-8a9d-240efaf82726 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670214881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.1670214881 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.1361718714 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 4350687013 ps |
| CPU time | 77.29 seconds |
| Started | Jul 30 08:46:14 PM PDT 24 |
| Finished | Jul 30 08:47:31 PM PDT 24 |
| Peak memory | 573960 kb |
| Host | smart-245d5cc2-3526-4476-a619-3d9996d567f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361718714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.1361718714 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.38229550 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 43088352 ps |
| CPU time | 6.87 seconds |
| Started | Jul 30 08:46:07 PM PDT 24 |
| Finished | Jul 30 08:46:14 PM PDT 24 |
| Peak memory | 573896 kb |
| Host | smart-b1b31717-06d4-462e-927e-742d632643be |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38229550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delays.38229550 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.759440168 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 14760565808 ps |
| CPU time | 621.28 seconds |
| Started | Jul 30 08:46:16 PM PDT 24 |
| Finished | Jul 30 08:56:37 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-cc99cd9d-05b3-43a8-93ba-f5555fcad17b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759440168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.759440168 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.2180595084 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 6568271997 ps |
| CPU time | 238.64 seconds |
| Started | Jul 30 08:46:14 PM PDT 24 |
| Finished | Jul 30 08:50:12 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-e77c1626-fbd3-40c5-bd7e-b2bae0f9dee6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180595084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.2180595084 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.4140737263 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 914485907 ps |
| CPU time | 374.54 seconds |
| Started | Jul 30 08:46:14 PM PDT 24 |
| Finished | Jul 30 08:52:29 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-a1419953-588c-4819-91d3-817804b0ce73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140737263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.4140737263 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3546339819 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 6240245733 ps |
| CPU time | 679.16 seconds |
| Started | Jul 30 08:46:14 PM PDT 24 |
| Finished | Jul 30 08:57:33 PM PDT 24 |
| Peak memory | 576856 kb |
| Host | smart-4b4ced7a-eb0a-4073-af36-51c19de8cc52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546339819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.3546339819 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.2941111074 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 256329358 ps |
| CPU time | 30.47 seconds |
| Started | Jul 30 08:46:23 PM PDT 24 |
| Finished | Jul 30 08:46:54 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-5908687b-9846-4c9c-a524-0f4d75dd5248 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941111074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.2941111074 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.825084307 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 1142644919 ps |
| CPU time | 52.19 seconds |
| Started | Jul 30 08:46:24 PM PDT 24 |
| Finished | Jul 30 08:47:17 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-292b81a7-e6f6-4603-99f3-b3179bcd6f41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825084307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device. 825084307 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.4123497883 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 120342762419 ps |
| CPU time | 2149.91 seconds |
| Started | Jul 30 08:46:26 PM PDT 24 |
| Finished | Jul 30 09:22:17 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-1449b1ba-3a07-40ec-9914-530068bb56f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123497883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.4123497883 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.2557002643 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 503976049 ps |
| CPU time | 24.16 seconds |
| Started | Jul 30 08:46:28 PM PDT 24 |
| Finished | Jul 30 08:46:52 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-20ffacee-5aae-46da-a0bd-6ffa118a95c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557002643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.2557002643 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.2793728382 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 2149632911 ps |
| CPU time | 80.65 seconds |
| Started | Jul 30 08:46:23 PM PDT 24 |
| Finished | Jul 30 08:47:44 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-a9784499-d4a8-47f0-baa4-2af809771373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793728382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.2793728382 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.1439853709 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 121348103 ps |
| CPU time | 13.9 seconds |
| Started | Jul 30 08:46:21 PM PDT 24 |
| Finished | Jul 30 08:46:34 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-e398f712-0f51-456f-bfd3-4a2c5b25932b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439853709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.1439853709 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.468265002 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 28100381311 ps |
| CPU time | 291.84 seconds |
| Started | Jul 30 08:46:21 PM PDT 24 |
| Finished | Jul 30 08:51:13 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-5d0054bc-4fc5-48d7-a816-9c3ec1ffcd58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468265002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.468265002 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.861343869 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 23866209847 ps |
| CPU time | 406.73 seconds |
| Started | Jul 30 08:46:25 PM PDT 24 |
| Finished | Jul 30 08:53:11 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-6072c873-cffb-4d11-a4eb-94c5494d5033 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861343869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.861343869 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.4255578753 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 316368461 ps |
| CPU time | 30.91 seconds |
| Started | Jul 30 08:46:23 PM PDT 24 |
| Finished | Jul 30 08:46:54 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-28c29526-8224-4618-b4ca-0612e176a220 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255578753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.4255578753 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.1966905007 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 106540194 ps |
| CPU time | 11.2 seconds |
| Started | Jul 30 08:46:24 PM PDT 24 |
| Finished | Jul 30 08:46:35 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-8d571334-e8c0-421c-851c-b58869ca449c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966905007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.1966905007 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.2353194055 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 147452391 ps |
| CPU time | 8.05 seconds |
| Started | Jul 30 08:46:24 PM PDT 24 |
| Finished | Jul 30 08:46:32 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-023ae026-441c-4fe1-abf9-196161ace4b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353194055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.2353194055 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.1641202978 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 6223030642 ps |
| CPU time | 67.72 seconds |
| Started | Jul 30 08:46:20 PM PDT 24 |
| Finished | Jul 30 08:47:28 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-dbb400d0-a56d-4823-90d9-586b28eeb781 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641202978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.1641202978 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3929012373 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 5797229567 ps |
| CPU time | 94.79 seconds |
| Started | Jul 30 08:46:17 PM PDT 24 |
| Finished | Jul 30 08:47:52 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-8363e093-73f4-4733-bd26-106cfef66277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929012373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.3929012373 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.1329756999 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 52453668 ps |
| CPU time | 6.94 seconds |
| Started | Jul 30 08:46:17 PM PDT 24 |
| Finished | Jul 30 08:46:24 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-e75979ad-8771-466f-a7f5-fa92d6950eec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329756999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.1329756999 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.2331782372 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 1870750735 ps |
| CPU time | 125.96 seconds |
| Started | Jul 30 08:46:27 PM PDT 24 |
| Finished | Jul 30 08:48:33 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-17b5a748-30f6-41a1-ac05-246ad1480894 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331782372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.2331782372 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.2173170217 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 3064574950 ps |
| CPU time | 116.7 seconds |
| Started | Jul 30 08:46:31 PM PDT 24 |
| Finished | Jul 30 08:48:27 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-4f4219cf-a2b1-49a2-96fc-5abe6e996e74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173170217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.2173170217 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3188385815 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 7842143497 ps |
| CPU time | 442.65 seconds |
| Started | Jul 30 08:46:29 PM PDT 24 |
| Finished | Jul 30 08:53:52 PM PDT 24 |
| Peak memory | 576840 kb |
| Host | smart-7ccbd806-9dce-48dd-8b7e-7c69e621e79a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188385815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_rand_reset.3188385815 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3279106771 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 3431987649 ps |
| CPU time | 192.3 seconds |
| Started | Jul 30 08:46:31 PM PDT 24 |
| Finished | Jul 30 08:49:44 PM PDT 24 |
| Peak memory | 576840 kb |
| Host | smart-0b6adbc2-f815-44bb-88bd-00f5654f74ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279106771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.3279106771 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.1461469849 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 267831855 ps |
| CPU time | 12.84 seconds |
| Started | Jul 30 08:46:29 PM PDT 24 |
| Finished | Jul 30 08:46:42 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-d4e574ef-9582-42d8-9803-89bc114394e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461469849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.1461469849 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.2071599311 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 2472730373 ps |
| CPU time | 124.53 seconds |
| Started | Jul 30 08:46:37 PM PDT 24 |
| Finished | Jul 30 08:48:42 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-71662790-792c-42e0-8314-9c135a64c4a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071599311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device .2071599311 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.4009758167 |
| Short name | T2937 |
| Test name | |
| Test status | |
| Simulation time | 81543300463 ps |
| CPU time | 1335.9 seconds |
| Started | Jul 30 08:46:38 PM PDT 24 |
| Finished | Jul 30 09:08:54 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-130b55b8-f9fa-464f-b233-44f6a4149b14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009758167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_ device_slow_rsp.4009758167 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.2674026520 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 50175930 ps |
| CPU time | 8.34 seconds |
| Started | Jul 30 08:46:38 PM PDT 24 |
| Finished | Jul 30 08:46:47 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-cc0b5071-af05-422f-b9fa-d0516f5800ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674026520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.2674026520 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.3252571043 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 816489602 ps |
| CPU time | 29.86 seconds |
| Started | Jul 30 08:46:38 PM PDT 24 |
| Finished | Jul 30 08:47:08 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-09817b1b-74ee-4382-adc7-85148891a03b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252571043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.3252571043 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.2403957446 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 482683752 ps |
| CPU time | 19.93 seconds |
| Started | Jul 30 08:46:37 PM PDT 24 |
| Finished | Jul 30 08:46:57 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-790613e9-bb7f-4774-9f00-479a5e779618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403957446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.2403957446 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.1634708981 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 52389368385 ps |
| CPU time | 580 seconds |
| Started | Jul 30 08:46:33 PM PDT 24 |
| Finished | Jul 30 08:56:13 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-4947c444-8e57-4a39-9320-1aae74b47c73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634708981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.1634708981 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.2460116908 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 31558766259 ps |
| CPU time | 575.17 seconds |
| Started | Jul 30 08:46:37 PM PDT 24 |
| Finished | Jul 30 08:56:12 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-6490ffac-1a3f-4507-8234-8d48e6a32c21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460116908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.2460116908 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.1178866056 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 557058162 ps |
| CPU time | 58.77 seconds |
| Started | Jul 30 08:46:35 PM PDT 24 |
| Finished | Jul 30 08:47:33 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-3fd62813-6bba-4fc6-8900-891246e62a34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178866056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del ays.1178866056 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.3034615024 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 160087375 ps |
| CPU time | 14.63 seconds |
| Started | Jul 30 08:46:37 PM PDT 24 |
| Finished | Jul 30 08:46:51 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-cceb86d2-903f-41c4-b340-dd56644aaf58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034615024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.3034615024 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.2641461461 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 234322748 ps |
| CPU time | 10.51 seconds |
| Started | Jul 30 08:46:33 PM PDT 24 |
| Finished | Jul 30 08:46:43 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-5e687a5b-187c-47b7-9a60-488f3adf09a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641461461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.2641461461 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.3441902337 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 7888723032 ps |
| CPU time | 86.19 seconds |
| Started | Jul 30 08:46:32 PM PDT 24 |
| Finished | Jul 30 08:47:58 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-efd8d7d5-4cb2-44ba-8753-e629f724e7e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441902337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.3441902337 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.3673368888 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 4141273537 ps |
| CPU time | 74.26 seconds |
| Started | Jul 30 08:46:34 PM PDT 24 |
| Finished | Jul 30 08:47:48 PM PDT 24 |
| Peak memory | 573964 kb |
| Host | smart-15c1a4db-1da2-4250-ae07-71adbbe90f8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673368888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.3673368888 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.4055046257 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 41803451 ps |
| CPU time | 6.06 seconds |
| Started | Jul 30 08:46:31 PM PDT 24 |
| Finished | Jul 30 08:46:37 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-7306f61c-7f91-458c-b740-9cb50bc87c28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055046257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.4055046257 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.2343479717 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 2833630193 ps |
| CPU time | 217.43 seconds |
| Started | Jul 30 08:46:37 PM PDT 24 |
| Finished | Jul 30 08:50:14 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-4ecf4c83-0c25-451b-83ff-a1c93d451fa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343479717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.2343479717 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.3790669387 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 2998519427 ps |
| CPU time | 252.3 seconds |
| Started | Jul 30 08:46:37 PM PDT 24 |
| Finished | Jul 30 08:50:50 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-e86888a3-84b4-43ce-909f-2fb564a20510 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790669387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.3790669387 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.3703248750 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 1443836534 ps |
| CPU time | 116.72 seconds |
| Started | Jul 30 08:46:37 PM PDT 24 |
| Finished | Jul 30 08:48:34 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-22b1b3fc-441e-4858-b7a2-3330bea779c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703248750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.3703248750 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.468891322 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 26930407 ps |
| CPU time | 6.08 seconds |
| Started | Jul 30 08:46:36 PM PDT 24 |
| Finished | Jul 30 08:46:42 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-625b5698-f59d-4b42-b0be-ffab50e9e496 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468891322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.468891322 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.3800650599 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 134004853 ps |
| CPU time | 11.37 seconds |
| Started | Jul 30 08:46:45 PM PDT 24 |
| Finished | Jul 30 08:46:56 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-ac78f70d-314e-4d1f-ad63-2bb3f3ea6859 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800650599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .3800650599 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.642148038 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 69266020591 ps |
| CPU time | 1185.19 seconds |
| Started | Jul 30 08:46:49 PM PDT 24 |
| Finished | Jul 30 09:06:35 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-42b046c5-25a9-4847-b659-f67758c17b8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642148038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_d evice_slow_rsp.642148038 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.82853172 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 1410586688 ps |
| CPU time | 53.26 seconds |
| Started | Jul 30 08:46:47 PM PDT 24 |
| Finished | Jul 30 08:47:41 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-c7e5b4d3-27a7-4a0b-b8c1-92e83ce52316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82853172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_addr.82853172 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.3892487764 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 815404044 ps |
| CPU time | 30.2 seconds |
| Started | Jul 30 08:46:47 PM PDT 24 |
| Finished | Jul 30 08:47:17 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-3c220a74-72b0-410f-9018-4cfb972ff837 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892487764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.3892487764 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.107483678 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 396522828 ps |
| CPU time | 36.64 seconds |
| Started | Jul 30 08:46:46 PM PDT 24 |
| Finished | Jul 30 08:47:23 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-56792141-da2e-4e74-bee4-89df38e0fc4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107483678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.107483678 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.305295930 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 15782851567 ps |
| CPU time | 182.77 seconds |
| Started | Jul 30 08:46:46 PM PDT 24 |
| Finished | Jul 30 08:49:49 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-cdb4527d-c903-4728-a70e-02aeae8b6636 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305295930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.305295930 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.2626369365 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 3407894300 ps |
| CPU time | 57.05 seconds |
| Started | Jul 30 08:46:43 PM PDT 24 |
| Finished | Jul 30 08:47:40 PM PDT 24 |
| Peak memory | 573896 kb |
| Host | smart-b761817c-5103-431a-b162-60f5e399f90b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626369365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.2626369365 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.3203327032 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 194398762 ps |
| CPU time | 20.45 seconds |
| Started | Jul 30 08:46:44 PM PDT 24 |
| Finished | Jul 30 08:47:05 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-3c9c7314-2737-4a2d-aa56-d3a021224bd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203327032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.3203327032 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.3635807790 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 2134330016 ps |
| CPU time | 68.1 seconds |
| Started | Jul 30 08:46:53 PM PDT 24 |
| Finished | Jul 30 08:48:01 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-e1619d4b-adea-4d3e-ad7e-7c826aacc02d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635807790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.3635807790 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.1773849529 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 48885387 ps |
| CPU time | 6.82 seconds |
| Started | Jul 30 08:46:41 PM PDT 24 |
| Finished | Jul 30 08:46:48 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-4ba4f589-988c-4dc4-93ee-1b217f6390cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773849529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.1773849529 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.3236002339 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 7805505091 ps |
| CPU time | 83.43 seconds |
| Started | Jul 30 08:46:41 PM PDT 24 |
| Finished | Jul 30 08:48:05 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-b1ed4289-3fe6-4859-9685-d980481a37fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236002339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.3236002339 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.699983741 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 4324455353 ps |
| CPU time | 78.7 seconds |
| Started | Jul 30 08:46:43 PM PDT 24 |
| Finished | Jul 30 08:48:02 PM PDT 24 |
| Peak memory | 573960 kb |
| Host | smart-a78fba1e-eb5a-4501-8d60-127733f5af9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699983741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.699983741 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.2256503125 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 54845712 ps |
| CPU time | 6.65 seconds |
| Started | Jul 30 08:46:42 PM PDT 24 |
| Finished | Jul 30 08:46:49 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-371aa137-3829-4dcf-a5ac-cf1e1279f21a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256503125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.2256503125 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.3981395473 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 13059810268 ps |
| CPU time | 464.66 seconds |
| Started | Jul 30 08:46:50 PM PDT 24 |
| Finished | Jul 30 08:54:35 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-3db1722b-0fc3-4619-8387-090fc7bee14b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981395473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.3981395473 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.3114420039 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 421920333 ps |
| CPU time | 41.83 seconds |
| Started | Jul 30 08:47:03 PM PDT 24 |
| Finished | Jul 30 08:47:45 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-ae25c42c-a201-49a4-939b-3115bcfcfefa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114420039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.3114420039 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.2810636008 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 199500937 ps |
| CPU time | 125.91 seconds |
| Started | Jul 30 08:46:47 PM PDT 24 |
| Finished | Jul 30 08:48:53 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-1f4f388d-2cca-4901-b189-634284bbf1de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810636008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.2810636008 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.2059254180 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 2779408690 ps |
| CPU time | 416.1 seconds |
| Started | Jul 30 08:46:54 PM PDT 24 |
| Finished | Jul 30 08:53:50 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-eb5da294-f9a4-4242-a6c0-ad288b25e378 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059254180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.2059254180 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.4287410797 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 198316444 ps |
| CPU time | 11.81 seconds |
| Started | Jul 30 08:46:49 PM PDT 24 |
| Finished | Jul 30 08:47:00 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-3cd81465-a9fb-4ebe-b0a3-568dabc308b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287410797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.4287410797 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.1959922215 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 513190841 ps |
| CPU time | 22.58 seconds |
| Started | Jul 30 08:47:04 PM PDT 24 |
| Finished | Jul 30 08:47:26 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-55759060-0a3f-42b7-94e9-3f99b19ba458 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959922215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .1959922215 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.2724812273 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 107717612912 ps |
| CPU time | 1839.84 seconds |
| Started | Jul 30 08:46:55 PM PDT 24 |
| Finished | Jul 30 09:17:35 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-89e8f1f6-55e5-4981-b79e-142b8053fd9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724812273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.2724812273 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.2495349944 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 176147027 ps |
| CPU time | 9.49 seconds |
| Started | Jul 30 08:46:58 PM PDT 24 |
| Finished | Jul 30 08:47:07 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-fc3bbebe-fe53-47f8-b6e7-6c76efa53bd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495349944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.2495349944 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.384920360 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 873771791 ps |
| CPU time | 33.52 seconds |
| Started | Jul 30 08:46:56 PM PDT 24 |
| Finished | Jul 30 08:47:30 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-e90405db-020f-4a92-bd9a-445475643356 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384920360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.384920360 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.1191914346 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 444928487 ps |
| CPU time | 20.38 seconds |
| Started | Jul 30 08:46:59 PM PDT 24 |
| Finished | Jul 30 08:47:19 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-a41344e9-ab95-461e-8e9d-e4809c590e7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191914346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.1191914346 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.3718239612 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 93814129804 ps |
| CPU time | 962.75 seconds |
| Started | Jul 30 08:47:03 PM PDT 24 |
| Finished | Jul 30 09:03:06 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-f9d7e23f-fa0b-466f-b29f-086350a7ccc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718239612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.3718239612 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.1940814063 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 14257099852 ps |
| CPU time | 251.93 seconds |
| Started | Jul 30 08:46:55 PM PDT 24 |
| Finished | Jul 30 08:51:07 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-156efca5-a866-416d-96e2-3bf2ad8600d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940814063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.1940814063 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.2416894185 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 387791645 ps |
| CPU time | 38.56 seconds |
| Started | Jul 30 08:46:58 PM PDT 24 |
| Finished | Jul 30 08:47:37 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-eae7ef31-cd52-4612-94c4-1341491b933c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416894185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.2416894185 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.3193496815 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 163182727 ps |
| CPU time | 15.13 seconds |
| Started | Jul 30 08:47:04 PM PDT 24 |
| Finished | Jul 30 08:47:19 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-602b51e7-b961-41db-974f-09d35fe6bb06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193496815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.3193496815 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.2808848616 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 197829439 ps |
| CPU time | 9.25 seconds |
| Started | Jul 30 08:47:04 PM PDT 24 |
| Finished | Jul 30 08:47:13 PM PDT 24 |
| Peak memory | 573876 kb |
| Host | smart-a32e96b5-4428-4cb1-aa17-4c82c3bed7b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808848616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.2808848616 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.1249743456 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 9534795643 ps |
| CPU time | 103.21 seconds |
| Started | Jul 30 08:46:51 PM PDT 24 |
| Finished | Jul 30 08:48:35 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-30d745f6-ddd5-4561-a8f2-a310bf36d7ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249743456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.1249743456 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.362724891 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 4374488803 ps |
| CPU time | 79.03 seconds |
| Started | Jul 30 08:47:04 PM PDT 24 |
| Finished | Jul 30 08:48:23 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-78840e5a-f29f-4d64-a491-4551f38395c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362724891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.362724891 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.4264724141 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 43718467 ps |
| CPU time | 6.01 seconds |
| Started | Jul 30 08:46:51 PM PDT 24 |
| Finished | Jul 30 08:46:57 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-585f3024-6ff6-404e-9acd-67de4cf20820 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264724141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.4264724141 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.3671069025 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 11374306930 ps |
| CPU time | 405.06 seconds |
| Started | Jul 30 08:46:58 PM PDT 24 |
| Finished | Jul 30 08:53:43 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-c9994f4e-4cb2-40e9-b163-f0e68044df0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671069025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.3671069025 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.3543610503 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 14520127875 ps |
| CPU time | 549.64 seconds |
| Started | Jul 30 08:46:58 PM PDT 24 |
| Finished | Jul 30 08:56:08 PM PDT 24 |
| Peak memory | 576860 kb |
| Host | smart-a863548a-ff56-4d6e-a3ab-6072885a078f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543610503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.3543610503 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.473291404 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 378995953 ps |
| CPU time | 142.23 seconds |
| Started | Jul 30 08:46:58 PM PDT 24 |
| Finished | Jul 30 08:49:21 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-eed5f618-2f0a-45cb-b5da-dd603f19f640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473291404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_ with_rand_reset.473291404 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3015331250 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 2024521948 ps |
| CPU time | 209.94 seconds |
| Started | Jul 30 08:46:57 PM PDT 24 |
| Finished | Jul 30 08:50:27 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-57a4e89f-3ad0-420a-a81d-2f4d1bafcb3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015331250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.3015331250 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.2127656905 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 376575606 ps |
| CPU time | 21.67 seconds |
| Started | Jul 30 08:46:57 PM PDT 24 |
| Finished | Jul 30 08:47:19 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-90ba5b37-cb9e-4fb0-a217-e0c139ba1988 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127656905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.2127656905 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.844587047 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 3086499526 ps |
| CPU time | 123.61 seconds |
| Started | Jul 30 08:47:06 PM PDT 24 |
| Finished | Jul 30 08:49:10 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-f72c8f58-9a27-4574-8034-aaf905c59b9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844587047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device. 844587047 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.1435095202 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 73426333567 ps |
| CPU time | 1177.77 seconds |
| Started | Jul 30 08:47:07 PM PDT 24 |
| Finished | Jul 30 09:06:45 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-6a247089-f1a2-46f8-8001-c200501bbc87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435095202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.1435095202 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.3655742683 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 651065062 ps |
| CPU time | 29.49 seconds |
| Started | Jul 30 08:47:05 PM PDT 24 |
| Finished | Jul 30 08:47:34 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-db2e4c83-c685-40a8-b736-4261657415e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655742683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add r.3655742683 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.3470782087 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 379069482 ps |
| CPU time | 37.1 seconds |
| Started | Jul 30 08:47:05 PM PDT 24 |
| Finished | Jul 30 08:47:42 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-421e2f9e-dfbf-4e97-ab28-523ce5219c0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470782087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.3470782087 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.1053364762 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1775237520 ps |
| CPU time | 65.58 seconds |
| Started | Jul 30 08:47:02 PM PDT 24 |
| Finished | Jul 30 08:48:07 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-a81a54a6-9e6b-4d41-9103-09f54414966c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053364762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.1053364762 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.4023548374 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 53348918468 ps |
| CPU time | 590.39 seconds |
| Started | Jul 30 08:47:06 PM PDT 24 |
| Finished | Jul 30 08:56:57 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-6e911f00-d29e-4600-88ca-abefd231bc27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023548374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.4023548374 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.3310686606 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 16285254339 ps |
| CPU time | 280.12 seconds |
| Started | Jul 30 08:47:06 PM PDT 24 |
| Finished | Jul 30 08:51:46 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-561e4f7a-b1b7-4b96-a144-77a3d9a2f663 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310686606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.3310686606 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.3337803281 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 515668972 ps |
| CPU time | 54.18 seconds |
| Started | Jul 30 08:47:02 PM PDT 24 |
| Finished | Jul 30 08:47:56 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-553a069a-5a5a-41cc-a590-c282c92ee046 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337803281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.3337803281 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.3209402085 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1308025179 ps |
| CPU time | 41.55 seconds |
| Started | Jul 30 08:47:06 PM PDT 24 |
| Finished | Jul 30 08:47:48 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-150a7ebc-f162-473c-b752-2c883e6eb2a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209402085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.3209402085 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.247069895 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 208178079 ps |
| CPU time | 9.18 seconds |
| Started | Jul 30 08:47:02 PM PDT 24 |
| Finished | Jul 30 08:47:11 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-145e7661-2ebb-4b5f-b8eb-878c3ed107d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247069895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.247069895 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.1571322626 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 9029238001 ps |
| CPU time | 88.82 seconds |
| Started | Jul 30 08:47:00 PM PDT 24 |
| Finished | Jul 30 08:48:29 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-7c194826-84aa-4cf9-9907-172d4d33606a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571322626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.1571322626 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.859492584 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 6007925258 ps |
| CPU time | 107.68 seconds |
| Started | Jul 30 08:47:02 PM PDT 24 |
| Finished | Jul 30 08:48:50 PM PDT 24 |
| Peak memory | 573964 kb |
| Host | smart-1a8f791a-2ea7-484f-acd7-e09e9c7bf2d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859492584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.859492584 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.130596671 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 52423436 ps |
| CPU time | 6.72 seconds |
| Started | Jul 30 08:47:02 PM PDT 24 |
| Finished | Jul 30 08:47:09 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-810b7b9c-e050-4ab4-a673-748094369ba8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130596671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delays .130596671 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.1649915267 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 971812097 ps |
| CPU time | 74.36 seconds |
| Started | Jul 30 08:47:12 PM PDT 24 |
| Finished | Jul 30 08:48:27 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-ba6d2b1a-1fe3-4578-8d15-f6b77e41d30b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649915267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.1649915267 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.3379554774 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 636633591 ps |
| CPU time | 56.77 seconds |
| Started | Jul 30 08:47:10 PM PDT 24 |
| Finished | Jul 30 08:48:07 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-5901f001-22c2-4400-8090-744aae31cfdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379554774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.3379554774 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.2172146367 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 12867774172 ps |
| CPU time | 711.17 seconds |
| Started | Jul 30 08:47:08 PM PDT 24 |
| Finished | Jul 30 08:58:59 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-1bd8218d-6f46-4d67-a975-9783a253bef9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172146367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.2172146367 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3341470583 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 2017719334 ps |
| CPU time | 261.45 seconds |
| Started | Jul 30 08:47:13 PM PDT 24 |
| Finished | Jul 30 08:51:35 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-c69eb165-fe3d-4f8a-a44b-f08235018f8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341470583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.3341470583 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.3855585927 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 850892513 ps |
| CPU time | 35.04 seconds |
| Started | Jul 30 08:47:06 PM PDT 24 |
| Finished | Jul 30 08:47:41 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-a79c4343-ebda-4636-994c-f2aa0b68a50d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855585927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.3855585927 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.2533000300 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 2733080638 ps |
| CPU time | 115.8 seconds |
| Started | Jul 30 08:47:15 PM PDT 24 |
| Finished | Jul 30 08:49:11 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-f78929ac-0cc7-4391-909c-8c997b6c8d9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533000300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .2533000300 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.1163787020 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 40086974268 ps |
| CPU time | 687.85 seconds |
| Started | Jul 30 08:47:20 PM PDT 24 |
| Finished | Jul 30 08:58:48 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-ee072aee-b2ab-43ce-9a55-9e9f02d8ad77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163787020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.1163787020 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.2868794859 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 48948345 ps |
| CPU time | 8.29 seconds |
| Started | Jul 30 08:47:16 PM PDT 24 |
| Finished | Jul 30 08:47:25 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-31365917-319f-4060-bb6e-01d719c5fae1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868794859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.2868794859 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.3399113655 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 2012914049 ps |
| CPU time | 72.34 seconds |
| Started | Jul 30 08:47:15 PM PDT 24 |
| Finished | Jul 30 08:48:28 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-2f890bc0-3508-4dbb-acb3-2e0c20b74869 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399113655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.3399113655 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.3864386040 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 424222409 ps |
| CPU time | 43.82 seconds |
| Started | Jul 30 08:47:16 PM PDT 24 |
| Finished | Jul 30 08:48:00 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-9c841504-e2df-447e-909d-a5086d8bd11e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864386040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.3864386040 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.1851894624 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 66005424358 ps |
| CPU time | 652.79 seconds |
| Started | Jul 30 08:47:13 PM PDT 24 |
| Finished | Jul 30 08:58:06 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-4c597ba5-9a6c-4b48-a541-ea3c930e1c2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851894624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.1851894624 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.13827838 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 20476973396 ps |
| CPU time | 373.78 seconds |
| Started | Jul 30 08:47:18 PM PDT 24 |
| Finished | Jul 30 08:53:32 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-6668a512-8a47-488a-a729-e1a62f40c891 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13827838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.13827838 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.2669675837 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 392587478 ps |
| CPU time | 35.99 seconds |
| Started | Jul 30 08:47:14 PM PDT 24 |
| Finished | Jul 30 08:47:50 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-45aa0014-bff9-468f-92d8-3366f834f6f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669675837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.2669675837 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.2065936224 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 103919340 ps |
| CPU time | 11 seconds |
| Started | Jul 30 08:47:19 PM PDT 24 |
| Finished | Jul 30 08:47:30 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-92f56ddd-bf8d-4d1a-80be-b43420dcd3cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065936224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.2065936224 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.703949182 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 165917384 ps |
| CPU time | 9.21 seconds |
| Started | Jul 30 08:47:09 PM PDT 24 |
| Finished | Jul 30 08:47:19 PM PDT 24 |
| Peak memory | 573876 kb |
| Host | smart-b5dbbba4-8a9e-4b2f-a46d-45172843ac84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703949182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.703949182 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.2735039401 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 7471119944 ps |
| CPU time | 82.13 seconds |
| Started | Jul 30 08:47:09 PM PDT 24 |
| Finished | Jul 30 08:48:31 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-e8ffbc3a-51d8-44d1-85a0-73a87905a429 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735039401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.2735039401 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.1466918649 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 5343198940 ps |
| CPU time | 92.62 seconds |
| Started | Jul 30 08:47:12 PM PDT 24 |
| Finished | Jul 30 08:48:45 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-04873872-1dee-4792-b59a-e1152ed80c4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466918649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.1466918649 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.1609454699 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 35836201 ps |
| CPU time | 6.33 seconds |
| Started | Jul 30 08:47:10 PM PDT 24 |
| Finished | Jul 30 08:47:17 PM PDT 24 |
| Peak memory | 573832 kb |
| Host | smart-b05ab572-fa17-441e-bc75-d33debea7cbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609454699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.1609454699 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.28216392 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 1863791086 ps |
| CPU time | 176.97 seconds |
| Started | Jul 30 08:47:15 PM PDT 24 |
| Finished | Jul 30 08:50:13 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-14d8aee9-41de-4ce4-bff2-3cf02dea65cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28216392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.28216392 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.750978183 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 5998361123 ps |
| CPU time | 240.42 seconds |
| Started | Jul 30 08:47:21 PM PDT 24 |
| Finished | Jul 30 08:51:21 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-5bff0f5d-b906-42c5-a0a6-716a266eb614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750978183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.750978183 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.3299272602 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 2047896219 ps |
| CPU time | 287.51 seconds |
| Started | Jul 30 08:47:16 PM PDT 24 |
| Finished | Jul 30 08:52:03 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-8bcc3f41-b1e1-4c65-a1b9-0bfb1c90c58f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299272602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.3299272602 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.391142101 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 1085631807 ps |
| CPU time | 163.8 seconds |
| Started | Jul 30 08:47:19 PM PDT 24 |
| Finished | Jul 30 08:50:03 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-8f9afcb7-3b29-4bd8-962b-544ce51a8f52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391142101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_reset_error.391142101 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.3829149879 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 73998519 ps |
| CPU time | 12.07 seconds |
| Started | Jul 30 08:47:19 PM PDT 24 |
| Finished | Jul 30 08:47:31 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-4344e0ad-70b8-4b8c-b7b0-1c171ae6bfb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829149879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.3829149879 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.904397913 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 959479917 ps |
| CPU time | 44.23 seconds |
| Started | Jul 30 08:47:28 PM PDT 24 |
| Finished | Jul 30 08:48:12 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-d3dc9c67-ff57-4a9d-9e78-e3188360d02b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904397913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device. 904397913 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.2948934593 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 10478371474 ps |
| CPU time | 171.41 seconds |
| Started | Jul 30 08:47:26 PM PDT 24 |
| Finished | Jul 30 08:50:18 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-56d0aa08-bd05-43fa-bba6-4e1178533ecc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948934593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_ device_slow_rsp.2948934593 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2310949009 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 315361425 ps |
| CPU time | 33.47 seconds |
| Started | Jul 30 08:47:30 PM PDT 24 |
| Finished | Jul 30 08:48:03 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-2e3c41ca-0b3a-4ca4-8dec-3424dd3ef47a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310949009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.2310949009 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.3432080641 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 1189252071 ps |
| CPU time | 43.39 seconds |
| Started | Jul 30 08:47:29 PM PDT 24 |
| Finished | Jul 30 08:48:12 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-52053d83-4771-4d43-84da-172d23f311e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432080641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.3432080641 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.2232087937 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 191396328 ps |
| CPU time | 21.12 seconds |
| Started | Jul 30 08:47:23 PM PDT 24 |
| Finished | Jul 30 08:47:44 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-3410effc-cc88-4268-9c6b-bb99014ebf7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232087937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.2232087937 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.1302810069 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 11078095001 ps |
| CPU time | 191.07 seconds |
| Started | Jul 30 08:47:23 PM PDT 24 |
| Finished | Jul 30 08:50:34 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-b5bd7e16-210b-4c86-b955-0711c0585859 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302810069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.1302810069 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.4215690113 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 34759560 ps |
| CPU time | 6.66 seconds |
| Started | Jul 30 08:47:22 PM PDT 24 |
| Finished | Jul 30 08:47:28 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-44f14457-f994-4f7f-a0b2-a60069f55936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215690113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del ays.4215690113 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.1527950746 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 1929673044 ps |
| CPU time | 56.33 seconds |
| Started | Jul 30 08:47:27 PM PDT 24 |
| Finished | Jul 30 08:48:23 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-2298e62d-36e3-41f1-81c2-5e657abe70f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527950746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.1527950746 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.1370735114 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 204221922 ps |
| CPU time | 9.6 seconds |
| Started | Jul 30 08:47:23 PM PDT 24 |
| Finished | Jul 30 08:47:32 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-4151897b-149a-4fb9-8a49-19a5f13308b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370735114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.1370735114 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.3886867159 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 8576813750 ps |
| CPU time | 93.81 seconds |
| Started | Jul 30 08:47:25 PM PDT 24 |
| Finished | Jul 30 08:48:59 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-9e235145-d62b-4852-ad4a-e33516250b00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886867159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.3886867159 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.1197366672 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 3125244520 ps |
| CPU time | 52.96 seconds |
| Started | Jul 30 08:47:23 PM PDT 24 |
| Finished | Jul 30 08:48:16 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-ce164506-424f-4284-8429-f3a80f9dfdcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197366672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.1197366672 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.787925629 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 46506810 ps |
| CPU time | 6.36 seconds |
| Started | Jul 30 08:47:23 PM PDT 24 |
| Finished | Jul 30 08:47:29 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-01fe21e6-b605-4fa1-b466-c857d9d6cefd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787925629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delays .787925629 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.3725005572 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 7155216036 ps |
| CPU time | 250.25 seconds |
| Started | Jul 30 08:47:32 PM PDT 24 |
| Finished | Jul 30 08:51:42 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-a5073b60-ac08-40ee-a66b-c8ffd34a383e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725005572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.3725005572 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.1937345217 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 433879761 ps |
| CPU time | 28.53 seconds |
| Started | Jul 30 08:47:31 PM PDT 24 |
| Finished | Jul 30 08:47:59 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-6b44aa86-ec95-4815-a98e-2c396c612324 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937345217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.1937345217 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.2776845050 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 152708772 ps |
| CPU time | 51.01 seconds |
| Started | Jul 30 08:47:29 PM PDT 24 |
| Finished | Jul 30 08:48:20 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-de0cf14f-5643-4903-b9ff-73f88b3bff0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776845050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.2776845050 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.251651845 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 1482327572 ps |
| CPU time | 213.13 seconds |
| Started | Jul 30 08:47:35 PM PDT 24 |
| Finished | Jul 30 08:51:08 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-ae3d22b2-f5bf-4a6c-988b-ae14ffe3f9aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251651845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_reset_error.251651845 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.540091144 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 20154324 ps |
| CPU time | 6.06 seconds |
| Started | Jul 30 08:47:30 PM PDT 24 |
| Finished | Jul 30 08:47:36 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-7515d014-e51b-4e8d-9661-dfe0c7b860b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540091144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.540091144 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.484062945 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 7074981104 ps |
| CPU time | 478.8 seconds |
| Started | Jul 30 08:31:01 PM PDT 24 |
| Finished | Jul 30 08:39:00 PM PDT 24 |
| Peak memory | 640564 kb |
| Host | smart-39c7c5ad-64eb-403a-8d28-12b0ddab52b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484062945 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.484062945 |
| Directory | /workspace/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.932883378 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 5794242231 ps |
| CPU time | 714.45 seconds |
| Started | Jul 30 08:30:55 PM PDT 24 |
| Finished | Jul 30 08:42:50 PM PDT 24 |
| Peak memory | 598988 kb |
| Host | smart-43ae148f-3443-4e1d-b77b-8f1e9355a7e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932883378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.932883378 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.3015867057 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 17874576888 ps |
| CPU time | 2181.25 seconds |
| Started | Jul 30 08:30:32 PM PDT 24 |
| Finished | Jul 30 09:06:53 PM PDT 24 |
| Peak memory | 593244 kb |
| Host | smart-4e88ab76-bddc-49cd-84da-0a7c7bd2e441 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015867057 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.3015867057 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.1767006732 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 3785148226 ps |
| CPU time | 227.64 seconds |
| Started | Jul 30 08:30:37 PM PDT 24 |
| Finished | Jul 30 08:34:24 PM PDT 24 |
| Peak memory | 603060 kb |
| Host | smart-43dd8f32-0fdd-466d-9000-8280e53d005b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767006732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.1767006732 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.2629577048 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 445013445 ps |
| CPU time | 40.03 seconds |
| Started | Jul 30 08:30:42 PM PDT 24 |
| Finished | Jul 30 08:31:22 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-52f63de4-03ac-4114-a2e2-964c9021833e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629577048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 2629577048 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2262458474 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 71430773057 ps |
| CPU time | 1314.5 seconds |
| Started | Jul 30 08:30:46 PM PDT 24 |
| Finished | Jul 30 08:52:40 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-08aba46a-4c3d-42ab-8227-488b8883dce4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262458474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.2262458474 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.4070682062 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 303813616 ps |
| CPU time | 40.85 seconds |
| Started | Jul 30 08:30:50 PM PDT 24 |
| Finished | Jul 30 08:31:31 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-7c569ae9-1d56-4d60-8838-115bf4130cc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070682062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .4070682062 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.4178806134 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 364273757 ps |
| CPU time | 35.51 seconds |
| Started | Jul 30 08:30:51 PM PDT 24 |
| Finished | Jul 30 08:31:26 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-0d796a0d-5a46-4fbf-99eb-d3e40ec0131d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178806134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.4178806134 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.4115713628 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 562514581 ps |
| CPU time | 22.57 seconds |
| Started | Jul 30 08:30:37 PM PDT 24 |
| Finished | Jul 30 08:31:00 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-9a686f4f-8d9a-45bc-a570-b6f42cc885e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115713628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.4115713628 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.876070861 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 8488861241 ps |
| CPU time | 92.37 seconds |
| Started | Jul 30 08:30:37 PM PDT 24 |
| Finished | Jul 30 08:32:10 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-151a4f9c-a742-40d0-9829-d6379886c609 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876070861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.876070861 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.401599802 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 15889060009 ps |
| CPU time | 277.94 seconds |
| Started | Jul 30 08:30:39 PM PDT 24 |
| Finished | Jul 30 08:35:17 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-d8aa7ae8-7aee-4375-a6a7-933f808ac91c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401599802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.401599802 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.3129243041 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 661516333 ps |
| CPU time | 62.14 seconds |
| Started | Jul 30 08:30:37 PM PDT 24 |
| Finished | Jul 30 08:31:40 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-89b882cd-4750-4c74-8bf0-fbb777cb9881 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129243041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.3129243041 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.2892679640 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 2121021919 ps |
| CPU time | 72.05 seconds |
| Started | Jul 30 08:30:46 PM PDT 24 |
| Finished | Jul 30 08:31:58 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-a0e60c78-b7c9-46de-8d01-fd78da4e56b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892679640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2892679640 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.209325173 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 178326254 ps |
| CPU time | 8.88 seconds |
| Started | Jul 30 08:30:35 PM PDT 24 |
| Finished | Jul 30 08:30:44 PM PDT 24 |
| Peak memory | 573752 kb |
| Host | smart-fe377388-5058-473c-b605-701c6c7ed123 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209325173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.209325173 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.2567344314 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 8810924097 ps |
| CPU time | 95.01 seconds |
| Started | Jul 30 08:30:34 PM PDT 24 |
| Finished | Jul 30 08:32:10 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-6a8259f7-7d31-45b7-8ed4-e5fb69327bd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567344314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2567344314 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.2418705064 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 5308332175 ps |
| CPU time | 94.75 seconds |
| Started | Jul 30 08:30:56 PM PDT 24 |
| Finished | Jul 30 08:32:31 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-f3ddca15-93b8-40eb-9137-f808fe92ebc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418705064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2418705064 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.319702471 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 43233225 ps |
| CPU time | 6.89 seconds |
| Started | Jul 30 08:30:35 PM PDT 24 |
| Finished | Jul 30 08:30:42 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-6c08c12a-72ab-44b7-b6ae-83eb60e43bf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319702471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays. 319702471 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.2767720541 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 504063448 ps |
| CPU time | 46.51 seconds |
| Started | Jul 30 08:30:53 PM PDT 24 |
| Finished | Jul 30 08:31:40 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-a9cfbaf7-6f6a-4820-8dd9-c18b8cefbd11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767720541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2767720541 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.3768175974 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 6916596392 ps |
| CPU time | 769.49 seconds |
| Started | Jul 30 08:30:57 PM PDT 24 |
| Finished | Jul 30 08:43:47 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-75fd8d08-015f-4af2-aa86-b510668f73f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768175974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.3768175974 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.4079271266 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 7734384 ps |
| CPU time | 13.54 seconds |
| Started | Jul 30 08:30:56 PM PDT 24 |
| Finished | Jul 30 08:31:10 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-96cfd27f-a646-499a-af11-210039f64da9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079271266 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all _with_reset_error.4079271266 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.3132576609 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 329060830 ps |
| CPU time | 16.39 seconds |
| Started | Jul 30 08:30:54 PM PDT 24 |
| Finished | Jul 30 08:31:10 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-32d34796-25b0-48a6-8be2-4d659d9623f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132576609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3132576609 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.1748296704 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 293969067 ps |
| CPU time | 16.31 seconds |
| Started | Jul 30 08:47:35 PM PDT 24 |
| Finished | Jul 30 08:47:51 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-d163a48d-6610-4f92-8774-5db9be1740fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748296704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .1748296704 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.1964853543 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 624024173 ps |
| CPU time | 30.47 seconds |
| Started | Jul 30 08:47:38 PM PDT 24 |
| Finished | Jul 30 08:48:09 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-f781df14-a6b9-43ea-9f17-79b488196e14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964853543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.1964853543 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.171025705 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 492250711 ps |
| CPU time | 44.17 seconds |
| Started | Jul 30 08:47:38 PM PDT 24 |
| Finished | Jul 30 08:48:22 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-dc504f80-ba5e-4da1-b80b-582aabd33735 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171025705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.171025705 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.329109706 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 355889687 ps |
| CPU time | 37.06 seconds |
| Started | Jul 30 08:47:37 PM PDT 24 |
| Finished | Jul 30 08:48:14 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-b2fd4f75-b004-40c0-a63b-b9e11590c1e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329109706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.329109706 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.203464023 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 9219170328 ps |
| CPU time | 97.08 seconds |
| Started | Jul 30 08:47:38 PM PDT 24 |
| Finished | Jul 30 08:49:15 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-1ac17ff9-04ee-493b-a8fd-339ac1da59cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203464023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.203464023 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.3160650469 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 61388223691 ps |
| CPU time | 1084.52 seconds |
| Started | Jul 30 08:47:36 PM PDT 24 |
| Finished | Jul 30 09:05:41 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-207e776e-acec-4a72-b49d-365c20ec3b8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160650469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.3160650469 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.3946264950 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 505608226 ps |
| CPU time | 45.22 seconds |
| Started | Jul 30 08:47:34 PM PDT 24 |
| Finished | Jul 30 08:48:19 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-d394c389-35d5-445e-bad7-2a44f8910ad5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946264950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.3946264950 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.2685105318 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 386731897 ps |
| CPU time | 27.39 seconds |
| Started | Jul 30 08:47:37 PM PDT 24 |
| Finished | Jul 30 08:48:04 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-f305deb5-97b1-46a0-82fd-23b5b6131325 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685105318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.2685105318 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.1024916297 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 237947469 ps |
| CPU time | 10.95 seconds |
| Started | Jul 30 08:47:31 PM PDT 24 |
| Finished | Jul 30 08:47:42 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-f120975b-14f2-4fec-8eef-b924e950192a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024916297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.1024916297 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.2421042328 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 7269822983 ps |
| CPU time | 77.34 seconds |
| Started | Jul 30 08:47:34 PM PDT 24 |
| Finished | Jul 30 08:48:51 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-c2e30d2f-6c3a-4b0a-bfbd-9536b9a8f8c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421042328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.2421042328 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.4065218986 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 4147640014 ps |
| CPU time | 75.47 seconds |
| Started | Jul 30 08:47:38 PM PDT 24 |
| Finished | Jul 30 08:48:54 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-5872eba5-255a-4dec-af80-9b4f162046de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065218986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.4065218986 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.911262659 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 56323005 ps |
| CPU time | 6.91 seconds |
| Started | Jul 30 08:47:30 PM PDT 24 |
| Finished | Jul 30 08:47:37 PM PDT 24 |
| Peak memory | 573876 kb |
| Host | smart-31c69bfc-236a-409a-97f1-83a6abe748ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911262659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delays .911262659 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.2850844171 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 3276579397 ps |
| CPU time | 122.51 seconds |
| Started | Jul 30 08:47:37 PM PDT 24 |
| Finished | Jul 30 08:49:40 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-7dedf502-110f-4b8d-9ac7-7992b9f9655d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850844171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.2850844171 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.365097155 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 2147354453 ps |
| CPU time | 171.54 seconds |
| Started | Jul 30 08:47:38 PM PDT 24 |
| Finished | Jul 30 08:50:30 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-637cfdc0-fbfc-4555-8768-f2cf409635a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365097155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.365097155 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.568370645 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 272524875 ps |
| CPU time | 90.93 seconds |
| Started | Jul 30 08:47:39 PM PDT 24 |
| Finished | Jul 30 08:49:10 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-478e9d8d-1277-43a6-9026-5a47546f8d7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568370645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_ with_rand_reset.568370645 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.3922594756 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 7188414385 ps |
| CPU time | 294.75 seconds |
| Started | Jul 30 08:47:35 PM PDT 24 |
| Finished | Jul 30 08:52:30 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-57dbc595-6093-4f5a-9c28-a6f94f85ccb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922594756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.3922594756 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.3665140495 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 673916423 ps |
| CPU time | 31.65 seconds |
| Started | Jul 30 08:47:38 PM PDT 24 |
| Finished | Jul 30 08:48:09 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-e08bbe5f-604f-48a7-b36e-0a22eace8478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665140495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.3665140495 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.1257121951 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 138817441497 ps |
| CPU time | 2243.8 seconds |
| Started | Jul 30 08:47:43 PM PDT 24 |
| Finished | Jul 30 09:25:07 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-8fd70753-2803-4e74-bc9e-161608092c8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257121951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.1257121951 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.2479384036 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 331870252 ps |
| CPU time | 42.24 seconds |
| Started | Jul 30 08:47:46 PM PDT 24 |
| Finished | Jul 30 08:48:28 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-1d9dd167-bca0-4e51-8ec8-aea9543f3c8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479384036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.2479384036 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.2828856529 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 493088558 ps |
| CPU time | 44.6 seconds |
| Started | Jul 30 08:47:48 PM PDT 24 |
| Finished | Jul 30 08:48:33 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-358bf217-32cc-4b86-9843-281b926f292a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828856529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.2828856529 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.1501158661 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 1055438575 ps |
| CPU time | 39.74 seconds |
| Started | Jul 30 08:47:44 PM PDT 24 |
| Finished | Jul 30 08:48:24 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-085bb273-29b5-444d-b373-203e8a3a1d0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501158661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.1501158661 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.775102958 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 58875532130 ps |
| CPU time | 620.59 seconds |
| Started | Jul 30 08:47:45 PM PDT 24 |
| Finished | Jul 30 08:58:05 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-0815d595-94b1-4525-a55e-468fbfdb16ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775102958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.775102958 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.2982094281 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 33257677891 ps |
| CPU time | 571.57 seconds |
| Started | Jul 30 08:47:44 PM PDT 24 |
| Finished | Jul 30 08:57:16 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-1ab89df0-98c3-4522-8dd8-3225b82328ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982094281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.2982094281 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.2871549872 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 576272626 ps |
| CPU time | 46.56 seconds |
| Started | Jul 30 08:47:41 PM PDT 24 |
| Finished | Jul 30 08:48:28 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-8d44c7d9-d114-4380-a3b7-2f84fe44105b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871549872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.2871549872 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.3908350250 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 562403671 ps |
| CPU time | 45.77 seconds |
| Started | Jul 30 08:47:47 PM PDT 24 |
| Finished | Jul 30 08:48:33 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-aeab7307-b215-4a8c-a9cf-611eaf2c11c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908350250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.3908350250 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.351125923 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 45876468 ps |
| CPU time | 6.47 seconds |
| Started | Jul 30 08:47:36 PM PDT 24 |
| Finished | Jul 30 08:47:42 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-c30c7ccf-314a-43f9-95de-74b59c5f6c44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351125923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.351125923 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.251057205 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 6609078236 ps |
| CPU time | 70.85 seconds |
| Started | Jul 30 08:47:41 PM PDT 24 |
| Finished | Jul 30 08:48:51 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-f060e90b-f918-4061-80a9-ee2f2bf38bea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251057205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.251057205 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.2342133269 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 5925333966 ps |
| CPU time | 107.11 seconds |
| Started | Jul 30 08:47:41 PM PDT 24 |
| Finished | Jul 30 08:49:28 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-3d4674f4-cbf4-4bf5-9bf9-96ff4b311404 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342133269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.2342133269 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.971041299 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 51315402 ps |
| CPU time | 6.93 seconds |
| Started | Jul 30 08:47:37 PM PDT 24 |
| Finished | Jul 30 08:47:44 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-09c2eb0f-db61-43d5-ba72-3276c52c13c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971041299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delays .971041299 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.7104199 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 2945093386 ps |
| CPU time | 257.88 seconds |
| Started | Jul 30 08:47:49 PM PDT 24 |
| Finished | Jul 30 08:52:07 PM PDT 24 |
| Peak memory | 576872 kb |
| Host | smart-bbfaf980-aa10-4b74-abe3-a3e0f419b2de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7104199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.7104199 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.2671948347 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 17049405296 ps |
| CPU time | 534.51 seconds |
| Started | Jul 30 08:47:48 PM PDT 24 |
| Finished | Jul 30 08:56:43 PM PDT 24 |
| Peak memory | 576828 kb |
| Host | smart-5cbbbbee-624a-4899-9385-34e87a3b4005 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671948347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.2671948347 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.2144578565 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 6860755137 ps |
| CPU time | 485.12 seconds |
| Started | Jul 30 08:47:49 PM PDT 24 |
| Finished | Jul 30 08:55:54 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-27997a2c-581a-43fe-a335-4f8b7c9386ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144578565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.2144578565 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.266702279 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 3731256554 ps |
| CPU time | 173.34 seconds |
| Started | Jul 30 08:47:51 PM PDT 24 |
| Finished | Jul 30 08:50:45 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-f6461bab-a89f-4a3f-8a43-de8f79a4bb80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266702279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_reset_error.266702279 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.3029012294 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 1033218588 ps |
| CPU time | 50.02 seconds |
| Started | Jul 30 08:47:48 PM PDT 24 |
| Finished | Jul 30 08:48:38 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-227c6d5e-0d92-4c46-9436-b88eb2cdd2b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029012294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.3029012294 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.1590731736 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 870786698 ps |
| CPU time | 82.67 seconds |
| Started | Jul 30 08:47:55 PM PDT 24 |
| Finished | Jul 30 08:49:18 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-00368d52-238a-4f88-aa10-5ab163d26dbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590731736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .1590731736 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.335262745 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 163303323442 ps |
| CPU time | 2776.58 seconds |
| Started | Jul 30 08:47:55 PM PDT 24 |
| Finished | Jul 30 09:34:12 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-74c0c06c-38ce-4a71-9639-8cffcb4e2d0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335262745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_d evice_slow_rsp.335262745 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.999347348 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 692728590 ps |
| CPU time | 27.46 seconds |
| Started | Jul 30 08:47:58 PM PDT 24 |
| Finished | Jul 30 08:48:25 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-d99ba7e7-1229-491d-ab4e-0c01eac98731 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999347348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_addr .999347348 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.3296057817 |
| Short name | T2932 |
| Test name | |
| Test status | |
| Simulation time | 423351990 ps |
| CPU time | 42.02 seconds |
| Started | Jul 30 08:47:51 PM PDT 24 |
| Finished | Jul 30 08:48:33 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-34ed6886-16c3-4dd9-b78f-98351d2f5adc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296057817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.3296057817 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.2214812289 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 16814766007 ps |
| CPU time | 168.9 seconds |
| Started | Jul 30 08:47:57 PM PDT 24 |
| Finished | Jul 30 08:50:46 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-5ed648a8-59e0-4607-b3fc-1d79bc258655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214812289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.2214812289 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.2531194460 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 46478038205 ps |
| CPU time | 804.76 seconds |
| Started | Jul 30 08:47:55 PM PDT 24 |
| Finished | Jul 30 09:01:20 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-1a87f4c9-37bc-4737-94d7-77446faf7b50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531194460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.2531194460 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.805052073 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 309243869 ps |
| CPU time | 30.23 seconds |
| Started | Jul 30 08:47:51 PM PDT 24 |
| Finished | Jul 30 08:48:21 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-76014c29-376a-467f-bfc8-1be0f071a87c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805052073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_dela ys.805052073 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.3374465883 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 2142720869 ps |
| CPU time | 59.92 seconds |
| Started | Jul 30 08:47:54 PM PDT 24 |
| Finished | Jul 30 08:48:54 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-fd8f36c4-9419-4f86-865d-bfcf2f5845c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374465883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.3374465883 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.1089446066 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 48669137 ps |
| CPU time | 6.62 seconds |
| Started | Jul 30 08:47:51 PM PDT 24 |
| Finished | Jul 30 08:47:58 PM PDT 24 |
| Peak memory | 573876 kb |
| Host | smart-bfa86f30-7996-4294-bd34-5dcd26b039f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089446066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.1089446066 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.2487513198 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 7917217762 ps |
| CPU time | 78.57 seconds |
| Started | Jul 30 08:47:49 PM PDT 24 |
| Finished | Jul 30 08:49:08 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-3db2be95-f7e7-4b3e-b8fb-d10c79cab5b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487513198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.2487513198 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.1477590759 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 4919450985 ps |
| CPU time | 87.43 seconds |
| Started | Jul 30 08:47:50 PM PDT 24 |
| Finished | Jul 30 08:49:17 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-29a1f807-153c-4101-b368-aa8ca58990c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477590759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.1477590759 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.2087241692 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 46026487 ps |
| CPU time | 6.55 seconds |
| Started | Jul 30 08:47:50 PM PDT 24 |
| Finished | Jul 30 08:47:57 PM PDT 24 |
| Peak memory | 573848 kb |
| Host | smart-a83f2c2c-f57a-4edc-9265-e525078a563b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087241692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.2087241692 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.33104447 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 7855009281 ps |
| CPU time | 289.21 seconds |
| Started | Jul 30 08:47:58 PM PDT 24 |
| Finished | Jul 30 08:52:47 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-7dec950a-359b-4af3-bbc2-2ddb86f4d60a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33104447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.33104447 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.4147261915 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 14178571751 ps |
| CPU time | 550.34 seconds |
| Started | Jul 30 08:48:04 PM PDT 24 |
| Finished | Jul 30 08:57:15 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-221fe2b0-c3da-447f-a178-e7d300a7b40b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147261915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.4147261915 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.2402779501 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 18876960 ps |
| CPU time | 28.95 seconds |
| Started | Jul 30 08:48:02 PM PDT 24 |
| Finished | Jul 30 08:48:31 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-2b057549-bf1e-46fd-93b5-79ef1fc87da2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402779501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.2402779501 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.3392925054 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 18310087 ps |
| CPU time | 33.91 seconds |
| Started | Jul 30 08:48:03 PM PDT 24 |
| Finished | Jul 30 08:48:37 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-05f408f4-bd2d-4f66-a6b4-f697ed315865 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392925054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.3392925054 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.2462957579 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 45921478 ps |
| CPU time | 8.24 seconds |
| Started | Jul 30 08:47:56 PM PDT 24 |
| Finished | Jul 30 08:48:04 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-9b68eabb-8b98-4516-a982-5846f49e2c5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462957579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.2462957579 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.2099897112 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 893767826 ps |
| CPU time | 82.05 seconds |
| Started | Jul 30 08:48:05 PM PDT 24 |
| Finished | Jul 30 08:49:27 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-a684d1ed-aa52-40c5-a183-a750916ff6c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099897112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .2099897112 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.1085484445 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 774180994 ps |
| CPU time | 31.85 seconds |
| Started | Jul 30 08:48:14 PM PDT 24 |
| Finished | Jul 30 08:48:46 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-e9d98009-324c-4823-bcdd-f190b5775ede |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085484445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.1085484445 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.2944010804 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 2047413537 ps |
| CPU time | 66.3 seconds |
| Started | Jul 30 08:48:15 PM PDT 24 |
| Finished | Jul 30 08:49:21 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-23bea597-441a-42f1-aee5-d2fdc6ccace7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944010804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.2944010804 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.1763781187 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 2353854614 ps |
| CPU time | 86.3 seconds |
| Started | Jul 30 08:48:05 PM PDT 24 |
| Finished | Jul 30 08:49:31 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-8b020b58-e392-4c55-a7ef-565558ae7826 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763781187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.1763781187 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.409686047 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 9225050818 ps |
| CPU time | 97.66 seconds |
| Started | Jul 30 08:48:06 PM PDT 24 |
| Finished | Jul 30 08:49:44 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-18205eba-c2b7-4b2b-ba7c-9938697bcba6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409686047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.409686047 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.2527162133 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 3588916742 ps |
| CPU time | 63.75 seconds |
| Started | Jul 30 08:48:07 PM PDT 24 |
| Finished | Jul 30 08:49:11 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-c6cda99c-f91d-4ab8-9cbd-afa981c1d8c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527162133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.2527162133 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.2936437935 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 466455092 ps |
| CPU time | 53.79 seconds |
| Started | Jul 30 08:48:07 PM PDT 24 |
| Finished | Jul 30 08:49:01 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-721b3042-a3f2-45a2-9501-da9836d11f07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936437935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.2936437935 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.3312545750 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 1765606052 ps |
| CPU time | 58.44 seconds |
| Started | Jul 30 08:48:05 PM PDT 24 |
| Finished | Jul 30 08:49:03 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-7fd62683-6b72-4114-8ff6-5ec17ba51999 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312545750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.3312545750 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.1685685678 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 53565166 ps |
| CPU time | 7.24 seconds |
| Started | Jul 30 08:48:00 PM PDT 24 |
| Finished | Jul 30 08:48:07 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-e568e9bd-4f56-4ed3-95b4-b1d4e369e4e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685685678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.1685685678 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.3702460659 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 5092730518 ps |
| CPU time | 54.43 seconds |
| Started | Jul 30 08:48:01 PM PDT 24 |
| Finished | Jul 30 08:48:56 PM PDT 24 |
| Peak memory | 573968 kb |
| Host | smart-6b8df617-6948-4b61-ac56-59a3c8daf52b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702460659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.3702460659 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.1347388104 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 7084416374 ps |
| CPU time | 119.44 seconds |
| Started | Jul 30 08:48:03 PM PDT 24 |
| Finished | Jul 30 08:50:03 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-710d8c4b-ab5f-4036-b175-e78559061403 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347388104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.1347388104 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2393242308 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 53747424 ps |
| CPU time | 7.77 seconds |
| Started | Jul 30 08:48:00 PM PDT 24 |
| Finished | Jul 30 08:48:08 PM PDT 24 |
| Peak memory | 573808 kb |
| Host | smart-9344dc3f-16f8-4b6d-a55d-ced055c83ef8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393242308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay s.2393242308 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.3589064724 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 752597510 ps |
| CPU time | 37.22 seconds |
| Started | Jul 30 08:48:14 PM PDT 24 |
| Finished | Jul 30 08:48:52 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-9ae23f69-a9ff-40c4-949a-d57459ca05d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589064724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.3589064724 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1508270716 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 96542968 ps |
| CPU time | 55.22 seconds |
| Started | Jul 30 08:48:10 PM PDT 24 |
| Finished | Jul 30 08:49:05 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-d293d4d6-53c6-4a7f-ab53-d843b8e9a2b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508270716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.1508270716 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.4203891479 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 43276242 ps |
| CPU time | 18.19 seconds |
| Started | Jul 30 08:48:12 PM PDT 24 |
| Finished | Jul 30 08:48:30 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-2ce37ec9-f840-48e1-bc79-1fbae6bf6a9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203891479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.4203891479 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.2284341209 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 40998517 ps |
| CPU time | 8 seconds |
| Started | Jul 30 08:48:10 PM PDT 24 |
| Finished | Jul 30 08:48:18 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-ee259408-68f1-4a1a-b333-71e54eb10b51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284341209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.2284341209 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.3537372303 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 1189223077 ps |
| CPU time | 45.02 seconds |
| Started | Jul 30 08:48:13 PM PDT 24 |
| Finished | Jul 30 08:48:58 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-14232e12-2ed5-4435-baeb-44be94dbec4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537372303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .3537372303 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.341330887 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 86212801768 ps |
| CPU time | 1435 seconds |
| Started | Jul 30 08:48:13 PM PDT 24 |
| Finished | Jul 30 09:12:08 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-7346c640-f75e-43d2-8a43-0bd18571909d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341330887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_d evice_slow_rsp.341330887 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.2700084976 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 262378693 ps |
| CPU time | 30.68 seconds |
| Started | Jul 30 08:48:16 PM PDT 24 |
| Finished | Jul 30 08:48:47 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-9550fee7-9829-4a4f-ba51-5c2a87e712e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700084976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.2700084976 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.12127375 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 1805762886 ps |
| CPU time | 58.08 seconds |
| Started | Jul 30 08:48:17 PM PDT 24 |
| Finished | Jul 30 08:49:16 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-845cd2e5-33b1-42ae-bc0e-a4953489bd8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12127375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.12127375 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.851429639 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 2038898044 ps |
| CPU time | 80.99 seconds |
| Started | Jul 30 08:48:12 PM PDT 24 |
| Finished | Jul 30 08:49:33 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-e25e478b-ee91-4916-a633-5cafe46c97e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851429639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.851429639 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.300092354 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 47678832917 ps |
| CPU time | 511.28 seconds |
| Started | Jul 30 08:48:16 PM PDT 24 |
| Finished | Jul 30 08:56:47 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-8b9b6c80-5c74-4dcb-8cca-629ceed6ebb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300092354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.300092354 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.3981765277 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 21633068283 ps |
| CPU time | 405.45 seconds |
| Started | Jul 30 08:48:15 PM PDT 24 |
| Finished | Jul 30 08:55:00 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-5a40a220-0636-425b-bb1a-c12fa0be11b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981765277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.3981765277 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.1893516847 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 38492575 ps |
| CPU time | 6.36 seconds |
| Started | Jul 30 08:48:12 PM PDT 24 |
| Finished | Jul 30 08:48:19 PM PDT 24 |
| Peak memory | 573864 kb |
| Host | smart-ba7b0c50-2586-424d-bcd6-cddea61b307b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893516847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.1893516847 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.734840420 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 2542166918 ps |
| CPU time | 81.7 seconds |
| Started | Jul 30 08:48:20 PM PDT 24 |
| Finished | Jul 30 08:49:42 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-af90d217-6c00-43fe-937d-a1adf2f9c1ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734840420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.734840420 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.2621532465 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 212064617 ps |
| CPU time | 9.58 seconds |
| Started | Jul 30 08:48:09 PM PDT 24 |
| Finished | Jul 30 08:48:19 PM PDT 24 |
| Peak memory | 573832 kb |
| Host | smart-a5a657a7-38c7-4ca4-8e92-5b08c5cf398c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621532465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.2621532465 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.2572256669 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 7878870536 ps |
| CPU time | 82.25 seconds |
| Started | Jul 30 08:48:11 PM PDT 24 |
| Finished | Jul 30 08:49:33 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-d3460d6f-2979-4d6f-b976-096a403fca19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572256669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.2572256669 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.1703004122 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 5414042783 ps |
| CPU time | 88.53 seconds |
| Started | Jul 30 08:48:13 PM PDT 24 |
| Finished | Jul 30 08:49:42 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-1c6f2d5e-d5bf-424f-abd2-d72e758380d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703004122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.1703004122 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.1281645194 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 46829477 ps |
| CPU time | 6.49 seconds |
| Started | Jul 30 08:48:14 PM PDT 24 |
| Finished | Jul 30 08:48:20 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-abc59b97-5c1c-49b8-9791-8eb40256904b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281645194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.1281645194 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.3350912059 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 3179368755 ps |
| CPU time | 251.96 seconds |
| Started | Jul 30 08:48:15 PM PDT 24 |
| Finished | Jul 30 08:52:27 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-12215474-9f62-4390-ab39-e1dea8c2677e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350912059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.3350912059 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.3272155030 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 907015797 ps |
| CPU time | 81.35 seconds |
| Started | Jul 30 08:48:18 PM PDT 24 |
| Finished | Jul 30 08:49:39 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-1c2049b5-b5f7-471f-aec2-287d15e2cefd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272155030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.3272155030 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.1196007072 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 7572057438 ps |
| CPU time | 339.45 seconds |
| Started | Jul 30 08:48:15 PM PDT 24 |
| Finished | Jul 30 08:53:54 PM PDT 24 |
| Peak memory | 576864 kb |
| Host | smart-e3c0d5fd-a8a5-4c9a-b628-2e2d8aa56808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196007072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.1196007072 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.1761510477 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 14061609643 ps |
| CPU time | 605.05 seconds |
| Started | Jul 30 08:48:17 PM PDT 24 |
| Finished | Jul 30 08:58:22 PM PDT 24 |
| Peak memory | 576848 kb |
| Host | smart-aaab8256-0b8a-40b6-8397-0cef2d8b3cba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761510477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al l_with_reset_error.1761510477 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.2228008207 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 876867317 ps |
| CPU time | 36.37 seconds |
| Started | Jul 30 08:48:20 PM PDT 24 |
| Finished | Jul 30 08:48:57 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-ccd34294-f469-4b64-b7b8-e91c25504b5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228008207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.2228008207 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.3532203350 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 1105850237 ps |
| CPU time | 71.21 seconds |
| Started | Jul 30 08:48:28 PM PDT 24 |
| Finished | Jul 30 08:49:39 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-d51e1fcd-941e-4a63-9181-cd803f5a06d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532203350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .3532203350 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.2196894538 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 90013229660 ps |
| CPU time | 1495.84 seconds |
| Started | Jul 30 08:48:21 PM PDT 24 |
| Finished | Jul 30 09:13:17 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-b9c47a32-c1ab-461e-9a0a-2b4bb428f544 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196894538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.2196894538 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.2787393410 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 186824206 ps |
| CPU time | 19.99 seconds |
| Started | Jul 30 08:48:25 PM PDT 24 |
| Finished | Jul 30 08:48:45 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-02e062cc-766a-4730-baf0-c1d689bed890 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787393410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.2787393410 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.710565903 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 383271950 ps |
| CPU time | 14.25 seconds |
| Started | Jul 30 08:48:27 PM PDT 24 |
| Finished | Jul 30 08:48:41 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-98cecbae-a67a-489b-8204-4bc49d1d80ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710565903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.710565903 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.3045328431 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 1195502215 ps |
| CPU time | 46.76 seconds |
| Started | Jul 30 08:48:21 PM PDT 24 |
| Finished | Jul 30 08:49:08 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-b2cb8362-b2e5-4dc6-8ac2-091c597dd5a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045328431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.3045328431 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.2677047183 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 89043752732 ps |
| CPU time | 962.21 seconds |
| Started | Jul 30 08:48:25 PM PDT 24 |
| Finished | Jul 30 09:04:27 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-92df96f6-3730-49d7-8a8b-5a674c8069e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677047183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.2677047183 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.992725206 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 45115201376 ps |
| CPU time | 747.44 seconds |
| Started | Jul 30 08:48:23 PM PDT 24 |
| Finished | Jul 30 09:00:50 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-6eada067-0d14-4dc7-93a5-8dcc469e3a71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992725206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.992725206 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.3389433614 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 219166963 ps |
| CPU time | 24 seconds |
| Started | Jul 30 08:48:24 PM PDT 24 |
| Finished | Jul 30 08:48:48 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-74bed25a-b8b4-45ba-94e1-b8701f8bc293 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389433614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.3389433614 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.1514798763 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 328515524 ps |
| CPU time | 25.17 seconds |
| Started | Jul 30 08:48:24 PM PDT 24 |
| Finished | Jul 30 08:48:50 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-068a456b-7b57-4a86-9dbf-ee312bec9238 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514798763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.1514798763 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.1520712329 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 190030557 ps |
| CPU time | 8.51 seconds |
| Started | Jul 30 08:48:18 PM PDT 24 |
| Finished | Jul 30 08:48:26 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-d84a9eda-704d-4387-968b-e056366907a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520712329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.1520712329 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.4145918140 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 5412872572 ps |
| CPU time | 61.23 seconds |
| Started | Jul 30 08:48:20 PM PDT 24 |
| Finished | Jul 30 08:49:22 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-edcee5e9-72de-4530-8a51-6c53cfa821cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145918140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.4145918140 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.1983209115 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 6474150030 ps |
| CPU time | 110.85 seconds |
| Started | Jul 30 08:48:24 PM PDT 24 |
| Finished | Jul 30 08:50:15 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-2249e520-6335-4d53-ba52-5759eb949095 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983209115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.1983209115 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.1901033119 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 38949150 ps |
| CPU time | 6.44 seconds |
| Started | Jul 30 08:48:20 PM PDT 24 |
| Finished | Jul 30 08:48:27 PM PDT 24 |
| Peak memory | 573848 kb |
| Host | smart-301457aa-4496-48e2-a056-c5a71c0a9255 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901033119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.1901033119 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.1008057750 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 10764849151 ps |
| CPU time | 387.11 seconds |
| Started | Jul 30 08:48:24 PM PDT 24 |
| Finished | Jul 30 08:54:51 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-01038ff7-12e4-4c87-bf0a-0f7d6bd798e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008057750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.1008057750 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.2139983317 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 4917236758 ps |
| CPU time | 179.72 seconds |
| Started | Jul 30 08:48:29 PM PDT 24 |
| Finished | Jul 30 08:51:29 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-bd53d0d8-4b17-421d-8093-4d59d3be0480 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139983317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.2139983317 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.4289576203 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 1129562819 ps |
| CPU time | 191.76 seconds |
| Started | Jul 30 08:48:27 PM PDT 24 |
| Finished | Jul 30 08:51:39 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-9cced303-24c6-46a1-92ff-18133bbbd2bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289576203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.4289576203 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.709673311 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 6101368672 ps |
| CPU time | 414.66 seconds |
| Started | Jul 30 08:48:28 PM PDT 24 |
| Finished | Jul 30 08:55:22 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-37c33cc1-4bf7-4380-92e6-38622a024484 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709673311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_reset_error.709673311 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.2062000506 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 1033233259 ps |
| CPU time | 46.39 seconds |
| Started | Jul 30 08:48:25 PM PDT 24 |
| Finished | Jul 30 08:49:12 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-4e272933-4a1f-4c41-985c-8dd511834f17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062000506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.2062000506 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.3466961489 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 2834804959 ps |
| CPU time | 132.41 seconds |
| Started | Jul 30 08:48:34 PM PDT 24 |
| Finished | Jul 30 08:50:47 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-7f1c3209-21c2-44ba-a79c-fc381bf14b6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466961489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .3466961489 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.3895633619 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 117722310073 ps |
| CPU time | 2006.77 seconds |
| Started | Jul 30 08:48:34 PM PDT 24 |
| Finished | Jul 30 09:22:01 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-5533121f-ec20-432d-a861-e0fbb246ff5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895633619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.3895633619 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1577127511 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 557661596 ps |
| CPU time | 25.34 seconds |
| Started | Jul 30 08:48:37 PM PDT 24 |
| Finished | Jul 30 08:49:02 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-fd4aad35-733d-43aa-8ce1-395ae8aa1efd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577127511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.1577127511 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.3440787615 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 1808135865 ps |
| CPU time | 64.58 seconds |
| Started | Jul 30 08:48:38 PM PDT 24 |
| Finished | Jul 30 08:49:42 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-caece2c9-de13-44f9-98b6-3e45b9969c97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440787615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.3440787615 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.3212727266 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 2465893345 ps |
| CPU time | 90.12 seconds |
| Started | Jul 30 08:48:30 PM PDT 24 |
| Finished | Jul 30 08:50:00 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-a88c0525-83c2-4cfa-9f3b-2900c1afe15f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212727266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.3212727266 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.1938479354 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 40265767908 ps |
| CPU time | 413.55 seconds |
| Started | Jul 30 08:48:34 PM PDT 24 |
| Finished | Jul 30 08:55:27 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-e4e33cca-7c05-4d43-a7ef-8b6132838797 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938479354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.1938479354 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.948514772 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 2709811524 ps |
| CPU time | 47.46 seconds |
| Started | Jul 30 08:48:34 PM PDT 24 |
| Finished | Jul 30 08:49:22 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-7745464d-9ce3-4842-8c33-373c6113176e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948514772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.948514772 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.2301233390 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 28838842 ps |
| CPU time | 5.55 seconds |
| Started | Jul 30 08:48:30 PM PDT 24 |
| Finished | Jul 30 08:48:35 PM PDT 24 |
| Peak memory | 573864 kb |
| Host | smart-51add97e-aaa0-49ac-b1dc-daadc51152a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301233390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.2301233390 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.3175420713 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 42947433 ps |
| CPU time | 6.33 seconds |
| Started | Jul 30 08:48:30 PM PDT 24 |
| Finished | Jul 30 08:48:36 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-6116046c-7aec-49e1-8a1d-52f6dab5a035 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175420713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.3175420713 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.4279606434 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 7678796601 ps |
| CPU time | 79.61 seconds |
| Started | Jul 30 08:48:30 PM PDT 24 |
| Finished | Jul 30 08:49:50 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-132f246b-05a2-49ff-bf11-0022848c5d23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279606434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.4279606434 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.2373173601 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 5634034130 ps |
| CPU time | 95.4 seconds |
| Started | Jul 30 08:48:31 PM PDT 24 |
| Finished | Jul 30 08:50:07 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-f9602fa3-6e76-43f5-a075-f8d2075c4411 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373173601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.2373173601 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.2416915175 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 51945318 ps |
| CPU time | 6.82 seconds |
| Started | Jul 30 08:48:31 PM PDT 24 |
| Finished | Jul 30 08:48:38 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-17ebbadc-90b4-4f99-b0f2-ac510977d53e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416915175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.2416915175 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.581965027 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 727863784 ps |
| CPU time | 58.57 seconds |
| Started | Jul 30 08:48:39 PM PDT 24 |
| Finished | Jul 30 08:49:38 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-af07e28f-0e45-4a64-83bf-559cc2001338 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581965027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.581965027 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.141840097 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 3017692827 ps |
| CPU time | 208.07 seconds |
| Started | Jul 30 08:48:41 PM PDT 24 |
| Finished | Jul 30 08:52:09 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-ce8d1738-7b5d-403a-941d-58f91f656f18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141840097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.141840097 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.308002389 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 1559517086 ps |
| CPU time | 121.6 seconds |
| Started | Jul 30 08:48:37 PM PDT 24 |
| Finished | Jul 30 08:50:39 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-5ebb5c97-8815-4892-9969-f8ec7f50e6c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308002389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_ with_rand_reset.308002389 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.4088532231 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 515573061 ps |
| CPU time | 136.2 seconds |
| Started | Jul 30 08:48:39 PM PDT 24 |
| Finished | Jul 30 08:50:56 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-c1eda0ae-3e8f-4ace-a8f7-1696df38dc79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088532231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al l_with_reset_error.4088532231 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.302646358 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 24272521 ps |
| CPU time | 5.49 seconds |
| Started | Jul 30 08:48:41 PM PDT 24 |
| Finished | Jul 30 08:48:46 PM PDT 24 |
| Peak memory | 573884 kb |
| Host | smart-5c324cfc-3ac7-44d5-9dd0-c7a72f7c114e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302646358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.302646358 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.492166063 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 1873896791 ps |
| CPU time | 71.96 seconds |
| Started | Jul 30 08:48:46 PM PDT 24 |
| Finished | Jul 30 08:49:58 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-101821b8-87f1-4bf6-8ee6-bd18c8db69c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492166063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device. 492166063 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.2205332642 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 137101846571 ps |
| CPU time | 2278.97 seconds |
| Started | Jul 30 08:48:47 PM PDT 24 |
| Finished | Jul 30 09:26:46 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-d1c93ecf-d49e-49d0-b947-0a9d229ad3b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205332642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.2205332642 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.2832295131 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 207272205 ps |
| CPU time | 21.95 seconds |
| Started | Jul 30 08:48:49 PM PDT 24 |
| Finished | Jul 30 08:49:11 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-de76a310-dcda-4d01-921f-3eca4162afc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832295131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.2832295131 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.2055007036 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 2505277970 ps |
| CPU time | 95.07 seconds |
| Started | Jul 30 08:48:49 PM PDT 24 |
| Finished | Jul 30 08:50:25 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-d2156ae0-53c9-4ad1-b35c-7c9b8305b8d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055007036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.2055007036 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.3988335553 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 967246104 ps |
| CPU time | 32.95 seconds |
| Started | Jul 30 08:48:41 PM PDT 24 |
| Finished | Jul 30 08:49:14 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-129a2739-2d95-41fb-ab92-dc894c51b69e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988335553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.3988335553 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.2258637311 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 60738162392 ps |
| CPU time | 651.47 seconds |
| Started | Jul 30 08:48:44 PM PDT 24 |
| Finished | Jul 30 08:59:36 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-04ec7c5c-0080-454d-bae9-42cc90b43a19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258637311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.2258637311 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.270349414 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 51795922770 ps |
| CPU time | 917.05 seconds |
| Started | Jul 30 08:48:44 PM PDT 24 |
| Finished | Jul 30 09:04:01 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-9bd0b67e-b113-4188-b2d3-1fa45d21302b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270349414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.270349414 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.2053381367 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 422658544 ps |
| CPU time | 36.95 seconds |
| Started | Jul 30 08:48:44 PM PDT 24 |
| Finished | Jul 30 08:49:21 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-9c23e027-27ed-4edc-bbf8-68b482f4d21c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053381367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.2053381367 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.2616358599 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 93171707 ps |
| CPU time | 10.35 seconds |
| Started | Jul 30 08:48:49 PM PDT 24 |
| Finished | Jul 30 08:48:59 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-7173902d-14ca-48dd-af10-2401b22e9c83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616358599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.2616358599 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.2689993704 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 50774983 ps |
| CPU time | 7.02 seconds |
| Started | Jul 30 08:48:36 PM PDT 24 |
| Finished | Jul 30 08:48:44 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-b1334e7f-1053-4bc0-b988-0b10f4e1e755 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689993704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.2689993704 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.2787643709 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 8013652316 ps |
| CPU time | 87.26 seconds |
| Started | Jul 30 08:48:43 PM PDT 24 |
| Finished | Jul 30 08:50:10 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-1b59fb30-22a3-48fd-8a4d-6dc87dedbd0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787643709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.2787643709 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.3763877503 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 4224426812 ps |
| CPU time | 77.47 seconds |
| Started | Jul 30 08:48:44 PM PDT 24 |
| Finished | Jul 30 08:50:01 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-029a8aaa-51d1-4ea8-bfda-b7950cd578aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763877503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.3763877503 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.2506386182 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 44348984 ps |
| CPU time | 6.86 seconds |
| Started | Jul 30 08:48:39 PM PDT 24 |
| Finished | Jul 30 08:48:46 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-a20aa592-7711-48b5-a251-560be42bf7a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506386182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.2506386182 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.1728673922 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 8531733083 ps |
| CPU time | 296.71 seconds |
| Started | Jul 30 08:48:49 PM PDT 24 |
| Finished | Jul 30 08:53:46 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-0985102a-4209-463d-8ca9-315ae1480f92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728673922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.1728673922 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.2104409465 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 2114703562 ps |
| CPU time | 157.94 seconds |
| Started | Jul 30 08:48:50 PM PDT 24 |
| Finished | Jul 30 08:51:28 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-ed9778bb-1596-497c-ac78-4fac27b194ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104409465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.2104409465 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.3778053205 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 128653881 ps |
| CPU time | 59.01 seconds |
| Started | Jul 30 08:48:50 PM PDT 24 |
| Finished | Jul 30 08:49:50 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-47970aa5-ea94-4f0c-b25b-aceec191e9e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778053205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.3778053205 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.3135548816 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 401631957 ps |
| CPU time | 161.09 seconds |
| Started | Jul 30 08:48:50 PM PDT 24 |
| Finished | Jul 30 08:51:31 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-ef69364a-4453-46af-917d-35a02f81c3ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135548816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.3135548816 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.2333490500 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 972758999 ps |
| CPU time | 45.15 seconds |
| Started | Jul 30 08:48:52 PM PDT 24 |
| Finished | Jul 30 08:49:38 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-81bb8418-c6ce-4f24-ac3c-6fd5e382a854 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333490500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.2333490500 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.3140043104 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 87231469 ps |
| CPU time | 13.29 seconds |
| Started | Jul 30 08:48:58 PM PDT 24 |
| Finished | Jul 30 08:49:11 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-f658209f-29ca-4485-8faa-399e6a685044 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140043104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .3140043104 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.3767276521 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 146401225829 ps |
| CPU time | 2483.39 seconds |
| Started | Jul 30 08:49:03 PM PDT 24 |
| Finished | Jul 30 09:30:27 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-8dda1ae6-0f3c-45a3-b906-1ccba107bb41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767276521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.3767276521 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.3834636001 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 936208970 ps |
| CPU time | 35.8 seconds |
| Started | Jul 30 08:48:57 PM PDT 24 |
| Finished | Jul 30 08:49:33 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-0b597de9-9779-4538-a64d-3f799214b2a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834636001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add r.3834636001 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.265683691 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 1406906495 ps |
| CPU time | 45.61 seconds |
| Started | Jul 30 08:48:58 PM PDT 24 |
| Finished | Jul 30 08:49:44 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-fa9e9373-9378-46cd-9f08-7643629da624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265683691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.265683691 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.2627840707 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 911710988 ps |
| CPU time | 36.76 seconds |
| Started | Jul 30 08:48:53 PM PDT 24 |
| Finished | Jul 30 08:49:30 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-f80829bc-c70f-4e7e-b5a5-4ec99db46944 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627840707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.2627840707 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.2212348440 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 64940498928 ps |
| CPU time | 677.29 seconds |
| Started | Jul 30 08:48:55 PM PDT 24 |
| Finished | Jul 30 09:00:12 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-2813f4a3-13d3-4dd3-a5f2-17b04d1b6eef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212348440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.2212348440 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.781266508 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 59980660091 ps |
| CPU time | 1008.17 seconds |
| Started | Jul 30 08:48:55 PM PDT 24 |
| Finished | Jul 30 09:05:43 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-23ed2fcc-9b59-4417-b978-9ceddd1c1a8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781266508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.781266508 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.4126658882 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 618742505 ps |
| CPU time | 58.99 seconds |
| Started | Jul 30 08:48:55 PM PDT 24 |
| Finished | Jul 30 08:49:54 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-21da7a2f-a277-4782-b8e3-a1e12e8bcd5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126658882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.4126658882 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.1768191014 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 1788716656 ps |
| CPU time | 53.16 seconds |
| Started | Jul 30 08:48:57 PM PDT 24 |
| Finished | Jul 30 08:49:50 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-ad615ff4-048e-49ba-a9ad-ea6e6670c031 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768191014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.1768191014 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.1012517525 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 36207356 ps |
| CPU time | 6.29 seconds |
| Started | Jul 30 08:48:57 PM PDT 24 |
| Finished | Jul 30 08:49:03 PM PDT 24 |
| Peak memory | 573896 kb |
| Host | smart-b9045785-af47-4884-9c61-fd86ae459cc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012517525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.1012517525 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.1308301850 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 9061575883 ps |
| CPU time | 96.11 seconds |
| Started | Jul 30 08:48:53 PM PDT 24 |
| Finished | Jul 30 08:50:30 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-1b9db3af-4e62-4243-a9a1-61fddb742e3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308301850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.1308301850 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.1901874761 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 4636605819 ps |
| CPU time | 80.79 seconds |
| Started | Jul 30 08:48:54 PM PDT 24 |
| Finished | Jul 30 08:50:15 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-e035de6e-d2d9-4786-8f78-e2db8f815850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901874761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.1901874761 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.101999854 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 45349107 ps |
| CPU time | 6.59 seconds |
| Started | Jul 30 08:48:55 PM PDT 24 |
| Finished | Jul 30 08:49:01 PM PDT 24 |
| Peak memory | 573852 kb |
| Host | smart-f8426118-e5e2-4d92-ab82-408c0d19bc73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101999854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delays .101999854 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.266255680 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 3222577677 ps |
| CPU time | 266.32 seconds |
| Started | Jul 30 08:49:03 PM PDT 24 |
| Finished | Jul 30 08:53:30 PM PDT 24 |
| Peak memory | 576856 kb |
| Host | smart-973fde48-d8db-4a65-ab57-e51f694b7959 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266255680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.266255680 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.872576501 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 2305436755 ps |
| CPU time | 182.84 seconds |
| Started | Jul 30 08:49:01 PM PDT 24 |
| Finished | Jul 30 08:52:04 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-2f3086f0-82a5-4b43-8b14-ec7b307c2abe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872576501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.872576501 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.1342145778 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 4303240892 ps |
| CPU time | 687.45 seconds |
| Started | Jul 30 08:49:01 PM PDT 24 |
| Finished | Jul 30 09:00:29 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-cf18afa3-8afc-4edf-ba3e-eb4a3d90df76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342145778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.1342145778 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.2826537461 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 5480498384 ps |
| CPU time | 275.07 seconds |
| Started | Jul 30 08:49:03 PM PDT 24 |
| Finished | Jul 30 08:53:38 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-fde5f030-3dee-4cc5-a8f4-62edadca5139 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826537461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_al l_with_reset_error.2826537461 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.4253772570 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 56858961 ps |
| CPU time | 9.99 seconds |
| Started | Jul 30 08:49:03 PM PDT 24 |
| Finished | Jul 30 08:49:13 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-778cfc42-847f-4c68-a691-15b20ca6f97a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253772570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.4253772570 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.1606897391 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 925064275 ps |
| CPU time | 91.58 seconds |
| Started | Jul 30 08:49:04 PM PDT 24 |
| Finished | Jul 30 08:50:36 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-c039e052-7959-4e34-82fc-37be3696ae9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606897391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device .1606897391 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.1002296786 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 182125697840 ps |
| CPU time | 2980.08 seconds |
| Started | Jul 30 08:49:08 PM PDT 24 |
| Finished | Jul 30 09:38:48 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-4a2911fa-11db-4c2b-82cd-5df67b15fb84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002296786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.1002296786 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1512108291 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 1113158476 ps |
| CPU time | 45.83 seconds |
| Started | Jul 30 08:49:12 PM PDT 24 |
| Finished | Jul 30 08:49:58 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-1dea1b8a-a6cf-4b73-a64f-adf57be96a7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512108291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.1512108291 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.1631475339 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 2395134804 ps |
| CPU time | 75.88 seconds |
| Started | Jul 30 08:49:13 PM PDT 24 |
| Finished | Jul 30 08:50:29 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-1392c989-18a0-43d5-a096-d2d22ca5e5ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631475339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.1631475339 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.1632580812 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 23855027 ps |
| CPU time | 5.85 seconds |
| Started | Jul 30 08:49:05 PM PDT 24 |
| Finished | Jul 30 08:49:11 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-c28cad1c-ca6b-41ea-946d-9289c74a4586 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632580812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.1632580812 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.3211875520 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 19518975098 ps |
| CPU time | 209.69 seconds |
| Started | Jul 30 08:49:06 PM PDT 24 |
| Finished | Jul 30 08:52:36 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-f0008f57-3bb4-4d02-99a1-c9c70e2ecd22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211875520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.3211875520 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.198283403 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 50726734333 ps |
| CPU time | 855.74 seconds |
| Started | Jul 30 08:49:06 PM PDT 24 |
| Finished | Jul 30 09:03:22 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-e740596a-bc71-4c83-ba54-7ea016f8b1b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198283403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.198283403 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.2746312609 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 486652314 ps |
| CPU time | 45.87 seconds |
| Started | Jul 30 08:49:05 PM PDT 24 |
| Finished | Jul 30 08:49:51 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-e5864136-7033-428b-bae7-40992c7e3119 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746312609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.2746312609 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.1851598809 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 287029189 ps |
| CPU time | 10.87 seconds |
| Started | Jul 30 08:49:07 PM PDT 24 |
| Finished | Jul 30 08:49:18 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-9f49d351-5cc0-4d30-a585-fdf3d44a6872 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851598809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.1851598809 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.3818940391 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 38032681 ps |
| CPU time | 6.02 seconds |
| Started | Jul 30 08:49:02 PM PDT 24 |
| Finished | Jul 30 08:49:08 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-ca628436-cd98-4fea-a29e-9b32bfa0a5d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818940391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.3818940391 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.2888372069 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 8055902142 ps |
| CPU time | 83.3 seconds |
| Started | Jul 30 08:49:07 PM PDT 24 |
| Finished | Jul 30 08:50:31 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-8855601e-a57a-46bf-a7a4-285243414850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888372069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.2888372069 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.2379515767 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 4333678144 ps |
| CPU time | 74.59 seconds |
| Started | Jul 30 08:49:06 PM PDT 24 |
| Finished | Jul 30 08:50:20 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-826ca7d1-c48e-4390-bf17-8a21f09cf9dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379515767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.2379515767 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.3970719211 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 46273327 ps |
| CPU time | 6.72 seconds |
| Started | Jul 30 08:49:03 PM PDT 24 |
| Finished | Jul 30 08:49:10 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-8e6688f0-13e3-40e1-8a8a-d3887fbf9de2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970719211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.3970719211 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.1902686916 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 11184975244 ps |
| CPU time | 420.73 seconds |
| Started | Jul 30 08:49:13 PM PDT 24 |
| Finished | Jul 30 08:56:14 PM PDT 24 |
| Peak memory | 576856 kb |
| Host | smart-664d5356-5bcf-470e-8a83-2e919df9c176 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902686916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.1902686916 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.3891252560 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 10649153232 ps |
| CPU time | 377.36 seconds |
| Started | Jul 30 08:49:16 PM PDT 24 |
| Finished | Jul 30 08:55:34 PM PDT 24 |
| Peak memory | 576200 kb |
| Host | smart-fd437dd6-036f-4b80-84f5-62c30163746e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891252560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.3891252560 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.280858292 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 7921274088 ps |
| CPU time | 440.33 seconds |
| Started | Jul 30 08:49:13 PM PDT 24 |
| Finished | Jul 30 08:56:34 PM PDT 24 |
| Peak memory | 576860 kb |
| Host | smart-bdfbabbd-1290-4575-a2f1-45a236628626 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280858292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_ with_rand_reset.280858292 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.2712250271 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 6542468360 ps |
| CPU time | 311.75 seconds |
| Started | Jul 30 08:49:12 PM PDT 24 |
| Finished | Jul 30 08:54:24 PM PDT 24 |
| Peak memory | 576852 kb |
| Host | smart-85641427-9e46-4fd1-ab35-f0db03767802 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712250271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al l_with_reset_error.2712250271 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.699492407 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 211883283 ps |
| CPU time | 26.88 seconds |
| Started | Jul 30 08:49:14 PM PDT 24 |
| Finished | Jul 30 08:49:41 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-8207a920-24a4-4ab8-8778-2812fb682e61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699492407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.699492407 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.1292862262 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 10883215970 ps |
| CPU time | 1051.64 seconds |
| Started | Jul 30 07:45:24 PM PDT 24 |
| Finished | Jul 30 08:02:56 PM PDT 24 |
| Peak memory | 608048 kb |
| Host | smart-28340ec0-cefd-4d98-bb9c-dbf51bf71f91 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292862262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.1292862262 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.2491901346 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 13812059600 ps |
| CPU time | 1631.15 seconds |
| Started | Jul 30 07:45:20 PM PDT 24 |
| Finished | Jul 30 08:12:32 PM PDT 24 |
| Peak memory | 607880 kb |
| Host | smart-9fc5d3bf-cb3f-493b-a138-1d66aa9ab119 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491901346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.2 491901346 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.1219618163 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 3461793370 ps |
| CPU time | 260.08 seconds |
| Started | Jul 30 07:53:21 PM PDT 24 |
| Finished | Jul 30 07:57:41 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-2dfae9bf-5fa6-4661-bca3-f0d117d1ed9f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1219618163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.1219618163 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2132715442 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 3093997251 ps |
| CPU time | 266.83 seconds |
| Started | Jul 30 07:54:14 PM PDT 24 |
| Finished | Jul 30 07:58:41 PM PDT 24 |
| Peak memory | 608532 kb |
| Host | smart-afb5f7a9-ccc8-4000-ac41-43d913127c1d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132 715442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.2132715442 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.4038999783 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 2969008108 ps |
| CPU time | 239.38 seconds |
| Started | Jul 30 07:52:08 PM PDT 24 |
| Finished | Jul 30 07:56:07 PM PDT 24 |
| Peak memory | 608752 kb |
| Host | smart-8f7cc773-107c-4237-a693-4c58d6907db3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038999783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.4038999783 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.52409659 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 2893373860 ps |
| CPU time | 255.23 seconds |
| Started | Jul 30 07:51:22 PM PDT 24 |
| Finished | Jul 30 07:55:37 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-398595f6-b5cb-4496-ac3f-077bf6da8185 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52409659 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.52409659 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.167354099 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 2373033736 ps |
| CPU time | 291.86 seconds |
| Started | Jul 30 07:54:12 PM PDT 24 |
| Finished | Jul 30 07:59:05 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-1dc6e610-3980-476d-a2b1-51c27602add8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167354099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.167354099 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.3317773640 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 3180968090 ps |
| CPU time | 281.04 seconds |
| Started | Jul 30 07:54:12 PM PDT 24 |
| Finished | Jul 30 07:58:53 PM PDT 24 |
| Peak memory | 610488 kb |
| Host | smart-bf84fccd-2169-4076-b123-bfcbc6617d9d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317773640 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.3317773640 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.1332422226 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 3213029400 ps |
| CPU time | 364.87 seconds |
| Started | Jul 30 07:55:58 PM PDT 24 |
| Finished | Jul 30 08:02:03 PM PDT 24 |
| Peak memory | 609584 kb |
| Host | smart-9d46fb23-4490-4583-8ab3-5c4534d12ddc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332422226 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.1332422226 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3826644170 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 3195571176 ps |
| CPU time | 290.59 seconds |
| Started | Jul 30 07:51:15 PM PDT 24 |
| Finished | Jul 30 07:56:06 PM PDT 24 |
| Peak memory | 609464 kb |
| Host | smart-c8627153-3ecd-4cae-ba80-20b7ffc611ad |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3826644170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.3826644170 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1748982024 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 5001407042 ps |
| CPU time | 614.44 seconds |
| Started | Jul 30 07:53:20 PM PDT 24 |
| Finished | Jul 30 08:03:35 PM PDT 24 |
| Peak memory | 619392 kb |
| Host | smart-1f445f28-e672-489c-9a37-93aa9e4458f5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1748982024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.1748982024 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.275739318 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 11280587302 ps |
| CPU time | 2733.09 seconds |
| Started | Jul 30 07:54:25 PM PDT 24 |
| Finished | Jul 30 08:39:59 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-ef222024-2ed3-4da7-9b27-63250e30967e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=275739318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.275739318 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.4091471674 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 7430091238 ps |
| CPU time | 1611.18 seconds |
| Started | Jul 30 07:51:22 PM PDT 24 |
| Finished | Jul 30 08:18:14 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-ff7b1331-3026-4440-8e59-093e46710b1b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091471674 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.4091471674 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2862408413 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 3100923776 ps |
| CPU time | 448.8 seconds |
| Started | Jul 30 07:51:20 PM PDT 24 |
| Finished | Jul 30 07:58:49 PM PDT 24 |
| Peak memory | 618936 kb |
| Host | smart-ff806bd5-bb07-4f97-ba8c-89e637217b87 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862408413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.2862408413 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1629757036 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 11313231884 ps |
| CPU time | 1257.09 seconds |
| Started | Jul 30 07:51:38 PM PDT 24 |
| Finished | Jul 30 08:12:36 PM PDT 24 |
| Peak memory | 610884 kb |
| Host | smart-45474468-75b3-4606-a9fa-fb15df559e46 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629757036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.1629757036 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2920151503 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 4683753344 ps |
| CPU time | 441.33 seconds |
| Started | Jul 30 07:53:51 PM PDT 24 |
| Finished | Jul 30 08:01:13 PM PDT 24 |
| Peak memory | 609804 kb |
| Host | smart-ebcb2e59-d883-4c0c-97c7-5ecc346398df |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2920151503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.2920151503 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.786742926 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 255381948386 ps |
| CPU time | 13567.4 seconds |
| Started | Jul 30 07:54:31 PM PDT 24 |
| Finished | Jul 30 11:40:40 PM PDT 24 |
| Peak memory | 610768 kb |
| Host | smart-b56e67b7-d779-4668-a3b3-ffb22f97efcc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786742926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.786742926 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.150239323 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 2579769590 ps |
| CPU time | 411.12 seconds |
| Started | Jul 30 07:55:37 PM PDT 24 |
| Finished | Jul 30 08:02:28 PM PDT 24 |
| Peak memory | 609884 kb |
| Host | smart-6eb78274-7a38-4082-82d1-7889987dc8c7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150239323 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_alert_test.150239323 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.3490130085 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 3948547696 ps |
| CPU time | 383.02 seconds |
| Started | Jul 30 07:52:21 PM PDT 24 |
| Finished | Jul 30 07:58:44 PM PDT 24 |
| Peak memory | 609652 kb |
| Host | smart-499c3fb4-fc72-4f23-bc5c-4ce64d8d3fad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490130085 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.3490130085 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2685865579 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 6067092872 ps |
| CPU time | 388.92 seconds |
| Started | Jul 30 07:54:26 PM PDT 24 |
| Finished | Jul 30 08:00:55 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-29184673-0746-4d10-b978-bddae2eb1d37 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2685865579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2685865579 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.4085433788 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 3386123048 ps |
| CPU time | 398.7 seconds |
| Started | Jul 30 07:56:51 PM PDT 24 |
| Finished | Jul 30 08:03:30 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-98faf638-1edb-49ed-b597-74f513e3777a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085433788 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.4085433788 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3636014679 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 8649289836 ps |
| CPU time | 957.24 seconds |
| Started | Jul 30 07:51:13 PM PDT 24 |
| Finished | Jul 30 08:07:10 PM PDT 24 |
| Peak memory | 609424 kb |
| Host | smart-7de27c79-2ec5-4563-bd76-9aa681eafa82 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3636014679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.3636014679 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3756743896 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 5675038358 ps |
| CPU time | 559.18 seconds |
| Started | Jul 30 07:54:04 PM PDT 24 |
| Finished | Jul 30 08:03:23 PM PDT 24 |
| Peak memory | 610708 kb |
| Host | smart-ce73ac91-1011-4cb0-92bd-ea6535b0681d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3756743896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.3756743896 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.1435495975 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 7565538632 ps |
| CPU time | 1164.99 seconds |
| Started | Jul 30 07:54:45 PM PDT 24 |
| Finished | Jul 30 08:14:11 PM PDT 24 |
| Peak memory | 617060 kb |
| Host | smart-9b08e70b-e6ec-4462-a68d-2acb266350c6 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435495975 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.1435495975 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3500553297 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 9248564005 ps |
| CPU time | 1271.92 seconds |
| Started | Jul 30 07:55:59 PM PDT 24 |
| Finished | Jul 30 08:17:11 PM PDT 24 |
| Peak memory | 621296 kb |
| Host | smart-bdae704c-11f3-4a06-87ed-12962ac7e1cb |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3500553297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.3500553297 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3464420259 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 3535773660 ps |
| CPU time | 675.21 seconds |
| Started | Jul 30 07:52:55 PM PDT 24 |
| Finished | Jul 30 08:04:11 PM PDT 24 |
| Peak memory | 611960 kb |
| Host | smart-c69c7bee-a595-466c-89ba-893e711d000a |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464420259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3464420259 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3171662256 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 3750025020 ps |
| CPU time | 749.34 seconds |
| Started | Jul 30 07:54:27 PM PDT 24 |
| Finished | Jul 30 08:06:57 PM PDT 24 |
| Peak memory | 613040 kb |
| Host | smart-4afa1a22-df13-4442-930e-1978eb739dea |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171662256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3171662256 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1091670647 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 4809091408 ps |
| CPU time | 750.41 seconds |
| Started | Jul 30 07:56:16 PM PDT 24 |
| Finished | Jul 30 08:08:47 PM PDT 24 |
| Peak memory | 612912 kb |
| Host | smart-f72c00b3-1fb8-4d58-875e-3adab2febf43 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091670647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1091670647 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1724531069 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 4815012000 ps |
| CPU time | 618.55 seconds |
| Started | Jul 30 07:54:20 PM PDT 24 |
| Finished | Jul 30 08:04:38 PM PDT 24 |
| Peak memory | 613028 kb |
| Host | smart-627b1cee-5d5c-4b3e-b854-7c8afed55588 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724531069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.1724531069 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.266801722 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 5144972600 ps |
| CPU time | 608.06 seconds |
| Started | Jul 30 07:53:33 PM PDT 24 |
| Finished | Jul 30 08:03:41 PM PDT 24 |
| Peak memory | 613136 kb |
| Host | smart-24f38cdd-c5a0-4859-b226-323c45db6537 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266801722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.266801722 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3720038080 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 2216735193 ps |
| CPU time | 230.13 seconds |
| Started | Jul 30 07:53:55 PM PDT 24 |
| Finished | Jul 30 07:57:45 PM PDT 24 |
| Peak memory | 609500 kb |
| Host | smart-07eb63e7-f193-4217-abb2-095595eb2323 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720038080 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.3720038080 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2723768601 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 3548168544 ps |
| CPU time | 443.51 seconds |
| Started | Jul 30 07:53:28 PM PDT 24 |
| Finished | Jul 30 08:00:52 PM PDT 24 |
| Peak memory | 609752 kb |
| Host | smart-1de35575-1713-467d-b1c7-239c21844685 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723768601 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.2723768601 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.358577566 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 2319185625 ps |
| CPU time | 160.93 seconds |
| Started | Jul 30 07:56:02 PM PDT 24 |
| Finished | Jul 30 07:58:43 PM PDT 24 |
| Peak memory | 609560 kb |
| Host | smart-118c76c2-3386-49e3-b0a5-1d7957dd8232 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358577566 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.358577566 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2631862859 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 5903166952 ps |
| CPU time | 531.5 seconds |
| Started | Jul 30 07:52:09 PM PDT 24 |
| Finished | Jul 30 08:01:01 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-7d75d0b5-919a-4c29-902f-c0bd6fe3b07a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631862859 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.2631862859 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.370049148 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 5191002400 ps |
| CPU time | 542.27 seconds |
| Started | Jul 30 07:54:26 PM PDT 24 |
| Finished | Jul 30 08:03:28 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-d05f30aa-b209-4518-bbf5-51eb45aacf46 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370049148 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.370049148 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1250367766 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 5146134424 ps |
| CPU time | 489.5 seconds |
| Started | Jul 30 07:54:23 PM PDT 24 |
| Finished | Jul 30 08:02:33 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-d45be903-619c-454b-a211-5fa91e7de5ff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250367766 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.1250367766 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2595898498 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 5200272414 ps |
| CPU time | 467.4 seconds |
| Started | Jul 30 07:53:55 PM PDT 24 |
| Finished | Jul 30 08:01:43 PM PDT 24 |
| Peak memory | 610472 kb |
| Host | smart-dd3cdc14-41b0-4b5e-945c-d727f4d6b686 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595898498 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.2595898498 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1011412337 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 12144993756 ps |
| CPU time | 984.8 seconds |
| Started | Jul 30 07:52:49 PM PDT 24 |
| Finished | Jul 30 08:09:14 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-b659ba62-4ba7-49a3-a1b9-48052cd15e09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011412337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.1011412337 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1697575008 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 3357693377 ps |
| CPU time | 425.42 seconds |
| Started | Jul 30 07:52:23 PM PDT 24 |
| Finished | Jul 30 07:59:29 PM PDT 24 |
| Peak memory | 610212 kb |
| Host | smart-96cde19c-6cd0-4e83-87ec-8cc164ef3e54 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697575008 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.1697575008 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.530631881 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 4493591104 ps |
| CPU time | 584.14 seconds |
| Started | Jul 30 07:52:54 PM PDT 24 |
| Finished | Jul 30 08:02:38 PM PDT 24 |
| Peak memory | 610232 kb |
| Host | smart-2fd33e18-9514-4113-a9fe-c2b0f67c6de7 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530631881 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.530631881 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1452466201 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 2971373432 ps |
| CPU time | 259.15 seconds |
| Started | Jul 30 07:54:10 PM PDT 24 |
| Finished | Jul 30 07:58:29 PM PDT 24 |
| Peak memory | 608384 kb |
| Host | smart-36a53fe2-639e-40d5-8c3e-f2cbd6ab046c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452466201 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.1452466201 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.58073807 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 71255555936 ps |
| CPU time | 15076.1 seconds |
| Started | Jul 30 07:54:24 PM PDT 24 |
| Finished | Jul 31 12:05:42 AM PDT 24 |
| Peak memory | 610436 kb |
| Host | smart-92106293-eb02-4930-a2f6-02f68cc67e8e |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=58073807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.58073807 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3218205601 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 13139017492 ps |
| CPU time | 3641.38 seconds |
| Started | Jul 30 07:55:42 PM PDT 24 |
| Finished | Jul 30 08:56:24 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-d6f4f358-3c9b-4da3-bf7b-b39981cdd22f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218205601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.3218205601 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1904369340 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 9460374363 ps |
| CPU time | 1954.7 seconds |
| Started | Jul 30 07:57:18 PM PDT 24 |
| Finished | Jul 30 08:29:53 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-1e5f9990-26a1-41dd-8be0-bf64b687c808 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1904369340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.1904369340 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3220696871 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 3572211466 ps |
| CPU time | 426.29 seconds |
| Started | Jul 30 07:51:50 PM PDT 24 |
| Finished | Jul 30 07:58:56 PM PDT 24 |
| Peak memory | 610520 kb |
| Host | smart-9b2b85b1-462f-4f75-ae4b-81fe5c2d17eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32206 96871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.3220696871 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.3235574868 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 2633102122 ps |
| CPU time | 274.03 seconds |
| Started | Jul 30 07:55:43 PM PDT 24 |
| Finished | Jul 30 08:00:17 PM PDT 24 |
| Peak memory | 609592 kb |
| Host | smart-2c66085f-bd9e-4264-a2d1-8b927514315d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235574868 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.3235574868 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1060735955 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 7901445527 ps |
| CPU time | 842.45 seconds |
| Started | Jul 30 07:53:47 PM PDT 24 |
| Finished | Jul 30 08:07:50 PM PDT 24 |
| Peak memory | 611028 kb |
| Host | smart-bd0e0761-11b7-4bb4-b52c-ef527540aba9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060735955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.1060735955 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.3531496751 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 2978924760 ps |
| CPU time | 293.93 seconds |
| Started | Jul 30 07:54:19 PM PDT 24 |
| Finished | Jul 30 07:59:13 PM PDT 24 |
| Peak memory | 609624 kb |
| Host | smart-2395b55a-be21-4ed4-8f58-07afb48924c9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531496751 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.3531496751 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.1994275943 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 4960923720 ps |
| CPU time | 1499.14 seconds |
| Started | Jul 30 07:55:10 PM PDT 24 |
| Finished | Jul 30 08:20:10 PM PDT 24 |
| Peak memory | 610244 kb |
| Host | smart-0afa16b4-41e6-43d8-a6da-b9d6a9047fc9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994275943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.1994275943 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3144819032 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 5615764664 ps |
| CPU time | 898.21 seconds |
| Started | Jul 30 07:54:24 PM PDT 24 |
| Finished | Jul 30 08:09:23 PM PDT 24 |
| Peak memory | 610968 kb |
| Host | smart-b2a9f887-9ca6-4002-aecf-6127810166ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3144819032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.3144819032 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3541151802 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 6778492022 ps |
| CPU time | 1320 seconds |
| Started | Jul 30 07:55:38 PM PDT 24 |
| Finished | Jul 30 08:17:39 PM PDT 24 |
| Peak memory | 610976 kb |
| Host | smart-3580c3fe-32fb-4e88-a358-e248ce5fcadf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541151802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.3541151802 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.2645893781 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 3536167240 ps |
| CPU time | 787.28 seconds |
| Started | Jul 30 07:54:28 PM PDT 24 |
| Finished | Jul 30 08:07:36 PM PDT 24 |
| Peak memory | 615616 kb |
| Host | smart-b9bfb6a4-6b09-487a-9c8b-5a492f8713e6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645893781 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.2645893781 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.705642536 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 10639088556 ps |
| CPU time | 2376.92 seconds |
| Started | Jul 30 07:52:43 PM PDT 24 |
| Finished | Jul 30 08:32:21 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-d56e7320-107f-4988-827a-403025b9e9f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705642536 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.705642536 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2430718548 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 3026058212 ps |
| CPU time | 229.51 seconds |
| Started | Jul 30 07:54:10 PM PDT 24 |
| Finished | Jul 30 07:58:00 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-acaf5c78-6fb4-4b8b-b21e-4506d01e01c1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24 30718548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.2430718548 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.486695823 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 6630402788 ps |
| CPU time | 1363.79 seconds |
| Started | Jul 30 07:53:38 PM PDT 24 |
| Finished | Jul 30 08:16:22 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-b31d4724-ca84-4b19-a6ff-d8fff0440588 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=486695823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.486695823 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3235072652 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 3138639934 ps |
| CPU time | 176.21 seconds |
| Started | Jul 30 07:55:35 PM PDT 24 |
| Finished | Jul 30 07:58:32 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-aa1eeefe-1010-401e-9d00-4593134c3ea0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235072652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.3235072652 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3482328914 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 3830944616 ps |
| CPU time | 448.37 seconds |
| Started | Jul 30 07:55:57 PM PDT 24 |
| Finished | Jul 30 08:03:26 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-611a7582-1aa9-4896-9c6d-7a896980c128 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3482328914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.3482328914 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.514732661 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 3294631484 ps |
| CPU time | 227.17 seconds |
| Started | Jul 30 07:52:07 PM PDT 24 |
| Finished | Jul 30 07:55:55 PM PDT 24 |
| Peak memory | 609564 kb |
| Host | smart-252f6b1f-7a11-4a62-a661-22ffea8308e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514732661 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_concurrency.514732661 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.2198446413 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 3153959372 ps |
| CPU time | 262.82 seconds |
| Started | Jul 30 07:52:39 PM PDT 24 |
| Finished | Jul 30 07:57:02 PM PDT 24 |
| Peak memory | 609608 kb |
| Host | smart-75a30cf3-c258-4bd9-a256-ee91b49d688c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198446413 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.2198446413 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.2025254075 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 2962194412 ps |
| CPU time | 243.2 seconds |
| Started | Jul 30 07:51:49 PM PDT 24 |
| Finished | Jul 30 07:55:52 PM PDT 24 |
| Peak memory | 609372 kb |
| Host | smart-529330f1-eb7d-4403-87b2-19ea32a7c318 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025254075 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.2025254075 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.4088310064 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 2452976504 ps |
| CPU time | 142.42 seconds |
| Started | Jul 30 07:50:13 PM PDT 24 |
| Finished | Jul 30 07:52:36 PM PDT 24 |
| Peak memory | 607920 kb |
| Host | smart-d81df47e-9736-49dd-976e-3750eac2b505 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088310064 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_rom.4088310064 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.73076627 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 58521922992 ps |
| CPU time | 10601.7 seconds |
| Started | Jul 30 07:50:54 PM PDT 24 |
| Finished | Jul 30 10:47:37 PM PDT 24 |
| Peak memory | 624780 kb |
| Host | smart-206c5de7-62a8-4bbf-8c9b-ad924f904d0c |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=73076627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.73076627 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.3740264081 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 4947072296 ps |
| CPU time | 779.63 seconds |
| Started | Jul 30 07:56:24 PM PDT 24 |
| Finished | Jul 30 08:09:24 PM PDT 24 |
| Peak memory | 611204 kb |
| Host | smart-bacd0363-8887-4ffc-80f7-93a2c3cc9387 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3740264081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.3740264081 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1022027576 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 5638602806 ps |
| CPU time | 809.74 seconds |
| Started | Jul 30 07:54:14 PM PDT 24 |
| Finished | Jul 30 08:07:44 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-d3b14ad1-8c80-4f04-8b75-237854f2cae6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022027576 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.1022027576 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1308144418 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 6219574216 ps |
| CPU time | 1229.4 seconds |
| Started | Jul 30 07:51:37 PM PDT 24 |
| Finished | Jul 30 08:12:06 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-de60ba5a-2390-46a8-892d-94ac72c02fcb |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308144418 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.1308144418 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2545435883 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 7506645969 ps |
| CPU time | 1108.51 seconds |
| Started | Jul 30 07:53:21 PM PDT 24 |
| Finished | Jul 30 08:11:50 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-de67c562-fb62-40e8-a0a2-f6c3c9686932 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545435883 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2545435883 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.838081487 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 5633979776 ps |
| CPU time | 1130.95 seconds |
| Started | Jul 30 07:53:31 PM PDT 24 |
| Finished | Jul 30 08:12:23 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-f9a10d34-8f64-468d-b42c-3b75336dab99 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838081487 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.838081487 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2989326659 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 3331581480 ps |
| CPU time | 370.38 seconds |
| Started | Jul 30 07:51:05 PM PDT 24 |
| Finished | Jul 30 07:57:16 PM PDT 24 |
| Peak memory | 609716 kb |
| Host | smart-c1e36994-2d8f-4d84-ad6e-e47deb34e945 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989326659 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.2989326659 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1420602264 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 4989748384 ps |
| CPU time | 375.84 seconds |
| Started | Jul 30 07:54:26 PM PDT 24 |
| Finished | Jul 30 08:00:41 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-0d3ad36d-eecd-426e-9654-0de11548a3c6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14 20602264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.1420602264 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3074279699 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 5739671806 ps |
| CPU time | 1158.02 seconds |
| Started | Jul 30 07:54:36 PM PDT 24 |
| Finished | Jul 30 08:13:55 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-2e24d800-7784-428e-ba21-3a4ac3515646 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074279699 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.3074279699 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3994097842 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 4463684721 ps |
| CPU time | 632.94 seconds |
| Started | Jul 30 07:54:34 PM PDT 24 |
| Finished | Jul 30 08:05:07 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-d36dc5d0-b2eb-4dcb-88ad-7be3838aa37c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3994097842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.3994097842 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4110093816 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 5173722830 ps |
| CPU time | 696.5 seconds |
| Started | Jul 30 07:53:30 PM PDT 24 |
| Finished | Jul 30 08:05:07 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-0f7db882-73b4-4cf1-a9dd-f597e195e125 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=4110093816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4110093816 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2425420864 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 2685274440 ps |
| CPU time | 373.34 seconds |
| Started | Jul 30 07:57:12 PM PDT 24 |
| Finished | Jul 30 08:03:26 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-631b2e9c-85d2-49d1-8077-70886fd3e59f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425420 864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.2425420864 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.81945945 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 17278513688 ps |
| CPU time | 1805.59 seconds |
| Started | Jul 30 07:50:59 PM PDT 24 |
| Finished | Jul 30 08:21:07 PM PDT 24 |
| Peak memory | 612572 kb |
| Host | smart-407a3bf0-4078-4076-8aa4-b6bcc24ced98 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81945945 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.81945945 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2113039048 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 2447616312 ps |
| CPU time | 180.01 seconds |
| Started | Jul 30 07:57:47 PM PDT 24 |
| Finished | Jul 30 08:00:47 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-9a17a263-67fe-4810-b406-49ed67f6a1ae |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2113039048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.2113039048 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.3435951097 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 2903477068 ps |
| CPU time | 265.13 seconds |
| Started | Jul 30 07:57:00 PM PDT 24 |
| Finished | Jul 30 08:01:26 PM PDT 24 |
| Peak memory | 608900 kb |
| Host | smart-49d92618-6881-4336-ba24-076471adf54a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435951097 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.3435951097 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.4233218802 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 2999951390 ps |
| CPU time | 226.61 seconds |
| Started | Jul 30 07:51:05 PM PDT 24 |
| Finished | Jul 30 07:54:52 PM PDT 24 |
| Peak memory | 609648 kb |
| Host | smart-612e5dbe-6917-4d75-845f-33260135b792 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233218802 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.4233218802 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.568518791 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 2648079104 ps |
| CPU time | 328.35 seconds |
| Started | Jul 30 07:56:05 PM PDT 24 |
| Finished | Jul 30 08:01:33 PM PDT 24 |
| Peak memory | 609504 kb |
| Host | smart-dcdd930c-99d1-41b4-89ce-6fef1254707c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568518791 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_hmac_enc_idle.568518791 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.761582440 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 3025886679 ps |
| CPU time | 258.89 seconds |
| Started | Jul 30 07:51:02 PM PDT 24 |
| Finished | Jul 30 07:55:21 PM PDT 24 |
| Peak memory | 609860 kb |
| Host | smart-69a59ea7-1c7c-4230-a672-3808530b8ad9 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761582440 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.761582440 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.2477548399 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 7893856020 ps |
| CPU time | 1881.07 seconds |
| Started | Jul 30 07:53:51 PM PDT 24 |
| Finished | Jul 30 08:25:13 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-9d8a5d1d-15b4-49af-8d1b-8c08cb6997e0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477548399 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.2477548399 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.718872106 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 3169952528 ps |
| CPU time | 303.92 seconds |
| Started | Jul 30 07:53:30 PM PDT 24 |
| Finished | Jul 30 07:58:34 PM PDT 24 |
| Peak memory | 609616 kb |
| Host | smart-c18f638f-3f4b-4705-a594-e4dd709ab3e5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718872106 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.718872106 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.3840516225 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 3218514872 ps |
| CPU time | 359.78 seconds |
| Started | Jul 30 07:55:46 PM PDT 24 |
| Finished | Jul 30 08:01:46 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-e3fdbfa0-f7d5-4084-93f1-da698fe232e3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840516225 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.3840516225 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2975374572 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 5401200512 ps |
| CPU time | 827.55 seconds |
| Started | Jul 30 07:50:56 PM PDT 24 |
| Finished | Jul 30 08:04:44 PM PDT 24 |
| Peak memory | 609216 kb |
| Host | smart-3ebd8c58-e360-401e-a78f-f2cbfd4f23dd |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975374572 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.2975374572 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1180142251 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 4703648240 ps |
| CPU time | 626.49 seconds |
| Started | Jul 30 07:54:06 PM PDT 24 |
| Finished | Jul 30 08:04:34 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-3f562c50-a6bc-4308-b268-8a514ac21f95 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180142251 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.1180142251 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1061964263 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 4433268340 ps |
| CPU time | 734.19 seconds |
| Started | Jul 30 07:51:45 PM PDT 24 |
| Finished | Jul 30 08:04:00 PM PDT 24 |
| Peak memory | 609224 kb |
| Host | smart-969f8f4c-f711-482b-bb80-5fc7c559a636 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061964263 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.1061964263 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3738618920 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 66841545252 ps |
| CPU time | 12274.6 seconds |
| Started | Jul 30 07:51:22 PM PDT 24 |
| Finished | Jul 30 11:15:58 PM PDT 24 |
| Peak memory | 624756 kb |
| Host | smart-6868b418-7526-4eea-929e-28da14564400 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3738618920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.3738618920 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.4011263640 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 8888816524 ps |
| CPU time | 2119.59 seconds |
| Started | Jul 30 07:53:08 PM PDT 24 |
| Finished | Jul 30 08:28:28 PM PDT 24 |
| Peak memory | 616548 kb |
| Host | smart-472e8582-c9b0-4b73-8e6d-625d178906f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011 263640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.4011263640 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.27481408 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 12751343603 ps |
| CPU time | 3047.16 seconds |
| Started | Jul 30 07:52:59 PM PDT 24 |
| Finished | Jul 30 08:43:47 PM PDT 24 |
| Peak memory | 617884 kb |
| Host | smart-41af3a1c-652a-49b6-99f5-b20788303cf2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=27481408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.27481408 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2549778766 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 8535696226 ps |
| CPU time | 1252 seconds |
| Started | Jul 30 07:54:18 PM PDT 24 |
| Finished | Jul 30 08:15:10 PM PDT 24 |
| Peak memory | 616880 kb |
| Host | smart-b7b153e8-44a5-466b-afc1-501e75f3ecdf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2549778766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2549778766 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2060081363 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 9450134054 ps |
| CPU time | 1879.76 seconds |
| Started | Jul 30 07:52:04 PM PDT 24 |
| Finished | Jul 30 08:23:24 PM PDT 24 |
| Peak memory | 617872 kb |
| Host | smart-b575bcd2-065e-4eb3-98d8-7b3f5d1d0f94 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2060081363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.2060081363 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.390028581 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 7977526900 ps |
| CPU time | 1673.48 seconds |
| Started | Jul 30 07:52:31 PM PDT 24 |
| Finished | Jul 30 08:20:25 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-e72f793b-5d23-49e4-af8d-c8862d2f27bd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39002 8581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.390028581 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.2938251204 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 2935242200 ps |
| CPU time | 212.57 seconds |
| Started | Jul 30 07:55:44 PM PDT 24 |
| Finished | Jul 30 07:59:17 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-09a6e847-79f8-42fe-ad98-c66d5c8207a0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938251204 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.2938251204 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.2090951924 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 3367158340 ps |
| CPU time | 320.14 seconds |
| Started | Jul 30 07:52:18 PM PDT 24 |
| Finished | Jul 30 07:57:38 PM PDT 24 |
| Peak memory | 608428 kb |
| Host | smart-954aea41-c65f-426a-9eaa-dfa101cd4f36 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090951924 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_entropy.2090951924 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.2009288462 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 2881479968 ps |
| CPU time | 223.03 seconds |
| Started | Jul 30 07:54:38 PM PDT 24 |
| Finished | Jul 30 07:58:21 PM PDT 24 |
| Peak memory | 609612 kb |
| Host | smart-f5afe1eb-7321-4434-90ca-38fb3d2abd25 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009288462 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.2009288462 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.789218526 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 2210018664 ps |
| CPU time | 184.54 seconds |
| Started | Jul 30 07:52:50 PM PDT 24 |
| Finished | Jul 30 07:55:54 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-cbc77832-6565-43a5-8ee1-a11e79faeff1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789218526 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_kmac_mode_cshake.789218526 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3261472245 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 2517546900 ps |
| CPU time | 310.66 seconds |
| Started | Jul 30 07:52:46 PM PDT 24 |
| Finished | Jul 30 07:57:57 PM PDT 24 |
| Peak memory | 608448 kb |
| Host | smart-17848c12-fc72-4cde-8d6f-4f1368c0b378 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261472245 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.3261472245 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.4098324959 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 2905622728 ps |
| CPU time | 260.65 seconds |
| Started | Jul 30 07:54:30 PM PDT 24 |
| Finished | Jul 30 07:58:51 PM PDT 24 |
| Peak memory | 609396 kb |
| Host | smart-eff16687-acda-45b2-935f-5700087904b0 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098324959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.4098324959 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1109949540 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 3813636966 ps |
| CPU time | 356.43 seconds |
| Started | Jul 30 07:56:51 PM PDT 24 |
| Finished | Jul 30 08:02:48 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-37cb84f1-2d83-4438-81a1-b8cc49fedd13 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11099495 40 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1109949540 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.380075917 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 2322583912 ps |
| CPU time | 280.74 seconds |
| Started | Jul 30 07:55:15 PM PDT 24 |
| Finished | Jul 30 07:59:56 PM PDT 24 |
| Peak memory | 609616 kb |
| Host | smart-4cdf7081-10e8-46d8-90a6-592f4b2a88a9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380075917 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_smoketest.380075917 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3297378590 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 2915457928 ps |
| CPU time | 274.19 seconds |
| Started | Jul 30 07:51:07 PM PDT 24 |
| Finished | Jul 30 07:55:42 PM PDT 24 |
| Peak memory | 609588 kb |
| Host | smart-2cf79270-f248-4c93-8deb-ebc57d8a1f81 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297378590 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.3297378590 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3688913782 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 2883379133 ps |
| CPU time | 131.4 seconds |
| Started | Jul 30 07:51:48 PM PDT 24 |
| Finished | Jul 30 07:54:00 PM PDT 24 |
| Peak memory | 620052 kb |
| Host | smart-4fd8c15a-a227-46c4-893d-793ab46b2daa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36889137 82 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.3688913782 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2620959987 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2616964857 ps |
| CPU time | 133.91 seconds |
| Started | Jul 30 07:52:14 PM PDT 24 |
| Finished | Jul 30 07:54:28 PM PDT 24 |
| Peak memory | 620044 kb |
| Host | smart-a48ef47f-8991-4f4a-ade6-50c3a8db633a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620959987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.2620959987 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.230120552 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 2985925135 ps |
| CPU time | 248.6 seconds |
| Started | Jul 30 07:52:10 PM PDT 24 |
| Finished | Jul 30 07:56:19 PM PDT 24 |
| Peak memory | 621656 kb |
| Host | smart-cfadf265-8359-4fd1-9b7e-1dc0dc22a59e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230120552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.230120552 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1308849695 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 3377971528 ps |
| CPU time | 164.21 seconds |
| Started | Jul 30 07:52:23 PM PDT 24 |
| Finished | Jul 30 07:55:08 PM PDT 24 |
| Peak memory | 620032 kb |
| Host | smart-13a33de9-1d00-4fc3-b3b7-7f6c654e4483 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1308849695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.1308849695 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1424843957 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 1941989558 ps |
| CPU time | 109.99 seconds |
| Started | Jul 30 07:52:44 PM PDT 24 |
| Finished | Jul 30 07:54:35 PM PDT 24 |
| Peak memory | 617564 kb |
| Host | smart-7561c084-43f2-496b-aa77-eabb3fa59d70 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1424843957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.1424843957 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.37222553 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 2712895279 ps |
| CPU time | 107.87 seconds |
| Started | Jul 30 07:53:15 PM PDT 24 |
| Finished | Jul 30 07:55:04 PM PDT 24 |
| Peak memory | 616956 kb |
| Host | smart-7d3a5b73-9aaf-429a-83f0-50ff8e5e0763 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37222553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.37222553 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3196368989 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 7965699914 ps |
| CPU time | 832.2 seconds |
| Started | Jul 30 07:50:48 PM PDT 24 |
| Finished | Jul 30 08:04:41 PM PDT 24 |
| Peak memory | 620308 kb |
| Host | smart-a8cf3e5c-d090-4dc2-a1a6-eb2da57f36fc |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196368989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.3196368989 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3090231174 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 25409951955 ps |
| CPU time | 2377.63 seconds |
| Started | Jul 30 07:53:09 PM PDT 24 |
| Finished | Jul 30 08:32:48 PM PDT 24 |
| Peak memory | 620856 kb |
| Host | smart-08210a6f-e4ef-4596-97c5-f7c92d6a8ac6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3090231174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.3090231174 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1037830782 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 17172863608 ps |
| CPU time | 4104.15 seconds |
| Started | Jul 30 07:51:49 PM PDT 24 |
| Finished | Jul 30 09:00:14 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-c9618220-499f-4170-ba3c-89d9b3c32e34 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1037830782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.1037830782 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1122268028 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 18702334559 ps |
| CPU time | 3671.93 seconds |
| Started | Jul 30 07:52:05 PM PDT 24 |
| Finished | Jul 30 08:53:18 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-3b22eba1-5462-447d-8640-165f335ca03d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1122268028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1122268028 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.173410390 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 3849178168 ps |
| CPU time | 428.18 seconds |
| Started | Jul 30 07:55:41 PM PDT 24 |
| Finished | Jul 30 08:02:49 PM PDT 24 |
| Peak memory | 608880 kb |
| Host | smart-7cfd1ab4-1624-4e48-819f-a89729798300 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173410390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.173410390 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.1476696791 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 5744316312 ps |
| CPU time | 1096.47 seconds |
| Started | Jul 30 07:55:30 PM PDT 24 |
| Finished | Jul 30 08:13:47 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-4ba7a034-48c1-4bb9-a8ca-835431e9108f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1476696791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.1476696791 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.3122602947 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 9561259820 ps |
| CPU time | 2188.89 seconds |
| Started | Jul 30 07:55:40 PM PDT 24 |
| Finished | Jul 30 08:32:09 PM PDT 24 |
| Peak memory | 608972 kb |
| Host | smart-2dedf14b-2e75-4eb1-831d-54afa9690698 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122602947 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.3122602947 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2175912743 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 28388404456 ps |
| CPU time | 6292.66 seconds |
| Started | Jul 30 07:51:00 PM PDT 24 |
| Finished | Jul 30 09:35:53 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-21cb123c-67e4-4ad9-ab00-b3f6efadebf6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217591 2743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.2175912743 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2025463760 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 3529663810 ps |
| CPU time | 264.59 seconds |
| Started | Jul 30 07:52:56 PM PDT 24 |
| Finished | Jul 30 07:57:22 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-cf9838f6-adda-4427-8b9b-84f2fc73833a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025463760 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.2025463760 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.494377577 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 5134781038 ps |
| CPU time | 539.7 seconds |
| Started | Jul 30 07:55:30 PM PDT 24 |
| Finished | Jul 30 08:04:30 PM PDT 24 |
| Peak memory | 611224 kb |
| Host | smart-5f406387-af7a-4e99-ae0e-60f0b2af4860 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 494377577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.494377577 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3400595433 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 7487857128 ps |
| CPU time | 1217.77 seconds |
| Started | Jul 30 07:51:32 PM PDT 24 |
| Finished | Jul 30 08:11:50 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-59838643-dfb9-4551-82c7-9545c15ba1ad |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3400595433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.3400595433 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.837405068 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 8560351264 ps |
| CPU time | 1431.19 seconds |
| Started | Jul 30 07:53:37 PM PDT 24 |
| Finished | Jul 30 08:17:29 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-215899a4-2d0f-4dce-acf5-57cfb0cf2004 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=837405068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.837405068 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3978175562 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 8539982456 ps |
| CPU time | 1506.86 seconds |
| Started | Jul 30 07:51:39 PM PDT 24 |
| Finished | Jul 30 08:16:47 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-b39cd430-4716-4bdb-bd2c-d57f80ae22e4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3978175562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.3978175562 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3561485118 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 4405563768 ps |
| CPU time | 644.2 seconds |
| Started | Jul 30 07:53:28 PM PDT 24 |
| Finished | Jul 30 08:04:13 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-bd693161-a2c2-4153-b787-29933a2c4f2c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3561485118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3561485118 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1173258356 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3007722320 ps |
| CPU time | 213.23 seconds |
| Started | Jul 30 07:55:16 PM PDT 24 |
| Finished | Jul 30 07:58:50 PM PDT 24 |
| Peak memory | 608388 kb |
| Host | smart-169a542f-4f10-4f97-aa1e-81ab9a07bbcb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173258356 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.1173258356 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.4102792448 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 3328653030 ps |
| CPU time | 268.46 seconds |
| Started | Jul 30 07:52:10 PM PDT 24 |
| Finished | Jul 30 07:56:39 PM PDT 24 |
| Peak memory | 612312 kb |
| Host | smart-77942b43-8834-4b70-8c51-a91a44880b75 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102792448 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.4102792448 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.2280070091 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 3843282432 ps |
| CPU time | 594.5 seconds |
| Started | Jul 30 07:57:00 PM PDT 24 |
| Finished | Jul 30 08:06:54 PM PDT 24 |
| Peak memory | 608896 kb |
| Host | smart-9046b613-1b02-4fd3-937b-c4e3adf2886b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280070091 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.2280070091 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.3053130414 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 11525115864 ps |
| CPU time | 498.69 seconds |
| Started | Jul 30 07:53:57 PM PDT 24 |
| Finished | Jul 30 08:02:16 PM PDT 24 |
| Peak memory | 610884 kb |
| Host | smart-54f79c00-2dde-4b4d-9fc2-cbf57378df3b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053130414 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.3053130414 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_virus.3110211814 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 5779840574 ps |
| CPU time | 1467.11 seconds |
| Started | Jul 30 07:59:57 PM PDT 24 |
| Finished | Jul 30 08:24:25 PM PDT 24 |
| Peak memory | 624992 kb |
| Host | smart-0b7ea85e-169c-4570-8577-f809c999e7e9 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3110211814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.3110211814 |
| Directory | /workspace/0.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2016204832 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 12927232815 ps |
| CPU time | 1237.35 seconds |
| Started | Jul 30 07:51:42 PM PDT 24 |
| Finished | Jul 30 08:12:20 PM PDT 24 |
| Peak memory | 611500 kb |
| Host | smart-4171bea8-315e-4365-83b7-30e04d8d3a7f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016 204832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.2016204832 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3879460247 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 30428615559 ps |
| CPU time | 2709.23 seconds |
| Started | Jul 30 07:56:07 PM PDT 24 |
| Finished | Jul 30 08:41:17 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-2069a567-7f9d-4b85-b3db-9212ab9e2abd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387 9460247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.3879460247 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4265943525 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 16326024841 ps |
| CPU time | 1762.86 seconds |
| Started | Jul 30 07:56:02 PM PDT 24 |
| Finished | Jul 30 08:25:25 PM PDT 24 |
| Peak memory | 611472 kb |
| Host | smart-8ba9e174-323d-4206-8dba-11577ec911c4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4265943525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4265943525 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1488117763 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 23284450780 ps |
| CPU time | 1326.69 seconds |
| Started | Jul 30 07:55:06 PM PDT 24 |
| Finished | Jul 30 08:17:13 PM PDT 24 |
| Peak memory | 611096 kb |
| Host | smart-4a224f02-52a6-4f67-a9df-ab14a41450d0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1488117763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1488117763 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1821627922 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 9551213400 ps |
| CPU time | 853.01 seconds |
| Started | Jul 30 07:52:09 PM PDT 24 |
| Finished | Jul 30 08:06:22 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-f088f626-973d-4ec2-b22b-191b9e170ce7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821627922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.1821627922 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.661317814 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 4882718215 ps |
| CPU time | 357.9 seconds |
| Started | Jul 30 07:53:30 PM PDT 24 |
| Finished | Jul 30 07:59:28 PM PDT 24 |
| Peak memory | 617588 kb |
| Host | smart-e53772a4-abed-42a4-a69d-92b051710edc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=661317814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.661317814 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4289930321 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 12878140877 ps |
| CPU time | 1618.66 seconds |
| Started | Jul 30 07:53:11 PM PDT 24 |
| Finished | Jul 30 08:20:10 PM PDT 24 |
| Peak memory | 611204 kb |
| Host | smart-50e152ba-5963-458e-8a79-3341967d7116 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289930321 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4289930321 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1516596470 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 7710876256 ps |
| CPU time | 391.9 seconds |
| Started | Jul 30 07:53:48 PM PDT 24 |
| Finished | Jul 30 08:00:20 PM PDT 24 |
| Peak memory | 609560 kb |
| Host | smart-f86120b4-482f-412b-9dcb-06fb252058bd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516596470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1516596470 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.968295713 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 6313456204 ps |
| CPU time | 694.82 seconds |
| Started | Jul 30 07:54:48 PM PDT 24 |
| Finished | Jul 30 08:06:23 PM PDT 24 |
| Peak memory | 609516 kb |
| Host | smart-885b8ff0-11f9-465c-85c7-4311d33b7adb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968295713 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.968295713 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2978286435 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 28323167490 ps |
| CPU time | 3149.58 seconds |
| Started | Jul 30 07:51:30 PM PDT 24 |
| Finished | Jul 30 08:44:00 PM PDT 24 |
| Peak memory | 611464 kb |
| Host | smart-d1111185-487a-4285-b513-fa385c087dd4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2978286435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2978286435 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2977126350 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 39405270838 ps |
| CPU time | 3388.33 seconds |
| Started | Jul 30 07:53:15 PM PDT 24 |
| Finished | Jul 30 08:49:44 PM PDT 24 |
| Peak memory | 612412 kb |
| Host | smart-195d9025-fbd7-4746-9b07-3b9db4d53ac2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977126350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2977126350 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.4138727475 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 3013781880 ps |
| CPU time | 223.67 seconds |
| Started | Jul 30 07:52:15 PM PDT 24 |
| Finished | Jul 30 07:55:59 PM PDT 24 |
| Peak memory | 609576 kb |
| Host | smart-67fa25fd-e964-4e2b-99b9-d26bc6b12b49 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138727475 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.4138727475 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.931682456 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 6032201992 ps |
| CPU time | 445.46 seconds |
| Started | Jul 30 07:54:43 PM PDT 24 |
| Finished | Jul 30 08:02:09 PM PDT 24 |
| Peak memory | 617460 kb |
| Host | smart-bae7c9ae-1594-4a33-b3bb-ed696ab058d5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=931682456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.931682456 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3832762563 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 5978589890 ps |
| CPU time | 456.83 seconds |
| Started | Jul 30 07:57:31 PM PDT 24 |
| Finished | Jul 30 08:05:08 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-ccfb7e19-eb31-4b39-aa91-7b0ef5eec072 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3832762563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.3832762563 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.965762208 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 6974325640 ps |
| CPU time | 481.59 seconds |
| Started | Jul 30 07:58:22 PM PDT 24 |
| Finished | Jul 30 08:06:24 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-78a206f1-1f78-4ca1-b134-dfbd31d64b7a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965762208 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.965762208 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1692836849 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 6957475856 ps |
| CPU time | 840.9 seconds |
| Started | Jul 30 07:51:45 PM PDT 24 |
| Finished | Jul 30 08:05:46 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-65bf7c74-e718-4ed5-82cb-eb67bfb35d10 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692836849 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.1692836849 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3056623399 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 5106751590 ps |
| CPU time | 464.39 seconds |
| Started | Jul 30 07:52:17 PM PDT 24 |
| Finished | Jul 30 08:00:02 PM PDT 24 |
| Peak memory | 610452 kb |
| Host | smart-9bf79370-91d7-44a5-beb2-f6bd105d60cf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056623399 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3056623399 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2532994398 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 6088009340 ps |
| CPU time | 419.75 seconds |
| Started | Jul 30 07:54:53 PM PDT 24 |
| Finished | Jul 30 08:01:53 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-135dbba4-36fd-4a73-a716-852b0b079b9d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532994398 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.2532994398 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.356437447 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 3632669272 ps |
| CPU time | 494.01 seconds |
| Started | Jul 30 07:52:49 PM PDT 24 |
| Finished | Jul 30 08:01:03 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-db8d757c-331c-4bae-8c03-52a90c4feb34 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356 437447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.356437447 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3920935116 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 8339078222 ps |
| CPU time | 731.55 seconds |
| Started | Jul 30 07:52:54 PM PDT 24 |
| Finished | Jul 30 08:05:05 PM PDT 24 |
| Peak memory | 624816 kb |
| Host | smart-d258c80b-c86c-4c73-ab6b-3423bc99c9e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920935116 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.3920935116 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3095907972 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 6312583556 ps |
| CPU time | 653.95 seconds |
| Started | Jul 30 07:53:47 PM PDT 24 |
| Finished | Jul 30 08:04:41 PM PDT 24 |
| Peak memory | 610212 kb |
| Host | smart-05c1f620-2efb-4714-acea-4d4e4e2b38fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095907972 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.3095907972 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1246409231 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 5725140636 ps |
| CPU time | 774.86 seconds |
| Started | Jul 30 07:50:40 PM PDT 24 |
| Finished | Jul 30 08:03:35 PM PDT 24 |
| Peak memory | 641676 kb |
| Host | smart-1ef0be20-c7f1-4938-a6d6-259c6ae82d3f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1246409231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.1246409231 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3797115810 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 2881441240 ps |
| CPU time | 258.79 seconds |
| Started | Jul 30 07:56:53 PM PDT 24 |
| Finished | Jul 30 08:01:12 PM PDT 24 |
| Peak memory | 609616 kb |
| Host | smart-92a17c3a-56ee-4e34-9a86-4ab9b36837ec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797115810 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.3797115810 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.4164455345 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4590467982 ps |
| CPU time | 380.05 seconds |
| Started | Jul 30 07:52:47 PM PDT 24 |
| Finished | Jul 30 07:59:07 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-388f89d9-c63a-4b06-8a57-b1e5f70e5353 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164455345 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.4164455345 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.2503966773 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 2878958160 ps |
| CPU time | 290.58 seconds |
| Started | Jul 30 07:52:39 PM PDT 24 |
| Finished | Jul 30 07:57:30 PM PDT 24 |
| Peak memory | 608404 kb |
| Host | smart-9b19e127-4633-410f-bd38-42ff228a4d60 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503966773 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.2503966773 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2879825591 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 3063947966 ps |
| CPU time | 269.79 seconds |
| Started | Jul 30 07:54:37 PM PDT 24 |
| Finished | Jul 30 07:59:07 PM PDT 24 |
| Peak memory | 609340 kb |
| Host | smart-62ae0719-4649-4eb1-9ffd-5cd232ee94a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879825591 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.2879825591 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3603880630 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 5504547488 ps |
| CPU time | 1182.47 seconds |
| Started | Jul 30 07:55:46 PM PDT 24 |
| Finished | Jul 30 08:15:29 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-753c6d54-e149-461d-b368-09638316ed05 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3603880630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.3603880630 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2926939575 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 6695875142 ps |
| CPU time | 480.42 seconds |
| Started | Jul 30 07:55:53 PM PDT 24 |
| Finished | Jul 30 08:03:54 PM PDT 24 |
| Peak memory | 621500 kb |
| Host | smart-6c2b275f-1917-4e17-9c59-fbd331791abb |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926939575 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.2926939575 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.118021537 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 2486660022 ps |
| CPU time | 208.58 seconds |
| Started | Jul 30 07:56:54 PM PDT 24 |
| Finished | Jul 30 08:00:23 PM PDT 24 |
| Peak memory | 609628 kb |
| Host | smart-dfa94e10-eea0-47d6-9885-d5fb100ffb04 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118021537 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rv_plic_smoketest.118021537 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.2131359894 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 2870819936 ps |
| CPU time | 347.83 seconds |
| Started | Jul 30 07:55:48 PM PDT 24 |
| Finished | Jul 30 08:01:36 PM PDT 24 |
| Peak memory | 609584 kb |
| Host | smart-bd9a55ae-93a3-49cd-9fda-61ad67aa2d30 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131359894 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.2131359894 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1709423297 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 3335058746 ps |
| CPU time | 228.08 seconds |
| Started | Jul 30 07:58:32 PM PDT 24 |
| Finished | Jul 30 08:02:20 PM PDT 24 |
| Peak memory | 609536 kb |
| Host | smart-9373ad16-5bd0-41b1-a185-e4f9ad2309ac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709423297 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.1709423297 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2343116302 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 3258928782 ps |
| CPU time | 255.34 seconds |
| Started | Jul 30 07:54:20 PM PDT 24 |
| Finished | Jul 30 07:58:36 PM PDT 24 |
| Peak memory | 609524 kb |
| Host | smart-a5097219-3880-4fbe-938c-96c8b51e008b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343116 302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.2343116302 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2948993665 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 8912415484 ps |
| CPU time | 879.84 seconds |
| Started | Jul 30 07:53:29 PM PDT 24 |
| Finished | Jul 30 08:08:09 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-6bab3711-d79e-46fc-b286-c38f8eb21cc7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948993665 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.2948993665 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2014776052 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 6912016650 ps |
| CPU time | 642.12 seconds |
| Started | Jul 30 07:53:30 PM PDT 24 |
| Finished | Jul 30 08:04:12 PM PDT 24 |
| Peak memory | 610612 kb |
| Host | smart-167c3cba-6a21-49c8-93fc-ca0fa0d5e708 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014776052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.2014776052 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1494058539 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 8705303664 ps |
| CPU time | 663.99 seconds |
| Started | Jul 30 07:52:23 PM PDT 24 |
| Finished | Jul 30 08:03:27 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-f2f21218-405c-4c17-9750-63ecb610c87b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494058539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.1494058539 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.1178794894 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 5946331055 ps |
| CPU time | 501.29 seconds |
| Started | Jul 30 07:51:33 PM PDT 24 |
| Finished | Jul 30 07:59:55 PM PDT 24 |
| Peak memory | 624836 kb |
| Host | smart-1705855e-00b6-43c6-8b25-dde1073e24a7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178794894 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.1178794894 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.2546209761 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3500330520 ps |
| CPU time | 434.05 seconds |
| Started | Jul 30 07:53:10 PM PDT 24 |
| Finished | Jul 30 08:00:25 PM PDT 24 |
| Peak memory | 618104 kb |
| Host | smart-593f3003-33f2-4b67-9b96-889afd6dc3ab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546209761 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.2546209761 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2513613887 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2784734190 ps |
| CPU time | 282.01 seconds |
| Started | Jul 30 07:52:19 PM PDT 24 |
| Finished | Jul 30 07:57:01 PM PDT 24 |
| Peak memory | 608860 kb |
| Host | smart-2b25fa56-3893-4814-a386-8d46c27226fe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513613887 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.2513613887 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1956747308 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 8882912126 ps |
| CPU time | 615.62 seconds |
| Started | Jul 30 07:52:29 PM PDT 24 |
| Finished | Jul 30 08:02:45 PM PDT 24 |
| Peak memory | 610708 kb |
| Host | smart-9e7c5a56-737a-4180-ae04-a0ecc1fb0b2c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956747308 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.1956747308 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.188873179 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 3616031580 ps |
| CPU time | 644.94 seconds |
| Started | Jul 30 07:54:29 PM PDT 24 |
| Finished | Jul 30 08:05:14 PM PDT 24 |
| Peak memory | 610916 kb |
| Host | smart-db94ee78-a4de-499f-a957-d684af87707e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188873179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ sram_ctrl_scrambled_access.188873179 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.138184208 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 5958795680 ps |
| CPU time | 636.94 seconds |
| Started | Jul 30 07:55:02 PM PDT 24 |
| Finished | Jul 30 08:05:39 PM PDT 24 |
| Peak memory | 611124 kb |
| Host | smart-ed7ad541-ed0b-4821-b464-a7b39b78d47e |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138184208 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.138184208 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1274515192 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 2868825576 ps |
| CPU time | 215.51 seconds |
| Started | Jul 30 07:57:19 PM PDT 24 |
| Finished | Jul 30 08:00:55 PM PDT 24 |
| Peak memory | 609580 kb |
| Host | smart-29d0659f-656c-4840-913c-6de529045d1b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274515192 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.1274515192 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3828604840 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 21073494711 ps |
| CPU time | 3754.46 seconds |
| Started | Jul 30 07:52:51 PM PDT 24 |
| Finished | Jul 30 08:55:26 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-c0287d70-4c4c-4de1-b5bb-823aeb976739 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828604840 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.3828604840 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2046322236 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 5584349265 ps |
| CPU time | 773.85 seconds |
| Started | Jul 30 07:52:11 PM PDT 24 |
| Finished | Jul 30 08:05:06 PM PDT 24 |
| Peak memory | 613692 kb |
| Host | smart-06a3a0a5-594d-4b2d-b672-2cfd1af496e0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046322236 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.2046322236 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.334725693 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 3294880346 ps |
| CPU time | 236.08 seconds |
| Started | Jul 30 07:53:57 PM PDT 24 |
| Finished | Jul 30 07:57:54 PM PDT 24 |
| Peak memory | 613260 kb |
| Host | smart-6b3bf313-0ae7-41f0-8735-2d1782648af5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334725693 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.334725693 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1342390572 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 3295965236 ps |
| CPU time | 348.59 seconds |
| Started | Jul 30 07:51:24 PM PDT 24 |
| Finished | Jul 30 07:57:13 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-2203a713-ce43-4f00-88c0-1fb7ca0cd7a9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342390572 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.1342390572 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2454570301 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 24402000532 ps |
| CPU time | 1736.1 seconds |
| Started | Jul 30 07:52:26 PM PDT 24 |
| Finished | Jul 30 08:21:23 PM PDT 24 |
| Peak memory | 615076 kb |
| Host | smart-eb2c84d7-8bd1-467b-9d7c-2a3dc584df23 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24545703 01 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.2454570301 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2766575036 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5928878000 ps |
| CPU time | 569.34 seconds |
| Started | Jul 30 07:53:27 PM PDT 24 |
| Finished | Jul 30 08:02:58 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-02a11fc3-fd9e-4289-8d3f-ee52be09fb72 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766575036 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2766575036 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.795444504 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 2778017268 ps |
| CPU time | 379.41 seconds |
| Started | Jul 30 07:59:29 PM PDT 24 |
| Finished | Jul 30 08:05:49 PM PDT 24 |
| Peak memory | 615056 kb |
| Host | smart-3959f5dd-06db-490f-b11d-971f2e39a9ba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795444504 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_uart_smoketest.795444504 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.241343560 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 4074646080 ps |
| CPU time | 648.48 seconds |
| Started | Jul 30 07:54:54 PM PDT 24 |
| Finished | Jul 30 08:05:43 PM PDT 24 |
| Peak memory | 623528 kb |
| Host | smart-2cfa34b6-824f-4ed3-9731-5224455cecaa |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241343560 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.241343560 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3206625609 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 3888488069 ps |
| CPU time | 407.03 seconds |
| Started | Jul 30 07:50:42 PM PDT 24 |
| Finished | Jul 30 07:57:30 PM PDT 24 |
| Peak memory | 623428 kb |
| Host | smart-5d98ec6f-9ee9-4788-a620-07cf227101b7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206625609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3206625609 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.523705669 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 78135029638 ps |
| CPU time | 13372 seconds |
| Started | Jul 30 07:54:07 PM PDT 24 |
| Finished | Jul 30 11:37:00 PM PDT 24 |
| Peak memory | 634040 kb |
| Host | smart-c20faa14-6b9b-4b0e-8b81-e73f2d434998 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=523705669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.523705669 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.847231572 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 4114113460 ps |
| CPU time | 625.63 seconds |
| Started | Jul 30 07:54:15 PM PDT 24 |
| Finished | Jul 30 08:04:41 PM PDT 24 |
| Peak memory | 623860 kb |
| Host | smart-d51b66bc-92cf-43fe-bb4f-82250af07553 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847231572 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.847231572 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.600499222 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3933268292 ps |
| CPU time | 555.97 seconds |
| Started | Jul 30 07:53:30 PM PDT 24 |
| Finished | Jul 30 08:02:47 PM PDT 24 |
| Peak memory | 623872 kb |
| Host | smart-e4e984f0-139f-43e0-ad98-3cc04c1f91ac |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600499222 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.600499222 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3869458378 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 3374453293 ps |
| CPU time | 359.16 seconds |
| Started | Jul 30 07:55:30 PM PDT 24 |
| Finished | Jul 30 08:01:30 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-ff3b5c08-1534-4f6b-a20b-85b1001e7104 |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869458378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.3869458378 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.1304229515 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7382914100 ps |
| CPU time | 2191.37 seconds |
| Started | Jul 30 07:52:29 PM PDT 24 |
| Finished | Jul 30 08:29:02 PM PDT 24 |
| Peak memory | 608936 kb |
| Host | smart-7b092078-9d42-4bda-a734-171be44f9e35 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13042 29515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.1304229515 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.350037313 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 31710682024 ps |
| CPU time | 7511.89 seconds |
| Started | Jul 30 07:53:57 PM PDT 24 |
| Finished | Jul 30 09:59:11 PM PDT 24 |
| Peak memory | 608892 kb |
| Host | smart-6f0deff3-b4b2-4c95-986a-c388055df267 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=350037313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.350037313 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.2634432331 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2845467360 ps |
| CPU time | 208.31 seconds |
| Started | Jul 30 07:53:51 PM PDT 24 |
| Finished | Jul 30 07:57:20 PM PDT 24 |
| Peak memory | 609716 kb |
| Host | smart-b6dfe7a9-d458-4948-85b1-4d7d207e168b |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634432331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.2634432331 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.1501789296 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 3275846956 ps |
| CPU time | 470.94 seconds |
| Started | Jul 30 07:50:41 PM PDT 24 |
| Finished | Jul 30 07:58:32 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-09da4a23-733f-4d7d-8ab3-9abdfad473d2 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150178929 6 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.1501789296 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.175503614 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 18720584328 ps |
| CPU time | 4616.06 seconds |
| Started | Jul 30 07:52:05 PM PDT 24 |
| Finished | Jul 30 09:09:03 PM PDT 24 |
| Peak memory | 609208 kb |
| Host | smart-ba3287d0-d847-4ace-84ef-b0ac844ec729 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=175503614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.175503614 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.1945454695 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 2211188130 ps |
| CPU time | 215.1 seconds |
| Started | Jul 30 07:52:04 PM PDT 24 |
| Finished | Jul 30 07:55:39 PM PDT 24 |
| Peak memory | 609756 kb |
| Host | smart-31184634-0892-4689-80a6-468df0a264fe |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945454695 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.1945454695 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.3733721505 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 2284590636 ps |
| CPU time | 134.98 seconds |
| Started | Jul 30 07:51:45 PM PDT 24 |
| Finished | Jul 30 07:54:01 PM PDT 24 |
| Peak memory | 623296 kb |
| Host | smart-d1c799c5-1dc8-4bcf-b478-4184993df64d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3733721505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.3733721505 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.3485700825 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 13459243176 ps |
| CPU time | 1558.03 seconds |
| Started | Jul 30 07:54:38 PM PDT 24 |
| Finished | Jul 30 08:20:36 PM PDT 24 |
| Peak memory | 624416 kb |
| Host | smart-91ea2cdf-9bac-4403-88b6-87b96bb73ae7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485700825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.3485700825 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.464271197 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 15735288966 ps |
| CPU time | 4368.05 seconds |
| Started | Jul 30 08:00:36 PM PDT 24 |
| Finished | Jul 30 09:13:24 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-8723c3b7-793e-4156-9715-0310dbfa094d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464271197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .rom_e2e_asm_init_dev.464271197 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.1281240224 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 14793246674 ps |
| CPU time | 4661.64 seconds |
| Started | Jul 30 08:00:44 PM PDT 24 |
| Finished | Jul 30 09:18:27 PM PDT 24 |
| Peak memory | 610552 kb |
| Host | smart-2549b74e-fd65-4b18-80a8-c8f34890dbd5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281240224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.1281240224 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2736114959 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 15055251251 ps |
| CPU time | 4309.44 seconds |
| Started | Jul 30 07:58:02 PM PDT 24 |
| Finished | Jul 30 09:09:52 PM PDT 24 |
| Peak memory | 610244 kb |
| Host | smart-c018b5c7-40a4-4bee-b43e-1b6c396c2ad2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736114959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.2736114959 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.1856084765 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 14989918596 ps |
| CPU time | 4390.62 seconds |
| Started | Jul 30 08:01:32 PM PDT 24 |
| Finished | Jul 30 09:14:44 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-dd27c113-9f64-419c-b7bc-7845b30f60e3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856084765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.1856084765 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1663346785 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 11889419167 ps |
| CPU time | 3301.29 seconds |
| Started | Jul 30 08:00:53 PM PDT 24 |
| Finished | Jul 30 08:55:55 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-05de286f-1687-4ece-a91a-43e4cde5dabb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663346785 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.1663346785 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3044277678 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 23887194928 ps |
| CPU time | 6840.87 seconds |
| Started | Jul 30 08:00:05 PM PDT 24 |
| Finished | Jul 30 09:54:07 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-c86f118f-65be-4a2e-8895-00682c99c8ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3044277678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3044277678 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3959449001 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 24777101956 ps |
| CPU time | 6319.09 seconds |
| Started | Jul 30 08:00:02 PM PDT 24 |
| Finished | Jul 30 09:45:24 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-0d74c0b8-fef6-4b94-bbdc-fa14afcb3c8c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3959449001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3959449001 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1016737008 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 22828601712 ps |
| CPU time | 6130.57 seconds |
| Started | Jul 30 08:01:05 PM PDT 24 |
| Finished | Jul 30 09:43:17 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-458b7209-dab8-4a43-a247-be023ac035c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1016737008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1016737008 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2274591693 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 18515644616 ps |
| CPU time | 5064.78 seconds |
| Started | Jul 30 08:00:17 PM PDT 24 |
| Finished | Jul 30 09:24:43 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-bcf7d315-131b-45c8-ba45-8374a84762be |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274591693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2274591693 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.819910483 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 15508646604 ps |
| CPU time | 4724.79 seconds |
| Started | Jul 30 08:00:07 PM PDT 24 |
| Finished | Jul 30 09:18:52 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-67fb1821-d275-4652-b93a-7553f6b2baf9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=819910483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.819910483 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3809435922 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 15677826220 ps |
| CPU time | 4326.55 seconds |
| Started | Jul 30 08:00:37 PM PDT 24 |
| Finished | Jul 30 09:12:44 PM PDT 24 |
| Peak memory | 609812 kb |
| Host | smart-3d487044-0577-4671-a269-317ac93195b7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3809435922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3809435922 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3778454935 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 15405044600 ps |
| CPU time | 4034.38 seconds |
| Started | Jul 30 07:59:57 PM PDT 24 |
| Finished | Jul 30 09:07:12 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-8794fc36-11f5-44d2-8e75-bc6beedd72b1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3778454935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3778454935 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.685051773 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 14713577400 ps |
| CPU time | 3977.77 seconds |
| Started | Jul 30 08:00:33 PM PDT 24 |
| Finished | Jul 30 09:06:52 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-2acbe7b5-a13a-4543-9bc8-b77fda250d23 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=685051773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.685051773 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3430653617 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 11706520952 ps |
| CPU time | 3327.05 seconds |
| Started | Jul 30 08:00:28 PM PDT 24 |
| Finished | Jul 30 08:55:56 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-2880ec26-cbfa-435f-bd98-8af389eb9019 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430653617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3430653617 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1095186207 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 15647732562 ps |
| CPU time | 5102.34 seconds |
| Started | Jul 30 08:00:02 PM PDT 24 |
| Finished | Jul 30 09:25:08 PM PDT 24 |
| Peak memory | 609252 kb |
| Host | smart-a22f15e3-7f88-4c68-89d0-e8787e532a60 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095186207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1095186207 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2743420990 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 15541921860 ps |
| CPU time | 4799.74 seconds |
| Started | Jul 30 07:57:11 PM PDT 24 |
| Finished | Jul 30 09:17:11 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-6c15e512-306e-4122-b376-c8e117d590ab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743420990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2743420990 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2306934312 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 15360759514 ps |
| CPU time | 4237 seconds |
| Started | Jul 30 07:59:07 PM PDT 24 |
| Finished | Jul 30 09:09:44 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-459d0a03-320a-41f8-ae8d-3897a800d93b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230693 4312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2306934312 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1089311618 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 15587270036 ps |
| CPU time | 4287.8 seconds |
| Started | Jul 30 08:00:15 PM PDT 24 |
| Finished | Jul 30 09:11:43 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-b667b311-e7ef-4c31-98c0-8d58025869a9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089311618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1089311618 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.218343861 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 11586748640 ps |
| CPU time | 3221.57 seconds |
| Started | Jul 30 07:58:37 PM PDT 24 |
| Finished | Jul 30 08:52:19 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-93e1a4d9-06d9-41bd-ac4b-863581815e49 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 218343861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.218343861 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.3449851400 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 11614845930 ps |
| CPU time | 2029.07 seconds |
| Started | Jul 30 07:54:55 PM PDT 24 |
| Finished | Jul 30 08:28:45 PM PDT 24 |
| Peak memory | 624576 kb |
| Host | smart-4df92918-3331-4f89-bb79-c1b4559d7020 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34498 51400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.3449851400 |
| Directory | /workspace/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.812485780 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 11658218069 ps |
| CPU time | 2394.75 seconds |
| Started | Jul 30 07:56:31 PM PDT 24 |
| Finished | Jul 30 08:36:26 PM PDT 24 |
| Peak memory | 624540 kb |
| Host | smart-7e07d43d-4915-4743-ad91-72080989b166 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81248 5780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.812485780 |
| Directory | /workspace/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3578967967 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 11281931878 ps |
| CPU time | 1945.91 seconds |
| Started | Jul 30 07:55:02 PM PDT 24 |
| Finished | Jul 30 08:27:29 PM PDT 24 |
| Peak memory | 624532 kb |
| Host | smart-60cb4c8e-8a48-4472-a552-267425cbe964 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3578967967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.3578967967 |
| Directory | /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3480226004 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 25564464050 ps |
| CPU time | 2618.33 seconds |
| Started | Jul 30 07:59:11 PM PDT 24 |
| Finished | Jul 30 08:42:50 PM PDT 24 |
| Peak memory | 620640 kb |
| Host | smart-4085aca0-96a1-4d33-a212-8c71b23f9e03 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3480226004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.3480226004 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.971667427 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 31617237908 ps |
| CPU time | 3644.26 seconds |
| Started | Jul 30 07:57:17 PM PDT 24 |
| Finished | Jul 30 08:58:02 PM PDT 24 |
| Peak memory | 621188 kb |
| Host | smart-3fb4a378-2969-4244-93d8-f51a071f35ad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=971667427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.971667427 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1798844433 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 34780255669 ps |
| CPU time | 2388.17 seconds |
| Started | Jul 30 07:57:02 PM PDT 24 |
| Finished | Jul 30 08:36:51 PM PDT 24 |
| Peak memory | 621544 kb |
| Host | smart-084ea20c-24e0-4ce8-b16f-a956f9855e80 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798844433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.1798844433 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1885089631 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 14817783664 ps |
| CPU time | 4520.85 seconds |
| Started | Jul 30 08:02:27 PM PDT 24 |
| Finished | Jul 30 09:17:48 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-866ed278-ba01-487e-b86d-2add0d10045d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885089631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1885089631 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1366244913 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 15481347616 ps |
| CPU time | 4017.72 seconds |
| Started | Jul 30 08:01:30 PM PDT 24 |
| Finished | Jul 30 09:08:28 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-0ee2232a-0a86-4f29-a3c7-f1b0e4d91a7e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366244913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.1366244913 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.400618881 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 14924330052 ps |
| CPU time | 4457.83 seconds |
| Started | Jul 30 08:01:22 PM PDT 24 |
| Finished | Jul 30 09:15:40 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-5c0887ff-bf92-497c-8e40-f691294a22bf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400618881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_ no_meas.400618881 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_self_hash.2021004998 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 26006213516 ps |
| CPU time | 6569.53 seconds |
| Started | Jul 30 07:58:31 PM PDT 24 |
| Finished | Jul 30 09:48:01 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-d1d91ecd-84c7-4249-b77d-6b17d9ccbfd2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021004998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.2021004998 |
| Directory | /workspace/0.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1926810437 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 14302376310 ps |
| CPU time | 3584.91 seconds |
| Started | Jul 30 07:58:05 PM PDT 24 |
| Finished | Jul 30 08:57:51 PM PDT 24 |
| Peak memory | 611656 kb |
| Host | smart-16870113-dfb7-4b2d-b53a-8ffae7eebdd1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926810437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.1926810437 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.1240950081 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 26495391146 ps |
| CPU time | 3522.74 seconds |
| Started | Jul 30 07:59:31 PM PDT 24 |
| Finished | Jul 30 08:58:14 PM PDT 24 |
| Peak memory | 611776 kb |
| Host | smart-8fbc4079-2948-4bd1-a0d0-cba7df55ebb1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240950081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.1240950081 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1725985408 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 23154571230 ps |
| CPU time | 5674.72 seconds |
| Started | Jul 30 07:58:20 PM PDT 24 |
| Finished | Jul 30 09:32:55 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-03fa88aa-a32c-4a54-92ce-ce189730e552 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1725985408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b ad_dev.1725985408 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2310640667 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 23773097147 ps |
| CPU time | 5813.68 seconds |
| Started | Jul 30 08:02:52 PM PDT 24 |
| Finished | Jul 30 09:39:46 PM PDT 24 |
| Peak memory | 609124 kb |
| Host | smart-73fe2c20-1bca-47d2-b637-6697d56f487e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2310640667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.2310640667 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.334191448 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 23598715990 ps |
| CPU time | 6736.92 seconds |
| Started | Jul 30 08:01:16 PM PDT 24 |
| Finished | Jul 30 09:53:34 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-c416c20c-7816-41b5-a220-66844237a88e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=334191448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_b ad_b_bad_prod_end.334191448 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.4093805203 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 23060131571 ps |
| CPU time | 6214.9 seconds |
| Started | Jul 30 08:00:27 PM PDT 24 |
| Finished | Jul 30 09:44:02 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-1e5ac7ab-c4f6-44df-a013-c93204103892 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=4093805203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_rma.4093805203 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1123645380 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 13881343025 ps |
| CPU time | 3830.91 seconds |
| Started | Jul 30 08:00:19 PM PDT 24 |
| Finished | Jul 30 09:04:11 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-5fb5e97c-2fe2-427f-9104-339ef7fc19cf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123645380 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1123645380 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3695321094 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 14812792288 ps |
| CPU time | 3136.9 seconds |
| Started | Jul 30 07:59:04 PM PDT 24 |
| Finished | Jul 30 08:51:22 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-06040d09-2cb5-492b-acfa-288a3fbac1d3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695321094 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3695321094 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1021944478 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 15002373048 ps |
| CPU time | 4136.31 seconds |
| Started | Jul 30 07:58:59 PM PDT 24 |
| Finished | Jul 30 09:07:56 PM PDT 24 |
| Peak memory | 609384 kb |
| Host | smart-e9cb0310-5d5f-4828-8c3e-788aa5d89bf1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021944478 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1021944478 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2531696515 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 14377628665 ps |
| CPU time | 4354.55 seconds |
| Started | Jul 30 07:59:50 PM PDT 24 |
| Finished | Jul 30 09:12:25 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-c08651ba-f81b-4ea3-a467-39d1085f6bb9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531696515 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2531696515 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1040144725 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 10971952256 ps |
| CPU time | 2877.77 seconds |
| Started | Jul 30 07:58:23 PM PDT 24 |
| Finished | Jul 30 08:46:21 PM PDT 24 |
| Peak memory | 610560 kb |
| Host | smart-07f1318a-e649-4995-8c44-3546088ca49c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040144725 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1040144725 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3362069337 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 15036349864 ps |
| CPU time | 4502.98 seconds |
| Started | Jul 30 08:00:31 PM PDT 24 |
| Finished | Jul 30 09:15:34 PM PDT 24 |
| Peak memory | 611136 kb |
| Host | smart-8c74bec8-9b44-4e54-9a9f-648394efc232 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362069337 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3362069337 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1223920745 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 14924784140 ps |
| CPU time | 3827.87 seconds |
| Started | Jul 30 07:57:51 PM PDT 24 |
| Finished | Jul 30 09:01:39 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-968c3b41-6fe8-4fe8-9c9b-3891f470eb43 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223920745 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1223920745 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1287190758 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 14526398144 ps |
| CPU time | 3895.76 seconds |
| Started | Jul 30 08:00:12 PM PDT 24 |
| Finished | Jul 30 09:05:08 PM PDT 24 |
| Peak memory | 609204 kb |
| Host | smart-f808ea50-8920-48c4-b5bf-e2c1f4d7a282 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287190758 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1287190758 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3408061763 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 14639219443 ps |
| CPU time | 3946.44 seconds |
| Started | Jul 30 08:00:50 PM PDT 24 |
| Finished | Jul 30 09:06:37 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-a1390bce-00b6-4dce-aeaf-662a222a56f9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408061763 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3408061763 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.631940387 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 10372923683 ps |
| CPU time | 3056.22 seconds |
| Started | Jul 30 08:00:21 PM PDT 24 |
| Finished | Jul 30 08:51:18 PM PDT 24 |
| Peak memory | 609440 kb |
| Host | smart-9006b8c4-3434-46eb-b7aa-5d3657d8ee3f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631940387 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.631940387 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.3020850829 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 15335667464 ps |
| CPU time | 4546.49 seconds |
| Started | Jul 30 07:57:18 PM PDT 24 |
| Finished | Jul 30 09:13:05 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-f499d710-8a98-4b60-9175-9553428743fe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=3020850829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.3020850829 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.548441906 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 17667382504 ps |
| CPU time | 4675.95 seconds |
| Started | Jul 30 08:02:29 PM PDT 24 |
| Finished | Jul 30 09:20:25 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-23b0058d-991e-46b9-a4fc-4e52be79a9f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548441906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.548441906 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.424699806 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 5503655432 ps |
| CPU time | 608.67 seconds |
| Started | Jul 30 07:55:32 PM PDT 24 |
| Finished | Jul 30 08:05:41 PM PDT 24 |
| Peak memory | 610560 kb |
| Host | smart-fc823a3c-b1fb-44d9-b239-268d7eb7cdf9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424699806 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.424699806 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_raw_unlock.3141185721 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 4138646491 ps |
| CPU time | 277.19 seconds |
| Started | Jul 30 07:57:43 PM PDT 24 |
| Finished | Jul 30 08:02:20 PM PDT 24 |
| Peak memory | 620124 kb |
| Host | smart-d02b8c24-1578-4a9c-a645-ab825f6b60be |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3141185721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.3141185721 |
| Directory | /workspace/0.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.2977034284 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 2393645540 ps |
| CPU time | 103.44 seconds |
| Started | Jul 30 07:58:11 PM PDT 24 |
| Finished | Jul 30 07:59:54 PM PDT 24 |
| Peak memory | 617532 kb |
| Host | smart-c46203dc-820a-41e5-9daf-63aeb3f62649 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977034284 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.2977034284 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.4251839535 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 13393328760 ps |
| CPU time | 1424.73 seconds |
| Started | Jul 30 07:57:17 PM PDT 24 |
| Finished | Jul 30 08:21:02 PM PDT 24 |
| Peak memory | 607944 kb |
| Host | smart-35602327-1956-4e78-8537-b690c8f8cbdb |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251839535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.4 251839535 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.580982227 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 3922430016 ps |
| CPU time | 359.69 seconds |
| Started | Jul 30 08:04:32 PM PDT 24 |
| Finished | Jul 30 08:10:33 PM PDT 24 |
| Peak memory | 620052 kb |
| Host | smart-49907fac-7cff-46ff-b897-2f4dbaf5c306 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5 80982227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.580982227 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.1572102509 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 3410004348 ps |
| CPU time | 288.18 seconds |
| Started | Jul 30 07:54:44 PM PDT 24 |
| Finished | Jul 30 07:59:32 PM PDT 24 |
| Peak memory | 609912 kb |
| Host | smart-75fc5a4e-9b1f-4833-bb03-dfaf874350ee |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1572102509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.1572102509 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.362178176 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 19145660968 ps |
| CPU time | 495.68 seconds |
| Started | Jul 30 07:59:49 PM PDT 24 |
| Finished | Jul 30 08:08:05 PM PDT 24 |
| Peak memory | 618600 kb |
| Host | smart-7e5f1c3a-b435-46a3-8f6c-a297cfac3b64 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=362178176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.362178176 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.473590707 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 3566804226 ps |
| CPU time | 330.26 seconds |
| Started | Jul 30 08:01:50 PM PDT 24 |
| Finished | Jul 30 08:07:21 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-a7ad2b6e-1740-4d84-9e42-ccc0bf13f5e4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473590707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.473590707 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.4182314354 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 2446211550 ps |
| CPU time | 277.13 seconds |
| Started | Jul 30 08:01:48 PM PDT 24 |
| Finished | Jul 30 08:06:25 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-559d064c-c451-4694-84a4-79df0db30d1d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182 314354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.4182314354 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2747635101 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 3234630399 ps |
| CPU time | 239.55 seconds |
| Started | Jul 30 08:05:09 PM PDT 24 |
| Finished | Jul 30 08:09:09 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-a1aab89f-f410-4627-855d-a5707ffd63a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747635101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.2747635101 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.2285699995 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 2983040328 ps |
| CPU time | 286.7 seconds |
| Started | Jul 30 08:02:57 PM PDT 24 |
| Finished | Jul 30 08:07:44 PM PDT 24 |
| Peak memory | 609620 kb |
| Host | smart-e2cf6489-71e6-49b0-a65e-fec181fee96d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285699995 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.2285699995 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.1259371524 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 2592740228 ps |
| CPU time | 254.58 seconds |
| Started | Jul 30 08:02:41 PM PDT 24 |
| Finished | Jul 30 08:06:56 PM PDT 24 |
| Peak memory | 609560 kb |
| Host | smart-c574f609-e1a1-4d06-add3-1684c07db7b1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259371524 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.1259371524 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.2792292936 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 2856399777 ps |
| CPU time | 229.81 seconds |
| Started | Jul 30 08:00:05 PM PDT 24 |
| Finished | Jul 30 08:03:55 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-80ef5f07-4780-40e7-86be-8f3e57d631c8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792292936 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.2792292936 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.2010565090 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 2789267972 ps |
| CPU time | 301.38 seconds |
| Started | Jul 30 08:05:56 PM PDT 24 |
| Finished | Jul 30 08:10:58 PM PDT 24 |
| Peak memory | 609564 kb |
| Host | smart-0bb1a0c5-df49-4658-99eb-01049b8cee94 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010565090 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.2010565090 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.1886019301 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 3106022330 ps |
| CPU time | 349.9 seconds |
| Started | Jul 30 08:00:12 PM PDT 24 |
| Finished | Jul 30 08:06:02 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-c957a5b7-e24c-4ef5-8249-098d0edfd1b5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1886019301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.1886019301 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.403949104 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 5334162936 ps |
| CPU time | 474.23 seconds |
| Started | Jul 30 08:01:39 PM PDT 24 |
| Finished | Jul 30 08:09:34 PM PDT 24 |
| Peak memory | 619412 kb |
| Host | smart-a42084ab-5f85-44ff-91a7-2254fd71cbf2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=403949104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.403949104 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.206729005 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 5645240856 ps |
| CPU time | 1080.41 seconds |
| Started | Jul 30 08:00:46 PM PDT 24 |
| Finished | Jul 30 08:18:46 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-8b13507e-a753-4e36-8132-567121cb3af7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=206729005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.206729005 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1097435761 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 6500014500 ps |
| CPU time | 1484.88 seconds |
| Started | Jul 30 07:59:36 PM PDT 24 |
| Finished | Jul 30 08:24:21 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-3a69e71e-8656-469e-a5bc-26666926b129 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097435761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.1097435761 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3464001784 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 13495882690 ps |
| CPU time | 1454.25 seconds |
| Started | Jul 30 08:00:15 PM PDT 24 |
| Finished | Jul 30 08:24:30 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-32001619-c6bd-4677-9be0-b5f808d9b672 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464001784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.3464001784 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3277417032 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 7445200328 ps |
| CPU time | 1137.77 seconds |
| Started | Jul 30 08:00:52 PM PDT 24 |
| Finished | Jul 30 08:19:51 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-00ea6d21-e9b0-4ed8-8679-1aa70d2d3dc4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3277417032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.3277417032 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.307508861 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 2897487952 ps |
| CPU time | 298.77 seconds |
| Started | Jul 30 08:02:57 PM PDT 24 |
| Finished | Jul 30 08:07:56 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-06ae5254-37b6-4699-bcd8-222b2b6ad20e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=307508861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.307508861 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1413988488 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 255753946254 ps |
| CPU time | 12715.3 seconds |
| Started | Jul 30 08:01:07 PM PDT 24 |
| Finished | Jul 30 11:33:04 PM PDT 24 |
| Peak memory | 610768 kb |
| Host | smart-4ed62a24-6c04-4e4f-9b36-2a391badf788 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1413988488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1413988488 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.2946652333 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 3604881960 ps |
| CPU time | 416.75 seconds |
| Started | Jul 30 07:59:19 PM PDT 24 |
| Finished | Jul 30 08:06:15 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-7fb4adad-f679-438d-8640-872f565e41cb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946652333 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.2946652333 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2321373310 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 7821829424 ps |
| CPU time | 601.05 seconds |
| Started | Jul 30 08:01:41 PM PDT 24 |
| Finished | Jul 30 08:11:42 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-16509813-9b38-4e15-9852-f1cb8a5c0dc5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2321373310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2321373310 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3479105774 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 2941164600 ps |
| CPU time | 324.37 seconds |
| Started | Jul 30 08:08:13 PM PDT 24 |
| Finished | Jul 30 08:13:38 PM PDT 24 |
| Peak memory | 609608 kb |
| Host | smart-93cc250a-4215-468f-a380-db0ab400f4c9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479105774 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.3479105774 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.618579872 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 8435893114 ps |
| CPU time | 969.17 seconds |
| Started | Jul 30 08:04:36 PM PDT 24 |
| Finished | Jul 30 08:20:45 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-adde6dc3-9a7d-4b5a-a7f6-fd0db79da6ef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 618579872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.618579872 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.254408868 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 5077073040 ps |
| CPU time | 737.81 seconds |
| Started | Jul 30 07:59:40 PM PDT 24 |
| Finished | Jul 30 08:11:58 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-63473930-b968-4c91-99b8-2e7216879290 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =254408868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.254408868 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.3894046188 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 7755974130 ps |
| CPU time | 863.7 seconds |
| Started | Jul 30 08:04:31 PM PDT 24 |
| Finished | Jul 30 08:18:56 PM PDT 24 |
| Peak memory | 617004 kb |
| Host | smart-3889fd68-7ed4-4f98-96e5-18641ed096cb |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894046188 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.3894046188 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.32307924 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 4202180840 ps |
| CPU time | 657.32 seconds |
| Started | Jul 30 08:03:19 PM PDT 24 |
| Finished | Jul 30 08:14:16 PM PDT 24 |
| Peak memory | 612788 kb |
| Host | smart-b01a3357-032a-4e18-9b0e-2fa898236344 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32307924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clk mgr_external_clk_src_for_sw_fast_dev.32307924 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3527543665 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 4618630092 ps |
| CPU time | 690.39 seconds |
| Started | Jul 30 08:04:27 PM PDT 24 |
| Finished | Jul 30 08:15:58 PM PDT 24 |
| Peak memory | 612084 kb |
| Host | smart-12649843-5ba5-4700-9309-e2f7bf274559 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527543665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3527543665 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1779997224 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 4614563872 ps |
| CPU time | 818.1 seconds |
| Started | Jul 30 08:04:08 PM PDT 24 |
| Finished | Jul 30 08:17:46 PM PDT 24 |
| Peak memory | 613160 kb |
| Host | smart-c7c65e65-8fa5-4efd-9dc9-108365edbc9b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779997224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1779997224 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.45615203 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 5087940886 ps |
| CPU time | 571.81 seconds |
| Started | Jul 30 08:04:14 PM PDT 24 |
| Finished | Jul 30 08:13:46 PM PDT 24 |
| Peak memory | 613128 kb |
| Host | smart-592ed3c7-3236-4628-b087-2c0cb5b5b152 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45615203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clk mgr_external_clk_src_for_sw_slow_dev.45615203 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.383926996 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 5185669846 ps |
| CPU time | 590.25 seconds |
| Started | Jul 30 08:04:45 PM PDT 24 |
| Finished | Jul 30 08:14:35 PM PDT 24 |
| Peak memory | 612092 kb |
| Host | smart-77b4254c-5805-44f8-b6e2-2d215e8120bd |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383926996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.383926996 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2278568187 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 4731025536 ps |
| CPU time | 786.93 seconds |
| Started | Jul 30 08:03:35 PM PDT 24 |
| Finished | Jul 30 08:16:42 PM PDT 24 |
| Peak memory | 613220 kb |
| Host | smart-239462d8-4c13-4eab-a117-a730921f3e01 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278568187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2278568187 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.1058915236 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 2791462267 ps |
| CPU time | 306.1 seconds |
| Started | Jul 30 08:04:45 PM PDT 24 |
| Finished | Jul 30 08:09:52 PM PDT 24 |
| Peak memory | 609636 kb |
| Host | smart-247ea06f-e7de-451f-bd17-158ca2458b6b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058915236 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.1058915236 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1581266407 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 3506206880 ps |
| CPU time | 459.02 seconds |
| Started | Jul 30 08:03:22 PM PDT 24 |
| Finished | Jul 30 08:11:01 PM PDT 24 |
| Peak memory | 609200 kb |
| Host | smart-c473e02d-0243-4f9a-9a76-b1a6d57d54e7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581266407 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.1581266407 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.403359371 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 2704425735 ps |
| CPU time | 233.6 seconds |
| Started | Jul 30 08:07:26 PM PDT 24 |
| Finished | Jul 30 08:11:20 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-a97ceb52-90db-42a6-b3df-9438b25e3cdf |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403359371 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.403359371 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1863638157 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 5045043280 ps |
| CPU time | 568.17 seconds |
| Started | Jul 30 08:03:48 PM PDT 24 |
| Finished | Jul 30 08:13:16 PM PDT 24 |
| Peak memory | 610472 kb |
| Host | smart-55a8eb8d-132c-4287-8612-6ed8eef17a3a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863638157 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.1863638157 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2189656922 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 5105615638 ps |
| CPU time | 454.74 seconds |
| Started | Jul 30 08:04:18 PM PDT 24 |
| Finished | Jul 30 08:11:53 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-5ba33b98-917d-4cd0-a36c-7eb9058d6759 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189656922 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.2189656922 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1885235163 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 5227873450 ps |
| CPU time | 363.32 seconds |
| Started | Jul 30 08:05:12 PM PDT 24 |
| Finished | Jul 30 08:11:16 PM PDT 24 |
| Peak memory | 610420 kb |
| Host | smart-b4fa8828-01c0-4fe4-b4d3-67b65073c046 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885235163 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.1885235163 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.575095206 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 4628187850 ps |
| CPU time | 482.23 seconds |
| Started | Jul 30 08:05:15 PM PDT 24 |
| Finished | Jul 30 08:13:18 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-9d8552cd-a523-48ab-a812-6e1093f2d159 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575095206 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.575095206 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3030016911 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 10379179742 ps |
| CPU time | 1445.54 seconds |
| Started | Jul 30 08:04:58 PM PDT 24 |
| Finished | Jul 30 08:29:04 PM PDT 24 |
| Peak memory | 610448 kb |
| Host | smart-549713a8-ce62-4fd3-9dc7-bae229f06bda |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030016911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.3030016911 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.260724673 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 4016534334 ps |
| CPU time | 490.76 seconds |
| Started | Jul 30 08:04:06 PM PDT 24 |
| Finished | Jul 30 08:12:17 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-56d12c0f-f7db-48a6-b5e3-46e61b1a356e |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260724673 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.260724673 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.429724177 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 4851978008 ps |
| CPU time | 662.99 seconds |
| Started | Jul 30 08:03:36 PM PDT 24 |
| Finished | Jul 30 08:14:39 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-85081dea-bde0-4e07-8808-46bce9c05cae |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429724177 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.429724177 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2598573620 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 2822409960 ps |
| CPU time | 368.6 seconds |
| Started | Jul 30 08:08:23 PM PDT 24 |
| Finished | Jul 30 08:14:32 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-4b657da0-fc53-441c-83b6-5ba83f891dea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598573620 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.2598573620 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2149109329 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 15842115888 ps |
| CPU time | 5126.02 seconds |
| Started | Jul 30 08:02:12 PM PDT 24 |
| Finished | Jul 30 09:27:39 PM PDT 24 |
| Peak memory | 610332 kb |
| Host | smart-dee6b0a8-669d-407b-960f-8a9a77934a0f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149109329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.2149109329 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.4215560664 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 23655077896 ps |
| CPU time | 4942.56 seconds |
| Started | Jul 30 08:07:55 PM PDT 24 |
| Finished | Jul 30 09:30:18 PM PDT 24 |
| Peak memory | 610208 kb |
| Host | smart-f5901168-238d-4422-b8f4-b6c753dce90b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4215560664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.4215560664 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2658107210 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 4038074244 ps |
| CPU time | 351.25 seconds |
| Started | Jul 30 08:01:43 PM PDT 24 |
| Finished | Jul 30 08:07:35 PM PDT 24 |
| Peak memory | 610472 kb |
| Host | smart-257e2022-ec8a-4493-995e-e8d5a4974e2c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26581 07210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.2658107210 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.4125834949 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 2889491594 ps |
| CPU time | 298.28 seconds |
| Started | Jul 30 08:02:29 PM PDT 24 |
| Finished | Jul 30 08:07:28 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-e93805f0-6090-4035-8da6-9439a9e24982 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125834949 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.4125834949 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.3250338158 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 2386004200 ps |
| CPU time | 168.87 seconds |
| Started | Jul 30 08:06:59 PM PDT 24 |
| Finished | Jul 30 08:09:48 PM PDT 24 |
| Peak memory | 609544 kb |
| Host | smart-8307c54f-9f05-45d3-a581-f1d6077fddec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250338158 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.3250338158 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.2241767384 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 5625268256 ps |
| CPU time | 887.87 seconds |
| Started | Jul 30 07:58:55 PM PDT 24 |
| Finished | Jul 30 08:13:44 PM PDT 24 |
| Peak memory | 610872 kb |
| Host | smart-c3f56c18-da01-4501-97fa-887bc5de2bd4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2241767384 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.2241767384 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.3532492862 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 3197887540 ps |
| CPU time | 701.75 seconds |
| Started | Jul 30 08:01:21 PM PDT 24 |
| Finished | Jul 30 08:13:03 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-7bd728c0-1e31-4358-aee6-c6bd265ac811 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532492862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.3532492862 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.117266521 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 6792488714 ps |
| CPU time | 1423.19 seconds |
| Started | Jul 30 08:04:27 PM PDT 24 |
| Finished | Jul 30 08:28:11 PM PDT 24 |
| Peak memory | 610936 kb |
| Host | smart-c047159f-492e-40b6-82fe-0033d7074576 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117266521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.117266521 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.2451302426 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 3444872442 ps |
| CPU time | 657.05 seconds |
| Started | Jul 30 08:02:00 PM PDT 24 |
| Finished | Jul 30 08:12:57 PM PDT 24 |
| Peak memory | 615588 kb |
| Host | smart-1204a68e-825c-4e19-adf0-c2c47683e2b1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451302426 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.2451302426 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.2682489221 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 9500268296 ps |
| CPU time | 2497.7 seconds |
| Started | Jul 30 08:02:12 PM PDT 24 |
| Finished | Jul 30 08:43:51 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-b3370934-2c42-4382-b4e5-565f5a412823 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682489221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.2682489221 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2926678275 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3240909496 ps |
| CPU time | 300.87 seconds |
| Started | Jul 30 08:01:56 PM PDT 24 |
| Finished | Jul 30 08:06:58 PM PDT 24 |
| Peak memory | 609740 kb |
| Host | smart-cf23d5c4-21a2-4b40-9743-8e6351c5366e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29 26678275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.2926678275 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2432927731 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 3485250042 ps |
| CPU time | 251.35 seconds |
| Started | Jul 30 08:00:40 PM PDT 24 |
| Finished | Jul 30 08:04:51 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-151ec8c1-97f4-4a11-a2f5-adb7bb771416 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432927731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.2432927731 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1290720732 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 3271160024 ps |
| CPU time | 447.76 seconds |
| Started | Jul 30 08:06:54 PM PDT 24 |
| Finished | Jul 30 08:14:22 PM PDT 24 |
| Peak memory | 609652 kb |
| Host | smart-f0ad2135-df93-4bbb-8f5f-429d9877c06e |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1290720732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.1290720732 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.1046045698 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 2971968840 ps |
| CPU time | 234.2 seconds |
| Started | Jul 30 07:55:37 PM PDT 24 |
| Finished | Jul 30 07:59:32 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-f060b223-a117-4339-a28d-3197150c34da |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046045698 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.1046045698 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.946741138 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 2816606756 ps |
| CPU time | 245.54 seconds |
| Started | Jul 30 07:56:03 PM PDT 24 |
| Finished | Jul 30 08:00:09 PM PDT 24 |
| Peak memory | 609564 kb |
| Host | smart-eefe9d3d-73cf-4d20-bdcb-ebcc5f968bc0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946741138 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.946741138 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.3703690460 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 3157693400 ps |
| CPU time | 264.85 seconds |
| Started | Jul 30 07:55:49 PM PDT 24 |
| Finished | Jul 30 08:00:14 PM PDT 24 |
| Peak memory | 609572 kb |
| Host | smart-1f91bf20-46b6-4a01-8bba-7a9058b86c81 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703690460 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.3703690460 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.1793495815 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 2275066478 ps |
| CPU time | 132.08 seconds |
| Started | Jul 30 07:53:59 PM PDT 24 |
| Finished | Jul 30 07:56:12 PM PDT 24 |
| Peak memory | 610112 kb |
| Host | smart-cb5b3f3b-244a-43c8-8075-ff6f16909fd9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793495815 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.1793495815 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2502932829 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 58123875736 ps |
| CPU time | 11656.2 seconds |
| Started | Jul 30 07:57:37 PM PDT 24 |
| Finished | Jul 30 11:11:55 PM PDT 24 |
| Peak memory | 624740 kb |
| Host | smart-d521fcf5-4c6b-48a4-a0a4-c6023612ec36 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2502932829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.2502932829 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.4019947623 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 5412451190 ps |
| CPU time | 575.97 seconds |
| Started | Jul 30 08:05:12 PM PDT 24 |
| Finished | Jul 30 08:14:49 PM PDT 24 |
| Peak memory | 611212 kb |
| Host | smart-c3d627ae-bbc9-4e96-b627-7c836730ff47 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=4019947623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.4019947623 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.2774538657 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 5848902248 ps |
| CPU time | 1158.38 seconds |
| Started | Jul 30 07:56:27 PM PDT 24 |
| Finished | Jul 30 08:15:46 PM PDT 24 |
| Peak memory | 608824 kb |
| Host | smart-d05a435b-f10d-4816-92dd-1cda88dd2183 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774538657 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.2774538657 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2316349462 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 6404732192 ps |
| CPU time | 1108.75 seconds |
| Started | Jul 30 07:56:42 PM PDT 24 |
| Finished | Jul 30 08:15:11 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-59afb35e-5a2b-4c6b-94c4-281d64646d45 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316349462 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.2316349462 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1427036353 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 7081648521 ps |
| CPU time | 1351.33 seconds |
| Started | Jul 30 08:04:52 PM PDT 24 |
| Finished | Jul 30 08:27:24 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-1fb01441-6383-4f83-8334-506c290add1a |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427036353 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1427036353 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2968014894 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 5614519479 ps |
| CPU time | 1227.79 seconds |
| Started | Jul 30 07:59:35 PM PDT 24 |
| Finished | Jul 30 08:20:03 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-78bef83f-370c-4b7d-8265-646eefb4a529 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968014894 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.2968014894 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.818113049 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 3972587750 ps |
| CPU time | 395.27 seconds |
| Started | Jul 30 07:57:32 PM PDT 24 |
| Finished | Jul 30 08:04:07 PM PDT 24 |
| Peak memory | 609508 kb |
| Host | smart-f3ebc3a5-794d-4d5e-b9bf-33377a9f1f91 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818113049 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.818113049 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1410435033 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 5013719548 ps |
| CPU time | 522.01 seconds |
| Started | Jul 30 07:56:54 PM PDT 24 |
| Finished | Jul 30 08:05:36 PM PDT 24 |
| Peak memory | 610924 kb |
| Host | smart-53188716-4cc6-4549-a975-8063b327b4e9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14 10435033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.1410435033 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3150438602 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 5815765970 ps |
| CPU time | 1287 seconds |
| Started | Jul 30 08:06:11 PM PDT 24 |
| Finished | Jul 30 08:27:38 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-ce3950a6-43a0-4c1b-9b02-2ff42deffac5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150438602 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.3150438602 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2625890781 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 4338252888 ps |
| CPU time | 716.18 seconds |
| Started | Jul 30 07:57:39 PM PDT 24 |
| Finished | Jul 30 08:09:36 PM PDT 24 |
| Peak memory | 610184 kb |
| Host | smart-d2f74ca1-57ad-4231-98b9-41e60becc591 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625890781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.2625890781 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1552277126 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 4105225690 ps |
| CPU time | 748.02 seconds |
| Started | Jul 30 08:01:26 PM PDT 24 |
| Finished | Jul 30 08:13:55 PM PDT 24 |
| Peak memory | 609888 kb |
| Host | smart-0d863261-eb08-4b9c-b117-dcd9ae272808 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1552277126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.1552277126 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2539915412 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 5256062790 ps |
| CPU time | 673.01 seconds |
| Started | Jul 30 08:06:40 PM PDT 24 |
| Finished | Jul 30 08:17:53 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-43b5bce7-c42c-48cd-8975-186479294d8e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2539915412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2539915412 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2913704280 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 3300112722 ps |
| CPU time | 373.73 seconds |
| Started | Jul 30 08:06:33 PM PDT 24 |
| Finished | Jul 30 08:12:47 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-5f884b27-9662-479e-8fc2-e5af8365bcff |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913704 280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.2913704280 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.391467507 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 23339818346 ps |
| CPU time | 2804.69 seconds |
| Started | Jul 30 07:57:36 PM PDT 24 |
| Finished | Jul 30 08:44:21 PM PDT 24 |
| Peak memory | 616476 kb |
| Host | smart-89a00fe2-285c-4a06-8abd-02c40f2628e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391467507 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.391467507 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1461662811 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 25497708170 ps |
| CPU time | 2061.54 seconds |
| Started | Jul 30 08:04:42 PM PDT 24 |
| Finished | Jul 30 08:39:04 PM PDT 24 |
| Peak memory | 611528 kb |
| Host | smart-6191e1c4-479c-4e2f-acdf-6571277c09c7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1461662811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.1461662811 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.4051037439 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 2867297872 ps |
| CPU time | 293.77 seconds |
| Started | Jul 30 08:09:56 PM PDT 24 |
| Finished | Jul 30 08:14:50 PM PDT 24 |
| Peak memory | 609628 kb |
| Host | smart-104db310-ee4b-41bd-86d2-72bb72d3f6da |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4051037439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.4051037439 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.4077689761 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4225996420 ps |
| CPU time | 450.93 seconds |
| Started | Jul 30 07:58:24 PM PDT 24 |
| Finished | Jul 30 08:05:56 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-65668494-5c2f-4558-9f6d-4b9e8f56d760 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077689761 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.4077689761 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.2862184994 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 3259649046 ps |
| CPU time | 305.45 seconds |
| Started | Jul 30 08:08:21 PM PDT 24 |
| Finished | Jul 30 08:13:27 PM PDT 24 |
| Peak memory | 608900 kb |
| Host | smart-e5b1f104-3155-4d8f-b30d-214cab8956a1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862184994 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.2862184994 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.3180125344 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 2849443642 ps |
| CPU time | 225.73 seconds |
| Started | Jul 30 08:03:06 PM PDT 24 |
| Finished | Jul 30 08:06:52 PM PDT 24 |
| Peak memory | 608704 kb |
| Host | smart-56b44598-6bdd-484d-8756-6fb1bc4231b3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180125344 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.3180125344 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.54276398 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 3405537128 ps |
| CPU time | 296.2 seconds |
| Started | Jul 30 08:03:51 PM PDT 24 |
| Finished | Jul 30 08:08:47 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-10bac165-3d30-42ae-8af4-44abf8c38a5e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54276398 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_hmac_enc_idle.54276398 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1088567968 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 3004119018 ps |
| CPU time | 279.05 seconds |
| Started | Jul 30 08:01:55 PM PDT 24 |
| Finished | Jul 30 08:06:34 PM PDT 24 |
| Peak memory | 609748 kb |
| Host | smart-891656f5-413b-4018-9f8c-a313105bde89 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088567968 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.1088567968 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.523224914 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 2832091681 ps |
| CPU time | 251.18 seconds |
| Started | Jul 30 08:05:24 PM PDT 24 |
| Finished | Jul 30 08:09:35 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-559bfe1b-32d4-4c56-bc4f-42f531da910a |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523224914 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.523224914 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.1359093280 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 8307112312 ps |
| CPU time | 1828.29 seconds |
| Started | Jul 30 08:02:15 PM PDT 24 |
| Finished | Jul 30 08:32:44 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-e8370ac7-c81d-41f4-964b-bec618327f71 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359093280 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_multistream.1359093280 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.981275999 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 2796162642 ps |
| CPU time | 240.92 seconds |
| Started | Jul 30 08:02:56 PM PDT 24 |
| Finished | Jul 30 08:06:57 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-5e8d433c-e160-4b3b-8fbe-43821459e1e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981275999 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.981275999 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.2588347721 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 3447004520 ps |
| CPU time | 394.15 seconds |
| Started | Jul 30 08:06:49 PM PDT 24 |
| Finished | Jul 30 08:13:23 PM PDT 24 |
| Peak memory | 608404 kb |
| Host | smart-12263878-2020-47ad-8ef4-a392a82f4f58 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588347721 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.2588347721 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1919486265 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 4228162360 ps |
| CPU time | 664.6 seconds |
| Started | Jul 30 07:58:10 PM PDT 24 |
| Finished | Jul 30 08:09:16 PM PDT 24 |
| Peak memory | 609472 kb |
| Host | smart-8211cc80-d47a-4f95-8fcf-4aa0f7ec46f1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919486265 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.1919486265 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1610418562 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 5378430530 ps |
| CPU time | 871.19 seconds |
| Started | Jul 30 07:58:33 PM PDT 24 |
| Finished | Jul 30 08:13:05 PM PDT 24 |
| Peak memory | 609228 kb |
| Host | smart-d218f56f-ecd6-48ba-95be-a2e57bb5763b |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610418562 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.1610418562 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3142429718 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 5050975752 ps |
| CPU time | 838.73 seconds |
| Started | Jul 30 07:59:21 PM PDT 24 |
| Finished | Jul 30 08:13:20 PM PDT 24 |
| Peak memory | 609260 kb |
| Host | smart-e0d3700b-3c39-4379-b2ed-1f14813f4b7e |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142429718 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.3142429718 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1089400871 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 4777771912 ps |
| CPU time | 786.47 seconds |
| Started | Jul 30 07:58:27 PM PDT 24 |
| Finished | Jul 30 08:11:34 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-d22c2055-0b91-4d8a-995b-6045151187ca |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089400871 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.1089400871 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.1212319406 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 65148700492 ps |
| CPU time | 12215.7 seconds |
| Started | Jul 30 07:56:19 PM PDT 24 |
| Finished | Jul 30 11:19:56 PM PDT 24 |
| Peak memory | 624716 kb |
| Host | smart-610486c6-4d98-4a7e-a4a6-9f6810e4750d |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1212319406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.1212319406 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.917850533 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 7801958296 ps |
| CPU time | 1317.55 seconds |
| Started | Jul 30 08:01:39 PM PDT 24 |
| Finished | Jul 30 08:23:37 PM PDT 24 |
| Peak memory | 616584 kb |
| Host | smart-1c4c22a2-32dd-4f26-8905-a859e20f19d6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9178 50533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.917850533 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.35985228 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 12347828769 ps |
| CPU time | 2289.15 seconds |
| Started | Jul 30 08:01:55 PM PDT 24 |
| Finished | Jul 30 08:40:04 PM PDT 24 |
| Peak memory | 618244 kb |
| Host | smart-127e8883-48d5-4323-9bbb-7b4b4893b1ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=35985228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.35985228 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.900412351 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 12418212210 ps |
| CPU time | 2089.21 seconds |
| Started | Jul 30 08:05:40 PM PDT 24 |
| Finished | Jul 30 08:40:30 PM PDT 24 |
| Peak memory | 617160 kb |
| Host | smart-07527a7d-825c-4528-b1ab-49ae1305e77d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=900412351 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en_ reduced_freq.900412351 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3309845348 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 7374567860 ps |
| CPU time | 1888.32 seconds |
| Started | Jul 30 08:04:40 PM PDT 24 |
| Finished | Jul 30 08:36:09 PM PDT 24 |
| Peak memory | 616868 kb |
| Host | smart-dae0259c-e771-4493-9e09-4e57feb22679 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3309845348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.3309845348 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2944535728 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 11587950388 ps |
| CPU time | 2462.74 seconds |
| Started | Jul 30 08:03:05 PM PDT 24 |
| Finished | Jul 30 08:44:08 PM PDT 24 |
| Peak memory | 611016 kb |
| Host | smart-c37547dc-c3d3-4c7b-8183-27b4713f3ea6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294453 5728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.2944535728 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2466819084 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 9485867772 ps |
| CPU time | 1688.71 seconds |
| Started | Jul 30 08:02:52 PM PDT 24 |
| Finished | Jul 30 08:31:01 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-c54faf14-a362-479d-8064-fad4e46adb95 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24668 19084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.2466819084 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.37243580 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 17132027836 ps |
| CPU time | 4326.41 seconds |
| Started | Jul 30 08:02:16 PM PDT 24 |
| Finished | Jul 30 09:14:23 PM PDT 24 |
| Peak memory | 610948 kb |
| Host | smart-7e5b2a01-8807-4c67-bce5-ad6ed08f9c5b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37243 580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.37243580 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.2156342727 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 2594944968 ps |
| CPU time | 198.06 seconds |
| Started | Jul 30 08:03:14 PM PDT 24 |
| Finished | Jul 30 08:06:33 PM PDT 24 |
| Peak memory | 608360 kb |
| Host | smart-03ed655a-bc05-4940-8e33-79bf994579c4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156342727 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.2156342727 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.193739302 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 3142786740 ps |
| CPU time | 237.65 seconds |
| Started | Jul 30 07:56:45 PM PDT 24 |
| Finished | Jul 30 08:00:43 PM PDT 24 |
| Peak memory | 609668 kb |
| Host | smart-ef224149-2c90-421e-b7c4-42f9dd805a3c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193739302 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_kmac_entropy.193739302 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.3840351092 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 2830619500 ps |
| CPU time | 227.88 seconds |
| Started | Jul 30 08:02:43 PM PDT 24 |
| Finished | Jul 30 08:06:31 PM PDT 24 |
| Peak memory | 608416 kb |
| Host | smart-9b6e64a3-8ec2-4462-84f5-adf3847a4b8d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840351092 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.3840351092 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3799213214 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 3544803170 ps |
| CPU time | 240.25 seconds |
| Started | Jul 30 08:03:27 PM PDT 24 |
| Finished | Jul 30 08:07:27 PM PDT 24 |
| Peak memory | 608388 kb |
| Host | smart-9472e503-f3e2-4c55-8b0c-0ef2310a4485 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799213214 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.3799213214 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3429356770 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 3220270280 ps |
| CPU time | 252.62 seconds |
| Started | Jul 30 08:04:21 PM PDT 24 |
| Finished | Jul 30 08:08:34 PM PDT 24 |
| Peak memory | 609596 kb |
| Host | smart-9448b621-e681-4e36-a0d5-13abedeefdb0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429356770 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.3429356770 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.4046025189 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 3614397836 ps |
| CPU time | 296.74 seconds |
| Started | Jul 30 08:02:53 PM PDT 24 |
| Finished | Jul 30 08:07:50 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-f2007684-fb15-4094-bb8d-4127697dcbef |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046025189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.4046025189 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1938006928 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 3160272227 ps |
| CPU time | 277.93 seconds |
| Started | Jul 30 08:04:37 PM PDT 24 |
| Finished | Jul 30 08:09:15 PM PDT 24 |
| Peak memory | 609708 kb |
| Host | smart-67d8a6a2-bbef-45c6-9611-d601e400ee75 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19380069 28 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1938006928 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.894786564 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 3306191080 ps |
| CPU time | 317 seconds |
| Started | Jul 30 08:06:53 PM PDT 24 |
| Finished | Jul 30 08:12:10 PM PDT 24 |
| Peak memory | 609608 kb |
| Host | smart-6f91b100-9ea9-47d6-9c23-bdcacfefbe0a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894786564 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_smoketest.894786564 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1726938920 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 2943070570 ps |
| CPU time | 292.08 seconds |
| Started | Jul 30 07:58:06 PM PDT 24 |
| Finished | Jul 30 08:02:58 PM PDT 24 |
| Peak memory | 609580 kb |
| Host | smart-c7c75099-659d-438d-9b43-9fc07471c7b3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726938920 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.1726938920 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.1268521303 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 5223051864 ps |
| CPU time | 375.92 seconds |
| Started | Jul 30 08:04:11 PM PDT 24 |
| Finished | Jul 30 08:10:27 PM PDT 24 |
| Peak memory | 610840 kb |
| Host | smart-936a77b2-0d7d-425f-b04f-da7ef7c25c87 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1268521303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.1268521303 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2198241140 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 3644931143 ps |
| CPU time | 252.5 seconds |
| Started | Jul 30 08:01:34 PM PDT 24 |
| Finished | Jul 30 08:05:47 PM PDT 24 |
| Peak memory | 621256 kb |
| Host | smart-8f1b4d3a-d0de-41f1-89fa-fea2de4635bc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21982411 40 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.2198241140 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3895848220 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 12496442293 ps |
| CPU time | 777.49 seconds |
| Started | Jul 30 07:57:47 PM PDT 24 |
| Finished | Jul 30 08:10:45 PM PDT 24 |
| Peak memory | 624768 kb |
| Host | smart-0779a8f6-c2ed-4d70-b824-c7263e3546d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895848220 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.3895848220 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1634422683 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 2592413912 ps |
| CPU time | 112.07 seconds |
| Started | Jul 30 07:58:23 PM PDT 24 |
| Finished | Jul 30 08:00:15 PM PDT 24 |
| Peak memory | 617712 kb |
| Host | smart-25f63bc3-61c9-4888-8897-ff1ac50121b7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1634422683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.1634422683 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1013559066 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 2606165718 ps |
| CPU time | 104.56 seconds |
| Started | Jul 30 07:57:51 PM PDT 24 |
| Finished | Jul 30 07:59:36 PM PDT 24 |
| Peak memory | 617068 kb |
| Host | smart-3797059e-b680-43b4-849c-d0ad8440c30b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013559066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1013559066 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3525533103 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 47835027356 ps |
| CPU time | 5666.74 seconds |
| Started | Jul 30 07:59:40 PM PDT 24 |
| Finished | Jul 30 09:34:08 PM PDT 24 |
| Peak memory | 619548 kb |
| Host | smart-1a071d94-1c51-45d1-a979-4b9f70d9f7ea |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525533103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_dev.3525533103 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1793142646 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 50408346760 ps |
| CPU time | 5162.56 seconds |
| Started | Jul 30 08:03:18 PM PDT 24 |
| Finished | Jul 30 09:29:21 PM PDT 24 |
| Peak memory | 620916 kb |
| Host | smart-50e70cd7-51b6-4414-9d94-fb134383318b |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793142646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_lc_walkthrough_prod.1793142646 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1020732571 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 9532888030 ps |
| CPU time | 850.07 seconds |
| Started | Jul 30 07:57:48 PM PDT 24 |
| Finished | Jul 30 08:11:59 PM PDT 24 |
| Peak memory | 620180 kb |
| Host | smart-d300602a-c1e9-4a0f-9c54-0cd3f0f336d0 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020732571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.1020732571 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1162597871 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 45858413818 ps |
| CPU time | 6847.07 seconds |
| Started | Jul 30 08:00:24 PM PDT 24 |
| Finished | Jul 30 09:54:33 PM PDT 24 |
| Peak memory | 616792 kb |
| Host | smart-b4d966e0-b7d9-439e-9d9d-bad0172737e9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162597871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.1162597871 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.99084158 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 22338689560 ps |
| CPU time | 1914.48 seconds |
| Started | Jul 30 07:58:52 PM PDT 24 |
| Finished | Jul 30 08:30:47 PM PDT 24 |
| Peak memory | 619936 kb |
| Host | smart-0f0639c2-5904-4f7e-bad0-0fff00ddb307 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=99084158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testunlocks.99084158 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.524006951 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 17070512032 ps |
| CPU time | 4096.88 seconds |
| Started | Jul 30 08:02:02 PM PDT 24 |
| Finished | Jul 30 09:10:20 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-efc71ab0-b5f7-43ba-babc-31b4d7ff148b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=524006951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.524006951 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.260986695 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 18760186583 ps |
| CPU time | 3933.15 seconds |
| Started | Jul 30 08:00:07 PM PDT 24 |
| Finished | Jul 30 09:05:41 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-87dc3654-ee73-4f46-9104-9056ea571851 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=260986695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.260986695 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1341735153 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 24537032488 ps |
| CPU time | 3703.14 seconds |
| Started | Jul 30 08:07:36 PM PDT 24 |
| Finished | Jul 30 09:09:20 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-a546146d-e551-4bc4-be6b-460c07b7c1b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341735153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.1341735153 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.688069219 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 3900969460 ps |
| CPU time | 450.71 seconds |
| Started | Jul 30 08:00:12 PM PDT 24 |
| Finished | Jul 30 08:07:43 PM PDT 24 |
| Peak memory | 608508 kb |
| Host | smart-56e6af72-b1ef-4ecf-83f3-67adc2459bcb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688069219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.688069219 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.913949070 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 5514406732 ps |
| CPU time | 877.48 seconds |
| Started | Jul 30 07:59:06 PM PDT 24 |
| Finished | Jul 30 08:13:44 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-237cf092-6462-47e3-96a8-0c9a7d19040b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=913949070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.913949070 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.2552960556 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 9977215220 ps |
| CPU time | 2457 seconds |
| Started | Jul 30 08:09:00 PM PDT 24 |
| Finished | Jul 30 08:49:58 PM PDT 24 |
| Peak memory | 610208 kb |
| Host | smart-ce304bfe-77f8-4a29-8450-00c0d8afe24e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552960556 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.2552960556 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.290022289 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 3101214179 ps |
| CPU time | 190.9 seconds |
| Started | Jul 30 07:57:47 PM PDT 24 |
| Finished | Jul 30 08:00:58 PM PDT 24 |
| Peak memory | 608764 kb |
| Host | smart-956b01b5-8c08-4592-b1a7-7bb4bd5ed25d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290022289 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.290022289 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1900932300 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 8335557960 ps |
| CPU time | 1541.91 seconds |
| Started | Jul 30 07:57:35 PM PDT 24 |
| Finished | Jul 30 08:23:18 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-5d7ef7fd-074c-4738-af8a-531ea1b9349a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1900932300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.1900932300 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.208215428 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 6852822764 ps |
| CPU time | 1121.91 seconds |
| Started | Jul 30 07:58:18 PM PDT 24 |
| Finished | Jul 30 08:17:01 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-0d2f24e8-2c79-43dc-96ca-1c68230ce297 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=208215428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.208215428 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4095354644 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 7615827364 ps |
| CPU time | 1352.13 seconds |
| Started | Jul 30 07:56:26 PM PDT 24 |
| Finished | Jul 30 08:18:59 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-24fba675-fab2-4418-9b6f-f21240506156 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4095354644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.4095354644 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3494324774 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 4370733920 ps |
| CPU time | 767.02 seconds |
| Started | Jul 30 07:58:56 PM PDT 24 |
| Finished | Jul 30 08:11:43 PM PDT 24 |
| Peak memory | 609844 kb |
| Host | smart-71f7b477-6f91-4332-9ed7-30d7466032fc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3494324774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3494324774 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.4228280580 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 3373631776 ps |
| CPU time | 301.23 seconds |
| Started | Jul 30 08:07:23 PM PDT 24 |
| Finished | Jul 30 08:12:25 PM PDT 24 |
| Peak memory | 609628 kb |
| Host | smart-3e5dbd70-3f01-4897-b3f6-f88229a9b515 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228280580 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.4228280580 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.459169857 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 3299963680 ps |
| CPU time | 310.65 seconds |
| Started | Jul 30 07:56:00 PM PDT 24 |
| Finished | Jul 30 08:01:11 PM PDT 24 |
| Peak memory | 612340 kb |
| Host | smart-add6101d-9ce7-429b-be46-c70906ac6c69 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459169857 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.459169857 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.1915481026 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 3334401600 ps |
| CPU time | 324.38 seconds |
| Started | Jul 30 08:03:17 PM PDT 24 |
| Finished | Jul 30 08:08:41 PM PDT 24 |
| Peak memory | 609548 kb |
| Host | smart-67be6b36-28c9-4449-a90d-97c609eb5329 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915481026 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.1915481026 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.4013140617 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 4787014084 ps |
| CPU time | 667.98 seconds |
| Started | Jul 30 08:06:36 PM PDT 24 |
| Finished | Jul 30 08:17:44 PM PDT 24 |
| Peak memory | 609532 kb |
| Host | smart-63f37e69-0181-43bd-b99e-026e0456c424 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013140617 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.4013140617 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.1735178766 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 9742955000 ps |
| CPU time | 429.58 seconds |
| Started | Jul 30 08:05:54 PM PDT 24 |
| Finished | Jul 30 08:13:04 PM PDT 24 |
| Peak memory | 610872 kb |
| Host | smart-dc08a431-14e6-4cb9-a100-5ff0980df4e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735178766 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.1735178766 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2673117148 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 9739925325 ps |
| CPU time | 1394.26 seconds |
| Started | Jul 30 07:57:36 PM PDT 24 |
| Finished | Jul 30 08:20:51 PM PDT 24 |
| Peak memory | 611452 kb |
| Host | smart-a8e6d97b-ee6d-445c-a51d-8b4cb777d299 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673 117148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.2673117148 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3262264707 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 24256460526 ps |
| CPU time | 2197.4 seconds |
| Started | Jul 30 08:03:04 PM PDT 24 |
| Finished | Jul 30 08:39:42 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-ad5f5094-ff9e-4298-a2bc-b10bdc708ecd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326 2264707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.3262264707 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3043826344 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 16255194191 ps |
| CPU time | 1097.92 seconds |
| Started | Jul 30 07:58:48 PM PDT 24 |
| Finished | Jul 30 08:17:06 PM PDT 24 |
| Peak memory | 611236 kb |
| Host | smart-57587231-2fdb-41bf-b8cb-3630877013ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3043826344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3043826344 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1355589111 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 21997404400 ps |
| CPU time | 1505.34 seconds |
| Started | Jul 30 08:04:24 PM PDT 24 |
| Finished | Jul 30 08:29:30 PM PDT 24 |
| Peak memory | 611116 kb |
| Host | smart-743e9a61-8b13-401d-9b5a-b81eb27df65c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1355589111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1355589111 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1009921226 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 9395866828 ps |
| CPU time | 459.31 seconds |
| Started | Jul 30 07:58:43 PM PDT 24 |
| Finished | Jul 30 08:06:23 PM PDT 24 |
| Peak memory | 610772 kb |
| Host | smart-5f56cbea-424c-4a9e-b26d-105f19b92c3e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009921226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.1009921226 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3068855833 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 7242707994 ps |
| CPU time | 571.74 seconds |
| Started | Jul 30 08:01:07 PM PDT 24 |
| Finished | Jul 30 08:10:39 PM PDT 24 |
| Peak memory | 616652 kb |
| Host | smart-4187824b-b0f5-414c-a90d-fa7d314f4c91 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3068855833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3068855833 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1564252615 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 6959955662 ps |
| CPU time | 406.54 seconds |
| Started | Jul 30 07:59:12 PM PDT 24 |
| Finished | Jul 30 08:05:59 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-5d6b4d4f-ff3b-47a7-b170-8091df547b64 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564252615 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.1564252615 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2605974070 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 4346370302 ps |
| CPU time | 275.7 seconds |
| Started | Jul 30 07:59:34 PM PDT 24 |
| Finished | Jul 30 08:04:10 PM PDT 24 |
| Peak memory | 616584 kb |
| Host | smart-57e04737-ad11-46ed-8103-6273cf8835f1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2605974070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.2605974070 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.372339457 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 12161779924 ps |
| CPU time | 1184.27 seconds |
| Started | Jul 30 08:00:07 PM PDT 24 |
| Finished | Jul 30 08:19:52 PM PDT 24 |
| Peak memory | 611456 kb |
| Host | smart-799c4024-7611-488f-9cf6-e2c425eac5cd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372339457 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.372339457 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3831242681 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 7201809608 ps |
| CPU time | 374.71 seconds |
| Started | Jul 30 08:05:30 PM PDT 24 |
| Finished | Jul 30 08:11:45 PM PDT 24 |
| Peak memory | 609560 kb |
| Host | smart-0fcc8078-2689-40b8-b749-936a675d521c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831242681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3831242681 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3847707055 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 6117046660 ps |
| CPU time | 522.07 seconds |
| Started | Jul 30 07:59:50 PM PDT 24 |
| Finished | Jul 30 08:08:32 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-b407f1c4-35a0-44d9-9cbf-8a3148a97e7b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847707055 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.3847707055 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2702204441 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 27459349329 ps |
| CPU time | 2681.37 seconds |
| Started | Jul 30 07:57:58 PM PDT 24 |
| Finished | Jul 30 08:42:40 PM PDT 24 |
| Peak memory | 611576 kb |
| Host | smart-26453d51-5217-4699-94ed-3f4dbe044f09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2702204441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2702204441 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.668237016 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 22281559178 ps |
| CPU time | 1846.93 seconds |
| Started | Jul 30 08:05:00 PM PDT 24 |
| Finished | Jul 30 08:35:47 PM PDT 24 |
| Peak memory | 611056 kb |
| Host | smart-89f0a994-27b9-4a5b-8e0b-858b1bb58512 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=668237016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.668237016 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1751380125 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 40965123186 ps |
| CPU time | 3485.91 seconds |
| Started | Jul 30 07:59:13 PM PDT 24 |
| Finished | Jul 30 08:57:20 PM PDT 24 |
| Peak memory | 612268 kb |
| Host | smart-65b0e059-6aec-407c-959f-b8e19284f804 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751380125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.1751380125 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.553575046 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 6323008004 ps |
| CPU time | 450.17 seconds |
| Started | Jul 30 08:05:05 PM PDT 24 |
| Finished | Jul 30 08:12:35 PM PDT 24 |
| Peak memory | 611000 kb |
| Host | smart-d265c123-a667-467c-8aa1-b96fe88ee629 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=553575046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_sl eep_wake_up.553575046 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3523711798 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3126240060 ps |
| CPU time | 254.38 seconds |
| Started | Jul 30 07:59:25 PM PDT 24 |
| Finished | Jul 30 08:03:39 PM PDT 24 |
| Peak memory | 609600 kb |
| Host | smart-487e3d40-04a3-4309-822b-3893d4b52705 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523711798 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.3523711798 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.188812034 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 6498916884 ps |
| CPU time | 595.39 seconds |
| Started | Jul 30 07:58:47 PM PDT 24 |
| Finished | Jul 30 08:08:42 PM PDT 24 |
| Peak memory | 617812 kb |
| Host | smart-4a6ed832-1390-461c-8043-fd17f9c7a4fa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=188812034 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.188812034 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3298168636 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 5986609600 ps |
| CPU time | 481.36 seconds |
| Started | Jul 30 08:04:34 PM PDT 24 |
| Finished | Jul 30 08:12:36 PM PDT 24 |
| Peak memory | 609896 kb |
| Host | smart-b880738b-e425-4449-b402-abf9f18419bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32981686 36 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3298168636 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.165266922 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 6457125116 ps |
| CPU time | 649.82 seconds |
| Started | Jul 30 08:04:11 PM PDT 24 |
| Finished | Jul 30 08:15:01 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-f66906d1-0da1-4c3a-9a24-6d064d335ebd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=165266922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.165266922 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3027830676 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 5231311168 ps |
| CPU time | 294.32 seconds |
| Started | Jul 30 08:07:32 PM PDT 24 |
| Finished | Jul 30 08:12:27 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-0691b438-8d62-4a69-88e9-c24a19d56e23 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027830676 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.3027830676 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.4197925402 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 8958160130 ps |
| CPU time | 1276.3 seconds |
| Started | Jul 30 07:57:49 PM PDT 24 |
| Finished | Jul 30 08:19:06 PM PDT 24 |
| Peak memory | 610932 kb |
| Host | smart-2dd9b97b-ee9d-4a4a-9ac2-4b6d4a6f523d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197925402 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.4197925402 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1266757621 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 4076195304 ps |
| CPU time | 613.41 seconds |
| Started | Jul 30 07:59:39 PM PDT 24 |
| Finished | Jul 30 08:09:53 PM PDT 24 |
| Peak memory | 610020 kb |
| Host | smart-4b91243c-fa18-4c55-b216-301c14d4913d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266757621 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1266757621 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2211461060 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 7160320604 ps |
| CPU time | 655.76 seconds |
| Started | Jul 30 08:07:36 PM PDT 24 |
| Finished | Jul 30 08:18:32 PM PDT 24 |
| Peak memory | 610356 kb |
| Host | smart-9728874f-6ca0-4f1f-9dde-229694fd5b1e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211461060 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.2211461060 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.708354900 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 5730321240 ps |
| CPU time | 637.62 seconds |
| Started | Jul 30 07:59:09 PM PDT 24 |
| Finished | Jul 30 08:09:47 PM PDT 24 |
| Peak memory | 610460 kb |
| Host | smart-1027467f-c74a-494d-887a-670d42fb27d0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708 354900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.708354900 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1493011025 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 9138337183 ps |
| CPU time | 596.32 seconds |
| Started | Jul 30 08:02:41 PM PDT 24 |
| Finished | Jul 30 08:12:38 PM PDT 24 |
| Peak memory | 624796 kb |
| Host | smart-b453c337-a8ca-4ebb-a12b-15fef01bac3a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493011025 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.1493011025 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2412696462 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 5499499384 ps |
| CPU time | 760.91 seconds |
| Started | Jul 30 08:03:14 PM PDT 24 |
| Finished | Jul 30 08:15:55 PM PDT 24 |
| Peak memory | 610552 kb |
| Host | smart-244d9626-bca8-47d4-bee2-8a0e653e3626 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412696462 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.2412696462 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2435574425 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 4467881632 ps |
| CPU time | 418.66 seconds |
| Started | Jul 30 07:55:30 PM PDT 24 |
| Finished | Jul 30 08:02:29 PM PDT 24 |
| Peak memory | 641736 kb |
| Host | smart-c239105e-0dab-41d7-b4f3-3ca10b9a3ea6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2435574425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.2435574425 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3129079537 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 2966554676 ps |
| CPU time | 264.89 seconds |
| Started | Jul 30 08:07:49 PM PDT 24 |
| Finished | Jul 30 08:12:14 PM PDT 24 |
| Peak memory | 609572 kb |
| Host | smart-c2eac4f4-e2df-4ff7-943f-28108807a3d0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129079537 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.3129079537 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3351719442 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 4370326936 ps |
| CPU time | 387.61 seconds |
| Started | Jul 30 07:58:26 PM PDT 24 |
| Finished | Jul 30 08:04:54 PM PDT 24 |
| Peak memory | 610364 kb |
| Host | smart-a13ab509-89b9-4952-881e-a75a098e579c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351719442 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.3351719442 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2670595231 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 2545318416 ps |
| CPU time | 262.84 seconds |
| Started | Jul 30 08:01:10 PM PDT 24 |
| Finished | Jul 30 08:05:33 PM PDT 24 |
| Peak memory | 609616 kb |
| Host | smart-55124402-ebaf-406b-bb34-e5db655fd8a0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670595231 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.2670595231 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.296340042 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2884036484 ps |
| CPU time | 248.65 seconds |
| Started | Jul 30 08:04:09 PM PDT 24 |
| Finished | Jul 30 08:08:18 PM PDT 24 |
| Peak memory | 609736 kb |
| Host | smart-762628c3-d14b-43b6-b3f6-134f1a16e583 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=296340042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.296340042 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.50456465 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 3318796898 ps |
| CPU time | 396.43 seconds |
| Started | Jul 30 08:06:32 PM PDT 24 |
| Finished | Jul 30 08:13:09 PM PDT 24 |
| Peak memory | 609864 kb |
| Host | smart-c334df00-9ed2-482a-b056-c3fe4ab7b494 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50456465 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.50456465 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.280156832 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 4694722358 ps |
| CPU time | 864.8 seconds |
| Started | Jul 30 08:01:57 PM PDT 24 |
| Finished | Jul 30 08:16:22 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-53d5f970-f3ea-4ec3-8e9d-d5d29e38f459 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28015 6832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.280156832 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3024309352 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 5072937708 ps |
| CPU time | 1115.67 seconds |
| Started | Jul 30 08:02:04 PM PDT 24 |
| Finished | Jul 30 08:20:40 PM PDT 24 |
| Peak memory | 608832 kb |
| Host | smart-f5973aec-2793-4ff1-88b1-c72157c0df80 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3024309352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.3024309352 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3904972104 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 5215413603 ps |
| CPU time | 489.19 seconds |
| Started | Jul 30 08:04:55 PM PDT 24 |
| Finished | Jul 30 08:13:04 PM PDT 24 |
| Peak memory | 624396 kb |
| Host | smart-d78673b9-db8d-40bf-98b0-b9ef24185c8b |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904972104 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.3904972104 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.2980162563 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 6636987336 ps |
| CPU time | 427.39 seconds |
| Started | Jul 30 08:04:16 PM PDT 24 |
| Finished | Jul 30 08:11:24 PM PDT 24 |
| Peak memory | 620512 kb |
| Host | smart-bc27d398-d8bc-4df0-97ce-38edf6a069b2 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980162563 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.2980162563 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.186782760 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 4893371320 ps |
| CPU time | 598.02 seconds |
| Started | Jul 30 08:05:09 PM PDT 24 |
| Finished | Jul 30 08:15:07 PM PDT 24 |
| Peak memory | 621320 kb |
| Host | smart-a78f35d0-2675-4344-bd66-b019fbedd7fc |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186782 760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.186782760 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2853323979 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 2756042952 ps |
| CPU time | 210.21 seconds |
| Started | Jul 30 08:06:49 PM PDT 24 |
| Finished | Jul 30 08:10:20 PM PDT 24 |
| Peak memory | 609544 kb |
| Host | smart-988cda6b-a43a-46a2-abef-6792b417e8b6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853323979 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.2853323979 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.3593161333 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 2650719536 ps |
| CPU time | 305.57 seconds |
| Started | Jul 30 08:00:21 PM PDT 24 |
| Finished | Jul 30 08:05:27 PM PDT 24 |
| Peak memory | 609524 kb |
| Host | smart-42c90827-1a3d-4de5-b661-b65ffc431b39 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593161333 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.3593161333 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3776600210 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 3208356604 ps |
| CPU time | 291.37 seconds |
| Started | Jul 30 08:07:47 PM PDT 24 |
| Finished | Jul 30 08:12:39 PM PDT 24 |
| Peak memory | 609544 kb |
| Host | smart-89a380d2-742b-438f-868c-592f161f6951 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776600210 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.3776600210 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3391527866 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 3616783824 ps |
| CPU time | 349.47 seconds |
| Started | Jul 30 08:03:24 PM PDT 24 |
| Finished | Jul 30 08:09:14 PM PDT 24 |
| Peak memory | 609948 kb |
| Host | smart-775de201-e8ac-4044-8963-82f0532c70a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33915278 66 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.3391527866 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1031145162 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3434238662 ps |
| CPU time | 319.19 seconds |
| Started | Jul 30 08:03:47 PM PDT 24 |
| Finished | Jul 30 08:09:06 PM PDT 24 |
| Peak memory | 609600 kb |
| Host | smart-ae0ee2e3-6da8-45fb-a685-32c7b2dc3def |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031145 162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.1031145162 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3399543797 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3880537688 ps |
| CPU time | 287 seconds |
| Started | Jul 30 07:55:57 PM PDT 24 |
| Finished | Jul 30 08:00:44 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-e25e8e8a-dbf8-4cf4-b095-5a98c579dafe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399543797 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.3399543797 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.4017636297 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 8404718168 ps |
| CPU time | 1237 seconds |
| Started | Jul 30 07:59:20 PM PDT 24 |
| Finished | Jul 30 08:19:58 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-909e9800-430e-40a9-8c63-34e00a8d7c42 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017636297 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.4017636297 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.804223610 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 8505813340 ps |
| CPU time | 797.25 seconds |
| Started | Jul 30 08:03:50 PM PDT 24 |
| Finished | Jul 30 08:17:07 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-b0002029-f011-4bc8-8bc4-e8865568af22 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804223610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sle ep_sram_ret_contents_no_scramble.804223610 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.399594954 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 7188102668 ps |
| CPU time | 866.68 seconds |
| Started | Jul 30 08:03:08 PM PDT 24 |
| Finished | Jul 30 08:17:35 PM PDT 24 |
| Peak memory | 610576 kb |
| Host | smart-6e81857f-1c30-444e-a803-fc9fecd146c1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399594954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_ sram_ret_contents_scramble.399594954 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.4041536673 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 6076578053 ps |
| CPU time | 663.15 seconds |
| Started | Jul 30 07:58:44 PM PDT 24 |
| Finished | Jul 30 08:09:47 PM PDT 24 |
| Peak memory | 624836 kb |
| Host | smart-b22f602e-dfa5-4b58-b283-186b17d76b46 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041536673 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.4041536673 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.707821104 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 4367444557 ps |
| CPU time | 510.32 seconds |
| Started | Jul 30 08:00:47 PM PDT 24 |
| Finished | Jul 30 08:09:18 PM PDT 24 |
| Peak memory | 624844 kb |
| Host | smart-ea501c75-4da0-42d5-ae3c-7258e96314c7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707821104 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.707821104 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.1941393395 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2844144260 ps |
| CPU time | 384.69 seconds |
| Started | Jul 30 08:01:38 PM PDT 24 |
| Finished | Jul 30 08:08:03 PM PDT 24 |
| Peak memory | 618592 kb |
| Host | smart-c66b942d-4058-4fe2-8faa-7943d34c9158 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941393395 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.1941393395 |
| Directory | /workspace/1.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.1132613468 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3526718539 ps |
| CPU time | 358.6 seconds |
| Started | Jul 30 08:00:58 PM PDT 24 |
| Finished | Jul 30 08:06:58 PM PDT 24 |
| Peak memory | 618356 kb |
| Host | smart-1a449a19-2d9a-4e32-8283-48a1f2d3c8d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132613468 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.1132613468 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1689642855 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3174208712 ps |
| CPU time | 334.29 seconds |
| Started | Jul 30 08:01:13 PM PDT 24 |
| Finished | Jul 30 08:06:48 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-734a2344-9d70-40b0-a2f8-7ab6a6e68ff8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689642855 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.1689642855 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2556291533 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 7148927342 ps |
| CPU time | 936.33 seconds |
| Started | Jul 30 08:02:23 PM PDT 24 |
| Finished | Jul 30 08:18:00 PM PDT 24 |
| Peak memory | 610436 kb |
| Host | smart-9cc9159c-d50f-4594-a961-1ba643d0ef80 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556291533 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.2556291533 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1391551305 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 5823065550 ps |
| CPU time | 710.25 seconds |
| Started | Jul 30 08:04:20 PM PDT 24 |
| Finished | Jul 30 08:16:11 PM PDT 24 |
| Peak memory | 611116 kb |
| Host | smart-be800424-63b1-4c2b-9632-6f11a26acef5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391551305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.1391551305 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4013617631 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 5310008778 ps |
| CPU time | 564.19 seconds |
| Started | Jul 30 08:03:36 PM PDT 24 |
| Finished | Jul 30 08:13:01 PM PDT 24 |
| Peak memory | 611176 kb |
| Host | smart-7d4aacba-95b5-43d0-8a0b-2854848a304d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013617631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4013617631 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.902461113 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 4968742901 ps |
| CPU time | 589.44 seconds |
| Started | Jul 30 08:06:06 PM PDT 24 |
| Finished | Jul 30 08:15:56 PM PDT 24 |
| Peak memory | 610860 kb |
| Host | smart-3b30c4b0-115f-424f-a46f-39fe965bfb71 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902461113 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.902461113 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.273524452 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 2299996566 ps |
| CPU time | 225.73 seconds |
| Started | Jul 30 08:07:54 PM PDT 24 |
| Finished | Jul 30 08:11:40 PM PDT 24 |
| Peak memory | 608432 kb |
| Host | smart-d6526094-869a-4183-9efa-c6ce8dac6665 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273524452 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_sram_ctrl_smoketest.273524452 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3726209491 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 20539531820 ps |
| CPU time | 4016.57 seconds |
| Started | Jul 30 08:02:24 PM PDT 24 |
| Finished | Jul 30 09:09:21 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-fefacd53-5849-45b7-96c7-bb06b0cb3096 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726209491 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.3726209491 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3959598884 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 4798688490 ps |
| CPU time | 677.58 seconds |
| Started | Jul 30 07:59:39 PM PDT 24 |
| Finished | Jul 30 08:10:58 PM PDT 24 |
| Peak memory | 613688 kb |
| Host | smart-6d7cf572-0bbd-47a4-a2a8-38e66ddb91fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959598884 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.3959598884 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3973158750 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 2909263046 ps |
| CPU time | 287.78 seconds |
| Started | Jul 30 08:01:35 PM PDT 24 |
| Finished | Jul 30 08:06:24 PM PDT 24 |
| Peak memory | 613372 kb |
| Host | smart-39007f94-7c22-409e-bb9f-045e339ab9a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973158750 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.3973158750 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3181497547 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 6420303240 ps |
| CPU time | 622.89 seconds |
| Started | Jul 30 07:59:47 PM PDT 24 |
| Finished | Jul 30 08:10:11 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-d5d16709-4f7f-4ebc-a3ce-557f122b69d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181497547 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3181497547 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2636134848 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 8874857696 ps |
| CPU time | 1993.64 seconds |
| Started | Jul 30 08:00:12 PM PDT 24 |
| Finished | Jul 30 08:33:27 PM PDT 24 |
| Peak memory | 624528 kb |
| Host | smart-2a229004-1795-4995-bdbb-875c0608d4a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2636134848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.2636134848 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.2369698410 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 3047320250 ps |
| CPU time | 275.38 seconds |
| Started | Jul 30 08:08:11 PM PDT 24 |
| Finished | Jul 30 08:12:46 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-dc5b692c-3166-47b5-9686-a40c2f6547b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369698410 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_uart_smoketest.2369698410 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.4227573101 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 4001304250 ps |
| CPU time | 682.87 seconds |
| Started | Jul 30 07:56:56 PM PDT 24 |
| Finished | Jul 30 08:08:19 PM PDT 24 |
| Peak memory | 623520 kb |
| Host | smart-779bd3b0-6231-4d68-902f-8d8132456863 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227573101 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.4227573101 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.4022313664 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 4746292712 ps |
| CPU time | 576.8 seconds |
| Started | Jul 30 07:58:14 PM PDT 24 |
| Finished | Jul 30 08:07:52 PM PDT 24 |
| Peak memory | 624560 kb |
| Host | smart-1bfb1d1b-1643-43d4-92c1-b1a1e22fb796 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022313664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.4022313664 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1991745093 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 8008352552 ps |
| CPU time | 900.6 seconds |
| Started | Jul 30 07:55:53 PM PDT 24 |
| Finished | Jul 30 08:10:54 PM PDT 24 |
| Peak memory | 623388 kb |
| Host | smart-fb98abc0-b6ab-4613-9bba-364b6ab20ad6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991745093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1991745093 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2832396194 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4169407590 ps |
| CPU time | 536.54 seconds |
| Started | Jul 30 07:57:29 PM PDT 24 |
| Finished | Jul 30 08:06:25 PM PDT 24 |
| Peak memory | 623788 kb |
| Host | smart-c2dab39f-9fb5-4d1a-843e-e0cfc0caadb6 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832396194 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.2832396194 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2316949949 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 4396464352 ps |
| CPU time | 724 seconds |
| Started | Jul 30 07:57:41 PM PDT 24 |
| Finished | Jul 30 08:09:45 PM PDT 24 |
| Peak memory | 623888 kb |
| Host | smart-16d3ef75-d1a2-4fc0-a6b9-12a34b787c25 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316949949 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.2316949949 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3286702911 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 4146386404 ps |
| CPU time | 765.18 seconds |
| Started | Jul 30 07:59:29 PM PDT 24 |
| Finished | Jul 30 08:12:15 PM PDT 24 |
| Peak memory | 623588 kb |
| Host | smart-b3643153-69ec-4ff4-a624-5176d751f9e6 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286702911 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.3286702911 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.3735853799 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 3280466174 ps |
| CPU time | 142.01 seconds |
| Started | Jul 30 08:05:01 PM PDT 24 |
| Finished | Jul 30 08:07:23 PM PDT 24 |
| Peak memory | 620916 kb |
| Host | smart-33a6a71a-488d-44ec-8f23-ec364b390342 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3735853799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.3735853799 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.1770664607 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 2737390234 ps |
| CPU time | 176.94 seconds |
| Started | Jul 30 08:05:53 PM PDT 24 |
| Finished | Jul 30 08:08:51 PM PDT 24 |
| Peak memory | 623744 kb |
| Host | smart-86058ec6-5b5c-4a27-a19e-57777ca4a9a2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770664607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.1770664607 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.4070515667 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 15910213894 ps |
| CPU time | 3963.04 seconds |
| Started | Jul 30 08:16:20 PM PDT 24 |
| Finished | Jul 30 09:22:23 PM PDT 24 |
| Peak memory | 610212 kb |
| Host | smart-04a3befb-9d20-491a-8a10-872eebfbb585 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070515667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.4070515667 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.1239154339 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 15166391574 ps |
| CPU time | 5416.47 seconds |
| Started | Jul 30 08:11:00 PM PDT 24 |
| Finished | Jul 30 09:41:17 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-69ff026b-6019-46ae-9c90-273d784c9566 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239154339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.1239154339 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.559159219 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 15204817894 ps |
| CPU time | 4158.25 seconds |
| Started | Jul 30 08:10:39 PM PDT 24 |
| Finished | Jul 30 09:19:58 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-2ece7fd4-75f1-4884-97e8-587d793a5a07 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559159219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.rom_e2e_asm_init_prod_end.559159219 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.3499091495 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 15123954995 ps |
| CPU time | 4221.49 seconds |
| Started | Jul 30 08:12:02 PM PDT 24 |
| Finished | Jul 30 09:22:24 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-93efe5c2-5091-4791-9e02-f888687390a6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499091495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.3499091495 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1978976432 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 12301142665 ps |
| CPU time | 3303.98 seconds |
| Started | Jul 30 08:09:58 PM PDT 24 |
| Finished | Jul 30 09:05:03 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-48c14a32-0367-4034-9f99-1348fa18ab03 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978976432 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.1978976432 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2993011020 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 15616408192 ps |
| CPU time | 3291.58 seconds |
| Started | Jul 30 08:11:19 PM PDT 24 |
| Finished | Jul 30 09:06:11 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-7e4a45ff-8065-4228-939e-f8f0e32d3241 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993011020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.2993011020 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.4239300450 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 15562677912 ps |
| CPU time | 5007.38 seconds |
| Started | Jul 30 08:13:13 PM PDT 24 |
| Finished | Jul 30 09:36:41 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-80fa704a-29f3-4e88-877e-e83cc37025ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239300450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.4239300450 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3797529154 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 14199582270 ps |
| CPU time | 4173.97 seconds |
| Started | Jul 30 08:12:28 PM PDT 24 |
| Finished | Jul 30 09:22:03 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-f328cc1a-bd07-4185-a3a1-1840f0a2711d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797529154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.3797529154 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_self_hash.3407466497 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 26298498612 ps |
| CPU time | 5896.62 seconds |
| Started | Jul 30 08:11:34 PM PDT 24 |
| Finished | Jul 30 09:49:52 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-cda84096-11f8-44f3-8334-64e4cd73f0bd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407466497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.3407466497 |
| Directory | /workspace/1.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.414859392 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 15007875345 ps |
| CPU time | 3673.23 seconds |
| Started | Jul 30 08:11:34 PM PDT 24 |
| Finished | Jul 30 09:12:48 PM PDT 24 |
| Peak memory | 611392 kb |
| Host | smart-e9b937fc-19b7-427f-8f8b-b9a5d1f59c7a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414859392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shut down_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_s hutdown_exception_c.414859392 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.1377251798 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29216605495 ps |
| CPU time | 3948.24 seconds |
| Started | Jul 30 08:10:56 PM PDT 24 |
| Finished | Jul 30 09:16:45 PM PDT 24 |
| Peak memory | 611212 kb |
| Host | smart-5730ce0d-6538-4fa9-833b-89a695542eb9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377251798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.1377251798 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.2229868932 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 15353373312 ps |
| CPU time | 4302.17 seconds |
| Started | Jul 30 08:15:47 PM PDT 24 |
| Finished | Jul 30 09:27:32 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-6e44a1bc-94e3-4e7f-b3ef-831666df45f9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=2229868932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.2229868932 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.491359658 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 17869221522 ps |
| CPU time | 4737.15 seconds |
| Started | Jul 30 08:10:10 PM PDT 24 |
| Finished | Jul 30 09:29:08 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-b96e4703-f9a4-47d6-b56f-9debf2ad6a46 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491359658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.491359658 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.1391831794 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 5071717720 ps |
| CPU time | 661.69 seconds |
| Started | Jul 30 08:06:54 PM PDT 24 |
| Finished | Jul 30 08:17:56 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-a81f878c-ef74-4c35-9a03-9efe012463ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391831794 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.1391831794 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_raw_unlock.3111242778 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 5742228058 ps |
| CPU time | 250.87 seconds |
| Started | Jul 30 08:06:56 PM PDT 24 |
| Finished | Jul 30 08:11:07 PM PDT 24 |
| Peak memory | 619840 kb |
| Host | smart-e533a153-e6e4-40cd-9c4d-e1080005d22c |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3111242778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.3111242778 |
| Directory | /workspace/1.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.2771956794 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 2049941204 ps |
| CPU time | 103.73 seconds |
| Started | Jul 30 08:06:28 PM PDT 24 |
| Finished | Jul 30 08:08:12 PM PDT 24 |
| Peak memory | 617552 kb |
| Host | smart-1a8ff05b-74cd-4d50-aec2-f4544b3afb80 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771956794 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.2771956794 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.202814111 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 5533892522 ps |
| CPU time | 477.66 seconds |
| Started | Jul 30 08:21:12 PM PDT 24 |
| Finished | Jul 30 08:29:10 PM PDT 24 |
| Peak memory | 620432 kb |
| Host | smart-420e7238-2f34-4bb3-9759-7e5cbb08f109 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202814111 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.202814111 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.157501029 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 4463350480 ps |
| CPU time | 613.14 seconds |
| Started | Jul 30 08:24:11 PM PDT 24 |
| Finished | Jul 30 08:34:26 PM PDT 24 |
| Peak memory | 624472 kb |
| Host | smart-c82a7139-a43d-4786-9a9f-735ae9f74e9b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=157501029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.157501029 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3527366643 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 8991424818 ps |
| CPU time | 692.98 seconds |
| Started | Jul 30 08:22:20 PM PDT 24 |
| Finished | Jul 30 08:33:53 PM PDT 24 |
| Peak memory | 621300 kb |
| Host | smart-862b816b-d090-4ec6-951b-dc46a3436b66 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527366643 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.3527366643 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1886571323 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 4586442256 ps |
| CPU time | 586.04 seconds |
| Started | Jul 30 08:22:59 PM PDT 24 |
| Finished | Jul 30 08:32:45 PM PDT 24 |
| Peak memory | 624540 kb |
| Host | smart-e95857b3-11d9-4833-b860-c12a68164c97 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1886571323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.1886571323 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.4032831017 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 5851654354 ps |
| CPU time | 673.65 seconds |
| Started | Jul 30 08:22:00 PM PDT 24 |
| Finished | Jul 30 08:33:14 PM PDT 24 |
| Peak memory | 616920 kb |
| Host | smart-9087c2e3-585d-4e72-9ff0-09f876f753ab |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4032831017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.4032831017 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2826502246 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 11184268219 ps |
| CPU time | 1241.97 seconds |
| Started | Jul 30 08:22:00 PM PDT 24 |
| Finished | Jul 30 08:42:42 PM PDT 24 |
| Peak memory | 620460 kb |
| Host | smart-d004a9b7-a3e6-48d2-90ca-d918874a49a0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826502246 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.2826502246 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.249778718 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 8371159968 ps |
| CPU time | 1879.4 seconds |
| Started | Jul 30 08:22:46 PM PDT 24 |
| Finished | Jul 30 08:54:05 PM PDT 24 |
| Peak memory | 624504 kb |
| Host | smart-3d7cca18-f764-46d7-ba37-30555e5068f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=249778718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.249778718 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3978838597 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 6828804620 ps |
| CPU time | 469.47 seconds |
| Started | Jul 30 08:22:48 PM PDT 24 |
| Finished | Jul 30 08:30:38 PM PDT 24 |
| Peak memory | 620492 kb |
| Host | smart-e00c102d-1d80-4c14-8eb2-4f5322920142 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978838597 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.3978838597 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1017352409 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 8311439656 ps |
| CPU time | 1429.58 seconds |
| Started | Jul 30 08:22:48 PM PDT 24 |
| Finished | Jul 30 08:46:38 PM PDT 24 |
| Peak memory | 623252 kb |
| Host | smart-14e2e981-bedd-4d22-97aa-95b1504be6f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1017352409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.1017352409 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.538059365 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 7016568256 ps |
| CPU time | 404.71 seconds |
| Started | Jul 30 08:22:50 PM PDT 24 |
| Finished | Jul 30 08:29:35 PM PDT 24 |
| Peak memory | 620488 kb |
| Host | smart-efffbec8-ad9a-4d91-8a9d-5da797131f98 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538059365 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.538059365 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2870070722 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 13434850668 ps |
| CPU time | 2200.36 seconds |
| Started | Jul 30 08:20:56 PM PDT 24 |
| Finished | Jul 30 08:57:37 PM PDT 24 |
| Peak memory | 624568 kb |
| Host | smart-86b1ba7d-841f-4ef6-8b02-76515ad455ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2870070722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.2870070722 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.951909280 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 3450451200 ps |
| CPU time | 426.86 seconds |
| Started | Jul 30 08:22:35 PM PDT 24 |
| Finished | Jul 30 08:29:42 PM PDT 24 |
| Peak memory | 649124 kb |
| Host | smart-6f1225ee-73bc-44a5-8ccc-7773d762c8c4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951909280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_s w_alert_handler_lpg_sleep_mode_alerts.951909280 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.316364027 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 3908712350 ps |
| CPU time | 638.74 seconds |
| Started | Jul 30 08:23:13 PM PDT 24 |
| Finished | Jul 30 08:33:52 PM PDT 24 |
| Peak memory | 623232 kb |
| Host | smart-89ae15ca-f6df-47b5-a5f6-adad8e0c7178 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=316364027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.316364027 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1862338829 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 4080292240 ps |
| CPU time | 685.48 seconds |
| Started | Jul 30 08:24:00 PM PDT 24 |
| Finished | Jul 30 08:35:26 PM PDT 24 |
| Peak memory | 624540 kb |
| Host | smart-edefd385-3135-4e3c-8ed0-a874cb81444d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1862338829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.1862338829 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.2140233882 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 4471831400 ps |
| CPU time | 569.2 seconds |
| Started | Jul 30 08:22:50 PM PDT 24 |
| Finished | Jul 30 08:32:19 PM PDT 24 |
| Peak memory | 650368 kb |
| Host | smart-ee0373f8-a6e4-4c98-b7b2-a2c062addc8f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2140233882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.2140233882 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.966101091 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 3275568622 ps |
| CPU time | 488.14 seconds |
| Started | Jul 30 08:23:21 PM PDT 24 |
| Finished | Jul 30 08:31:29 PM PDT 24 |
| Peak memory | 623192 kb |
| Host | smart-8b36b439-44a2-43e7-94f4-0923070766f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=966101091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.966101091 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.397372053 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 3306797840 ps |
| CPU time | 436.29 seconds |
| Started | Jul 30 08:23:05 PM PDT 24 |
| Finished | Jul 30 08:30:21 PM PDT 24 |
| Peak memory | 649076 kb |
| Host | smart-82a958c1-271a-4a6b-971d-3ca07e03589c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397372053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_s w_alert_handler_lpg_sleep_mode_alerts.397372053 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3955850988 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 4012430240 ps |
| CPU time | 593.32 seconds |
| Started | Jul 30 08:22:14 PM PDT 24 |
| Finished | Jul 30 08:32:08 PM PDT 24 |
| Peak memory | 624532 kb |
| Host | smart-72cb96e3-8846-4e48-932c-11436717af55 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3955850988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.3955850988 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3946099772 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 3323634118 ps |
| CPU time | 370.88 seconds |
| Started | Jul 30 08:22:55 PM PDT 24 |
| Finished | Jul 30 08:29:07 PM PDT 24 |
| Peak memory | 649116 kb |
| Host | smart-a789f5c7-9493-46ad-ae95-d2efab78b305 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946099772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3946099772 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2038253455 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 12492530350 ps |
| CPU time | 2450.08 seconds |
| Started | Jul 30 08:21:49 PM PDT 24 |
| Finished | Jul 30 09:02:40 PM PDT 24 |
| Peak memory | 624552 kb |
| Host | smart-e5516b8c-8fc8-4b51-9b17-5738eb7f2e40 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2038253455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.2038253455 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.1655285033 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 13977330492 ps |
| CPU time | 1501.58 seconds |
| Started | Jul 30 08:08:07 PM PDT 24 |
| Finished | Jul 30 08:33:09 PM PDT 24 |
| Peak memory | 605704 kb |
| Host | smart-be6e9b5b-c41a-4ca9-b081-22a85b9be743 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655285033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.1 655285033 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.4090049395 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 4303171112 ps |
| CPU time | 430.23 seconds |
| Started | Jul 30 08:16:14 PM PDT 24 |
| Finished | Jul 30 08:23:24 PM PDT 24 |
| Peak memory | 619820 kb |
| Host | smart-d0c5cc6f-70f5-4559-9a72-c852f2d699b5 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4 090049395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.4090049395 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.128651196 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3581018446 ps |
| CPU time | 327.44 seconds |
| Started | Jul 30 08:07:45 PM PDT 24 |
| Finished | Jul 30 08:13:13 PM PDT 24 |
| Peak memory | 609884 kb |
| Host | smart-d2eea42f-d349-41a7-b144-b70b1bafa8ec |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=128651196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.128651196 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1450746203 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 20034262120 ps |
| CPU time | 754.42 seconds |
| Started | Jul 30 08:10:42 PM PDT 24 |
| Finished | Jul 30 08:23:17 PM PDT 24 |
| Peak memory | 619660 kb |
| Host | smart-dbb505da-f15f-4a2f-bcf4-dbca366947f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1450746203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1450746203 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.3156188694 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 2750462864 ps |
| CPU time | 290.26 seconds |
| Started | Jul 30 08:11:12 PM PDT 24 |
| Finished | Jul 30 08:16:03 PM PDT 24 |
| Peak memory | 609416 kb |
| Host | smart-91950110-68a3-4ffe-b4cc-1efba3622bdf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156188694 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.3156188694 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3372054871 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 3245935530 ps |
| CPU time | 244.41 seconds |
| Started | Jul 30 08:11:57 PM PDT 24 |
| Finished | Jul 30 08:16:02 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-69383e9b-e602-45ef-a70e-65996f2b07b9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372 054871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.3372054871 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3355300007 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 2912947910 ps |
| CPU time | 212.31 seconds |
| Started | Jul 30 08:15:36 PM PDT 24 |
| Finished | Jul 30 08:19:08 PM PDT 24 |
| Peak memory | 609740 kb |
| Host | smart-d5148413-1f57-49c8-92f2-8534dc3e713f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355300007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.3355300007 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.2018979179 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 2736936480 ps |
| CPU time | 258.58 seconds |
| Started | Jul 30 08:12:12 PM PDT 24 |
| Finished | Jul 30 08:16:31 PM PDT 24 |
| Peak memory | 609412 kb |
| Host | smart-b35364cb-2c60-449d-a422-57a775889edc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018979179 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.2018979179 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.288785938 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 3270785770 ps |
| CPU time | 206.46 seconds |
| Started | Jul 30 08:11:40 PM PDT 24 |
| Finished | Jul 30 08:15:06 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-959995a8-fc27-4290-9e6d-c3ca7a2f0e4f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288785938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.288785938 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.1613318218 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 2560859179 ps |
| CPU time | 448.71 seconds |
| Started | Jul 30 08:12:05 PM PDT 24 |
| Finished | Jul 30 08:19:34 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-a68af615-eea1-4676-93f6-413ef5563714 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613318218 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.1613318218 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.3996157813 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 3614049828 ps |
| CPU time | 371.29 seconds |
| Started | Jul 30 08:19:08 PM PDT 24 |
| Finished | Jul 30 08:25:20 PM PDT 24 |
| Peak memory | 608376 kb |
| Host | smart-e17015d3-542d-4c18-8eb7-2d1e1d9ff3f5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996157813 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.3996157813 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.3020787190 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 3544149843 ps |
| CPU time | 289.97 seconds |
| Started | Jul 30 08:11:53 PM PDT 24 |
| Finished | Jul 30 08:16:44 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-b5ba44d3-6974-4bed-95e0-f089337945da |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3020787190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.3020787190 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.3025636285 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 5704615460 ps |
| CPU time | 515.56 seconds |
| Started | Jul 30 08:11:57 PM PDT 24 |
| Finished | Jul 30 08:20:32 PM PDT 24 |
| Peak memory | 619656 kb |
| Host | smart-e950086b-12b5-4317-9d2c-46565356d6cc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3025636285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.3025636285 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.761935184 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 7164652994 ps |
| CPU time | 1596.46 seconds |
| Started | Jul 30 08:13:00 PM PDT 24 |
| Finished | Jul 30 08:39:37 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-3382d4cc-80dd-4538-b708-37c0a5f20b62 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=761935184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.761935184 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.831506757 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 8247845616 ps |
| CPU time | 1956.27 seconds |
| Started | Jul 30 08:12:20 PM PDT 24 |
| Finished | Jul 30 08:44:57 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-87f88952-34c7-4b5a-8ffe-e03d420a107d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831506757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_toggle.831506757 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1005234167 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 3428448008 ps |
| CPU time | 390.58 seconds |
| Started | Jul 30 08:20:11 PM PDT 24 |
| Finished | Jul 30 08:26:42 PM PDT 24 |
| Peak memory | 648984 kb |
| Host | smart-f736a5ad-28d4-4304-99d3-9caff9a5801b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005234167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.1005234167 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2966870769 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 8363861520 ps |
| CPU time | 1814.5 seconds |
| Started | Jul 30 08:19:33 PM PDT 24 |
| Finished | Jul 30 08:49:48 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-fac2cdc3-8641-4a16-8473-dec6ff0abe84 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2966870769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.2966870769 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.4181917992 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 3839297494 ps |
| CPU time | 386.75 seconds |
| Started | Jul 30 08:19:25 PM PDT 24 |
| Finished | Jul 30 08:25:52 PM PDT 24 |
| Peak memory | 609500 kb |
| Host | smart-8a0936b8-bff4-4e31-b0c8-26adda91fb37 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4181917992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.4181917992 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1961156440 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 256371869776 ps |
| CPU time | 12460.1 seconds |
| Started | Jul 30 08:20:48 PM PDT 24 |
| Finished | Jul 30 11:48:30 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-e1d059b4-fdf6-4dda-bd66-c383a98411f5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1961156440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1961156440 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.272024518 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3242397896 ps |
| CPU time | 296.5 seconds |
| Started | Jul 30 08:12:49 PM PDT 24 |
| Finished | Jul 30 08:17:46 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-7027cf76-c178-49c5-97bb-f5f2134c2349 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272024518 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_alert_test.272024518 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.4253715454 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 3552869800 ps |
| CPU time | 525.21 seconds |
| Started | Jul 30 08:11:57 PM PDT 24 |
| Finished | Jul 30 08:20:43 PM PDT 24 |
| Peak memory | 609204 kb |
| Host | smart-5a356be8-b498-4112-a76f-3d4fc921c97f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253715454 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.4253715454 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3237333099 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 7232831256 ps |
| CPU time | 382.65 seconds |
| Started | Jul 30 08:11:53 PM PDT 24 |
| Finished | Jul 30 08:18:16 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-db84b338-498e-4f21-b41d-955b020d9d49 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3237333099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3237333099 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.751519392 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 3349676044 ps |
| CPU time | 334.75 seconds |
| Started | Jul 30 08:18:09 PM PDT 24 |
| Finished | Jul 30 08:23:44 PM PDT 24 |
| Peak memory | 609564 kb |
| Host | smart-e85142be-6e52-4b64-918f-479a748896eb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751519392 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_aon_timer_smoketest.751519392 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.693407832 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 8466932264 ps |
| CPU time | 782.48 seconds |
| Started | Jul 30 08:11:25 PM PDT 24 |
| Finished | Jul 30 08:24:28 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-1eb85164-8e86-453c-9ece-bf273e209205 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 693407832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.693407832 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3593047512 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 5600103094 ps |
| CPU time | 846.37 seconds |
| Started | Jul 30 08:13:59 PM PDT 24 |
| Finished | Jul 30 08:28:05 PM PDT 24 |
| Peak memory | 609388 kb |
| Host | smart-7b882a01-8071-482e-a10c-7c58b875fe51 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3593047512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.3593047512 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.852577219 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 7400943504 ps |
| CPU time | 1058.35 seconds |
| Started | Jul 30 08:15:58 PM PDT 24 |
| Finished | Jul 30 08:33:36 PM PDT 24 |
| Peak memory | 616264 kb |
| Host | smart-64050d9f-6268-4723-bf25-083a0f5c075d |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852577219 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.852577219 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3660296459 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 25173186829 ps |
| CPU time | 4217.8 seconds |
| Started | Jul 30 08:17:34 PM PDT 24 |
| Finished | Jul 30 09:27:53 PM PDT 24 |
| Peak memory | 611080 kb |
| Host | smart-7212ae73-210c-47c4-8398-8699502a97c3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660296459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.3660296459 |
| Directory | /workspace/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1077298484 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 14117824854 ps |
| CPU time | 1199.95 seconds |
| Started | Jul 30 08:15:11 PM PDT 24 |
| Finished | Jul 30 08:35:11 PM PDT 24 |
| Peak memory | 621140 kb |
| Host | smart-5cbc9d20-75ad-4785-b206-b8dd6817ad6f |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1077298484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.1077298484 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3406396974 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 3978128586 ps |
| CPU time | 688.83 seconds |
| Started | Jul 30 08:15:09 PM PDT 24 |
| Finished | Jul 30 08:26:38 PM PDT 24 |
| Peak memory | 611956 kb |
| Host | smart-a8de9d1b-b23c-4bec-8843-5f03758ef42a |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406396974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3406396974 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1000985067 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 4130369712 ps |
| CPU time | 604.47 seconds |
| Started | Jul 30 08:15:12 PM PDT 24 |
| Finished | Jul 30 08:25:17 PM PDT 24 |
| Peak memory | 612712 kb |
| Host | smart-f43e2e87-de42-4180-a838-2e081819bc80 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000985067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.1000985067 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.518533382 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 4613000968 ps |
| CPU time | 674.61 seconds |
| Started | Jul 30 08:15:02 PM PDT 24 |
| Finished | Jul 30 08:26:17 PM PDT 24 |
| Peak memory | 613128 kb |
| Host | smart-b205755a-7f3d-4a14-82d7-9dd0aa690f05 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518533382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.518533382 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1136586321 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 5105373236 ps |
| CPU time | 596.27 seconds |
| Started | Jul 30 08:15:10 PM PDT 24 |
| Finished | Jul 30 08:25:06 PM PDT 24 |
| Peak memory | 612104 kb |
| Host | smart-953a546a-fbc0-4171-95ec-4c4cbb555367 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136586321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1136586321 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1882837051 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 5121814280 ps |
| CPU time | 702.11 seconds |
| Started | Jul 30 08:15:34 PM PDT 24 |
| Finished | Jul 30 08:27:17 PM PDT 24 |
| Peak memory | 612076 kb |
| Host | smart-2c214aa6-0056-4f58-825a-94573c2ebebb |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882837051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.1882837051 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1240783704 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 5384361800 ps |
| CPU time | 671.81 seconds |
| Started | Jul 30 08:18:06 PM PDT 24 |
| Finished | Jul 30 08:29:18 PM PDT 24 |
| Peak memory | 613160 kb |
| Host | smart-0e465ced-3e68-44d5-b362-78b8dd659b2c |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240783704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1240783704 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3483228462 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 2921444694 ps |
| CPU time | 329.8 seconds |
| Started | Jul 30 08:15:33 PM PDT 24 |
| Finished | Jul 30 08:21:03 PM PDT 24 |
| Peak memory | 608396 kb |
| Host | smart-1ac3a974-503e-4c27-af75-24e96326beb5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483228462 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.3483228462 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.901707280 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 3294775760 ps |
| CPU time | 478.08 seconds |
| Started | Jul 30 08:14:55 PM PDT 24 |
| Finished | Jul 30 08:22:53 PM PDT 24 |
| Peak memory | 609380 kb |
| Host | smart-c26c5b64-5014-4b54-8c24-77c63cd6105d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901707280 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.901707280 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.396823728 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 3102987041 ps |
| CPU time | 235.43 seconds |
| Started | Jul 30 08:18:33 PM PDT 24 |
| Finished | Jul 30 08:22:28 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-cf42205a-0b7e-4588-a4eb-09adc7bb94c2 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396823728 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.396823728 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1334917027 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 4528234500 ps |
| CPU time | 631.88 seconds |
| Started | Jul 30 08:15:04 PM PDT 24 |
| Finished | Jul 30 08:25:36 PM PDT 24 |
| Peak memory | 610420 kb |
| Host | smart-80293af4-e916-4539-9d26-d4e5747e8dd5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334917027 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.1334917027 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.616143350 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 4336444680 ps |
| CPU time | 534.76 seconds |
| Started | Jul 30 08:18:07 PM PDT 24 |
| Finished | Jul 30 08:27:02 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-d404c275-d68f-4f80-84d9-7b9e466403d6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616143350 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.616143350 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3586661994 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 4057663200 ps |
| CPU time | 523.03 seconds |
| Started | Jul 30 08:18:12 PM PDT 24 |
| Finished | Jul 30 08:26:55 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-3e71c6ee-e7ee-41b3-a9fc-98746d65056d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586661994 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.3586661994 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1930072106 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 4142918078 ps |
| CPU time | 495.63 seconds |
| Started | Jul 30 08:14:47 PM PDT 24 |
| Finished | Jul 30 08:23:03 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-26b06f2d-8529-4ff5-b2b5-ff13525d9803 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930072106 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.1930072106 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.4113743729 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 12068668860 ps |
| CPU time | 1479.09 seconds |
| Started | Jul 30 08:14:16 PM PDT 24 |
| Finished | Jul 30 08:38:55 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-d0b1a889-404f-4a13-9be1-6d02fc859724 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113743729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.4113743729 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3637370788 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 4033311060 ps |
| CPU time | 533.63 seconds |
| Started | Jul 30 08:16:30 PM PDT 24 |
| Finished | Jul 30 08:25:24 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-bf79b3ec-a212-4c0d-92b3-b5382073551e |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637370788 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.3637370788 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.4206152865 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 4736882410 ps |
| CPU time | 659.35 seconds |
| Started | Jul 30 08:16:11 PM PDT 24 |
| Finished | Jul 30 08:27:11 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-c461868e-1d43-4afd-8f86-220e10e5d281 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206152865 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.4206152865 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1025941118 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 2905477200 ps |
| CPU time | 315.37 seconds |
| Started | Jul 30 08:18:09 PM PDT 24 |
| Finished | Jul 30 08:23:24 PM PDT 24 |
| Peak memory | 609544 kb |
| Host | smart-03ae0ff3-3d5d-4567-9891-16ff66080986 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025941118 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.1025941118 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.131880263 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 18952630070 ps |
| CPU time | 4724.9 seconds |
| Started | Jul 30 08:13:14 PM PDT 24 |
| Finished | Jul 30 09:32:00 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-c9ee251d-a2e1-4d17-90a2-38c72a9ee495 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131880263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.131880263 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.718022717 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 33937067074 ps |
| CPU time | 5316.4 seconds |
| Started | Jul 30 08:19:59 PM PDT 24 |
| Finished | Jul 30 09:48:36 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-ef2c0fa0-9932-442b-a820-8600e078f276 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=718022717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.718022717 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.222486329 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 3827367960 ps |
| CPU time | 583.95 seconds |
| Started | Jul 30 08:13:23 PM PDT 24 |
| Finished | Jul 30 08:23:07 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-2b0ca269-92a1-4d69-bbc8-ec28ace40cf0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22248 6329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.222486329 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.3664787731 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 3431794882 ps |
| CPU time | 265.16 seconds |
| Started | Jul 30 08:14:05 PM PDT 24 |
| Finished | Jul 30 08:18:31 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-cfd1e086-7101-475a-b839-e562b8ad04da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664787731 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.3664787731 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.823296432 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 6844174444 ps |
| CPU time | 640.89 seconds |
| Started | Jul 30 08:12:55 PM PDT 24 |
| Finished | Jul 30 08:23:36 PM PDT 24 |
| Peak memory | 611048 kb |
| Host | smart-453246bc-1642-4253-b441-9b8a9bc096df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823296432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrn g_lc_hw_debug_en_test.823296432 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.2583167379 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 2989080996 ps |
| CPU time | 314.32 seconds |
| Started | Jul 30 08:18:32 PM PDT 24 |
| Finished | Jul 30 08:23:46 PM PDT 24 |
| Peak memory | 608340 kb |
| Host | smart-c226a9c6-0387-4c4b-8b7a-91c36531d0de |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583167379 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.2583167379 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.802280383 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 6103955192 ps |
| CPU time | 700.06 seconds |
| Started | Jul 30 08:08:37 PM PDT 24 |
| Finished | Jul 30 08:20:18 PM PDT 24 |
| Peak memory | 610776 kb |
| Host | smart-ecf5f97d-6e6a-4855-ad6a-77749adb4bb6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=802280383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.802280383 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.3249998288 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 6928568916 ps |
| CPU time | 1660.71 seconds |
| Started | Jul 30 08:12:22 PM PDT 24 |
| Finished | Jul 30 08:40:03 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-cf4f3cdf-8f5a-4b96-8b93-7f1d4b4d985f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249998288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.3249998288 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.1791868496 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 2951851288 ps |
| CPU time | 770.61 seconds |
| Started | Jul 30 08:12:45 PM PDT 24 |
| Finished | Jul 30 08:25:36 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-838e794a-b40a-4c85-bf13-78685253fbc1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791868496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.1791868496 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2661112858 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 7712701212 ps |
| CPU time | 1324.47 seconds |
| Started | Jul 30 08:12:47 PM PDT 24 |
| Finished | Jul 30 08:34:52 PM PDT 24 |
| Peak memory | 610952 kb |
| Host | smart-2f02e6c9-e884-4fa0-90f5-4cb1acb04fe5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2661112858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.2661112858 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3031791214 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 6190187794 ps |
| CPU time | 1015.9 seconds |
| Started | Jul 30 08:13:35 PM PDT 24 |
| Finished | Jul 30 08:30:32 PM PDT 24 |
| Peak memory | 610968 kb |
| Host | smart-284e9b29-0077-4c36-bcdc-faf943fdab45 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031791214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.3031791214 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.1165724008 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 3653899414 ps |
| CPU time | 704.34 seconds |
| Started | Jul 30 08:14:32 PM PDT 24 |
| Finished | Jul 30 08:26:17 PM PDT 24 |
| Peak memory | 615508 kb |
| Host | smart-53380891-5108-4a01-958a-ffe236980271 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165724008 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_edn_kat.1165724008 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.1501878422 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 8347259080 ps |
| CPU time | 1836.27 seconds |
| Started | Jul 30 08:20:12 PM PDT 24 |
| Finished | Jul 30 08:50:49 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-9d8ac30b-6d71-4f69-8451-a2ad8bc7cc78 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501878422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.1501878422 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1028528801 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 2687246904 ps |
| CPU time | 297.03 seconds |
| Started | Jul 30 08:14:38 PM PDT 24 |
| Finished | Jul 30 08:19:36 PM PDT 24 |
| Peak memory | 608692 kb |
| Host | smart-1e28e107-16c1-405e-8023-23659c31d4b2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10 28528801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.1028528801 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.1043000549 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 5622075718 ps |
| CPU time | 1239.6 seconds |
| Started | Jul 30 08:14:59 PM PDT 24 |
| Finished | Jul 30 08:35:39 PM PDT 24 |
| Peak memory | 609044 kb |
| Host | smart-1714b28e-1462-4faa-9e84-9ffa2b9b60f9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1043000549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.1043000549 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.221559876 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 2711849942 ps |
| CPU time | 172.45 seconds |
| Started | Jul 30 08:19:03 PM PDT 24 |
| Finished | Jul 30 08:21:57 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-931d3e01-141c-43be-b47b-e7395d0124b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221559876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.221559876 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.300732638 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 3376767578 ps |
| CPU time | 536.66 seconds |
| Started | Jul 30 08:18:26 PM PDT 24 |
| Finished | Jul 30 08:27:23 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-d1dca839-e72d-463a-8664-cbe4f64f3732 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=300732638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.300732638 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.514017331 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 2591072160 ps |
| CPU time | 290.05 seconds |
| Started | Jul 30 08:07:31 PM PDT 24 |
| Finished | Jul 30 08:12:21 PM PDT 24 |
| Peak memory | 608392 kb |
| Host | smart-e9303a87-e1f8-4928-acea-f4d9dc2ccb92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514017331 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_concurrency.514017331 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.1595472474 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 3007395710 ps |
| CPU time | 240.78 seconds |
| Started | Jul 30 08:07:31 PM PDT 24 |
| Finished | Jul 30 08:11:32 PM PDT 24 |
| Peak memory | 608300 kb |
| Host | smart-3a2e263b-8e2a-44e7-974e-c37facd0f2b4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595472474 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.1595472474 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.329704559 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 2712178456 ps |
| CPU time | 256.53 seconds |
| Started | Jul 30 08:07:41 PM PDT 24 |
| Finished | Jul 30 08:11:58 PM PDT 24 |
| Peak memory | 609592 kb |
| Host | smart-eb9583ca-6571-4f71-a6d4-3f9357ce608b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329704559 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.chip_sw_example_manufacturer.329704559 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.2873811482 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 2334419034 ps |
| CPU time | 134.76 seconds |
| Started | Jul 30 08:06:45 PM PDT 24 |
| Finished | Jul 30 08:08:59 PM PDT 24 |
| Peak memory | 609048 kb |
| Host | smart-806abbab-a377-4f38-a993-5f7e5d764252 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873811482 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.2873811482 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.4167623964 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 58103824692 ps |
| CPU time | 10563.7 seconds |
| Started | Jul 30 08:07:48 PM PDT 24 |
| Finished | Jul 30 11:03:53 PM PDT 24 |
| Peak memory | 624816 kb |
| Host | smart-8e6e55fc-a4aa-45e8-aadd-9060a1356692 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=4167623964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.4167623964 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.3758476023 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 5155080184 ps |
| CPU time | 617.03 seconds |
| Started | Jul 30 08:17:47 PM PDT 24 |
| Finished | Jul 30 08:28:05 PM PDT 24 |
| Peak memory | 610928 kb |
| Host | smart-e74b9f2b-3508-473e-a1c7-dc70da4fe2f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3758476023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.3758476023 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1630829752 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 5448244416 ps |
| CPU time | 1120.61 seconds |
| Started | Jul 30 08:11:08 PM PDT 24 |
| Finished | Jul 30 08:29:49 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-f52196aa-76ac-47f7-8b82-b1ac74d342cb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630829752 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.1630829752 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3574995402 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 5998041499 ps |
| CPU time | 996.03 seconds |
| Started | Jul 30 08:09:08 PM PDT 24 |
| Finished | Jul 30 08:25:45 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-b16195c9-453c-4437-9e75-0dce8e4ae180 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574995402 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.3574995402 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1693954841 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 7485998905 ps |
| CPU time | 1355.88 seconds |
| Started | Jul 30 08:17:59 PM PDT 24 |
| Finished | Jul 30 08:40:36 PM PDT 24 |
| Peak memory | 610184 kb |
| Host | smart-63a46d6e-46ea-4c33-869e-08f849e42a1d |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693954841 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1693954841 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2034884501 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 5140359418 ps |
| CPU time | 1054.3 seconds |
| Started | Jul 30 08:11:18 PM PDT 24 |
| Finished | Jul 30 08:28:52 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-d04ac4db-50ea-4256-abb2-66634e2a9605 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034884501 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.2034884501 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1570098326 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 3780129000 ps |
| CPU time | 372.99 seconds |
| Started | Jul 30 08:10:31 PM PDT 24 |
| Finished | Jul 30 08:16:44 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-d4ffe802-13e4-4849-9055-3261c1e959f8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570098326 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.1570098326 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1388560148 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 5586755098 ps |
| CPU time | 1248.87 seconds |
| Started | Jul 30 08:16:09 PM PDT 24 |
| Finished | Jul 30 08:36:58 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-7efec278-ef61-4ab8-a261-413619903d8a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388560148 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.1388560148 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.4209531387 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 3787153540 ps |
| CPU time | 877.28 seconds |
| Started | Jul 30 08:09:21 PM PDT 24 |
| Finished | Jul 30 08:23:59 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-84c8f3c6-2c98-4b58-b395-305dc20580f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209531387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.4209531387 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.4284830246 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4370321826 ps |
| CPU time | 620.48 seconds |
| Started | Jul 30 08:09:26 PM PDT 24 |
| Finished | Jul 30 08:19:46 PM PDT 24 |
| Peak memory | 610232 kb |
| Host | smart-1c09f15b-51cb-4070-9c24-b1b9c87cc41a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=4284830246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.4284830246 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1492707129 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4807654076 ps |
| CPU time | 806.39 seconds |
| Started | Jul 30 08:16:35 PM PDT 24 |
| Finished | Jul 30 08:30:02 PM PDT 24 |
| Peak memory | 610216 kb |
| Host | smart-27d2f9f1-97b3-4e88-baef-632fbc5a662e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1492707129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1492707129 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1834457721 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 3061469882 ps |
| CPU time | 444.72 seconds |
| Started | Jul 30 08:18:36 PM PDT 24 |
| Finished | Jul 30 08:26:01 PM PDT 24 |
| Peak memory | 609764 kb |
| Host | smart-0bee7059-6192-4c96-a3e1-ac6d74e8679d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834457 721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.1834457721 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.2004566590 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 20971889791 ps |
| CPU time | 2531.55 seconds |
| Started | Jul 30 08:10:06 PM PDT 24 |
| Finished | Jul 30 08:52:19 PM PDT 24 |
| Peak memory | 613528 kb |
| Host | smart-bf8a6f2f-05f1-4779-ab54-5fa9c48cbdc4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004566590 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.2004566590 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2953844044 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 20048789687 ps |
| CPU time | 2057.3 seconds |
| Started | Jul 30 08:18:12 PM PDT 24 |
| Finished | Jul 30 08:52:30 PM PDT 24 |
| Peak memory | 615552 kb |
| Host | smart-b20f0242-7062-4fb1-98fc-6f4a54399303 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2953844044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.2953844044 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1399618470 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 2938671966 ps |
| CPU time | 148.02 seconds |
| Started | Jul 30 08:23:24 PM PDT 24 |
| Finished | Jul 30 08:25:52 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-4364693b-d3cf-46ec-9f9d-19f70a4920e1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1399618470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.1399618470 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.1710198601 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2083056829 ps |
| CPU time | 270.98 seconds |
| Started | Jul 30 08:17:33 PM PDT 24 |
| Finished | Jul 30 08:22:05 PM PDT 24 |
| Peak memory | 608588 kb |
| Host | smart-783b0372-51a2-45cd-b76c-30732feab472 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710198601 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.1710198601 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.2167092037 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 2861327680 ps |
| CPU time | 240.18 seconds |
| Started | Jul 30 08:13:01 PM PDT 24 |
| Finished | Jul 30 08:17:02 PM PDT 24 |
| Peak memory | 608468 kb |
| Host | smart-a70e0a3a-8f2f-4b76-8796-7e50db93e25a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167092037 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.2167092037 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.2140878680 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 3089259592 ps |
| CPU time | 278.13 seconds |
| Started | Jul 30 08:14:39 PM PDT 24 |
| Finished | Jul 30 08:19:17 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-2f6b5404-9ff7-4388-875e-652e5372b37b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140878680 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.2140878680 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1706872170 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 2331361525 ps |
| CPU time | 233.86 seconds |
| Started | Jul 30 08:13:59 PM PDT 24 |
| Finished | Jul 30 08:17:53 PM PDT 24 |
| Peak memory | 609388 kb |
| Host | smart-86b47c2c-edb9-4ca6-9c59-0593bc978188 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706872170 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.1706872170 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.4145788139 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 3605598270 ps |
| CPU time | 230.55 seconds |
| Started | Jul 30 08:16:31 PM PDT 24 |
| Finished | Jul 30 08:20:21 PM PDT 24 |
| Peak memory | 609804 kb |
| Host | smart-1082fc6f-6cc4-419a-9b16-473775d92724 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145788139 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.4145788139 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.3873143696 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 7787263172 ps |
| CPU time | 1992.64 seconds |
| Started | Jul 30 08:13:20 PM PDT 24 |
| Finished | Jul 30 08:46:33 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-6e92575a-2629-49c0-ac9c-f10a3c89ec98 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873143696 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_multistream.3873143696 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.1142450045 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 3678974920 ps |
| CPU time | 263.17 seconds |
| Started | Jul 30 08:12:38 PM PDT 24 |
| Finished | Jul 30 08:17:01 PM PDT 24 |
| Peak memory | 609668 kb |
| Host | smart-841baa89-06bc-46e8-a29c-918b86f8daa7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142450045 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.1142450045 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.1604484226 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 3380940520 ps |
| CPU time | 457.8 seconds |
| Started | Jul 30 08:18:31 PM PDT 24 |
| Finished | Jul 30 08:26:09 PM PDT 24 |
| Peak memory | 609600 kb |
| Host | smart-36f50a9b-b566-4ac9-9f84-edc5488ef11a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604484226 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.1604484226 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3819160477 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 3119641180 ps |
| CPU time | 439.26 seconds |
| Started | Jul 30 08:09:18 PM PDT 24 |
| Finished | Jul 30 08:16:38 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-345420be-19f3-4b17-9550-e690f95fbf55 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819160477 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.3819160477 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2794151341 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 4782271998 ps |
| CPU time | 832.95 seconds |
| Started | Jul 30 08:08:11 PM PDT 24 |
| Finished | Jul 30 08:22:05 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-45be29af-8d1a-47d7-86d4-258e39baa70a |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794151341 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.2794151341 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.882264074 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 5469378940 ps |
| CPU time | 737.78 seconds |
| Started | Jul 30 08:09:39 PM PDT 24 |
| Finished | Jul 30 08:21:57 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-6960bdba-ea00-4025-94ec-bf39003d0165 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882264074 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.882264074 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1270750609 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 4988007720 ps |
| CPU time | 936.99 seconds |
| Started | Jul 30 08:08:54 PM PDT 24 |
| Finished | Jul 30 08:24:31 PM PDT 24 |
| Peak memory | 609228 kb |
| Host | smart-9dbc3355-3f33-479a-b24a-707533bacfd0 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270750609 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.1270750609 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.1087224449 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 66527417273 ps |
| CPU time | 12019.7 seconds |
| Started | Jul 30 08:08:27 PM PDT 24 |
| Finished | Jul 30 11:28:48 PM PDT 24 |
| Peak memory | 624772 kb |
| Host | smart-af686de6-5b43-404f-a745-e35966fc02db |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1087224449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.1087224449 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2316140497 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 8029951470 ps |
| CPU time | 1864.77 seconds |
| Started | Jul 30 08:13:22 PM PDT 24 |
| Finished | Jul 30 08:44:28 PM PDT 24 |
| Peak memory | 617868 kb |
| Host | smart-1c0b69b6-427c-4c77-9845-d67947fa86af |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316 140497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.2316140497 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.4111935151 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 13233015824 ps |
| CPU time | 2049.49 seconds |
| Started | Jul 30 08:13:18 PM PDT 24 |
| Finished | Jul 30 08:47:28 PM PDT 24 |
| Peak memory | 618156 kb |
| Host | smart-6d732321-8459-47c8-898e-3abe6825784c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4111935151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.4111935151 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.701811939 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 12610121794 ps |
| CPU time | 2152.89 seconds |
| Started | Jul 30 08:15:52 PM PDT 24 |
| Finished | Jul 30 08:51:45 PM PDT 24 |
| Peak memory | 617208 kb |
| Host | smart-3bffbe2a-6187-49e6-92a5-c0798142c201 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=701811939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en_ reduced_freq.701811939 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1304480755 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 8892793804 ps |
| CPU time | 2246.83 seconds |
| Started | Jul 30 08:13:45 PM PDT 24 |
| Finished | Jul 30 08:51:13 PM PDT 24 |
| Peak memory | 617888 kb |
| Host | smart-f6eddf0b-df10-4f0f-8c8e-d982c19dea54 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1304480755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.1304480755 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.71281134 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 13406596312 ps |
| CPU time | 2919.69 seconds |
| Started | Jul 30 08:13:33 PM PDT 24 |
| Finished | Jul 30 09:02:13 PM PDT 24 |
| Peak memory | 611312 kb |
| Host | smart-47dcfcae-cc95-494f-9ffc-6979f45e811a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712811 34 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.71281134 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3189439267 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 7272753524 ps |
| CPU time | 1395.45 seconds |
| Started | Jul 30 08:12:40 PM PDT 24 |
| Finished | Jul 30 08:35:55 PM PDT 24 |
| Peak memory | 611368 kb |
| Host | smart-0be29dba-e48a-4965-a85e-fda2916a1595 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31894 39267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.3189439267 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.253662008 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 16801646056 ps |
| CPU time | 5100.48 seconds |
| Started | Jul 30 08:13:39 PM PDT 24 |
| Finished | Jul 30 09:38:40 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-261665f2-cf84-4f97-82a3-4e3399ba1501 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25366 2008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.253662008 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.4078412315 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 2392194200 ps |
| CPU time | 281.31 seconds |
| Started | Jul 30 08:12:57 PM PDT 24 |
| Finished | Jul 30 08:17:38 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-528c4f66-cce5-45b1-a372-5d0230940571 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078412315 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.4078412315 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.1481531022 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 3050945400 ps |
| CPU time | 325.34 seconds |
| Started | Jul 30 08:09:45 PM PDT 24 |
| Finished | Jul 30 08:15:11 PM PDT 24 |
| Peak memory | 609596 kb |
| Host | smart-1ed2687f-c70c-4481-bf3f-08b0f466e686 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481531022 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.1481531022 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.1534468234 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 2426161810 ps |
| CPU time | 321.27 seconds |
| Started | Jul 30 08:14:15 PM PDT 24 |
| Finished | Jul 30 08:19:36 PM PDT 24 |
| Peak memory | 609612 kb |
| Host | smart-641944d5-8d8f-4a93-9e46-d4311dc20c62 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534468234 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.1534468234 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.607074320 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 3178587968 ps |
| CPU time | 364.4 seconds |
| Started | Jul 30 08:14:43 PM PDT 24 |
| Finished | Jul 30 08:20:48 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-be11feff-4ff4-4d16-aa44-9f42e492aed8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607074320 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_kmac_mode_cshake.607074320 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1194314423 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 3015945612 ps |
| CPU time | 397.54 seconds |
| Started | Jul 30 08:14:45 PM PDT 24 |
| Finished | Jul 30 08:21:23 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-43bb2172-4f9a-400f-83b9-a164d92fc0de |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194314423 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.1194314423 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3022660575 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 3754629960 ps |
| CPU time | 327.87 seconds |
| Started | Jul 30 08:13:37 PM PDT 24 |
| Finished | Jul 30 08:19:05 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-2e757fc4-9256-40db-8281-7b06477d9e33 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022660575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.3022660575 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.341080914 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 3890724984 ps |
| CPU time | 325.91 seconds |
| Started | Jul 30 08:17:43 PM PDT 24 |
| Finished | Jul 30 08:23:09 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-60204d72-c42d-424d-bff2-2a6b7885d641 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34108091 4 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.341080914 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.262299694 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 3602674762 ps |
| CPU time | 366.68 seconds |
| Started | Jul 30 08:17:22 PM PDT 24 |
| Finished | Jul 30 08:23:29 PM PDT 24 |
| Peak memory | 609620 kb |
| Host | smart-179d2db6-1cf5-4441-8c24-398518d35163 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262299694 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_smoketest.262299694 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2708084442 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 3371312500 ps |
| CPU time | 318.54 seconds |
| Started | Jul 30 08:09:37 PM PDT 24 |
| Finished | Jul 30 08:14:56 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-d8540663-10d3-4823-87e1-9c0ee0e24982 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708084442 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.2708084442 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.680885633 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 5228622172 ps |
| CPU time | 704.17 seconds |
| Started | Jul 30 08:15:32 PM PDT 24 |
| Finished | Jul 30 08:27:16 PM PDT 24 |
| Peak memory | 610848 kb |
| Host | smart-aee25b69-eca0-448a-99f8-014e989fb82b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=680885633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.680885633 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.285564694 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 11174043022 ps |
| CPU time | 1047.24 seconds |
| Started | Jul 30 08:09:33 PM PDT 24 |
| Finished | Jul 30 08:27:01 PM PDT 24 |
| Peak memory | 621260 kb |
| Host | smart-de948628-fb91-4862-93a3-82f17e5c0f11 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285564694 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.285564694 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3551586194 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 2744277414 ps |
| CPU time | 116.17 seconds |
| Started | Jul 30 08:10:48 PM PDT 24 |
| Finished | Jul 30 08:12:44 PM PDT 24 |
| Peak memory | 617716 kb |
| Host | smart-f1b24451-95f5-4bb7-872f-7542af390689 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3551586194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.3551586194 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2246466234 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2797450497 ps |
| CPU time | 120.22 seconds |
| Started | Jul 30 08:10:30 PM PDT 24 |
| Finished | Jul 30 08:12:30 PM PDT 24 |
| Peak memory | 617040 kb |
| Host | smart-fa4713e1-9434-4058-b671-c2ac196e7364 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246466234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2246466234 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.4109647312 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 49200509427 ps |
| CPU time | 5563.35 seconds |
| Started | Jul 30 08:10:06 PM PDT 24 |
| Finished | Jul 30 09:42:50 PM PDT 24 |
| Peak memory | 620844 kb |
| Host | smart-a500315f-21a8-4746-a386-33c7c81c379c |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109647312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_dev.4109647312 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3923321314 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 50109197000 ps |
| CPU time | 5061.62 seconds |
| Started | Jul 30 08:11:03 PM PDT 24 |
| Finished | Jul 30 09:35:25 PM PDT 24 |
| Peak memory | 620920 kb |
| Host | smart-39814b3d-e4fd-4dd0-b8e4-d28ea038f42f |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923321314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_lc_walkthrough_prod.3923321314 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.335656254 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 10242583760 ps |
| CPU time | 1104.46 seconds |
| Started | Jul 30 08:10:06 PM PDT 24 |
| Finished | Jul 30 08:28:31 PM PDT 24 |
| Peak memory | 619012 kb |
| Host | smart-dab597f4-0bd3-4baf-a8f8-9a6d0f66ddef |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=335656254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.335656254 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1694779286 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 45217207675 ps |
| CPU time | 5272.25 seconds |
| Started | Jul 30 08:10:26 PM PDT 24 |
| Finished | Jul 30 09:38:20 PM PDT 24 |
| Peak memory | 616960 kb |
| Host | smart-bec458d4-300e-463c-9827-da4ccc1dc8c9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694779286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.1694779286 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2313308647 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 24867660377 ps |
| CPU time | 1832.48 seconds |
| Started | Jul 30 08:09:49 PM PDT 24 |
| Finished | Jul 30 08:40:21 PM PDT 24 |
| Peak memory | 619908 kb |
| Host | smart-2e5485a3-39f5-4062-96e6-5be903be824d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2313308647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.2313308647 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.785587594 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 17109254628 ps |
| CPU time | 3354.52 seconds |
| Started | Jul 30 08:13:19 PM PDT 24 |
| Finished | Jul 30 09:09:14 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-f5c5d1a9-dce4-455c-927d-5a9fde8ec6f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=785587594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.785587594 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.914485897 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 18783075082 ps |
| CPU time | 3740.63 seconds |
| Started | Jul 30 08:13:20 PM PDT 24 |
| Finished | Jul 30 09:15:41 PM PDT 24 |
| Peak memory | 609220 kb |
| Host | smart-f9584fc1-c415-43e1-99aa-540028e936ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=914485897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.914485897 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3421009416 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 25300929368 ps |
| CPU time | 4667.37 seconds |
| Started | Jul 30 08:16:57 PM PDT 24 |
| Finished | Jul 30 09:34:46 PM PDT 24 |
| Peak memory | 610316 kb |
| Host | smart-c531c0ff-d48c-471a-a7df-13920a88e9d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421009416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3421009416 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3788580904 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 3359221216 ps |
| CPU time | 511.9 seconds |
| Started | Jul 30 08:11:46 PM PDT 24 |
| Finished | Jul 30 08:20:18 PM PDT 24 |
| Peak memory | 609896 kb |
| Host | smart-4d4720ff-a55d-4dcf-b169-d2b46e36ad2d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788580904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.3788580904 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.312525076 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 5498755798 ps |
| CPU time | 1105.26 seconds |
| Started | Jul 30 08:11:22 PM PDT 24 |
| Finished | Jul 30 08:29:48 PM PDT 24 |
| Peak memory | 610316 kb |
| Host | smart-5809d131-9c30-4835-ae88-ea4501ef4ad0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=312525076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.312525076 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.3263389848 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 5653189400 ps |
| CPU time | 1066.21 seconds |
| Started | Jul 30 08:19:21 PM PDT 24 |
| Finished | Jul 30 08:37:07 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-8ab61aab-ef41-4a27-8604-8dd25694ed52 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263389848 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.3263389848 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3180411119 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 3160293085 ps |
| CPU time | 277.78 seconds |
| Started | Jul 30 08:09:27 PM PDT 24 |
| Finished | Jul 30 08:14:05 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-18ef7b4a-1b11-4df3-82bf-0d1488c14a31 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180411119 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.3180411119 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1435304579 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 8761629020 ps |
| CPU time | 1341.52 seconds |
| Started | Jul 30 08:09:42 PM PDT 24 |
| Finished | Jul 30 08:32:04 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-fc6657af-c0a3-4be7-9767-701871a15301 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1435304579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.1435304579 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1934542193 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 6796981116 ps |
| CPU time | 1181.08 seconds |
| Started | Jul 30 08:09:37 PM PDT 24 |
| Finished | Jul 30 08:29:19 PM PDT 24 |
| Peak memory | 610412 kb |
| Host | smart-08510c69-d7b1-4e3c-b26a-b0bf7d606c1b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1934542193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.1934542193 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.4143840596 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 7795675996 ps |
| CPU time | 1271.18 seconds |
| Started | Jul 30 08:09:14 PM PDT 24 |
| Finished | Jul 30 08:30:25 PM PDT 24 |
| Peak memory | 610480 kb |
| Host | smart-f6b53230-8e12-463f-9640-2a149362302a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4143840596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.4143840596 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1499579536 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 4253546520 ps |
| CPU time | 879.17 seconds |
| Started | Jul 30 08:09:34 PM PDT 24 |
| Finished | Jul 30 08:24:13 PM PDT 24 |
| Peak memory | 609768 kb |
| Host | smart-17a12d05-150b-4587-b5d3-57805dc10298 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1499579536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1499579536 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3825635383 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 3336759304 ps |
| CPU time | 285.97 seconds |
| Started | Jul 30 08:17:42 PM PDT 24 |
| Finished | Jul 30 08:22:28 PM PDT 24 |
| Peak memory | 608396 kb |
| Host | smart-2c373796-6df1-4f78-98cf-43c55f28583e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825635383 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.3825635383 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.95410433 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 3385829368 ps |
| CPU time | 218.69 seconds |
| Started | Jul 30 08:08:39 PM PDT 24 |
| Finished | Jul 30 08:12:18 PM PDT 24 |
| Peak memory | 610276 kb |
| Host | smart-456dd409-e049-45c0-9d08-550927b43436 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95410433 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.95410433 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.3893117934 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 2671274982 ps |
| CPU time | 288.86 seconds |
| Started | Jul 30 08:15:30 PM PDT 24 |
| Finished | Jul 30 08:20:19 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-63852aba-2cdc-430b-b33a-091774dce9a4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893117934 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.3893117934 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.565248895 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 4157416320 ps |
| CPU time | 797.06 seconds |
| Started | Jul 30 08:18:03 PM PDT 24 |
| Finished | Jul 30 08:31:21 PM PDT 24 |
| Peak memory | 609340 kb |
| Host | smart-eb7bddf7-51f9-479b-95b7-c36b1199bf0f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565248895 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.565248895 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.116865176 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 4844256684 ps |
| CPU time | 405.89 seconds |
| Started | Jul 30 08:16:21 PM PDT 24 |
| Finished | Jul 30 08:23:07 PM PDT 24 |
| Peak memory | 609416 kb |
| Host | smart-ac54be36-b9cb-417f-b9e6-432e865f8505 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116865176 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.116865176 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_virus.2569230192 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 5980702616 ps |
| CPU time | 1477.64 seconds |
| Started | Jul 30 08:24:08 PM PDT 24 |
| Finished | Jul 30 08:48:46 PM PDT 24 |
| Peak memory | 625152 kb |
| Host | smart-3a53d671-e12d-423f-8876-203e357b9b30 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2569230192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.2569230192 |
| Directory | /workspace/2.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3260990606 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 11130420129 ps |
| CPU time | 1602.47 seconds |
| Started | Jul 30 08:10:02 PM PDT 24 |
| Finished | Jul 30 08:36:45 PM PDT 24 |
| Peak memory | 611248 kb |
| Host | smart-073bef0a-5f2d-426d-b32a-b47f65598e70 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260 990606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.3260990606 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2803776826 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 20287880588 ps |
| CPU time | 1978.79 seconds |
| Started | Jul 30 08:13:56 PM PDT 24 |
| Finished | Jul 30 08:46:55 PM PDT 24 |
| Peak memory | 610848 kb |
| Host | smart-d33af055-6063-498d-8d00-e56042018335 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280 3776826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.2803776826 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2030758307 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 17545805588 ps |
| CPU time | 2084.2 seconds |
| Started | Jul 30 08:10:32 PM PDT 24 |
| Finished | Jul 30 08:45:16 PM PDT 24 |
| Peak memory | 611528 kb |
| Host | smart-6cc5b79a-c1e8-4659-8ea7-12f94347e94f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2030758307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2030758307 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2277103271 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 22735613980 ps |
| CPU time | 1387.49 seconds |
| Started | Jul 30 08:15:10 PM PDT 24 |
| Finished | Jul 30 08:38:18 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-3cb6a9d4-9674-4d8b-9cd9-628342158321 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2277103271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2277103271 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2268594481 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 9930157100 ps |
| CPU time | 616.95 seconds |
| Started | Jul 30 08:10:54 PM PDT 24 |
| Finished | Jul 30 08:21:11 PM PDT 24 |
| Peak memory | 609480 kb |
| Host | smart-d3c06b9c-1062-489a-a116-707919640894 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268594481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.2268594481 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1660473323 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 7983846100 ps |
| CPU time | 551.74 seconds |
| Started | Jul 30 08:14:24 PM PDT 24 |
| Finished | Jul 30 08:23:38 PM PDT 24 |
| Peak memory | 616776 kb |
| Host | smart-ee7351ce-a22e-4570-b917-834fbab02934 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1660473323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1660473323 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2480540985 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 8829105296 ps |
| CPU time | 511.21 seconds |
| Started | Jul 30 08:10:28 PM PDT 24 |
| Finished | Jul 30 08:19:00 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-5912505e-87ce-4d00-8eaa-294348838acb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480540985 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.2480540985 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.830337215 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 3932367582 ps |
| CPU time | 407.98 seconds |
| Started | Jul 30 08:14:36 PM PDT 24 |
| Finished | Jul 30 08:21:24 PM PDT 24 |
| Peak memory | 609716 kb |
| Host | smart-80d03642-11a9-41b3-a969-54c44472a319 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830337215 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.830337215 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1747695963 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 4176754260 ps |
| CPU time | 538.74 seconds |
| Started | Jul 30 08:10:11 PM PDT 24 |
| Finished | Jul 30 08:19:10 PM PDT 24 |
| Peak memory | 616280 kb |
| Host | smart-a76bf4f9-8775-43cd-b21e-5789beca2b7c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1747695963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.1747695963 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3320860457 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 9549368604 ps |
| CPU time | 1607.34 seconds |
| Started | Jul 30 08:10:53 PM PDT 24 |
| Finished | Jul 30 08:37:41 PM PDT 24 |
| Peak memory | 611164 kb |
| Host | smart-0867612d-7bf2-4166-812f-b6e6666d3d3e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320860457 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3320860457 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2448750285 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 4865533240 ps |
| CPU time | 579.3 seconds |
| Started | Jul 30 08:10:48 PM PDT 24 |
| Finished | Jul 30 08:20:27 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-b01fe21e-9b7f-4b59-866b-8d0e060e0aed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448750285 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.2448750285 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2808337015 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 26412473726 ps |
| CPU time | 2582.61 seconds |
| Started | Jul 30 08:14:54 PM PDT 24 |
| Finished | Jul 30 08:57:57 PM PDT 24 |
| Peak memory | 611660 kb |
| Host | smart-ef6c4140-62e9-4544-b2a9-6684d02f6dbd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2808337015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2808337015 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.4078863039 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 24399798018 ps |
| CPU time | 1600.28 seconds |
| Started | Jul 30 08:15:55 PM PDT 24 |
| Finished | Jul 30 08:42:35 PM PDT 24 |
| Peak memory | 611016 kb |
| Host | smart-4782322f-63aa-458e-b910-617bee5455b8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4078863039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.4078863039 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2036679612 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 26721147736 ps |
| CPU time | 3062.76 seconds |
| Started | Jul 30 08:10:29 PM PDT 24 |
| Finished | Jul 30 09:01:32 PM PDT 24 |
| Peak memory | 611884 kb |
| Host | smart-f2b9ff3c-b26c-4586-85c1-015065df023c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036679612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2036679612 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1371357789 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 7205114488 ps |
| CPU time | 646.7 seconds |
| Started | Jul 30 08:15:57 PM PDT 24 |
| Finished | Jul 30 08:26:44 PM PDT 24 |
| Peak memory | 611036 kb |
| Host | smart-836baf63-7521-49fa-bf61-cb8814aa1ff0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1371357789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.1371357789 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1801652916 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 2955636390 ps |
| CPU time | 256.02 seconds |
| Started | Jul 30 08:09:51 PM PDT 24 |
| Finished | Jul 30 08:14:07 PM PDT 24 |
| Peak memory | 609668 kb |
| Host | smart-b929533c-4c4f-4f60-8774-9721f1204bfa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801652916 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.1801652916 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.5077844 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4680810216 ps |
| CPU time | 567.88 seconds |
| Started | Jul 30 08:10:06 PM PDT 24 |
| Finished | Jul 30 08:19:34 PM PDT 24 |
| Peak memory | 617508 kb |
| Host | smart-41a1c98e-0080-4052-821e-992039e08a87 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=5077844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.5077844 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1668216514 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 5425094532 ps |
| CPU time | 409.8 seconds |
| Started | Jul 30 08:17:34 PM PDT 24 |
| Finished | Jul 30 08:24:24 PM PDT 24 |
| Peak memory | 608672 kb |
| Host | smart-4d8c10d9-1a31-4c23-9383-76cbbe832362 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16682165 14 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1668216514 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3658197335 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 6658870970 ps |
| CPU time | 579.74 seconds |
| Started | Jul 30 08:15:51 PM PDT 24 |
| Finished | Jul 30 08:25:31 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-69d8a94d-8665-4f33-97e7-815f0f72c021 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3658197335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.3658197335 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1119911544 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 6788718898 ps |
| CPU time | 507.52 seconds |
| Started | Jul 30 08:18:22 PM PDT 24 |
| Finished | Jul 30 08:26:49 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-2f0998c5-bce1-4c9e-a795-9894946fcbdb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119911544 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.1119911544 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.749203358 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 6845621960 ps |
| CPU time | 1037.6 seconds |
| Started | Jul 30 08:11:49 PM PDT 24 |
| Finished | Jul 30 08:29:07 PM PDT 24 |
| Peak memory | 610864 kb |
| Host | smart-bac3bd16-17a6-4dd3-a221-d3b6eecf78a9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749203358 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.749203358 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.4091932872 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 4024236340 ps |
| CPU time | 353.6 seconds |
| Started | Jul 30 08:11:35 PM PDT 24 |
| Finished | Jul 30 08:17:29 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-3da286c7-d1a3-457a-bd7f-0c000809b694 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091932872 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.4091932872 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3538077807 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 6168254940 ps |
| CPU time | 450.31 seconds |
| Started | Jul 30 08:18:13 PM PDT 24 |
| Finished | Jul 30 08:25:44 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-4cbbed19-175e-45c2-8d70-61b35c3dd59c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538077807 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.3538077807 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.4131059724 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 4793923144 ps |
| CPU time | 702.02 seconds |
| Started | Jul 30 08:11:26 PM PDT 24 |
| Finished | Jul 30 08:23:08 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-d41897cc-716f-4bb7-a313-b26e1b64a651 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413 1059724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.4131059724 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1364338637 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 8423384737 ps |
| CPU time | 684.8 seconds |
| Started | Jul 30 08:12:55 PM PDT 24 |
| Finished | Jul 30 08:24:20 PM PDT 24 |
| Peak memory | 624824 kb |
| Host | smart-178bce0c-3bea-416d-aaf4-ea5cc2c0cbb8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364338637 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.1364338637 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2122991931 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 11716262102 ps |
| CPU time | 1921.2 seconds |
| Started | Jul 30 08:10:38 PM PDT 24 |
| Finished | Jul 30 08:42:40 PM PDT 24 |
| Peak memory | 610976 kb |
| Host | smart-4eaaef1a-7125-49f0-a695-7d3432ed0cad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2122991931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.2122991931 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1590411262 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 6803769612 ps |
| CPU time | 710.72 seconds |
| Started | Jul 30 08:10:49 PM PDT 24 |
| Finished | Jul 30 08:22:39 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-336f537b-0054-47dc-8b56-cde0e6f69f23 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590411262 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.1590411262 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1891473107 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 5267276596 ps |
| CPU time | 726.03 seconds |
| Started | Jul 30 08:07:42 PM PDT 24 |
| Finished | Jul 30 08:19:49 PM PDT 24 |
| Peak memory | 641724 kb |
| Host | smart-0fbc4a6f-d17c-4ef8-a62b-62a16414c93a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1891473107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.1891473107 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.56835320 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 3139033812 ps |
| CPU time | 328.77 seconds |
| Started | Jul 30 08:19:29 PM PDT 24 |
| Finished | Jul 30 08:24:58 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-b1d06f3a-814b-4e56-9d2b-539a1081bd24 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56835320 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_rstmgr_smoketest.56835320 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1339410290 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 4762930676 ps |
| CPU time | 450.61 seconds |
| Started | Jul 30 08:11:02 PM PDT 24 |
| Finished | Jul 30 08:18:33 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-80fa02b3-2a8e-43bc-9975-af7c9088d78a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339410290 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.1339410290 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2986114032 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 3404105864 ps |
| CPU time | 256.03 seconds |
| Started | Jul 30 08:09:30 PM PDT 24 |
| Finished | Jul 30 08:13:46 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-e23b53a2-dd85-44f9-afb9-aa39a0112b38 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986114032 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.2986114032 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.849234000 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3226900896 ps |
| CPU time | 307.6 seconds |
| Started | Jul 30 08:17:36 PM PDT 24 |
| Finished | Jul 30 08:22:44 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-7a49c709-c801-4ecb-8d14-894f5fbbbbb5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=849234000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.849234000 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1813211646 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 3503118663 ps |
| CPU time | 219.7 seconds |
| Started | Jul 30 08:15:41 PM PDT 24 |
| Finished | Jul 30 08:19:21 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-19bb2e8d-bc9f-4763-908c-0242836d15c5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813211646 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.1813211646 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3169868911 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2678116256 ps |
| CPU time | 305.01 seconds |
| Started | Jul 30 08:15:42 PM PDT 24 |
| Finished | Jul 30 08:20:47 PM PDT 24 |
| Peak memory | 617264 kb |
| Host | smart-c3928e94-a44e-4f5e-951a-52409a65e23e |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169868911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.3169868911 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.318190045 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 5064764824 ps |
| CPU time | 983.44 seconds |
| Started | Jul 30 08:11:44 PM PDT 24 |
| Finished | Jul 30 08:28:08 PM PDT 24 |
| Peak memory | 608924 kb |
| Host | smart-b7748bc4-de7e-4f59-85e9-c35bb66e5cfb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31819 0045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.318190045 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2309878097 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 5747725480 ps |
| CPU time | 1131.67 seconds |
| Started | Jul 30 08:13:23 PM PDT 24 |
| Finished | Jul 30 08:32:14 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-0a4a6e0a-ea78-4207-859b-8f31d1777f70 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2309878097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.2309878097 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2206499420 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 5056395762 ps |
| CPU time | 485.75 seconds |
| Started | Jul 30 08:15:07 PM PDT 24 |
| Finished | Jul 30 08:23:13 PM PDT 24 |
| Peak memory | 624368 kb |
| Host | smart-308489ba-0d30-4124-b1b2-568489b0eac1 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206499420 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.2206499420 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2829728769 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 5766334752 ps |
| CPU time | 435.2 seconds |
| Started | Jul 30 08:15:11 PM PDT 24 |
| Finished | Jul 30 08:22:27 PM PDT 24 |
| Peak memory | 620192 kb |
| Host | smart-811d5191-4da0-40e2-a274-63985a57f45d |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829728769 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.2829728769 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.585652925 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 4458718424 ps |
| CPU time | 440.72 seconds |
| Started | Jul 30 08:14:42 PM PDT 24 |
| Finished | Jul 30 08:22:03 PM PDT 24 |
| Peak memory | 620108 kb |
| Host | smart-c05f274d-8147-40b7-8038-7cf0aa135050 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585652 925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.585652925 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1521899761 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 2779304580 ps |
| CPU time | 270.01 seconds |
| Started | Jul 30 08:17:53 PM PDT 24 |
| Finished | Jul 30 08:22:24 PM PDT 24 |
| Peak memory | 608384 kb |
| Host | smart-7432004c-6d89-4606-98e9-165a06fd0f91 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521899761 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.1521899761 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.1740753166 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 3476551688 ps |
| CPU time | 315.19 seconds |
| Started | Jul 30 08:10:48 PM PDT 24 |
| Finished | Jul 30 08:16:04 PM PDT 24 |
| Peak memory | 609560 kb |
| Host | smart-9b9552a0-e0da-4e3c-b9e2-a7b4c262ceca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740753166 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.1740753166 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.4045675764 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 3464229888 ps |
| CPU time | 349.06 seconds |
| Started | Jul 30 08:18:16 PM PDT 24 |
| Finished | Jul 30 08:24:06 PM PDT 24 |
| Peak memory | 608412 kb |
| Host | smart-23dcaa35-e8b4-4ef0-b1e4-60a7734504f0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045675764 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.4045675764 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.553687456 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 9099554352 ps |
| CPU time | 1205.01 seconds |
| Started | Jul 30 08:13:18 PM PDT 24 |
| Finished | Jul 30 08:33:23 PM PDT 24 |
| Peak memory | 610316 kb |
| Host | smart-d4228f80-55bf-409f-8420-bcd2136eff70 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55368745 6 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.553687456 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3831019862 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 2796062892 ps |
| CPU time | 255.67 seconds |
| Started | Jul 30 08:13:32 PM PDT 24 |
| Finished | Jul 30 08:17:48 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-9be2af26-95ec-4e44-b75f-755633382137 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831019 862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.3831019862 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1680014293 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3661388430 ps |
| CPU time | 319.31 seconds |
| Started | Jul 30 08:07:46 PM PDT 24 |
| Finished | Jul 30 08:13:05 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-7204bf79-877b-40c9-b6a3-0863f6edf073 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680014293 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.1680014293 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3422989272 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 9246415588 ps |
| CPU time | 1114.29 seconds |
| Started | Jul 30 08:07:49 PM PDT 24 |
| Finished | Jul 30 08:26:24 PM PDT 24 |
| Peak memory | 610688 kb |
| Host | smart-b7c43652-429b-41d6-be67-5138719533bc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422989272 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.3422989272 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3953807114 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 7658748908 ps |
| CPU time | 881.55 seconds |
| Started | Jul 30 08:16:01 PM PDT 24 |
| Finished | Jul 30 08:30:42 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-2541f09b-ffb6-4dc4-ab27-b677bb328970 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953807114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.3953807114 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2556824240 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 8151332056 ps |
| CPU time | 882.13 seconds |
| Started | Jul 30 08:14:16 PM PDT 24 |
| Finished | Jul 30 08:28:59 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-7762d863-889d-4bee-85e8-68f0332e04ae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556824240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.2556824240 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3493357295 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 5810679937 ps |
| CPU time | 578.51 seconds |
| Started | Jul 30 08:07:49 PM PDT 24 |
| Finished | Jul 30 08:17:27 PM PDT 24 |
| Peak memory | 624800 kb |
| Host | smart-a1d6670b-4869-4ee2-aed0-6673dc3d165b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493357295 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.3493357295 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3077587906 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 3826414676 ps |
| CPU time | 482.09 seconds |
| Started | Jul 30 08:09:03 PM PDT 24 |
| Finished | Jul 30 08:17:06 PM PDT 24 |
| Peak memory | 624840 kb |
| Host | smart-ff07ec00-9b60-466d-96cd-28551d990292 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077587906 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.3077587906 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2121024983 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3642366369 ps |
| CPU time | 322.2 seconds |
| Started | Jul 30 08:08:10 PM PDT 24 |
| Finished | Jul 30 08:13:33 PM PDT 24 |
| Peak memory | 618912 kb |
| Host | smart-18ed284e-6e76-4fa9-8487-b6bf6e03f6e0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121024983 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.2121024983 |
| Directory | /workspace/2.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.751897167 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3381861263 ps |
| CPU time | 348.19 seconds |
| Started | Jul 30 08:10:23 PM PDT 24 |
| Finished | Jul 30 08:16:11 PM PDT 24 |
| Peak memory | 618420 kb |
| Host | smart-495b59e5-fa28-4032-a875-82a69f671324 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751897167 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.751897167 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.818184903 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2659152900 ps |
| CPU time | 266.24 seconds |
| Started | Jul 30 08:08:58 PM PDT 24 |
| Finished | Jul 30 08:13:25 PM PDT 24 |
| Peak memory | 608928 kb |
| Host | smart-1f108a39-83f7-45bc-88f7-d9ca86c70375 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818184903 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.818184903 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2315504720 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 9018300830 ps |
| CPU time | 996.1 seconds |
| Started | Jul 30 08:15:24 PM PDT 24 |
| Finished | Jul 30 08:32:00 PM PDT 24 |
| Peak memory | 610720 kb |
| Host | smart-486664a7-3ea4-46c1-9dd3-fb1f155bd82a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315504720 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.2315504720 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.895452359 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 5046569308 ps |
| CPU time | 701.27 seconds |
| Started | Jul 30 08:13:55 PM PDT 24 |
| Finished | Jul 30 08:25:37 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-1979abd9-2c88-475c-a94d-4a62d19af908 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895452359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ sram_ctrl_scrambled_access.895452359 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1484051125 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3569885172 ps |
| CPU time | 582.01 seconds |
| Started | Jul 30 08:14:20 PM PDT 24 |
| Finished | Jul 30 08:24:03 PM PDT 24 |
| Peak memory | 609480 kb |
| Host | smart-85f58817-0c21-42dc-8737-c6e2e9578755 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484051125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1484051125 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3424140726 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 4022596306 ps |
| CPU time | 496.45 seconds |
| Started | Jul 30 08:16:59 PM PDT 24 |
| Finished | Jul 30 08:25:16 PM PDT 24 |
| Peak memory | 610764 kb |
| Host | smart-e000fac1-2241-4d1d-87cc-3bb52bde820d |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424140726 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3424140726 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.607845303 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 3547934168 ps |
| CPU time | 281.5 seconds |
| Started | Jul 30 08:19:07 PM PDT 24 |
| Finished | Jul 30 08:23:49 PM PDT 24 |
| Peak memory | 609572 kb |
| Host | smart-5a3ac5f0-362a-4b44-8394-f7fde3774b16 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607845303 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_sram_ctrl_smoketest.607845303 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.4164698961 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 20514664964 ps |
| CPU time | 3477.02 seconds |
| Started | Jul 30 08:11:32 PM PDT 24 |
| Finished | Jul 30 09:09:29 PM PDT 24 |
| Peak memory | 610552 kb |
| Host | smart-4787db11-564b-496e-a8af-e8dba44f64f6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164698961 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.4164698961 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.4167691035 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 5100522790 ps |
| CPU time | 805.68 seconds |
| Started | Jul 30 08:11:03 PM PDT 24 |
| Finished | Jul 30 08:24:30 PM PDT 24 |
| Peak memory | 613368 kb |
| Host | smart-ede9a787-1ba9-4843-a449-af2e96164c9e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167691035 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.4167691035 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.947059672 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 3458778699 ps |
| CPU time | 280.84 seconds |
| Started | Jul 30 08:12:07 PM PDT 24 |
| Finished | Jul 30 08:16:49 PM PDT 24 |
| Peak memory | 613360 kb |
| Host | smart-5e7111a3-70e1-451a-989c-20cc9cc3ab32 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947059672 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.947059672 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.4131743818 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3827377552 ps |
| CPU time | 367.54 seconds |
| Started | Jul 30 08:11:41 PM PDT 24 |
| Finished | Jul 30 08:17:49 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-64a246f9-5043-4304-9c7f-45c421e30fcb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131743818 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.4131743818 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1461549216 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 25134722996 ps |
| CPU time | 1891.1 seconds |
| Started | Jul 30 08:11:46 PM PDT 24 |
| Finished | Jul 30 08:43:18 PM PDT 24 |
| Peak memory | 614156 kb |
| Host | smart-bc40cc4d-825d-4485-b42f-a36b65a1d83b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14615492 16 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.1461549216 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3225682873 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 5807614784 ps |
| CPU time | 628.93 seconds |
| Started | Jul 30 08:15:20 PM PDT 24 |
| Finished | Jul 30 08:25:50 PM PDT 24 |
| Peak memory | 610944 kb |
| Host | smart-463b2497-e0e4-41ac-bb30-d61c95c2c98d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225682873 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3225682873 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3248659686 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 4646778808 ps |
| CPU time | 642.85 seconds |
| Started | Jul 30 08:08:18 PM PDT 24 |
| Finished | Jul 30 08:19:02 PM PDT 24 |
| Peak memory | 624516 kb |
| Host | smart-7311cc95-1aee-4ef9-a02d-fdec48f82b56 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3248659686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.3248659686 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.3620155582 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 3254763670 ps |
| CPU time | 277.84 seconds |
| Started | Jul 30 08:21:00 PM PDT 24 |
| Finished | Jul 30 08:25:38 PM PDT 24 |
| Peak memory | 614892 kb |
| Host | smart-63faac97-b4d5-47d6-a5ea-52e9d57d7a6a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620155582 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.3620155582 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.2128586361 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 4894051868 ps |
| CPU time | 658.26 seconds |
| Started | Jul 30 08:08:22 PM PDT 24 |
| Finished | Jul 30 08:19:21 PM PDT 24 |
| Peak memory | 624140 kb |
| Host | smart-b0db8215-a913-47c0-bad3-567a3f9bb38e |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128586361 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.2128586361 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2492702378 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 8657864244 ps |
| CPU time | 1259.55 seconds |
| Started | Jul 30 08:09:44 PM PDT 24 |
| Finished | Jul 30 08:30:44 PM PDT 24 |
| Peak memory | 624584 kb |
| Host | smart-e97ae428-c3c0-4566-acf3-bda0c8eb0552 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492702378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.2492702378 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2466331307 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 8616787088 ps |
| CPU time | 1278.32 seconds |
| Started | Jul 30 08:08:18 PM PDT 24 |
| Finished | Jul 30 08:29:37 PM PDT 24 |
| Peak memory | 619644 kb |
| Host | smart-7165b7ea-2f43-4498-a6f7-528bbad1ffc1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466331307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2466331307 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1861191271 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 79194503184 ps |
| CPU time | 13823.9 seconds |
| Started | Jul 30 08:10:10 PM PDT 24 |
| Finished | Jul 31 12:00:36 AM PDT 24 |
| Peak memory | 634060 kb |
| Host | smart-543e68a3-62e0-4c90-8551-5cf3cbd663e0 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1861191271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.1861191271 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3799045804 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 3787073410 ps |
| CPU time | 560.52 seconds |
| Started | Jul 30 08:07:42 PM PDT 24 |
| Finished | Jul 30 08:17:03 PM PDT 24 |
| Peak memory | 623836 kb |
| Host | smart-0176cff7-695e-4aa2-b7e5-783d6480d161 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799045804 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.3799045804 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3990662841 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 4113884290 ps |
| CPU time | 593.71 seconds |
| Started | Jul 30 08:08:15 PM PDT 24 |
| Finished | Jul 30 08:18:10 PM PDT 24 |
| Peak memory | 623840 kb |
| Host | smart-0a52f8de-a255-4366-a217-7251bbbd18c6 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990662841 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.3990662841 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1342093485 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 4778860770 ps |
| CPU time | 563.04 seconds |
| Started | Jul 30 08:10:10 PM PDT 24 |
| Finished | Jul 30 08:19:34 PM PDT 24 |
| Peak memory | 624164 kb |
| Host | smart-70cb9f1d-9e53-460e-a5b4-fda79c0a04f2 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342093485 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.1342093485 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.600118377 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 4643993628 ps |
| CPU time | 310.57 seconds |
| Started | Jul 30 08:15:34 PM PDT 24 |
| Finished | Jul 30 08:20:45 PM PDT 24 |
| Peak memory | 622960 kb |
| Host | smart-307709a1-25c3-45b8-9dff-86416eb6381c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=600118377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.600118377 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.908164370 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 2751708890 ps |
| CPU time | 163.06 seconds |
| Started | Jul 30 08:15:35 PM PDT 24 |
| Finished | Jul 30 08:18:19 PM PDT 24 |
| Peak memory | 620880 kb |
| Host | smart-8bb147a7-6ccc-4e36-8721-3d887753a0dc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908164370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.908164370 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.2999005800 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 2887765286 ps |
| CPU time | 218.46 seconds |
| Started | Jul 30 08:15:40 PM PDT 24 |
| Finished | Jul 30 08:19:19 PM PDT 24 |
| Peak memory | 622696 kb |
| Host | smart-542f7395-272c-42ea-83f0-1bb914df4220 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999005800 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.2999005800 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.180117451 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 5878151994 ps |
| CPU time | 549.02 seconds |
| Started | Jul 30 08:15:26 PM PDT 24 |
| Finished | Jul 30 08:24:36 PM PDT 24 |
| Peak memory | 632816 kb |
| Host | smart-ddf26696-fe06-4ebf-ad3d-5da11172b918 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=180117451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.180117451 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.470050333 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 15122214877 ps |
| CPU time | 3746.26 seconds |
| Started | Jul 30 08:22:17 PM PDT 24 |
| Finished | Jul 30 09:24:43 PM PDT 24 |
| Peak memory | 610020 kb |
| Host | smart-02b0af57-c26d-4b4f-adf6-9c272d9506e7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470050333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rom_e2e_asm_init_dev.470050333 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.552721517 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 15902386887 ps |
| CPU time | 4884.93 seconds |
| Started | Jul 30 08:20:52 PM PDT 24 |
| Finished | Jul 30 09:42:18 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-a8db8b4a-7d12-4e66-a118-f5f23f4a7b79 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552721517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.552721517 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1248913340 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 15888131006 ps |
| CPU time | 4767.15 seconds |
| Started | Jul 30 08:20:47 PM PDT 24 |
| Finished | Jul 30 09:40:15 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-9bc0582c-ee85-4c96-892d-b0362d9d4fc9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248913340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.1248913340 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.3150522984 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 15316409461 ps |
| CPU time | 3110.59 seconds |
| Started | Jul 30 08:21:50 PM PDT 24 |
| Finished | Jul 30 09:13:41 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-76ecd418-7166-44e2-a84f-9ccd8f2ddd8f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150522984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.3150522984 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1064909174 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 12225468114 ps |
| CPU time | 3062.3 seconds |
| Started | Jul 30 08:21:31 PM PDT 24 |
| Finished | Jul 30 09:12:34 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-aa190ae0-2aa3-45f4-a598-0c606a511fdc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064909174 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.1064909174 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3759847679 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 14856216744 ps |
| CPU time | 3533.25 seconds |
| Started | Jul 30 08:20:42 PM PDT 24 |
| Finished | Jul 30 09:19:36 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-c3ef5ae8-0f01-4db1-a401-51e283db3cc6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759847679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3759847679 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3547202321 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 15252954052 ps |
| CPU time | 3352.13 seconds |
| Started | Jul 30 08:22:59 PM PDT 24 |
| Finished | Jul 30 09:18:52 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-654c93cd-a895-4c0d-a230-78db759b9b70 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547202321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.3547202321 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.4031504855 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 14925202552 ps |
| CPU time | 4297.66 seconds |
| Started | Jul 30 08:21:45 PM PDT 24 |
| Finished | Jul 30 09:33:23 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-cf53a9e0-7ea7-437f-b8da-0bb5f1b52ac4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031504855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.4031504855 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.849777310 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 14985361587 ps |
| CPU time | 4637.25 seconds |
| Started | Jul 30 08:21:17 PM PDT 24 |
| Finished | Jul 30 09:38:35 PM PDT 24 |
| Peak memory | 611132 kb |
| Host | smart-fcba9d52-a3f0-4ef3-81ae-f9ea379ee743 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849777310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shut down_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_s hutdown_exception_c.849777310 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.2276375557 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 25485044540 ps |
| CPU time | 3498.12 seconds |
| Started | Jul 30 08:21:30 PM PDT 24 |
| Finished | Jul 30 09:19:48 PM PDT 24 |
| Peak memory | 611776 kb |
| Host | smart-f1a59ecd-1120-48c6-b5dc-61077b840dae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276375557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.2276375557 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.3115795674 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 15388513048 ps |
| CPU time | 4015.04 seconds |
| Started | Jul 30 08:22:03 PM PDT 24 |
| Finished | Jul 30 09:28:58 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-54d00a6d-1b5d-4934-b9db-604edfa6483c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=3115795674 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.3115795674 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.2341947842 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 17338577080 ps |
| CPU time | 4443.91 seconds |
| Started | Jul 30 08:20:51 PM PDT 24 |
| Finished | Jul 30 09:34:55 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-fc2bb17c-b4be-4135-8700-fd3c1ec63d09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341947842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.2341947842 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.2297042254 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 4497404240 ps |
| CPU time | 559.01 seconds |
| Started | Jul 30 08:19:15 PM PDT 24 |
| Finished | Jul 30 08:28:35 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-f079b3cd-397f-48c5-9acb-bd655a2c5c02 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297042254 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.2297042254 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_raw_unlock.3377763660 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 5871963863 ps |
| CPU time | 286.84 seconds |
| Started | Jul 30 08:17:22 PM PDT 24 |
| Finished | Jul 30 08:22:09 PM PDT 24 |
| Peak memory | 623844 kb |
| Host | smart-9b767900-e2b0-406b-baf1-9cd8d4f70880 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3377763660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.3377763660 |
| Directory | /workspace/2.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.2032491428 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2887300627 ps |
| CPU time | 136.17 seconds |
| Started | Jul 30 08:18:20 PM PDT 24 |
| Finished | Jul 30 08:20:36 PM PDT 24 |
| Peak memory | 616948 kb |
| Host | smart-a9810a6c-9a2e-4036-9292-c5a3bb775ad2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032491428 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.2032491428 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2294886967 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 4095445432 ps |
| CPU time | 448 seconds |
| Started | Jul 30 08:24:09 PM PDT 24 |
| Finished | Jul 30 08:31:37 PM PDT 24 |
| Peak memory | 649016 kb |
| Host | smart-09d599c2-e3b4-4203-8d61-a0646fcecc08 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294886967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2294886967 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.1705388100 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 5016964768 ps |
| CPU time | 642.41 seconds |
| Started | Jul 30 08:25:15 PM PDT 24 |
| Finished | Jul 30 08:35:58 PM PDT 24 |
| Peak memory | 650396 kb |
| Host | smart-b446e17f-69af-4edc-b3f3-3c0ca0f57f93 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1705388100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.1705388100 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.765777794 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 3451884192 ps |
| CPU time | 411.3 seconds |
| Started | Jul 30 08:23:19 PM PDT 24 |
| Finished | Jul 30 08:30:11 PM PDT 24 |
| Peak memory | 649020 kb |
| Host | smart-22d15b48-425e-4a61-b4b0-ff60bb574591 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765777794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_s w_alert_handler_lpg_sleep_mode_alerts.765777794 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1488672125 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 4179412444 ps |
| CPU time | 504.44 seconds |
| Started | Jul 30 08:24:59 PM PDT 24 |
| Finished | Jul 30 08:33:23 PM PDT 24 |
| Peak memory | 648724 kb |
| Host | smart-0c3803bb-ca37-41f6-baf6-7b6f4b7ad863 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488672125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1488672125 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.3264242940 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 5910280876 ps |
| CPU time | 879.77 seconds |
| Started | Jul 30 08:24:56 PM PDT 24 |
| Finished | Jul 30 08:39:36 PM PDT 24 |
| Peak memory | 650436 kb |
| Host | smart-7c6de8b1-f4d9-4cf4-b16f-747e9e5bf595 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3264242940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.3264242940 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1113743397 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 7325273704 ps |
| CPU time | 529.61 seconds |
| Started | Jul 30 08:21:43 PM PDT 24 |
| Finished | Jul 30 08:30:33 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-cf806c83-d367-4e66-92b0-03563d1a7347 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1113743397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1113743397 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2780331757 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 21438777060 ps |
| CPU time | 4376.63 seconds |
| Started | Jul 30 08:19:43 PM PDT 24 |
| Finished | Jul 30 09:32:41 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-77341ce9-aa5e-4607-995c-63e65bc248d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780331757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.2780331757 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.1090330025 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 5716457298 ps |
| CPU time | 921.32 seconds |
| Started | Jul 30 08:18:35 PM PDT 24 |
| Finished | Jul 30 08:33:56 PM PDT 24 |
| Peak memory | 611072 kb |
| Host | smart-7faa47b6-5ab1-43ba-8071-2acb8cad864a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1090330025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.1090330025 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1142464204 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 6981921474 ps |
| CPU time | 597.57 seconds |
| Started | Jul 30 08:18:29 PM PDT 24 |
| Finished | Jul 30 08:28:27 PM PDT 24 |
| Peak memory | 620472 kb |
| Host | smart-73102a3f-3b9f-4ff2-aca6-373c341fbe1e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142464204 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.1142464204 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2636986025 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 13754763144 ps |
| CPU time | 2815.1 seconds |
| Started | Jul 30 08:19:06 PM PDT 24 |
| Finished | Jul 30 09:06:02 PM PDT 24 |
| Peak memory | 624468 kb |
| Host | smart-622cc90d-d23f-4d91-88dd-0dd8d4a34e3c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2636986025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.2636986025 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.231198717 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 4572379400 ps |
| CPU time | 661.56 seconds |
| Started | Jul 30 08:20:48 PM PDT 24 |
| Finished | Jul 30 08:31:50 PM PDT 24 |
| Peak memory | 624216 kb |
| Host | smart-64bef700-4775-40dc-a44c-97ce9be0d6eb |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231198717 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.231198717 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.410611504 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 3613336406 ps |
| CPU time | 489.83 seconds |
| Started | Jul 30 08:19:44 PM PDT 24 |
| Finished | Jul 30 08:27:55 PM PDT 24 |
| Peak memory | 624496 kb |
| Host | smart-21870947-d6e8-44b6-ac03-35662cf76c13 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410611504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_ alt_clk_freq.410611504 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1757795616 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 3690854032 ps |
| CPU time | 407.29 seconds |
| Started | Jul 30 08:19:44 PM PDT 24 |
| Finished | Jul 30 08:26:32 PM PDT 24 |
| Peak memory | 623340 kb |
| Host | smart-13964b60-57b0-4d94-9ef6-8c0985b0254d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757795616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1757795616 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.923532978 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 4628561544 ps |
| CPU time | 586.52 seconds |
| Started | Jul 30 08:20:49 PM PDT 24 |
| Finished | Jul 30 08:30:37 PM PDT 24 |
| Peak memory | 624216 kb |
| Host | smart-35082ee7-d552-4ea4-b54a-98c7b9fbd572 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923532978 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.923532978 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2629453462 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 4434408540 ps |
| CPU time | 655.14 seconds |
| Started | Jul 30 08:20:40 PM PDT 24 |
| Finished | Jul 30 08:31:37 PM PDT 24 |
| Peak memory | 624212 kb |
| Host | smart-32743e3e-0c3f-46fc-9cc2-6bdda17ffd77 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629453462 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.2629453462 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.896280553 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 3903476950 ps |
| CPU time | 815.36 seconds |
| Started | Jul 30 08:19:50 PM PDT 24 |
| Finished | Jul 30 08:33:26 PM PDT 24 |
| Peak memory | 623864 kb |
| Host | smart-f8b76671-bc1f-4f29-b6d9-35b567b6a273 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896280553 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.896280553 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.3177841739 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 11213937188 ps |
| CPU time | 1114.9 seconds |
| Started | Jul 30 08:18:35 PM PDT 24 |
| Finished | Jul 30 08:37:11 PM PDT 24 |
| Peak memory | 624436 kb |
| Host | smart-6ac2b4df-a463-4622-a98c-45f76163e7c7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3177841739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.3177841739 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.1705908819 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 2725399232 ps |
| CPU time | 184.17 seconds |
| Started | Jul 30 08:19:56 PM PDT 24 |
| Finished | Jul 30 08:23:00 PM PDT 24 |
| Peak memory | 623312 kb |
| Host | smart-5664706f-aa1f-4bda-8426-528f408f6e34 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705908819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.1705908819 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_rma.1892345443 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 4675955363 ps |
| CPU time | 381.92 seconds |
| Started | Jul 30 08:18:23 PM PDT 24 |
| Finished | Jul 30 08:24:45 PM PDT 24 |
| Peak memory | 621072 kb |
| Host | smart-74fd4e6a-65f6-4e54-bf7e-b2c13f9eb73c |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892345443 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.1892345443 |
| Directory | /workspace/3.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.3597433967 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 4941528590 ps |
| CPU time | 664.21 seconds |
| Started | Jul 30 08:25:23 PM PDT 24 |
| Finished | Jul 30 08:36:27 PM PDT 24 |
| Peak memory | 619612 kb |
| Host | smart-e6e4773e-2390-48f8-81c5-0000019a11ce |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3597433967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.3597433967 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1750090229 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 3509643090 ps |
| CPU time | 454.9 seconds |
| Started | Jul 30 08:24:26 PM PDT 24 |
| Finished | Jul 30 08:32:01 PM PDT 24 |
| Peak memory | 649140 kb |
| Host | smart-5afb1cb1-8862-4aee-b6ad-f45578c916a8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750090229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1750090229 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.4176413525 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 5260942508 ps |
| CPU time | 806.2 seconds |
| Started | Jul 30 08:25:54 PM PDT 24 |
| Finished | Jul 30 08:39:20 PM PDT 24 |
| Peak memory | 610992 kb |
| Host | smart-f5c5910f-996d-4ef9-9b1f-2f3d0d06bc06 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4176413525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.4176413525 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.1071032187 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 5460187112 ps |
| CPU time | 712.72 seconds |
| Started | Jul 30 08:25:14 PM PDT 24 |
| Finished | Jul 30 08:37:07 PM PDT 24 |
| Peak memory | 650372 kb |
| Host | smart-3d9d3963-0468-4d49-ad2e-522351603700 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1071032187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.1071032187 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3804352224 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 3698559480 ps |
| CPU time | 297.94 seconds |
| Started | Jul 30 08:28:59 PM PDT 24 |
| Finished | Jul 30 08:33:57 PM PDT 24 |
| Peak memory | 649064 kb |
| Host | smart-b38cece3-9d5b-4b17-b255-fd58f2deab87 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804352224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3804352224 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.4206586422 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 5480959660 ps |
| CPU time | 537.3 seconds |
| Started | Jul 30 08:24:56 PM PDT 24 |
| Finished | Jul 30 08:33:53 PM PDT 24 |
| Peak memory | 650384 kb |
| Host | smart-4d4420ca-be0f-49e1-9d12-577491f66dc0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4206586422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.4206586422 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3668341893 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 4311258700 ps |
| CPU time | 375.29 seconds |
| Started | Jul 30 08:28:46 PM PDT 24 |
| Finished | Jul 30 08:35:01 PM PDT 24 |
| Peak memory | 649124 kb |
| Host | smart-160b30bc-0852-41a1-9152-7e36a8d14f19 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668341893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3668341893 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3398725544 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 3442524500 ps |
| CPU time | 418.01 seconds |
| Started | Jul 30 08:24:55 PM PDT 24 |
| Finished | Jul 30 08:31:54 PM PDT 24 |
| Peak memory | 648980 kb |
| Host | smart-98b48ae5-de8f-47c3-b8fc-cf4f3ac67bcb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398725544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3398725544 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.3668799670 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 5468773198 ps |
| CPU time | 541.31 seconds |
| Started | Jul 30 08:24:34 PM PDT 24 |
| Finished | Jul 30 08:33:35 PM PDT 24 |
| Peak memory | 650016 kb |
| Host | smart-ab6a482e-1a60-4d5d-a126-f44dea1819fa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3668799670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.3668799670 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.1010084297 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 5818380910 ps |
| CPU time | 912.7 seconds |
| Started | Jul 30 08:24:52 PM PDT 24 |
| Finished | Jul 30 08:40:05 PM PDT 24 |
| Peak memory | 650256 kb |
| Host | smart-9aa767f0-e7cb-4a10-89d5-a5f8dbd91acc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1010084297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.1010084297 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.557301833 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 4981331384 ps |
| CPU time | 690.8 seconds |
| Started | Jul 30 08:21:07 PM PDT 24 |
| Finished | Jul 30 08:32:38 PM PDT 24 |
| Peak memory | 650332 kb |
| Host | smart-0d67eb98-01c3-484b-b380-f5609fdc4542 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 557301833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.557301833 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.4261379233 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 5849379444 ps |
| CPU time | 448.17 seconds |
| Started | Jul 30 08:19:59 PM PDT 24 |
| Finished | Jul 30 08:27:27 PM PDT 24 |
| Peak memory | 610508 kb |
| Host | smart-58777fbf-cac8-4a80-a62b-0f5b1879f3c2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4261379233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.4261379233 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2143864304 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 27103611620 ps |
| CPU time | 5973.84 seconds |
| Started | Jul 30 08:20:45 PM PDT 24 |
| Finished | Jul 30 10:00:20 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-76e49b1e-2ebd-48c7-8f2f-bc85ec5aa640 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143864304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.2143864304 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.809907353 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 11611901829 ps |
| CPU time | 1399.72 seconds |
| Started | Jul 30 08:19:55 PM PDT 24 |
| Finished | Jul 30 08:43:15 PM PDT 24 |
| Peak memory | 620492 kb |
| Host | smart-ae0dbe73-f47f-4972-8ee3-cf8ef0d73313 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809907353 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.809907353 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2903492839 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 9051793528 ps |
| CPU time | 1040.07 seconds |
| Started | Jul 30 08:21:24 PM PDT 24 |
| Finished | Jul 30 08:38:44 PM PDT 24 |
| Peak memory | 609256 kb |
| Host | smart-f1b1dedb-326d-4f50-8146-2bbe832dc96f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29034928 39 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.2903492839 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3166054414 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 3916971956 ps |
| CPU time | 649.27 seconds |
| Started | Jul 30 08:20:19 PM PDT 24 |
| Finished | Jul 30 08:31:09 PM PDT 24 |
| Peak memory | 624384 kb |
| Host | smart-e420bb25-a23e-467a-8824-9698f9098765 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3166054414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.3166054414 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.725155162 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 4170461878 ps |
| CPU time | 599.37 seconds |
| Started | Jul 30 08:20:38 PM PDT 24 |
| Finished | Jul 30 08:30:38 PM PDT 24 |
| Peak memory | 623564 kb |
| Host | smart-0d1825af-f1fb-41c9-8279-f54431f339d8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725155162 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.725155162 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2828297352 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 4391633955 ps |
| CPU time | 469.86 seconds |
| Started | Jul 30 08:20:06 PM PDT 24 |
| Finished | Jul 30 08:27:56 PM PDT 24 |
| Peak memory | 623492 kb |
| Host | smart-e8fdc238-cdd4-423c-b4c1-f0bddcd8b57c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828297352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2828297352 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.258456186 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 4356430590 ps |
| CPU time | 679.12 seconds |
| Started | Jul 30 08:19:52 PM PDT 24 |
| Finished | Jul 30 08:31:12 PM PDT 24 |
| Peak memory | 623908 kb |
| Host | smart-dcff2198-c3ee-4d88-a48a-4555c6d865cc |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258456186 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.258456186 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1945091179 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 4180420680 ps |
| CPU time | 618.15 seconds |
| Started | Jul 30 08:19:45 PM PDT 24 |
| Finished | Jul 30 08:30:04 PM PDT 24 |
| Peak memory | 623580 kb |
| Host | smart-30f6683f-c596-41ba-8b4e-3d722a4e7b72 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945091179 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.1945091179 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2738579996 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 4016276696 ps |
| CPU time | 671.15 seconds |
| Started | Jul 30 08:20:30 PM PDT 24 |
| Finished | Jul 30 08:31:41 PM PDT 24 |
| Peak memory | 623596 kb |
| Host | smart-29e35c20-46b7-46de-bc53-320a352d7393 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738579996 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.2738579996 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.2203845909 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 2796174937 ps |
| CPU time | 167.53 seconds |
| Started | Jul 30 08:20:12 PM PDT 24 |
| Finished | Jul 30 08:23:00 PM PDT 24 |
| Peak memory | 623724 kb |
| Host | smart-5b4357aa-4050-455a-87a9-7c4dd9317080 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2203845909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.2203845909 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.1620145118 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 12762400739 ps |
| CPU time | 1566.28 seconds |
| Started | Jul 30 08:19:43 PM PDT 24 |
| Finished | Jul 30 08:45:49 PM PDT 24 |
| Peak memory | 624452 kb |
| Host | smart-0b4aa692-76c9-4a09-bb51-d8ac66cc5bbe |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620145118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.1620145118 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.424714946 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2548982616 ps |
| CPU time | 183.34 seconds |
| Started | Jul 30 08:19:43 PM PDT 24 |
| Finished | Jul 30 08:22:47 PM PDT 24 |
| Peak memory | 624668 kb |
| Host | smart-794fe132-3a44-4f4b-b70d-7b2910813e6f |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424714946 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.424714946 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.303691366 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 3459223142 ps |
| CPU time | 513.98 seconds |
| Started | Jul 30 08:26:22 PM PDT 24 |
| Finished | Jul 30 08:34:56 PM PDT 24 |
| Peak memory | 649388 kb |
| Host | smart-fb94086f-3673-4ca2-ac4e-e2e239fd6d4f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303691366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_s w_alert_handler_lpg_sleep_mode_alerts.303691366 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.341271056 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 3438934240 ps |
| CPU time | 430.36 seconds |
| Started | Jul 30 08:27:04 PM PDT 24 |
| Finished | Jul 30 08:34:15 PM PDT 24 |
| Peak memory | 649312 kb |
| Host | smart-c9ad16b9-dfe4-4cc1-8209-ef72486312fc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341271056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_s w_alert_handler_lpg_sleep_mode_alerts.341271056 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.3943764080 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 6034040600 ps |
| CPU time | 586.3 seconds |
| Started | Jul 30 08:26:55 PM PDT 24 |
| Finished | Jul 30 08:36:43 PM PDT 24 |
| Peak memory | 649748 kb |
| Host | smart-430109b8-1ad2-496a-919e-4a4c87278c2a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3943764080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.3943764080 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3647217410 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 3872121560 ps |
| CPU time | 465.37 seconds |
| Started | Jul 30 08:26:42 PM PDT 24 |
| Finished | Jul 30 08:34:28 PM PDT 24 |
| Peak memory | 648812 kb |
| Host | smart-bcad69e6-a701-434b-9960-0a9c68e2005f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647217410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3647217410 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.3067010386 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 5762650468 ps |
| CPU time | 717.02 seconds |
| Started | Jul 30 08:28:11 PM PDT 24 |
| Finished | Jul 30 08:40:08 PM PDT 24 |
| Peak memory | 650264 kb |
| Host | smart-1776b314-ce25-49e2-87a9-a18ded6e856b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3067010386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.3067010386 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2738418821 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 3342264712 ps |
| CPU time | 385 seconds |
| Started | Jul 30 08:26:26 PM PDT 24 |
| Finished | Jul 30 08:32:52 PM PDT 24 |
| Peak memory | 649052 kb |
| Host | smart-2abb59b9-329c-4230-a28c-c8c9af2a3929 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738418821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2738418821 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.539694601 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 3976227642 ps |
| CPU time | 403.44 seconds |
| Started | Jul 30 08:25:47 PM PDT 24 |
| Finished | Jul 30 08:32:31 PM PDT 24 |
| Peak memory | 648896 kb |
| Host | smart-a2d393c7-206a-4021-b3be-605d651d664a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539694601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_s w_alert_handler_lpg_sleep_mode_alerts.539694601 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.2755708403 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 4514873496 ps |
| CPU time | 500.21 seconds |
| Started | Jul 30 08:24:53 PM PDT 24 |
| Finished | Jul 30 08:33:14 PM PDT 24 |
| Peak memory | 650384 kb |
| Host | smart-26473959-9829-4e96-a214-3a0e7ef42206 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2755708403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.2755708403 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1295329209 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 4278266036 ps |
| CPU time | 394.2 seconds |
| Started | Jul 30 08:26:07 PM PDT 24 |
| Finished | Jul 30 08:32:41 PM PDT 24 |
| Peak memory | 648980 kb |
| Host | smart-8e7d80aa-e13c-4043-96a9-eb03baa00dce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295329209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1295329209 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.2833548108 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 4391709380 ps |
| CPU time | 554.59 seconds |
| Started | Jul 30 08:26:16 PM PDT 24 |
| Finished | Jul 30 08:35:31 PM PDT 24 |
| Peak memory | 650416 kb |
| Host | smart-73828214-22e0-4ef7-9c23-b4cb58930f88 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2833548108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.2833548108 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.2279642091 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 5593761050 ps |
| CPU time | 708.42 seconds |
| Started | Jul 30 08:21:25 PM PDT 24 |
| Finished | Jul 30 08:33:14 PM PDT 24 |
| Peak memory | 650268 kb |
| Host | smart-3addc243-7eec-4e81-90aa-0dce6c93acc7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2279642091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.2279642091 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3642854033 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 22137107956 ps |
| CPU time | 6016.38 seconds |
| Started | Jul 30 08:21:43 PM PDT 24 |
| Finished | Jul 30 10:02:00 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-15549e89-6338-4800-a118-f4bb1f878da0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642854033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.3642854033 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.929215446 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 5723935682 ps |
| CPU time | 689.19 seconds |
| Started | Jul 30 08:21:19 PM PDT 24 |
| Finished | Jul 30 08:32:49 PM PDT 24 |
| Peak memory | 611088 kb |
| Host | smart-2f9fccbe-1f8b-4ffb-9687-9f210df76288 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=929215446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.929215446 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1023839880 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 13044369115 ps |
| CPU time | 1215.2 seconds |
| Started | Jul 30 08:21:26 PM PDT 24 |
| Finished | Jul 30 08:41:42 PM PDT 24 |
| Peak memory | 620516 kb |
| Host | smart-263a28bc-0180-42a1-9af0-bfc99429e2c2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023839880 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.1023839880 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2636666422 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 8960412252 ps |
| CPU time | 1828.02 seconds |
| Started | Jul 30 08:21:20 PM PDT 24 |
| Finished | Jul 30 08:51:48 PM PDT 24 |
| Peak memory | 624508 kb |
| Host | smart-11d0436a-5e8b-4a0b-b90c-560cb0b62a08 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2636666422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.2636666422 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1784814312 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 4360684340 ps |
| CPU time | 493.17 seconds |
| Started | Jul 30 08:28:32 PM PDT 24 |
| Finished | Jul 30 08:36:45 PM PDT 24 |
| Peak memory | 649620 kb |
| Host | smart-5ff1e54a-ad28-44d1-ba09-a3adbf8857ed |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784814312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1784814312 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.481662195 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 6209489308 ps |
| CPU time | 658.41 seconds |
| Started | Jul 30 08:25:37 PM PDT 24 |
| Finished | Jul 30 08:36:36 PM PDT 24 |
| Peak memory | 650688 kb |
| Host | smart-5ecea93b-8299-46db-8627-afa33c00c832 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 481662195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.481662195 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.906051909 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 3035189392 ps |
| CPU time | 361.8 seconds |
| Started | Jul 30 08:25:37 PM PDT 24 |
| Finished | Jul 30 08:31:39 PM PDT 24 |
| Peak memory | 618988 kb |
| Host | smart-6964d538-8821-4422-b545-c33b5cf62f4f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906051909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_s w_alert_handler_lpg_sleep_mode_alerts.906051909 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.681207054 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 3568643552 ps |
| CPU time | 508.92 seconds |
| Started | Jul 30 08:28:08 PM PDT 24 |
| Finished | Jul 30 08:36:37 PM PDT 24 |
| Peak memory | 648972 kb |
| Host | smart-92c134bf-95bb-41fc-a7a9-2fcd9f4972a9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681207054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_s w_alert_handler_lpg_sleep_mode_alerts.681207054 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.2546782207 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 4947294832 ps |
| CPU time | 640.98 seconds |
| Started | Jul 30 08:25:47 PM PDT 24 |
| Finished | Jul 30 08:36:28 PM PDT 24 |
| Peak memory | 650348 kb |
| Host | smart-6a4627d4-2457-4a7a-80b9-cd17006a0744 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2546782207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.2546782207 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3173775495 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 3665751366 ps |
| CPU time | 407.53 seconds |
| Started | Jul 30 08:27:57 PM PDT 24 |
| Finished | Jul 30 08:34:45 PM PDT 24 |
| Peak memory | 649188 kb |
| Host | smart-e50f402b-dc2c-4c46-940d-502754cc523c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173775495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3173775495 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.886708227 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5877192428 ps |
| CPU time | 675.57 seconds |
| Started | Jul 30 08:28:39 PM PDT 24 |
| Finished | Jul 30 08:39:54 PM PDT 24 |
| Peak memory | 650364 kb |
| Host | smart-1e99e390-7e4f-417e-887d-afbce256728c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 886708227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.886708227 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.1368702488 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 4182821978 ps |
| CPU time | 525.58 seconds |
| Started | Jul 30 08:27:19 PM PDT 24 |
| Finished | Jul 30 08:36:05 PM PDT 24 |
| Peak memory | 650368 kb |
| Host | smart-41acb3d2-c084-415f-9cf0-4be75e68b67d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1368702488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.1368702488 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.18371093 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 4253772264 ps |
| CPU time | 501.69 seconds |
| Started | Jul 30 08:28:31 PM PDT 24 |
| Finished | Jul 30 08:36:53 PM PDT 24 |
| Peak memory | 648980 kb |
| Host | smart-92808ebc-2811-405e-b7f8-53dcb58b9db3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18371093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw _alert_handler_lpg_sleep_mode_alerts.18371093 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.3322541542 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 5587115384 ps |
| CPU time | 674.82 seconds |
| Started | Jul 30 08:27:21 PM PDT 24 |
| Finished | Jul 30 08:38:36 PM PDT 24 |
| Peak memory | 649916 kb |
| Host | smart-546a24a4-be9c-4b98-931c-aaa3bc5f7563 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3322541542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.3322541542 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.1323174540 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 5535289110 ps |
| CPU time | 802.72 seconds |
| Started | Jul 30 08:26:26 PM PDT 24 |
| Finished | Jul 30 08:39:49 PM PDT 24 |
| Peak memory | 650292 kb |
| Host | smart-3cec8d19-3a8e-40ac-991e-211ee24b2249 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1323174540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.1323174540 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2110386949 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 3598204060 ps |
| CPU time | 412.68 seconds |
| Started | Jul 30 08:26:26 PM PDT 24 |
| Finished | Jul 30 08:33:18 PM PDT 24 |
| Peak memory | 648840 kb |
| Host | smart-ebd02f33-5d22-4860-8bc7-671b35b5694c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110386949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2110386949 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.2357695599 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4906841128 ps |
| CPU time | 679.86 seconds |
| Started | Jul 30 08:26:33 PM PDT 24 |
| Finished | Jul 30 08:37:53 PM PDT 24 |
| Peak memory | 619640 kb |
| Host | smart-455be9f3-5e1c-4015-b6a5-95e96b740099 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2357695599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.2357695599 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1849783986 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 3923323060 ps |
| CPU time | 405.69 seconds |
| Started | Jul 30 08:22:05 PM PDT 24 |
| Finished | Jul 30 08:28:51 PM PDT 24 |
| Peak memory | 648992 kb |
| Host | smart-c8c4accf-8876-4346-ae70-a9d532d0505c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849783986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s w_alert_handler_lpg_sleep_mode_alerts.1849783986 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.2601770559 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 4140197674 ps |
| CPU time | 578.81 seconds |
| Started | Jul 30 08:21:53 PM PDT 24 |
| Finished | Jul 30 08:31:32 PM PDT 24 |
| Peak memory | 649928 kb |
| Host | smart-969a2b06-4f5f-40ac-a16a-2db52c339764 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2601770559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.2601770559 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1552523946 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 17259332760 ps |
| CPU time | 4424.22 seconds |
| Started | Jul 30 08:20:55 PM PDT 24 |
| Finished | Jul 30 09:34:40 PM PDT 24 |
| Peak memory | 610372 kb |
| Host | smart-ddbe51b9-34d6-47a6-9e1d-22a594efb01e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552523946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.1552523946 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3066884322 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 10934697697 ps |
| CPU time | 1217.13 seconds |
| Started | Jul 30 08:20:56 PM PDT 24 |
| Finished | Jul 30 08:41:14 PM PDT 24 |
| Peak memory | 620644 kb |
| Host | smart-e72c4e91-7acf-4cad-ad01-ab1750788420 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066884322 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.3066884322 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3085230487 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 3833243792 ps |
| CPU time | 608.58 seconds |
| Started | Jul 30 08:21:16 PM PDT 24 |
| Finished | Jul 30 08:31:25 PM PDT 24 |
| Peak memory | 624376 kb |
| Host | smart-653fb94a-acb0-4ea6-8dfd-acd83b9b2a0f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3085230487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.3085230487 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.2483101804 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 4811271488 ps |
| CPU time | 470.19 seconds |
| Started | Jul 30 08:28:06 PM PDT 24 |
| Finished | Jul 30 08:35:56 PM PDT 24 |
| Peak memory | 650304 kb |
| Host | smart-c55725b6-33f1-449f-80f4-821006cb95f6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2483101804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.2483101804 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.977381177 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 3435967780 ps |
| CPU time | 376.19 seconds |
| Started | Jul 30 08:27:29 PM PDT 24 |
| Finished | Jul 30 08:33:45 PM PDT 24 |
| Peak memory | 648740 kb |
| Host | smart-fed2f4a4-04da-4d05-9024-105daae88875 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977381177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_s w_alert_handler_lpg_sleep_mode_alerts.977381177 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2150240364 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 3584704344 ps |
| CPU time | 423.58 seconds |
| Started | Jul 30 08:27:57 PM PDT 24 |
| Finished | Jul 30 08:35:01 PM PDT 24 |
| Peak memory | 649592 kb |
| Host | smart-b0fecda5-2d94-40d0-a1c4-8af60f8e0783 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150240364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2150240364 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.3790943617 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 6132253840 ps |
| CPU time | 627.92 seconds |
| Started | Jul 30 08:28:52 PM PDT 24 |
| Finished | Jul 30 08:39:20 PM PDT 24 |
| Peak memory | 650084 kb |
| Host | smart-c70142c9-abbc-4562-9b2b-178422c80815 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3790943617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.3790943617 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3964264784 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 4332133874 ps |
| CPU time | 438.83 seconds |
| Started | Jul 30 08:27:48 PM PDT 24 |
| Finished | Jul 30 08:35:07 PM PDT 24 |
| Peak memory | 649440 kb |
| Host | smart-06a139b9-16a0-4cfe-9d6d-0356185ec6e3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964264784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3964264784 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.623764093 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 6104414528 ps |
| CPU time | 564.18 seconds |
| Started | Jul 30 08:26:44 PM PDT 24 |
| Finished | Jul 30 08:36:08 PM PDT 24 |
| Peak memory | 650268 kb |
| Host | smart-e8ebc45c-251b-4a4f-b4b3-4b9e5909fad9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 623764093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.623764093 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.320781479 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 3365325632 ps |
| CPU time | 422.28 seconds |
| Started | Jul 30 08:29:08 PM PDT 24 |
| Finished | Jul 30 08:36:11 PM PDT 24 |
| Peak memory | 649556 kb |
| Host | smart-4db74c97-f251-46c0-b54e-3b6b1412b323 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320781479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_s w_alert_handler_lpg_sleep_mode_alerts.320781479 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.4245565323 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 6058605092 ps |
| CPU time | 820.25 seconds |
| Started | Jul 30 08:27:09 PM PDT 24 |
| Finished | Jul 30 08:40:49 PM PDT 24 |
| Peak memory | 649952 kb |
| Host | smart-be40a611-2cd1-4b83-8e3d-10d2e255905a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4245565323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.4245565323 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.854287162 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 4607970488 ps |
| CPU time | 426.82 seconds |
| Started | Jul 30 08:27:23 PM PDT 24 |
| Finished | Jul 30 08:34:30 PM PDT 24 |
| Peak memory | 649692 kb |
| Host | smart-077fa9f7-c484-4a67-ab19-d3d31749413b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854287162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_s w_alert_handler_lpg_sleep_mode_alerts.854287162 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3260753606 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 4014779052 ps |
| CPU time | 441.76 seconds |
| Started | Jul 30 08:29:25 PM PDT 24 |
| Finished | Jul 30 08:36:47 PM PDT 24 |
| Peak memory | 649048 kb |
| Host | smart-356641d2-ccf0-4ac6-9574-dc974306cc15 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260753606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3260753606 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.2090926577 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 4878924610 ps |
| CPU time | 584.4 seconds |
| Started | Jul 30 08:27:09 PM PDT 24 |
| Finished | Jul 30 08:36:54 PM PDT 24 |
| Peak memory | 649952 kb |
| Host | smart-3612dab4-392b-4ca7-b59f-2e52e7caa87c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2090926577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.2090926577 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2191027686 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 3744003310 ps |
| CPU time | 385.08 seconds |
| Started | Jul 30 08:29:15 PM PDT 24 |
| Finished | Jul 30 08:35:40 PM PDT 24 |
| Peak memory | 649068 kb |
| Host | smart-20e384bc-3d8a-4967-abfc-b17fa5f24d75 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191027686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2191027686 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1998503463 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 3149041064 ps |
| CPU time | 401.57 seconds |
| Started | Jul 30 08:27:41 PM PDT 24 |
| Finished | Jul 30 08:34:23 PM PDT 24 |
| Peak memory | 649052 kb |
| Host | smart-9cbe5cad-deab-47bd-b7c2-53bd86aa7e01 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998503463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1998503463 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1416504128 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 3857654558 ps |
| CPU time | 366.03 seconds |
| Started | Jul 30 08:27:54 PM PDT 24 |
| Finished | Jul 30 08:34:00 PM PDT 24 |
| Peak memory | 649388 kb |
| Host | smart-48d1158f-483f-410e-8a93-e20d98c623b3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416504128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1416504128 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.3828567499 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 4799797198 ps |
| CPU time | 712.24 seconds |
| Started | Jul 30 08:28:01 PM PDT 24 |
| Finished | Jul 30 08:39:54 PM PDT 24 |
| Peak memory | 650060 kb |
| Host | smart-8e13be47-e858-4378-a8c5-6f5582f66656 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3828567499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.3828567499 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2696928114 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 15686799976 ps |
| CPU time | 3865.21 seconds |
| Started | Jul 30 08:21:52 PM PDT 24 |
| Finished | Jul 30 09:26:18 PM PDT 24 |
| Peak memory | 610468 kb |
| Host | smart-ba13c19a-9df4-4744-baf3-752850c0b1b1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696928114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.2696928114 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2172261003 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 13953775828 ps |
| CPU time | 1190.08 seconds |
| Started | Jul 30 08:21:33 PM PDT 24 |
| Finished | Jul 30 08:41:24 PM PDT 24 |
| Peak memory | 620480 kb |
| Host | smart-37d7084d-98fb-4d66-a34a-06e4901d4efe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172261003 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.2172261003 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2721083895 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 4549302664 ps |
| CPU time | 658.48 seconds |
| Started | Jul 30 08:20:21 PM PDT 24 |
| Finished | Jul 30 08:31:20 PM PDT 24 |
| Peak memory | 624472 kb |
| Host | smart-a8f78820-b862-4672-9f79-fbf93b95ae16 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2721083895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.2721083895 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.351179330 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 5062649608 ps |
| CPU time | 776.39 seconds |
| Started | Jul 30 08:28:59 PM PDT 24 |
| Finished | Jul 30 08:41:55 PM PDT 24 |
| Peak memory | 649988 kb |
| Host | smart-0ae5f1be-f690-489c-9f05-86b067a2ebdd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 351179330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.351179330 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.784670990 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 4485129660 ps |
| CPU time | 366.31 seconds |
| Started | Jul 30 08:31:23 PM PDT 24 |
| Finished | Jul 30 08:37:29 PM PDT 24 |
| Peak memory | 648552 kb |
| Host | smart-5864e75a-0621-4b64-a826-70aa12920986 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784670990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_s w_alert_handler_lpg_sleep_mode_alerts.784670990 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.3244541771 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 5124813944 ps |
| CPU time | 531.27 seconds |
| Started | Jul 30 08:28:42 PM PDT 24 |
| Finished | Jul 30 08:37:33 PM PDT 24 |
| Peak memory | 650336 kb |
| Host | smart-fed87703-5d6b-4e2f-9f4f-ca6e9578fe5c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3244541771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.3244541771 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3644327672 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 3979551830 ps |
| CPU time | 340.83 seconds |
| Started | Jul 30 08:27:55 PM PDT 24 |
| Finished | Jul 30 08:33:36 PM PDT 24 |
| Peak memory | 648800 kb |
| Host | smart-528bbca5-29f1-46e9-9ecd-6cba2443903d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644327672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3644327672 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.2819599858 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 4466021560 ps |
| CPU time | 563.22 seconds |
| Started | Jul 30 08:27:43 PM PDT 24 |
| Finished | Jul 30 08:37:07 PM PDT 24 |
| Peak memory | 650368 kb |
| Host | smart-d5394486-c1c3-4c65-bc38-a3cd4be3ac28 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2819599858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.2819599858 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.333050508 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 3720896086 ps |
| CPU time | 321.87 seconds |
| Started | Jul 30 08:27:53 PM PDT 24 |
| Finished | Jul 30 08:33:15 PM PDT 24 |
| Peak memory | 649020 kb |
| Host | smart-acb3d824-ad33-43e5-a3a0-23a501408fe7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333050508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_s w_alert_handler_lpg_sleep_mode_alerts.333050508 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3533887350 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 4301110600 ps |
| CPU time | 463.81 seconds |
| Started | Jul 30 08:30:06 PM PDT 24 |
| Finished | Jul 30 08:37:50 PM PDT 24 |
| Peak memory | 649676 kb |
| Host | smart-f3e702c4-489f-4ce1-b921-e059f84275e7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533887350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3533887350 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.3100789678 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 5354653320 ps |
| CPU time | 556.02 seconds |
| Started | Jul 30 08:28:03 PM PDT 24 |
| Finished | Jul 30 08:37:19 PM PDT 24 |
| Peak memory | 649940 kb |
| Host | smart-432f35a6-386d-4072-8299-093742800966 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3100789678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.3100789678 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3725163851 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 4432481370 ps |
| CPU time | 456.51 seconds |
| Started | Jul 30 08:29:18 PM PDT 24 |
| Finished | Jul 30 08:36:55 PM PDT 24 |
| Peak memory | 649696 kb |
| Host | smart-b8901f70-b899-4347-9efa-266d105c18d1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725163851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3725163851 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.476892789 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 5574415132 ps |
| CPU time | 690.84 seconds |
| Started | Jul 30 08:29:18 PM PDT 24 |
| Finished | Jul 30 08:40:49 PM PDT 24 |
| Peak memory | 616940 kb |
| Host | smart-e51bb972-db6b-4cf7-ac93-d1c632ec4de4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 476892789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.476892789 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1610169477 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 4036324496 ps |
| CPU time | 406.94 seconds |
| Started | Jul 30 08:29:05 PM PDT 24 |
| Finished | Jul 30 08:35:52 PM PDT 24 |
| Peak memory | 649088 kb |
| Host | smart-d94314c4-1dc7-40a2-a22b-c125af164bac |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610169477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1610169477 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.2155140510 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 4979388462 ps |
| CPU time | 505.31 seconds |
| Started | Jul 30 08:29:58 PM PDT 24 |
| Finished | Jul 30 08:38:23 PM PDT 24 |
| Peak memory | 650372 kb |
| Host | smart-0d16ba7b-34ef-48f8-acd6-5bfe91872a59 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2155140510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.2155140510 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.6116340 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 4025558354 ps |
| CPU time | 405.58 seconds |
| Started | Jul 30 08:28:44 PM PDT 24 |
| Finished | Jul 30 08:35:30 PM PDT 24 |
| Peak memory | 649068 kb |
| Host | smart-671d90e0-3483-4585-84ef-e77ffa679589 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6116340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_e scalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_ alert_handler_lpg_sleep_mode_alerts.6116340 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.3391768767 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 5536360064 ps |
| CPU time | 625.76 seconds |
| Started | Jul 30 08:28:51 PM PDT 24 |
| Finished | Jul 30 08:39:17 PM PDT 24 |
| Peak memory | 650328 kb |
| Host | smart-ba7b32dd-8540-48cb-9fb5-b6e2554a1f2e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3391768767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.3391768767 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.624394908 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 5924110438 ps |
| CPU time | 760.94 seconds |
| Started | Jul 30 08:28:37 PM PDT 24 |
| Finished | Jul 30 08:41:18 PM PDT 24 |
| Peak memory | 650340 kb |
| Host | smart-f3ef93e2-5030-4789-839c-1e1b9954b379 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 624394908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.624394908 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3366241962 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 3176275484 ps |
| CPU time | 396.84 seconds |
| Started | Jul 30 08:30:17 PM PDT 24 |
| Finished | Jul 30 08:36:54 PM PDT 24 |
| Peak memory | 648996 kb |
| Host | smart-07969a6d-8128-4378-809c-d80d3edf8f7e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366241962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3366241962 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.3239965416 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 4963000622 ps |
| CPU time | 689.85 seconds |
| Started | Jul 30 08:29:13 PM PDT 24 |
| Finished | Jul 30 08:40:43 PM PDT 24 |
| Peak memory | 650092 kb |
| Host | smart-8264c844-cb90-42a0-beb1-98b561d666a7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3239965416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.3239965416 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3458704702 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 3325339410 ps |
| CPU time | 382.68 seconds |
| Started | Jul 30 08:21:20 PM PDT 24 |
| Finished | Jul 30 08:27:43 PM PDT 24 |
| Peak memory | 648944 kb |
| Host | smart-56724182-5782-4e3e-a3a2-4c5a7d36f3de |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458704702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.3458704702 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.3496737140 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 4823140262 ps |
| CPU time | 578.08 seconds |
| Started | Jul 30 08:21:51 PM PDT 24 |
| Finished | Jul 30 08:31:29 PM PDT 24 |
| Peak memory | 650408 kb |
| Host | smart-ac8e03fe-c69e-48cf-a10a-92e9c4999fe4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3496737140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.3496737140 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.4146105866 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 9220019280 ps |
| CPU time | 978.69 seconds |
| Started | Jul 30 08:22:07 PM PDT 24 |
| Finished | Jul 30 08:38:27 PM PDT 24 |
| Peak memory | 620460 kb |
| Host | smart-8b300319-137c-482c-9599-1af07d6844a2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146105866 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.4146105866 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.625179977 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 4725606054 ps |
| CPU time | 443.83 seconds |
| Started | Jul 30 08:20:08 PM PDT 24 |
| Finished | Jul 30 08:27:32 PM PDT 24 |
| Peak memory | 624468 kb |
| Host | smart-4bc9dfe9-1c45-430b-b224-487b50fa105f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=625179977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.625179977 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.121176601 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 3720438834 ps |
| CPU time | 434.99 seconds |
| Started | Jul 30 08:28:34 PM PDT 24 |
| Finished | Jul 30 08:35:49 PM PDT 24 |
| Peak memory | 649024 kb |
| Host | smart-2ea73dde-093a-4827-b28c-06a14f15edbf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121176601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_s w_alert_handler_lpg_sleep_mode_alerts.121176601 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3985014818 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 4021294912 ps |
| CPU time | 399.57 seconds |
| Started | Jul 30 08:30:02 PM PDT 24 |
| Finished | Jul 30 08:36:42 PM PDT 24 |
| Peak memory | 649080 kb |
| Host | smart-ca13db94-9c63-46b8-9ac4-023e1dc68a99 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985014818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3985014818 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.783411633 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 5141592454 ps |
| CPU time | 630.98 seconds |
| Started | Jul 30 08:31:40 PM PDT 24 |
| Finished | Jul 30 08:42:11 PM PDT 24 |
| Peak memory | 650588 kb |
| Host | smart-68f944f5-2bad-46ff-852e-7df1378c4494 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 783411633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.783411633 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.508373180 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 3462058390 ps |
| CPU time | 366.67 seconds |
| Started | Jul 30 08:29:19 PM PDT 24 |
| Finished | Jul 30 08:35:26 PM PDT 24 |
| Peak memory | 649008 kb |
| Host | smart-8562f89b-c8cd-4ac1-bbe5-5c1bf7a0d025 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508373180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_s w_alert_handler_lpg_sleep_mode_alerts.508373180 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.3434434145 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 5786981344 ps |
| CPU time | 645.93 seconds |
| Started | Jul 30 08:29:55 PM PDT 24 |
| Finished | Jul 30 08:40:41 PM PDT 24 |
| Peak memory | 650012 kb |
| Host | smart-0872b1bc-85be-42c2-a7c0-ff6760eaead0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3434434145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.3434434145 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1368964754 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 3558596092 ps |
| CPU time | 403.05 seconds |
| Started | Jul 30 08:29:33 PM PDT 24 |
| Finished | Jul 30 08:36:16 PM PDT 24 |
| Peak memory | 649220 kb |
| Host | smart-b7a8b7d8-325e-47a7-b25f-1ea4c46dc1ec |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368964754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1368964754 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.295883009 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 5599469844 ps |
| CPU time | 604.81 seconds |
| Started | Jul 30 08:31:37 PM PDT 24 |
| Finished | Jul 30 08:41:43 PM PDT 24 |
| Peak memory | 610872 kb |
| Host | smart-1083acc3-1753-4fa0-b25c-081a5d0794fa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 295883009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.295883009 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.3111351069 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 5961038528 ps |
| CPU time | 575.61 seconds |
| Started | Jul 30 08:31:46 PM PDT 24 |
| Finished | Jul 30 08:41:22 PM PDT 24 |
| Peak memory | 611072 kb |
| Host | smart-6ff15ab9-dcfb-4400-8102-1d192a879339 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3111351069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.3111351069 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.84057549 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 3552286512 ps |
| CPU time | 410.93 seconds |
| Started | Jul 30 08:29:15 PM PDT 24 |
| Finished | Jul 30 08:36:06 PM PDT 24 |
| Peak memory | 648912 kb |
| Host | smart-45da8c4f-c1fa-43bb-aade-3549a54c1c36 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84057549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw _alert_handler_lpg_sleep_mode_alerts.84057549 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.2908743413 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 5921018340 ps |
| CPU time | 716.82 seconds |
| Started | Jul 30 08:31:31 PM PDT 24 |
| Finished | Jul 30 08:43:28 PM PDT 24 |
| Peak memory | 650160 kb |
| Host | smart-21348d61-69ad-4a09-bbe7-a8f03073715d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2908743413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.2908743413 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.373598977 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 3746099888 ps |
| CPU time | 366.14 seconds |
| Started | Jul 30 08:29:36 PM PDT 24 |
| Finished | Jul 30 08:35:42 PM PDT 24 |
| Peak memory | 649388 kb |
| Host | smart-cfe6a9ec-a48b-4c72-b763-27cb4d732e7b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373598977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_s w_alert_handler_lpg_sleep_mode_alerts.373598977 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3749717650 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 3290633052 ps |
| CPU time | 399.98 seconds |
| Started | Jul 30 08:30:17 PM PDT 24 |
| Finished | Jul 30 08:36:57 PM PDT 24 |
| Peak memory | 648984 kb |
| Host | smart-b0690dab-e98a-44a4-a71f-796eeaf56b45 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749717650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3749717650 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.4193621119 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 4880834328 ps |
| CPU time | 472.44 seconds |
| Started | Jul 30 08:31:06 PM PDT 24 |
| Finished | Jul 30 08:38:58 PM PDT 24 |
| Peak memory | 650296 kb |
| Host | smart-fa7abf5e-3823-4d04-a37f-95564678932e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4193621119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.4193621119 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.4088475513 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 5478138264 ps |
| CPU time | 688.79 seconds |
| Started | Jul 30 08:29:50 PM PDT 24 |
| Finished | Jul 30 08:41:19 PM PDT 24 |
| Peak memory | 616980 kb |
| Host | smart-8a2542ed-0c6e-48de-b301-3fae5175e781 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4088475513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.4088475513 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.2581156162 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 5313067486 ps |
| CPU time | 466.15 seconds |
| Started | Jul 30 08:30:07 PM PDT 24 |
| Finished | Jul 30 08:37:54 PM PDT 24 |
| Peak memory | 650348 kb |
| Host | smart-d718dfc0-5b17-40c5-8cae-95fea977a603 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2581156162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.2581156162 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4009362834 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 3764344968 ps |
| CPU time | 349.28 seconds |
| Started | Jul 30 08:21:07 PM PDT 24 |
| Finished | Jul 30 08:26:57 PM PDT 24 |
| Peak memory | 649104 kb |
| Host | smart-f2ad94ce-fe15-47e7-8553-7be4ee0110bf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009362834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.4009362834 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2776819592 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 19560979540 ps |
| CPU time | 4718.32 seconds |
| Started | Jul 30 08:22:50 PM PDT 24 |
| Finished | Jul 30 09:41:29 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-e57f5a20-c37b-4266-8922-e0d2f233000e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776819592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.2776819592 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2086014776 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 9205395942 ps |
| CPU time | 1477.59 seconds |
| Started | Jul 30 08:22:04 PM PDT 24 |
| Finished | Jul 30 08:46:42 PM PDT 24 |
| Peak memory | 624800 kb |
| Host | smart-266c0653-f47d-46ea-9c3f-fa7917edac61 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086014776 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.2086014776 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.864602499 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 4425642308 ps |
| CPU time | 634.67 seconds |
| Started | Jul 30 08:22:35 PM PDT 24 |
| Finished | Jul 30 08:33:11 PM PDT 24 |
| Peak memory | 623272 kb |
| Host | smart-af37b46d-6418-47d5-ab14-71dd543ec959 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=864602499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.864602499 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.3891270229 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 5182784922 ps |
| CPU time | 573.85 seconds |
| Started | Jul 30 08:29:48 PM PDT 24 |
| Finished | Jul 30 08:39:22 PM PDT 24 |
| Peak memory | 649952 kb |
| Host | smart-c7d71887-37dd-456f-b719-826567933a4c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3891270229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.3891270229 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.4103132525 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 5484694766 ps |
| CPU time | 741.32 seconds |
| Started | Jul 30 08:30:46 PM PDT 24 |
| Finished | Jul 30 08:43:08 PM PDT 24 |
| Peak memory | 650448 kb |
| Host | smart-01aed2cd-1c36-4a03-b1b9-6808333b0dfd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4103132525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.4103132525 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.37325494 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 4873035664 ps |
| CPU time | 613.41 seconds |
| Started | Jul 30 08:30:13 PM PDT 24 |
| Finished | Jul 30 08:40:27 PM PDT 24 |
| Peak memory | 650000 kb |
| Host | smart-67e041b2-7a5b-4e8f-a77a-a2d2a18b597f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 37325494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.37325494 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.3756705934 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 6379275794 ps |
| CPU time | 699.71 seconds |
| Started | Jul 30 08:30:35 PM PDT 24 |
| Finished | Jul 30 08:42:15 PM PDT 24 |
| Peak memory | 650432 kb |
| Host | smart-1bfc41ff-5854-4e49-a0c6-01df0553899d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3756705934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.3756705934 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.1691918328 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 5769352218 ps |
| CPU time | 497 seconds |
| Started | Jul 30 08:30:02 PM PDT 24 |
| Finished | Jul 30 08:38:19 PM PDT 24 |
| Peak memory | 619760 kb |
| Host | smart-fb7b9238-e09b-4e99-9f73-d58ba4818e8d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1691918328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.1691918328 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.4194541135 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 6066596280 ps |
| CPU time | 649.35 seconds |
| Started | Jul 30 08:30:49 PM PDT 24 |
| Finished | Jul 30 08:41:39 PM PDT 24 |
| Peak memory | 650076 kb |
| Host | smart-670bd5a9-5969-4abe-93a9-3e2431225c07 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4194541135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.4194541135 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.1405379253 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 6385674448 ps |
| CPU time | 603.94 seconds |
| Started | Jul 30 08:33:03 PM PDT 24 |
| Finished | Jul 30 08:43:07 PM PDT 24 |
| Peak memory | 650436 kb |
| Host | smart-3027dbf5-026a-484b-852a-43f15491640b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1405379253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.1405379253 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.3964305140 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 5366315240 ps |
| CPU time | 642.99 seconds |
| Started | Jul 30 08:30:55 PM PDT 24 |
| Finished | Jul 30 08:41:39 PM PDT 24 |
| Peak memory | 610768 kb |
| Host | smart-6aa5fcf8-ef6e-4936-a2e2-19e17ccbcda2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3964305140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.3964305140 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.1448843769 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 5360803520 ps |
| CPU time | 528.29 seconds |
| Started | Jul 30 08:30:15 PM PDT 24 |
| Finished | Jul 30 08:39:04 PM PDT 24 |
| Peak memory | 650348 kb |
| Host | smart-d5719364-af1f-4ea7-b422-9feb12ffb1be |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1448843769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.1448843769 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.1752671910 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 5158058720 ps |
| CPU time | 795.3 seconds |
| Started | Jul 30 08:30:48 PM PDT 24 |
| Finished | Jul 30 08:44:03 PM PDT 24 |
| Peak memory | 650592 kb |
| Host | smart-dbcab499-36d4-4b82-ba32-9513c790186d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1752671910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.1752671910 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1489889998 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 4541706749 ps |
| CPU time | 273 seconds |
| Started | Jul 30 07:43:38 PM PDT 24 |
| Finished | Jul 30 07:48:11 PM PDT 24 |
| Peak memory | 657336 kb |
| Host | smart-3d012820-9124-481b-a8c3-d90e64e85dcc |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489889998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.1489889998 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1147307075 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4702167171 ps |
| CPU time | 228.47 seconds |
| Started | Jul 30 07:43:41 PM PDT 24 |
| Finished | Jul 30 07:47:30 PM PDT 24 |
| Peak memory | 641036 kb |
| Host | smart-e0df6a88-02f9-4227-b2ba-3801128e4dd9 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147307075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.1147307075 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1069065890 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 4768234447 ps |
| CPU time | 258.07 seconds |
| Started | Jul 30 07:43:37 PM PDT 24 |
| Finished | Jul 30 07:47:55 PM PDT 24 |
| Peak memory | 651848 kb |
| Host | smart-ba557b87-a202-4dfe-8083-46eea8d937c5 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069065890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.1069065890 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1980298062 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 5039946950 ps |
| CPU time | 270.48 seconds |
| Started | Jul 30 07:43:41 PM PDT 24 |
| Finished | Jul 30 07:48:12 PM PDT 24 |
| Peak memory | 649984 kb |
| Host | smart-599d1674-781f-40c9-88ea-54e3eb228bdf |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980298062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.1980298062 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2195269982 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 5365161392 ps |
| CPU time | 256.7 seconds |
| Started | Jul 30 07:43:38 PM PDT 24 |
| Finished | Jul 30 07:47:54 PM PDT 24 |
| Peak memory | 657332 kb |
| Host | smart-25596030-f57e-404b-ab97-29296769e118 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195269982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.2195269982 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3350151470 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 4606708688 ps |
| CPU time | 169.48 seconds |
| Started | Jul 30 07:43:41 PM PDT 24 |
| Finished | Jul 30 07:46:31 PM PDT 24 |
| Peak memory | 641000 kb |
| Host | smart-abca1268-b5d5-4e00-88cd-0a67f47d70a8 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350151470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.3350151470 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3001041271 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 4563879156 ps |
| CPU time | 210.61 seconds |
| Started | Jul 30 07:43:43 PM PDT 24 |
| Finished | Jul 30 07:47:14 PM PDT 24 |
| Peak memory | 657288 kb |
| Host | smart-e0298697-50d3-4e31-a4d7-198d1358fbc1 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001041271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.3001041271 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.161434762 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 5175637920 ps |
| CPU time | 213.51 seconds |
| Started | Jul 30 07:43:42 PM PDT 24 |
| Finished | Jul 30 07:47:16 PM PDT 24 |
| Peak memory | 649152 kb |
| Host | smart-a4cd9650-4814-46c8-b03a-36f6c72b7c98 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161434762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 8.chip_padctrl_attributes.161434762 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
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