| T1216 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2651428590 |
|
|
Jul 30 08:21:38 PM PDT 24 |
Jul 30 08:28:10 PM PDT 24 |
3223179120 ps |
| T1217 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.4098324959 |
|
|
Jul 30 07:54:30 PM PDT 24 |
Jul 30 07:58:51 PM PDT 24 |
2905622728 ps |
| T1218 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1706872170 |
|
|
Jul 30 08:13:59 PM PDT 24 |
Jul 30 08:17:53 PM PDT 24 |
2331361525 ps |
| T360 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3831019862 |
|
|
Jul 30 08:13:32 PM PDT 24 |
Jul 30 08:17:48 PM PDT 24 |
2796062892 ps |
| T852 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3756705934 |
|
|
Jul 30 08:30:35 PM PDT 24 |
Jul 30 08:42:15 PM PDT 24 |
6379275794 ps |
| T1219 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1410435033 |
|
|
Jul 30 07:56:54 PM PDT 24 |
Jul 30 08:05:36 PM PDT 24 |
5013719548 ps |
| T1220 |
/workspace/coverage/default/1.chip_sw_power_idle_load.4013140617 |
|
|
Jul 30 08:06:36 PM PDT 24 |
Jul 30 08:17:44 PM PDT 24 |
4787014084 ps |
| T1221 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.3664787731 |
|
|
Jul 30 08:14:05 PM PDT 24 |
Jul 30 08:18:31 PM PDT 24 |
3431794882 ps |
| T1222 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.3025636285 |
|
|
Jul 30 08:11:57 PM PDT 24 |
Jul 30 08:20:32 PM PDT 24 |
5704615460 ps |
| T1223 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.3758476023 |
|
|
Jul 30 08:17:47 PM PDT 24 |
Jul 30 08:28:05 PM PDT 24 |
5155080184 ps |
| T1224 |
/workspace/coverage/default/2.rom_e2e_static_critical.2341947842 |
|
|
Jul 30 08:20:51 PM PDT 24 |
Jul 30 09:34:55 PM PDT 24 |
17338577080 ps |
| T1225 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.2583167379 |
|
|
Jul 30 08:18:32 PM PDT 24 |
Jul 30 08:23:46 PM PDT 24 |
2989080996 ps |
| T1226 |
/workspace/coverage/default/4.chip_tap_straps_prod.1620145118 |
|
|
Jul 30 08:19:43 PM PDT 24 |
Jul 30 08:45:49 PM PDT 24 |
12762400739 ps |
| T1227 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1570098326 |
|
|
Jul 30 08:10:31 PM PDT 24 |
Jul 30 08:16:44 PM PDT 24 |
3780129000 ps |
| T1228 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.4091932872 |
|
|
Jul 30 08:11:35 PM PDT 24 |
Jul 30 08:17:29 PM PDT 24 |
4024236340 ps |
| T1229 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1011412337 |
|
|
Jul 30 07:52:49 PM PDT 24 |
Jul 30 08:09:14 PM PDT 24 |
12144993756 ps |
| T1230 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.476892789 |
|
|
Jul 30 08:29:18 PM PDT 24 |
Jul 30 08:40:49 PM PDT 24 |
5574415132 ps |
| T1231 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2189656922 |
|
|
Jul 30 08:04:18 PM PDT 24 |
Jul 30 08:11:53 PM PDT 24 |
5105615638 ps |
| T1232 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1452466201 |
|
|
Jul 30 07:54:10 PM PDT 24 |
Jul 30 07:58:29 PM PDT 24 |
2971373432 ps |
| T200 |
/workspace/coverage/default/0.chip_sw_power_virus.3110211814 |
|
|
Jul 30 07:59:57 PM PDT 24 |
Jul 30 08:24:25 PM PDT 24 |
5779840574 ps |
| T829 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2110386949 |
|
|
Jul 30 08:26:26 PM PDT 24 |
Jul 30 08:33:18 PM PDT 24 |
3598204060 ps |
| T1233 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.782235425 |
|
|
Jul 30 07:53:32 PM PDT 24 |
Jul 30 08:04:21 PM PDT 24 |
18074443100 ps |
| T1234 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.966101091 |
|
|
Jul 30 08:23:21 PM PDT 24 |
Jul 30 08:31:29 PM PDT 24 |
3275568622 ps |
| T1235 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.2156342727 |
|
|
Jul 30 08:03:14 PM PDT 24 |
Jul 30 08:06:33 PM PDT 24 |
2594944968 ps |
| T1236 |
/workspace/coverage/default/2.chip_tap_straps_dev.600118377 |
|
|
Jul 30 08:15:34 PM PDT 24 |
Jul 30 08:20:45 PM PDT 24 |
4643993628 ps |
| T446 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.341271056 |
|
|
Jul 30 08:27:04 PM PDT 24 |
Jul 30 08:34:15 PM PDT 24 |
3438934240 ps |
| T817 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1896722688 |
|
|
Jul 30 08:27:06 PM PDT 24 |
Jul 30 08:40:51 PM PDT 24 |
6369845992 ps |
| T201 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.1178794894 |
|
|
Jul 30 07:51:33 PM PDT 24 |
Jul 30 07:59:55 PM PDT 24 |
5946331055 ps |
| T205 |
/workspace/coverage/default/2.chip_jtag_csr_rw.3738704093 |
|
|
Jul 30 08:07:59 PM PDT 24 |
Jul 30 08:45:43 PM PDT 24 |
20122083142 ps |
| T135 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3391527866 |
|
|
Jul 30 08:03:24 PM PDT 24 |
Jul 30 08:09:14 PM PDT 24 |
3616783824 ps |
| T1237 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3895848220 |
|
|
Jul 30 07:57:47 PM PDT 24 |
Jul 30 08:10:45 PM PDT 24 |
12496442293 ps |
| T1238 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3658197335 |
|
|
Jul 30 08:15:51 PM PDT 24 |
Jul 30 08:25:31 PM PDT 24 |
6658870970 ps |
| T1239 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.4011263640 |
|
|
Jul 30 07:53:08 PM PDT 24 |
Jul 30 08:28:28 PM PDT 24 |
8888816524 ps |
| T1240 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3400595433 |
|
|
Jul 30 07:51:32 PM PDT 24 |
Jul 30 08:11:50 PM PDT 24 |
7487857128 ps |
| T800 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1368964754 |
|
|
Jul 30 08:29:33 PM PDT 24 |
Jul 30 08:36:16 PM PDT 24 |
3558596092 ps |
| T337 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.955101992 |
|
|
Jul 30 08:14:10 PM PDT 24 |
Jul 30 08:28:24 PM PDT 24 |
4158622576 ps |
| T1241 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.783411633 |
|
|
Jul 30 08:31:40 PM PDT 24 |
Jul 30 08:42:11 PM PDT 24 |
5141592454 ps |
| T1242 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.4131059724 |
|
|
Jul 30 08:11:26 PM PDT 24 |
Jul 30 08:23:08 PM PDT 24 |
4793923144 ps |
| T253 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.3241790210 |
|
|
Jul 30 08:26:27 PM PDT 24 |
Jul 30 08:38:11 PM PDT 24 |
4461429384 ps |
| T1243 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2702204441 |
|
|
Jul 30 07:57:58 PM PDT 24 |
Jul 30 08:42:40 PM PDT 24 |
27459349329 ps |
| T1244 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.708354900 |
|
|
Jul 30 07:59:09 PM PDT 24 |
Jul 30 08:09:47 PM PDT 24 |
5730321240 ps |
| T722 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1499470937 |
|
|
Jul 30 07:56:33 PM PDT 24 |
Jul 30 08:57:56 PM PDT 24 |
24517391852 ps |
| T1245 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.315481843 |
|
|
Jul 30 08:24:47 PM PDT 24 |
Jul 30 08:30:51 PM PDT 24 |
4153925568 ps |
| T1246 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3852102951 |
|
|
Jul 30 08:10:13 PM PDT 24 |
Jul 30 09:39:03 PM PDT 24 |
43177207404 ps |
| T742 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1801652916 |
|
|
Jul 30 08:09:51 PM PDT 24 |
Jul 30 08:14:07 PM PDT 24 |
2955636390 ps |
| T1247 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.1071032187 |
|
|
Jul 30 08:25:14 PM PDT 24 |
Jul 30 08:37:07 PM PDT 24 |
5460187112 ps |
| T1248 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2060081363 |
|
|
Jul 30 07:52:04 PM PDT 24 |
Jul 30 08:23:24 PM PDT 24 |
9450134054 ps |
| T353 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2794151341 |
|
|
Jul 30 08:08:11 PM PDT 24 |
Jul 30 08:22:05 PM PDT 24 |
4782271998 ps |
| T1249 |
/workspace/coverage/default/2.chip_sw_aes_enc.3156188694 |
|
|
Jul 30 08:11:12 PM PDT 24 |
Jul 30 08:16:03 PM PDT 24 |
2750462864 ps |
| T808 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.373598977 |
|
|
Jul 30 08:29:36 PM PDT 24 |
Jul 30 08:35:42 PM PDT 24 |
3746099888 ps |
| T1250 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2466819084 |
|
|
Jul 30 08:02:52 PM PDT 24 |
Jul 30 08:31:01 PM PDT 24 |
9485867772 ps |
| T1251 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1366244913 |
|
|
Jul 30 08:01:30 PM PDT 24 |
Jul 30 09:08:28 PM PDT 24 |
15481347616 ps |
| T1252 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2432927731 |
|
|
Jul 30 08:00:40 PM PDT 24 |
Jul 30 08:04:51 PM PDT 24 |
3485250042 ps |
| T170 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1944088546 |
|
|
Jul 30 07:53:33 PM PDT 24 |
Jul 30 08:01:22 PM PDT 24 |
4377807502 ps |
| T1253 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1025941118 |
|
|
Jul 30 08:18:09 PM PDT 24 |
Jul 30 08:23:24 PM PDT 24 |
2905477200 ps |
| T1254 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2636986025 |
|
|
Jul 30 08:19:06 PM PDT 24 |
Jul 30 09:06:02 PM PDT 24 |
13754763144 ps |
| T1255 |
/workspace/coverage/default/3.chip_tap_straps_dev.3177841739 |
|
|
Jul 30 08:18:35 PM PDT 24 |
Jul 30 08:37:11 PM PDT 24 |
11213937188 ps |
| T345 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2046641095 |
|
|
Jul 30 07:54:44 PM PDT 24 |
Jul 30 08:02:20 PM PDT 24 |
3966753526 ps |
| T1256 |
/workspace/coverage/default/2.chip_sw_power_idle_load.565248895 |
|
|
Jul 30 08:18:03 PM PDT 24 |
Jul 30 08:31:21 PM PDT 24 |
4157416320 ps |
| T1257 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2625890781 |
|
|
Jul 30 07:57:39 PM PDT 24 |
Jul 30 08:09:36 PM PDT 24 |
4338252888 ps |
| T1258 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2598573620 |
|
|
Jul 30 08:08:23 PM PDT 24 |
Jul 30 08:14:32 PM PDT 24 |
2822409960 ps |
| T1259 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1494058539 |
|
|
Jul 30 07:52:23 PM PDT 24 |
Jul 30 08:03:27 PM PDT 24 |
8705303664 ps |
| T816 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.403139839 |
|
|
Jul 30 08:22:11 PM PDT 24 |
Jul 30 08:29:44 PM PDT 24 |
3820633920 ps |
| T151 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.2260992315 |
|
|
Jul 30 08:03:45 PM PDT 24 |
Jul 30 08:14:22 PM PDT 24 |
3915674424 ps |
| T1260 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3809435922 |
|
|
Jul 30 08:00:37 PM PDT 24 |
Jul 30 09:12:44 PM PDT 24 |
15677826220 ps |
| T1261 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.4111935151 |
|
|
Jul 30 08:13:18 PM PDT 24 |
Jul 30 08:47:28 PM PDT 24 |
13233015824 ps |
| T1262 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.356437447 |
|
|
Jul 30 07:52:49 PM PDT 24 |
Jul 30 08:01:03 PM PDT 24 |
3632669272 ps |
| T51 |
/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3081111879 |
|
|
Jul 30 07:54:28 PM PDT 24 |
Jul 30 07:58:58 PM PDT 24 |
3218311901 ps |
| T259 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.116865176 |
|
|
Jul 30 08:16:21 PM PDT 24 |
Jul 30 08:23:07 PM PDT 24 |
4844256684 ps |
| T1263 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.559159219 |
|
|
Jul 30 08:10:39 PM PDT 24 |
Jul 30 09:19:58 PM PDT 24 |
15204817894 ps |
| T380 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.162733299 |
|
|
Jul 30 08:26:42 PM PDT 24 |
Jul 30 08:36:15 PM PDT 24 |
6259112764 ps |
| T1264 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1821627922 |
|
|
Jul 30 07:52:09 PM PDT 24 |
Jul 30 08:06:22 PM PDT 24 |
9551213400 ps |
| T767 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3578967967 |
|
|
Jul 30 07:55:02 PM PDT 24 |
Jul 30 08:27:29 PM PDT 24 |
11281931878 ps |
| T1265 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3150438602 |
|
|
Jul 30 08:06:11 PM PDT 24 |
Jul 30 08:27:38 PM PDT 24 |
5815765970 ps |
| T811 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1397009690 |
|
|
Jul 30 08:24:17 PM PDT 24 |
Jul 30 08:32:15 PM PDT 24 |
3456867408 ps |
| T335 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.3203345745 |
|
|
Jul 30 07:53:45 PM PDT 24 |
Jul 30 08:12:30 PM PDT 24 |
6381796856 ps |
| T311 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.50456465 |
|
|
Jul 30 08:06:32 PM PDT 24 |
Jul 30 08:13:09 PM PDT 24 |
3318796898 ps |
| T1266 |
/workspace/coverage/default/2.chip_sw_aes_entropy.2018979179 |
|
|
Jul 30 08:12:12 PM PDT 24 |
Jul 30 08:16:31 PM PDT 24 |
2736936480 ps |
| T819 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1935947341 |
|
|
Jul 30 08:29:48 PM PDT 24 |
Jul 30 08:36:09 PM PDT 24 |
3723340240 ps |
| T1267 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2448750285 |
|
|
Jul 30 08:10:48 PM PDT 24 |
Jul 30 08:20:27 PM PDT 24 |
4865533240 ps |
| T270 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.239502867 |
|
|
Jul 30 08:22:19 PM PDT 24 |
Jul 30 08:32:54 PM PDT 24 |
4609565064 ps |
| T1268 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.464271197 |
|
|
Jul 30 08:00:36 PM PDT 24 |
Jul 30 09:13:24 PM PDT 24 |
15735288966 ps |
| T1269 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1061964263 |
|
|
Jul 30 07:51:45 PM PDT 24 |
Jul 30 08:04:00 PM PDT 24 |
4433268340 ps |
| T1270 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3541151802 |
|
|
Jul 30 07:55:38 PM PDT 24 |
Jul 30 08:17:39 PM PDT 24 |
6778492022 ps |
| T1271 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2086014776 |
|
|
Jul 30 08:22:04 PM PDT 24 |
Jul 30 08:46:42 PM PDT 24 |
9205395942 ps |
| T271 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2412696462 |
|
|
Jul 30 08:03:14 PM PDT 24 |
Jul 30 08:15:55 PM PDT 24 |
5499499384 ps |
| T1272 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.27481408 |
|
|
Jul 30 07:52:59 PM PDT 24 |
Jul 30 08:43:47 PM PDT 24 |
12751343603 ps |
| T1273 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3879460247 |
|
|
Jul 30 07:56:07 PM PDT 24 |
Jul 30 08:41:17 PM PDT 24 |
30428615559 ps |
| T1274 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.530631881 |
|
|
Jul 30 07:52:54 PM PDT 24 |
Jul 30 08:02:38 PM PDT 24 |
4493591104 ps |
| T1275 |
/workspace/coverage/default/0.chip_sw_power_idle_load.2280070091 |
|
|
Jul 30 07:57:00 PM PDT 24 |
Jul 30 08:06:54 PM PDT 24 |
3843282432 ps |
| T1276 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4110093816 |
|
|
Jul 30 07:53:30 PM PDT 24 |
Jul 30 08:05:07 PM PDT 24 |
5173722830 ps |
| T1277 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3527543665 |
|
|
Jul 30 08:04:27 PM PDT 24 |
Jul 30 08:15:58 PM PDT 24 |
4618630092 ps |
| T1278 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3964305140 |
|
|
Jul 30 08:30:55 PM PDT 24 |
Jul 30 08:41:39 PM PDT 24 |
5366315240 ps |
| T1279 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2046322236 |
|
|
Jul 30 07:52:11 PM PDT 24 |
Jul 30 08:05:06 PM PDT 24 |
5584349265 ps |
| T423 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3831242681 |
|
|
Jul 30 08:05:30 PM PDT 24 |
Jul 30 08:11:45 PM PDT 24 |
7201809608 ps |
| T1280 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3586661994 |
|
|
Jul 30 08:18:12 PM PDT 24 |
Jul 30 08:26:55 PM PDT 24 |
4057663200 ps |
| T343 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2386179642 |
|
|
Jul 30 07:54:15 PM PDT 24 |
Jul 30 08:04:55 PM PDT 24 |
4027157556 ps |
| T1281 |
/workspace/coverage/default/1.chip_sw_aes_idle.1259371524 |
|
|
Jul 30 08:02:41 PM PDT 24 |
Jul 30 08:06:56 PM PDT 24 |
2592740228 ps |
| T1282 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3043826344 |
|
|
Jul 30 07:58:48 PM PDT 24 |
Jul 30 08:17:06 PM PDT 24 |
16255194191 ps |
| T812 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4009362834 |
|
|
Jul 30 08:21:07 PM PDT 24 |
Jul 30 08:26:57 PM PDT 24 |
3764344968 ps |
| T1283 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3398725544 |
|
|
Jul 30 08:24:55 PM PDT 24 |
Jul 30 08:31:54 PM PDT 24 |
3442524500 ps |
| T299 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3749717650 |
|
|
Jul 30 08:30:17 PM PDT 24 |
Jul 30 08:36:57 PM PDT 24 |
3290633052 ps |
| T1284 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.4143840596 |
|
|
Jul 30 08:09:14 PM PDT 24 |
Jul 30 08:30:25 PM PDT 24 |
7795675996 ps |
| T1285 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3260990606 |
|
|
Jul 30 08:10:02 PM PDT 24 |
Jul 30 08:36:45 PM PDT 24 |
11130420129 ps |
| T1286 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3464420259 |
|
|
Jul 30 07:52:55 PM PDT 24 |
Jul 30 08:04:11 PM PDT 24 |
3535773660 ps |
| T1287 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.1501789296 |
|
|
Jul 30 07:50:41 PM PDT 24 |
Jul 30 07:58:32 PM PDT 24 |
3275846956 ps |
| T1288 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3527366643 |
|
|
Jul 30 08:22:20 PM PDT 24 |
Jul 30 08:33:53 PM PDT 24 |
8991424818 ps |
| T1289 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.2946652333 |
|
|
Jul 30 07:59:19 PM PDT 24 |
Jul 30 08:06:15 PM PDT 24 |
3604881960 ps |
| T1290 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1882837051 |
|
|
Jul 30 08:15:34 PM PDT 24 |
Jul 30 08:27:17 PM PDT 24 |
5121814280 ps |
| T272 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3095907972 |
|
|
Jul 30 07:53:47 PM PDT 24 |
Jul 30 08:04:41 PM PDT 24 |
6312583556 ps |
| T1291 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.2276375557 |
|
|
Jul 30 08:21:30 PM PDT 24 |
Jul 30 09:19:48 PM PDT 24 |
25485044540 ps |
| T1292 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2673117148 |
|
|
Jul 30 07:57:36 PM PDT 24 |
Jul 30 08:20:51 PM PDT 24 |
9739925325 ps |
| T1293 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.552721517 |
|
|
Jul 30 08:20:52 PM PDT 24 |
Jul 30 09:42:18 PM PDT 24 |
15902386887 ps |
| T1294 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1060735955 |
|
|
Jul 30 07:53:47 PM PDT 24 |
Jul 30 08:07:50 PM PDT 24 |
7901445527 ps |
| T1295 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3994097842 |
|
|
Jul 30 07:54:34 PM PDT 24 |
Jul 30 08:05:07 PM PDT 24 |
4463684721 ps |
| T1296 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.1994275943 |
|
|
Jul 30 07:55:10 PM PDT 24 |
Jul 30 08:20:10 PM PDT 24 |
4960923720 ps |
| T1297 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.4253715454 |
|
|
Jul 30 08:11:57 PM PDT 24 |
Jul 30 08:20:43 PM PDT 24 |
3552869800 ps |
| T1298 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.894786564 |
|
|
Jul 30 08:06:53 PM PDT 24 |
Jul 30 08:12:10 PM PDT 24 |
3306191080 ps |
| T1299 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2920151503 |
|
|
Jul 30 07:53:51 PM PDT 24 |
Jul 30 08:01:13 PM PDT 24 |
4683753344 ps |
| T1300 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1342093485 |
|
|
Jul 30 08:10:10 PM PDT 24 |
Jul 30 08:19:34 PM PDT 24 |
4778860770 ps |
| T162 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2947778028 |
|
|
Jul 30 08:09:21 PM PDT 24 |
Jul 30 08:10:55 PM PDT 24 |
2409101380 ps |
| T1301 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3799045804 |
|
|
Jul 30 08:07:42 PM PDT 24 |
Jul 30 08:17:03 PM PDT 24 |
3787073410 ps |
| T1302 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1610418562 |
|
|
Jul 30 07:58:33 PM PDT 24 |
Jul 30 08:13:05 PM PDT 24 |
5378430530 ps |
| T1303 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.173410390 |
|
|
Jul 30 07:55:41 PM PDT 24 |
Jul 30 08:02:49 PM PDT 24 |
3849178168 ps |
| T837 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.139677139 |
|
|
Jul 30 08:23:07 PM PDT 24 |
Jul 30 08:28:33 PM PDT 24 |
3776537500 ps |
| T1304 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3959598884 |
|
|
Jul 30 07:59:39 PM PDT 24 |
Jul 30 08:10:58 PM PDT 24 |
4798688490 ps |
| T1305 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.1239154339 |
|
|
Jul 30 08:11:00 PM PDT 24 |
Jul 30 09:41:17 PM PDT 24 |
15166391574 ps |
| T1306 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.1476696791 |
|
|
Jul 30 07:55:30 PM PDT 24 |
Jul 30 08:13:47 PM PDT 24 |
5744316312 ps |
| T396 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3169868911 |
|
|
Jul 30 08:15:42 PM PDT 24 |
Jul 30 08:20:47 PM PDT 24 |
2678116256 ps |
| T1307 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.896280553 |
|
|
Jul 30 08:19:50 PM PDT 24 |
Jul 30 08:33:26 PM PDT 24 |
3903476950 ps |
| T716 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.5353360 |
|
|
Jul 30 07:52:14 PM PDT 24 |
Jul 30 08:00:21 PM PDT 24 |
3183805000 ps |
| T1308 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1040144725 |
|
|
Jul 30 07:58:23 PM PDT 24 |
Jul 30 08:46:21 PM PDT 24 |
10971952256 ps |
| T818 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3644327672 |
|
|
Jul 30 08:27:55 PM PDT 24 |
Jul 30 08:33:36 PM PDT 24 |
3979551830 ps |
| T1309 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1660473323 |
|
|
Jul 30 08:14:24 PM PDT 24 |
Jul 30 08:23:38 PM PDT 24 |
7983846100 ps |
| T1310 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.616143350 |
|
|
Jul 30 08:18:07 PM PDT 24 |
Jul 30 08:27:02 PM PDT 24 |
4336444680 ps |
| T1311 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.761935184 |
|
|
Jul 30 08:13:00 PM PDT 24 |
Jul 30 08:39:37 PM PDT 24 |
7164652994 ps |
| T1312 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.2771956794 |
|
|
Jul 30 08:06:28 PM PDT 24 |
Jul 30 08:08:12 PM PDT 24 |
2049941204 ps |
| T1313 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.4261379233 |
|
|
Jul 30 08:19:59 PM PDT 24 |
Jul 30 08:27:27 PM PDT 24 |
5849379444 ps |
| T1314 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2502932829 |
|
|
Jul 30 07:57:37 PM PDT 24 |
Jul 30 11:11:55 PM PDT 24 |
58123875736 ps |
| T774 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.3683452387 |
|
|
Jul 30 08:24:07 PM PDT 24 |
Jul 30 08:39:23 PM PDT 24 |
6093384378 ps |
| T1315 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3804352224 |
|
|
Jul 30 08:28:59 PM PDT 24 |
Jul 30 08:33:57 PM PDT 24 |
3698559480 ps |
| T1316 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.4078412315 |
|
|
Jul 30 08:12:57 PM PDT 24 |
Jul 30 08:17:38 PM PDT 24 |
2392194200 ps |
| T1317 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1862338829 |
|
|
Jul 30 08:24:00 PM PDT 24 |
Jul 30 08:35:26 PM PDT 24 |
4080292240 ps |
| T1318 |
/workspace/coverage/default/0.chip_sw_example_flash.2198446413 |
|
|
Jul 30 07:52:39 PM PDT 24 |
Jul 30 07:57:02 PM PDT 24 |
3153959372 ps |
| T862 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.2090926577 |
|
|
Jul 30 08:27:09 PM PDT 24 |
Jul 30 08:36:54 PM PDT 24 |
4878924610 ps |
| T355 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.459169857 |
|
|
Jul 30 07:56:00 PM PDT 24 |
Jul 30 08:01:11 PM PDT 24 |
3299963680 ps |
| T1319 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.701811939 |
|
|
Jul 30 08:15:52 PM PDT 24 |
Jul 30 08:51:45 PM PDT 24 |
12610121794 ps |
| T1320 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1391551305 |
|
|
Jul 30 08:04:20 PM PDT 24 |
Jul 30 08:16:11 PM PDT 24 |
5823065550 ps |
| T36 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3181497547 |
|
|
Jul 30 07:59:47 PM PDT 24 |
Jul 30 08:10:11 PM PDT 24 |
6420303240 ps |
| T1321 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2014776052 |
|
|
Jul 30 07:53:30 PM PDT 24 |
Jul 30 08:04:12 PM PDT 24 |
6912016650 ps |
| T1322 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1064909174 |
|
|
Jul 30 08:21:31 PM PDT 24 |
Jul 30 09:12:34 PM PDT 24 |
12225468114 ps |
| T103 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3226735278 |
|
|
Jul 30 07:55:32 PM PDT 24 |
Jul 30 08:04:03 PM PDT 24 |
5837886718 ps |
| T374 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1252038379 |
|
|
Jul 30 07:52:46 PM PDT 24 |
Jul 30 07:58:37 PM PDT 24 |
5998779944 ps |
| T431 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.258456186 |
|
|
Jul 30 08:19:52 PM PDT 24 |
Jul 30 08:31:12 PM PDT 24 |
4356430590 ps |
| T432 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3959449001 |
|
|
Jul 30 08:00:02 PM PDT 24 |
Jul 30 09:45:24 PM PDT 24 |
24777101956 ps |
| T300 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.84057549 |
|
|
Jul 30 08:29:15 PM PDT 24 |
Jul 30 08:36:06 PM PDT 24 |
3552286512 ps |
| T433 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1005234167 |
|
|
Jul 30 08:20:11 PM PDT 24 |
Jul 30 08:26:42 PM PDT 24 |
3428448008 ps |
| T130 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1753187521 |
|
|
Jul 30 07:52:53 PM PDT 24 |
Jul 30 08:04:16 PM PDT 24 |
6555716376 ps |
| T434 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.3878284108 |
|
|
Jul 30 07:50:42 PM PDT 24 |
Jul 30 07:59:11 PM PDT 24 |
4338891444 ps |
| T435 |
/workspace/coverage/default/2.chip_sw_hmac_multistream.3873143696 |
|
|
Jul 30 08:13:20 PM PDT 24 |
Jul 30 08:46:33 PM PDT 24 |
7787263172 ps |
| T436 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3144819032 |
|
|
Jul 30 07:54:24 PM PDT 24 |
Jul 30 08:09:23 PM PDT 24 |
5615764664 ps |
| T836 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.658076717 |
|
|
Jul 30 08:26:35 PM PDT 24 |
Jul 30 08:36:43 PM PDT 24 |
5448670366 ps |
| T1323 |
/workspace/coverage/default/1.rom_e2e_static_critical.491359658 |
|
|
Jul 30 08:10:10 PM PDT 24 |
Jul 30 09:29:08 PM PDT 24 |
17869221522 ps |
| T1324 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.661317814 |
|
|
Jul 30 07:53:30 PM PDT 24 |
Jul 30 07:59:28 PM PDT 24 |
4882718215 ps |
| T1325 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3847707055 |
|
|
Jul 30 07:59:50 PM PDT 24 |
Jul 30 08:08:32 PM PDT 24 |
6117046660 ps |
| T1326 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.3100789678 |
|
|
Jul 30 08:28:03 PM PDT 24 |
Jul 30 08:37:19 PM PDT 24 |
5354653320 ps |
| T1327 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.32307924 |
|
|
Jul 30 08:03:19 PM PDT 24 |
Jul 30 08:14:16 PM PDT 24 |
4202180840 ps |
| T1328 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.1915481026 |
|
|
Jul 30 08:03:17 PM PDT 24 |
Jul 30 08:08:41 PM PDT 24 |
3334401600 ps |
| T1329 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2661112858 |
|
|
Jul 30 08:12:47 PM PDT 24 |
Jul 30 08:34:52 PM PDT 24 |
7712701212 ps |
| T301 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3136401051 |
|
|
Jul 30 08:25:04 PM PDT 24 |
Jul 30 08:32:26 PM PDT 24 |
4292602462 ps |
| T1330 |
/workspace/coverage/default/2.chip_sw_kmac_idle.1534468234 |
|
|
Jul 30 08:14:15 PM PDT 24 |
Jul 30 08:19:36 PM PDT 24 |
2426161810 ps |
| T1331 |
/workspace/coverage/default/1.chip_sw_edn_kat.2451302426 |
|
|
Jul 30 08:02:00 PM PDT 24 |
Jul 30 08:12:57 PM PDT 24 |
3444872442 ps |
| T1332 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1919486265 |
|
|
Jul 30 07:58:10 PM PDT 24 |
Jul 30 08:09:16 PM PDT 24 |
4228162360 ps |
| T1333 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3421009416 |
|
|
Jul 30 08:16:57 PM PDT 24 |
Jul 30 09:34:46 PM PDT 24 |
25300929368 ps |
| T1334 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2953844044 |
|
|
Jul 30 08:18:12 PM PDT 24 |
Jul 30 08:52:30 PM PDT 24 |
20048789687 ps |
| T48 |
/workspace/coverage/default/0.chip_sw_alert_test.150239323 |
|
|
Jul 30 07:55:37 PM PDT 24 |
Jul 30 08:02:28 PM PDT 24 |
2579769590 ps |
| T1335 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1342390572 |
|
|
Jul 30 07:51:24 PM PDT 24 |
Jul 30 07:57:13 PM PDT 24 |
3295965236 ps |
| T1336 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2425420864 |
|
|
Jul 30 07:57:12 PM PDT 24 |
Jul 30 08:03:26 PM PDT 24 |
2685274440 ps |
| T1337 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2316949949 |
|
|
Jul 30 07:57:41 PM PDT 24 |
Jul 30 08:09:45 PM PDT 24 |
4396464352 ps |
| T273 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.1368702488 |
|
|
Jul 30 08:27:19 PM PDT 24 |
Jul 30 08:36:05 PM PDT 24 |
4182821978 ps |
| T848 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1405379253 |
|
|
Jul 30 08:33:03 PM PDT 24 |
Jul 30 08:43:07 PM PDT 24 |
6385674448 ps |
| T1338 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3935430879 |
|
|
Jul 30 07:53:45 PM PDT 24 |
Jul 30 08:34:17 PM PDT 24 |
25844048805 ps |
| T840 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2191027686 |
|
|
Jul 30 08:29:15 PM PDT 24 |
Jul 30 08:35:40 PM PDT 24 |
3744003310 ps |
| T1339 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.372339457 |
|
|
Jul 30 08:00:07 PM PDT 24 |
Jul 30 08:19:52 PM PDT 24 |
12161779924 ps |
| T1340 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.3738618920 |
|
|
Jul 30 07:51:22 PM PDT 24 |
Jul 30 11:15:58 PM PDT 24 |
66841545252 ps |
| T771 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2828917455 |
|
|
Jul 30 08:21:49 PM PDT 24 |
Jul 30 08:29:26 PM PDT 24 |
3352931440 ps |
| T1341 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3832762563 |
|
|
Jul 30 07:57:31 PM PDT 24 |
Jul 30 08:05:08 PM PDT 24 |
5978589890 ps |
| T809 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.951909280 |
|
|
Jul 30 08:22:35 PM PDT 24 |
Jul 30 08:29:42 PM PDT 24 |
3450451200 ps |
| T1342 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1000985067 |
|
|
Jul 30 08:15:12 PM PDT 24 |
Jul 30 08:25:17 PM PDT 24 |
4130369712 ps |
| T1343 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.4046025189 |
|
|
Jul 30 08:02:53 PM PDT 24 |
Jul 30 08:07:50 PM PDT 24 |
3614397836 ps |
| T1344 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.231198717 |
|
|
Jul 30 08:20:48 PM PDT 24 |
Jul 30 08:31:50 PM PDT 24 |
4572379400 ps |
| T424 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1488117763 |
|
|
Jul 30 07:55:06 PM PDT 24 |
Jul 30 08:17:13 PM PDT 24 |
23284450780 ps |
| T1345 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1634422683 |
|
|
Jul 30 07:58:23 PM PDT 24 |
Jul 30 08:00:15 PM PDT 24 |
2592413912 ps |
| T1346 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2532994398 |
|
|
Jul 30 07:54:53 PM PDT 24 |
Jul 30 08:01:53 PM PDT 24 |
6088009340 ps |
| T801 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3946099772 |
|
|
Jul 30 08:22:55 PM PDT 24 |
Jul 30 08:29:07 PM PDT 24 |
3323634118 ps |
| T1347 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3480226004 |
|
|
Jul 30 07:59:11 PM PDT 24 |
Jul 30 08:42:50 PM PDT 24 |
25564464050 ps |
| T1348 |
/workspace/coverage/default/0.chip_sw_example_rom.4088310064 |
|
|
Jul 30 07:50:13 PM PDT 24 |
Jul 30 07:52:36 PM PDT 24 |
2452976504 ps |
| T1349 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.117266521 |
|
|
Jul 30 08:04:27 PM PDT 24 |
Jul 30 08:28:11 PM PDT 24 |
6792488714 ps |
| T202 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3077587906 |
|
|
Jul 30 08:09:03 PM PDT 24 |
Jul 30 08:17:06 PM PDT 24 |
3826414676 ps |
| T1350 |
/workspace/coverage/default/1.chip_sw_flash_init.391467507 |
|
|
Jul 30 07:57:36 PM PDT 24 |
Jul 30 08:44:21 PM PDT 24 |
23339818346 ps |
| T1351 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.3996157813 |
|
|
Jul 30 08:19:08 PM PDT 24 |
Jul 30 08:25:20 PM PDT 24 |
3614049828 ps |
| T1352 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.3826644170 |
|
|
Jul 30 07:51:15 PM PDT 24 |
Jul 30 07:56:06 PM PDT 24 |
3195571176 ps |
| T1353 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.847231572 |
|
|
Jul 30 07:54:15 PM PDT 24 |
Jul 30 08:04:41 PM PDT 24 |
4114113460 ps |
| T84 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.102750837 |
|
|
Jul 30 08:24:18 PM PDT 24 |
Jul 30 08:31:48 PM PDT 24 |
4027313368 ps |
| T1354 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.4093805203 |
|
|
Jul 30 08:00:27 PM PDT 24 |
Jul 30 09:44:02 PM PDT 24 |
23060131571 ps |
| T1355 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1863638157 |
|
|
Jul 30 08:03:48 PM PDT 24 |
Jul 30 08:13:16 PM PDT 24 |
5045043280 ps |
| T830 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.2500849457 |
|
|
Jul 30 08:25:52 PM PDT 24 |
Jul 30 08:34:37 PM PDT 24 |
4121353710 ps |
| T1356 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2466331307 |
|
|
Jul 30 08:08:18 PM PDT 24 |
Jul 30 08:29:37 PM PDT 24 |
8616787088 ps |
| T52 |
/workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.1941393395 |
|
|
Jul 30 08:01:38 PM PDT 24 |
Jul 30 08:08:03 PM PDT 24 |
2844144260 ps |
| T280 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1090330025 |
|
|
Jul 30 08:18:35 PM PDT 24 |
Jul 30 08:33:56 PM PDT 24 |
5716457298 ps |
| T282 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.823296432 |
|
|
Jul 30 08:12:55 PM PDT 24 |
Jul 30 08:23:36 PM PDT 24 |
6844174444 ps |
| T283 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2926678275 |
|
|
Jul 30 08:01:56 PM PDT 24 |
Jul 30 08:06:58 PM PDT 24 |
3240909496 ps |
| T284 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.1435495975 |
|
|
Jul 30 07:54:45 PM PDT 24 |
Jul 30 08:14:11 PM PDT 24 |
7565538632 ps |
| T285 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1420602264 |
|
|
Jul 30 07:54:26 PM PDT 24 |
Jul 30 08:00:41 PM PDT 24 |
4989748384 ps |
| T286 |
/workspace/coverage/default/0.chip_sw_hmac_multistream.2477548399 |
|
|
Jul 30 07:53:51 PM PDT 24 |
Jul 30 08:25:13 PM PDT 24 |
7893856020 ps |
| T287 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1031145162 |
|
|
Jul 30 08:03:47 PM PDT 24 |
Jul 30 08:09:06 PM PDT 24 |
3434238662 ps |
| T288 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.1735178766 |
|
|
Jul 30 08:05:54 PM PDT 24 |
Jul 30 08:13:04 PM PDT 24 |
9742955000 ps |
| T289 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1077351736 |
|
|
Jul 30 07:54:19 PM PDT 24 |
Jul 30 08:04:13 PM PDT 24 |
4120803406 ps |
| T290 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1877482387 |
|
|
Jul 30 07:52:45 PM PDT 24 |
Jul 30 08:00:06 PM PDT 24 |
4663090720 ps |
| T1357 |
/workspace/coverage/default/1.chip_sival_flash_info_access.1572102509 |
|
|
Jul 30 07:54:44 PM PDT 24 |
Jul 30 07:59:32 PM PDT 24 |
3410004348 ps |
| T1358 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.947059672 |
|
|
Jul 30 08:12:07 PM PDT 24 |
Jul 30 08:16:49 PM PDT 24 |
3458778699 ps |
| T1359 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.4167691035 |
|
|
Jul 30 08:11:03 PM PDT 24 |
Jul 30 08:24:30 PM PDT 24 |
5100522790 ps |
| T163 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2516267011 |
|
|
Jul 30 07:52:43 PM PDT 24 |
Jul 30 07:54:19 PM PDT 24 |
2012320797 ps |
| T1360 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.3263389848 |
|
|
Jul 30 08:19:21 PM PDT 24 |
Jul 30 08:37:07 PM PDT 24 |
5653189400 ps |
| T804 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.160402610 |
|
|
Jul 30 08:27:27 PM PDT 24 |
Jul 30 08:39:15 PM PDT 24 |
4823304412 ps |
| T1361 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.4176413525 |
|
|
Jul 30 08:25:54 PM PDT 24 |
Jul 30 08:39:20 PM PDT 24 |
5260942508 ps |
| T1362 |
/workspace/coverage/default/1.chip_sw_kmac_idle.3840351092 |
|
|
Jul 30 08:02:43 PM PDT 24 |
Jul 30 08:06:31 PM PDT 24 |
2830619500 ps |
| T375 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1371357789 |
|
|
Jul 30 08:15:57 PM PDT 24 |
Jul 30 08:26:44 PM PDT 24 |
7205114488 ps |
| T1363 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2723768601 |
|
|
Jul 30 07:53:28 PM PDT 24 |
Jul 30 08:00:52 PM PDT 24 |
3548168544 ps |
| T131 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.553687456 |
|
|
Jul 30 08:13:18 PM PDT 24 |
Jul 30 08:33:23 PM PDT 24 |
9099554352 ps |
| T1364 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.718022717 |
|
|
Jul 30 08:19:59 PM PDT 24 |
Jul 30 09:48:36 PM PDT 24 |
33937067074 ps |
| T1365 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3024309352 |
|
|
Jul 30 08:02:04 PM PDT 24 |
Jul 30 08:20:40 PM PDT 24 |
5072937708 ps |
| T1366 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.882264074 |
|
|
Jul 30 08:09:39 PM PDT 24 |
Jul 30 08:21:57 PM PDT 24 |
5469378940 ps |
| T1367 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2629453462 |
|
|
Jul 30 08:20:40 PM PDT 24 |
Jul 30 08:31:37 PM PDT 24 |
4434408540 ps |
| T152 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.3171970849 |
|
|
Jul 30 08:14:04 PM PDT 24 |
Jul 30 08:22:41 PM PDT 24 |
3853118944 ps |
| T1368 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.95410433 |
|
|
Jul 30 08:08:39 PM PDT 24 |
Jul 30 08:12:18 PM PDT 24 |
3385829368 ps |
| T1369 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.1240950081 |
|
|
Jul 30 07:59:31 PM PDT 24 |
Jul 30 08:58:14 PM PDT 24 |
26495391146 ps |
| T1370 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3799213214 |
|
|
Jul 30 08:03:27 PM PDT 24 |
Jul 30 08:07:27 PM PDT 24 |
3544803170 ps |
| T810 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2177562323 |
|
|
Jul 30 08:21:07 PM PDT 24 |
Jul 30 08:28:02 PM PDT 24 |
4147002072 ps |
| T1371 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1694779286 |
|
|
Jul 30 08:10:26 PM PDT 24 |
Jul 30 09:38:20 PM PDT 24 |
45217207675 ps |
| T281 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1524583029 |
|
|
Jul 30 07:50:50 PM PDT 24 |
Jul 30 08:04:55 PM PDT 24 |
6669280828 ps |
| T1372 |
/workspace/coverage/default/1.chip_sw_example_concurrency.1046045698 |
|
|
Jul 30 07:55:37 PM PDT 24 |
Jul 30 07:59:32 PM PDT 24 |
2971968840 ps |
| T1373 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2038253455 |
|
|
Jul 30 08:21:49 PM PDT 24 |
Jul 30 09:02:40 PM PDT 24 |
12492530350 ps |
| T1374 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.785587594 |
|
|
Jul 30 08:13:19 PM PDT 24 |
Jul 30 09:09:14 PM PDT 24 |
17109254628 ps |
| T1375 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3891270229 |
|
|
Jul 30 08:29:48 PM PDT 24 |
Jul 30 08:39:22 PM PDT 24 |
5182784922 ps |
| T1376 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.838081487 |
|
|
Jul 30 07:53:31 PM PDT 24 |
Jul 30 08:12:23 PM PDT 24 |
5633979776 ps |
| T843 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3642292067 |
|
|
Jul 30 08:30:10 PM PDT 24 |
Jul 30 08:37:28 PM PDT 24 |
4436728614 ps |
| T1377 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3351719442 |
|
|
Jul 30 07:58:26 PM PDT 24 |
Jul 30 08:04:54 PM PDT 24 |
4370326936 ps |
| T11 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1663870970 |
|
|
Jul 30 07:51:14 PM PDT 24 |
Jul 30 07:56:24 PM PDT 24 |
2658456332 ps |
| T858 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1101287815 |
|
|
Jul 30 08:20:16 PM PDT 24 |
Jul 30 08:25:36 PM PDT 24 |
3143818328 ps |