| T1068 |
/workspace/coverage/default/0.chip_sw_example_concurrency.514732661 |
|
|
Jul 30 07:52:07 PM PDT 24 |
Jul 30 07:55:55 PM PDT 24 |
3294631484 ps |
| T126 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3298168636 |
|
|
Jul 30 08:04:34 PM PDT 24 |
Jul 30 08:12:36 PM PDT 24 |
5986609600 ps |
| T354 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.4102792448 |
|
|
Jul 30 07:52:10 PM PDT 24 |
Jul 30 07:56:39 PM PDT 24 |
3328653030 ps |
| T719 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3173775495 |
|
|
Jul 30 08:27:57 PM PDT 24 |
Jul 30 08:34:45 PM PDT 24 |
3665751366 ps |
| T1069 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1751380125 |
|
|
Jul 30 07:59:13 PM PDT 24 |
Jul 30 08:57:20 PM PDT 24 |
40965123186 ps |
| T1070 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3085230487 |
|
|
Jul 30 08:21:16 PM PDT 24 |
Jul 30 08:31:25 PM PDT 24 |
3833243792 ps |
| T241 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1162597871 |
|
|
Jul 30 08:00:24 PM PDT 24 |
Jul 30 09:54:33 PM PDT 24 |
45858413818 ps |
| T370 |
/workspace/coverage/default/1.chip_sw_hmac_enc.3180125344 |
|
|
Jul 30 08:03:06 PM PDT 24 |
Jul 30 08:06:52 PM PDT 24 |
2849443642 ps |
| T736 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.3111351069 |
|
|
Jul 30 08:31:46 PM PDT 24 |
Jul 30 08:41:22 PM PDT 24 |
5961038528 ps |
| T1071 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2803776826 |
|
|
Jul 30 08:13:56 PM PDT 24 |
Jul 30 08:46:55 PM PDT 24 |
20287880588 ps |
| T1072 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1089311618 |
|
|
Jul 30 08:00:15 PM PDT 24 |
Jul 30 09:11:43 PM PDT 24 |
15587270036 ps |
| T821 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.784670990 |
|
|
Jul 30 08:31:23 PM PDT 24 |
Jul 30 08:37:29 PM PDT 24 |
4485129660 ps |
| T1073 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2828297352 |
|
|
Jul 30 08:20:06 PM PDT 24 |
Jul 30 08:27:56 PM PDT 24 |
4391633955 ps |
| T1074 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2708084442 |
|
|
Jul 30 08:09:37 PM PDT 24 |
Jul 30 08:14:56 PM PDT 24 |
3371312500 ps |
| T1075 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3129079537 |
|
|
Jul 30 08:07:49 PM PDT 24 |
Jul 30 08:12:14 PM PDT 24 |
2966554676 ps |
| T1076 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.523224914 |
|
|
Jul 30 08:05:24 PM PDT 24 |
Jul 30 08:09:35 PM PDT 24 |
2832091681 ps |
| T1077 |
/workspace/coverage/default/0.chip_sw_coremark.58073807 |
|
|
Jul 30 07:54:24 PM PDT 24 |
Jul 31 12:05:42 AM PDT 24 |
71255555936 ps |
| T1078 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2224859267 |
|
|
Jul 30 07:51:29 PM PDT 24 |
Jul 30 08:04:33 PM PDT 24 |
4193025280 ps |
| T1079 |
/workspace/coverage/default/0.chip_sival_flash_info_access.1219618163 |
|
|
Jul 30 07:53:21 PM PDT 24 |
Jul 30 07:57:41 PM PDT 24 |
3461793370 ps |
| T1080 |
/workspace/coverage/default/2.rom_keymgr_functest.2297042254 |
|
|
Jul 30 08:19:15 PM PDT 24 |
Jul 30 08:28:35 PM PDT 24 |
4497404240 ps |
| T1081 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.157501029 |
|
|
Jul 30 08:24:11 PM PDT 24 |
Jul 30 08:34:26 PM PDT 24 |
4463350480 ps |
| T296 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1484051125 |
|
|
Jul 30 08:14:20 PM PDT 24 |
Jul 30 08:24:03 PM PDT 24 |
3569885172 ps |
| T1082 |
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2696928114 |
|
|
Jul 30 08:21:52 PM PDT 24 |
Jul 30 09:26:18 PM PDT 24 |
15686799976 ps |
| T1083 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.410611504 |
|
|
Jul 30 08:19:44 PM PDT 24 |
Jul 30 08:27:55 PM PDT 24 |
3613336406 ps |
| T1084 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.837405068 |
|
|
Jul 30 07:53:37 PM PDT 24 |
Jul 30 08:17:29 PM PDT 24 |
8560351264 ps |
| T1085 |
/workspace/coverage/default/3.chip_tap_straps_prod.1705908819 |
|
|
Jul 30 08:19:56 PM PDT 24 |
Jul 30 08:23:00 PM PDT 24 |
2725399232 ps |
| T1086 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.390028581 |
|
|
Jul 30 07:52:31 PM PDT 24 |
Jul 30 08:20:25 PM PDT 24 |
7977526900 ps |
| T1087 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.3435951097 |
|
|
Jul 30 07:57:00 PM PDT 24 |
Jul 30 08:01:26 PM PDT 24 |
2903477068 ps |
| T1088 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2310640667 |
|
|
Jul 30 08:02:52 PM PDT 24 |
Jul 30 09:39:46 PM PDT 24 |
23773097147 ps |
| T1089 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2175912743 |
|
|
Jul 30 07:51:00 PM PDT 24 |
Jul 30 09:35:53 PM PDT 24 |
28388404456 ps |
| T373 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.553575046 |
|
|
Jul 30 08:05:05 PM PDT 24 |
Jul 30 08:12:35 PM PDT 24 |
6323008004 ps |
| T1090 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1339410290 |
|
|
Jul 30 08:11:02 PM PDT 24 |
Jul 30 08:18:33 PM PDT 24 |
4762930676 ps |
| T1091 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1552523946 |
|
|
Jul 30 08:20:55 PM PDT 24 |
Jul 30 09:34:40 PM PDT 24 |
17259332760 ps |
| T340 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2832396194 |
|
|
Jul 30 07:57:29 PM PDT 24 |
Jul 30 08:06:25 PM PDT 24 |
4169407590 ps |
| T1092 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1266757621 |
|
|
Jul 30 07:59:39 PM PDT 24 |
Jul 30 08:09:53 PM PDT 24 |
4076195304 ps |
| T349 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.4209531387 |
|
|
Jul 30 08:09:21 PM PDT 24 |
Jul 30 08:23:59 PM PDT 24 |
3787153540 ps |
| T1093 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.3620155582 |
|
|
Jul 30 08:21:00 PM PDT 24 |
Jul 30 08:25:38 PM PDT 24 |
3254763670 ps |
| T806 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1382047005 |
|
|
Jul 30 08:23:45 PM PDT 24 |
Jul 30 08:30:31 PM PDT 24 |
3723787948 ps |
| T161 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.348094576 |
|
|
Jul 30 07:57:33 PM PDT 24 |
Jul 30 08:01:51 PM PDT 24 |
2739016866 ps |
| T10 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.799284437 |
|
|
Jul 30 08:08:01 PM PDT 24 |
Jul 30 08:14:23 PM PDT 24 |
3357825732 ps |
| T445 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1784814312 |
|
|
Jul 30 08:28:32 PM PDT 24 |
Jul 30 08:36:45 PM PDT 24 |
4360684340 ps |
| T1094 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.334191448 |
|
|
Jul 30 08:01:16 PM PDT 24 |
Jul 30 09:53:34 PM PDT 24 |
23598715990 ps |
| T1095 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.341080914 |
|
|
Jul 30 08:17:43 PM PDT 24 |
Jul 30 08:23:09 PM PDT 24 |
3890724984 ps |
| T1096 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.804223610 |
|
|
Jul 30 08:03:50 PM PDT 24 |
Jul 30 08:17:07 PM PDT 24 |
8505813340 ps |
| T1097 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.2862184994 |
|
|
Jul 30 08:08:21 PM PDT 24 |
Jul 30 08:13:27 PM PDT 24 |
3259649046 ps |
| T319 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1956747308 |
|
|
Jul 30 07:52:29 PM PDT 24 |
Jul 30 08:02:45 PM PDT 24 |
8882912126 ps |
| T211 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2454570301 |
|
|
Jul 30 07:52:26 PM PDT 24 |
Jul 30 08:21:23 PM PDT 24 |
24402000532 ps |
| T1098 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.262299694 |
|
|
Jul 30 08:17:22 PM PDT 24 |
Jul 30 08:23:29 PM PDT 24 |
3602674762 ps |
| T239 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.4109647312 |
|
|
Jul 30 08:10:06 PM PDT 24 |
Jul 30 09:42:50 PM PDT 24 |
49200509427 ps |
| T1099 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.1501878422 |
|
|
Jul 30 08:20:12 PM PDT 24 |
Jul 30 08:50:49 PM PDT 24 |
8347259080 ps |
| T1100 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.4227573101 |
|
|
Jul 30 07:56:56 PM PDT 24 |
Jul 30 08:08:19 PM PDT 24 |
4001304250 ps |
| T1101 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2926939575 |
|
|
Jul 30 07:55:53 PM PDT 24 |
Jul 30 08:03:54 PM PDT 24 |
6695875142 ps |
| T1102 |
/workspace/coverage/default/2.rom_e2e_smoke.3115795674 |
|
|
Jul 30 08:22:03 PM PDT 24 |
Jul 30 09:28:58 PM PDT 24 |
15388513048 ps |
| T824 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.303691366 |
|
|
Jul 30 08:26:22 PM PDT 24 |
Jul 30 08:34:56 PM PDT 24 |
3459223142 ps |
| T1103 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.818113049 |
|
|
Jul 30 07:57:32 PM PDT 24 |
Jul 30 08:04:07 PM PDT 24 |
3972587750 ps |
| T410 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2277103271 |
|
|
Jul 30 08:15:10 PM PDT 24 |
Jul 30 08:38:18 PM PDT 24 |
22735613980 ps |
| T785 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3657137297 |
|
|
Jul 30 08:32:02 PM PDT 24 |
Jul 30 08:38:14 PM PDT 24 |
3615860468 ps |
| T378 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1488672125 |
|
|
Jul 30 08:24:59 PM PDT 24 |
Jul 30 08:33:23 PM PDT 24 |
4179412444 ps |
| T1104 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3406396974 |
|
|
Jul 30 08:15:09 PM PDT 24 |
Jul 30 08:26:38 PM PDT 24 |
3978128586 ps |
| T1105 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1938006928 |
|
|
Jul 30 08:04:37 PM PDT 24 |
Jul 30 08:09:15 PM PDT 24 |
3160272227 ps |
| T1106 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2313308647 |
|
|
Jul 30 08:09:49 PM PDT 24 |
Jul 30 08:40:21 PM PDT 24 |
24867660377 ps |
| T1107 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1885235163 |
|
|
Jul 30 08:05:12 PM PDT 24 |
Jul 30 08:11:16 PM PDT 24 |
5227873450 ps |
| T460 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3031791214 |
|
|
Jul 30 08:13:35 PM PDT 24 |
Jul 30 08:30:32 PM PDT 24 |
6190187794 ps |
| T196 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.827645951 |
|
|
Jul 30 07:54:33 PM PDT 24 |
Jul 30 08:02:23 PM PDT 24 |
3909000529 ps |
| T1108 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1663346785 |
|
|
Jul 30 08:00:53 PM PDT 24 |
Jul 30 08:55:55 PM PDT 24 |
11889419167 ps |
| T297 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.2241767384 |
|
|
Jul 30 07:58:55 PM PDT 24 |
Jul 30 08:13:44 PM PDT 24 |
5625268256 ps |
| T789 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.2475675055 |
|
|
Jul 30 08:22:58 PM PDT 24 |
Jul 30 08:34:05 PM PDT 24 |
4937119920 ps |
| T1109 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2198241140 |
|
|
Jul 30 08:01:34 PM PDT 24 |
Jul 30 08:05:47 PM PDT 24 |
3644931143 ps |
| T846 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3322541542 |
|
|
Jul 30 08:27:21 PM PDT 24 |
Jul 30 08:38:36 PM PDT 24 |
5587115384 ps |
| T405 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1493011025 |
|
|
Jul 30 08:02:41 PM PDT 24 |
Jul 30 08:12:38 PM PDT 24 |
9138337183 ps |
| T841 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3223249418 |
|
|
Jul 30 08:02:25 PM PDT 24 |
Jul 30 08:10:24 PM PDT 24 |
3247881020 ps |
| T1110 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3206625609 |
|
|
Jul 30 07:50:42 PM PDT 24 |
Jul 30 07:57:30 PM PDT 24 |
3888488069 ps |
| T1111 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.54276398 |
|
|
Jul 30 08:03:51 PM PDT 24 |
Jul 30 08:08:47 PM PDT 24 |
3405537128 ps |
| T1112 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.693407832 |
|
|
Jul 30 08:11:25 PM PDT 24 |
Jul 30 08:24:28 PM PDT 24 |
8466932264 ps |
| T715 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.1791868496 |
|
|
Jul 30 08:12:45 PM PDT 24 |
Jul 30 08:25:36 PM PDT 24 |
2951851288 ps |
| T1113 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1246409231 |
|
|
Jul 30 07:50:40 PM PDT 24 |
Jul 30 08:03:35 PM PDT 24 |
5725140636 ps |
| T553 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.138184208 |
|
|
Jul 30 07:55:02 PM PDT 24 |
Jul 30 08:05:39 PM PDT 24 |
5958795680 ps |
| T776 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3964264784 |
|
|
Jul 30 08:27:48 PM PDT 24 |
Jul 30 08:35:07 PM PDT 24 |
4332133874 ps |
| T1114 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.165266922 |
|
|
Jul 30 08:04:11 PM PDT 24 |
Jul 30 08:15:01 PM PDT 24 |
6457125116 ps |
| T1115 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1020732571 |
|
|
Jul 30 07:57:48 PM PDT 24 |
Jul 30 08:11:59 PM PDT 24 |
9532888030 ps |
| T551 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3424140726 |
|
|
Jul 30 08:16:59 PM PDT 24 |
Jul 30 08:25:16 PM PDT 24 |
4022596306 ps |
| T1116 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.3720038080 |
|
|
Jul 30 07:53:55 PM PDT 24 |
Jul 30 07:57:45 PM PDT 24 |
2216735193 ps |
| T1117 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.538059365 |
|
|
Jul 30 08:22:50 PM PDT 24 |
Jul 30 08:29:35 PM PDT 24 |
7016568256 ps |
| T1118 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1424843957 |
|
|
Jul 30 07:52:44 PM PDT 24 |
Jul 30 07:54:35 PM PDT 24 |
1941989558 ps |
| T1119 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3797115810 |
|
|
Jul 30 07:56:53 PM PDT 24 |
Jul 30 08:01:12 PM PDT 24 |
2881441240 ps |
| T1120 |
/workspace/coverage/default/2.chip_sw_edn_kat.1165724008 |
|
|
Jul 30 08:14:32 PM PDT 24 |
Jul 30 08:26:17 PM PDT 24 |
3653899414 ps |
| T160 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1961156440 |
|
|
Jul 30 08:20:48 PM PDT 24 |
Jul 30 11:48:30 PM PDT 24 |
256371869776 ps |
| T243 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1793142646 |
|
|
Jul 30 08:03:18 PM PDT 24 |
Jul 30 09:29:21 PM PDT 24 |
50408346760 ps |
| T1121 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.688069219 |
|
|
Jul 30 08:00:12 PM PDT 24 |
Jul 30 08:07:43 PM PDT 24 |
3900969460 ps |
| T844 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3790943617 |
|
|
Jul 30 08:28:52 PM PDT 24 |
Jul 30 08:39:20 PM PDT 24 |
6132253840 ps |
| T1122 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3538077807 |
|
|
Jul 30 08:18:13 PM PDT 24 |
Jul 30 08:25:44 PM PDT 24 |
6168254940 ps |
| T344 |
/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.830337215 |
|
|
Jul 30 08:14:36 PM PDT 24 |
Jul 30 08:21:24 PM PDT 24 |
3932367582 ps |
| T1123 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.3531496751 |
|
|
Jul 30 07:54:19 PM PDT 24 |
Jul 30 07:59:13 PM PDT 24 |
2978924760 ps |
| T726 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2206499420 |
|
|
Jul 30 08:15:07 PM PDT 24 |
Jul 30 08:23:13 PM PDT 24 |
5056395762 ps |
| T34 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2766575036 |
|
|
Jul 30 07:53:27 PM PDT 24 |
Jul 30 08:02:58 PM PDT 24 |
5928878000 ps |
| T1124 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.2980162563 |
|
|
Jul 30 08:04:16 PM PDT 24 |
Jul 30 08:11:24 PM PDT 24 |
6636987336 ps |
| T1125 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2306934312 |
|
|
Jul 30 07:59:07 PM PDT 24 |
Jul 30 09:09:44 PM PDT 24 |
15360759514 ps |
| T395 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2542761602 |
|
|
Jul 30 07:55:12 PM PDT 24 |
Jul 30 07:58:10 PM PDT 24 |
2418137712 ps |
| T1126 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.4239300450 |
|
|
Jul 30 08:13:13 PM PDT 24 |
Jul 30 09:36:41 PM PDT 24 |
15562677912 ps |
| T1127 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.685051773 |
|
|
Jul 30 08:00:33 PM PDT 24 |
Jul 30 09:06:52 PM PDT 24 |
14713577400 ps |
| T249 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.1688769777 |
|
|
Jul 30 08:22:54 PM PDT 24 |
Jul 30 08:31:42 PM PDT 24 |
5398210820 ps |
| T1128 |
/workspace/coverage/default/0.chip_sw_edn_kat.2645893781 |
|
|
Jul 30 07:54:28 PM PDT 24 |
Jul 30 08:07:36 PM PDT 24 |
3536167240 ps |
| T813 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.3668799670 |
|
|
Jul 30 08:24:34 PM PDT 24 |
Jul 30 08:33:35 PM PDT 24 |
5468773198 ps |
| T1129 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.914485897 |
|
|
Jul 30 08:13:20 PM PDT 24 |
Jul 30 09:15:41 PM PDT 24 |
18783075082 ps |
| T822 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3596222846 |
|
|
Jul 30 08:27:04 PM PDT 24 |
Jul 30 08:33:22 PM PDT 24 |
3547327320 ps |
| T1130 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3776600210 |
|
|
Jul 30 08:07:47 PM PDT 24 |
Jul 30 08:12:39 PM PDT 24 |
3208356604 ps |
| T1131 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.3483228462 |
|
|
Jul 30 08:15:33 PM PDT 24 |
Jul 30 08:21:03 PM PDT 24 |
2921444694 ps |
| T1132 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2736114959 |
|
|
Jul 30 07:58:02 PM PDT 24 |
Jul 30 09:09:52 PM PDT 24 |
15055251251 ps |
| T1133 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.1630829752 |
|
|
Jul 30 08:11:08 PM PDT 24 |
Jul 30 08:29:49 PM PDT 24 |
5448244416 ps |
| T1134 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1223920745 |
|
|
Jul 30 07:57:51 PM PDT 24 |
Jul 30 09:01:39 PM PDT 24 |
14924784140 ps |
| T1135 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2829728769 |
|
|
Jul 30 08:15:11 PM PDT 24 |
Jul 30 08:22:27 PM PDT 24 |
5766334752 ps |
| T1136 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2556824240 |
|
|
Jul 30 08:14:16 PM PDT 24 |
Jul 30 08:28:59 PM PDT 24 |
8151332056 ps |
| T1137 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3171662256 |
|
|
Jul 30 07:54:27 PM PDT 24 |
Jul 30 08:06:57 PM PDT 24 |
3750025020 ps |
| T1138 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3494324774 |
|
|
Jul 30 07:58:56 PM PDT 24 |
Jul 30 08:11:43 PM PDT 24 |
4370733920 ps |
| T1139 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2738579996 |
|
|
Jul 30 08:20:30 PM PDT 24 |
Jul 30 08:31:41 PM PDT 24 |
4016276696 ps |
| T1140 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3261472245 |
|
|
Jul 30 07:52:46 PM PDT 24 |
Jul 30 07:57:57 PM PDT 24 |
2517546900 ps |
| T1141 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.523705669 |
|
|
Jul 30 07:54:07 PM PDT 24 |
Jul 30 11:37:00 PM PDT 24 |
78135029638 ps |
| T35 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3225682873 |
|
|
Jul 30 08:15:20 PM PDT 24 |
Jul 30 08:25:50 PM PDT 24 |
5807614784 ps |
| T1142 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3027830676 |
|
|
Jul 30 08:07:32 PM PDT 24 |
Jul 30 08:12:27 PM PDT 24 |
5231311168 ps |
| T1143 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1021944478 |
|
|
Jul 30 07:58:59 PM PDT 24 |
Jul 30 09:07:56 PM PDT 24 |
15002373048 ps |
| T784 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3699404524 |
|
|
Jul 30 08:20:20 PM PDT 24 |
Jul 30 08:26:51 PM PDT 24 |
3855458700 ps |
| T1144 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3953807114 |
|
|
Jul 30 08:16:01 PM PDT 24 |
Jul 30 08:30:42 PM PDT 24 |
7658748908 ps |
| T1145 |
/workspace/coverage/default/2.chip_sw_aes_idle.288785938 |
|
|
Jul 30 08:11:40 PM PDT 24 |
Jul 30 08:15:06 PM PDT 24 |
3270785770 ps |
| T834 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.1652776658 |
|
|
Jul 30 08:20:04 PM PDT 24 |
Jul 30 08:32:12 PM PDT 24 |
5849516372 ps |
| T1146 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.4197925402 |
|
|
Jul 30 07:57:49 PM PDT 24 |
Jul 30 08:19:06 PM PDT 24 |
8958160130 ps |
| T1147 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2140878680 |
|
|
Jul 30 08:14:39 PM PDT 24 |
Jul 30 08:19:17 PM PDT 24 |
3089259592 ps |
| T1148 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2826502246 |
|
|
Jul 30 08:22:00 PM PDT 24 |
Jul 30 08:42:42 PM PDT 24 |
11184268219 ps |
| T242 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.20268768 |
|
|
Jul 30 07:53:21 PM PDT 24 |
Jul 30 09:30:35 PM PDT 24 |
48170607882 ps |
| T1149 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.329704559 |
|
|
Jul 30 08:07:41 PM PDT 24 |
Jul 30 08:11:58 PM PDT 24 |
2712178456 ps |
| T1150 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2986114032 |
|
|
Jul 30 08:09:30 PM PDT 24 |
Jul 30 08:13:46 PM PDT 24 |
3404105864 ps |
| T33 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1689642855 |
|
|
Jul 30 08:01:13 PM PDT 24 |
Jul 30 08:06:48 PM PDT 24 |
3174208712 ps |
| T197 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.3493357295 |
|
|
Jul 30 08:07:49 PM PDT 24 |
Jul 30 08:17:27 PM PDT 24 |
5810679937 ps |
| T1151 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.3122602947 |
|
|
Jul 30 07:55:40 PM PDT 24 |
Jul 30 08:32:09 PM PDT 24 |
9561259820 ps |
| T252 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3391768767 |
|
|
Jul 30 08:28:51 PM PDT 24 |
Jul 30 08:39:17 PM PDT 24 |
5536360064 ps |
| T1152 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1274515192 |
|
|
Jul 30 07:57:19 PM PDT 24 |
Jul 30 08:00:55 PM PDT 24 |
2868825576 ps |
| T372 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1757795616 |
|
|
Jul 30 08:19:44 PM PDT 24 |
Jul 30 08:26:32 PM PDT 24 |
3690854032 ps |
| T1153 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.901707280 |
|
|
Jul 30 08:14:55 PM PDT 24 |
Jul 30 08:22:53 PM PDT 24 |
3294775760 ps |
| T825 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3990886439 |
|
|
Jul 30 08:21:43 PM PDT 24 |
Jul 30 08:28:51 PM PDT 24 |
3872996532 ps |
| T203 |
/workspace/coverage/default/0.chip_jtag_mem_access.2491901346 |
|
|
Jul 30 07:45:20 PM PDT 24 |
Jul 30 08:12:32 PM PDT 24 |
13812059600 ps |
| T845 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1610169477 |
|
|
Jul 30 08:29:05 PM PDT 24 |
Jul 30 08:35:52 PM PDT 24 |
4036324496 ps |
| T371 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1088567968 |
|
|
Jul 30 08:01:55 PM PDT 24 |
Jul 30 08:06:34 PM PDT 24 |
3004119018 ps |
| T805 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.2539155727 |
|
|
Jul 30 08:21:56 PM PDT 24 |
Jul 30 08:31:10 PM PDT 24 |
4998876824 ps |
| T53 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1570180852 |
|
|
Jul 30 07:52:38 PM PDT 24 |
Jul 30 07:57:17 PM PDT 24 |
3405114408 ps |
| T406 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3920935116 |
|
|
Jul 30 07:52:54 PM PDT 24 |
Jul 30 08:05:05 PM PDT 24 |
8339078222 ps |
| T415 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2435574425 |
|
|
Jul 30 07:55:30 PM PDT 24 |
Jul 30 08:02:29 PM PDT 24 |
4467881632 ps |
| T416 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2309878097 |
|
|
Jul 30 08:13:23 PM PDT 24 |
Jul 30 08:32:14 PM PDT 24 |
5747725480 ps |
| T417 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.906051909 |
|
|
Jul 30 08:25:37 PM PDT 24 |
Jul 30 08:31:39 PM PDT 24 |
3035189392 ps |
| T418 |
/workspace/coverage/default/1.chip_sw_example_flash.946741138 |
|
|
Jul 30 07:56:03 PM PDT 24 |
Jul 30 08:00:09 PM PDT 24 |
2816606756 ps |
| T419 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.2010565090 |
|
|
Jul 30 08:05:56 PM PDT 24 |
Jul 30 08:10:58 PM PDT 24 |
2789267972 ps |
| T420 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.2369698410 |
|
|
Jul 30 08:08:11 PM PDT 24 |
Jul 30 08:12:46 PM PDT 24 |
3047320250 ps |
| T421 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2747635101 |
|
|
Jul 30 08:05:09 PM PDT 24 |
Jul 30 08:09:09 PM PDT 24 |
3234630399 ps |
| T422 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.318190045 |
|
|
Jul 30 08:11:44 PM PDT 24 |
Jul 30 08:28:08 PM PDT 24 |
5064764824 ps |
| T1154 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.965762208 |
|
|
Jul 30 07:58:22 PM PDT 24 |
Jul 30 08:06:24 PM PDT 24 |
6974325640 ps |
| T1155 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2989326659 |
|
|
Jul 30 07:51:05 PM PDT 24 |
Jul 30 07:57:16 PM PDT 24 |
3331581480 ps |
| T803 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3434434145 |
|
|
Jul 30 08:29:55 PM PDT 24 |
Jul 30 08:40:41 PM PDT 24 |
5786981344 ps |
| T204 |
/workspace/coverage/default/0.chip_jtag_csr_rw.1292862262 |
|
|
Jul 30 07:45:24 PM PDT 24 |
Jul 30 08:02:56 PM PDT 24 |
10883215970 ps |
| T1156 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2968014894 |
|
|
Jul 30 07:59:35 PM PDT 24 |
Jul 30 08:20:03 PM PDT 24 |
5614519479 ps |
| T777 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.776780359 |
|
|
Jul 30 08:28:35 PM PDT 24 |
Jul 30 08:35:54 PM PDT 24 |
3959530712 ps |
| T107 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3660296459 |
|
|
Jul 30 08:17:34 PM PDT 24 |
Jul 30 09:27:53 PM PDT 24 |
25173186829 ps |
| T78 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3464001784 |
|
|
Jul 30 08:00:15 PM PDT 24 |
Jul 30 08:24:30 PM PDT 24 |
13495882690 ps |
| T1157 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4289930321 |
|
|
Jul 30 07:53:11 PM PDT 24 |
Jul 30 08:20:10 PM PDT 24 |
12878140877 ps |
| T815 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.2836843969 |
|
|
Jul 30 08:22:20 PM PDT 24 |
Jul 30 08:33:55 PM PDT 24 |
5702924852 ps |
| T244 |
/workspace/coverage/default/2.chip_sw_flash_init.2004566590 |
|
|
Jul 30 08:10:06 PM PDT 24 |
Jul 30 08:52:19 PM PDT 24 |
20971889791 ps |
| T770 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.4193621119 |
|
|
Jul 30 08:31:06 PM PDT 24 |
Jul 30 08:38:58 PM PDT 24 |
4880834328 ps |
| T1158 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.254408868 |
|
|
Jul 30 07:59:40 PM PDT 24 |
Jul 30 08:11:58 PM PDT 24 |
5077073040 ps |
| T1159 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1023839880 |
|
|
Jul 30 08:21:26 PM PDT 24 |
Jul 30 08:41:42 PM PDT 24 |
13044369115 ps |
| T147 |
/workspace/coverage/default/2.rom_raw_unlock.3377763660 |
|
|
Jul 30 08:17:22 PM PDT 24 |
Jul 30 08:22:09 PM PDT 24 |
5871963863 ps |
| T1160 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3978175562 |
|
|
Jul 30 07:51:39 PM PDT 24 |
Jul 30 08:16:47 PM PDT 24 |
8539982456 ps |
| T741 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3523711798 |
|
|
Jul 30 07:59:25 PM PDT 24 |
Jul 30 08:03:39 PM PDT 24 |
3126240060 ps |
| T738 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1092757251 |
|
|
Jul 30 07:52:46 PM PDT 24 |
Jul 30 08:05:58 PM PDT 24 |
5130896168 ps |
| T1161 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.751519392 |
|
|
Jul 30 08:18:09 PM PDT 24 |
Jul 30 08:23:44 PM PDT 24 |
3349676044 ps |
| T1162 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3422989272 |
|
|
Jul 30 08:07:49 PM PDT 24 |
Jul 30 08:26:24 PM PDT 24 |
9246415588 ps |
| T1163 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1123645380 |
|
|
Jul 30 08:00:19 PM PDT 24 |
Jul 30 09:04:11 PM PDT 24 |
13881343025 ps |
| T1164 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.902461113 |
|
|
Jul 30 08:06:06 PM PDT 24 |
Jul 30 08:15:56 PM PDT 24 |
4968742901 ps |
| T404 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3869458378 |
|
|
Jul 30 07:55:30 PM PDT 24 |
Jul 30 08:01:30 PM PDT 24 |
3374453293 ps |
| T1165 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.518533382 |
|
|
Jul 30 08:15:02 PM PDT 24 |
Jul 30 08:26:17 PM PDT 24 |
4613000968 ps |
| T1166 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1724531069 |
|
|
Jul 30 07:54:20 PM PDT 24 |
Jul 30 08:04:38 PM PDT 24 |
4815012000 ps |
| T1167 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.4182314354 |
|
|
Jul 30 08:01:48 PM PDT 24 |
Jul 30 08:06:25 PM PDT 24 |
2446211550 ps |
| T1168 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.1058915236 |
|
|
Jul 30 08:04:45 PM PDT 24 |
Jul 30 08:09:52 PM PDT 24 |
2791462267 ps |
| T1169 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1790193160 |
|
|
Jul 30 08:21:11 PM PDT 24 |
Jul 30 08:27:25 PM PDT 24 |
3729896130 ps |
| T772 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.643015153 |
|
|
Jul 30 08:19:26 PM PDT 24 |
Jul 30 08:27:06 PM PDT 24 |
3450897160 ps |
| T1170 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3574995402 |
|
|
Jul 30 08:09:08 PM PDT 24 |
Jul 30 08:25:45 PM PDT 24 |
5998041499 ps |
| T1171 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.4031504855 |
|
|
Jul 30 08:21:45 PM PDT 24 |
Jul 30 09:33:23 PM PDT 24 |
14925202552 ps |
| T333 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.486695823 |
|
|
Jul 30 07:53:38 PM PDT 24 |
Jul 30 08:16:22 PM PDT 24 |
6630402788 ps |
| T1172 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3218205601 |
|
|
Jul 30 07:55:42 PM PDT 24 |
Jul 30 08:56:24 PM PDT 24 |
13139017492 ps |
| T1173 |
/workspace/coverage/default/0.chip_tap_straps_dev.3733721505 |
|
|
Jul 30 07:51:45 PM PDT 24 |
Jul 30 07:54:01 PM PDT 24 |
2284590636 ps |
| T851 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2755708403 |
|
|
Jul 30 08:24:53 PM PDT 24 |
Jul 30 08:33:14 PM PDT 24 |
4514873496 ps |
| T1174 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.968295713 |
|
|
Jul 30 07:54:48 PM PDT 24 |
Jul 30 08:06:23 PM PDT 24 |
6313456204 ps |
| T1175 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.241343560 |
|
|
Jul 30 07:54:54 PM PDT 24 |
Jul 30 08:05:43 PM PDT 24 |
4074646080 ps |
| T1176 |
/workspace/coverage/default/0.chip_sw_aes_entropy.52409659 |
|
|
Jul 30 07:51:22 PM PDT 24 |
Jul 30 07:55:37 PM PDT 24 |
2893373860 ps |
| T1177 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.3020787190 |
|
|
Jul 30 08:11:53 PM PDT 24 |
Jul 30 08:16:44 PM PDT 24 |
3544149843 ps |
| T1178 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.568518791 |
|
|
Jul 30 07:56:05 PM PDT 24 |
Jul 30 08:01:33 PM PDT 24 |
2648079104 ps |
| T1179 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1552277126 |
|
|
Jul 30 08:01:26 PM PDT 24 |
Jul 30 08:13:55 PM PDT 24 |
4105225690 ps |
| T1180 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.705642536 |
|
|
Jul 30 07:52:43 PM PDT 24 |
Jul 30 08:32:21 PM PDT 24 |
10639088556 ps |
| T245 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3525533103 |
|
|
Jul 30 07:59:40 PM PDT 24 |
Jul 30 09:34:08 PM PDT 24 |
47835027356 ps |
| T1181 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.864602499 |
|
|
Jul 30 08:22:35 PM PDT 24 |
Jul 30 08:33:11 PM PDT 24 |
4425642308 ps |
| T1182 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3090231174 |
|
|
Jul 30 07:53:09 PM PDT 24 |
Jul 30 08:32:48 PM PDT 24 |
25409951955 ps |
| T1183 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.73076627 |
|
|
Jul 30 07:50:54 PM PDT 24 |
Jul 30 10:47:37 PM PDT 24 |
58521922992 ps |
| T1184 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.1212319406 |
|
|
Jul 30 07:56:19 PM PDT 24 |
Jul 30 11:19:56 PM PDT 24 |
65148700492 ps |
| T1185 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3430653617 |
|
|
Jul 30 08:00:28 PM PDT 24 |
Jul 30 08:55:56 PM PDT 24 |
11706520952 ps |
| T1186 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.188812034 |
|
|
Jul 30 07:58:47 PM PDT 24 |
Jul 30 08:08:42 PM PDT 24 |
6498916884 ps |
| T1187 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.400618881 |
|
|
Jul 30 08:01:22 PM PDT 24 |
Jul 30 09:15:40 PM PDT 24 |
14924330052 ps |
| T1188 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3759847679 |
|
|
Jul 30 08:20:42 PM PDT 24 |
Jul 30 09:19:36 PM PDT 24 |
14856216744 ps |
| T1189 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3695321094 |
|
|
Jul 30 07:59:04 PM PDT 24 |
Jul 30 08:51:22 PM PDT 24 |
14812792288 ps |
| T329 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.1176434830 |
|
|
Jul 30 08:13:26 PM PDT 24 |
Jul 30 08:32:23 PM PDT 24 |
6034597178 ps |
| T1190 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3066884322 |
|
|
Jul 30 08:20:56 PM PDT 24 |
Jul 30 08:41:14 PM PDT 24 |
10934697697 ps |
| T246 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3923321314 |
|
|
Jul 30 08:11:03 PM PDT 24 |
Jul 30 09:35:25 PM PDT 24 |
50109197000 ps |
| T1191 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2492702378 |
|
|
Jul 30 08:09:44 PM PDT 24 |
Jul 30 08:30:44 PM PDT 24 |
8657864244 ps |
| T198 |
/workspace/coverage/default/2.chip_sw_power_virus.2569230192 |
|
|
Jul 30 08:24:08 PM PDT 24 |
Jul 30 08:48:46 PM PDT 24 |
5980702616 ps |
| T773 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3647217410 |
|
|
Jul 30 08:26:42 PM PDT 24 |
Jul 30 08:34:28 PM PDT 24 |
3872121560 ps |
| T1192 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2430718548 |
|
|
Jul 30 07:54:10 PM PDT 24 |
Jul 30 07:58:00 PM PDT 24 |
3026058212 ps |
| T269 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1590411262 |
|
|
Jul 30 08:10:49 PM PDT 24 |
Jul 30 08:22:39 PM PDT 24 |
6803769612 ps |
| T1193 |
/workspace/coverage/default/0.chip_sw_hmac_enc.4233218802 |
|
|
Jul 30 07:51:05 PM PDT 24 |
Jul 30 07:54:52 PM PDT 24 |
2999951390 ps |
| T199 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.707821104 |
|
|
Jul 30 08:00:47 PM PDT 24 |
Jul 30 08:09:18 PM PDT 24 |
4367444557 ps |
| T1194 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.3703690460 |
|
|
Jul 30 07:55:49 PM PDT 24 |
Jul 30 08:00:14 PM PDT 24 |
3157693400 ps |
| T853 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3215727559 |
|
|
Jul 30 08:29:01 PM PDT 24 |
Jul 30 08:35:52 PM PDT 24 |
3854755452 ps |
| T363 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.249778718 |
|
|
Jul 30 08:22:46 PM PDT 24 |
Jul 30 08:54:05 PM PDT 24 |
8371159968 ps |
| T379 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.1323174540 |
|
|
Jul 30 08:26:26 PM PDT 24 |
Jul 30 08:39:49 PM PDT 24 |
5535289110 ps |
| T1195 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1926810437 |
|
|
Jul 30 07:58:05 PM PDT 24 |
Jul 30 08:57:51 PM PDT 24 |
14302376310 ps |
| T1196 |
/workspace/coverage/default/0.chip_sw_kmac_idle.2009288462 |
|
|
Jul 30 07:54:38 PM PDT 24 |
Jul 30 07:58:21 PM PDT 24 |
2881479968 ps |
| T310 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1835503700 |
|
|
Jul 30 07:52:03 PM PDT 24 |
Jul 30 07:56:44 PM PDT 24 |
3096232034 ps |
| T47 |
/workspace/coverage/default/2.chip_sw_alert_test.272024518 |
|
|
Jul 30 08:12:49 PM PDT 24 |
Jul 30 08:17:46 PM PDT 24 |
3242397896 ps |
| T83 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.3411307158 |
|
|
Jul 30 08:28:36 PM PDT 24 |
Jul 30 08:39:34 PM PDT 24 |
4589335976 ps |
| T842 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1752671910 |
|
|
Jul 30 08:30:48 PM PDT 24 |
Jul 30 08:44:03 PM PDT 24 |
5158058720 ps |
| T1197 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3482328914 |
|
|
Jul 30 07:55:57 PM PDT 24 |
Jul 30 08:03:26 PM PDT 24 |
3830944616 ps |
| T49 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.1680014293 |
|
|
Jul 30 08:07:46 PM PDT 24 |
Jul 30 08:13:05 PM PDT 24 |
3661388430 ps |
| T1198 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.516957575 |
|
|
Jul 30 07:52:25 PM PDT 24 |
Jul 30 08:12:54 PM PDT 24 |
8423305570 ps |
| T1199 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.1481531022 |
|
|
Jul 30 08:09:45 PM PDT 24 |
Jul 30 08:15:11 PM PDT 24 |
3050945400 ps |
| T320 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.585652925 |
|
|
Jul 30 08:14:42 PM PDT 24 |
Jul 30 08:22:03 PM PDT 24 |
4458718424 ps |
| T832 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.3239965416 |
|
|
Jul 30 08:29:13 PM PDT 24 |
Jul 30 08:40:43 PM PDT 24 |
4963000622 ps |
| T1200 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.2682489221 |
|
|
Jul 30 08:02:12 PM PDT 24 |
Jul 30 08:43:51 PM PDT 24 |
9500268296 ps |
| T1201 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1521899761 |
|
|
Jul 30 08:17:53 PM PDT 24 |
Jul 30 08:22:24 PM PDT 24 |
2779304580 ps |
| T762 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.3449851400 |
|
|
Jul 30 07:54:55 PM PDT 24 |
Jul 30 08:28:45 PM PDT 24 |
11614845930 ps |
| T1202 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1691918328 |
|
|
Jul 30 08:30:02 PM PDT 24 |
Jul 30 08:38:19 PM PDT 24 |
5769352218 ps |
| T1203 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.2977034284 |
|
|
Jul 30 07:58:11 PM PDT 24 |
Jul 30 07:59:54 PM PDT 24 |
2393645540 ps |
| T66 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.180117451 |
|
|
Jul 30 08:15:26 PM PDT 24 |
Jul 30 08:24:36 PM PDT 24 |
5878151994 ps |
| T1204 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.1281240224 |
|
|
Jul 30 08:00:44 PM PDT 24 |
Jul 30 09:18:27 PM PDT 24 |
14793246674 ps |
| T1205 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.2090951924 |
|
|
Jul 30 07:52:18 PM PDT 24 |
Jul 30 07:57:38 PM PDT 24 |
3367158340 ps |
| T1206 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1194314423 |
|
|
Jul 30 08:14:45 PM PDT 24 |
Jul 30 08:21:23 PM PDT 24 |
3015945612 ps |
| T1207 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.2131359894 |
|
|
Jul 30 07:55:48 PM PDT 24 |
Jul 30 08:01:36 PM PDT 24 |
2870819936 ps |
| T1208 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2279642091 |
|
|
Jul 30 08:21:25 PM PDT 24 |
Jul 30 08:33:14 PM PDT 24 |
5593761050 ps |
| T1209 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1304480755 |
|
|
Jul 30 08:13:45 PM PDT 24 |
Jul 30 08:51:13 PM PDT 24 |
8892793804 ps |
| T1210 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.607074320 |
|
|
Jul 30 08:14:43 PM PDT 24 |
Jul 30 08:20:48 PM PDT 24 |
3178587968 ps |
| T127 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1668216514 |
|
|
Jul 30 08:17:34 PM PDT 24 |
Jul 30 08:24:24 PM PDT 24 |
5425094532 ps |
| T1211 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3362069337 |
|
|
Jul 30 08:00:31 PM PDT 24 |
Jul 30 09:15:34 PM PDT 24 |
15036349864 ps |
| T1212 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.575095206 |
|
|
Jul 30 08:05:15 PM PDT 24 |
Jul 30 08:13:18 PM PDT 24 |
4628187850 ps |
| T1213 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.4022313664 |
|
|
Jul 30 07:58:14 PM PDT 24 |
Jul 30 08:07:52 PM PDT 24 |
4746292712 ps |
| T68 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.350037313 |
|
|
Jul 30 07:53:57 PM PDT 24 |
Jul 30 09:59:11 PM PDT 24 |
31710682024 ps |
| T1214 |
/workspace/coverage/default/1.rom_raw_unlock.3111242778 |
|
|
Jul 30 08:06:56 PM PDT 24 |
Jul 30 08:11:07 PM PDT 24 |
5742228058 ps |
| T1215 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2951073979 |
|
|
Jul 30 07:51:16 PM PDT 24 |
Jul 30 08:00:07 PM PDT 24 |
8184903694 ps |