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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.33 90.80 80.59 90.24 92.12 97.35 84.87


Total test records in report: 1026
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T243 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3592956555 Aug 04 07:27:29 PM PDT 24 Aug 04 07:34:47 PM PDT 24 3871897432 ps
T160 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3372009157 Aug 04 07:14:46 PM PDT 24 Aug 04 07:54:58 PM PDT 24 16492202680 ps
T565 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3985979931 Aug 04 07:21:11 PM PDT 24 Aug 04 07:31:55 PM PDT 24 4922851482 ps
T383 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1975638190 Aug 04 07:14:22 PM PDT 24 Aug 04 07:24:19 PM PDT 24 4262286664 ps
T566 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1856228996 Aug 04 07:17:32 PM PDT 24 Aug 04 07:27:51 PM PDT 24 5975776700 ps
T285 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1932399494 Aug 04 07:24:57 PM PDT 24 Aug 04 08:27:31 PM PDT 24 14520080332 ps
T336 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.663837157 Aug 04 07:13:20 PM PDT 24 Aug 04 07:37:16 PM PDT 24 8992913480 ps
T567 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2210583568 Aug 04 07:29:26 PM PDT 24 Aug 04 07:43:00 PM PDT 24 6136323742 ps
T249 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.180527832 Aug 04 07:16:00 PM PDT 24 Aug 04 08:44:29 PM PDT 24 45882211346 ps
T568 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2154161163 Aug 04 07:45:30 PM PDT 24 Aug 04 08:03:24 PM PDT 24 7470687746 ps
T190 /workspace/coverage/default/0.chip_plic_all_irqs_20.3302073435 Aug 04 07:16:06 PM PDT 24 Aug 04 07:26:29 PM PDT 24 4531688904 ps
T72 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.1565112823 Aug 04 07:43:15 PM PDT 24 Aug 04 08:11:17 PM PDT 24 6668202644 ps
T66 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3213308099 Aug 04 07:17:24 PM PDT 24 Aug 04 07:40:20 PM PDT 24 6770324519 ps
T436 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3177743210 Aug 04 07:57:48 PM PDT 24 Aug 04 08:03:36 PM PDT 24 3668518468 ps
T244 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.569102042 Aug 04 07:14:56 PM PDT 24 Aug 04 07:18:59 PM PDT 24 2462904773 ps
T438 /workspace/coverage/default/41.chip_sw_all_escalation_resets.672755410 Aug 04 07:55:47 PM PDT 24 Aug 04 08:03:57 PM PDT 24 6106595640 ps
T569 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.732241682 Aug 04 07:54:07 PM PDT 24 Aug 04 08:03:24 PM PDT 24 4437601524 ps
T456 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3426723777 Aug 04 07:56:17 PM PDT 24 Aug 04 08:03:05 PM PDT 24 3644018936 ps
T570 /workspace/coverage/default/2.chip_sw_kmac_smoketest.2615245125 Aug 04 07:48:51 PM PDT 24 Aug 04 07:56:07 PM PDT 24 3550679486 ps
T571 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3014952386 Aug 04 07:41:27 PM PDT 24 Aug 04 07:51:02 PM PDT 24 4759897214 ps
T572 /workspace/coverage/default/0.chip_sw_flash_crash_alert.3380229484 Aug 04 07:16:36 PM PDT 24 Aug 04 07:28:35 PM PDT 24 5574619200 ps
T223 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1449872155 Aug 04 07:45:55 PM PDT 24 Aug 04 07:50:53 PM PDT 24 2479858630 ps
T217 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.586527333 Aug 04 07:13:32 PM PDT 24 Aug 04 07:16:00 PM PDT 24 3614145051 ps
T340 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2457576546 Aug 04 07:43:06 PM PDT 24 Aug 04 08:08:18 PM PDT 24 9717650060 ps
T474 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.4220203339 Aug 04 07:59:33 PM PDT 24 Aug 04 08:06:14 PM PDT 24 3535068416 ps
T573 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.948687368 Aug 04 07:16:14 PM PDT 24 Aug 04 07:22:10 PM PDT 24 3208966832 ps
T145 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3474491393 Aug 04 07:15:54 PM PDT 24 Aug 04 07:21:23 PM PDT 24 4898097096 ps
T439 /workspace/coverage/default/84.chip_sw_all_escalation_resets.456520590 Aug 04 08:01:07 PM PDT 24 Aug 04 08:11:28 PM PDT 24 4931139592 ps
T105 /workspace/coverage/default/1.chip_sw_alert_test.1618890253 Aug 04 07:27:55 PM PDT 24 Aug 04 07:32:46 PM PDT 24 3177372346 ps
T574 /workspace/coverage/default/2.chip_tap_straps_dev.2599070698 Aug 04 07:45:00 PM PDT 24 Aug 04 07:47:36 PM PDT 24 1971459405 ps
T575 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2898687726 Aug 04 07:25:35 PM PDT 24 Aug 04 07:38:08 PM PDT 24 4261367448 ps
T576 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1183347174 Aug 04 07:34:17 PM PDT 24 Aug 04 07:37:59 PM PDT 24 3136426776 ps
T277 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1417839310 Aug 04 07:38:43 PM PDT 24 Aug 04 07:47:05 PM PDT 24 5585481216 ps
T94 /workspace/coverage/default/2.chip_sw_power_idle_load.2304230971 Aug 04 07:46:07 PM PDT 24 Aug 04 07:56:17 PM PDT 24 4258929080 ps
T406 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2611641500 Aug 04 07:15:56 PM PDT 24 Aug 04 07:38:32 PM PDT 24 7413291792 ps
T169 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3208949564 Aug 04 07:30:59 PM PDT 24 Aug 04 07:41:30 PM PDT 24 4580959508 ps
T493 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.829383373 Aug 04 08:01:22 PM PDT 24 Aug 04 08:07:18 PM PDT 24 3291380750 ps
T577 /workspace/coverage/default/0.rom_keymgr_functest.2449385504 Aug 04 07:19:47 PM PDT 24 Aug 04 07:29:09 PM PDT 24 4208541704 ps
T481 /workspace/coverage/default/93.chip_sw_all_escalation_resets.4113621345 Aug 04 08:02:06 PM PDT 24 Aug 04 08:10:49 PM PDT 24 5127582800 ps
T495 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1765219331 Aug 04 07:57:04 PM PDT 24 Aug 04 08:03:58 PM PDT 24 3163379778 ps
T578 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1378674749 Aug 04 07:13:57 PM PDT 24 Aug 04 08:04:19 PM PDT 24 28895188597 ps
T428 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3279012577 Aug 04 07:16:51 PM PDT 24 Aug 04 07:27:10 PM PDT 24 6632169240 ps
T579 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3619580839 Aug 04 07:52:12 PM PDT 24 Aug 04 08:04:00 PM PDT 24 4647782880 ps
T580 /workspace/coverage/default/0.chip_sw_aes_smoketest.2394746523 Aug 04 07:19:11 PM PDT 24 Aug 04 07:23:31 PM PDT 24 2694586108 ps
T183 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2914466658 Aug 04 07:33:00 PM PDT 24 Aug 04 07:39:57 PM PDT 24 6643907160 ps
T488 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.678902814 Aug 04 07:57:30 PM PDT 24 Aug 04 08:04:58 PM PDT 24 3875760822 ps
T581 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.576274859 Aug 04 07:56:03 PM PDT 24 Aug 04 08:01:15 PM PDT 24 3947235824 ps
T582 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3165856 Aug 04 07:22:10 PM PDT 24 Aug 04 08:29:51 PM PDT 24 14815540252 ps
T412 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.899990032 Aug 04 07:21:39 PM PDT 24 Aug 04 07:30:12 PM PDT 24 6436481704 ps
T342 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1092538219 Aug 04 07:30:35 PM PDT 24 Aug 04 08:05:56 PM PDT 24 10715736903 ps
T583 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1584920738 Aug 04 07:16:27 PM PDT 24 Aug 04 07:36:58 PM PDT 24 9228716916 ps
T180 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1391133207 Aug 04 07:49:45 PM PDT 24 Aug 04 07:52:56 PM PDT 24 2650697028 ps
T584 /workspace/coverage/default/0.rom_e2e_self_hash.3498047101 Aug 04 07:23:37 PM PDT 24 Aug 04 08:57:11 PM PDT 24 27003116002 ps
T585 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.839226213 Aug 04 07:53:47 PM PDT 24 Aug 04 08:14:28 PM PDT 24 8543218872 ps
T586 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2735946230 Aug 04 07:13:23 PM PDT 24 Aug 04 07:22:59 PM PDT 24 4308976620 ps
T587 /workspace/coverage/default/1.chip_sw_uart_smoketest.1654770875 Aug 04 07:35:32 PM PDT 24 Aug 04 07:39:52 PM PDT 24 2545049316 ps
T588 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3446889482 Aug 04 07:16:54 PM PDT 24 Aug 04 07:21:48 PM PDT 24 2859739104 ps
T181 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1656592668 Aug 04 07:15:38 PM PDT 24 Aug 04 07:28:10 PM PDT 24 9222186275 ps
T589 /workspace/coverage/default/2.chip_sw_uart_smoketest.1177346954 Aug 04 07:48:04 PM PDT 24 Aug 04 07:53:55 PM PDT 24 2945151778 ps
T127 /workspace/coverage/default/53.chip_sw_all_escalation_resets.1803543626 Aug 04 07:57:49 PM PDT 24 Aug 04 08:06:20 PM PDT 24 4228043308 ps
T590 /workspace/coverage/default/1.chip_sw_aes_masking_off.1697353593 Aug 04 07:32:06 PM PDT 24 Aug 04 07:37:02 PM PDT 24 3082875362 ps
T591 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1663731687 Aug 04 07:27:09 PM PDT 24 Aug 04 07:37:38 PM PDT 24 5513241076 ps
T89 /workspace/coverage/default/3.chip_tap_straps_testunlock0.984793063 Aug 04 07:48:46 PM PDT 24 Aug 04 08:04:06 PM PDT 24 8443351547 ps
T12 /workspace/coverage/default/2.chip_sw_power_virus.2500475594 Aug 04 07:52:02 PM PDT 24 Aug 04 08:15:53 PM PDT 24 5708379480 ps
T231 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3571609735 Aug 04 07:36:27 PM PDT 24 Aug 04 07:51:00 PM PDT 24 5150607032 ps
T592 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2989406856 Aug 04 07:32:55 PM PDT 24 Aug 04 07:38:33 PM PDT 24 3309739728 ps
T73 /workspace/coverage/default/2.chip_sw_edn_kat.668429677 Aug 04 07:42:06 PM PDT 24 Aug 04 07:51:47 PM PDT 24 2933006806 ps
T593 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1583348488 Aug 04 07:22:06 PM PDT 24 Aug 04 07:25:57 PM PDT 24 2205254260 ps
T516 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.480698699 Aug 04 07:57:43 PM PDT 24 Aug 04 08:02:57 PM PDT 24 3070985350 ps
T224 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1536060355 Aug 04 07:29:00 PM PDT 24 Aug 04 07:35:33 PM PDT 24 3644063398 ps
T341 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2060847507 Aug 04 07:16:49 PM PDT 24 Aug 04 08:10:45 PM PDT 24 10148029600 ps
T182 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3871513119 Aug 04 07:30:44 PM PDT 24 Aug 04 07:46:29 PM PDT 24 8837928072 ps
T219 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.4243484222 Aug 04 07:44:29 PM PDT 24 Aug 04 07:52:46 PM PDT 24 3569621065 ps
T43 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.3314306223 Aug 04 07:14:00 PM PDT 24 Aug 04 07:27:16 PM PDT 24 8670344590 ps
T594 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1399667359 Aug 04 07:15:45 PM PDT 24 Aug 04 07:37:00 PM PDT 24 8453933004 ps
T595 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3703956275 Aug 04 07:32:17 PM PDT 24 Aug 04 07:52:11 PM PDT 24 10583687448 ps
T596 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.738897805 Aug 04 07:42:29 PM PDT 24 Aug 04 07:47:03 PM PDT 24 2517802296 ps
T59 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.321626446 Aug 04 07:45:02 PM PDT 24 Aug 04 07:48:02 PM PDT 24 2475898477 ps
T225 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.671125541 Aug 04 07:42:08 PM PDT 24 Aug 04 07:47:54 PM PDT 24 5015025282 ps
T597 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1821624042 Aug 04 07:42:04 PM PDT 24 Aug 04 08:25:11 PM PDT 24 12838202224 ps
T598 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3478767156 Aug 04 07:50:01 PM PDT 24 Aug 04 09:22:12 PM PDT 24 27367705080 ps
T599 /workspace/coverage/default/1.chip_sw_edn_kat.523015363 Aug 04 07:28:59 PM PDT 24 Aug 04 07:39:47 PM PDT 24 3877077828 ps
T151 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1208031269 Aug 04 07:16:16 PM PDT 24 Aug 04 07:22:29 PM PDT 24 3778055060 ps
T152 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.3196354772 Aug 04 07:21:15 PM PDT 24 Aug 04 07:55:15 PM PDT 24 24921392974 ps
T600 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2745428683 Aug 04 07:14:48 PM PDT 24 Aug 04 07:32:18 PM PDT 24 6038850381 ps
T229 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2596229988 Aug 04 07:39:52 PM PDT 24 Aug 04 07:43:05 PM PDT 24 2490376950 ps
T601 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1370754161 Aug 04 07:23:51 PM PDT 24 Aug 04 08:21:35 PM PDT 24 14602125076 ps
T602 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1011536021 Aug 04 07:45:12 PM PDT 24 Aug 04 07:55:47 PM PDT 24 4697041868 ps
T603 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2791403481 Aug 04 07:17:08 PM PDT 24 Aug 04 07:20:49 PM PDT 24 2298819810 ps
T604 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1816436624 Aug 04 07:14:58 PM PDT 24 Aug 04 07:27:50 PM PDT 24 6005864210 ps
T170 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.864982249 Aug 04 07:31:43 PM PDT 24 Aug 04 07:40:10 PM PDT 24 5095008632 ps
T25 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.490695264 Aug 04 07:13:17 PM PDT 24 Aug 04 07:17:01 PM PDT 24 3376778280 ps
T605 /workspace/coverage/default/1.chip_sw_example_rom.3016723368 Aug 04 07:19:48 PM PDT 24 Aug 04 07:21:27 PM PDT 24 3099166104 ps
T521 /workspace/coverage/default/9.chip_sw_all_escalation_resets.2332578768 Aug 04 07:52:44 PM PDT 24 Aug 04 08:04:35 PM PDT 24 5447537704 ps
T606 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3775647595 Aug 04 07:23:01 PM PDT 24 Aug 04 07:31:59 PM PDT 24 4441969990 ps
T607 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.785606387 Aug 04 07:44:23 PM PDT 24 Aug 04 07:53:20 PM PDT 24 4776004936 ps
T453 /workspace/coverage/default/85.chip_sw_all_escalation_resets.1542991893 Aug 04 08:00:45 PM PDT 24 Aug 04 08:10:18 PM PDT 24 6250781368 ps
T608 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.10584707 Aug 04 07:38:24 PM PDT 24 Aug 04 07:46:55 PM PDT 24 5247997042 ps
T609 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.801919729 Aug 04 07:30:54 PM PDT 24 Aug 04 07:36:23 PM PDT 24 3840383593 ps
T610 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3358492175 Aug 04 07:26:53 PM PDT 24 Aug 04 08:34:28 PM PDT 24 38891111751 ps
T611 /workspace/coverage/default/1.chip_sw_aes_entropy.2976777239 Aug 04 07:29:15 PM PDT 24 Aug 04 07:32:29 PM PDT 24 2778383032 ps
T612 /workspace/coverage/default/1.chip_sw_kmac_idle.272459317 Aug 04 07:30:08 PM PDT 24 Aug 04 07:33:44 PM PDT 24 2880307440 ps
T465 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3591242781 Aug 04 07:52:19 PM PDT 24 Aug 04 07:58:40 PM PDT 24 3373702874 ps
T613 /workspace/coverage/default/1.chip_sw_example_flash.3143934608 Aug 04 07:20:51 PM PDT 24 Aug 04 07:24:45 PM PDT 24 3398633800 ps
T200 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3574532173 Aug 04 07:24:43 PM PDT 24 Aug 04 07:28:05 PM PDT 24 2567045241 ps
T614 /workspace/coverage/default/0.chip_sw_example_concurrency.2945421566 Aug 04 07:15:17 PM PDT 24 Aug 04 07:18:42 PM PDT 24 3112239064 ps
T615 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1040785726 Aug 04 07:46:44 PM PDT 24 Aug 04 08:13:49 PM PDT 24 9031992674 ps
T422 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1491799515 Aug 04 07:13:56 PM PDT 24 Aug 04 07:15:47 PM PDT 24 2648959687 ps
T616 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3140362016 Aug 04 07:55:57 PM PDT 24 Aug 04 08:02:51 PM PDT 24 4527572692 ps
T423 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2298563616 Aug 04 07:25:57 PM PDT 24 Aug 04 07:27:44 PM PDT 24 2518317689 ps
T155 /workspace/coverage/default/0.chip_sw_kmac_app_rom.1200771673 Aug 04 07:17:07 PM PDT 24 Aug 04 07:20:09 PM PDT 24 2582150856 ps
T313 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3178819603 Aug 04 07:18:19 PM PDT 24 Aug 04 07:22:29 PM PDT 24 3465405110 ps
T429 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1772947701 Aug 04 07:31:16 PM PDT 24 Aug 04 07:37:27 PM PDT 24 6456029936 ps
T617 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1206443715 Aug 04 07:52:28 PM PDT 24 Aug 04 08:08:31 PM PDT 24 12395235632 ps
T618 /workspace/coverage/default/2.chip_sw_kmac_entropy.2642079617 Aug 04 07:36:49 PM PDT 24 Aug 04 07:41:36 PM PDT 24 3565726524 ps
T41 /workspace/coverage/default/2.chip_sw_spi_device_tpm.260411813 Aug 04 07:37:09 PM PDT 24 Aug 04 07:45:54 PM PDT 24 4208654819 ps
T619 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3723263192 Aug 04 07:13:42 PM PDT 24 Aug 04 07:29:22 PM PDT 24 7600733522 ps
T620 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.869962236 Aug 04 07:54:20 PM PDT 24 Aug 04 08:24:41 PM PDT 24 8101094780 ps
T621 /workspace/coverage/default/1.chip_sw_all_escalation_resets.2553149636 Aug 04 07:22:01 PM PDT 24 Aug 04 07:33:24 PM PDT 24 4789720328 ps
T414 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.326518642 Aug 04 07:15:48 PM PDT 24 Aug 04 07:23:16 PM PDT 24 7664801600 ps
T489 /workspace/coverage/default/10.chip_sw_all_escalation_resets.1083244226 Aug 04 07:52:19 PM PDT 24 Aug 04 08:04:18 PM PDT 24 5639457356 ps
T477 /workspace/coverage/default/68.chip_sw_all_escalation_resets.2285007467 Aug 04 07:58:32 PM PDT 24 Aug 04 08:06:14 PM PDT 24 5811077120 ps
T622 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3044576714 Aug 04 07:15:28 PM PDT 24 Aug 04 07:57:37 PM PDT 24 26937299968 ps
T623 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4200480608 Aug 04 07:16:09 PM PDT 24 Aug 04 07:25:03 PM PDT 24 3782989142 ps
T218 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1563153525 Aug 04 07:42:07 PM PDT 24 Aug 04 07:44:06 PM PDT 24 3178830095 ps
T624 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2665282106 Aug 04 07:17:03 PM PDT 24 Aug 04 07:23:17 PM PDT 24 5105230828 ps
T625 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.386033127 Aug 04 07:53:39 PM PDT 24 Aug 04 08:00:50 PM PDT 24 3633230518 ps
T626 /workspace/coverage/default/0.chip_sw_hmac_oneshot.1994988690 Aug 04 07:15:27 PM PDT 24 Aug 04 07:20:36 PM PDT 24 3020521256 ps
T627 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.9027434 Aug 04 07:26:09 PM PDT 24 Aug 04 07:40:13 PM PDT 24 6965934140 ps
T517 /workspace/coverage/default/12.chip_sw_all_escalation_resets.4184940324 Aug 04 07:51:48 PM PDT 24 Aug 04 08:03:53 PM PDT 24 4974946648 ps
T628 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1486636621 Aug 04 07:26:28 PM PDT 24 Aug 04 08:51:28 PM PDT 24 15264532184 ps
T193 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2266869373 Aug 04 07:14:05 PM PDT 24 Aug 04 07:29:53 PM PDT 24 11375918056 ps
T629 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.747589178 Aug 04 07:36:05 PM PDT 24 Aug 04 07:40:24 PM PDT 24 2301667361 ps
T128 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.612345530 Aug 04 07:54:31 PM PDT 24 Aug 04 08:01:20 PM PDT 24 3829473860 ps
T147 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.612660760 Aug 04 07:35:28 PM PDT 24 Aug 04 07:43:27 PM PDT 24 5683515376 ps
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T631 /workspace/coverage/default/2.chip_sival_flash_info_access.1481918581 Aug 04 07:36:47 PM PDT 24 Aug 04 07:42:40 PM PDT 24 3637861656 ps
T632 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2790082635 Aug 04 07:37:31 PM PDT 24 Aug 04 08:49:31 PM PDT 24 15701245586 ps
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T635 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2972463701 Aug 04 07:42:00 PM PDT 24 Aug 04 08:07:34 PM PDT 24 8409642968 ps
T518 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.4169432015 Aug 04 07:51:45 PM PDT 24 Aug 04 07:58:08 PM PDT 24 4214459030 ps
T501 /workspace/coverage/default/18.chip_sw_all_escalation_resets.2665085078 Aug 04 07:53:12 PM PDT 24 Aug 04 08:03:54 PM PDT 24 4876221424 ps
T636 /workspace/coverage/default/3.chip_tap_straps_dev.1945363566 Aug 04 07:50:02 PM PDT 24 Aug 04 08:05:09 PM PDT 24 7984890107 ps
T206 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1412142745 Aug 04 07:15:04 PM PDT 24 Aug 04 07:25:34 PM PDT 24 5470514210 ps
T637 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2518649065 Aug 04 07:14:12 PM PDT 24 Aug 04 07:18:14 PM PDT 24 2826454000 ps
T413 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2409099057 Aug 04 07:19:16 PM PDT 24 Aug 04 07:24:17 PM PDT 24 2383589932 ps
T638 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1357052311 Aug 04 07:42:17 PM PDT 24 Aug 04 10:46:28 PM PDT 24 256412116848 ps
T522 /workspace/coverage/default/8.chip_sw_all_escalation_resets.1006309508 Aug 04 07:51:26 PM PDT 24 Aug 04 08:01:31 PM PDT 24 5821813958 ps
T639 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1758356320 Aug 04 07:46:38 PM PDT 24 Aug 04 07:51:45 PM PDT 24 2554337668 ps
T640 /workspace/coverage/default/0.chip_sw_example_manufacturer.618449524 Aug 04 07:15:54 PM PDT 24 Aug 04 07:19:28 PM PDT 24 2971915802 ps
T641 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1862436643 Aug 04 07:15:32 PM PDT 24 Aug 04 07:24:20 PM PDT 24 4545408832 ps
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T245 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1785330817 Aug 04 07:40:12 PM PDT 24 Aug 04 08:04:38 PM PDT 24 23966276316 ps
T343 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.625133936 Aug 04 07:31:23 PM PDT 24 Aug 04 08:10:50 PM PDT 24 12119721200 ps
T454 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2257177447 Aug 04 07:41:44 PM PDT 24 Aug 04 07:47:57 PM PDT 24 3206049664 ps
T156 /workspace/coverage/default/1.chip_sw_kmac_app_rom.1252610790 Aug 04 07:30:42 PM PDT 24 Aug 04 07:33:55 PM PDT 24 2879332402 ps
T643 /workspace/coverage/default/2.chip_sw_aes_masking_off.479100770 Aug 04 07:41:00 PM PDT 24 Aug 04 07:46:43 PM PDT 24 2744579439 ps
T116 /workspace/coverage/default/3.chip_tap_straps_rma.2094256716 Aug 04 07:48:48 PM PDT 24 Aug 04 07:53:59 PM PDT 24 3858356592 ps
T215 /workspace/coverage/default/1.chip_sw_flash_init.1397396488 Aug 04 07:26:26 PM PDT 24 Aug 04 08:08:36 PM PDT 24 23242829960 ps
T270 /workspace/coverage/default/0.chip_sw_power_sleep_load.1589897727 Aug 04 07:16:16 PM PDT 24 Aug 04 07:21:30 PM PDT 24 3826262232 ps
T366 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2015027153 Aug 04 07:29:59 PM PDT 24 Aug 04 07:44:16 PM PDT 24 5171132336 ps
T644 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2163459219 Aug 04 07:30:50 PM PDT 24 Aug 04 08:41:48 PM PDT 24 17156477544 ps
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T646 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2164948690 Aug 04 07:17:05 PM PDT 24 Aug 04 07:58:06 PM PDT 24 9214372248 ps
T647 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1561508783 Aug 04 07:13:59 PM PDT 24 Aug 04 07:25:36 PM PDT 24 9207305564 ps
T648 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2769330564 Aug 04 07:41:07 PM PDT 24 Aug 04 08:10:47 PM PDT 24 8901656840 ps
T649 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.33632586 Aug 04 07:37:57 PM PDT 24 Aug 04 07:56:09 PM PDT 24 5685987500 ps
T464 /workspace/coverage/default/86.chip_sw_all_escalation_resets.4192310673 Aug 04 08:01:24 PM PDT 24 Aug 04 08:10:45 PM PDT 24 4239202730 ps
T220 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2283572063 Aug 04 07:15:08 PM PDT 24 Aug 04 07:24:17 PM PDT 24 4065988984 ps
T650 /workspace/coverage/default/1.chip_sw_uart_tx_rx.1949811335 Aug 04 07:21:47 PM PDT 24 Aug 04 07:32:03 PM PDT 24 4280416744 ps
T651 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2521421647 Aug 04 07:22:48 PM PDT 24 Aug 04 08:19:10 PM PDT 24 14409619571 ps
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T652 /workspace/coverage/default/0.rom_e2e_asm_init_prod.1178286746 Aug 04 07:25:55 PM PDT 24 Aug 04 08:31:21 PM PDT 24 15834022366 ps
T296 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3812774291 Aug 04 07:16:14 PM PDT 24 Aug 04 07:27:38 PM PDT 24 4698961595 ps
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T404 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.598974442 Aug 04 07:32:46 PM PDT 24 Aug 04 07:36:10 PM PDT 24 2098540576 ps
T653 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.402277321 Aug 04 07:30:45 PM PDT 24 Aug 04 07:40:05 PM PDT 24 6729153050 ps
T197 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3319743565 Aug 04 07:36:02 PM PDT 24 Aug 04 10:22:56 PM PDT 24 58103307004 ps
T252 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3587252444 Aug 04 07:25:02 PM PDT 24 Aug 04 07:32:02 PM PDT 24 3997045198 ps
T450 /workspace/coverage/default/37.chip_sw_all_escalation_resets.3539955759 Aug 04 07:57:14 PM PDT 24 Aug 04 08:09:04 PM PDT 24 5521470900 ps
T654 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.559505109 Aug 04 07:20:10 PM PDT 24 Aug 04 07:25:52 PM PDT 24 3173702704 ps
T655 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1504630977 Aug 04 07:18:18 PM PDT 24 Aug 04 07:28:28 PM PDT 24 4244016188 ps
T656 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.28471530 Aug 04 07:25:25 PM PDT 24 Aug 04 11:14:26 PM PDT 24 78430620950 ps
T657 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.580652246 Aug 04 07:26:31 PM PDT 24 Aug 04 08:05:33 PM PDT 24 29934747790 ps
T658 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1518547117 Aug 04 07:40:24 PM PDT 24 Aug 04 07:44:44 PM PDT 24 3015763153 ps
T263 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1809071736 Aug 04 07:57:42 PM PDT 24 Aug 04 08:02:45 PM PDT 24 3902150868 ps
T487 /workspace/coverage/default/50.chip_sw_all_escalation_resets.1719210284 Aug 04 07:56:17 PM PDT 24 Aug 04 08:05:22 PM PDT 24 5718701464 ps
T122 /workspace/coverage/default/0.chip_sw_usbdev_pullup.2383400639 Aug 04 07:15:04 PM PDT 24 Aug 04 07:19:54 PM PDT 24 3024142672 ps
T490 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2912368270 Aug 04 08:01:11 PM PDT 24 Aug 04 08:05:49 PM PDT 24 3093812968 ps
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T660 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.4120539751 Aug 04 07:27:10 PM PDT 24 Aug 04 08:30:58 PM PDT 24 20686182546 ps
T661 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.975036879 Aug 04 07:17:03 PM PDT 24 Aug 04 07:33:58 PM PDT 24 5750691860 ps
T662 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.130730981 Aug 04 07:16:13 PM PDT 24 Aug 04 07:24:46 PM PDT 24 4942273736 ps
T79 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3682576021 Aug 04 07:17:53 PM PDT 24 Aug 04 07:25:18 PM PDT 24 4722808872 ps
T264 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2021709058 Aug 04 07:51:37 PM PDT 24 Aug 04 07:59:47 PM PDT 24 3726467986 ps
T398 /workspace/coverage/default/60.chip_sw_all_escalation_resets.3187238240 Aug 04 07:58:38 PM PDT 24 Aug 04 08:07:45 PM PDT 24 4815582600 ps
T663 /workspace/coverage/default/1.chip_sw_aes_smoketest.2843401397 Aug 04 07:33:58 PM PDT 24 Aug 04 07:39:27 PM PDT 24 3373374422 ps
T664 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.473291115 Aug 04 07:17:39 PM PDT 24 Aug 04 07:32:10 PM PDT 24 7149400843 ps
T665 /workspace/coverage/default/2.chip_sw_example_rom.3354952366 Aug 04 07:36:11 PM PDT 24 Aug 04 07:38:34 PM PDT 24 2394789304 ps
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T666 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1819418647 Aug 04 07:44:59 PM PDT 24 Aug 04 07:55:27 PM PDT 24 6553514774 ps
T513 /workspace/coverage/default/38.chip_sw_all_escalation_resets.3826039707 Aug 04 07:55:11 PM PDT 24 Aug 04 08:04:25 PM PDT 24 4663999420 ps
T491 /workspace/coverage/default/45.chip_sw_all_escalation_resets.4088812315 Aug 04 07:57:02 PM PDT 24 Aug 04 08:05:41 PM PDT 24 4734300750 ps
T667 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3766629717 Aug 04 07:14:27 PM PDT 24 Aug 04 07:22:02 PM PDT 24 7355817832 ps
T246 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.295916258 Aug 04 07:15:25 PM PDT 24 Aug 04 07:42:55 PM PDT 24 24163807882 ps
T668 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2262393804 Aug 04 07:45:00 PM PDT 24 Aug 04 07:56:32 PM PDT 24 4715903276 ps
T332 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2918934659 Aug 04 07:28:06 PM PDT 24 Aug 04 07:39:23 PM PDT 24 19378822552 ps
T482 /workspace/coverage/default/64.chip_sw_all_escalation_resets.3541497534 Aug 04 07:59:10 PM PDT 24 Aug 04 08:11:17 PM PDT 24 5376874528 ps
T297 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1489033198 Aug 04 07:30:51 PM PDT 24 Aug 04 07:40:17 PM PDT 24 4258530003 ps
T42 /workspace/coverage/default/1.chip_sw_spi_device_tpm.3218666447 Aug 04 07:23:17 PM PDT 24 Aug 04 07:29:15 PM PDT 24 3460346271 ps
T373 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3301215152 Aug 04 07:28:42 PM PDT 24 Aug 04 07:54:58 PM PDT 24 11517524340 ps
T669 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2000719360 Aug 04 07:29:59 PM PDT 24 Aug 04 07:41:03 PM PDT 24 8422319935 ps
T670 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3575479073 Aug 04 07:18:30 PM PDT 24 Aug 04 07:25:26 PM PDT 24 3810651352 ps
T380 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2920711643 Aug 04 07:31:23 PM PDT 24 Aug 04 07:39:15 PM PDT 24 4669296432 ps
T671 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3056735370 Aug 04 07:50:59 PM PDT 24 Aug 04 07:58:42 PM PDT 24 4412623064 ps
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T350 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3753293791 Aug 04 08:00:36 PM PDT 24 Aug 04 08:06:48 PM PDT 24 3711235500 ps
T354 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.4196140425 Aug 04 07:58:35 PM PDT 24 Aug 04 08:05:16 PM PDT 24 3299073816 ps
T355 /workspace/coverage/default/0.rom_e2e_asm_init_dev.3006929654 Aug 04 07:23:14 PM PDT 24 Aug 04 08:33:43 PM PDT 24 15306353864 ps
T356 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2374322662 Aug 04 07:21:48 PM PDT 24 Aug 04 08:54:32 PM PDT 24 22915912320 ps
T357 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2422575415 Aug 04 07:51:37 PM PDT 24 Aug 04 07:57:40 PM PDT 24 4056388200 ps
T358 /workspace/coverage/default/1.rom_e2e_self_hash.1136267790 Aug 04 07:37:47 PM PDT 24 Aug 04 09:08:27 PM PDT 24 25661593336 ps
T359 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1611693046 Aug 04 08:00:06 PM PDT 24 Aug 04 08:09:09 PM PDT 24 4233953464 ps
T360 /workspace/coverage/default/1.chip_sw_kmac_entropy.356029834 Aug 04 07:25:21 PM PDT 24 Aug 04 07:29:31 PM PDT 24 1954700220 ps
T331 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2706974669 Aug 04 07:20:39 PM PDT 24 Aug 04 07:59:01 PM PDT 24 24634593438 ps
T361 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3777190395 Aug 04 07:13:28 PM PDT 24 Aug 04 07:15:27 PM PDT 24 2127057147 ps
T673 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3823240907 Aug 04 07:15:06 PM PDT 24 Aug 04 07:24:29 PM PDT 24 4861066890 ps
T367 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.203845627 Aug 04 07:15:44 PM PDT 24 Aug 04 07:30:44 PM PDT 24 4776195880 ps
T102 /workspace/coverage/default/1.chip_plic_all_irqs_10.3138350441 Aug 04 07:31:13 PM PDT 24 Aug 04 07:42:36 PM PDT 24 4735118408 ps
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T70 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.3024979196 Aug 04 07:13:54 PM PDT 24 Aug 04 07:23:33 PM PDT 24 4253176120 ps
T675 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1407528743 Aug 04 07:14:18 PM PDT 24 Aug 04 11:13:53 PM PDT 24 77578788480 ps
T468 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3889632380 Aug 04 07:51:06 PM PDT 24 Aug 04 07:56:17 PM PDT 24 3663935838 ps
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T184 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3995343993 Aug 04 07:16:49 PM PDT 24 Aug 04 07:24:27 PM PDT 24 5202837944 ps
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T677 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1929505391 Aug 04 07:44:10 PM PDT 24 Aug 04 07:55:52 PM PDT 24 4188545308 ps
T485 /workspace/coverage/default/55.chip_sw_all_escalation_resets.1195355372 Aug 04 07:57:53 PM PDT 24 Aug 04 08:06:14 PM PDT 24 4905899880 ps
T479 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.350476429 Aug 04 07:54:56 PM PDT 24 Aug 04 08:02:05 PM PDT 24 3676339564 ps
T678 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1174353375 Aug 04 07:48:02 PM PDT 24 Aug 04 08:06:16 PM PDT 24 13206333142 ps
T679 /workspace/coverage/default/0.chip_sw_otbn_smoketest.1390887848 Aug 04 07:20:01 PM PDT 24 Aug 04 08:00:23 PM PDT 24 10072266432 ps
T680 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1654839483 Aug 04 07:15:17 PM PDT 24 Aug 04 07:21:10 PM PDT 24 3082878400 ps
T396 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3518443403 Aug 04 07:46:26 PM PDT 24 Aug 04 07:50:08 PM PDT 24 2831912342 ps
T374 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.909000329 Aug 04 07:29:04 PM PDT 24 Aug 04 07:47:33 PM PDT 24 5761750276 ps
T681 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2575754145 Aug 04 07:14:54 PM PDT 24 Aug 04 07:30:52 PM PDT 24 5685951184 ps
T682 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1015390064 Aug 04 07:14:28 PM PDT 24 Aug 04 07:35:13 PM PDT 24 8745371536 ps
T683 /workspace/coverage/default/1.chip_sw_edn_sw_mode.3129498120 Aug 04 07:28:47 PM PDT 24 Aug 04 07:57:52 PM PDT 24 8172907138 ps
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