| T844 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.51345593 |
|
|
Aug 04 07:33:48 PM PDT 24 |
Aug 04 07:43:39 PM PDT 24 |
3751152140 ps |
| T178 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.3369353042 |
|
|
Aug 04 07:20:49 PM PDT 24 |
Aug 04 08:02:33 PM PDT 24 |
10246040521 ps |
| T421 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.183494057 |
|
|
Aug 04 07:34:42 PM PDT 24 |
Aug 04 07:42:26 PM PDT 24 |
4158675387 ps |
| T281 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.2337669764 |
|
|
Aug 04 08:00:24 PM PDT 24 |
Aug 04 08:10:00 PM PDT 24 |
5165810664 ps |
| T845 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2250436222 |
|
|
Aug 04 07:42:52 PM PDT 24 |
Aug 04 08:36:52 PM PDT 24 |
20933931138 ps |
| T846 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2645477750 |
|
|
Aug 04 07:13:30 PM PDT 24 |
Aug 04 07:22:37 PM PDT 24 |
3758025241 ps |
| T847 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3666760597 |
|
|
Aug 04 07:31:18 PM PDT 24 |
Aug 04 07:45:20 PM PDT 24 |
7998016054 ps |
| T77 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.649275564 |
|
|
Aug 04 07:33:07 PM PDT 24 |
Aug 04 08:36:44 PM PDT 24 |
25006103276 ps |
| T455 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.1807421206 |
|
|
Aug 04 07:57:39 PM PDT 24 |
Aug 04 08:04:04 PM PDT 24 |
4791086894 ps |
| T309 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.1185304587 |
|
|
Aug 04 07:53:16 PM PDT 24 |
Aug 04 08:04:01 PM PDT 24 |
5454709692 ps |
| T344 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3367981704 |
|
|
Aug 04 07:29:28 PM PDT 24 |
Aug 04 08:34:11 PM PDT 24 |
15603834920 ps |
| T376 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.333387045 |
|
|
Aug 04 07:36:19 PM PDT 24 |
Aug 04 07:48:19 PM PDT 24 |
4998958640 ps |
| T848 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1763639173 |
|
|
Aug 04 07:26:34 PM PDT 24 |
Aug 04 07:30:47 PM PDT 24 |
2955208947 ps |
| T478 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.23351550 |
|
|
Aug 04 07:57:54 PM PDT 24 |
Aug 04 08:09:03 PM PDT 24 |
5139951544 ps |
| T849 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.859081881 |
|
|
Aug 04 07:34:14 PM PDT 24 |
Aug 04 07:37:46 PM PDT 24 |
2663234136 ps |
| T850 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.4070628821 |
|
|
Aug 04 07:35:56 PM PDT 24 |
Aug 04 07:50:31 PM PDT 24 |
6382749784 ps |
| T282 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2345179013 |
|
|
Aug 04 08:00:02 PM PDT 24 |
Aug 04 08:09:48 PM PDT 24 |
5183825100 ps |
| T851 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.677563867 |
|
|
Aug 04 07:29:24 PM PDT 24 |
Aug 04 08:04:52 PM PDT 24 |
9265511150 ps |
| T852 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1940311587 |
|
|
Aug 04 07:37:41 PM PDT 24 |
Aug 04 09:09:48 PM PDT 24 |
46555980642 ps |
| T853 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3048306803 |
|
|
Aug 04 07:26:14 PM PDT 24 |
Aug 04 07:33:16 PM PDT 24 |
5637101304 ps |
| T854 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1653370538 |
|
|
Aug 04 07:48:00 PM PDT 24 |
Aug 04 08:06:28 PM PDT 24 |
5531059804 ps |
| T385 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.2980116838 |
|
|
Aug 04 07:21:31 PM PDT 24 |
Aug 04 07:25:55 PM PDT 24 |
2693542300 ps |
| T855 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1255225295 |
|
|
Aug 04 07:14:52 PM PDT 24 |
Aug 04 07:23:03 PM PDT 24 |
5121209744 ps |
| T191 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.3057434156 |
|
|
Aug 04 07:30:39 PM PDT 24 |
Aug 04 07:43:21 PM PDT 24 |
4012992654 ps |
| T514 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3154814865 |
|
|
Aug 04 07:59:05 PM PDT 24 |
Aug 04 08:06:45 PM PDT 24 |
3911576062 ps |
| T463 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1282655884 |
|
|
Aug 04 07:53:53 PM PDT 24 |
Aug 04 08:00:06 PM PDT 24 |
3301940698 ps |
| T856 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2097497774 |
|
|
Aug 04 07:14:35 PM PDT 24 |
Aug 04 07:24:52 PM PDT 24 |
19126117702 ps |
| T39 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1584716072 |
|
|
Aug 04 07:39:23 PM PDT 24 |
Aug 04 07:47:58 PM PDT 24 |
6664869056 ps |
| T857 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3281414021 |
|
|
Aug 04 07:24:35 PM PDT 24 |
Aug 04 07:43:44 PM PDT 24 |
5730924904 ps |
| T472 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.609386663 |
|
|
Aug 04 07:55:01 PM PDT 24 |
Aug 04 08:01:51 PM PDT 24 |
3986561620 ps |
| T35 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2388646875 |
|
|
Aug 04 07:14:25 PM PDT 24 |
Aug 04 07:19:36 PM PDT 24 |
2847087606 ps |
| T858 |
/workspace/coverage/default/2.rom_keymgr_functest.2092759693 |
|
|
Aug 04 07:50:15 PM PDT 24 |
Aug 04 07:56:57 PM PDT 24 |
3852728052 ps |
| T426 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.513623651 |
|
|
Aug 04 07:32:31 PM PDT 24 |
Aug 04 08:00:56 PM PDT 24 |
24206237734 ps |
| T859 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2473045362 |
|
|
Aug 04 07:40:21 PM PDT 24 |
Aug 04 08:28:07 PM PDT 24 |
18619709417 ps |
| T860 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1641002274 |
|
|
Aug 04 07:51:08 PM PDT 24 |
Aug 04 08:15:43 PM PDT 24 |
8667350636 ps |
| T28 |
/workspace/coverage/default/1.chip_sw_gpio.1523681266 |
|
|
Aug 04 07:24:39 PM PDT 24 |
Aug 04 07:31:57 PM PDT 24 |
3850443613 ps |
| T861 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1310789080 |
|
|
Aug 04 07:45:20 PM PDT 24 |
Aug 04 07:55:54 PM PDT 24 |
4583956188 ps |
| T862 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.562998982 |
|
|
Aug 04 07:48:11 PM PDT 24 |
Aug 04 08:15:12 PM PDT 24 |
8314029209 ps |
| T315 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1424764573 |
|
|
Aug 04 07:34:43 PM PDT 24 |
Aug 04 07:38:51 PM PDT 24 |
2687122514 ps |
| T863 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.3310028482 |
|
|
Aug 04 07:49:18 PM PDT 24 |
Aug 04 07:54:46 PM PDT 24 |
4161904776 ps |
| T86 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.102381688 |
|
|
Aug 04 07:15:36 PM PDT 24 |
Aug 04 07:33:54 PM PDT 24 |
9450853786 ps |
| T283 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2444654173 |
|
|
Aug 04 07:14:30 PM PDT 24 |
Aug 04 07:23:12 PM PDT 24 |
5853781560 ps |
| T864 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.72372583 |
|
|
Aug 04 07:45:06 PM PDT 24 |
Aug 04 07:49:45 PM PDT 24 |
3117633152 ps |
| T865 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3748370581 |
|
|
Aug 04 07:33:53 PM PDT 24 |
Aug 04 07:40:16 PM PDT 24 |
3376438252 ps |
| T866 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3759362314 |
|
|
Aug 04 08:01:53 PM PDT 24 |
Aug 04 08:11:08 PM PDT 24 |
5434139120 ps |
| T330 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.528166516 |
|
|
Aug 04 07:31:28 PM PDT 24 |
Aug 04 07:40:30 PM PDT 24 |
4892992068 ps |
| T867 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.3100783332 |
|
|
Aug 04 07:17:33 PM PDT 24 |
Aug 04 07:38:21 PM PDT 24 |
6112193632 ps |
| T868 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.969155752 |
|
|
Aug 04 07:34:43 PM PDT 24 |
Aug 04 07:40:24 PM PDT 24 |
3383686248 ps |
| T353 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2075671621 |
|
|
Aug 04 08:00:07 PM PDT 24 |
Aug 04 08:05:48 PM PDT 24 |
3374286834 ps |
| T869 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3725381044 |
|
|
Aug 04 07:13:46 PM PDT 24 |
Aug 04 07:43:16 PM PDT 24 |
7794549640 ps |
| T870 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.4160242310 |
|
|
Aug 04 07:28:11 PM PDT 24 |
Aug 04 07:41:58 PM PDT 24 |
7868449800 ps |
| T173 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3914115471 |
|
|
Aug 04 07:41:49 PM PDT 24 |
Aug 04 07:55:35 PM PDT 24 |
6232231575 ps |
| T871 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2676375730 |
|
|
Aug 04 07:45:39 PM PDT 24 |
Aug 04 07:48:52 PM PDT 24 |
2363560090 ps |
| T872 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3895479759 |
|
|
Aug 04 07:23:00 PM PDT 24 |
Aug 04 08:24:03 PM PDT 24 |
15440248312 ps |
| T873 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1401232190 |
|
|
Aug 04 07:41:43 PM PDT 24 |
Aug 04 07:51:11 PM PDT 24 |
19594446168 ps |
| T461 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3710755714 |
|
|
Aug 04 08:01:27 PM PDT 24 |
Aug 04 08:10:46 PM PDT 24 |
4994527356 ps |
| T874 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4211709300 |
|
|
Aug 04 07:26:39 PM PDT 24 |
Aug 04 07:54:55 PM PDT 24 |
21686150400 ps |
| T875 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.704749284 |
|
|
Aug 04 07:49:59 PM PDT 24 |
Aug 04 07:56:04 PM PDT 24 |
3320261048 ps |
| T876 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.904899742 |
|
|
Aug 04 07:38:36 PM PDT 24 |
Aug 04 07:50:33 PM PDT 24 |
10172792340 ps |
| T434 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1335109125 |
|
|
Aug 04 07:58:51 PM PDT 24 |
Aug 04 08:07:38 PM PDT 24 |
3882467268 ps |
| T877 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2164651954 |
|
|
Aug 04 07:13:54 PM PDT 24 |
Aug 04 07:25:55 PM PDT 24 |
5725754260 ps |
| T878 |
/workspace/coverage/default/2.chip_sw_flash_init.1293135305 |
|
|
Aug 04 07:36:25 PM PDT 24 |
Aug 04 08:07:33 PM PDT 24 |
18397051028 ps |
| T271 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.1804819706 |
|
|
Aug 04 07:31:04 PM PDT 24 |
Aug 04 07:36:45 PM PDT 24 |
3794418568 ps |
| T496 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.2700741735 |
|
|
Aug 04 07:52:23 PM PDT 24 |
Aug 04 08:03:07 PM PDT 24 |
5891291346 ps |
| T879 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.810863187 |
|
|
Aug 04 07:36:52 PM PDT 24 |
Aug 04 08:01:04 PM PDT 24 |
13436035208 ps |
| T451 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.1451895049 |
|
|
Aug 04 07:54:11 PM PDT 24 |
Aug 04 08:02:51 PM PDT 24 |
5604980916 ps |
| T8 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1185865151 |
|
|
Aug 04 07:36:40 PM PDT 24 |
Aug 04 07:40:14 PM PDT 24 |
2284438848 ps |
| T880 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2157537855 |
|
|
Aug 04 07:21:26 PM PDT 24 |
Aug 04 07:25:27 PM PDT 24 |
2621667360 ps |
| T881 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3819080623 |
|
|
Aug 04 07:50:52 PM PDT 24 |
Aug 04 10:03:41 PM PDT 24 |
39046889154 ps |
| T882 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3859941153 |
|
|
Aug 04 07:55:37 PM PDT 24 |
Aug 04 08:01:45 PM PDT 24 |
3879713848 ps |
| T192 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.3393904439 |
|
|
Aug 04 07:44:11 PM PDT 24 |
Aug 04 07:58:32 PM PDT 24 |
4173713560 ps |
| T883 |
/workspace/coverage/default/0.chip_sw_hmac_multistream.1756546039 |
|
|
Aug 04 07:17:03 PM PDT 24 |
Aug 04 07:47:10 PM PDT 24 |
7778782400 ps |
| T328 |
/workspace/coverage/default/0.rom_raw_unlock.2015289278 |
|
|
Aug 04 07:21:47 PM PDT 24 |
Aug 04 07:26:08 PM PDT 24 |
5690490184 ps |
| T884 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.3937164569 |
|
|
Aug 04 07:59:13 PM PDT 24 |
Aug 04 08:11:07 PM PDT 24 |
4450187898 ps |
| T394 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3808672011 |
|
|
Aug 04 07:46:20 PM PDT 24 |
Aug 04 07:58:02 PM PDT 24 |
4773374586 ps |
| T475 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.2773624177 |
|
|
Aug 04 07:49:38 PM PDT 24 |
Aug 04 08:02:24 PM PDT 24 |
6072880540 ps |
| T885 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2458463673 |
|
|
Aug 04 07:50:41 PM PDT 24 |
Aug 04 07:58:03 PM PDT 24 |
5894925100 ps |
| T886 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1505666743 |
|
|
Aug 04 07:50:50 PM PDT 24 |
Aug 04 08:33:36 PM PDT 24 |
12957066232 ps |
| T511 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2455434632 |
|
|
Aug 04 07:54:30 PM PDT 24 |
Aug 04 08:02:56 PM PDT 24 |
4510929688 ps |
| T210 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.851267011 |
|
|
Aug 04 07:46:22 PM PDT 24 |
Aug 04 07:54:48 PM PDT 24 |
3593842500 ps |
| T887 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1855959179 |
|
|
Aug 04 07:20:48 PM PDT 24 |
Aug 04 08:30:06 PM PDT 24 |
15387310810 ps |
| T494 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.4047681832 |
|
|
Aug 04 08:00:00 PM PDT 24 |
Aug 04 08:08:57 PM PDT 24 |
4934226820 ps |
| T888 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1864527997 |
|
|
Aug 04 07:21:47 PM PDT 24 |
Aug 04 08:27:34 PM PDT 24 |
14280350635 ps |
| T319 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2605217800 |
|
|
Aug 04 07:19:43 PM PDT 24 |
Aug 04 07:54:29 PM PDT 24 |
10301729686 ps |
| T889 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3057659152 |
|
|
Aug 04 07:45:47 PM PDT 24 |
Aug 04 07:54:28 PM PDT 24 |
6680886128 ps |
| T890 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3378284913 |
|
|
Aug 04 07:42:47 PM PDT 24 |
Aug 04 08:16:27 PM PDT 24 |
13070150260 ps |
| T891 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2320736868 |
|
|
Aug 04 07:26:41 PM PDT 24 |
Aug 04 09:01:22 PM PDT 24 |
50351242479 ps |
| T892 |
/workspace/coverage/default/1.chip_tap_straps_prod.4039664807 |
|
|
Aug 04 07:32:38 PM PDT 24 |
Aug 04 07:35:05 PM PDT 24 |
2367802314 ps |
| T893 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2571527005 |
|
|
Aug 04 07:21:59 PM PDT 24 |
Aug 04 07:27:05 PM PDT 24 |
2489402880 ps |
| T894 |
/workspace/coverage/default/4.chip_tap_straps_prod.3155900107 |
|
|
Aug 04 07:49:19 PM PDT 24 |
Aug 04 07:51:27 PM PDT 24 |
2549481849 ps |
| T895 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2090901197 |
|
|
Aug 04 07:57:33 PM PDT 24 |
Aug 04 08:03:21 PM PDT 24 |
3812959786 ps |
| T896 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.618630336 |
|
|
Aug 04 07:13:21 PM PDT 24 |
Aug 04 07:17:28 PM PDT 24 |
3747580542 ps |
| T897 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.2703975946 |
|
|
Aug 04 07:49:26 PM PDT 24 |
Aug 04 08:18:41 PM PDT 24 |
9389890548 ps |
| T470 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2734596409 |
|
|
Aug 04 07:58:34 PM PDT 24 |
Aug 04 08:08:34 PM PDT 24 |
4568320964 ps |
| T898 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1957175184 |
|
|
Aug 04 07:16:58 PM PDT 24 |
Aug 04 07:28:42 PM PDT 24 |
3753654046 ps |
| T899 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.3881839279 |
|
|
Aug 04 07:13:13 PM PDT 24 |
Aug 04 10:23:35 PM PDT 24 |
64364823199 ps |
| T900 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.1953798643 |
|
|
Aug 04 07:28:25 PM PDT 24 |
Aug 04 07:57:02 PM PDT 24 |
6444821976 ps |
| T901 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2750461725 |
|
|
Aug 04 07:28:44 PM PDT 24 |
Aug 04 07:33:15 PM PDT 24 |
2881786232 ps |
| T902 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1671799095 |
|
|
Aug 04 07:15:43 PM PDT 24 |
Aug 04 07:22:56 PM PDT 24 |
7528015220 ps |
| T903 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3067362068 |
|
|
Aug 04 07:32:18 PM PDT 24 |
Aug 04 07:43:03 PM PDT 24 |
5472179651 ps |
| T904 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1853796734 |
|
|
Aug 04 08:02:45 PM PDT 24 |
Aug 04 08:12:10 PM PDT 24 |
4794687408 ps |
| T486 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2138717311 |
|
|
Aug 04 07:59:36 PM PDT 24 |
Aug 04 08:04:35 PM PDT 24 |
3667854880 ps |
| T905 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.692874760 |
|
|
Aug 04 07:37:53 PM PDT 24 |
Aug 04 07:45:35 PM PDT 24 |
2923086308 ps |
| T906 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.4166432405 |
|
|
Aug 04 07:37:11 PM PDT 24 |
Aug 04 07:59:26 PM PDT 24 |
7547428700 ps |
| T907 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.1062945557 |
|
|
Aug 04 07:40:20 PM PDT 24 |
Aug 04 07:56:39 PM PDT 24 |
5534406516 ps |
| T908 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2565021532 |
|
|
Aug 04 07:15:20 PM PDT 24 |
Aug 04 07:24:59 PM PDT 24 |
8934228335 ps |
| T909 |
/workspace/coverage/default/2.rom_e2e_static_critical.1767213488 |
|
|
Aug 04 07:53:04 PM PDT 24 |
Aug 04 08:50:18 PM PDT 24 |
17349094484 ps |
| T910 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3534724633 |
|
|
Aug 04 07:37:49 PM PDT 24 |
Aug 04 07:42:08 PM PDT 24 |
2194486184 ps |
| T911 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3067927977 |
|
|
Aug 04 07:22:54 PM PDT 24 |
Aug 04 08:57:07 PM PDT 24 |
23117645075 ps |
| T310 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2779729903 |
|
|
Aug 04 08:00:47 PM PDT 24 |
Aug 04 08:06:30 PM PDT 24 |
2968669916 ps |
| T912 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.3751975513 |
|
|
Aug 04 07:50:27 PM PDT 24 |
Aug 04 08:44:04 PM PDT 24 |
14333330340 ps |
| T913 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.532441092 |
|
|
Aug 04 07:27:41 PM PDT 24 |
Aug 04 07:36:52 PM PDT 24 |
3587530592 ps |
| T914 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.1066666621 |
|
|
Aug 04 07:35:34 PM PDT 24 |
Aug 04 07:46:13 PM PDT 24 |
4562688144 ps |
| T915 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1561561328 |
|
|
Aug 04 07:21:27 PM PDT 24 |
Aug 04 07:28:10 PM PDT 24 |
5149817712 ps |
| T916 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.722386345 |
|
|
Aug 04 07:50:31 PM PDT 24 |
Aug 04 08:00:53 PM PDT 24 |
3940077176 ps |
| T917 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.87815095 |
|
|
Aug 04 07:29:31 PM PDT 24 |
Aug 04 07:58:13 PM PDT 24 |
7412852790 ps |
| T918 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2517625050 |
|
|
Aug 04 07:34:04 PM PDT 24 |
Aug 04 07:39:36 PM PDT 24 |
2927673136 ps |
| T919 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2198218960 |
|
|
Aug 04 07:25:30 PM PDT 24 |
Aug 04 08:33:24 PM PDT 24 |
14659354700 ps |
| T920 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.1891223626 |
|
|
Aug 04 07:18:52 PM PDT 24 |
Aug 04 07:58:50 PM PDT 24 |
10666836139 ps |
| T921 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1890598971 |
|
|
Aug 04 07:16:35 PM PDT 24 |
Aug 04 07:23:01 PM PDT 24 |
3573797320 ps |
| T922 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.3841192605 |
|
|
Aug 04 07:54:16 PM PDT 24 |
Aug 04 08:03:32 PM PDT 24 |
4657211704 ps |
| T427 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3073187806 |
|
|
Aug 04 07:40:26 PM PDT 24 |
Aug 04 07:58:12 PM PDT 24 |
4866974678 ps |
| T923 |
/workspace/coverage/default/0.rom_e2e_static_critical.2975491646 |
|
|
Aug 04 07:24:16 PM PDT 24 |
Aug 04 08:34:27 PM PDT 24 |
16989771050 ps |
| T100 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.656830071 |
|
|
Aug 04 07:37:02 PM PDT 24 |
Aug 04 07:49:29 PM PDT 24 |
4738414236 ps |
| T924 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1931872755 |
|
|
Aug 04 07:19:23 PM PDT 24 |
Aug 04 07:23:10 PM PDT 24 |
2481326274 ps |
| T226 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.950715686 |
|
|
Aug 04 07:15:26 PM PDT 24 |
Aug 04 07:26:21 PM PDT 24 |
4260593106 ps |
| T925 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3981391068 |
|
|
Aug 04 07:50:41 PM PDT 24 |
Aug 04 07:59:52 PM PDT 24 |
6708044733 ps |
| T926 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3515821179 |
|
|
Aug 04 07:14:40 PM PDT 24 |
Aug 04 07:18:20 PM PDT 24 |
2866416692 ps |
| T85 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1188458287 |
|
|
Aug 04 07:49:15 PM PDT 24 |
Aug 04 07:58:42 PM PDT 24 |
4500301482 ps |
| T927 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.15270768 |
|
|
Aug 04 07:22:10 PM PDT 24 |
Aug 04 08:12:37 PM PDT 24 |
10758353680 ps |
| T189 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.1801148548 |
|
|
Aug 04 07:15:45 PM PDT 24 |
Aug 04 07:36:15 PM PDT 24 |
6381472520 ps |
| T928 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.584720898 |
|
|
Aug 04 07:42:57 PM PDT 24 |
Aug 04 07:48:12 PM PDT 24 |
2788600858 ps |
| T929 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2343072546 |
|
|
Aug 04 07:18:10 PM PDT 24 |
Aug 04 07:28:59 PM PDT 24 |
6790318750 ps |
| T502 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.2999199868 |
|
|
Aug 04 07:54:39 PM PDT 24 |
Aug 04 08:04:51 PM PDT 24 |
4965759076 ps |
| T311 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.4062773655 |
|
|
Aug 04 07:54:33 PM PDT 24 |
Aug 04 07:59:59 PM PDT 24 |
4018127228 ps |
| T930 |
/workspace/coverage/default/2.rom_e2e_smoke.2152350164 |
|
|
Aug 04 07:50:56 PM PDT 24 |
Aug 04 08:44:36 PM PDT 24 |
15229884320 ps |
| T931 |
/workspace/coverage/default/2.chip_sw_aes_entropy.2692857025 |
|
|
Aug 04 07:42:00 PM PDT 24 |
Aug 04 07:46:38 PM PDT 24 |
3058974764 ps |
| T932 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.189711200 |
|
|
Aug 04 07:17:20 PM PDT 24 |
Aug 04 07:23:13 PM PDT 24 |
3864551708 ps |
| T375 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.1672116891 |
|
|
Aug 04 07:15:03 PM PDT 24 |
Aug 04 07:34:21 PM PDT 24 |
6495375590 ps |
| T395 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1463077717 |
|
|
Aug 04 07:37:02 PM PDT 24 |
Aug 04 07:48:02 PM PDT 24 |
3557359780 ps |
| T933 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.4108961479 |
|
|
Aug 04 07:29:19 PM PDT 24 |
Aug 04 07:33:38 PM PDT 24 |
2860693882 ps |
| T934 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1537405785 |
|
|
Aug 04 07:13:47 PM PDT 24 |
Aug 04 07:23:32 PM PDT 24 |
4752209706 ps |
| T935 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3711854319 |
|
|
Aug 04 07:19:22 PM PDT 24 |
Aug 04 07:23:54 PM PDT 24 |
3140613672 ps |
| T936 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1153198464 |
|
|
Aug 04 07:25:57 PM PDT 24 |
Aug 04 08:54:24 PM PDT 24 |
44769958433 ps |
| T937 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.133666138 |
|
|
Aug 04 07:56:21 PM PDT 24 |
Aug 04 08:06:56 PM PDT 24 |
6123500300 ps |
| T109 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.720153376 |
|
|
Aug 04 07:22:24 PM PDT 24 |
Aug 04 07:27:14 PM PDT 24 |
4292588992 ps |
| T938 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.1351584462 |
|
|
Aug 04 07:50:03 PM PDT 24 |
Aug 04 07:59:49 PM PDT 24 |
4530151000 ps |
| T208 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2548262886 |
|
|
Aug 04 07:50:20 PM PDT 24 |
Aug 04 08:00:06 PM PDT 24 |
6196828194 ps |
| T939 |
/workspace/coverage/default/0.rom_e2e_smoke.1225211199 |
|
|
Aug 04 07:25:48 PM PDT 24 |
Aug 04 08:51:41 PM PDT 24 |
14729620816 ps |
| T940 |
/workspace/coverage/default/2.chip_sw_aes_idle.514949985 |
|
|
Aug 04 07:40:43 PM PDT 24 |
Aug 04 07:45:38 PM PDT 24 |
2612295576 ps |
| T452 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1618292891 |
|
|
Aug 04 08:01:21 PM PDT 24 |
Aug 04 08:07:58 PM PDT 24 |
3569942400 ps |
| T941 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2861106763 |
|
|
Aug 04 07:28:36 PM PDT 24 |
Aug 04 07:37:41 PM PDT 24 |
4656415944 ps |
| T312 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2733192291 |
|
|
Aug 04 07:59:29 PM PDT 24 |
Aug 04 08:06:38 PM PDT 24 |
3561376168 ps |
| T942 |
/workspace/coverage/default/1.chip_sw_aes_enc.627914162 |
|
|
Aug 04 07:29:32 PM PDT 24 |
Aug 04 07:35:30 PM PDT 24 |
3177819614 ps |
| T473 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3663418730 |
|
|
Aug 04 07:52:35 PM PDT 24 |
Aug 04 08:00:11 PM PDT 24 |
4251905158 ps |
| T943 |
/workspace/coverage/default/0.chip_tap_straps_prod.568117758 |
|
|
Aug 04 07:15:32 PM PDT 24 |
Aug 04 07:35:41 PM PDT 24 |
10980890011 ps |
| T944 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2425508893 |
|
|
Aug 04 07:32:51 PM PDT 24 |
Aug 04 07:39:08 PM PDT 24 |
2857902920 ps |
| T945 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.2510769121 |
|
|
Aug 04 07:38:31 PM PDT 24 |
Aug 04 07:43:12 PM PDT 24 |
2946109170 ps |
| T946 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1909971698 |
|
|
Aug 04 07:44:35 PM PDT 24 |
Aug 04 07:54:23 PM PDT 24 |
4123471764 ps |
| T947 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.4079324938 |
|
|
Aug 04 07:31:54 PM PDT 24 |
Aug 04 07:38:17 PM PDT 24 |
4604362616 ps |
| T505 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3673921362 |
|
|
Aug 04 07:53:54 PM PDT 24 |
Aug 04 07:59:29 PM PDT 24 |
3568713900 ps |
| T948 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.4043617923 |
|
|
Aug 04 07:25:02 PM PDT 24 |
Aug 04 07:36:03 PM PDT 24 |
4141447368 ps |
| T949 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2920354278 |
|
|
Aug 04 07:39:12 PM PDT 24 |
Aug 04 07:41:14 PM PDT 24 |
2836454581 ps |
| T325 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.1828578333 |
|
|
Aug 04 07:45:44 PM PDT 24 |
Aug 04 07:55:04 PM PDT 24 |
10784093070 ps |
| T950 |
/workspace/coverage/default/2.chip_sw_hmac_oneshot.696225761 |
|
|
Aug 04 07:43:47 PM PDT 24 |
Aug 04 07:49:27 PM PDT 24 |
3594953024 ps |
| T951 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.161993558 |
|
|
Aug 04 07:15:11 PM PDT 24 |
Aug 04 07:23:06 PM PDT 24 |
4688515352 ps |
| T952 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2365267633 |
|
|
Aug 04 07:35:07 PM PDT 24 |
Aug 04 07:43:53 PM PDT 24 |
6200142440 ps |
| T953 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2943734254 |
|
|
Aug 04 07:19:14 PM PDT 24 |
Aug 04 07:25:01 PM PDT 24 |
3262271312 ps |
| T954 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.287720536 |
|
|
Aug 04 07:52:07 PM PDT 24 |
Aug 04 08:01:51 PM PDT 24 |
5499709027 ps |
| T955 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.4150751360 |
|
|
Aug 04 07:35:36 PM PDT 24 |
Aug 04 07:44:10 PM PDT 24 |
3597301587 ps |
| T400 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.568577243 |
|
|
Aug 04 07:36:31 PM PDT 24 |
Aug 04 07:45:18 PM PDT 24 |
4771588310 ps |
| T956 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.661505830 |
|
|
Aug 04 07:28:12 PM PDT 24 |
Aug 04 07:37:42 PM PDT 24 |
5338247800 ps |
| T957 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.985568097 |
|
|
Aug 04 07:13:32 PM PDT 24 |
Aug 04 07:23:47 PM PDT 24 |
4604915224 ps |
| T36 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3941619996 |
|
|
Aug 04 07:23:05 PM PDT 24 |
Aug 04 07:27:46 PM PDT 24 |
3158815048 ps |
| T958 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.3327569344 |
|
|
Aug 04 07:13:38 PM PDT 24 |
Aug 04 07:24:55 PM PDT 24 |
4784538984 ps |
| T959 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2653703485 |
|
|
Aug 04 07:40:08 PM PDT 24 |
Aug 04 07:44:35 PM PDT 24 |
3205765724 ps |
| T960 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1876520467 |
|
|
Aug 04 07:51:33 PM PDT 24 |
Aug 04 08:10:06 PM PDT 24 |
11442204526 ps |
| T961 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.37385893 |
|
|
Aug 04 07:32:19 PM PDT 24 |
Aug 04 07:36:38 PM PDT 24 |
3636589664 ps |
| T962 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2365953329 |
|
|
Aug 04 07:51:30 PM PDT 24 |
Aug 04 08:53:23 PM PDT 24 |
15194562030 ps |
| T963 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.741003287 |
|
|
Aug 04 07:22:45 PM PDT 24 |
Aug 04 08:31:12 PM PDT 24 |
14790401264 ps |
| T964 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3688498224 |
|
|
Aug 04 07:19:50 PM PDT 24 |
Aug 04 07:23:50 PM PDT 24 |
2836618560 ps |
| T507 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3414734563 |
|
|
Aug 04 07:57:36 PM PDT 24 |
Aug 04 08:06:30 PM PDT 24 |
4334381040 ps |
| T965 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.789687577 |
|
|
Aug 04 07:33:21 PM PDT 24 |
Aug 04 07:41:49 PM PDT 24 |
4616094784 ps |
| T966 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2683358324 |
|
|
Aug 04 07:38:04 PM PDT 24 |
Aug 04 08:27:38 PM PDT 24 |
11483825288 ps |
| T967 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.2630239347 |
|
|
Aug 04 07:56:31 PM PDT 24 |
Aug 04 08:06:38 PM PDT 24 |
5404493506 ps |
| T968 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.1973555032 |
|
|
Aug 04 07:16:05 PM PDT 24 |
Aug 04 07:20:21 PM PDT 24 |
3303140680 ps |
| T969 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.294739529 |
|
|
Aug 04 07:25:21 PM PDT 24 |
Aug 04 09:13:37 PM PDT 24 |
50961467850 ps |
| T970 |
/workspace/coverage/default/4.chip_tap_straps_dev.3864355743 |
|
|
Aug 04 07:49:44 PM PDT 24 |
Aug 04 08:06:23 PM PDT 24 |
10347485691 ps |
| T520 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3437834054 |
|
|
Aug 04 08:01:09 PM PDT 24 |
Aug 04 08:07:24 PM PDT 24 |
4307401196 ps |
| T971 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.2777555648 |
|
|
Aug 04 07:21:03 PM PDT 24 |
Aug 04 07:34:00 PM PDT 24 |
5790012504 ps |
| T972 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.4065295062 |
|
|
Aug 04 07:27:08 PM PDT 24 |
Aug 04 07:36:15 PM PDT 24 |
4587453130 ps |
| T973 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1966806093 |
|
|
Aug 04 07:57:04 PM PDT 24 |
Aug 04 08:02:49 PM PDT 24 |
3326411296 ps |
| T471 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.2390722901 |
|
|
Aug 04 07:54:02 PM PDT 24 |
Aug 04 08:04:11 PM PDT 24 |
5353419416 ps |
| T492 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2728611738 |
|
|
Aug 04 07:54:38 PM PDT 24 |
Aug 04 08:02:22 PM PDT 24 |
3816362872 ps |
| T974 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.3905269924 |
|
|
Aug 04 07:41:36 PM PDT 24 |
Aug 04 07:45:45 PM PDT 24 |
3368362439 ps |
| T9 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3823349441 |
|
|
Aug 04 07:15:26 PM PDT 24 |
Aug 04 07:20:20 PM PDT 24 |
3060630377 ps |
| T975 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.658873402 |
|
|
Aug 04 07:26:13 PM PDT 24 |
Aug 04 08:31:38 PM PDT 24 |
15069043222 ps |
| T976 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1432744044 |
|
|
Aug 04 07:15:53 PM PDT 24 |
Aug 04 07:25:22 PM PDT 24 |
5727271928 ps |
| T977 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.470054061 |
|
|
Aug 04 07:33:43 PM PDT 24 |
Aug 04 07:42:43 PM PDT 24 |
4520310290 ps |
| T978 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.958395712 |
|
|
Aug 04 07:35:59 PM PDT 24 |
Aug 04 07:40:44 PM PDT 24 |
3207867782 ps |
| T979 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1407863682 |
|
|
Aug 04 07:52:32 PM PDT 24 |
Aug 04 08:34:40 PM PDT 24 |
11620540184 ps |
| T980 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1196772174 |
|
|
Aug 04 07:50:43 PM PDT 24 |
Aug 04 07:58:35 PM PDT 24 |
6227872319 ps |
| T981 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1390333862 |
|
|
Aug 04 07:16:15 PM PDT 24 |
Aug 04 07:26:35 PM PDT 24 |
5006475502 ps |
| T982 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2881528499 |
|
|
Aug 04 07:25:56 PM PDT 24 |
Aug 04 08:23:37 PM PDT 24 |
10523436957 ps |
| T983 |
/workspace/coverage/default/2.chip_sw_hmac_multistream.666885070 |
|
|
Aug 04 07:42:08 PM PDT 24 |
Aug 04 08:12:14 PM PDT 24 |
7643645044 ps |
| T984 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.2766211534 |
|
|
Aug 04 07:32:02 PM PDT 24 |
Aug 04 07:40:19 PM PDT 24 |
6078782872 ps |
| T985 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2810718304 |
|
|
Aug 04 08:01:22 PM PDT 24 |
Aug 04 08:10:06 PM PDT 24 |
5390536300 ps |
| T512 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3798564875 |
|
|
Aug 04 07:59:18 PM PDT 24 |
Aug 04 08:05:37 PM PDT 24 |
3408962200 ps |
| T986 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1222668236 |
|
|
Aug 04 07:29:18 PM PDT 24 |
Aug 04 07:46:52 PM PDT 24 |
6565223776 ps |
| T987 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2513021414 |
|
|
Aug 04 07:15:29 PM PDT 24 |
Aug 04 08:39:17 PM PDT 24 |
21394822040 ps |
| T988 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2956723870 |
|
|
Aug 04 07:22:30 PM PDT 24 |
Aug 04 07:30:29 PM PDT 24 |
4126991294 ps |
| T989 |
/workspace/coverage/default/0.chip_sw_power_idle_load.3275956674 |
|
|
Aug 04 07:17:44 PM PDT 24 |
Aug 04 07:30:39 PM PDT 24 |
4669631050 ps |
| T466 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.879337448 |
|
|
Aug 04 07:53:46 PM PDT 24 |
Aug 04 08:04:11 PM PDT 24 |
5069308060 ps |
| T241 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.4248541081 |
|
|
Aug 04 07:22:28 PM PDT 24 |
Aug 04 07:35:29 PM PDT 24 |
6603370052 ps |
| T990 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1495314936 |
|
|
Aug 04 07:14:29 PM PDT 24 |
Aug 04 07:16:44 PM PDT 24 |
2684070904 ps |
| T483 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.4081454256 |
|
|
Aug 04 07:52:14 PM PDT 24 |
Aug 04 08:05:13 PM PDT 24 |
4645077256 ps |
| T991 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2257595661 |
|
|
Aug 04 07:22:59 PM PDT 24 |
Aug 04 10:31:32 PM PDT 24 |
57269290695 ps |
| T992 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1527367797 |
|
|
Aug 04 07:57:52 PM PDT 24 |
Aug 04 08:07:15 PM PDT 24 |
5564250880 ps |
| T993 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.340617232 |
|
|
Aug 04 07:52:14 PM PDT 24 |
Aug 04 08:11:47 PM PDT 24 |
12796434383 ps |
| T994 |
/workspace/coverage/default/2.chip_sw_aes_enc.4122469708 |
|
|
Aug 04 07:39:43 PM PDT 24 |
Aug 04 07:45:29 PM PDT 24 |
3204432980 ps |
| T995 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.2419711187 |
|
|
Aug 04 07:20:31 PM PDT 24 |
Aug 04 07:24:59 PM PDT 24 |
2533228064 ps |
| T996 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1080868653 |
|
|
Aug 04 07:38:40 PM PDT 24 |
Aug 04 07:40:43 PM PDT 24 |
2676541450 ps |
| T123 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3348405141 |
|
|
Aug 04 07:13:27 PM PDT 24 |
Aug 04 07:20:26 PM PDT 24 |
3951288632 ps |
| T997 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2230044524 |
|
|
Aug 04 07:52:03 PM PDT 24 |
Aug 04 08:43:57 PM PDT 24 |
14792099688 ps |
| T998 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.902885251 |
|
|
Aug 04 07:25:41 PM PDT 24 |
Aug 04 08:30:39 PM PDT 24 |
14597257842 ps |
| T999 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3154297366 |
|
|
Aug 04 07:30:51 PM PDT 24 |
Aug 04 07:45:19 PM PDT 24 |
4871505496 ps |
| T1000 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1972674667 |
|
|
Aug 04 07:28:34 PM PDT 24 |
Aug 04 11:10:10 PM PDT 24 |
256307198512 ps |
| T1001 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3010396476 |
|
|
Aug 04 07:35:57 PM PDT 24 |
Aug 04 07:40:13 PM PDT 24 |
2894725420 ps |
| T1002 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.1467280509 |
|
|
Aug 04 07:15:51 PM PDT 24 |
Aug 04 07:21:09 PM PDT 24 |
2967491684 ps |
| T409 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.823630964 |
|
|
Aug 04 07:32:02 PM PDT 24 |
Aug 04 07:42:18 PM PDT 24 |
3291264978 ps |
| T1003 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.802775295 |
|
|
Aug 04 07:50:23 PM PDT 24 |
Aug 04 08:01:26 PM PDT 24 |
4785683500 ps |
| T382 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.770211619 |
|
|
Aug 04 07:23:47 PM PDT 24 |
Aug 04 07:33:54 PM PDT 24 |
4217514220 ps |
| T1004 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.630894176 |
|
|
Aug 04 07:18:19 PM PDT 24 |
Aug 04 07:23:22 PM PDT 24 |
2685893064 ps |
| T1005 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.2862923182 |
|
|
Aug 04 07:56:42 PM PDT 24 |
Aug 04 08:09:08 PM PDT 24 |
4641806448 ps |
| T1006 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1557136772 |
|
|
Aug 04 07:14:13 PM PDT 24 |
Aug 04 07:31:03 PM PDT 24 |
5541984040 ps |
| T106 |
/workspace/coverage/default/0.chip_sw_alert_test.3376797128 |
|
|
Aug 04 07:14:19 PM PDT 24 |
Aug 04 07:19:40 PM PDT 24 |
3301686100 ps |
| T1007 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.1968637747 |
|
|
Aug 04 07:21:20 PM PDT 24 |
Aug 04 07:26:15 PM PDT 24 |
3701140852 ps |
| T1008 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1647608701 |
|
|
Aug 04 07:43:18 PM PDT 24 |
Aug 04 07:58:14 PM PDT 24 |
9194992360 ps |
| T87 |
/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.1837438340 |
|
|
Aug 04 07:19:51 PM PDT 24 |
Aug 04 08:27:00 PM PDT 24 |
24082200903 ps |
| T101 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1905132895 |
|
|
Aug 04 07:23:28 PM PDT 24 |
Aug 04 07:34:21 PM PDT 24 |
4913842360 ps |
| T1009 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.745815295 |
|
|
Aug 04 07:38:48 PM PDT 24 |
Aug 04 07:51:47 PM PDT 24 |
7620882455 ps |
| T1010 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1725505103 |
|
|
Aug 04 07:17:40 PM PDT 24 |
Aug 04 07:22:29 PM PDT 24 |
2781780496 ps |
| T1011 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2908235782 |
|
|
Aug 04 07:18:38 PM PDT 24 |
Aug 04 07:28:52 PM PDT 24 |
6000281200 ps |
| T345 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.4145716964 |
|
|
Aug 04 07:42:33 PM PDT 24 |
Aug 04 08:43:48 PM PDT 24 |
15270647336 ps |
| T1012 |
/workspace/coverage/default/1.chip_sw_hmac_oneshot.353385250 |
|
|
Aug 04 07:29:55 PM PDT 24 |
Aug 04 07:34:13 PM PDT 24 |
2924721320 ps |
| T1013 |
/workspace/coverage/default/1.rom_keymgr_functest.1291320760 |
|
|
Aug 04 07:35:17 PM PDT 24 |
Aug 04 07:45:52 PM PDT 24 |
4551203752 ps |
| T1014 |
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3332316368 |
|
|
Aug 04 07:51:11 PM PDT 24 |
Aug 04 09:09:25 PM PDT 24 |
21166683032 ps |
| T1015 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1963870221 |
|
|
Aug 04 07:24:31 PM PDT 24 |
Aug 04 09:04:29 PM PDT 24 |
23826981368 ps |
| T503 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.4068376323 |
|
|
Aug 04 07:50:58 PM PDT 24 |
Aug 04 08:05:19 PM PDT 24 |
6534468158 ps |
| T1016 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.38992360 |
|
|
Aug 04 07:26:40 PM PDT 24 |
Aug 04 07:35:29 PM PDT 24 |
7342705050 ps |