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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.33 90.80 80.59 90.24 92.12 97.35 84.87


Total test records in report: 1026
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T26 /workspace/coverage/default/2.chip_sw_gpio.512990613 Aug 04 07:37:56 PM PDT 24 Aug 04 07:45:30 PM PDT 24 3900108280 ps
T430 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1191492389 Aug 04 07:57:31 PM PDT 24 Aug 04 08:03:26 PM PDT 24 3837377254 ps
T684 /workspace/coverage/default/2.chip_sw_hmac_smoketest.2875581643 Aug 04 07:47:40 PM PDT 24 Aug 04 07:53:56 PM PDT 24 3311122512 ps
T685 /workspace/coverage/default/47.chip_sw_all_escalation_resets.3233564774 Aug 04 07:57:05 PM PDT 24 Aug 04 08:06:53 PM PDT 24 4847756364 ps
T44 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2571193348 Aug 04 07:14:42 PM PDT 24 Aug 04 07:23:54 PM PDT 24 3809528651 ps
T686 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2669932256 Aug 04 07:49:51 PM PDT 24 Aug 04 09:05:00 PM PDT 24 21215683000 ps
T687 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1438840356 Aug 04 07:16:22 PM PDT 24 Aug 04 07:26:28 PM PDT 24 5717132855 ps
T688 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3139643667 Aug 04 07:40:10 PM PDT 24 Aug 04 07:50:20 PM PDT 24 6772495493 ps
T689 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.503786469 Aug 04 07:14:14 PM PDT 24 Aug 04 07:40:13 PM PDT 24 8324588924 ps
T690 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.261485187 Aug 04 07:42:10 PM PDT 24 Aug 04 08:16:56 PM PDT 24 8981815280 ps
T424 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3743982517 Aug 04 07:25:31 PM PDT 24 Aug 04 07:28:32 PM PDT 24 3313845669 ps
T691 /workspace/coverage/default/2.chip_sw_aes_smoketest.3556568220 Aug 04 07:48:08 PM PDT 24 Aug 04 07:53:20 PM PDT 24 3459512504 ps
T692 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4044583170 Aug 04 07:39:17 PM PDT 24 Aug 04 07:53:25 PM PDT 24 3612429776 ps
T693 /workspace/coverage/default/1.chip_sw_hmac_enc.2411863887 Aug 04 07:28:43 PM PDT 24 Aug 04 07:32:01 PM PDT 24 2609216608 ps
T694 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.652945663 Aug 04 07:29:00 PM PDT 24 Aug 04 07:33:43 PM PDT 24 3181682496 ps
T510 /workspace/coverage/default/91.chip_sw_all_escalation_resets.188974983 Aug 04 08:01:21 PM PDT 24 Aug 04 08:09:04 PM PDT 24 6321903640 ps
T695 /workspace/coverage/default/2.chip_sw_kmac_app_rom.3473695956 Aug 04 07:43:10 PM PDT 24 Aug 04 07:47:28 PM PDT 24 2383460048 ps
T696 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.237379368 Aug 04 07:47:24 PM PDT 24 Aug 04 07:52:16 PM PDT 24 5330956012 ps
T697 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2211881165 Aug 04 07:37:09 PM PDT 24 Aug 04 08:39:55 PM PDT 24 14856905856 ps
T698 /workspace/coverage/default/0.chip_sw_example_rom.105582978 Aug 04 07:13:45 PM PDT 24 Aug 04 07:16:20 PM PDT 24 1847756300 ps
T699 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1464137233 Aug 04 07:43:49 PM PDT 24 Aug 04 08:16:02 PM PDT 24 20630196878 ps
T700 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3815280630 Aug 04 07:42:11 PM PDT 24 Aug 04 08:02:41 PM PDT 24 8220457856 ps
T372 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2049474400 Aug 04 07:13:24 PM PDT 24 Aug 04 07:20:13 PM PDT 24 5021950013 ps
T188 /workspace/coverage/default/2.chip_plic_all_irqs_0.2195111523 Aug 04 07:43:31 PM PDT 24 Aug 04 08:03:23 PM PDT 24 6131289128 ps
T276 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2436759616 Aug 04 07:31:00 PM PDT 24 Aug 04 07:52:31 PM PDT 24 11208949900 ps
T506 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.180052113 Aug 04 07:57:21 PM PDT 24 Aug 04 08:04:49 PM PDT 24 4184687034 ps
T701 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.474359357 Aug 04 07:25:47 PM PDT 24 Aug 04 07:51:33 PM PDT 24 7365087638 ps
T702 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2530396413 Aug 04 07:44:30 PM PDT 24 Aug 04 07:54:36 PM PDT 24 4968734824 ps
T703 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2047472182 Aug 04 07:51:13 PM PDT 24 Aug 04 08:00:16 PM PDT 24 4815134430 ps
T415 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1595289157 Aug 04 07:18:15 PM PDT 24 Aug 04 07:48:56 PM PDT 24 22533982464 ps
T704 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.4261261810 Aug 04 07:24:49 PM PDT 24 Aug 04 07:46:24 PM PDT 24 6174290200 ps
T705 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2566156460 Aug 04 07:39:03 PM PDT 24 Aug 04 08:01:41 PM PDT 24 15699437149 ps
T480 /workspace/coverage/default/27.chip_sw_all_escalation_resets.2181355588 Aug 04 07:54:13 PM PDT 24 Aug 04 08:04:36 PM PDT 24 5023179790 ps
T706 /workspace/coverage/default/1.chip_sw_kmac_smoketest.692722259 Aug 04 07:35:14 PM PDT 24 Aug 04 07:41:50 PM PDT 24 3480931502 ps
T82 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.568762059 Aug 04 07:49:36 PM PDT 24 Aug 04 08:05:28 PM PDT 24 7585073990 ps
T707 /workspace/coverage/default/1.rom_e2e_asm_init_prod.3876372749 Aug 04 07:38:15 PM PDT 24 Aug 04 08:37:29 PM PDT 24 16158735232 ps
T519 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1692737982 Aug 04 07:57:01 PM PDT 24 Aug 04 08:02:53 PM PDT 24 3844120616 ps
T278 /workspace/coverage/default/29.chip_sw_all_escalation_resets.3467393172 Aug 04 07:54:18 PM PDT 24 Aug 04 08:03:47 PM PDT 24 5202336560 ps
T351 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1576391600 Aug 04 07:52:49 PM PDT 24 Aug 04 07:57:56 PM PDT 24 3073954520 ps
T708 /workspace/coverage/default/0.chip_sw_coremark.581329381 Aug 04 07:16:09 PM PDT 24 Aug 04 11:07:29 PM PDT 24 71394283592 ps
T709 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.801979239 Aug 04 07:18:54 PM PDT 24 Aug 04 07:24:46 PM PDT 24 3184585000 ps
T710 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1854374683 Aug 04 07:26:13 PM PDT 24 Aug 04 07:54:10 PM PDT 24 10396475891 ps
T314 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1003370184 Aug 04 07:17:04 PM PDT 24 Aug 04 07:22:12 PM PDT 24 3222088250 ps
T711 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1329780433 Aug 04 07:39:55 PM PDT 24 Aug 04 07:49:52 PM PDT 24 3413476960 ps
T712 /workspace/coverage/default/1.chip_sw_example_concurrency.2102568338 Aug 04 07:22:36 PM PDT 24 Aug 04 07:26:47 PM PDT 24 2662402108 ps
T713 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2035801775 Aug 04 07:13:53 PM PDT 24 Aug 04 07:18:27 PM PDT 24 3042502400 ps
T714 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1198270399 Aug 04 07:23:15 PM PDT 24 Aug 04 08:31:53 PM PDT 24 15107589762 ps
T715 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2450300762 Aug 04 07:15:13 PM PDT 24 Aug 04 08:03:12 PM PDT 24 36646478180 ps
T251 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.985541274 Aug 04 07:46:44 PM PDT 24 Aug 04 08:23:23 PM PDT 24 22034927663 ps
T716 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1233679559 Aug 04 07:41:31 PM PDT 24 Aug 04 07:44:51 PM PDT 24 2662098950 ps
T267 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.895290812 Aug 04 07:23:09 PM PDT 24 Aug 04 08:47:14 PM PDT 24 17937600468 ps
T469 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1114287797 Aug 04 07:57:31 PM PDT 24 Aug 04 08:04:04 PM PDT 24 3764608820 ps
T298 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4286567686 Aug 04 07:46:51 PM PDT 24 Aug 04 07:57:10 PM PDT 24 4148359307 ps
T377 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1842629358 Aug 04 07:22:59 PM PDT 24 Aug 04 07:33:53 PM PDT 24 4138273770 ps
T717 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3619432302 Aug 04 07:41:30 PM PDT 24 Aug 04 07:44:40 PM PDT 24 2880330642 ps
T718 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1008513315 Aug 04 07:37:58 PM PDT 24 Aug 04 08:40:28 PM PDT 24 14802236488 ps
T719 /workspace/coverage/default/0.chip_sw_csrng_kat_test.3448821981 Aug 04 07:16:06 PM PDT 24 Aug 04 07:19:30 PM PDT 24 2450845896 ps
T720 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1184792997 Aug 04 07:15:11 PM PDT 24 Aug 04 07:27:01 PM PDT 24 7770495108 ps
T379 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1474777470 Aug 04 07:37:45 PM PDT 24 Aug 04 07:48:05 PM PDT 24 4157072852 ps
T7 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.900818954 Aug 04 07:20:46 PM PDT 24 Aug 04 07:24:04 PM PDT 24 3012363348 ps
T721 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.80718740 Aug 04 07:39:26 PM PDT 24 Aug 04 08:22:05 PM PDT 24 26538900852 ps
T722 /workspace/coverage/default/2.chip_sw_all_escalation_resets.3094010802 Aug 04 07:35:49 PM PDT 24 Aug 04 07:44:51 PM PDT 24 4446979288 ps
T279 /workspace/coverage/default/26.chip_sw_all_escalation_resets.238416414 Aug 04 07:54:36 PM PDT 24 Aug 04 08:05:38 PM PDT 24 5939682082 ps
T723 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1097932045 Aug 04 07:26:11 PM PDT 24 Aug 04 07:30:43 PM PDT 24 2772957664 ps
T724 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1812927884 Aug 04 07:14:22 PM PDT 24 Aug 04 08:37:20 PM PDT 24 43825874135 ps
T725 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3784735873 Aug 04 07:15:45 PM PDT 24 Aug 04 07:31:00 PM PDT 24 8205986852 ps
T318 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3605277882 Aug 04 07:43:22 PM PDT 24 Aug 04 07:53:48 PM PDT 24 7442609828 ps
T378 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3099270613 Aug 04 07:23:55 PM PDT 24 Aug 04 07:33:14 PM PDT 24 4691334412 ps
T726 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2799389986 Aug 04 07:21:52 PM PDT 24 Aug 04 07:39:33 PM PDT 24 8458865238 ps
T459 /workspace/coverage/default/13.chip_sw_all_escalation_resets.418181410 Aug 04 07:52:37 PM PDT 24 Aug 04 08:03:31 PM PDT 24 5342871416 ps
T727 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.122366992 Aug 04 07:28:49 PM PDT 24 Aug 04 08:30:52 PM PDT 24 18750697858 ps
T174 /workspace/coverage/default/2.chip_jtag_mem_access.158290930 Aug 04 07:37:57 PM PDT 24 Aug 04 07:59:14 PM PDT 24 13795220888 ps
T728 /workspace/coverage/default/1.chip_sw_aon_timer_irq.2921744801 Aug 04 07:29:16 PM PDT 24 Aug 04 07:36:01 PM PDT 24 3314445752 ps
T185 /workspace/coverage/default/0.chip_sw_edn_boot_mode.3294143354 Aug 04 07:14:38 PM PDT 24 Aug 04 07:24:02 PM PDT 24 3391475854 ps
T729 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.308676209 Aug 04 07:36:38 PM PDT 24 Aug 04 07:50:40 PM PDT 24 5500249652 ps
T103 /workspace/coverage/default/2.chip_plic_all_irqs_10.3098320807 Aug 04 07:43:43 PM PDT 24 Aug 04 07:52:55 PM PDT 24 3245826384 ps
T730 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1914806711 Aug 04 07:15:53 PM PDT 24 Aug 04 07:23:34 PM PDT 24 5278793980 ps
T499 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3611344018 Aug 04 07:53:59 PM PDT 24 Aug 04 08:00:13 PM PDT 24 4220126946 ps
T250 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3267390902 Aug 04 07:25:23 PM PDT 24 Aug 04 08:56:31 PM PDT 24 44874720400 ps
T731 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1106187793 Aug 04 07:38:56 PM PDT 24 Aug 04 08:14:55 PM PDT 24 30442678568 ps
T732 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3485829949 Aug 04 07:25:26 PM PDT 24 Aug 04 07:31:09 PM PDT 24 3946546343 ps
T253 /workspace/coverage/default/0.chip_sw_flash_init.1155879664 Aug 04 07:15:16 PM PDT 24 Aug 04 07:49:38 PM PDT 24 24232010261 ps
T733 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.4183811936 Aug 04 07:13:44 PM PDT 24 Aug 04 07:39:07 PM PDT 24 7905909160 ps
T207 /workspace/coverage/default/79.chip_sw_all_escalation_resets.1581574519 Aug 04 08:00:04 PM PDT 24 Aug 04 08:10:22 PM PDT 24 5890921408 ps
T734 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2135858141 Aug 04 07:42:29 PM PDT 24 Aug 04 07:47:08 PM PDT 24 2575530874 ps
T735 /workspace/coverage/default/2.chip_sw_kmac_idle.2054957035 Aug 04 07:42:35 PM PDT 24 Aug 04 07:46:33 PM PDT 24 2331229656 ps
T736 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1410536706 Aug 04 07:15:50 PM PDT 24 Aug 04 07:47:49 PM PDT 24 8449786184 ps
T737 /workspace/coverage/default/2.chip_sw_edn_auto_mode.4185317216 Aug 04 07:43:34 PM PDT 24 Aug 04 08:15:27 PM PDT 24 6607387500 ps
T738 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.4268204767 Aug 04 07:32:40 PM PDT 24 Aug 04 08:01:56 PM PDT 24 8133996884 ps
T739 /workspace/coverage/default/1.chip_sw_power_idle_load.4117187115 Aug 04 07:33:28 PM PDT 24 Aug 04 07:43:19 PM PDT 24 4154073264 ps
T740 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2615864160 Aug 04 07:36:50 PM PDT 24 Aug 04 07:47:02 PM PDT 24 4106138562 ps
T741 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.2785197933 Aug 04 07:43:57 PM PDT 24 Aug 04 08:10:04 PM PDT 24 13920914924 ps
T504 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2408170113 Aug 04 07:53:10 PM PDT 24 Aug 04 07:59:58 PM PDT 24 3763456488 ps
T742 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3994166098 Aug 04 07:25:50 PM PDT 24 Aug 04 07:42:13 PM PDT 24 10459810340 ps
T743 /workspace/coverage/default/1.rom_e2e_smoke.2969881603 Aug 04 07:38:59 PM PDT 24 Aug 04 08:37:18 PM PDT 24 15417703680 ps
T509 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.565784158 Aug 04 07:49:47 PM PDT 24 Aug 04 07:57:19 PM PDT 24 3647014830 ps
T335 /workspace/coverage/default/0.chip_sw_gpio_smoketest.896731842 Aug 04 07:21:09 PM PDT 24 Aug 04 07:25:25 PM PDT 24 2927020078 ps
T306 /workspace/coverage/default/72.chip_sw_all_escalation_resets.703630756 Aug 04 07:59:24 PM PDT 24 Aug 04 08:07:59 PM PDT 24 5284984084 ps
T744 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3940515904 Aug 04 07:49:06 PM PDT 24 Aug 04 08:07:34 PM PDT 24 7717979634 ps
T484 /workspace/coverage/default/89.chip_sw_all_escalation_resets.544299579 Aug 04 08:00:45 PM PDT 24 Aug 04 08:09:41 PM PDT 24 5904432884 ps
T307 /workspace/coverage/default/59.chip_sw_all_escalation_resets.4097829694 Aug 04 07:57:11 PM PDT 24 Aug 04 08:04:42 PM PDT 24 4472782530 ps
T431 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2784488852 Aug 04 08:00:32 PM PDT 24 Aug 04 08:06:08 PM PDT 24 3288379364 ps
T745 /workspace/coverage/default/0.chip_sw_aon_timer_irq.1715105522 Aug 04 07:16:03 PM PDT 24 Aug 04 07:23:04 PM PDT 24 3776702306 ps
T299 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.967208024 Aug 04 07:40:36 PM PDT 24 Aug 04 07:48:41 PM PDT 24 3616293380 ps
T746 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.2695186087 Aug 04 07:41:24 PM PDT 24 Aug 04 07:46:10 PM PDT 24 2591045440 ps
T117 /workspace/coverage/default/2.chip_tap_straps_rma.2595161419 Aug 04 07:45:43 PM PDT 24 Aug 04 07:49:12 PM PDT 24 3101473936 ps
T747 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.906731518 Aug 04 07:36:07 PM PDT 24 Aug 04 07:47:05 PM PDT 24 4045789328 ps
T748 /workspace/coverage/default/96.chip_sw_all_escalation_resets.2523873452 Aug 04 08:01:40 PM PDT 24 Aug 04 08:09:51 PM PDT 24 4923617352 ps
T749 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.4289950992 Aug 04 07:28:43 PM PDT 24 Aug 04 07:35:46 PM PDT 24 4457059232 ps
T750 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.324191340 Aug 04 07:50:26 PM PDT 24 Aug 04 08:01:24 PM PDT 24 6361629200 ps
T751 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3386243982 Aug 04 07:50:18 PM PDT 24 Aug 04 07:54:07 PM PDT 24 2354475848 ps
T254 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2916557534 Aug 04 07:13:32 PM PDT 24 Aug 04 07:19:08 PM PDT 24 5189071320 ps
T80 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4001456840 Aug 04 07:42:58 PM PDT 24 Aug 04 07:49:01 PM PDT 24 4864830624 ps
T752 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2037225152 Aug 04 07:27:44 PM PDT 24 Aug 04 07:34:45 PM PDT 24 7111266744 ps
T753 /workspace/coverage/default/0.chip_sw_kmac_entropy.2903563923 Aug 04 07:14:34 PM PDT 24 Aug 04 07:18:24 PM PDT 24 1936145744 ps
T754 /workspace/coverage/default/1.rom_e2e_shutdown_output.403592570 Aug 04 07:36:34 PM PDT 24 Aug 04 08:37:53 PM PDT 24 29231670600 ps
T755 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2758950892 Aug 04 07:32:46 PM PDT 24 Aug 04 07:44:30 PM PDT 24 4724152840 ps
T756 /workspace/coverage/default/32.chip_sw_all_escalation_resets.604867464 Aug 04 07:56:18 PM PDT 24 Aug 04 08:07:32 PM PDT 24 4402295014 ps
T118 /workspace/coverage/default/0.chip_tap_straps_testunlock0.331054659 Aug 04 07:15:45 PM PDT 24 Aug 04 07:23:26 PM PDT 24 5967565388 ps
T757 /workspace/coverage/default/0.chip_sw_edn_kat.3087837545 Aug 04 07:13:59 PM PDT 24 Aug 04 07:23:48 PM PDT 24 3234098940 ps
T83 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4027236849 Aug 04 07:30:29 PM PDT 24 Aug 04 07:38:09 PM PDT 24 5635477400 ps
T758 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3644190772 Aug 04 07:35:28 PM PDT 24 Aug 04 07:39:21 PM PDT 24 3135992356 ps
T759 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2362546349 Aug 04 07:38:15 PM PDT 24 Aug 04 07:42:52 PM PDT 24 2261379554 ps
T760 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.876803196 Aug 04 07:51:22 PM PDT 24 Aug 04 09:26:35 PM PDT 24 26453828030 ps
T761 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2583838639 Aug 04 07:39:39 PM PDT 24 Aug 04 07:43:14 PM PDT 24 2866474588 ps
T762 /workspace/coverage/default/1.chip_sw_otbn_smoketest.3630419462 Aug 04 07:40:06 PM PDT 24 Aug 04 08:12:39 PM PDT 24 7484522520 ps
T763 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.564084436 Aug 04 07:17:54 PM PDT 24 Aug 04 07:40:28 PM PDT 24 7801430800 ps
T764 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1409002980 Aug 04 07:42:42 PM PDT 24 Aug 04 07:56:04 PM PDT 24 7713876240 ps
T765 /workspace/coverage/default/2.chip_sw_example_flash.3148454070 Aug 04 07:35:54 PM PDT 24 Aug 04 07:40:32 PM PDT 24 3192734150 ps
T766 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1808540954 Aug 04 07:25:00 PM PDT 24 Aug 04 07:42:45 PM PDT 24 6445121550 ps
T148 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2852331946 Aug 04 07:32:02 PM PDT 24 Aug 04 07:37:46 PM PDT 24 4007756368 ps
T767 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3904783285 Aug 04 07:56:15 PM PDT 24 Aug 04 08:02:00 PM PDT 24 3183452820 ps
T768 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2174551006 Aug 04 07:36:35 PM PDT 24 Aug 04 08:35:32 PM PDT 24 25025929616 ps
T146 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.869464945 Aug 04 07:46:18 PM PDT 24 Aug 04 08:13:07 PM PDT 24 24826385332 ps
T172 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.134973131 Aug 04 07:28:46 PM PDT 24 Aug 04 07:39:01 PM PDT 24 5249120692 ps
T769 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.513977273 Aug 04 07:28:27 PM PDT 24 Aug 04 07:33:15 PM PDT 24 3058587765 ps
T770 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1621047547 Aug 04 07:26:58 PM PDT 24 Aug 04 09:29:17 PM PDT 24 24356081136 ps
T333 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3198509130 Aug 04 07:46:06 PM PDT 24 Aug 04 07:54:07 PM PDT 24 3826113064 ps
T329 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1980641904 Aug 04 07:45:12 PM PDT 24 Aug 04 07:53:09 PM PDT 24 4798032494 ps
T771 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1622799628 Aug 04 07:30:09 PM PDT 24 Aug 04 07:35:15 PM PDT 24 3335798288 ps
T346 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.673957683 Aug 04 07:28:51 PM PDT 24 Aug 04 07:33:43 PM PDT 24 2724901100 ps
T462 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3541498437 Aug 04 07:54:05 PM PDT 24 Aug 04 08:00:15 PM PDT 24 3575090538 ps
T248 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3544018942 Aug 04 07:38:09 PM PDT 24 Aug 04 09:04:01 PM PDT 24 47651919928 ps
T104 /workspace/coverage/default/0.chip_plic_all_irqs_10.3045931235 Aug 04 07:17:09 PM PDT 24 Aug 04 07:24:11 PM PDT 24 3863529128 ps
T772 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1027943469 Aug 04 07:23:14 PM PDT 24 Aug 04 07:35:45 PM PDT 24 3996139040 ps
T773 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1663861505 Aug 04 07:30:45 PM PDT 24 Aug 04 08:06:31 PM PDT 24 9216401480 ps
T381 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.646519969 Aug 04 07:38:24 PM PDT 24 Aug 04 07:48:49 PM PDT 24 4594399247 ps
T420 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4286083646 Aug 04 07:17:37 PM PDT 24 Aug 04 07:25:17 PM PDT 24 4819656018 ps
T198 /workspace/coverage/default/1.rom_raw_unlock.1504002994 Aug 04 07:34:35 PM PDT 24 Aug 04 07:39:08 PM PDT 24 5900330313 ps
T774 /workspace/coverage/default/2.chip_sw_hmac_enc.3950053480 Aug 04 07:41:42 PM PDT 24 Aug 04 07:45:59 PM PDT 24 3000827000 ps
T775 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.4039886762 Aug 04 07:47:50 PM PDT 24 Aug 04 07:56:13 PM PDT 24 5016544994 ps
T776 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1479823345 Aug 04 07:14:29 PM PDT 24 Aug 04 08:46:39 PM PDT 24 28509553964 ps
T129 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3366787717 Aug 04 07:29:12 PM PDT 24 Aug 04 07:36:20 PM PDT 24 3578647932 ps
T777 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1844389242 Aug 04 07:41:48 PM PDT 24 Aug 04 07:45:46 PM PDT 24 2585938220 ps
T778 /workspace/coverage/default/0.rom_e2e_shutdown_output.3794753600 Aug 04 07:24:26 PM PDT 24 Aug 04 08:27:54 PM PDT 24 22948228816 ps
T779 /workspace/coverage/default/56.chip_sw_all_escalation_resets.2679324419 Aug 04 08:00:43 PM PDT 24 Aug 04 08:11:10 PM PDT 24 6484018856 ps
T425 /workspace/coverage/default/0.rom_volatile_raw_unlock.2709508790 Aug 04 07:19:37 PM PDT 24 Aug 04 07:21:20 PM PDT 24 2354124013 ps
T90 /workspace/coverage/default/0.chip_tap_straps_rma.2649074299 Aug 04 07:16:10 PM PDT 24 Aug 04 07:28:12 PM PDT 24 7402384796 ps
T780 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3646446861 Aug 04 07:26:38 PM PDT 24 Aug 04 07:33:52 PM PDT 24 7140606630 ps
T781 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2174562228 Aug 04 07:22:06 PM PDT 24 Aug 04 08:26:10 PM PDT 24 15178422264 ps
T782 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2370717171 Aug 04 07:45:48 PM PDT 24 Aug 04 07:49:19 PM PDT 24 2067028647 ps
T783 /workspace/coverage/default/1.chip_sw_aes_idle.955353330 Aug 04 07:32:05 PM PDT 24 Aug 04 07:36:16 PM PDT 24 2753597832 ps
T280 /workspace/coverage/default/88.chip_sw_all_escalation_resets.1547044775 Aug 04 08:00:39 PM PDT 24 Aug 04 08:10:36 PM PDT 24 6445524672 ps
T784 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.164955505 Aug 04 07:19:18 PM PDT 24 Aug 04 07:24:27 PM PDT 24 3011061604 ps
T785 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2469422909 Aug 04 07:37:48 PM PDT 24 Aug 04 07:46:46 PM PDT 24 4329965180 ps
T786 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1528598307 Aug 04 07:38:20 PM PDT 24 Aug 04 07:59:14 PM PDT 24 6199293000 ps
T787 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1365090742 Aug 04 07:39:24 PM PDT 24 Aug 04 07:49:35 PM PDT 24 8410032200 ps
T788 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3640710431 Aug 04 07:19:06 PM PDT 24 Aug 04 07:27:02 PM PDT 24 3896133560 ps
T789 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3353910121 Aug 04 07:21:33 PM PDT 24 Aug 04 08:27:26 PM PDT 24 15180275128 ps
T790 /workspace/coverage/default/1.rom_volatile_raw_unlock.2544939161 Aug 04 07:33:49 PM PDT 24 Aug 04 07:35:38 PM PDT 24 2828310901 ps
T791 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3619949428 Aug 04 07:44:04 PM PDT 24 Aug 04 07:50:05 PM PDT 24 3585066660 ps
T792 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3815478755 Aug 04 07:30:26 PM PDT 24 Aug 04 08:11:52 PM PDT 24 30092823413 ps
T793 /workspace/coverage/default/0.chip_sw_example_flash.2571750441 Aug 04 07:15:49 PM PDT 24 Aug 04 07:19:27 PM PDT 24 3055292824 ps
T308 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1788210959 Aug 04 07:53:14 PM PDT 24 Aug 04 07:59:09 PM PDT 24 4144626968 ps
T467 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3138408589 Aug 04 07:55:15 PM PDT 24 Aug 04 08:02:00 PM PDT 24 3924049352 ps
T794 /workspace/coverage/default/4.chip_sw_uart_tx_rx.623610731 Aug 04 07:51:02 PM PDT 24 Aug 04 08:00:15 PM PDT 24 3957145750 ps
T34 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.4035671854 Aug 04 07:37:02 PM PDT 24 Aug 04 07:41:31 PM PDT 24 3713378520 ps
T795 /workspace/coverage/default/1.chip_tap_straps_testunlock0.351466992 Aug 04 07:33:02 PM PDT 24 Aug 04 07:40:04 PM PDT 24 5247794294 ps
T796 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.3795089481 Aug 04 07:24:54 PM PDT 24 Aug 04 10:53:44 PM PDT 24 63417903346 ps
T797 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3922422592 Aug 04 07:16:27 PM PDT 24 Aug 04 07:22:48 PM PDT 24 4576537046 ps
T798 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.512067268 Aug 04 07:16:43 PM PDT 24 Aug 04 07:24:35 PM PDT 24 3642741735 ps
T799 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.122527989 Aug 04 07:16:26 PM PDT 24 Aug 04 07:22:18 PM PDT 24 3240009808 ps
T800 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1491719792 Aug 04 07:42:26 PM PDT 24 Aug 04 07:55:31 PM PDT 24 6200034369 ps
T801 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3040084258 Aug 04 07:16:06 PM PDT 24 Aug 04 08:58:25 PM PDT 24 50011519207 ps
T364 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1361948651 Aug 04 07:39:23 PM PDT 24 Aug 04 07:49:14 PM PDT 24 4064638722 ps
T352 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3581550892 Aug 04 07:57:22 PM PDT 24 Aug 04 08:04:18 PM PDT 24 3762738152 ps
T802 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.455970170 Aug 04 07:37:27 PM PDT 24 Aug 04 10:48:08 PM PDT 24 63645747845 ps
T803 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3937587784 Aug 04 07:44:34 PM PDT 24 Aug 04 07:53:34 PM PDT 24 4507018200 ps
T804 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2933214722 Aug 04 07:16:00 PM PDT 24 Aug 04 07:28:47 PM PDT 24 7860640706 ps
T805 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2268900383 Aug 04 07:46:59 PM PDT 24 Aug 04 07:53:03 PM PDT 24 3145665221 ps
T806 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2122732399 Aug 04 07:37:08 PM PDT 24 Aug 04 08:41:22 PM PDT 24 15535819634 ps
T232 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.866092070 Aug 04 07:25:04 PM PDT 24 Aug 04 07:39:15 PM PDT 24 5252672034 ps
T807 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.3445558091 Aug 04 07:18:58 PM PDT 24 Aug 04 07:36:49 PM PDT 24 6979879440 ps
T808 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1007500606 Aug 04 07:52:08 PM PDT 24 Aug 04 08:34:57 PM PDT 24 13660718200 ps
T201 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3729832923 Aug 04 07:14:11 PM PDT 24 Aug 04 07:18:29 PM PDT 24 3012858923 ps
T809 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1488390833 Aug 04 07:13:54 PM PDT 24 Aug 04 07:18:59 PM PDT 24 5728236071 ps
T810 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1965015088 Aug 04 07:24:46 PM PDT 24 Aug 04 09:06:17 PM PDT 24 23999548250 ps
T811 /workspace/coverage/default/2.rom_e2e_shutdown_output.3211854539 Aug 04 07:50:21 PM PDT 24 Aug 04 09:00:36 PM PDT 24 31317236720 ps
T812 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3308807460 Aug 04 07:28:26 PM PDT 24 Aug 04 07:49:33 PM PDT 24 6027544728 ps
T813 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2136338194 Aug 04 07:18:35 PM PDT 24 Aug 04 08:26:45 PM PDT 24 25085414889 ps
T202 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1320534471 Aug 04 07:36:54 PM PDT 24 Aug 04 07:41:32 PM PDT 24 2686119126 ps
T186 /workspace/coverage/default/2.chip_sw_edn_boot_mode.227401462 Aug 04 07:42:10 PM PDT 24 Aug 04 07:55:21 PM PDT 24 2797984120 ps
T814 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.979514130 Aug 04 07:29:53 PM PDT 24 Aug 04 07:48:04 PM PDT 24 7452121426 ps
T384 /workspace/coverage/default/0.chip_sw_pattgen_ios.3065081564 Aug 04 07:13:30 PM PDT 24 Aug 04 07:16:43 PM PDT 24 2574424400 ps
T815 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.570082079 Aug 04 07:16:50 PM PDT 24 Aug 04 08:21:03 PM PDT 24 17487893992 ps
T816 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3558211767 Aug 04 08:01:25 PM PDT 24 Aug 04 08:07:00 PM PDT 24 4040502858 ps
T460 /workspace/coverage/default/42.chip_sw_all_escalation_resets.836196671 Aug 04 07:55:37 PM PDT 24 Aug 04 08:09:23 PM PDT 24 6412892774 ps
T817 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3170106802 Aug 04 07:42:21 PM PDT 24 Aug 04 08:09:23 PM PDT 24 6834317944 ps
T818 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1614803074 Aug 04 07:35:53 PM PDT 24 Aug 04 08:01:17 PM PDT 24 8531618010 ps
T819 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.4069090359 Aug 04 07:35:00 PM PDT 24 Aug 04 08:09:35 PM PDT 24 22987850817 ps
T820 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1727130692 Aug 04 07:21:23 PM PDT 24 Aug 04 07:26:31 PM PDT 24 2873344776 ps
T821 /workspace/coverage/default/2.chip_sw_csrng_kat_test.4164905270 Aug 04 07:41:59 PM PDT 24 Aug 04 07:45:39 PM PDT 24 2483895548 ps
T91 /workspace/coverage/default/1.chip_tap_straps_rma.858564324 Aug 04 07:32:02 PM PDT 24 Aug 04 07:36:17 PM PDT 24 3652373810 ps
T822 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.4278939300 Aug 04 07:56:39 PM PDT 24 Aug 04 08:03:33 PM PDT 24 3664298472 ps
T497 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1554299922 Aug 04 07:59:15 PM PDT 24 Aug 04 08:05:01 PM PDT 24 3546995416 ps
T823 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.4081790415 Aug 04 07:23:18 PM PDT 24 Aug 04 07:33:56 PM PDT 24 5144819608 ps
T824 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1633496834 Aug 04 07:44:53 PM PDT 24 Aug 04 07:54:20 PM PDT 24 4507971120 ps
T825 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3819745635 Aug 04 07:40:29 PM PDT 24 Aug 04 07:48:08 PM PDT 24 7178725090 ps
T27 /workspace/coverage/default/0.chip_sw_gpio.1298795331 Aug 04 07:14:00 PM PDT 24 Aug 04 07:21:06 PM PDT 24 4158427200 ps
T826 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3612551864 Aug 04 07:20:39 PM PDT 24 Aug 04 08:22:31 PM PDT 24 15573910530 ps
T827 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2692041925 Aug 04 07:38:03 PM PDT 24 Aug 04 07:42:54 PM PDT 24 2814571271 ps
T111 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3158400392 Aug 04 07:14:18 PM PDT 24 Aug 04 07:21:53 PM PDT 24 6538976648 ps
T828 /workspace/coverage/default/1.chip_sw_otbn_randomness.4023648436 Aug 04 07:27:34 PM PDT 24 Aug 04 07:41:17 PM PDT 24 6040425100 ps
T829 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.171392937 Aug 04 07:25:57 PM PDT 24 Aug 04 08:06:00 PM PDT 24 20455056172 ps
T830 /workspace/coverage/default/0.chip_sw_kmac_smoketest.1588525534 Aug 04 07:20:06 PM PDT 24 Aug 04 07:24:38 PM PDT 24 2825329704 ps
T130 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.298876867 Aug 04 07:58:52 PM PDT 24 Aug 04 08:04:24 PM PDT 24 3278293276 ps
T286 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.489656870 Aug 04 07:36:26 PM PDT 24 Aug 04 07:47:36 PM PDT 24 4489302408 ps
T287 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2613451792 Aug 04 07:38:53 PM PDT 24 Aug 04 07:50:43 PM PDT 24 7445309892 ps
T288 /workspace/coverage/default/2.rom_raw_unlock.3961086678 Aug 04 07:48:47 PM PDT 24 Aug 04 07:54:08 PM PDT 24 5182900644 ps
T289 /workspace/coverage/default/70.chip_sw_all_escalation_resets.27579287 Aug 04 07:58:51 PM PDT 24 Aug 04 08:07:49 PM PDT 24 5464575880 ps
T290 /workspace/coverage/default/1.rom_e2e_static_critical.868107335 Aug 04 07:39:06 PM PDT 24 Aug 04 08:52:05 PM PDT 24 17565295566 ps
T291 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1353207841 Aug 04 07:58:07 PM PDT 24 Aug 04 08:04:16 PM PDT 24 4028927270 ps
T292 /workspace/coverage/default/2.chip_sw_csrng_smoketest.1085057986 Aug 04 07:47:44 PM PDT 24 Aug 04 07:50:39 PM PDT 24 2133663768 ps
T293 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2968720099 Aug 04 07:24:28 PM PDT 24 Aug 04 07:27:58 PM PDT 24 2957387016 ps
T294 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3266038247 Aug 04 07:50:58 PM PDT 24 Aug 04 07:55:19 PM PDT 24 2735092296 ps
T295 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.17336207 Aug 04 08:00:21 PM PDT 24 Aug 04 08:06:19 PM PDT 24 3808892962 ps
T831 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.759730593 Aug 04 07:44:26 PM PDT 24 Aug 04 07:54:35 PM PDT 24 4473342972 ps
T832 /workspace/coverage/default/1.chip_sw_gpio_smoketest.3438934362 Aug 04 07:33:38 PM PDT 24 Aug 04 07:39:22 PM PDT 24 3003636031 ps
T833 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.554446203 Aug 04 07:26:59 PM PDT 24 Aug 04 07:52:10 PM PDT 24 13517289926 ps
T834 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.170944965 Aug 04 07:42:34 PM PDT 24 Aug 04 07:51:24 PM PDT 24 4390671464 ps
T835 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3072063258 Aug 04 07:16:23 PM PDT 24 Aug 04 07:30:39 PM PDT 24 8799220988 ps
T836 /workspace/coverage/default/2.chip_sw_flash_crash_alert.3495663060 Aug 04 07:47:04 PM PDT 24 Aug 04 07:57:55 PM PDT 24 5566791660 ps
T837 /workspace/coverage/default/0.chip_sw_usbdev_dpi.799633726 Aug 04 07:14:54 PM PDT 24 Aug 04 08:09:18 PM PDT 24 12878538536 ps
T838 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1830036338 Aug 04 07:27:18 PM PDT 24 Aug 04 07:32:55 PM PDT 24 3214469864 ps
T347 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3956145473 Aug 04 07:14:12 PM PDT 24 Aug 04 07:18:43 PM PDT 24 2565882156 ps
T839 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1572614392 Aug 04 07:14:44 PM PDT 24 Aug 04 07:25:01 PM PDT 24 4711734838 ps
T840 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2075900352 Aug 04 07:35:17 PM PDT 24 Aug 04 07:42:51 PM PDT 24 6003179244 ps
T841 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.4026023316 Aug 04 07:28:44 PM PDT 24 Aug 04 07:57:06 PM PDT 24 7948159656 ps
T842 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2579733171 Aug 04 07:49:50 PM PDT 24 Aug 04 07:55:49 PM PDT 24 3345038964 ps
T843 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2533308001 Aug 04 07:42:38 PM PDT 24 Aug 04 07:59:56 PM PDT 24 6213074573 ps
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