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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.33 90.80 80.59 90.24 92.12 97.35 84.87


Total test records in report: 1026
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T1017 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.809047820 Aug 04 07:17:03 PM PDT 24 Aug 04 07:29:16 PM PDT 24 4501289496 ps
T500 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.42424960 Aug 04 08:00:09 PM PDT 24 Aug 04 08:05:34 PM PDT 24 4574972152 ps
T432 /workspace/coverage/default/16.chip_sw_all_escalation_resets.1618099961 Aug 04 07:53:55 PM PDT 24 Aug 04 08:01:35 PM PDT 24 5485866648 ps
T1018 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.4103036536 Aug 04 07:22:35 PM PDT 24 Aug 04 08:32:20 PM PDT 24 14811728840 ps
T399 /workspace/coverage/default/87.chip_sw_all_escalation_resets.1482360368 Aug 04 08:00:22 PM PDT 24 Aug 04 08:08:18 PM PDT 24 4242081160 ps
T1019 /workspace/coverage/default/0.chip_sw_aes_enc.44646296 Aug 04 07:14:58 PM PDT 24 Aug 04 07:18:54 PM PDT 24 2960031726 ps
T1020 /workspace/coverage/default/2.chip_sw_example_concurrency.89477011 Aug 04 07:35:08 PM PDT 24 Aug 04 07:39:53 PM PDT 24 2844253636 ps
T88 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1482372036 Aug 04 07:48:04 PM PDT 24 Aug 04 08:24:09 PM PDT 24 14766130486 ps
T211 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.854188635 Aug 04 07:14:59 PM PDT 24 Aug 04 07:23:23 PM PDT 24 4752015800 ps
T1021 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.713986610 Aug 04 07:49:22 PM PDT 24 Aug 04 07:59:03 PM PDT 24 4832136568 ps
T1022 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3887476618 Aug 04 07:58:35 PM PDT 24 Aug 04 08:05:22 PM PDT 24 4362568300 ps
T476 /workspace/coverage/default/77.chip_sw_all_escalation_resets.3188747787 Aug 04 08:00:19 PM PDT 24 Aug 04 08:12:06 PM PDT 24 4855299772 ps
T1023 /workspace/coverage/default/0.chip_sw_aes_masking_off.95380566 Aug 04 07:16:33 PM PDT 24 Aug 04 07:21:40 PM PDT 24 3448581170 ps
T1024 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1235836760 Aug 04 07:41:27 PM PDT 24 Aug 04 08:31:58 PM PDT 24 14772805696 ps
T1025 /workspace/coverage/default/0.chip_sw_aes_idle.4200599791 Aug 04 07:17:28 PM PDT 24 Aug 04 07:21:20 PM PDT 24 3306487386 ps
T1026 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1212780923 Aug 04 07:17:32 PM PDT 24 Aug 04 07:21:58 PM PDT 24 3128251823 ps
T29 /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1696240559 Aug 04 07:06:21 PM PDT 24 Aug 04 07:09:41 PM PDT 24 4755524675 ps
T30 /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.506914179 Aug 04 07:06:22 PM PDT 24 Aug 04 07:09:43 PM PDT 24 3752378691 ps
T31 /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2129899363 Aug 04 07:06:23 PM PDT 24 Aug 04 07:10:54 PM PDT 24 5109307950 ps
T33 /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2831222080 Aug 04 07:06:20 PM PDT 24 Aug 04 07:09:58 PM PDT 24 5019085273 ps
T234 /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1409371235 Aug 04 07:06:26 PM PDT 24 Aug 04 07:11:52 PM PDT 24 4872460720 ps
T235 /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.545822328 Aug 04 07:06:22 PM PDT 24 Aug 04 07:10:48 PM PDT 24 5107117745 ps
T236 /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1954381189 Aug 04 07:06:30 PM PDT 24 Aug 04 07:10:23 PM PDT 24 4515311632 ps
T237 /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2245265714 Aug 04 07:06:26 PM PDT 24 Aug 04 07:11:06 PM PDT 24 4660298891 ps
T238 /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1177379512 Aug 04 07:06:23 PM PDT 24 Aug 04 07:10:17 PM PDT 24 4528064330 ps
T239 /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3632494374 Aug 04 07:06:26 PM PDT 24 Aug 04 07:11:25 PM PDT 24 5225866541 ps

Test location /workspace/coverage/default/73.chip_sw_all_escalation_resets.1965330380
Short name T125
Test name
Test status
Simulation time 4680138672 ps
CPU time 544.38 seconds
Started Aug 04 08:00:13 PM PDT 24
Finished Aug 04 08:09:18 PM PDT 24
Peak memory 650132 kb
Host smart-7769b0ba-21b8-44a9-b5ff-3a69b0e6d028
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1965330380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.1965330380
Directory /workspace/73.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/1.chip_jtag_csr_rw.240350244
Short name T110
Test name
Test status
Simulation time 13998385396 ps
CPU time 1458.79 seconds
Started Aug 04 07:24:40 PM PDT 24
Finished Aug 04 07:48:59 PM PDT 24
Peak memory 608028 kb
Host smart-5b91c13e-934c-427d-8cec-edf47780d281
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240350244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch
ip_jtag_csr_rw.240350244
Directory /workspace/1.chip_jtag_csr_rw/latest

Test location /workspace/coverage/default/2.chip_sw_alert_test.1882210423
Short name T97
Test name
Test status
Simulation time 2655435360 ps
CPU time 244.99 seconds
Started Aug 04 07:42:03 PM PDT 24
Finished Aug 04 07:46:08 PM PDT 24
Peak memory 609736 kb
Host smart-b76fa097-56c4-4184-8ab8-1f1ee05c01a5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882210423 -assert nopostproc +UVM_TESTNAME=chip_ba
se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.chip_sw_alert_test.1882210423
Directory /workspace/2.chip_sw_alert_test/latest

Test location /workspace/coverage/default/0.chip_jtag_csr_rw.2100078205
Short name T6
Test name
Test status
Simulation time 12815059400 ps
CPU time 1173.34 seconds
Started Aug 04 07:08:40 PM PDT 24
Finished Aug 04 07:28:14 PM PDT 24
Peak memory 608012 kb
Host smart-a3648b6b-164f-45ff-8523-aaaa9873ea63
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100078205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c
hip_jtag_csr_rw.2100078205
Directory /workspace/0.chip_jtag_csr_rw/latest

Test location /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1696240559
Short name T29
Test name
Test status
Simulation time 4755524675 ps
CPU time 198.87 seconds
Started Aug 04 07:06:21 PM PDT 24
Finished Aug 04 07:09:41 PM PDT 24
Peak memory 640924 kb
Host smart-85c23e44-917e-41c1-aaea-b35ed5b037c3
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696240559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 4.chip_padctrl_attributes.1696240559
Directory /workspace/4.chip_padctrl_attributes/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3711260549
Short name T32
Test name
Test status
Simulation time 11164457166 ps
CPU time 2213.03 seconds
Started Aug 04 07:15:56 PM PDT 24
Finished Aug 04 07:52:49 PM PDT 24
Peak memory 617976 kb
Host smart-02537568-d7c6-46ca-b7ab-590c651ac311
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3711260549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.3711260549
Directory /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1894993273
Short name T5
Test name
Test status
Simulation time 47967809912 ps
CPU time 6022.51 seconds
Started Aug 04 07:14:55 PM PDT 24
Finished Aug 04 08:55:19 PM PDT 24
Peak memory 620600 kb
Host smart-1bcc1064-82d6-4308-8acd-11a64c06e60f
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d
evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894993273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi
p_sw_lc_walkthrough_prod.1894993273
Directory /workspace/0.chip_sw_lc_walkthrough_prod/latest

Test location /workspace/coverage/default/1.chip_plic_all_irqs_0.2321696261
Short name T187
Test name
Test status
Simulation time 6156066296 ps
CPU time 1329.91 seconds
Started Aug 04 07:30:53 PM PDT 24
Finished Aug 04 07:53:04 PM PDT 24
Peak memory 610112 kb
Host smart-65fe2ed1-7614-4ed1-bfc7-20f26f688e85
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321696261 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_plic_all_irqs_0.2321696261
Directory /workspace/1.chip_plic_all_irqs_0/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.900818954
Short name T7
Test name
Test status
Simulation time 3012363348 ps
CPU time 197.69 seconds
Started Aug 04 07:20:46 PM PDT 24
Finished Aug 04 07:24:04 PM PDT 24
Peak memory 610120 kb
Host smart-424c23a1-99a7-4e30-9527-f5a6a20025b7
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9008
18954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.900818954
Directory /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest

Test location /workspace/coverage/default/0.chip_sw_power_virus.1689778779
Short name T11
Test name
Test status
Simulation time 5888117108 ps
CPU time 1539.42 seconds
Started Aug 04 07:22:09 PM PDT 24
Finished Aug 04 07:47:49 PM PDT 24
Peak memory 625016 kb
Host smart-d4f6f994-736a-4c14-a89c-833bcc785088
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_
power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes
t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1689778779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.1689778779
Directory /workspace/0.chip_sw_power_virus/latest

Test location /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3372471740
Short name T49
Test name
Test status
Simulation time 15368204430 ps
CPU time 3189.84 seconds
Started Aug 04 07:51:43 PM PDT 24
Finished Aug 04 08:44:54 PM PDT 24
Peak memory 610180 kb
Host smart-0a9d5ca9-0721-463b-94df-aa98c711cf14
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:
new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372471740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.3372471740
Directory /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3956392936
Short name T221
Test name
Test status
Simulation time 2771581714 ps
CPU time 218.18 seconds
Started Aug 04 07:47:32 PM PDT 24
Finished Aug 04 07:51:10 PM PDT 24
Peak memory 608512 kb
Host smart-657dbb16-6ee8-4d29-8e04-5659dfda4edf
User root
Command /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3956392936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.3956392936
Directory /workspace/2.chip_sw_rv_core_ibex_address_translation/latest

Test location /workspace/coverage/default/0.chip_plic_all_irqs_20.3302073435
Short name T190
Test name
Test status
Simulation time 4531688904 ps
CPU time 622.3 seconds
Started Aug 04 07:16:06 PM PDT 24
Finished Aug 04 07:26:29 PM PDT 24
Peak memory 610016 kb
Host smart-dc5f0c82-1d51-4174-912c-b83106bd64d1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302073435 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.chip_plic_all_irqs_20.3302073435
Directory /workspace/0.chip_plic_all_irqs_20/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2457576546
Short name T340
Test name
Test status
Simulation time 9717650060 ps
CPU time 1511.74 seconds
Started Aug 04 07:43:06 PM PDT 24
Finished Aug 04 08:08:18 PM PDT 24
Peak memory 610872 kb
Host smart-b32a125a-62d9-49fc-9223-5fd35592a228
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245757
6546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.2457576546
Directory /workspace/2.chip_sw_keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.506069404
Short name T17
Test name
Test status
Simulation time 23416759500 ps
CPU time 1472.56 seconds
Started Aug 04 07:44:50 PM PDT 24
Finished Aug 04 08:09:23 PM PDT 24
Peak memory 611144 kb
Host smart-1a3d17ff-60bd-4a63-ace6-059f4f0ebeb9
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
506069404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.506069404
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/2.chip_jtag_csr_rw.2538820230
Short name T52
Test name
Test status
Simulation time 12759614764 ps
CPU time 1290.92 seconds
Started Aug 04 07:37:40 PM PDT 24
Finished Aug 04 07:59:11 PM PDT 24
Peak memory 608040 kb
Host smart-122ee7e7-98ca-4548-9f39-c6af35225ace
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538820230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c
hip_jtag_csr_rw.2538820230
Directory /workspace/2.chip_jtag_csr_rw/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.367998010
Short name T212
Test name
Test status
Simulation time 5774839040 ps
CPU time 658.8 seconds
Started Aug 04 07:28:46 PM PDT 24
Finished Aug 04 07:39:45 PM PDT 24
Peak memory 610564 kb
Host smart-6e39c10d-5d52-4d3b-972c-0fc620d0d231
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367998010 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_rstmgr_cpu_info.367998010
Directory /workspace/1.chip_sw_rstmgr_cpu_info/latest

Test location /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1382428357
Short name T1
Test name
Test status
Simulation time 3208993800 ps
CPU time 415.29 seconds
Started Aug 04 08:00:17 PM PDT 24
Finished Aug 04 08:07:12 PM PDT 24
Peak memory 649096 kb
Host smart-374c7b42-49e3-4b14-99b0-2da4612f8429
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382428357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1382428357
Directory /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/2.chip_plic_all_irqs_10.3098320807
Short name T103
Test name
Test status
Simulation time 3245826384 ps
CPU time 551.81 seconds
Started Aug 04 07:43:43 PM PDT 24
Finished Aug 04 07:52:55 PM PDT 24
Peak memory 608508 kb
Host smart-34be454b-795e-4efc-afc9-1f93fd7724f1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098320807 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.chip_plic_all_irqs_10.3098320807
Directory /workspace/2.chip_plic_all_irqs_10/latest

Test location /workspace/coverage/default/2.chip_sw_gpio_smoketest.219251301
Short name T13
Test name
Test status
Simulation time 2561944447 ps
CPU time 335.36 seconds
Started Aug 04 07:48:25 PM PDT 24
Finished Aug 04 07:54:00 PM PDT 24
Peak memory 608740 kb
Host smart-3ef32049-bc2a-4c8d-9508-13316f430b2d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219251301 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_gpio_smoketest.219251301
Directory /workspace/2.chip_sw_gpio_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1874775843
Short name T78
Test name
Test status
Simulation time 6707635480 ps
CPU time 537.89 seconds
Started Aug 04 07:30:46 PM PDT 24
Finished Aug 04 07:39:44 PM PDT 24
Peak memory 610592 kb
Host smart-46b343b9-089e-431a-b103-0cb0838f8550
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18747758
43 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.1874775843
Directory /workspace/1.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.48115269
Short name T168
Test name
Test status
Simulation time 16370699432 ps
CPU time 3682.61 seconds
Started Aug 04 07:52:23 PM PDT 24
Finished Aug 04 08:53:46 PM PDT 24
Peak memory 610192 kb
Host smart-3d9ca82a-e0ff-4109-8b4b-0aacb84dcb88
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48115269 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.48115269
Directory /workspace/8.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.833432390
Short name T56
Test name
Test status
Simulation time 3484255680 ps
CPU time 333.66 seconds
Started Aug 04 07:13:53 PM PDT 24
Finished Aug 04 07:19:27 PM PDT 24
Peak memory 617788 kb
Host smart-553b1a9d-6a81-4651-aa46-dc0598cb792b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833432390 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.833432390
Directory /workspace/0.chip_sw_spi_device_pinmux_sleep_retention/latest

Test location /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.664302519
Short name T54
Test name
Test status
Simulation time 10227750955 ps
CPU time 775.62 seconds
Started Aug 04 07:51:30 PM PDT 24
Finished Aug 04 08:04:26 PM PDT 24
Peak memory 620392 kb
Host smart-dcec70ef-ebd1-47e4-b9c2-093eabdc6d14
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664302519 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.664302519
Directory /workspace/6.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3682576021
Short name T79
Test name
Test status
Simulation time 4722808872 ps
CPU time 444.75 seconds
Started Aug 04 07:17:53 PM PDT 24
Finished Aug 04 07:25:18 PM PDT 24
Peak memory 609996 kb
Host smart-169730d5-00d9-4d73-b106-9b42e508994b
User root
Command /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36825760
21 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3682576021
Directory /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1111106889
Short name T99
Test name
Test status
Simulation time 13440193142 ps
CPU time 1542.33 seconds
Started Aug 04 07:41:23 PM PDT 24
Finished Aug 04 08:07:06 PM PDT 24
Peak memory 610760 kb
Host smart-0d7c01a1-0e77-44cd-8a91-907a41cd9103
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler
_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111106889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han
dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.chip_sw_alert_handler_lpg_sleep_mode_pings.1111106889
Directory /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3823349441
Short name T9
Test name
Test status
Simulation time 3060630377 ps
CPU time 293.52 seconds
Started Aug 04 07:15:26 PM PDT 24
Finished Aug 04 07:20:20 PM PDT 24
Peak memory 610216 kb
Host smart-3141c9a5-10a3-48b3-a34c-5d38e37a3bd1
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823
349441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.3823349441
Directory /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest

Test location /workspace/coverage/default/78.chip_sw_all_escalation_resets.3984325915
Short name T157
Test name
Test status
Simulation time 6139339192 ps
CPU time 591.32 seconds
Started Aug 04 08:00:40 PM PDT 24
Finished Aug 04 08:10:31 PM PDT 24
Peak memory 649976 kb
Host smart-c56a61c1-e08e-4537-a154-9b7bc74eb1b8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3984325915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.3984325915
Directory /workspace/78.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1409371235
Short name T234
Test name
Test status
Simulation time 4872460720 ps
CPU time 325.66 seconds
Started Aug 04 07:06:26 PM PDT 24
Finished Aug 04 07:11:52 PM PDT 24
Peak memory 652876 kb
Host smart-402013e7-5bbc-401c-bb09-4bb0f0729c46
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409371235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 0.chip_padctrl_attributes.1409371235
Directory /workspace/0.chip_padctrl_attributes/latest

Test location /workspace/coverage/default/79.chip_sw_all_escalation_resets.1581574519
Short name T207
Test name
Test status
Simulation time 5890921408 ps
CPU time 617.36 seconds
Started Aug 04 08:00:04 PM PDT 24
Finished Aug 04 08:10:22 PM PDT 24
Peak memory 619792 kb
Host smart-e7ad9002-c73c-4ee1-b86a-ac5c45a0f974
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1581574519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.1581574519
Directory /workspace/79.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1480211564
Short name T242
Test name
Test status
Simulation time 3150070559 ps
CPU time 350.69 seconds
Started Aug 04 07:39:56 PM PDT 24
Finished Aug 04 07:45:48 PM PDT 24
Peak memory 613052 kb
Host smart-2fa369e6-905c-4e01-b092-a39aeb1ec321
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480211564 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.1480211564
Directory /workspace/2.chip_sw_sysrst_ctrl_inputs/latest

Test location /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3100733597
Short name T214
Test name
Test status
Simulation time 43595931448 ps
CPU time 5038.36 seconds
Started Aug 04 07:36:24 PM PDT 24
Finished Aug 04 09:00:23 PM PDT 24
Peak memory 622948 kb
Host smart-802f6b66-91d9-4bbd-b161-f4c37aec1621
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_
rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3100733597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.3100733597
Directory /workspace/2.chip_sw_flash_rma_unlocked/latest

Test location /workspace/coverage/default/20.chip_sw_all_escalation_resets.3496768922
Short name T126
Test name
Test status
Simulation time 5090952680 ps
CPU time 782.98 seconds
Started Aug 04 07:54:02 PM PDT 24
Finished Aug 04 08:07:05 PM PDT 24
Peak memory 650872 kb
Host smart-e09ca6b3-fa70-4ca6-80a8-1b66655a0745
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3496768922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.3496768922
Directory /workspace/20.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1576391600
Short name T351
Test name
Test status
Simulation time 3073954520 ps
CPU time 306.87 seconds
Started Aug 04 07:52:49 PM PDT 24
Finished Aug 04 07:57:56 PM PDT 24
Peak memory 648912 kb
Host smart-ee7ea181-ffe4-4b99-bea6-00d65bfb533b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576391600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1576391600
Directory /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/75.chip_sw_all_escalation_resets.1911775280
Short name T144
Test name
Test status
Simulation time 5227288200 ps
CPU time 586.78 seconds
Started Aug 04 07:59:22 PM PDT 24
Finished Aug 04 08:09:09 PM PDT 24
Peak memory 650248 kb
Host smart-3b4c0739-60cf-4ce3-8240-0bb4a096d979
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1911775280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.1911775280
Directory /workspace/75.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1185865151
Short name T8
Test name
Test status
Simulation time 2284438848 ps
CPU time 213.96 seconds
Started Aug 04 07:36:40 PM PDT 24
Finished Aug 04 07:40:14 PM PDT 24
Peak memory 609944 kb
Host smart-81fa25b5-a1f8-4116-b15e-980b7bee474a
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185
865151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.1185865151
Directory /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest

Test location /workspace/coverage/default/4.chip_sw_data_integrity_escalation.504143099
Short name T260
Test name
Test status
Simulation time 5712441164 ps
CPU time 712.64 seconds
Started Aug 04 07:49:57 PM PDT 24
Finished Aug 04 08:01:50 PM PDT 24
Peak memory 611092 kb
Host smart-fffb7474-55c9-4cf0-aad5-37d707c6edf9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=504143099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.504143099
Directory /workspace/4.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/14.chip_sw_all_escalation_resets.2700741735
Short name T496
Test name
Test status
Simulation time 5891291346 ps
CPU time 643.02 seconds
Started Aug 04 07:52:23 PM PDT 24
Finished Aug 04 08:03:07 PM PDT 24
Peak memory 650476 kb
Host smart-f1c6d845-d2bb-4dc4-abee-5bc367099139
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2700741735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.2700741735
Directory /workspace/14.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/39.chip_sw_all_escalation_resets.3131042909
Short name T95
Test name
Test status
Simulation time 6065092872 ps
CPU time 538.88 seconds
Started Aug 04 07:55:37 PM PDT 24
Finished Aug 04 08:04:36 PM PDT 24
Peak memory 650200 kb
Host smart-039c5c60-78cc-437a-a7b6-c4413fb91f44
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3131042909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.3131042909
Directory /workspace/39.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/1.chip_sw_all_escalation_resets.2553149636
Short name T621
Test name
Test status
Simulation time 4789720328 ps
CPU time 681.84 seconds
Started Aug 04 07:22:01 PM PDT 24
Finished Aug 04 07:33:24 PM PDT 24
Peak memory 649864 kb
Host smart-7ab3dcbb-dfc7-40dc-9d10-5539bb9cc9ff
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2553149636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.2553149636
Directory /workspace/1.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/62.chip_sw_all_escalation_resets.790411554
Short name T143
Test name
Test status
Simulation time 4816911288 ps
CPU time 594.05 seconds
Started Aug 04 07:57:41 PM PDT 24
Finished Aug 04 08:07:35 PM PDT 24
Peak memory 650412 kb
Host smart-870deb88-da33-4e35-9173-b8095a4d3319
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
790411554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.790411554
Directory /workspace/62.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/37.chip_sw_all_escalation_resets.3539955759
Short name T450
Test name
Test status
Simulation time 5521470900 ps
CPU time 709.59 seconds
Started Aug 04 07:57:14 PM PDT 24
Finished Aug 04 08:09:04 PM PDT 24
Peak memory 650320 kb
Host smart-6fdcdf47-df72-4bff-a500-f2befafa87ef
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3539955759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.3539955759
Directory /workspace/37.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1446553672
Short name T317
Test name
Test status
Simulation time 3582665000 ps
CPU time 466.41 seconds
Started Aug 04 07:54:57 PM PDT 24
Finished Aug 04 08:02:43 PM PDT 24
Peak memory 650696 kb
Host smart-9bbe9f3a-5247-4c3b-b234-3527a0853d1a
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446553672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1446553672
Directory /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1038632170
Short name T449
Test name
Test status
Simulation time 3677029272 ps
CPU time 396.61 seconds
Started Aug 04 07:15:05 PM PDT 24
Finished Aug 04 07:21:41 PM PDT 24
Peak memory 649164 kb
Host smart-1edd3221-9b9e-4a35-b6db-33f3eb5ae12c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038632170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s
w_alert_handler_lpg_sleep_mode_alerts.1038632170
Directory /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/0.chip_sw_all_escalation_resets.1718102369
Short name T2
Test name
Test status
Simulation time 4281230752 ps
CPU time 563.93 seconds
Started Aug 04 07:12:52 PM PDT 24
Finished Aug 04 07:22:16 PM PDT 24
Peak memory 649868 kb
Host smart-994f0310-5365-43bc-84d1-3697c91f21fc
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1718102369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.1718102369
Directory /workspace/0.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3366787717
Short name T129
Test name
Test status
Simulation time 3578647932 ps
CPU time 426.88 seconds
Started Aug 04 07:29:12 PM PDT 24
Finished Aug 04 07:36:20 PM PDT 24
Peak memory 649656 kb
Host smart-299a761a-5f22-4bef-9d99-1ea54d655e69
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366787717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s
w_alert_handler_lpg_sleep_mode_alerts.3366787717
Directory /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/10.chip_sw_all_escalation_resets.1083244226
Short name T489
Test name
Test status
Simulation time 5639457356 ps
CPU time 719.14 seconds
Started Aug 04 07:52:19 PM PDT 24
Finished Aug 04 08:04:18 PM PDT 24
Peak memory 650372 kb
Host smart-6e5e2810-0f98-4a03-a373-4ee32d65d9ad
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1083244226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.1083244226
Directory /workspace/10.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3591242781
Short name T465
Test name
Test status
Simulation time 3373702874 ps
CPU time 380.22 seconds
Started Aug 04 07:52:19 PM PDT 24
Finished Aug 04 07:58:40 PM PDT 24
Peak memory 649468 kb
Host smart-4e24aed4-af2e-4922-b520-a8e0a60682d2
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591242781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3591242781
Directory /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/11.chip_sw_all_escalation_resets.4081454256
Short name T483
Test name
Test status
Simulation time 4645077256 ps
CPU time 777.97 seconds
Started Aug 04 07:52:14 PM PDT 24
Finished Aug 04 08:05:13 PM PDT 24
Peak memory 650376 kb
Host smart-b20c0a87-584d-4a3f-a44f-d766bc5abf2e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4081454256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.4081454256
Directory /workspace/11.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1013465311
Short name T411
Test name
Test status
Simulation time 3502197464 ps
CPU time 345.4 seconds
Started Aug 04 07:53:24 PM PDT 24
Finished Aug 04 07:59:10 PM PDT 24
Peak memory 648884 kb
Host smart-68d65c63-e2c2-48a2-a56c-07849dd92175
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013465311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1013465311
Directory /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/12.chip_sw_all_escalation_resets.4184940324
Short name T517
Test name
Test status
Simulation time 4974946648 ps
CPU time 725.15 seconds
Started Aug 04 07:51:48 PM PDT 24
Finished Aug 04 08:03:53 PM PDT 24
Peak memory 650164 kb
Host smart-162ecb2f-55d2-4977-a75f-676a4b431409
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4184940324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.4184940324
Directory /workspace/12.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3663418730
Short name T473
Test name
Test status
Simulation time 4251905158 ps
CPU time 455.43 seconds
Started Aug 04 07:52:35 PM PDT 24
Finished Aug 04 08:00:11 PM PDT 24
Peak memory 648956 kb
Host smart-914becaa-9552-4f54-b350-b5a2a2820d83
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663418730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3663418730
Directory /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/13.chip_sw_all_escalation_resets.418181410
Short name T459
Test name
Test status
Simulation time 5342871416 ps
CPU time 653.15 seconds
Started Aug 04 07:52:37 PM PDT 24
Finished Aug 04 08:03:31 PM PDT 24
Peak memory 650336 kb
Host smart-58b39579-b558-44d2-aa4b-145a539fe12b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
418181410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.418181410
Directory /workspace/13.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3798508375
Short name T416
Test name
Test status
Simulation time 3851088320 ps
CPU time 439.72 seconds
Started Aug 04 07:54:04 PM PDT 24
Finished Aug 04 08:01:24 PM PDT 24
Peak memory 649000 kb
Host smart-c090579b-c462-49ca-9319-a2451eee6d27
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798508375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3798508375
Directory /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2408170113
Short name T504
Test name
Test status
Simulation time 3763456488 ps
CPU time 406.75 seconds
Started Aug 04 07:53:10 PM PDT 24
Finished Aug 04 07:59:58 PM PDT 24
Peak memory 649084 kb
Host smart-d37a6d66-3128-4914-88f9-8e916992cedd
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408170113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2408170113
Directory /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/15.chip_sw_all_escalation_resets.2390722901
Short name T471
Test name
Test status
Simulation time 5353419416 ps
CPU time 609.07 seconds
Started Aug 04 07:54:02 PM PDT 24
Finished Aug 04 08:04:11 PM PDT 24
Peak memory 650308 kb
Host smart-87f4cbc2-b54b-4864-9990-d5504724398e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2390722901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.2390722901
Directory /workspace/15.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2728611738
Short name T492
Test name
Test status
Simulation time 3816362872 ps
CPU time 463.78 seconds
Started Aug 04 07:54:38 PM PDT 24
Finished Aug 04 08:02:22 PM PDT 24
Peak memory 649188 kb
Host smart-3bf4dc04-9256-43d5-b00c-95319b0c279f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728611738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2728611738
Directory /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3611344018
Short name T499
Test name
Test status
Simulation time 4220126946 ps
CPU time 374.08 seconds
Started Aug 04 07:53:59 PM PDT 24
Finished Aug 04 08:00:13 PM PDT 24
Peak memory 648784 kb
Host smart-a11f69f5-f77b-4046-b1dd-22b68c99da0f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611344018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3611344018
Directory /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/18.chip_sw_all_escalation_resets.2665085078
Short name T501
Test name
Test status
Simulation time 4876221424 ps
CPU time 641.88 seconds
Started Aug 04 07:53:12 PM PDT 24
Finished Aug 04 08:03:54 PM PDT 24
Peak memory 649936 kb
Host smart-87cbec35-b625-495e-9446-44646e78b3de
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2665085078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.2665085078
Directory /workspace/18.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/19.chip_sw_all_escalation_resets.879337448
Short name T466
Test name
Test status
Simulation time 5069308060 ps
CPU time 623.9 seconds
Started Aug 04 07:53:46 PM PDT 24
Finished Aug 04 08:04:11 PM PDT 24
Peak memory 650316 kb
Host smart-edeb5157-dd1d-40e9-87f5-84c3f4dc11ba
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
879337448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.879337448
Directory /workspace/19.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2257177447
Short name T454
Test name
Test status
Simulation time 3206049664 ps
CPU time 373.65 seconds
Started Aug 04 07:41:44 PM PDT 24
Finished Aug 04 07:47:57 PM PDT 24
Peak memory 648820 kb
Host smart-0c177706-104d-47f0-b299-836c77337ef4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257177447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s
w_alert_handler_lpg_sleep_mode_alerts.2257177447
Directory /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1282655884
Short name T463
Test name
Test status
Simulation time 3301940698 ps
CPU time 373.12 seconds
Started Aug 04 07:53:53 PM PDT 24
Finished Aug 04 08:00:06 PM PDT 24
Peak memory 649120 kb
Host smart-9ccdf781-08ab-4f7e-9227-33c0e0b6677e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282655884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1282655884
Directory /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1788210959
Short name T308
Test name
Test status
Simulation time 4144626968 ps
CPU time 354.76 seconds
Started Aug 04 07:53:14 PM PDT 24
Finished Aug 04 07:59:09 PM PDT 24
Peak memory 649084 kb
Host smart-c6e67b63-09f8-4cef-8c3e-d459b998aff5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788210959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1788210959
Directory /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3564325235
Short name T362
Test name
Test status
Simulation time 3142411848 ps
CPU time 336.38 seconds
Started Aug 04 07:53:48 PM PDT 24
Finished Aug 04 07:59:24 PM PDT 24
Peak memory 649064 kb
Host smart-6aa77132-2db2-47ed-84b6-7d6186916517
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564325235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3564325235
Directory /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/22.chip_sw_all_escalation_resets.1657209355
Short name T369
Test name
Test status
Simulation time 5845400680 ps
CPU time 570.46 seconds
Started Aug 04 07:54:13 PM PDT 24
Finished Aug 04 08:03:44 PM PDT 24
Peak memory 650060 kb
Host smart-d4e7a306-c440-4239-821d-242a4cfcc772
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1657209355 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.1657209355
Directory /workspace/22.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/23.chip_sw_all_escalation_resets.1325803081
Short name T365
Test name
Test status
Simulation time 4005486422 ps
CPU time 502.77 seconds
Started Aug 04 07:54:09 PM PDT 24
Finished Aug 04 08:02:32 PM PDT 24
Peak memory 649724 kb
Host smart-c1c293ae-cee2-44a1-b601-ed34e5cadab6
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1325803081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.1325803081
Directory /workspace/23.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/26.chip_sw_all_escalation_resets.238416414
Short name T279
Test name
Test status
Simulation time 5939682082 ps
CPU time 661.22 seconds
Started Aug 04 07:54:36 PM PDT 24
Finished Aug 04 08:05:38 PM PDT 24
Peak memory 650196 kb
Host smart-703f2054-3d44-45af-b503-911e2fbe4874
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
238416414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.238416414
Directory /workspace/26.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.754233516
Short name T142
Test name
Test status
Simulation time 4457950560 ps
CPU time 504.34 seconds
Started Aug 04 07:54:38 PM PDT 24
Finished Aug 04 08:03:02 PM PDT 24
Peak memory 649360 kb
Host smart-783b7b83-35c9-4b32-8039-1c43fe9d9067
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754233516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_s
w_alert_handler_lpg_sleep_mode_alerts.754233516
Directory /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/29.chip_sw_all_escalation_resets.3467393172
Short name T278
Test name
Test status
Simulation time 5202336560 ps
CPU time 568.96 seconds
Started Aug 04 07:54:18 PM PDT 24
Finished Aug 04 08:03:47 PM PDT 24
Peak memory 650264 kb
Host smart-5e58bb76-c870-408f-a822-1404d34f007e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3467393172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.3467393172
Directory /workspace/29.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.565784158
Short name T509
Test name
Test status
Simulation time 3647014830 ps
CPU time 452.53 seconds
Started Aug 04 07:49:47 PM PDT 24
Finished Aug 04 07:57:19 PM PDT 24
Peak memory 649248 kb
Host smart-65113e47-1536-4380-942b-2bf38961a194
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565784158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw
_alert_handler_lpg_sleep_mode_alerts.565784158
Directory /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/3.chip_sw_all_escalation_resets.3648423316
Short name T389
Test name
Test status
Simulation time 5432054998 ps
CPU time 713.51 seconds
Started Aug 04 07:50:04 PM PDT 24
Finished Aug 04 08:01:58 PM PDT 24
Peak memory 650380 kb
Host smart-7fab276d-e4dc-4d96-a750-2ec2d32c16fe
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3648423316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.3648423316
Directory /workspace/3.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/30.chip_sw_all_escalation_resets.3841192605
Short name T922
Test name
Test status
Simulation time 4657211704 ps
CPU time 555.85 seconds
Started Aug 04 07:54:16 PM PDT 24
Finished Aug 04 08:03:32 PM PDT 24
Peak memory 649968 kb
Host smart-3971ebb0-631a-4cae-9248-ee7a752e3d5d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3841192605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.3841192605
Directory /workspace/30.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2455434632
Short name T511
Test name
Test status
Simulation time 4510929688 ps
CPU time 505.59 seconds
Started Aug 04 07:54:30 PM PDT 24
Finished Aug 04 08:02:56 PM PDT 24
Peak memory 649528 kb
Host smart-588dab7f-f354-40c9-97b8-c6d7ce96304d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455434632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2455434632
Directory /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3426723777
Short name T456
Test name
Test status
Simulation time 3644018936 ps
CPU time 407.49 seconds
Started Aug 04 07:56:17 PM PDT 24
Finished Aug 04 08:03:05 PM PDT 24
Peak memory 648824 kb
Host smart-10729059-44f5-41c6-8eaf-e1436708fe9f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426723777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3426723777
Directory /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/35.chip_sw_all_escalation_resets.3055006983
Short name T444
Test name
Test status
Simulation time 5659078660 ps
CPU time 590.52 seconds
Started Aug 04 07:55:34 PM PDT 24
Finished Aug 04 08:05:24 PM PDT 24
Peak memory 650228 kb
Host smart-087bd564-a2e2-4630-b32c-12bfcf461c9a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3055006983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.3055006983
Directory /workspace/35.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3138408589
Short name T467
Test name
Test status
Simulation time 3924049352 ps
CPU time 404.43 seconds
Started Aug 04 07:55:15 PM PDT 24
Finished Aug 04 08:02:00 PM PDT 24
Peak memory 649176 kb
Host smart-06583704-6e49-4201-b4cf-7cf6a38ea49d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138408589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3138408589
Directory /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2316022514
Short name T498
Test name
Test status
Simulation time 3660779284 ps
CPU time 379.11 seconds
Started Aug 04 07:55:06 PM PDT 24
Finished Aug 04 08:01:25 PM PDT 24
Peak memory 649128 kb
Host smart-f864a33e-eb74-46c7-8987-de9f535479bd
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316022514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2316022514
Directory /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/38.chip_sw_all_escalation_resets.3826039707
Short name T513
Test name
Test status
Simulation time 4663999420 ps
CPU time 553.31 seconds
Started Aug 04 07:55:11 PM PDT 24
Finished Aug 04 08:04:25 PM PDT 24
Peak memory 649988 kb
Host smart-fc6c8eb9-1ad6-47a0-84ff-9182d00f6afa
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3826039707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.3826039707
Directory /workspace/38.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/4.chip_sw_all_escalation_resets.2773624177
Short name T475
Test name
Test status
Simulation time 6072880540 ps
CPU time 764.86 seconds
Started Aug 04 07:49:38 PM PDT 24
Finished Aug 04 08:02:24 PM PDT 24
Peak memory 650016 kb
Host smart-06a3da76-c0ba-4224-ba2c-d61be5c02ec3
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2773624177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.2773624177
Directory /workspace/4.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/40.chip_sw_all_escalation_resets.23351550
Short name T478
Test name
Test status
Simulation time 5139951544 ps
CPU time 668.14 seconds
Started Aug 04 07:57:54 PM PDT 24
Finished Aug 04 08:09:03 PM PDT 24
Peak memory 650056 kb
Host smart-45970015-5646-425d-a8cb-701c0e0bf29e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
23351550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.23351550
Directory /workspace/40.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1765219331
Short name T495
Test name
Test status
Simulation time 3163379778 ps
CPU time 413.32 seconds
Started Aug 04 07:57:04 PM PDT 24
Finished Aug 04 08:03:58 PM PDT 24
Peak memory 649092 kb
Host smart-9de85749-b24c-4daa-a7ec-72b5d406bf17
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765219331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1765219331
Directory /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1692737982
Short name T519
Test name
Test status
Simulation time 3844120616 ps
CPU time 351.7 seconds
Started Aug 04 07:57:01 PM PDT 24
Finished Aug 04 08:02:53 PM PDT 24
Peak memory 648972 kb
Host smart-faeae954-88b1-483c-a645-79179adfa471
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692737982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1692737982
Directory /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2090901197
Short name T895
Test name
Test status
Simulation time 3812959786 ps
CPU time 347.33 seconds
Started Aug 04 07:57:33 PM PDT 24
Finished Aug 04 08:03:21 PM PDT 24
Peak memory 649164 kb
Host smart-ef9c8886-31ce-44d3-a3dc-cf3f189d7593
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090901197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2090901197
Directory /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/49.chip_sw_all_escalation_resets.1105076371
Short name T390
Test name
Test status
Simulation time 6017782096 ps
CPU time 611.19 seconds
Started Aug 04 07:56:51 PM PDT 24
Finished Aug 04 08:07:03 PM PDT 24
Peak memory 650308 kb
Host smart-c6c97bd4-60cd-445b-ab48-30ca287b1726
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1105076371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.1105076371
Directory /workspace/49.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3889632380
Short name T468
Test name
Test status
Simulation time 3663935838 ps
CPU time 310.71 seconds
Started Aug 04 07:51:06 PM PDT 24
Finished Aug 04 07:56:17 PM PDT 24
Peak memory 649084 kb
Host smart-ea55a64a-f3fa-4bb9-913c-98a07d93d03a
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889632380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s
w_alert_handler_lpg_sleep_mode_alerts.3889632380
Directory /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/50.chip_sw_all_escalation_resets.1719210284
Short name T487
Test name
Test status
Simulation time 5718701464 ps
CPU time 544.91 seconds
Started Aug 04 07:56:17 PM PDT 24
Finished Aug 04 08:05:22 PM PDT 24
Peak memory 650348 kb
Host smart-e42bb844-079a-477d-84f9-53c58edaddf7
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1719210284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.1719210284
Directory /workspace/50.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/54.chip_sw_all_escalation_resets.2348297552
Short name T458
Test name
Test status
Simulation time 5804434674 ps
CPU time 615.84 seconds
Started Aug 04 07:58:26 PM PDT 24
Finished Aug 04 08:08:42 PM PDT 24
Peak memory 650008 kb
Host smart-04ca1450-173b-4271-a4b6-178d7f89d7f4
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2348297552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.2348297552
Directory /workspace/54.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.180052113
Short name T506
Test name
Test status
Simulation time 4184687034 ps
CPU time 447.6 seconds
Started Aug 04 07:57:21 PM PDT 24
Finished Aug 04 08:04:49 PM PDT 24
Peak memory 649252 kb
Host smart-8325ffdc-d910-42ce-9bf0-a8d26d82b6c4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180052113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_s
w_alert_handler_lpg_sleep_mode_alerts.180052113
Directory /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/55.chip_sw_all_escalation_resets.1195355372
Short name T485
Test name
Test status
Simulation time 4905899880 ps
CPU time 500.9 seconds
Started Aug 04 07:57:53 PM PDT 24
Finished Aug 04 08:06:14 PM PDT 24
Peak memory 650332 kb
Host smart-5bca0f3b-4bfd-44d2-a22d-3cbab8ce44e2
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1195355372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.1195355372
Directory /workspace/55.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3798564875
Short name T512
Test name
Test status
Simulation time 3408962200 ps
CPU time 379.62 seconds
Started Aug 04 07:59:18 PM PDT 24
Finished Aug 04 08:05:37 PM PDT 24
Peak memory 649248 kb
Host smart-e28f640e-4715-400b-9b3d-b5493ab4b2e1
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798564875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3798564875
Directory /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1353207841
Short name T291
Test name
Test status
Simulation time 4028927270 ps
CPU time 368.82 seconds
Started Aug 04 07:58:07 PM PDT 24
Finished Aug 04 08:04:16 PM PDT 24
Peak memory 649348 kb
Host smart-e4c3d7a6-f04b-4962-8d60-d2623062384e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353207841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1353207841
Directory /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1335109125
Short name T434
Test name
Test status
Simulation time 3882467268 ps
CPU time 527.23 seconds
Started Aug 04 07:58:51 PM PDT 24
Finished Aug 04 08:07:38 PM PDT 24
Peak memory 649064 kb
Host smart-7ffefd4c-701e-414a-8da7-586103af2c83
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335109125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1335109125
Directory /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1611693046
Short name T359
Test name
Test status
Simulation time 4233953464 ps
CPU time 541.99 seconds
Started Aug 04 08:00:06 PM PDT 24
Finished Aug 04 08:09:09 PM PDT 24
Peak memory 649076 kb
Host smart-098aef65-b8ea-4ea7-bfe5-a1da76f4bfe6
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611693046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1611693046
Directory /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.4220203339
Short name T474
Test name
Test status
Simulation time 3535068416 ps
CPU time 401.02 seconds
Started Aug 04 07:59:33 PM PDT 24
Finished Aug 04 08:06:14 PM PDT 24
Peak memory 649208 kb
Host smart-48d190d0-853c-47d3-aa51-1547a6799be6
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220203339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4220203339
Directory /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/70.chip_sw_all_escalation_resets.27579287
Short name T289
Test name
Test status
Simulation time 5464575880 ps
CPU time 538.31 seconds
Started Aug 04 07:58:51 PM PDT 24
Finished Aug 04 08:07:49 PM PDT 24
Peak memory 650260 kb
Host smart-88fab6f7-90d1-46eb-9ac9-77707e877d42
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
27579287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.27579287
Directory /workspace/70.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1554299922
Short name T497
Test name
Test status
Simulation time 3546995416 ps
CPU time 345.64 seconds
Started Aug 04 07:59:15 PM PDT 24
Finished Aug 04 08:05:01 PM PDT 24
Peak memory 649348 kb
Host smart-ec31363f-f891-47d6-83e3-ec5d0b3e1784
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554299922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1554299922
Directory /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/77.chip_sw_all_escalation_resets.3188747787
Short name T476
Test name
Test status
Simulation time 4855299772 ps
CPU time 706.36 seconds
Started Aug 04 08:00:19 PM PDT 24
Finished Aug 04 08:12:06 PM PDT 24
Peak memory 650132 kb
Host smart-81ae4c85-b2c0-4cf0-9d3a-09b396db602f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3188747787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.3188747787
Directory /workspace/77.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3753293791
Short name T350
Test name
Test status
Simulation time 3711235500 ps
CPU time 372.38 seconds
Started Aug 04 08:00:36 PM PDT 24
Finished Aug 04 08:06:48 PM PDT 24
Peak memory 648960 kb
Host smart-8bb2097a-2c59-44f8-82b1-92b20fe3322b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753293791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3753293791
Directory /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/80.chip_sw_all_escalation_resets.4047681832
Short name T494
Test name
Test status
Simulation time 4934226820 ps
CPU time 537.33 seconds
Started Aug 04 08:00:00 PM PDT 24
Finished Aug 04 08:08:57 PM PDT 24
Peak memory 650300 kb
Host smart-985446d6-676d-4e00-b9a2-a163e434daef
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4047681832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.4047681832
Directory /workspace/80.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2854141596
Short name T417
Test name
Test status
Simulation time 3520225200 ps
CPU time 476.05 seconds
Started Aug 04 08:00:30 PM PDT 24
Finished Aug 04 08:08:26 PM PDT 24
Peak memory 648728 kb
Host smart-28ea1cb8-2516-4c49-8cab-e51379844a8a
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854141596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2854141596
Directory /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/86.chip_sw_all_escalation_resets.4192310673
Short name T464
Test name
Test status
Simulation time 4239202730 ps
CPU time 561.04 seconds
Started Aug 04 08:01:24 PM PDT 24
Finished Aug 04 08:10:45 PM PDT 24
Peak memory 650196 kb
Host smart-b7ee7a44-bd0c-4b0d-8b4e-38eefd17e120
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4192310673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.4192310673
Directory /workspace/86.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/88.chip_sw_all_escalation_resets.1547044775
Short name T280
Test name
Test status
Simulation time 6445524672 ps
CPU time 596.23 seconds
Started Aug 04 08:00:39 PM PDT 24
Finished Aug 04 08:10:36 PM PDT 24
Peak memory 650208 kb
Host smart-8a99e9ee-4d62-4c69-9c8c-55939e56213a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1547044775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.1547044775
Directory /workspace/88.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/94.chip_sw_all_escalation_resets.2658064860
Short name T433
Test name
Test status
Simulation time 4690636820 ps
CPU time 493.97 seconds
Started Aug 04 08:00:41 PM PDT 24
Finished Aug 04 08:08:56 PM PDT 24
Peak memory 650064 kb
Host smart-558897d3-bc18-4541-b573-f7211b15c480
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2658064860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.2658064860
Directory /workspace/94.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/95.chip_sw_all_escalation_resets.1628375849
Short name T391
Test name
Test status
Simulation time 5260181216 ps
CPU time 568.5 seconds
Started Aug 04 08:02:02 PM PDT 24
Finished Aug 04 08:11:30 PM PDT 24
Peak memory 650220 kb
Host smart-b8b0a9d1-3a23-42a1-ab80-eb140eef80a5
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1628375849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.1628375849
Directory /workspace/95.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3587252444
Short name T252
Test name
Test status
Simulation time 3997045198 ps
CPU time 419.75 seconds
Started Aug 04 07:25:02 PM PDT 24
Finished Aug 04 07:32:02 PM PDT 24
Peak memory 610608 kb
Host smart-19d8019c-15a2-49a3-b134-657032443e72
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35
87252444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.3587252444
Directory /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest

Test location /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.4035671854
Short name T34
Test name
Test status
Simulation time 3713378520 ps
CPU time 268.36 seconds
Started Aug 04 07:37:02 PM PDT 24
Finished Aug 04 07:41:31 PM PDT 24
Peak memory 608996 kb
Host smart-07ea777f-e2b3-42f0-b1f1-b2b04807a363
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035671854 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.4035671854
Directory /workspace/2.chip_sw_spi_host_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.632787605
Short name T216
Test name
Test status
Simulation time 3222303063 ps
CPU time 246.77 seconds
Started Aug 04 07:13:54 PM PDT 24
Finished Aug 04 07:18:02 PM PDT 24
Peak memory 621292 kb
Host smart-d52802a8-b54e-4277-85d7-431ff5ca71eb
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63278760
5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.632787605
Directory /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1656592668
Short name T181
Test name
Test status
Simulation time 9222186275 ps
CPU time 752.68 seconds
Started Aug 04 07:15:38 PM PDT 24
Finished Aug 04 07:28:10 PM PDT 24
Peak memory 609484 kb
Host smart-70247bb9-774d-4996-80ce-b74e52e18c8a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656592668 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.1656592668
Directory /workspace/0.chip_sw_sram_ctrl_execution_main/latest

Test location /workspace/coverage/default/2.chip_sw_data_integrity_escalation.489656870
Short name T286
Test name
Test status
Simulation time 4489302408 ps
CPU time 669.78 seconds
Started Aug 04 07:36:26 PM PDT 24
Finished Aug 04 07:47:36 PM PDT 24
Peak memory 611024 kb
Host smart-c725c745-26dd-41b8-a801-e916edd3d8a7
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=489656870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.489656870
Directory /workspace/2.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/2.chip_plic_all_irqs_0.2195111523
Short name T188
Test name
Test status
Simulation time 6131289128 ps
CPU time 1191.82 seconds
Started Aug 04 07:43:31 PM PDT 24
Finished Aug 04 08:03:23 PM PDT 24
Peak memory 608884 kb
Host smart-755f73ac-41e1-4c36-b442-db6ecb88fd6d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195111523 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_plic_all_irqs_0.2195111523
Directory /workspace/2.chip_plic_all_irqs_0/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pin_wake.612660760
Short name T147
Test name
Test status
Simulation time 5683515376 ps
CPU time 478.2 seconds
Started Aug 04 07:35:28 PM PDT 24
Finished Aug 04 07:43:27 PM PDT 24
Peak memory 610864 kb
Host smart-9e362785-83e5-4069-a913-3a56e2203cbb
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612660760 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.612660760
Directory /workspace/2.chip_sw_sleep_pin_wake/latest

Test location /workspace/coverage/default/3.chip_tap_straps_rma.2094256716
Short name T116
Test name
Test status
Simulation time 3858356592 ps
CPU time 310.92 seconds
Started Aug 04 07:48:48 PM PDT 24
Finished Aug 04 07:53:59 PM PDT 24
Peak memory 633068 kb
Host smart-813ba227-4f59-43f4-9dbc-cdcaf161bd11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094256716 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.2094256716
Directory /workspace/3.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.982325706
Short name T257
Test name
Test status
Simulation time 4434560997 ps
CPU time 597.18 seconds
Started Aug 04 07:15:51 PM PDT 24
Finished Aug 04 07:25:48 PM PDT 24
Peak memory 610148 kb
Host smart-14a4708f-4cf8-4bf2-b970-b0520efc31b5
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=982325706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.982325706
Directory /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3811340188
Short name T81
Test name
Test status
Simulation time 7021313912 ps
CPU time 1107.47 seconds
Started Aug 04 07:43:27 PM PDT 24
Finished Aug 04 08:01:55 PM PDT 24
Peak memory 610508 kb
Host smart-c6dcff90-687b-4a78-a683-2e21b8044618
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38113401
88 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.3811340188
Directory /workspace/2.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2550399921
Short name T159
Test name
Test status
Simulation time 15652642872 ps
CPU time 1794.6 seconds
Started Aug 04 07:38:00 PM PDT 24
Finished Aug 04 08:07:55 PM PDT 24
Peak memory 610956 kb
Host smart-8903a7ce-f88b-48a4-b045-1481fb3a6c67
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=2550399921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.2550399921
Directory /workspace/2.chip_sw_rstmgr_alert_info/latest

Test location /workspace/coverage/default/2.chip_sw_gpio.512990613
Short name T26
Test name
Test status
Simulation time 3900108280 ps
CPU time 453.9 seconds
Started Aug 04 07:37:56 PM PDT 24
Finished Aug 04 07:45:30 PM PDT 24
Peak memory 609264 kb
Host smart-a742efa6-057a-4339-864b-891486b90c09
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512990613 -assert nopostproc +UVM_TESTNAME=chip_base
_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.chip_sw_gpio.512990613
Directory /workspace/2.chip_sw_gpio/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_pincfg.3984335554
Short name T20
Test name
Test status
Simulation time 31683455136 ps
CPU time 7587.82 seconds
Started Aug 04 07:13:07 PM PDT 24
Finished Aug 04 09:19:36 PM PDT 24
Peak memory 609252 kb
Host smart-036c572c-abce-4303-ad21-ac380e05ffa4
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=3984335554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.3984335554
Directory /workspace/0.chip_sw_usbdev_pincfg/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4175511927
Short name T38
Test name
Test status
Simulation time 6707414496 ps
CPU time 507.92 seconds
Started Aug 04 07:14:36 PM PDT 24
Finished Aug 04 07:23:04 PM PDT 24
Peak memory 610556 kb
Host smart-e7818840-c965-4e8f-8a22-8fcc17eec4b8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175511927 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4175511927
Directory /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1208031269
Short name T151
Test name
Test status
Simulation time 3778055060 ps
CPU time 372.69 seconds
Started Aug 04 07:16:16 PM PDT 24
Finished Aug 04 07:22:29 PM PDT 24
Peak memory 621368 kb
Host smart-52bfdb7a-7462-4aab-ab79-a477a808da34
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120803
1269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1208031269
Directory /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2157316270
Short name T15
Test name
Test status
Simulation time 78169487027 ps
CPU time 13236.5 seconds
Started Aug 04 07:35:18 PM PDT 24
Finished Aug 04 11:15:56 PM PDT 24
Peak memory 635044 kb
Host smart-a81ab471-84e7-4e0f-8858-e21049add2f6
User root
Command /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2157316270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.2157316270
Directory /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3901472577
Short name T46
Test name
Test status
Simulation time 14851465428 ps
CPU time 4094.21 seconds
Started Aug 04 07:25:01 PM PDT 24
Finished Aug 04 08:33:16 PM PDT 24
Peak memory 609960 kb
Host smart-d47e3c34-ebbe-41e5-8b14-468a833f6c80
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901472577 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3901472577
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pin_retention.720153376
Short name T109
Test name
Test status
Simulation time 4292588992 ps
CPU time 289.86 seconds
Started Aug 04 07:22:24 PM PDT 24
Finished Aug 04 07:27:14 PM PDT 24
Peak memory 608956 kb
Host smart-f6ad5e77-ff5e-4a3b-bd09-9dc512bb4bdf
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720153376 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.720153376
Directory /workspace/1.chip_sw_sleep_pin_retention/latest

Test location /workspace/coverage/default/1.chip_plic_all_irqs_20.3057434156
Short name T191
Test name
Test status
Simulation time 4012992654 ps
CPU time 761.94 seconds
Started Aug 04 07:30:39 PM PDT 24
Finished Aug 04 07:43:21 PM PDT 24
Peak memory 608576 kb
Host smart-3518862e-680d-4199-98f9-01819693623a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057434156 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.chip_plic_all_irqs_20.3057434156
Directory /workspace/1.chip_plic_all_irqs_20/latest

Test location /workspace/coverage/default/21.chip_sw_all_escalation_resets.1629740174
Short name T397
Test name
Test status
Simulation time 4663326560 ps
CPU time 693.08 seconds
Started Aug 04 07:54:19 PM PDT 24
Finished Aug 04 08:05:52 PM PDT 24
Peak memory 610804 kb
Host smart-c701f4f8-e0e0-4f86-bd5c-42dd54bd25bd
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1629740174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.1629740174
Directory /workspace/21.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3013127631
Short name T68
Test name
Test status
Simulation time 4050090906 ps
CPU time 454.41 seconds
Started Aug 04 07:17:01 PM PDT 24
Finished Aug 04 07:24:36 PM PDT 24
Peak memory 612908 kb
Host smart-58ce98a9-3b14-4fc8-b00d-55ba66c99f9c
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013127631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_dev.3013127631
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.649275564
Short name T77
Test name
Test status
Simulation time 25006103276 ps
CPU time 3815.76 seconds
Started Aug 04 07:33:07 PM PDT 24
Finished Aug 04 08:36:44 PM PDT 24
Peak memory 611176 kb
Host smart-f515ae7b-54f4-42d2-9203-e4aa71b41baa
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649275564 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.649275564
Directory /workspace/1.chip_sw_ast_clk_rst_inputs/latest

Test location /workspace/coverage/default/0.chip_jtag_mem_access.4126876066
Short name T53
Test name
Test status
Simulation time 13305945404 ps
CPU time 1434.53 seconds
Started Aug 04 07:08:47 PM PDT 24
Finished Aug 04 07:32:42 PM PDT 24
Peak memory 607912 kb
Host smart-0f521c49-8de4-423c-9a84-abb1c3b9ca58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126876066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_
mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.4
126876066
Directory /workspace/0.chip_jtag_mem_access/latest

Test location /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.102381688
Short name T86
Test name
Test status
Simulation time 9450853786 ps
CPU time 1097.55 seconds
Started Aug 04 07:15:36 PM PDT 24
Finished Aug 04 07:33:54 PM PDT 24
Peak memory 610196 kb
Host smart-f812cd4c-d3d5-4b31-a316-bc824daf8a3c
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10238168
8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.102381688
Directory /workspace/0.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2670850319
Short name T531
Test name
Test status
Simulation time 11291124025 ps
CPU time 891.42 seconds
Started Aug 04 07:17:21 PM PDT 24
Finished Aug 04 07:32:14 PM PDT 24
Peak memory 620496 kb
Host smart-f6b0805f-e1ce-4563-8472-7f7169c6d5ce
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=2670850319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.2670850319
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1812927884
Short name T724
Test name
Test status
Simulation time 43825874135 ps
CPU time 4976.3 seconds
Started Aug 04 07:14:22 PM PDT 24
Finished Aug 04 08:37:20 PM PDT 24
Peak memory 621940 kb
Host smart-e052fc74-2369-416f-94c2-071953f496dc
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_
rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1812927884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.1812927884
Directory /workspace/0.chip_sw_flash_rma_unlocked/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1407528743
Short name T675
Test name
Test status
Simulation time 77578788480 ps
CPU time 14373.4 seconds
Started Aug 04 07:14:18 PM PDT 24
Finished Aug 04 11:13:53 PM PDT 24
Peak memory 635088 kb
Host smart-17ece66c-a886-49d5-94cf-8764d4656586
User root
Command /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1407528743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.1407528743
Directory /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest

Test location /workspace/coverage/default/2.chip_plic_all_irqs_20.3393904439
Short name T192
Test name
Test status
Simulation time 4173713560 ps
CPU time 860.99 seconds
Started Aug 04 07:44:11 PM PDT 24
Finished Aug 04 07:58:32 PM PDT 24
Peak memory 609716 kb
Host smart-1e1b0ccc-0a07-4072-9966-f9cb71f583ad
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393904439 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.chip_plic_all_irqs_20.3393904439
Directory /workspace/2.chip_plic_all_irqs_20/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_tpm.2052638164
Short name T40
Test name
Test status
Simulation time 3971083639 ps
CPU time 388.01 seconds
Started Aug 04 07:15:18 PM PDT 24
Finished Aug 04 07:21:47 PM PDT 24
Peak memory 619540 kb
Host smart-e192bb7d-b75b-4404-9c1a-ee86e91baed8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052638164 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.2052638164
Directory /workspace/0.chip_sw_spi_device_tpm/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1320534471
Short name T202
Test name
Test status
Simulation time 2686119126 ps
CPU time 277.01 seconds
Started Aug 04 07:36:54 PM PDT 24
Finished Aug 04 07:41:32 PM PDT 24
Peak memory 622596 kb
Host smart-f53e1644-d83b-4f96-9ae6-742228b5d89e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320534471 -assert nopost
proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.1320534471
Directory /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location /workspace/coverage/default/0.chip_plic_all_irqs_0.1801148548
Short name T189
Test name
Test status
Simulation time 6381472520 ps
CPU time 1229.17 seconds
Started Aug 04 07:15:45 PM PDT 24
Finished Aug 04 07:36:15 PM PDT 24
Peak memory 610132 kb
Host smart-34c90345-bcac-4932-9b27-5d9acfca0104
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801148548 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_plic_all_irqs_0.1801148548
Directory /workspace/0.chip_plic_all_irqs_0/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx.2842569389
Short name T348
Test name
Test status
Simulation time 4453051742 ps
CPU time 669.04 seconds
Started Aug 04 07:13:39 PM PDT 24
Finished Aug 04 07:24:49 PM PDT 24
Peak memory 624248 kb
Host smart-fcb7ab90-14fb-474d-986d-507a716847ae
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842569389 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.2842569389
Directory /workspace/0.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3725381044
Short name T869
Test name
Test status
Simulation time 7794549640 ps
CPU time 1768.79 seconds
Started Aug 04 07:13:46 PM PDT 24
Finished Aug 04 07:43:16 PM PDT 24
Peak memory 624504 kb
Host smart-72721a35-cb9d-40b4-9855-33225959156f
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3725381044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.3725381044
Directory /workspace/0.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.965712707
Short name T247
Test name
Test status
Simulation time 25581406124 ps
CPU time 1944.68 seconds
Started Aug 04 07:16:58 PM PDT 24
Finished Aug 04 07:49:23 PM PDT 24
Peak memory 613532 kb
Host smart-ad28a27d-b6f4-40d5-af84-525d3bafc0db
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=965712707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.965712707
Directory /workspace/0.chip_sw_flash_init_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1153198464
Short name T936
Test name
Test status
Simulation time 44769958433 ps
CPU time 5305.79 seconds
Started Aug 04 07:25:57 PM PDT 24
Finished Aug 04 08:54:24 PM PDT 24
Peak memory 622872 kb
Host smart-bfd2306e-a3d2-431c-8859-0ff3833c622d
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_
rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1153198464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.1153198464
Directory /workspace/1.chip_sw_flash_rma_unlocked/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3348405141
Short name T123
Test name
Test status
Simulation time 3951288632 ps
CPU time 418.97 seconds
Started Aug 04 07:13:27 PM PDT 24
Finished Aug 04 07:20:26 PM PDT 24
Peak memory 608536 kb
Host smart-5100ed54-bf2b-4189-baf6-281fd820f8eb
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334840
5141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3348405141
Directory /workspace/0.chip_sw_usbdev_aon_pullup/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2083080114
Short name T274
Test name
Test status
Simulation time 7586164580 ps
CPU time 1009.25 seconds
Started Aug 04 07:39:05 PM PDT 24
Finished Aug 04 07:55:55 PM PDT 24
Peak memory 610852 kb
Host smart-3d739f28-0d67-4a7e-9747-a660709615ff
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083080114 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.2083080114
Directory /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_app_rom.1200771673
Short name T155
Test name
Test status
Simulation time 2582150856 ps
CPU time 181.62 seconds
Started Aug 04 07:17:07 PM PDT 24
Finished Aug 04 07:20:09 PM PDT 24
Peak memory 609676 kb
Host smart-49ffa484-9273-42ef-bac2-a79080118184
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200771673 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_kmac_app_rom.1200771673
Directory /workspace/0.chip_sw_kmac_app_rom/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2283572063
Short name T220
Test name
Test status
Simulation time 4065988984 ps
CPU time 548.94 seconds
Started Aug 04 07:15:08 PM PDT 24
Finished Aug 04 07:24:17 PM PDT 24
Peak memory 610704 kb
Host smart-2c3ff078-c092-4766-ad44-f1cf544fcdd9
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283572063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr
l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw
_sram_ctrl_scrambled_access.2283572063
Directory /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest

Test location /workspace/coverage/default/0.chip_plic_all_irqs_10.3045931235
Short name T104
Test name
Test status
Simulation time 3863529128 ps
CPU time 422.2 seconds
Started Aug 04 07:17:09 PM PDT 24
Finished Aug 04 07:24:11 PM PDT 24
Peak memory 609832 kb
Host smart-bcf198cb-eaf6-4833-b8bc-fa1b5701a949
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045931235 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.chip_plic_all_irqs_10.3045931235
Directory /workspace/0.chip_plic_all_irqs_10/latest

Test location /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4286083646
Short name T420
Test name
Test status
Simulation time 4819656018 ps
CPU time 459.56 seconds
Started Aug 04 07:17:37 PM PDT 24
Finished Aug 04 07:25:17 PM PDT 24
Peak memory 624396 kb
Host smart-c648ee74-12c4-4462-8366-ffb1e0e96949
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286083646 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.4286083646
Directory /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location /workspace/coverage/default/0.chip_sw_power_sleep_load.1589897727
Short name T270
Test name
Test status
Simulation time 3826262232 ps
CPU time 313.5 seconds
Started Aug 04 07:16:16 PM PDT 24
Finished Aug 04 07:21:30 PM PDT 24
Peak memory 610132 kb
Host smart-4c9893c7-e9d7-4220-8895-accee9e0dfca
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589897727 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.1589897727
Directory /workspace/0.chip_sw_power_sleep_load/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3574532173
Short name T200
Test name
Test status
Simulation time 2567045241 ps
CPU time 202.09 seconds
Started Aug 04 07:24:43 PM PDT 24
Finished Aug 04 07:28:05 PM PDT 24
Peak memory 623940 kb
Host smart-3ce1f981-3bd8-4226-93eb-178dd5eb1ee1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574532173 -assert nopost
proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.3574532173
Directory /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location /workspace/coverage/default/0.chip_sw_edn_boot_mode.3294143354
Short name T185
Test name
Test status
Simulation time 3391475854 ps
CPU time 563.56 seconds
Started Aug 04 07:14:38 PM PDT 24
Finished Aug 04 07:24:02 PM PDT 24
Peak memory 610036 kb
Host smart-011ff4b7-e1bd-4014-9b9c-2eaefd930156
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294143354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_
boot_mode.3294143354
Directory /workspace/0.chip_sw_edn_boot_mode/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1088464296
Short name T139
Test name
Test status
Simulation time 25060107568 ps
CPU time 1914 seconds
Started Aug 04 07:16:35 PM PDT 24
Finished Aug 04 07:48:29 PM PDT 24
Peak memory 611092 kb
Host smart-6f1f2976-4a5d-4449-876a-599c04e3c3e1
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1088464296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1088464296
Directory /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/1.chip_plic_all_irqs_10.3138350441
Short name T102
Test name
Test status
Simulation time 4735118408 ps
CPU time 682.2 seconds
Started Aug 04 07:31:13 PM PDT 24
Finished Aug 04 07:42:36 PM PDT 24
Peak memory 608844 kb
Host smart-756f8dae-0d8a-4e6e-b6da-4d087eda3b30
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138350441 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.chip_plic_all_irqs_10.3138350441
Directory /workspace/1.chip_plic_all_irqs_10/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3995343993
Short name T184
Test name
Test status
Simulation time 5202837944 ps
CPU time 457.88 seconds
Started Aug 04 07:16:49 PM PDT 24
Finished Aug 04 07:24:27 PM PDT 24
Peak memory 610292 kb
Host smart-d8ec1b13-0990-4d2d-bd83-b7485e2b5354
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul
es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3995343993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s
leep_wake_up.3995343993
Directory /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.770211619
Short name T382
Test name
Test status
Simulation time 4217514220 ps
CPU time 607.02 seconds
Started Aug 04 07:23:47 PM PDT 24
Finished Aug 04 07:33:54 PM PDT 24
Peak memory 609900 kb
Host smart-2c490a7a-37ec-4e89-8c83-22c63299196d
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=770211619 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.770211619
Directory /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_gpio.1523681266
Short name T28
Test name
Test status
Simulation time 3850443613 ps
CPU time 438.13 seconds
Started Aug 04 07:24:39 PM PDT 24
Finished Aug 04 07:31:57 PM PDT 24
Peak memory 609308 kb
Host smart-4b54b119-a83f-435a-a33a-3f3a1306dbf8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523681266 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.chip_sw_gpio.1523681266
Directory /workspace/1.chip_sw_gpio/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2920711643
Short name T380
Test name
Test status
Simulation time 4669296432 ps
CPU time 471.39 seconds
Started Aug 04 07:31:23 PM PDT 24
Finished Aug 04 07:39:15 PM PDT 24
Peak memory 609864 kb
Host smart-9aabd8f7-cde5-4ac1-ab6e-cc741b7b3307
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920711643 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.2920711643
Directory /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest

Test location /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2097497774
Short name T856
Test name
Test status
Simulation time 19126117702 ps
CPU time 617.07 seconds
Started Aug 04 07:14:35 PM PDT 24
Finished Aug 04 07:24:52 PM PDT 24
Peak memory 619692 kb
Host smart-6ce5d970-06e6-43cd-b813-9630cc9ca646
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2097497774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2097497774
Directory /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location /workspace/coverage/default/0.chip_sw_flash_init.1155879664
Short name T253
Test name
Test status
Simulation time 24232010261 ps
CPU time 2059.79 seconds
Started Aug 04 07:15:16 PM PDT 24
Finished Aug 04 07:49:38 PM PDT 24
Peak memory 612664 kb
Host smart-beb8542c-0620-4712-b1c6-9b219b4410d1
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155879664 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.1155879664
Directory /workspace/0.chip_sw_flash_init/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3226454316
Short name T58
Test name
Test status
Simulation time 9222133246 ps
CPU time 348.02 seconds
Started Aug 04 07:14:31 PM PDT 24
Finished Aug 04 07:20:19 PM PDT 24
Peak memory 610844 kb
Host smart-bed39f7f-cd65-4312-8991-c12c9dce2f9d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226454316 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.3226454316
Directory /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest

Test location /workspace/coverage/default/1.chip_sw_ast_clk_outputs.3644665539
Short name T552
Test name
Test status
Simulation time 8636779740 ps
CPU time 1094.38 seconds
Started Aug 04 07:32:37 PM PDT 24
Finished Aug 04 07:50:52 PM PDT 24
Peak memory 617352 kb
Host smart-047c94b8-5bb8-482b-869f-dc4aea540a6b
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644665539 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.3644665539
Directory /workspace/1.chip_sw_ast_clk_outputs/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1119822589
Short name T405
Test name
Test status
Simulation time 10998766100 ps
CPU time 2907.8 seconds
Started Aug 04 07:21:43 PM PDT 24
Finished Aug 04 08:10:12 PM PDT 24
Peak memory 610016 kb
Host smart-36c919f1-6976-4bd0-b2bf-4e689191beeb
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1119822589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1119822589
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_tap_straps_dev.1932411994
Short name T121
Test name
Test status
Simulation time 7210199885 ps
CPU time 744.04 seconds
Started Aug 04 07:31:58 PM PDT 24
Finished Aug 04 07:44:22 PM PDT 24
Peak memory 632728 kb
Host smart-afe14957-20c5-4102-b4fd-d686ee72d647
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1932411994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.1932411994
Directory /workspace/1.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_csrng.1672116891
Short name T375
Test name
Test status
Simulation time 6495375590 ps
CPU time 1157.47 seconds
Started Aug 04 07:15:03 PM PDT 24
Finished Aug 04 07:34:21 PM PDT 24
Peak memory 610076 kb
Host smart-c7956bcf-b20f-4501-b71f-3e1caa2e50bc
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_
csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1672116891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.1672116891
Directory /workspace/0.chip_sw_entropy_src_csrng/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.203845627
Short name T367
Test name
Test status
Simulation time 4776195880 ps
CPU time 899 seconds
Started Aug 04 07:15:44 PM PDT 24
Finished Aug 04 07:30:44 PM PDT 24
Peak memory 610192 kb
Host smart-895a2c57-c957-4410-b551-3e8ebb06b0fa
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20384
5627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.203845627
Directory /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2049474400
Short name T372
Test name
Test status
Simulation time 5021950013 ps
CPU time 408.94 seconds
Started Aug 04 07:13:24 PM PDT 24
Finished Aug 04 07:20:13 PM PDT 24
Peak memory 619020 kb
Host smart-488c06c6-6355-467c-b258-4ed29e6242e1
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049474400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.2049474400
Directory /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.866092070
Short name T232
Test name
Test status
Simulation time 5252672034 ps
CPU time 850.91 seconds
Started Aug 04 07:25:04 PM PDT 24
Finished Aug 04 07:39:15 PM PDT 24
Peak memory 610220 kb
Host smart-929ad76c-7b11-4bd4-ad20-ecb668a6670d
User root
Command /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866092070 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.866092070
Directory /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2571193348
Short name T44
Test name
Test status
Simulation time 3809528651 ps
CPU time 551.8 seconds
Started Aug 04 07:14:42 PM PDT 24
Finished Aug 04 07:23:54 PM PDT 24
Peak memory 624844 kb
Host smart-5e36cb69-9911-4c0d-984e-4b5a1c89faca
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571193348 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.2571193348
Directory /workspace/0.chip_sw_spi_device_pass_through_collision/latest

Test location /workspace/coverage/default/0.rom_raw_unlock.2015289278
Short name T328
Test name
Test status
Simulation time 5690490184 ps
CPU time 261.32 seconds
Started Aug 04 07:21:47 PM PDT 24
Finished Aug 04 07:26:08 PM PDT 24
Peak memory 619820 kb
Host smart-56def676-5a86-4c70-9fee-467041e1df63
User root
Command /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE
xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2015289278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.2015289278
Directory /workspace/0.rom_raw_unlock/latest

Test location /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3474491393
Short name T145
Test name
Test status
Simulation time 4898097096 ps
CPU time 328.64 seconds
Started Aug 04 07:15:54 PM PDT 24
Finished Aug 04 07:21:23 PM PDT 24
Peak memory 619668 kb
Host smart-204df04a-b48c-4f6c-bd79-be3627b88f9c
User root
Command /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3
474491393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.3474491393
Directory /workspace/0.chip_rv_dm_ndm_reset_req/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3766629717
Short name T667
Test name
Test status
Simulation time 7355817832 ps
CPU time 455.51 seconds
Started Aug 04 07:14:27 PM PDT 24
Finished Aug 04 07:22:02 PM PDT 24
Peak memory 610488 kb
Host smart-1a25eda7-859b-4999-9b88-61ec35276389
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3766629717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3766629717
Directory /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.276585703
Short name T76
Test name
Test status
Simulation time 120930561736 ps
CPU time 16782.1 seconds
Started Aug 04 07:19:00 PM PDT 24
Finished Aug 04 11:58:44 PM PDT 24
Peak memory 610456 kb
Host smart-e05dd927-7186-4487-9ee4-8ba778172bd5
User root
Command /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_
cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=276585703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.276585703
Directory /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.854188635
Short name T211
Test name
Test status
Simulation time 4752015800 ps
CPU time 504.11 seconds
Started Aug 04 07:14:59 PM PDT 24
Finished Aug 04 07:23:23 PM PDT 24
Peak memory 611084 kb
Host smart-b5c60d27-10c5-44ad-a3f7-2eba9d8bddf0
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=854188635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.854188635
Directory /workspace/0.chip_sw_lc_ctrl_program_error/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3729832923
Short name T201
Test name
Test status
Simulation time 3012858923 ps
CPU time 257.94 seconds
Started Aug 04 07:14:11 PM PDT 24
Finished Aug 04 07:18:29 PM PDT 24
Peak memory 622596 kb
Host smart-5646d763-7566-405a-bc14-a170a7640f47
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729832923 -assert nopost
proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.3729832923
Directory /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3922422592
Short name T797
Test name
Test status
Simulation time 4576537046 ps
CPU time 381.13 seconds
Started Aug 04 07:16:27 PM PDT 24
Finished Aug 04 07:22:48 PM PDT 24
Peak memory 616360 kb
Host smart-9928e26a-ccfb-437c-af10-45aadd9ddc3f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3922422592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.3922422592
Directory /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2458463673
Short name T885
Test name
Test status
Simulation time 5894925100 ps
CPU time 442.57 seconds
Started Aug 04 07:50:41 PM PDT 24
Finished Aug 04 07:58:03 PM PDT 24
Peak memory 610556 kb
Host smart-beecf0fc-30df-43a9-9d62-39e209270e1a
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2458463673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2458463673
Directory /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/0.chip_sw_gpio.1298795331
Short name T27
Test name
Test status
Simulation time 4158427200 ps
CPU time 425.84 seconds
Started Aug 04 07:14:00 PM PDT 24
Finished Aug 04 07:21:06 PM PDT 24
Peak memory 610280 kb
Host smart-581e1552-9fa1-4180-b3b2-03d9d488e07f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298795331 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.chip_sw_gpio.1298795331
Directory /workspace/0.chip_sw_gpio/latest

Test location /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2831222080
Short name T33
Test name
Test status
Simulation time 5019085273 ps
CPU time 218.03 seconds
Started Aug 04 07:06:20 PM PDT 24
Finished Aug 04 07:09:58 PM PDT 24
Peak memory 641008 kb
Host smart-01990587-4ac4-4eb3-90c0-803881572c01
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831222080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 1.chip_padctrl_attributes.2831222080
Directory /workspace/1.chip_padctrl_attributes/latest

Test location /workspace/coverage/default/0.chip_tap_straps_rma.2649074299
Short name T90
Test name
Test status
Simulation time 7402384796 ps
CPU time 721.41 seconds
Started Aug 04 07:16:10 PM PDT 24
Finished Aug 04 07:28:12 PM PDT 24
Peak memory 633112 kb
Host smart-302052ab-4d20-40ad-b846-a1dc7c4ddc34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649074299 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.2649074299
Directory /workspace/0.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2060847507
Short name T341
Test name
Test status
Simulation time 10148029600 ps
CPU time 3235.98 seconds
Started Aug 04 07:16:49 PM PDT 24
Finished Aug 04 08:10:45 PM PDT 24
Peak memory 610864 kb
Host smart-e0d29489-47ef-44c3-b63a-482c71e7b2dd
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20608
47507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2060847507
Directory /workspace/0.chip_sw_keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.570082079
Short name T815
Test name
Test status
Simulation time 17487893992 ps
CPU time 3852.06 seconds
Started Aug 04 07:16:50 PM PDT 24
Finished Aug 04 08:21:03 PM PDT 24
Peak memory 610084 kb
Host smart-6eb2b3c6-d36c-46bd-8e78-3724eafbf7be
User root
Command /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_
rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=570082079 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.570082079
Directory /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2933214722
Short name T804
Test name
Test status
Simulation time 7860640706 ps
CPU time 766.68 seconds
Started Aug 04 07:16:00 PM PDT 24
Finished Aug 04 07:28:47 PM PDT 24
Peak memory 610632 kb
Host smart-0e67b60b-e785-4048-b44c-56774fad8e75
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933214722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep
_sram_ret_contents_scramble.2933214722
Directory /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1890598971
Short name T921
Test name
Test status
Simulation time 3573797320 ps
CPU time 385.34 seconds
Started Aug 04 07:16:35 PM PDT 24
Finished Aug 04 07:23:01 PM PDT 24
Peak memory 610024 kb
Host smart-d76897c5-9d07-4aaa-9edd-8bc30ee1030b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890598971 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.1890598971
Directory /workspace/0.chip_sw_sysrst_ctrl_outputs/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1965015088
Short name T810
Test name
Test status
Simulation time 23999548250 ps
CPU time 6090.8 seconds
Started Aug 04 07:24:46 PM PDT 24
Finished Aug 04 09:06:17 PM PDT 24
Peak memory 610184 kb
Host smart-e0a796a4-b028-4b71-8483-092fa72eab5b
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1965015088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1965015088
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.3369353042
Short name T178
Test name
Test status
Simulation time 10246040521 ps
CPU time 2502.15 seconds
Started Aug 04 07:20:49 PM PDT 24
Finished Aug 04 08:02:33 PM PDT 24
Peak memory 624524 kb
Host smart-13bb7275-899d-4ce6-9728-0bd7f6f62ffb
User root
Command /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33693
53042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.3369353042
Directory /workspace/0.rom_e2e_jtag_debug_rma/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.598974442
Short name T404
Test name
Test status
Simulation time 2098540576 ps
CPU time 203.94 seconds
Started Aug 04 07:32:46 PM PDT 24
Finished Aug 04 07:36:10 PM PDT 24
Peak memory 617016 kb
Host smart-eb806dad-f6aa-40a2-b2c0-54dcb18470c8
User root
Command /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598974442 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.598974442
Directory /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.950715686
Short name T226
Test name
Test status
Simulation time 4260593106 ps
CPU time 654.64 seconds
Started Aug 04 07:15:26 PM PDT 24
Finished Aug 04 07:26:21 PM PDT 24
Peak memory 609436 kb
Host smart-32139392-de0f-4acd-b8f4-165cc21701b0
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95071
5686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.950715686
Directory /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location /workspace/coverage/default/0.chip_sival_flash_info_access.1573041624
Short name T256
Test name
Test status
Simulation time 2787346500 ps
CPU time 278.9 seconds
Started Aug 04 07:14:17 PM PDT 24
Finished Aug 04 07:18:56 PM PDT 24
Peak memory 609952 kb
Host smart-0d547c33-993a-4c3a-94ba-fd88af8c891e
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=1573041624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.1573041624
Directory /workspace/0.chip_sival_flash_info_access/latest

Test location /workspace/coverage/default/0.chip_sw_aes_enc.44646296
Short name T1019
Test name
Test status
Simulation time 2960031726 ps
CPU time 235.94 seconds
Started Aug 04 07:14:58 PM PDT 24
Finished Aug 04 07:18:54 PM PDT 24
Peak memory 609488 kb
Host smart-9cecb088-dd5a-4f2f-b641-2cd49f5e0610
User root
Command /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44646296 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.44646296
Directory /workspace/0.chip_sw_aes_enc/latest

Test location /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1212780923
Short name T1026
Test name
Test status
Simulation time 3128251823 ps
CPU time 265.91 seconds
Started Aug 04 07:17:32 PM PDT 24
Finished Aug 04 07:21:58 PM PDT 24
Peak memory 609740 kb
Host smart-5c324b68-bb4d-4baf-a464-0499bd1a1b75
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212
780923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.1212780923
Directory /workspace/0.chip_sw_aes_enc_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3098295951
Short name T64
Test name
Test status
Simulation time 2848250482 ps
CPU time 277.22 seconds
Started Aug 04 07:17:42 PM PDT 24
Finished Aug 04 07:22:19 PM PDT 24
Peak memory 609548 kb
Host smart-a59b20e0-810c-4796-b7c3-9ec1d0a91283
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3098295951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.3098295951
Directory /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_aes_entropy.2399724772
Short name T630
Test name
Test status
Simulation time 2304638694 ps
CPU time 184.58 seconds
Started Aug 04 07:15:24 PM PDT 24
Finished Aug 04 07:18:29 PM PDT 24
Peak memory 609660 kb
Host smart-5a25e8f0-10cb-4040-93b4-19414566d72f
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399724772 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.2399724772
Directory /workspace/0.chip_sw_aes_entropy/latest

Test location /workspace/coverage/default/0.chip_sw_aes_idle.4200599791
Short name T1025
Test name
Test status
Simulation time 3306487386 ps
CPU time 232.44 seconds
Started Aug 04 07:17:28 PM PDT 24
Finished Aug 04 07:21:20 PM PDT 24
Peak memory 609276 kb
Host smart-c7af1821-0214-4aa1-91a6-ac6a8c551525
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200599791 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.4200599791
Directory /workspace/0.chip_sw_aes_idle/latest

Test location /workspace/coverage/default/0.chip_sw_aes_masking_off.95380566
Short name T1023
Test name
Test status
Simulation time 3448581170 ps
CPU time 307.02 seconds
Started Aug 04 07:16:33 PM PDT 24
Finished Aug 04 07:21:40 PM PDT 24
Peak memory 610536 kb
Host smart-e329b6a0-8b32-41ae-b0e9-29f34ea2c51d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95380566 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.95380566
Directory /workspace/0.chip_sw_aes_masking_off/latest

Test location /workspace/coverage/default/0.chip_sw_aes_smoketest.2394746523
Short name T580
Test name
Test status
Simulation time 2694586108 ps
CPU time 260.12 seconds
Started Aug 04 07:19:11 PM PDT 24
Finished Aug 04 07:23:31 PM PDT 24
Peak memory 608480 kb
Host smart-2168d413-1aed-4710-a4f7-0518cbbfc712
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394746523 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_aes_smoketest.2394746523
Directory /workspace/0.chip_sw_aes_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3560239110
Short name T124
Test name
Test status
Simulation time 3760871053 ps
CPU time 374.78 seconds
Started Aug 04 07:14:17 PM PDT 24
Finished Aug 04 07:20:32 PM PDT 24
Peak memory 609780 kb
Host smart-9ea36979-b14f-4ece-b628-ca98d24738fc
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3560239110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.3560239110
Directory /workspace/0.chip_sw_alert_handler_entropy/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_escalation.161993558
Short name T951
Test name
Test status
Simulation time 4688515352 ps
CPU time 474.84 seconds
Started Aug 04 07:15:11 PM PDT 24
Finished Aug 04 07:23:06 PM PDT 24
Peak memory 619652 kb
Host smart-6332d195-5a82-475e-834b-f1f6145ec72b
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=161993558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.161993558
Directory /workspace/0.chip_sw_alert_handler_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.4183811936
Short name T733
Test name
Test status
Simulation time 7905909160 ps
CPU time 1522.29 seconds
Started Aug 04 07:13:44 PM PDT 24
Finished Aug 04 07:39:07 PM PDT 24
Peak memory 610212 kb
Host smart-d969023f-4709-4c18-9466-9f80b06634be
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4183811936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.4183811936
Directory /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1410536706
Short name T736
Test name
Test status
Simulation time 8449786184 ps
CPU time 1917.26 seconds
Started Aug 04 07:15:50 PM PDT 24
Finished Aug 04 07:47:49 PM PDT 24
Peak memory 610144 kb
Host smart-db2c22d5-7d34-46d0-8570-2a3dc4c7fafe
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1410536706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg
le.1410536706
Directory /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2266869373
Short name T193
Test name
Test status
Simulation time 11375918056 ps
CPU time 948.06 seconds
Started Aug 04 07:14:05 PM PDT 24
Finished Aug 04 07:29:53 PM PDT 24
Peak memory 610672 kb
Host smart-53070088-6139-4d4a-a5e0-c03e0d5b11fb
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler
_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266869373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han
dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.chip_sw_alert_handler_lpg_sleep_mode_pings.2266869373
Directory /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.564084436
Short name T763
Test name
Test status
Simulation time 7801430800 ps
CPU time 1353.04 seconds
Started Aug 04 07:17:54 PM PDT 24
Finished Aug 04 07:40:28 PM PDT 24
Peak memory 609776 kb
Host smart-a78a7db6-728f-4771-bba3-5538b900309b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=564084436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.564084436
Directory /workspace/0.chip_sw_alert_handler_ping_ok/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1856228996
Short name T566
Test name
Test status
Simulation time 5975776700 ps
CPU time 618.42 seconds
Started Aug 04 07:17:32 PM PDT 24
Finished Aug 04 07:27:51 PM PDT 24
Peak memory 610068 kb
Host smart-d38f8a94-6d8a-4477-bb48-16ccbc531d9e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1856228996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.1856228996
Directory /workspace/0.chip_sw_alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3056946131
Short name T62
Test name
Test status
Simulation time 255036361098 ps
CPU time 12660.3 seconds
Started Aug 04 07:15:38 PM PDT 24
Finished Aug 04 10:46:40 PM PDT 24
Peak memory 610584 kb
Host smart-6dbff276-cd55-4950-9760-ee4f6972bd31
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056946131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3056946131
Directory /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location /workspace/coverage/default/0.chip_sw_alert_test.3376797128
Short name T106
Test name
Test status
Simulation time 3301686100 ps
CPU time 321.27 seconds
Started Aug 04 07:14:19 PM PDT 24
Finished Aug 04 07:19:40 PM PDT 24
Peak memory 610044 kb
Host smart-e03708ac-4f48-4144-b094-2db639ea2d7f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376797128 -assert nopostproc +UVM_TESTNAME=chip_ba
se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.chip_sw_alert_test.3376797128
Directory /workspace/0.chip_sw_alert_test/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_irq.1715105522
Short name T745
Test name
Test status
Simulation time 3776702306 ps
CPU time 420.95 seconds
Started Aug 04 07:16:03 PM PDT 24
Finished Aug 04 07:23:04 PM PDT 24
Peak memory 609436 kb
Host smart-566ea349-15eb-4a61-a476-1f0c0a4f047d
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715105522 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.1715105522
Directory /workspace/0.chip_sw_aon_timer_irq/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.559505109
Short name T654
Test name
Test status
Simulation time 3173702704 ps
CPU time 341.76 seconds
Started Aug 04 07:20:10 PM PDT 24
Finished Aug 04 07:25:52 PM PDT 24
Peak memory 609588 kb
Host smart-9678587b-8db0-4b2e-8a7e-93fbc4639201
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559505109 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_aon_timer_smoketest.559505109
Directory /workspace/0.chip_sw_aon_timer_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1184792997
Short name T720
Test name
Test status
Simulation time 7770495108 ps
CPU time 709.91 seconds
Started Aug 04 07:15:11 PM PDT 24
Finished Aug 04 07:27:01 PM PDT 24
Peak memory 610504 kb
Host smart-c0883ba2-2f08-470c-90e6-e03bfee7d32d
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1184792997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.1184792997
Directory /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1255225295
Short name T855
Test name
Test status
Simulation time 5121209744 ps
CPU time 490.48 seconds
Started Aug 04 07:14:52 PM PDT 24
Finished Aug 04 07:23:03 PM PDT 24
Peak memory 609336 kb
Host smart-01745263-55f6-4b92-a3a6-6951acf86835
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1255225295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.1255225295
Directory /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location /workspace/coverage/default/0.chip_sw_ast_clk_outputs.3445558091
Short name T807
Test name
Test status
Simulation time 6979879440 ps
CPU time 1069.53 seconds
Started Aug 04 07:18:58 PM PDT 24
Finished Aug 04 07:36:49 PM PDT 24
Peak memory 616292 kb
Host smart-f817d717-66b2-4299-9deb-cd8e89f67640
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445558091 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.3445558091
Directory /workspace/0.chip_sw_ast_clk_outputs/latest

Test location /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.1837438340
Short name T87
Test name
Test status
Simulation time 24082200903 ps
CPU time 4027.73 seconds
Started Aug 04 07:19:51 PM PDT 24
Finished Aug 04 08:27:00 PM PDT 24
Peak memory 611176 kb
Host smart-18ad5fa0-4f4c-4753-89d4-a54781425cfd
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837438340
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.1837438340
Directory /workspace/0.chip_sw_ast_clk_rst_inputs/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1957175184
Short name T898
Test name
Test status
Simulation time 3753654046 ps
CPU time 703.25 seconds
Started Aug 04 07:16:58 PM PDT 24
Finished Aug 04 07:28:42 PM PDT 24
Peak memory 613092 kb
Host smart-3e0801e5-f649-4927-ba42-77a65100251d
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957175184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_rma.1957175184
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4200480608
Short name T623
Test name
Test status
Simulation time 3782989142 ps
CPU time 533.63 seconds
Started Aug 04 07:16:09 PM PDT 24
Finished Aug 04 07:25:03 PM PDT 24
Peak memory 613148 kb
Host smart-272b46bf-76ce-493b-8f45-62a303a394a3
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200480608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4200480608
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3823240907
Short name T673
Test name
Test status
Simulation time 4861066890 ps
CPU time 562.64 seconds
Started Aug 04 07:15:06 PM PDT 24
Finished Aug 04 07:24:29 PM PDT 24
Peak memory 612124 kb
Host smart-66a39c08-5f54-420e-a569-5ead817e11c8
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823240907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_dev.3823240907
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.809047820
Short name T1017
Test name
Test status
Simulation time 4501289496 ps
CPU time 733.35 seconds
Started Aug 04 07:17:03 PM PDT 24
Finished Aug 04 07:29:16 PM PDT 24
Peak memory 612876 kb
Host smart-93122b6f-3003-4616-b1d1-be9f271b4728
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809047820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl
kmgr_external_clk_src_for_sw_slow_rma.809047820
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.130730981
Short name T662
Test name
Test status
Simulation time 4942273736 ps
CPU time 512.62 seconds
Started Aug 04 07:16:13 PM PDT 24
Finished Aug 04 07:24:46 PM PDT 24
Peak memory 613136 kb
Host smart-55829698-f07d-4cb3-aa11-419239ebcbcd
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130730981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM
_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.130730981
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_jitter.630894176
Short name T1004
Test name
Test status
Simulation time 2685893064 ps
CPU time 302.39 seconds
Started Aug 04 07:18:19 PM PDT 24
Finished Aug 04 07:23:22 PM PDT 24
Peak memory 608424 kb
Host smart-fe407fab-aeb9-436d-8a03-d1661a27b2e8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630894176 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_clkmgr_jitter.630894176
Directory /workspace/0.chip_sw_clkmgr_jitter/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3575479073
Short name T670
Test name
Test status
Simulation time 3810651352 ps
CPU time 415.74 seconds
Started Aug 04 07:18:30 PM PDT 24
Finished Aug 04 07:25:26 PM PDT 24
Peak memory 609488 kb
Host smart-3a11c9ef-07d8-41f6-b647-c463c2cc6850
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575479073 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.3575479073
Directory /workspace/0.chip_sw_clkmgr_jitter_frequency/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1931872755
Short name T924
Test name
Test status
Simulation time 2481326274 ps
CPU time 226.78 seconds
Started Aug 04 07:19:23 PM PDT 24
Finished Aug 04 07:23:10 PM PDT 24
Peak memory 609724 kb
Host smart-1c50174d-703b-466d-88a8-ce18d094ce5f
User root
Command /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931872755 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.1931872755
Directory /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2665282106
Short name T624
Test name
Test status
Simulation time 5105230828 ps
CPU time 373.95 seconds
Started Aug 04 07:17:03 PM PDT 24
Finished Aug 04 07:23:17 PM PDT 24
Peak memory 610444 kb
Host smart-9adb445b-d056-4e41-91af-c3128aae5420
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665282106 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.2665282106
Directory /workspace/0.chip_sw_clkmgr_off_aes_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.78584749
Short name T167
Test name
Test status
Simulation time 3825029688 ps
CPU time 296.92 seconds
Started Aug 04 07:16:57 PM PDT 24
Finished Aug 04 07:21:54 PM PDT 24
Peak memory 610076 kb
Host smart-6ce0b5de-e976-4f91-8315-3c4f6993a6ce
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78584749 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.78584749
Directory /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3640710431
Short name T788
Test name
Test status
Simulation time 3896133560 ps
CPU time 476.19 seconds
Started Aug 04 07:19:06 PM PDT 24
Finished Aug 04 07:27:02 PM PDT 24
Peak memory 609904 kb
Host smart-a91e3e7c-0009-4342-add9-d87ea551b4f0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640710431 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.3640710431
Directory /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.189711200
Short name T932
Test name
Test status
Simulation time 3864551708 ps
CPU time 352.5 seconds
Started Aug 04 07:17:20 PM PDT 24
Finished Aug 04 07:23:13 PM PDT 24
Peak memory 609312 kb
Host smart-ae39d93e-e363-4636-bb27-1462b565800b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189711200 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.189711200
Directory /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3072063258
Short name T835
Test name
Test status
Simulation time 8799220988 ps
CPU time 855.03 seconds
Started Aug 04 07:16:23 PM PDT 24
Finished Aug 04 07:30:39 PM PDT 24
Peak memory 610488 kb
Host smart-4a357944-0138-4a0e-8ac5-934713d3766a
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072063258
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.3072063258
Directory /workspace/0.chip_sw_clkmgr_off_peri/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3446889482
Short name T588
Test name
Test status
Simulation time 2859739104 ps
CPU time 293.91 seconds
Started Aug 04 07:16:54 PM PDT 24
Finished Aug 04 07:21:48 PM PDT 24
Peak memory 608720 kb
Host smart-73bce2fc-9369-4c93-89f4-255f0f6242ce
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446889482 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.3446889482
Directory /workspace/0.chip_sw_clkmgr_reset_frequency/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1504630977
Short name T655
Test name
Test status
Simulation time 4244016188 ps
CPU time 609.97 seconds
Started Aug 04 07:18:18 PM PDT 24
Finished Aug 04 07:28:28 PM PDT 24
Peak memory 609988 kb
Host smart-630fa95c-9b07-4d02-9873-fdae1bfb17a1
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504630977 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.1504630977
Directory /workspace/0.chip_sw_clkmgr_sleep_frequency/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3711854319
Short name T935
Test name
Test status
Simulation time 3140613672 ps
CPU time 271.45 seconds
Started Aug 04 07:19:22 PM PDT 24
Finished Aug 04 07:23:54 PM PDT 24
Peak memory 609672 kb
Host smart-8db8d9c3-28aa-4513-bd05-bb9352d1fa95
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711854319 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.chip_sw_clkmgr_smoketest.3711854319
Directory /workspace/0.chip_sw_clkmgr_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_coremark.581329381
Short name T708
Test name
Test status
Simulation time 71394283592 ps
CPU time 13878.6 seconds
Started Aug 04 07:16:09 PM PDT 24
Finished Aug 04 11:07:29 PM PDT 24
Peak memory 610396 kb
Host smart-ed9f5c7e-61c5-4570-b252-495db2a447b7
User root
Command /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=581329381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.581329381
Directory /workspace/0.chip_sw_coremark/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2513021414
Short name T987
Test name
Test status
Simulation time 21394822040 ps
CPU time 5027.4 seconds
Started Aug 04 07:15:29 PM PDT 24
Finished Aug 04 08:39:17 PM PDT 24
Peak memory 610404 kb
Host smart-e1907770-8bf7-469b-8960-d75e52352a36
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513021414 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.2513021414
Directory /workspace/0.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_kat_test.3448821981
Short name T719
Test name
Test status
Simulation time 2450845896 ps
CPU time 204.25 seconds
Started Aug 04 07:16:06 PM PDT 24
Finished Aug 04 07:19:30 PM PDT 24
Peak memory 609424 kb
Host smart-e8cf5ff7-ac43-4c00-9913-ad205d55f8e1
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448821981 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.3448821981
Directory /workspace/0.chip_sw_csrng_kat_test/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1432744044
Short name T976
Test name
Test status
Simulation time 5727271928 ps
CPU time 568.36 seconds
Started Aug 04 07:15:53 PM PDT 24
Finished Aug 04 07:25:22 PM PDT 24
Peak memory 611360 kb
Host smart-921e989c-bef7-41f4-9095-6a570701c60b
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima
ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432744044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_
lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr
ng_lc_hw_debug_en_test.1432744044
Directory /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_smoketest.2419711187
Short name T995
Test name
Test status
Simulation time 2533228064 ps
CPU time 267.36 seconds
Started Aug 04 07:20:31 PM PDT 24
Finished Aug 04 07:24:59 PM PDT 24
Peak memory 608400 kb
Host smart-f8b63cff-8565-4e6d-b00e-4aa5e8ea2798
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419711187 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.chip_sw_csrng_smoketest.2419711187
Directory /workspace/0.chip_sw_csrng_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_data_integrity_escalation.3327569344
Short name T958
Test name
Test status
Simulation time 4784538984 ps
CPU time 675.01 seconds
Started Aug 04 07:13:38 PM PDT 24
Finished Aug 04 07:24:55 PM PDT 24
Peak memory 611072 kb
Host smart-04f8cf7b-e5e7-4ed4-a381-be84bd640d2c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3327569344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.3327569344
Directory /workspace/0.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_edn_auto_mode.1088816154
Short name T71
Test name
Test status
Simulation time 4215494516 ps
CPU time 978.46 seconds
Started Aug 04 07:15:02 PM PDT 24
Finished Aug 04 07:31:21 PM PDT 24
Peak memory 609724 kb
Host smart-3dcda670-a5aa-4aef-b0e4-1ea1857e59e8
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088816154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_
auto_mode.1088816154
Directory /workspace/0.chip_sw_edn_auto_mode/latest

Test location /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2611641500
Short name T406
Test name
Test status
Simulation time 7413291792 ps
CPU time 1356.32 seconds
Started Aug 04 07:15:56 PM PDT 24
Finished Aug 04 07:38:32 PM PDT 24
Peak memory 611004 kb
Host smart-e279fd67-9e0f-47ca-be59-da9d4e96a011
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed
n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2611641500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.2611641500
Directory /workspace/0.chip_sw_edn_entropy_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3213308099
Short name T66
Test name
Test status
Simulation time 6770324519 ps
CPU time 1374.77 seconds
Started Aug 04 07:17:24 PM PDT 24
Finished Aug 04 07:40:20 PM PDT 24
Peak memory 610992 kb
Host smart-da0885cd-2cd1-40ba-8e94-73be75896661
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e
ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213308099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.3213308099
Directory /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest

Test location /workspace/coverage/default/0.chip_sw_edn_kat.3087837545
Short name T757
Test name
Test status
Simulation time 3234098940 ps
CPU time 588.94 seconds
Started Aug 04 07:13:59 PM PDT 24
Finished Aug 04 07:23:48 PM PDT 24
Peak memory 615316 kb
Host smart-dedfd76f-1dbc-4472-bcad-7ac11701d82c
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3
+accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087837545 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_edn_kat.3087837545
Directory /workspace/0.chip_sw_edn_kat/latest

Test location /workspace/coverage/default/0.chip_sw_edn_sw_mode.3100783332
Short name T867
Test name
Test status
Simulation time 6112193632 ps
CPU time 1247.32 seconds
Started Aug 04 07:17:33 PM PDT 24
Finished Aug 04 07:38:21 PM PDT 24
Peak memory 609968 kb
Host smart-7606531a-85a0-485f-9dc8-e7b0b5caf6bf
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100783332 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.3100783332
Directory /workspace/0.chip_sw_edn_sw_mode/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.723902705
Short name T133
Test name
Test status
Simulation time 3010584280 ps
CPU time 297.48 seconds
Started Aug 04 07:14:50 PM PDT 24
Finished Aug 04 07:19:48 PM PDT 24
Peak memory 609804 kb
Host smart-f3e09562-0261-4177-9479-2e87d2d7cd0f
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72
3902705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.723902705
Directory /workspace/0.chip_sw_entropy_src_ast_rng_req/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3515821179
Short name T926
Test name
Test status
Simulation time 2866416692 ps
CPU time 220.13 seconds
Started Aug 04 07:14:40 PM PDT 24
Finished Aug 04 07:18:20 PM PDT 24
Peak memory 609864 kb
Host smart-62b90ea1-69a9-4856-aa64-080245136ed5
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515821179
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.3515821179
Directory /workspace/0.chip_sw_entropy_src_kat_test/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.801979239
Short name T709
Test name
Test status
Simulation time 3184585000 ps
CPU time 351.74 seconds
Started Aug 04 07:18:54 PM PDT 24
Finished Aug 04 07:24:46 PM PDT 24
Peak memory 609832 kb
Host smart-d5a5e806-3c04-4125-90d7-5e240b2356ad
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=801979239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.801979239
Directory /workspace/0.chip_sw_entropy_src_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_example_concurrency.2945421566
Short name T614
Test name
Test status
Simulation time 3112239064 ps
CPU time 204.78 seconds
Started Aug 04 07:15:17 PM PDT 24
Finished Aug 04 07:18:42 PM PDT 24
Peak memory 609672 kb
Host smart-f57ae213-1ace-4b68-b4d4-cf066f4f0c0f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945421566 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.chip_sw_example_concurrency.2945421566
Directory /workspace/0.chip_sw_example_concurrency/latest

Test location /workspace/coverage/default/0.chip_sw_example_flash.2571750441
Short name T793
Test name
Test status
Simulation time 3055292824 ps
CPU time 217.24 seconds
Started Aug 04 07:15:49 PM PDT 24
Finished Aug 04 07:19:27 PM PDT 24
Peak memory 609572 kb
Host smart-b7f1f15e-0e20-4702-9a61-e9a6cb746e9e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571750441 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_example_flash.2571750441
Directory /workspace/0.chip_sw_example_flash/latest

Test location /workspace/coverage/default/0.chip_sw_example_manufacturer.618449524
Short name T640
Test name
Test status
Simulation time 2971915802 ps
CPU time 213.23 seconds
Started Aug 04 07:15:54 PM PDT 24
Finished Aug 04 07:19:28 PM PDT 24
Peak memory 609284 kb
Host smart-5fbcfb89-1d92-4655-921a-163213dfe8e4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618449524 -assert nopostproc +UVM_TESTNAME=chip_b
ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.chip_sw_example_manufacturer.618449524
Directory /workspace/0.chip_sw_example_manufacturer/latest

Test location /workspace/coverage/default/0.chip_sw_example_rom.105582978
Short name T698
Test name
Test status
Simulation time 1847756300 ps
CPU time 154.16 seconds
Started Aug 04 07:13:45 PM PDT 24
Finished Aug 04 07:16:20 PM PDT 24
Peak memory 609012 kb
Host smart-e0fe0a46-d5df-4274-a58e-f9140fcf133b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105582978 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.chip_sw_example_rom.105582978
Directory /workspace/0.chip_sw_example_rom/latest

Test location /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3902223088
Short name T4
Test name
Test status
Simulation time 58323812222 ps
CPU time 10570.8 seconds
Started Aug 04 07:15:27 PM PDT 24
Finished Aug 04 10:11:39 PM PDT 24
Peak memory 624744 kb
Host smart-36822216-cafd-4476-859c-22a8f97b8412
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=3902223088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.3902223088
Directory /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest

Test location /workspace/coverage/default/0.chip_sw_flash_crash_alert.3380229484
Short name T572
Test name
Test status
Simulation time 5574619200 ps
CPU time 718.57 seconds
Started Aug 04 07:16:36 PM PDT 24
Finished Aug 04 07:28:35 PM PDT 24
Peak memory 611276 kb
Host smart-e096b4a6-4ab7-44a0-9286-52b88f947f89
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:
new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=3380229484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.3380229484
Directory /workspace/0.chip_sw_flash_crash_alert/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_access.416145614
Short name T551
Test name
Test status
Simulation time 5145195750 ps
CPU time 877.93 seconds
Started Aug 04 07:14:06 PM PDT 24
Finished Aug 04 07:28:44 PM PDT 24
Peak memory 610032 kb
Host smart-1a3c3efe-939f-4f0a-8317-f7221985e98d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416145614 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_flash_ctrl_access.416145614
Directory /workspace/0.chip_sw_flash_ctrl_access/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2745428683
Short name T600
Test name
Test status
Simulation time 6038850381 ps
CPU time 1049.95 seconds
Started Aug 04 07:14:48 PM PDT 24
Finished Aug 04 07:32:18 PM PDT 24
Peak memory 610016 kb
Host smart-f20786d5-477b-419f-bafc-13f63b8a45a7
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745428683 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.2745428683
Directory /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3784735873
Short name T725
Test name
Test status
Simulation time 8205986852 ps
CPU time 914.41 seconds
Started Aug 04 07:15:45 PM PDT 24
Finished Aug 04 07:31:00 PM PDT 24
Peak memory 610136 kb
Host smart-7e555d95-3ef8-4bac-8c94-4e84ec351b5d
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784735873 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3784735873
Directory /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3589796873
Short name T410
Test name
Test status
Simulation time 5662312346 ps
CPU time 1106.78 seconds
Started Aug 04 07:14:50 PM PDT 24
Finished Aug 04 07:33:17 PM PDT 24
Peak memory 610028 kb
Host smart-c066ee6d-275d-4bed-8151-91aa1a303c03
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589796873 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.3589796873
Directory /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2035801775
Short name T713
Test name
Test status
Simulation time 3042502400 ps
CPU time 274.3 seconds
Started Aug 04 07:13:53 PM PDT 24
Finished Aug 04 07:18:27 PM PDT 24
Peak memory 609892 kb
Host smart-be7e1d3b-3a1b-4bc5-939d-9ed3676da397
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035801775 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.2035801775
Directory /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2916557534
Short name T254
Test name
Test status
Simulation time 5189071320 ps
CPU time 336.02 seconds
Started Aug 04 07:13:32 PM PDT 24
Finished Aug 04 07:19:08 PM PDT 24
Peak memory 610920 kb
Host smart-6cdf5d4a-9518-4aec-9a0b-444c53c986d5
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29
16557534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.2916557534
Directory /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.975036879
Short name T661
Test name
Test status
Simulation time 5750691860 ps
CPU time 1014.71 seconds
Started Aug 04 07:17:03 PM PDT 24
Finished Aug 04 07:33:58 PM PDT 24
Peak memory 609860 kb
Host smart-4096affb-5a79-4855-bae4-a526c1720033
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975036879 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.975036879
Directory /workspace/0.chip_sw_flash_ctrl_mem_protection/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1975638190
Short name T383
Test name
Test status
Simulation time 4262286664 ps
CPU time 597.07 seconds
Started Aug 04 07:14:22 PM PDT 24
Finished Aug 04 07:24:19 PM PDT 24
Peak memory 609628 kb
Host smart-2560ba26-f84c-4230-bac0-ec8446e6cf5d
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975638190
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.1975638190
Directory /workspace/0.chip_sw_flash_ctrl_ops/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1390333862
Short name T981
Test name
Test status
Simulation time 5006475502 ps
CPU time 619.24 seconds
Started Aug 04 07:16:15 PM PDT 24
Finished Aug 04 07:26:35 PM PDT 24
Peak memory 608972 kb
Host smart-69bc7369-f884-435c-bef0-1d0afc330b96
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_
rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1390333862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1390333862
Directory /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.948687368
Short name T573
Test name
Test status
Simulation time 3208966832 ps
CPU time 355.6 seconds
Started Aug 04 07:16:14 PM PDT 24
Finished Aug 04 07:22:10 PM PDT 24
Peak memory 609836 kb
Host smart-18031850-aa51-4ffd-bed7-3ac7dfd32a07
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9486873
68 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.948687368
Directory /workspace/0.chip_sw_flash_ctrl_write_clear/latest

Test location /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1727130692
Short name T820
Test name
Test status
Simulation time 2873344776 ps
CPU time 307.54 seconds
Started Aug 04 07:21:23 PM PDT 24
Finished Aug 04 07:26:31 PM PDT 24
Peak memory 609632 kb
Host smart-8f145dc8-4ce9-4d3f-bfe1-8e729f878dcc
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket
est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1727130692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.1727130692
Directory /workspace/0.chip_sw_flash_scrambling_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_gpio_smoketest.896731842
Short name T335
Test name
Test status
Simulation time 2927020078 ps
CPU time 255.85 seconds
Started Aug 04 07:21:09 PM PDT 24
Finished Aug 04 07:25:25 PM PDT 24
Peak memory 608936 kb
Host smart-be32dbaa-79a5-4bae-9845-e07ae10480e4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896731842 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.chip_sw_gpio_smoketest.896731842
Directory /workspace/0.chip_sw_gpio_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc.736219602
Short name T194
Test name
Test status
Simulation time 3273733528 ps
CPU time 334.52 seconds
Started Aug 04 07:15:39 PM PDT 24
Finished Aug 04 07:21:14 PM PDT 24
Peak memory 608428 kb
Host smart-1eba5a97-b111-4d37-a862-ac0ba459c970
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736219602 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_hmac_enc.736219602
Directory /workspace/0.chip_sw_hmac_enc/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc_idle.122527989
Short name T799
Test name
Test status
Simulation time 3240009808 ps
CPU time 352.04 seconds
Started Aug 04 07:16:26 PM PDT 24
Finished Aug 04 07:22:18 PM PDT 24
Peak memory 609796 kb
Host smart-791c0a65-043e-4a25-b12a-bb861af65905
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122527989 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_hmac_enc_idle.122527989
Directory /workspace/0.chip_sw_hmac_enc_idle/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1725505103
Short name T1010
Test name
Test status
Simulation time 2781780496 ps
CPU time 288.86 seconds
Started Aug 04 07:17:40 PM PDT 24
Finished Aug 04 07:22:29 PM PDT 24
Peak memory 609732 kb
Host smart-611f543b-c7f2-4349-bee3-783b7ada72a4
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725505103 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.1725505103
Directory /workspace/0.chip_sw_hmac_enc_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.164955505
Short name T784
Test name
Test status
Simulation time 3011061604 ps
CPU time 308.62 seconds
Started Aug 04 07:19:18 PM PDT 24
Finished Aug 04 07:24:27 PM PDT 24
Peak memory 609812 kb
Host smart-1cd82999-5604-41b3-9172-fca1e79e570a
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164955505 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.164955505
Directory /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_multistream.1756546039
Short name T883
Test name
Test status
Simulation time 7778782400 ps
CPU time 1807.23 seconds
Started Aug 04 07:17:03 PM PDT 24
Finished Aug 04 07:47:10 PM PDT 24
Peak memory 608876 kb
Host smart-6eb3c686-5164-4b71-9203-b22c199073eb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756546039 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.chip_sw_hmac_multistream.1756546039
Directory /workspace/0.chip_sw_hmac_multistream/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_oneshot.1994988690
Short name T626
Test name
Test status
Simulation time 3020521256 ps
CPU time 308.13 seconds
Started Aug 04 07:15:27 PM PDT 24
Finished Aug 04 07:20:36 PM PDT 24
Peak memory 608472 kb
Host smart-d4d38aa8-0775-4165-9b2d-c8bf2be7b4a0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994988690 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_hmac_oneshot.1994988690
Directory /workspace/0.chip_sw_hmac_oneshot/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_smoketest.1968637747
Short name T1007
Test name
Test status
Simulation time 3701140852 ps
CPU time 294.73 seconds
Started Aug 04 07:21:20 PM PDT 24
Finished Aug 04 07:26:15 PM PDT 24
Peak memory 608544 kb
Host smart-5a4d30b9-9f6d-4d26-ba5b-68ca605139cf
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968637747 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_hmac_smoketest.1968637747
Directory /workspace/0.chip_sw_hmac_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1537405785
Short name T934
Test name
Test status
Simulation time 4752209706 ps
CPU time 584.5 seconds
Started Aug 04 07:13:47 PM PDT 24
Finished Aug 04 07:23:32 PM PDT 24
Peak memory 609456 kb
Host smart-e0e165dd-c42f-4a82-8ee7-1b0b4df200d8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537405785 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.1537405785
Directory /workspace/0.chip_sw_i2c_device_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2764520809
Short name T230
Test name
Test status
Simulation time 5810191688 ps
CPU time 859.23 seconds
Started Aug 04 07:14:47 PM PDT 24
Finished Aug 04 07:29:07 PM PDT 24
Peak memory 609200 kb
Host smart-2cc85dbd-6ca7-4b6a-a4cd-b83820885303
User root
Command /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764520809 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.2764520809
Directory /workspace/0.chip_sw_i2c_host_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3380816033
Short name T228
Test name
Test status
Simulation time 5805699630 ps
CPU time 874.91 seconds
Started Aug 04 07:14:24 PM PDT 24
Finished Aug 04 07:28:59 PM PDT 24
Peak memory 609256 kb
Host smart-e4530379-b5c3-4e50-9b85-34b00f7d6a5e
User root
Command /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380816033 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.3380816033
Directory /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1557136772
Short name T1006
Test name
Test status
Simulation time 5541984040 ps
CPU time 1009.37 seconds
Started Aug 04 07:14:13 PM PDT 24
Finished Aug 04 07:31:03 PM PDT 24
Peak memory 610264 kb
Host smart-f669ae23-bbc6-4c07-aa41-4be22fbe1d10
User root
Command /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557136772 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.1557136772
Directory /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest

Test location /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3881839279
Short name T899
Test name
Test status
Simulation time 64364823199 ps
CPU time 11420.3 seconds
Started Aug 04 07:13:13 PM PDT 24
Finished Aug 04 10:23:35 PM PDT 24
Peak memory 624776 kb
Host smart-a88f56a8-441e-4067-850d-8430e332ca3b
User root
Command /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3881839279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.3881839279
Directory /workspace/0.chip_sw_inject_scramble_seed/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1816436624
Short name T604
Test name
Test status
Simulation time 6005864210 ps
CPU time 771.99 seconds
Started Aug 04 07:14:58 PM PDT 24
Finished Aug 04 07:27:50 PM PDT 24
Peak memory 618192 kb
Host smart-a2a728f8-df04-4add-b4bd-4128b09c7d49
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816
436624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.1816436624
Directory /workspace/0.chip_sw_keymgr_key_derivation/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.473291115
Short name T664
Test name
Test status
Simulation time 7149400843 ps
CPU time 870.86 seconds
Started Aug 04 07:17:39 PM PDT 24
Finished Aug 04 07:32:10 PM PDT 24
Peak memory 617192 kb
Host smart-a3e84272-c807-46f2-9990-985ca08749a4
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=473291115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en_
reduced_freq.473291115
Directory /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3346279023
Short name T166
Test name
Test status
Simulation time 9937621000 ps
CPU time 1916.87 seconds
Started Aug 04 07:17:00 PM PDT 24
Finished Aug 04 07:48:57 PM PDT 24
Peak memory 616908 kb
Host smart-fe2bf105-95db-4f86-b99b-f8815bd3c084
User root
Command /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3346279023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.3346279023
Directory /workspace/0.chip_sw_keymgr_key_derivation_prod/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2164948690
Short name T646
Test name
Test status
Simulation time 9214372248 ps
CPU time 2460.9 seconds
Started Aug 04 07:17:05 PM PDT 24
Finished Aug 04 07:58:06 PM PDT 24
Peak memory 611108 kb
Host smart-82a83818-4ab4-48da-84a7-4a3df5d6731e
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21649
48690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.2164948690
Directory /workspace/0.chip_sw_keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_entropy.2903563923
Short name T753
Test name
Test status
Simulation time 1936145744 ps
CPU time 229.7 seconds
Started Aug 04 07:14:34 PM PDT 24
Finished Aug 04 07:18:24 PM PDT 24
Peak memory 609668 kb
Host smart-413ab3fb-c683-46df-84f5-db61032ba20e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903563923 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_kmac_entropy.2903563923
Directory /workspace/0.chip_sw_kmac_entropy/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_idle.1709875481
Short name T559
Test name
Test status
Simulation time 3005117072 ps
CPU time 200.75 seconds
Started Aug 04 07:14:13 PM PDT 24
Finished Aug 04 07:17:34 PM PDT 24
Peak memory 609676 kb
Host smart-35efa1c5-3211-4bde-b422-e8fb439ee084
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709875481 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_kmac_idle.1709875481
Directory /workspace/0.chip_sw_kmac_idle/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2791403481
Short name T603
Test name
Test status
Simulation time 2298819810 ps
CPU time 220.8 seconds
Started Aug 04 07:17:08 PM PDT 24
Finished Aug 04 07:20:49 PM PDT 24
Peak memory 609796 kb
Host smart-b12cf64e-e01e-4a24-a74f-bb3c39c80085
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791403481 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.chip_sw_kmac_mode_cshake.2791403481
Directory /workspace/0.chip_sw_kmac_mode_cshake/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1588855739
Short name T164
Test name
Test status
Simulation time 3090400290 ps
CPU time 254.18 seconds
Started Aug 04 07:15:32 PM PDT 24
Finished Aug 04 07:19:46 PM PDT 24
Peak memory 608480 kb
Host smart-1288a08e-3c96-4a59-abb2-acfccb15a4b1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588855739 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.chip_sw_kmac_mode_kmac.1588855739
Directory /workspace/0.chip_sw_kmac_mode_kmac/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.168022216
Short name T165
Test name
Test status
Simulation time 3350600990 ps
CPU time 262.47 seconds
Started Aug 04 07:16:13 PM PDT 24
Finished Aug 04 07:20:35 PM PDT 24
Peak memory 609688 kb
Host smart-dc7ca783-5fb8-42c6-b209-7689238bcf61
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168022216 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.168022216
Directory /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2943734254
Short name T953
Test name
Test status
Simulation time 3262271312 ps
CPU time 346.11 seconds
Started Aug 04 07:19:14 PM PDT 24
Finished Aug 04 07:25:01 PM PDT 24
Peak memory 609792 kb
Host smart-11375d14-c1b4-4523-a2c9-0592309a0637
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29437342
54 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2943734254
Directory /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_smoketest.1588525534
Short name T830
Test name
Test status
Simulation time 2825329704 ps
CPU time 271.06 seconds
Started Aug 04 07:20:06 PM PDT 24
Finished Aug 04 07:24:38 PM PDT 24
Peak memory 609592 kb
Host smart-0082d043-10a1-4104-983c-1ce8afc217e8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588525534 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_kmac_smoketest.1588525534
Directory /workspace/0.chip_sw_kmac_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2518649065
Short name T637
Test name
Test status
Simulation time 2826454000 ps
CPU time 241.63 seconds
Started Aug 04 07:14:12 PM PDT 24
Finished Aug 04 07:18:14 PM PDT 24
Peak memory 609692 kb
Host smart-04f2149a-e43d-4d51-a90a-c8ba74820533
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518649065 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.2518649065
Directory /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1495314936
Short name T990
Test name
Test status
Simulation time 2684070904 ps
CPU time 134.69 seconds
Started Aug 04 07:14:29 PM PDT 24
Finished Aug 04 07:16:44 PM PDT 24
Peak memory 620676 kb
Host smart-dab84bac-fc49-4365-bc67-c8eb22482fe9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules
,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1495314936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.1495314936
Directory /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.618630336
Short name T896
Test name
Test status
Simulation time 3747580542 ps
CPU time 246.52 seconds
Started Aug 04 07:13:21 PM PDT 24
Finished Aug 04 07:17:28 PM PDT 24
Peak memory 621292 kb
Host smart-ed36aabd-93cc-4225-ae3d-ed6fe682bed0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules
,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=618630336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.618630336
Directory /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.586527333
Short name T217
Test name
Test status
Simulation time 3614145051 ps
CPU time 147.98 seconds
Started Aug 04 07:13:32 PM PDT 24
Finished Aug 04 07:16:00 PM PDT 24
Peak memory 620048 kb
Host smart-545f5105-1f61-46ac-ba7a-bb06c207451b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586527333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.586527333
Directory /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3928186283
Short name T560
Test name
Test status
Simulation time 6588700446 ps
CPU time 806.81 seconds
Started Aug 04 07:14:15 PM PDT 24
Finished Aug 04 07:27:42 PM PDT 24
Peak memory 620324 kb
Host smart-8130e677-94d9-4cbc-bca7-199664b67d4a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928186283 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.3928186283
Directory /workspace/0.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1491799515
Short name T422
Test name
Test status
Simulation time 2648959687 ps
CPU time 111.07 seconds
Started Aug 04 07:13:56 PM PDT 24
Finished Aug 04 07:15:47 PM PDT 24
Peak memory 616988 kb
Host smart-24311aec-1559-45a4-a911-602634a161e6
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes
t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1491799515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.1491799515
Directory /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3777190395
Short name T361
Test name
Test status
Simulation time 2127057147 ps
CPU time 119 seconds
Started Aug 04 07:13:28 PM PDT 24
Finished Aug 04 07:15:27 PM PDT 24
Peak memory 616948 kb
Host smart-6b0df263-9536-42c0-bf09-4e264bd3a284
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s
im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777190395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3777190395
Directory /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3040084258
Short name T801
Test name
Test status
Simulation time 50011519207 ps
CPU time 6138.42 seconds
Started Aug 04 07:16:06 PM PDT 24
Finished Aug 04 08:58:25 PM PDT 24
Peak memory 620888 kb
Host smart-81110363-5d63-43ea-b096-1b4d7178e275
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040084258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip
_sw_lc_walkthrough_dev.3040084258
Directory /workspace/0.chip_sw_lc_walkthrough_dev/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1820649893
Short name T205
Test name
Test status
Simulation time 7908191688 ps
CPU time 888.62 seconds
Started Aug 04 07:15:42 PM PDT 24
Finished Aug 04 07:30:32 PM PDT 24
Peak memory 620344 kb
Host smart-945104b0-b0e7-4ba5-ae34-788594a07f10
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa
lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820649893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.1820649893
Directory /workspace/0.chip_sw_lc_walkthrough_prodend/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.180527832
Short name T249
Test name
Test status
Simulation time 45882211346 ps
CPU time 5307.36 seconds
Started Aug 04 07:16:00 PM PDT 24
Finished Aug 04 08:44:29 PM PDT 24
Peak memory 620344 kb
Host smart-f84c19f0-d603-414a-adee-3f9c9a58875b
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180527832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch
ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_
sw_lc_walkthrough_rma.180527832
Directory /workspace/0.chip_sw_lc_walkthrough_rma/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2450300762
Short name T715
Test name
Test status
Simulation time 36646478180 ps
CPU time 2878.56 seconds
Started Aug 04 07:15:13 PM PDT 24
Finished Aug 04 08:03:12 PM PDT 24
Peak memory 620900 kb
Host smart-99e4fb06-be1a-445b-a6a7-159c1994d11c
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks
_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2450300762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun
locks.2450300762
Directory /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2667688767
Short name T135
Test name
Test status
Simulation time 19181798492 ps
CPU time 4029.41 seconds
Started Aug 04 07:17:41 PM PDT 24
Finished Aug 04 08:24:51 PM PDT 24
Peak memory 610068 kb
Host smart-aab8f369-5cf1-4bab-902f-77505d0639dc
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne
w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2667688767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2667688767
Directory /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2136338194
Short name T813
Test name
Test status
Simulation time 25085414889 ps
CPU time 4088.82 seconds
Started Aug 04 07:18:35 PM PDT 24
Finished Aug 04 08:26:45 PM PDT 24
Peak memory 610140 kb
Host smart-45c2a9e3-0ef6-45fa-a54d-bc7b39981c74
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e
cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136338194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu
ced_freq.2136338194
Directory /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1720614896
Short name T261
Test name
Test status
Simulation time 3815968058 ps
CPU time 473.28 seconds
Started Aug 04 07:13:16 PM PDT 24
Finished Aug 04 07:21:10 PM PDT 24
Peak memory 609820 kb
Host smart-6d70873c-2a91-4b49-ba9e-6d9a5c7db5f5
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn
_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720614896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.1720614896
Directory /workspace/0.chip_sw_otbn_mem_scramble/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_randomness.689074957
Short name T74
Test name
Test status
Simulation time 5825926604 ps
CPU time 849.71 seconds
Started Aug 04 07:14:22 PM PDT 24
Finished Aug 04 07:28:32 PM PDT 24
Peak memory 610284 kb
Host smart-3c1a2403-50db-44be-8732-6dc27b358947
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=689074957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.689074957
Directory /workspace/0.chip_sw_otbn_randomness/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_smoketest.1390887848
Short name T679
Test name
Test status
Simulation time 10072266432 ps
CPU time 2422.01 seconds
Started Aug 04 07:20:01 PM PDT 24
Finished Aug 04 08:00:23 PM PDT 24
Peak memory 610268 kb
Host smart-6de98256-d381-4d09-849d-06fe24f9fc3b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390887848 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_otbn_smoketest.1390887848
Directory /workspace/0.chip_sw_otbn_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1479823345
Short name T776
Test name
Test status
Simulation time 28509553964 ps
CPU time 5528.39 seconds
Started Aug 04 07:14:29 PM PDT 24
Finished Aug 04 08:46:39 PM PDT 24
Peak memory 610512 kb
Host smart-59c9c1b0-7e94-4f45-ad99-a470f53fdacd
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147982
3345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.1479823345
Directory /workspace/0.chip_sw_otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3265216041
Short name T554
Test name
Test status
Simulation time 2301069673 ps
CPU time 234.11 seconds
Started Aug 04 07:14:29 PM PDT 24
Finished Aug 04 07:18:24 PM PDT 24
Peak memory 609380 kb
Host smart-4b203bbe-bbae-434c-883f-1f2e2ab533d8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265216041 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.3265216041
Directory /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1412142745
Short name T206
Test name
Test status
Simulation time 5470514210 ps
CPU time 629.78 seconds
Started Aug 04 07:15:04 PM PDT 24
Finished Aug 04 07:25:34 PM PDT 24
Peak memory 611020 kb
Host smart-6e5ce198-b580-4b9f-ada0-fe1210f3d457
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1412142745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.1412142745
Directory /workspace/0.chip_sw_otp_ctrl_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1015390064
Short name T682
Test name
Test status
Simulation time 8745371536 ps
CPU time 1244.77 seconds
Started Aug 04 07:14:28 PM PDT 24
Finished Aug 04 07:35:13 PM PDT 24
Peak memory 609696 kb
Host smart-7d8d2ab1-b0bb-42e6-85ec-bcff0bcd714d
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1015390064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.1015390064
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1399667359
Short name T594
Test name
Test status
Simulation time 8453933004 ps
CPU time 1275.02 seconds
Started Aug 04 07:15:45 PM PDT 24
Finished Aug 04 07:37:00 PM PDT 24
Peak memory 610684 kb
Host smart-b404f271-2bdf-42f5-82e6-c1f95f073234
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1399667359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.1399667359
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3723263192
Short name T619
Test name
Test status
Simulation time 7600733522 ps
CPU time 939.34 seconds
Started Aug 04 07:13:42 PM PDT 24
Finished Aug 04 07:29:22 PM PDT 24
Peak memory 610728 kb
Host smart-0a2c596b-30e9-473e-b80b-496f132a6b8d
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3723263192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.3723263192
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1862436643
Short name T641
Test name
Test status
Simulation time 4545408832 ps
CPU time 528.21 seconds
Started Aug 04 07:15:32 PM PDT 24
Finished Aug 04 07:24:20 PM PDT 24
Peak memory 609828 kb
Host smart-ea298250-a46f-4906-b6a3-c6465753a7d3
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=1862436643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1862436643
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.4276752356
Short name T370
Test name
Test status
Simulation time 2743535072 ps
CPU time 249.22 seconds
Started Aug 04 07:21:16 PM PDT 24
Finished Aug 04 07:25:25 PM PDT 24
Peak memory 609684 kb
Host smart-32a91c7c-b95c-4356-94f8-a703a855d812
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276752356 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_otp_ctrl_smoketest.4276752356
Directory /workspace/0.chip_sw_otp_ctrl_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_pattgen_ios.3065081564
Short name T384
Test name
Test status
Simulation time 2574424400 ps
CPU time 192.77 seconds
Started Aug 04 07:13:30 PM PDT 24
Finished Aug 04 07:16:43 PM PDT 24
Peak memory 610332 kb
Host smart-a6bdf4f6-9805-40ce-8e25-1397146636c7
User root
Command /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065081564 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.3065081564
Directory /workspace/0.chip_sw_pattgen_ios/latest

Test location /workspace/coverage/default/0.chip_sw_plic_sw_irq.1467280509
Short name T1002
Test name
Test status
Simulation time 2967491684 ps
CPU time 317.28 seconds
Started Aug 04 07:15:51 PM PDT 24
Finished Aug 04 07:21:09 PM PDT 24
Peak memory 608452 kb
Host smart-3b95a30d-4fd6-4b79-aec2-9c76e88f98b6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467280509 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.chip_sw_plic_sw_irq.1467280509
Directory /workspace/0.chip_sw_plic_sw_irq/latest

Test location /workspace/coverage/default/0.chip_sw_power_idle_load.3275956674
Short name T989
Test name
Test status
Simulation time 4669631050 ps
CPU time 774.1 seconds
Started Aug 04 07:17:44 PM PDT 24
Finished Aug 04 07:30:39 PM PDT 24
Peak memory 609244 kb
Host smart-00ca4afb-854d-403a-830f-fef34d073191
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275956674 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.3275956674
Directory /workspace/0.chip_sw_power_idle_load/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.503786469
Short name T689
Test name
Test status
Simulation time 8324588924 ps
CPU time 1558.72 seconds
Started Aug 04 07:14:14 PM PDT 24
Finished Aug 04 07:40:13 PM PDT 24
Peak memory 611172 kb
Host smart-4527e517-d427-454b-b8f8-235658220207
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5037
86469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.503786469
Directory /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3044576714
Short name T622
Test name
Test status
Simulation time 26937299968 ps
CPU time 2528.73 seconds
Started Aug 04 07:15:28 PM PDT 24
Finished Aug 04 07:57:37 PM PDT 24
Peak memory 610692 kb
Host smart-9a6fe177-b5a8-4579-8bb2-a8a355ed3081
User root
Command /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304
4576714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.3044576714
Directory /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2526683601
Short name T60
Test name
Test status
Simulation time 15536226281 ps
CPU time 1303.97 seconds
Started Aug 04 07:16:06 PM PDT 24
Finished Aug 04 07:37:50 PM PDT 24
Peak memory 611528 kb
Host smart-12fdd446-5e14-4751-9712-d0c151a01d17
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2526683601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2526683601
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1595289157
Short name T415
Test name
Test status
Simulation time 22533982464 ps
CPU time 1840.24 seconds
Started Aug 04 07:18:15 PM PDT 24
Finished Aug 04 07:48:56 PM PDT 24
Peak memory 611300 kb
Host smart-3c02c873-de7d-4f2f-905e-8302f818f3b5
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1595289157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1595289157
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1561508783
Short name T647
Test name
Test status
Simulation time 9207305564 ps
CPU time 696.66 seconds
Started Aug 04 07:13:59 PM PDT 24
Finished Aug 04 07:25:36 PM PDT 24
Peak memory 610856 kb
Host smart-29a4b4da-952f-48e6-aaa6-279cb53150b4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561508783 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.1561508783
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1671799095
Short name T902
Test name
Test status
Simulation time 7528015220 ps
CPU time 433.02 seconds
Started Aug 04 07:15:43 PM PDT 24
Finished Aug 04 07:22:56 PM PDT 24
Peak memory 616680 kb
Host smart-cb09f303-c6c9-4292-b4ee-b7b534e8366c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1671799095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1671799095
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3374283199
Short name T392
Test name
Test status
Simulation time 12208171973 ps
CPU time 1256.2 seconds
Started Aug 04 07:14:49 PM PDT 24
Finished Aug 04 07:35:45 PM PDT 24
Peak memory 611276 kb
Host smart-b63848dc-8188-4ca3-98d9-db67283332f3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374283199 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3374283199
Directory /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.326518642
Short name T414
Test name
Test status
Simulation time 7664801600 ps
CPU time 448.24 seconds
Started Aug 04 07:15:48 PM PDT 24
Finished Aug 04 07:23:16 PM PDT 24
Peak memory 609408 kb
Host smart-c89f7925-1706-462e-b3bf-5b87ca1dce1e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326518642 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.326518642
Directory /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1438840356
Short name T687
Test name
Test status
Simulation time 5717132855 ps
CPU time 606.24 seconds
Started Aug 04 07:16:22 PM PDT 24
Finished Aug 04 07:26:28 PM PDT 24
Peak memory 610572 kb
Host smart-370a0023-54d8-4afb-b926-ced3ca1c0cf7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438840356 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.1438840356
Directory /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1378674749
Short name T578
Test name
Test status
Simulation time 28895188597 ps
CPU time 3021.39 seconds
Started Aug 04 07:13:57 PM PDT 24
Finished Aug 04 08:04:19 PM PDT 24
Peak memory 611336 kb
Host smart-28ff8461-860a-49b2-93e5-e678f5eaaf07
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1378674749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1378674749
Directory /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3278174976
Short name T441
Test name
Test status
Simulation time 32674267924 ps
CPU time 3564.07 seconds
Started Aug 04 07:16:02 PM PDT 24
Finished Aug 04 08:15:27 PM PDT 24
Peak memory 611916 kb
Host smart-19b2d6fd-702e-4e4c-8bf3-8a421c028508
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power
_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278174976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit
ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s
leep_power_glitch_reset.3278174976
Directory /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3956145473
Short name T347
Test name
Test status
Simulation time 2565882156 ps
CPU time 270.44 seconds
Started Aug 04 07:14:12 PM PDT 24
Finished Aug 04 07:18:43 PM PDT 24
Peak memory 609556 kb
Host smart-a9426965-b267-4d1a-a51c-4fd442e97c84
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956145473 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.3956145473
Directory /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1488390833
Short name T809
Test name
Test status
Simulation time 5728236071 ps
CPU time 305.28 seconds
Started Aug 04 07:13:54 PM PDT 24
Finished Aug 04 07:18:59 PM PDT 24
Peak memory 616824 kb
Host smart-c0dd350b-f671-4de6-8d3d-c6c42f823aa9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=1488390833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.1488390833
Directory /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3279012577
Short name T428
Test name
Test status
Simulation time 6632169240 ps
CPU time 618.65 seconds
Started Aug 04 07:16:51 PM PDT 24
Finished Aug 04 07:27:10 PM PDT 24
Peak memory 610696 kb
Host smart-5beaedfa-e8ba-4d0d-ae8e-b1e35aa569f0
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3279012577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.3279012577
Directory /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1561561328
Short name T915
Test name
Test status
Simulation time 5149817712 ps
CPU time 402.95 seconds
Started Aug 04 07:21:27 PM PDT 24
Finished Aug 04 07:28:10 PM PDT 24
Peak memory 610164 kb
Host smart-e7f62445-f9a9-417a-9161-1a8563bf0d7d
User root
Command /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561561328 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.1561561328
Directory /workspace/0.chip_sw_pwrmgr_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1584920738
Short name T583
Test name
Test status
Simulation time 9228716916 ps
CPU time 1230.9 seconds
Started Aug 04 07:16:27 PM PDT 24
Finished Aug 04 07:36:58 PM PDT 24
Peak memory 610596 kb
Host smart-fa35c5d4-1fe1-4bee-ae30-79189c8f4cf0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584920738 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.1584920738
Directory /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1914806711
Short name T730
Test name
Test status
Simulation time 5278793980 ps
CPU time 460.66 seconds
Started Aug 04 07:15:53 PM PDT 24
Finished Aug 04 07:23:34 PM PDT 24
Peak memory 610704 kb
Host smart-2db6a7e6-b3cb-4e5a-a78d-8ea6c4a6da0a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914806711 -assert no
postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1914806711
Directory /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.899990032
Short name T412
Test name
Test status
Simulation time 6436481704 ps
CPU time 512.73 seconds
Started Aug 04 07:21:39 PM PDT 24
Finished Aug 04 07:30:12 PM PDT 24
Peak memory 610080 kb
Host smart-c24aa581-4752-4a75-9589-8ffc2cfc154d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899990032 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.899990032
Directory /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3560481276
Short name T240
Test name
Test status
Simulation time 4630294360 ps
CPU time 681.44 seconds
Started Aug 04 07:16:08 PM PDT 24
Finished Aug 04 07:27:30 PM PDT 24
Peak memory 610396 kb
Host smart-1707c169-3f68-4ab1-96a0-01d2cc3e171b
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356
0481276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.3560481276
Directory /workspace/0.chip_sw_pwrmgr_wdog_reset/latest

Test location /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2565021532
Short name T908
Test name
Test status
Simulation time 8934228335 ps
CPU time 579.25 seconds
Started Aug 04 07:15:20 PM PDT 24
Finished Aug 04 07:24:59 PM PDT 24
Peak memory 624756 kb
Host smart-1e20aae4-b421-461d-b66d-00b27e44580b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565021532 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.2565021532
Directory /workspace/0.chip_sw_rom_ctrl_integrity_check/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3372009157
Short name T160
Test name
Test status
Simulation time 16492202680 ps
CPU time 2412.38 seconds
Started Aug 04 07:14:46 PM PDT 24
Finished Aug 04 07:54:58 PM PDT 24
Peak memory 610976 kb
Host smart-c041d777-fb4e-41e7-a940-719e7357aa95
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=3372009157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.3372009157
Directory /workspace/0.chip_sw_rstmgr_alert_info/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2444654173
Short name T283
Test name
Test status
Simulation time 5853781560 ps
CPU time 521.75 seconds
Started Aug 04 07:14:30 PM PDT 24
Finished Aug 04 07:23:12 PM PDT 24
Peak memory 610492 kb
Host smart-059e432c-33b9-400d-8169-88958788243b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444654173 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.2444654173
Directory /workspace/0.chip_sw_rstmgr_cpu_info/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2164651954
Short name T877
Test name
Test status
Simulation time 5725754260 ps
CPU time 720.53 seconds
Started Aug 04 07:13:54 PM PDT 24
Finished Aug 04 07:25:55 PM PDT 24
Peak memory 641720 kb
Host smart-be22974d-ffca-41bb-a8a4-7cdff5ccc92b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2164651954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.2164651954
Directory /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1583348488
Short name T593
Test name
Test status
Simulation time 2205254260 ps
CPU time 231.61 seconds
Started Aug 04 07:22:06 PM PDT 24
Finished Aug 04 07:25:57 PM PDT 24
Peak memory 609724 kb
Host smart-83b54998-499f-46f0-8151-06f479c0efd5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583348488 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.chip_sw_rstmgr_smoketest.1583348488
Directory /workspace/0.chip_sw_rstmgr_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2741152920
Short name T523
Test name
Test status
Simulation time 4673218232 ps
CPU time 306.61 seconds
Started Aug 04 07:13:42 PM PDT 24
Finished Aug 04 07:18:49 PM PDT 24
Peak memory 610396 kb
Host smart-412e8198-d17e-4fa7-8a03-b48718ea3ea3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741152920 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_rstmgr_sw_req.2741152920
Directory /workspace/0.chip_sw_rstmgr_sw_req/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1654839483
Short name T680
Test name
Test status
Simulation time 3082878400 ps
CPU time 352.9 seconds
Started Aug 04 07:15:17 PM PDT 24
Finished Aug 04 07:21:10 PM PDT 24
Peak memory 609860 kb
Host smart-2aa6cd3a-2573-4be5-8574-85a907d59b67
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654839483 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.1654839483
Directory /workspace/0.chip_sw_rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3178819603
Short name T313
Test name
Test status
Simulation time 3465405110 ps
CPU time 249.59 seconds
Started Aug 04 07:18:19 PM PDT 24
Finished Aug 04 07:22:29 PM PDT 24
Peak memory 609784 kb
Host smart-09aab58e-7cd0-46c4-a35a-882e60ed1a1a
User root
Command /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3178819603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.3178819603
Directory /workspace/0.chip_sw_rv_core_ibex_address_translation/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1003370184
Short name T314
Test name
Test status
Simulation time 3222088250 ps
CPU time 307.68 seconds
Started Aug 04 07:17:04 PM PDT 24
Finished Aug 04 07:22:12 PM PDT 24
Peak memory 609504 kb
Host smart-3926abfb-512d-41e4-b24d-4f58f8515886
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003370184 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.1003370184
Directory /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2575754145
Short name T681
Test name
Test status
Simulation time 5685951184 ps
CPU time 957.43 seconds
Started Aug 04 07:14:54 PM PDT 24
Finished Aug 04 07:30:52 PM PDT 24
Peak memory 610008 kb
Host smart-9be21a81-8883-4652-82e7-e92638123582
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2575754145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.2575754145
Directory /workspace/0.chip_sw_rv_core_ibex_rnd/latest

Test location /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2908235782
Short name T1011
Test name
Test status
Simulation time 6000281200 ps
CPU time 612.71 seconds
Started Aug 04 07:18:38 PM PDT 24
Finished Aug 04 07:28:52 PM PDT 24
Peak memory 620244 kb
Host smart-ea45b1b0-231d-4a70-a11c-85b00bef2af8
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908235782 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.2908235782
Directory /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest

Test location /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2571527005
Short name T893
Test name
Test status
Simulation time 2489402880 ps
CPU time 306.12 seconds
Started Aug 04 07:21:59 PM PDT 24
Finished Aug 04 07:27:05 PM PDT 24
Peak memory 609616 kb
Host smart-6a4178f8-cf82-498f-b3c8-936dae052b23
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571527005 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_rv_plic_smoketest.2571527005
Directory /workspace/0.chip_sw_rv_plic_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_rv_timer_irq.1973555032
Short name T968
Test name
Test status
Simulation time 3303140680 ps
CPU time 254.97 seconds
Started Aug 04 07:16:05 PM PDT 24
Finished Aug 04 07:20:21 PM PDT 24
Peak memory 608448 kb
Host smart-6ed1d2d4-a67a-41de-b6a4-49924183614e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973555032 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_rv_timer_irq.1973555032
Directory /workspace/0.chip_sw_rv_timer_irq/latest

Test location /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2157537855
Short name T880
Test name
Test status
Simulation time 2621667360 ps
CPU time 241.03 seconds
Started Aug 04 07:21:26 PM PDT 24
Finished Aug 04 07:25:27 PM PDT 24
Peak memory 609560 kb
Host smart-b7c0537a-1cec-4c46-bc29-4fb40e855f69
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157537855 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_rv_timer_smoketest.2157537855
Directory /workspace/0.chip_sw_rv_timer_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.266162179
Short name T57
Test name
Test status
Simulation time 3259675387 ps
CPU time 247.26 seconds
Started Aug 04 07:17:53 PM PDT 24
Finished Aug 04 07:22:00 PM PDT 24
Peak memory 609752 kb
Host smart-5092b5cc-516a-45a0-8d35-b3ec2c2b37c2
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661621
79 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.266162179
Directory /workspace/0.chip_sw_sensor_ctrl_status/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pin_retention.490695264
Short name T25
Test name
Test status
Simulation time 3376778280 ps
CPU time 223.72 seconds
Started Aug 04 07:13:17 PM PDT 24
Finished Aug 04 07:17:01 PM PDT 24
Peak memory 610136 kb
Host smart-bce64b0a-690f-48c7-8a8d-097f31414a4d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490695264 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.490695264
Directory /workspace/0.chip_sw_sleep_pin_retention/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3158400392
Short name T111
Test name
Test status
Simulation time 6538976648 ps
CPU time 454.08 seconds
Started Aug 04 07:14:18 PM PDT 24
Finished Aug 04 07:21:53 PM PDT 24
Peak memory 610908 kb
Host smart-0ab5acb6-50d8-4e95-97ff-ed907a1239f4
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158400392
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.3158400392
Directory /workspace/0.chip_sw_sleep_pin_wake/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.663837157
Short name T336
Test name
Test status
Simulation time 8992913480 ps
CPU time 1436.35 seconds
Started Aug 04 07:13:20 PM PDT 24
Finished Aug 04 07:37:16 PM PDT 24
Peak memory 610788 kb
Host smart-2237c23b-ea11-4211-a72b-ae75c8691062
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663837157 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.663837157
Directory /workspace/0.chip_sw_sleep_pwm_pulses/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2343072546
Short name T929
Test name
Test status
Simulation time 6790318750 ps
CPU time 649.32 seconds
Started Aug 04 07:18:10 PM PDT 24
Finished Aug 04 07:28:59 PM PDT 24
Peak memory 610680 kb
Host smart-a59f117a-1f7c-44b5-8c64-f2a9c2d5e17f
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343072546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl
eep_sram_ret_contents_no_scramble.2343072546
Directory /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_pass_through.3314306223
Short name T43
Test name
Test status
Simulation time 8670344590 ps
CPU time 796.37 seconds
Started Aug 04 07:14:00 PM PDT 24
Finished Aug 04 07:27:16 PM PDT 24
Peak memory 624844 kb
Host smart-b199c65a-1985-43b9-b1f5-2275dd709eb9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314306223 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.3314306223
Directory /workspace/0.chip_sw_spi_device_pass_through/latest

Test location /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2388646875
Short name T35
Test name
Test status
Simulation time 2847087606 ps
CPU time 309.92 seconds
Started Aug 04 07:14:25 PM PDT 24
Finished Aug 04 07:19:36 PM PDT 24
Peak memory 610152 kb
Host smart-f065e46a-9b86-435e-8d93-ce9534d52af4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388646875 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.2388646875
Directory /workspace/0.chip_sw_spi_host_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3812774291
Short name T296
Test name
Test status
Simulation time 4698961595 ps
CPU time 683.13 seconds
Started Aug 04 07:16:14 PM PDT 24
Finished Aug 04 07:27:38 PM PDT 24
Peak memory 611120 kb
Host smart-a2f3afd6-fc66-4aae-b46a-863f696d7741
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s
w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812774291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3812774291
Directory /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.512067268
Short name T798
Test name
Test status
Simulation time 3642741735 ps
CPU time 471.53 seconds
Started Aug 04 07:16:43 PM PDT 24
Finished Aug 04 07:24:35 PM PDT 24
Peak memory 610580 kb
Host smart-0ceb53bb-7b16-4246-b47f-0161dfa24c0e
User root
Command /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk
_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512067268 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.512067268
Directory /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3688498224
Short name T964
Test name
Test status
Simulation time 2836618560 ps
CPU time 239.82 seconds
Started Aug 04 07:19:50 PM PDT 24
Finished Aug 04 07:23:50 PM PDT 24
Peak memory 609544 kb
Host smart-f950fb51-81f9-4367-811b-74e81710fc66
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688498224 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.3688498224
Directory /workspace/0.chip_sw_sram_ctrl_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2000721905
Short name T21
Test name
Test status
Simulation time 19997766932 ps
CPU time 3393.78 seconds
Started Aug 04 07:14:37 PM PDT 24
Finished Aug 04 08:11:11 PM PDT 24
Peak memory 610524 kb
Host smart-f3c6d187-0914-4d22-aaff-db0666800c03
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000721905 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.2000721905
Directory /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1572614392
Short name T839
Test name
Test status
Simulation time 4711734838 ps
CPU time 615.68 seconds
Started Aug 04 07:14:44 PM PDT 24
Finished Aug 04 07:25:01 PM PDT 24
Peak memory 614636 kb
Host smart-c8a1b25b-ad68-49ec-8ee3-cc83fca757f9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572614392 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.1572614392
Directory /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.569102042
Short name T244
Test name
Test status
Simulation time 2462904773 ps
CPU time 242.83 seconds
Started Aug 04 07:14:56 PM PDT 24
Finished Aug 04 07:18:59 PM PDT 24
Peak memory 613008 kb
Host smart-e14b1f7b-dcbc-4de1-a9b1-401f056cf4f6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569102042 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.569102042
Directory /workspace/0.chip_sw_sysrst_ctrl_inputs/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.295916258
Short name T246
Test name
Test status
Simulation time 24163807882 ps
CPU time 1648.78 seconds
Started Aug 04 07:15:25 PM PDT 24
Finished Aug 04 07:42:55 PM PDT 24
Peak memory 614152 kb
Host smart-951fcb54-09df-4df5-bbcb-5f4a7d1427e3
User root
Command /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29591625
8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.295916258
Directory /workspace/0.chip_sw_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/0.chip_sw_uart_smoketest.1236690520
Short name T131
Test name
Test status
Simulation time 3148701704 ps
CPU time 268.85 seconds
Started Aug 04 07:20:33 PM PDT 24
Finished Aug 04 07:25:02 PM PDT 24
Peak memory 610040 kb
Host smart-54c4c1e0-9667-428d-a266-e0dd337e8c37
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236690520 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_sw_uart_smoketest.1236690520
Directory /workspace/0.chip_sw_uart_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2645477750
Short name T846
Test name
Test status
Simulation time 3758025241 ps
CPU time 546.54 seconds
Started Aug 04 07:13:30 PM PDT 24
Finished Aug 04 07:22:37 PM PDT 24
Peak memory 623480 kb
Host smart-feee0339-1d25-4417-8e83-10923ac8cdb5
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645477750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx
_alt_clk_freq.2645477750
Directory /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.985568097
Short name T957
Test name
Test status
Simulation time 4604915224 ps
CPU time 615.08 seconds
Started Aug 04 07:13:32 PM PDT 24
Finished Aug 04 07:23:47 PM PDT 24
Peak memory 624220 kb
Host smart-26979ea0-f4af-4a65-b56a-476837d84783
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985568097 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.985568097
Directory /workspace/0.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2735946230
Short name T586
Test name
Test status
Simulation time 4308976620 ps
CPU time 575.17 seconds
Started Aug 04 07:13:23 PM PDT 24
Finished Aug 04 07:22:59 PM PDT 24
Peak memory 624256 kb
Host smart-d19d846d-365c-4342-9e2f-42496c4b8d1d
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735946230 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.2735946230
Directory /workspace/0.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2337820498
Short name T322
Test name
Test status
Simulation time 3496379696 ps
CPU time 485.36 seconds
Started Aug 04 07:13:21 PM PDT 24
Finished Aug 04 07:21:27 PM PDT 24
Peak memory 623948 kb
Host smart-30bddda1-720d-41a9-98ed-011175380561
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337820498 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.2337820498
Directory /workspace/0.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2409099057
Short name T413
Test name
Test status
Simulation time 2383589932 ps
CPU time 300.42 seconds
Started Aug 04 07:19:16 PM PDT 24
Finished Aug 04 07:24:17 PM PDT 24
Peak memory 609028 kb
Host smart-dc2d1503-8a84-4e73-9ec2-55ec64be005c
User root
Command /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409099057
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.2409099057
Directory /workspace/0.chip_sw_usb_ast_clk_calib/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_config_host.2122276270
Short name T19
Test name
Test status
Simulation time 8006474478 ps
CPU time 1889.29 seconds
Started Aug 04 07:13:56 PM PDT 24
Finished Aug 04 07:45:26 PM PDT 24
Peak memory 608868 kb
Host smart-4c7b9aee-0086-4d89-ae5d-a22e677c5ab8
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21222
76270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.2122276270
Directory /workspace/0.chip_sw_usbdev_config_host/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_dpi.799633726
Short name T837
Test name
Test status
Simulation time 12878538536 ps
CPU time 3264.19 seconds
Started Aug 04 07:14:54 PM PDT 24
Finished Aug 04 08:09:18 PM PDT 24
Peak memory 609108 kb
Host smart-465046bd-6dfb-407c-8ed6-b7f64ef380e0
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=799633726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.799633726
Directory /workspace/0.chip_sw_usbdev_dpi/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_pullup.2383400639
Short name T122
Test name
Test status
Simulation time 3024142672 ps
CPU time 289.48 seconds
Started Aug 04 07:15:04 PM PDT 24
Finished Aug 04 07:19:54 PM PDT 24
Peak memory 608588 kb
Host smart-812259ad-969c-4b42-99fb-55a4f4ea22a7
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383400639
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.2383400639
Directory /workspace/0.chip_sw_usbdev_pullup/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_setuprx.3024979196
Short name T70
Test name
Test status
Simulation time 4253176120 ps
CPU time 578.5 seconds
Started Aug 04 07:13:54 PM PDT 24
Finished Aug 04 07:23:33 PM PDT 24
Peak memory 609764 kb
Host smart-f574f321-faa9-4b1e-ba80-5a3ca81ed48d
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302497919
6 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.3024979196
Directory /workspace/0.chip_sw_usbdev_setuprx/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_stream.2897519273
Short name T23
Test name
Test status
Simulation time 18302598694 ps
CPU time 4905.01 seconds
Started Aug 04 07:14:09 PM PDT 24
Finished Aug 04 08:35:55 PM PDT 24
Peak memory 609244 kb
Host smart-3d3692e7-e936-4729-a39b-f4a4e953d1ab
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru
les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2897519273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.2897519273
Directory /workspace/0.chip_sw_usbdev_stream/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_vbus.3534931355
Short name T546
Test name
Test status
Simulation time 3055908714 ps
CPU time 232.81 seconds
Started Aug 04 07:15:49 PM PDT 24
Finished Aug 04 07:19:42 PM PDT 24
Peak memory 608676 kb
Host smart-a6a7404f-82cb-423f-ba69-7686498507a7
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534931355 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.3534931355
Directory /workspace/0.chip_sw_usbdev_vbus/latest

Test location /workspace/coverage/default/0.chip_tap_straps_dev.3366300527
Short name T120
Test name
Test status
Simulation time 12913073075 ps
CPU time 1266 seconds
Started Aug 04 07:16:02 PM PDT 24
Finished Aug 04 07:37:09 PM PDT 24
Peak memory 625116 kb
Host smart-de2a5898-295f-450a-95c4-bcc4eb6abc98
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3366300527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.3366300527
Directory /workspace/0.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/0.chip_tap_straps_prod.568117758
Short name T943
Test name
Test status
Simulation time 10980890011 ps
CPU time 1209.42 seconds
Started Aug 04 07:15:32 PM PDT 24
Finished Aug 04 07:35:41 PM PDT 24
Peak memory 624484 kb
Host smart-c3b01d7e-19d3-4021-a560-029756e70cab
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=568117758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.568117758
Directory /workspace/0.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/0.chip_tap_straps_testunlock0.331054659
Short name T118
Test name
Test status
Simulation time 5967565388 ps
CPU time 458.54 seconds
Started Aug 04 07:15:45 PM PDT 24
Finished Aug 04 07:23:26 PM PDT 24
Peak memory 633100 kb
Host smart-4c7a8b2f-c8cd-472e-9623-7741c9eccb14
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331054659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.331054659
Directory /workspace/0.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_dev.3006929654
Short name T355
Test name
Test status
Simulation time 15306353864 ps
CPU time 4228.15 seconds
Started Aug 04 07:23:14 PM PDT 24
Finished Aug 04 08:33:43 PM PDT 24
Peak memory 610252 kb
Host smart-f2d4ca58-3192-4310-bc6c-b5ba1ee41034
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006929654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rom_e2e_asm_init_dev.3006929654
Directory /workspace/0.rom_e2e_asm_init_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_prod.1178286746
Short name T652
Test name
Test status
Simulation time 15834022366 ps
CPU time 3925.38 seconds
Started Aug 04 07:25:55 PM PDT 24
Finished Aug 04 08:31:21 PM PDT 24
Peak memory 610112 kb
Host smart-cc6af969-2294-4c90-b5c5-9f846cea7502
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178286746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_
SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rom_e2e_asm_init_prod.1178286746
Directory /workspace/0.rom_e2e_asm_init_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1249231448
Short name T401
Test name
Test status
Simulation time 15827431699 ps
CPU time 4279.66 seconds
Started Aug 04 07:25:23 PM PDT 24
Finished Aug 04 08:36:43 PM PDT 24
Peak memory 611220 kb
Host smart-f55e2888-940f-47fb-916d-122169541e58
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249231448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_e2e_asm_init_prod_end.1249231448
Directory /workspace/0.rom_e2e_asm_init_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_rma.741003287
Short name T963
Test name
Test status
Simulation time 14790401264 ps
CPU time 4105.86 seconds
Started Aug 04 07:22:45 PM PDT 24
Finished Aug 04 08:31:12 PM PDT 24
Peak memory 610312 kb
Host smart-dc168495-488d-447e-b133-f6e4d2b16d88
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741003287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rom_e2e_asm_init_rma.741003287
Directory /workspace/0.rom_e2e_asm_init_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.260056300
Short name T563
Test name
Test status
Simulation time 10750494161 ps
CPU time 3510.6 seconds
Started Aug 04 07:22:53 PM PDT 24
Finished Aug 04 08:21:24 PM PDT 24
Peak memory 610612 kb
Host smart-5b51a6eb-c182-4f33-a960-8faf866dbce7
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260056300 -assert nopostproc +UVM_TESTNAME=chip_base_tes
t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.rom_e2e_asm_init_test_unlocked0.260056300
Directory /workspace/0.rom_e2e_asm_init_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2451232155
Short name T265
Test name
Test status
Simulation time 23764678460 ps
CPU time 5562.23 seconds
Started Aug 04 07:21:55 PM PDT 24
Finished Aug 04 08:54:38 PM PDT 24
Peak memory 609472 kb
Host smart-eac1de1b-704f-47e4-9f15-eaad2baa74ea
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2451232155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2451232155
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1621047547
Short name T770
Test name
Test status
Simulation time 24356081136 ps
CPU time 7337.66 seconds
Started Aug 04 07:26:58 PM PDT 24
Finished Aug 04 09:29:17 PM PDT 24
Peak memory 610148 kb
Host smart-ba63f4ea-ecf3-4803-a398-0dedfb26697b
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1621047547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1621047547
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3011623304
Short name T266
Test name
Test status
Simulation time 23870145480 ps
CPU time 5991.48 seconds
Started Aug 04 07:23:38 PM PDT 24
Finished Aug 04 09:03:30 PM PDT 24
Peak memory 609984 kb
Host smart-2c65bfeb-9c68-404c-95cd-9b04b799790c
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3011623304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3011623304
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.895290812
Short name T267
Test name
Test status
Simulation time 17937600468 ps
CPU time 5044.34 seconds
Started Aug 04 07:23:09 PM PDT 24
Finished Aug 04 08:47:14 PM PDT 24
Peak memory 610092 kb
Host smart-abf86df4-b26d-4875-b168-0b7efac9c2f2
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,
mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=895290812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.895290812
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.436557506
Short name T538
Test name
Test status
Simulation time 15859587700 ps
CPU time 4856.08 seconds
Started Aug 04 07:26:36 PM PDT 24
Finished Aug 04 08:47:32 PM PDT 24
Peak memory 610160 kb
Host smart-45943b98-ca3b-4862-a734-2ceffaf3e2b7
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=436557506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.436557506
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2174562228
Short name T781
Test name
Test status
Simulation time 15178422264 ps
CPU time 3842.93 seconds
Started Aug 04 07:22:06 PM PDT 24
Finished Aug 04 08:26:10 PM PDT 24
Peak memory 610188 kb
Host smart-0b56caac-17c2-4f04-8661-6f6d10a1db43
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2174562228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2174562228
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.658873402
Short name T975
Test name
Test status
Simulation time 15069043222 ps
CPU time 3924.32 seconds
Started Aug 04 07:26:13 PM PDT 24
Finished Aug 04 08:31:38 PM PDT 24
Peak memory 610276 kb
Host smart-559243a5-5864-4aa9-a1f6-77e5fe085a60
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=658873402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.658873402
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3895479759
Short name T872
Test name
Test status
Simulation time 15440248312 ps
CPU time 3661.69 seconds
Started Aug 04 07:23:00 PM PDT 24
Finished Aug 04 08:24:03 PM PDT 24
Peak memory 609896 kb
Host smart-549a8f37-a3ad-4b96-b929-ab851454ac08
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3895479759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3895479759
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2567021663
Short name T556
Test name
Test status
Simulation time 11510526910 ps
CPU time 3474.32 seconds
Started Aug 04 07:26:00 PM PDT 24
Finished Aug 04 08:23:55 PM PDT 24
Peak memory 610184 kb
Host smart-c200ca45-2642-44f5-8ae4-a2127e076faf
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4,
mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2567021663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2567021663
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1486636621
Short name T628
Test name
Test status
Simulation time 15264532184 ps
CPU time 5098.38 seconds
Started Aug 04 07:26:28 PM PDT 24
Finished Aug 04 08:51:28 PM PDT 24
Peak memory 610208 kb
Host smart-e5a2d067-e910-4b97-9a9e-4d57f1586408
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486636621
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1486636621
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3353910121
Short name T789
Test name
Test status
Simulation time 15180275128 ps
CPU time 3952.37 seconds
Started Aug 04 07:21:33 PM PDT 24
Finished Aug 04 08:27:26 PM PDT 24
Peak memory 610176 kb
Host smart-62194757-85e9-4548-8431-d2dee75f5540
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353910121
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3353910121
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1198270399
Short name T714
Test name
Test status
Simulation time 15107589762 ps
CPU time 4117.64 seconds
Started Aug 04 07:23:15 PM PDT 24
Finished Aug 04 08:31:53 PM PDT 24
Peak memory 610204 kb
Host smart-d86a4f46-5668-408c-ae30-dee27c95b010
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119827
0399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1198270399
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1370754161
Short name T601
Test name
Test status
Simulation time 14602125076 ps
CPU time 3463.38 seconds
Started Aug 04 07:23:51 PM PDT 24
Finished Aug 04 08:21:35 PM PDT 24
Peak memory 610264 kb
Host smart-add6d214-49cb-41ed-b1de-8df2d2d076e6
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370754161
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1370754161
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.1891223626
Short name T920
Test name
Test status
Simulation time 10666836139 ps
CPU time 2396.78 seconds
Started Aug 04 07:18:52 PM PDT 24
Finished Aug 04 07:58:50 PM PDT 24
Peak memory 624536 kb
Host smart-3f7e194f-5199-4822-ad8a-b681cad0f8f5
User root
Command /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18912
23626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.1891223626
Directory /workspace/0.rom_e2e_jtag_debug_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2605217800
Short name T319
Test name
Test status
Simulation time 10301729686 ps
CPU time 2085.23 seconds
Started Aug 04 07:19:43 PM PDT 24
Finished Aug 04 07:54:29 PM PDT 24
Peak memory 624356 kb
Host smart-0e927b98-aac6-4d60-9db4-04d4b03ace6e
User root
Command /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2605217800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.2605217800
Directory /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2706974669
Short name T331
Test name
Test status
Simulation time 24634593438 ps
CPU time 2300.8 seconds
Started Aug 04 07:20:39 PM PDT 24
Finished Aug 04 07:59:01 PM PDT 24
Peak memory 623880 kb
Host smart-b2568e1b-dec7-4a7b-a98b-c03d31536799
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di
sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2706974669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.2706974669
Directory /workspace/0.rom_e2e_jtag_inject_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2062866733
Short name T114
Test name
Test status
Simulation time 32404395185 ps
CPU time 3005.53 seconds
Started Aug 04 07:21:00 PM PDT 24
Finished Aug 04 08:11:06 PM PDT 24
Peak memory 623904 kb
Host smart-f31c44a3-60dc-4877-9a47-859cf3f79b30
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di
sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2062866733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.2062866733
Directory /workspace/0.rom_e2e_jtag_inject_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.3196354772
Short name T152
Test name
Test status
Simulation time 24921392974 ps
CPU time 2038.97 seconds
Started Aug 04 07:21:15 PM PDT 24
Finished Aug 04 07:55:15 PM PDT 24
Peak memory 620396 kb
Host smart-6fcb4e7d-4fce-476e-8e30-632bff83cd19
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock
ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196354772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_
inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject
_test_unlocked0.3196354772
Directory /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.902885251
Short name T998
Test name
Test status
Simulation time 14597257842 ps
CPU time 3897.91 seconds
Started Aug 04 07:25:41 PM PDT 24
Finished Aug 04 08:30:39 PM PDT 24
Peak memory 610204 kb
Host smart-098f53ba-0dcd-4729-bf40-83e2d3dc04f3
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid
_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902885251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_ini
t_rom_ext_invalid_meas.902885251
Directory /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2198218960
Short name T919
Test name
Test status
Simulation time 14659354700 ps
CPU time 4073.13 seconds
Started Aug 04 07:25:30 PM PDT 24
Finished Aug 04 08:33:24 PM PDT 24
Peak memory 610184 kb
Host smart-07b2ac50-cd30-4228-b57c-30902984b287
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:
new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198218960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.2198218960
Directory /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2369988242
Short name T535
Test name
Test status
Simulation time 14726829262 ps
CPU time 3781.87 seconds
Started Aug 04 07:23:50 PM PDT 24
Finished Aug 04 08:26:52 PM PDT 24
Peak memory 609880 kb
Host smart-58a7df35-a107-4f24-b26a-2e3e15527c8c
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas
:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369988242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext
_no_meas.2369988242
Directory /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location /workspace/coverage/default/0.rom_e2e_self_hash.3498047101
Short name T584
Test name
Test status
Simulation time 27003116002 ps
CPU time 5612.81 seconds
Started Aug 04 07:23:37 PM PDT 24
Finished Aug 04 08:57:11 PM PDT 24
Peak memory 610084 kb
Host smart-a08d95cf-7bf5-43a4-b297-c5f3dc9a3ede
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r
ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498047101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.3498047101
Directory /workspace/0.rom_e2e_self_hash/latest

Test location /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3612551864
Short name T826
Test name
Test status
Simulation time 15573910530 ps
CPU time 3711.83 seconds
Started Aug 04 07:20:39 PM PDT 24
Finished Aug 04 08:22:31 PM PDT 24
Peak memory 611132 kb
Host smart-e1cbb182-d882-45e8-84d7-5ef365722a9e
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne
w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612551864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu
tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_
shutdown_exception_c.3612551864
Directory /workspace/0.rom_e2e_shutdown_exception_c/latest

Test location /workspace/coverage/default/0.rom_e2e_shutdown_output.3794753600
Short name T778
Test name
Test status
Simulation time 22948228816 ps
CPU time 3807.52 seconds
Started Aug 04 07:24:26 PM PDT 24
Finished Aug 04 08:27:54 PM PDT 24
Peak memory 611536 kb
Host smart-b0c43a25-efc1-4066-8474-f78bb5923fa0
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f
lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794753600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rom_e2e_shutdown_output.3794753600
Directory /workspace/0.rom_e2e_shutdown_output/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2374322662
Short name T356
Test name
Test status
Simulation time 22915912320 ps
CPU time 5563.01 seconds
Started Aug 04 07:21:48 PM PDT 24
Finished Aug 04 08:54:32 PM PDT 24
Peak memory 610408 kb
Host smart-554b1252-edfc-42cf-99a4-12dc5ce0fbec
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev
:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2374322662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b
ad_dev.2374322662
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1963870221
Short name T1015
Test name
Test status
Simulation time 23826981368 ps
CPU time 5997.12 seconds
Started Aug 04 07:24:31 PM PDT 24
Finished Aug 04 09:04:29 PM PDT 24
Peak memory 609380 kb
Host smart-bb0f90bb-9f9f-4cb4-9886-b60174011766
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p
rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1963870221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_
b_bad_prod.1963870221
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3067927977
Short name T911
Test name
Test status
Simulation time 23117645075 ps
CPU time 5652.32 seconds
Started Aug 04 07:22:54 PM PDT 24
Finished Aug 04 08:57:07 PM PDT 24
Peak memory 609276 kb
Host smart-c0c57be4-0695-4a0c-8001-6f930f0ebfec
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p
rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=3067927977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_
bad_b_bad_prod_end.3067927977
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.611236991
Short name T47
Test name
Test status
Simulation time 22589136855 ps
CPU time 5264.03 seconds
Started Aug 04 07:24:45 PM PDT 24
Finished Aug 04 08:52:29 PM PDT 24
Peak memory 609432 kb
Host smart-ad5c15cc-b33d-4c40-be2e-f317febe6dd9
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r
ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=611236991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_
bad_rma.611236991
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.4142033641
Short name T539
Test name
Test status
Simulation time 17566749709 ps
CPU time 4872.14 seconds
Started Aug 04 07:22:39 PM PDT 24
Finished Aug 04 08:43:52 PM PDT 24
Peak memory 610520 kb
Host smart-e3145743-ea4a-4ea3-b83a-65dd655935b0
User root
Command /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t
est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4142033641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b
_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw
ays_a_bad_b_bad_test_unlocked0.4142033641
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.4103036536
Short name T1018
Test name
Test status
Simulation time 14811728840 ps
CPU time 4184.77 seconds
Started Aug 04 07:22:35 PM PDT 24
Finished Aug 04 08:32:20 PM PDT 24
Peak memory 610416 kb
Host smart-ddb0e712-0cc0-4af9-9717-e98cc6adcd83
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103036536 -assert nopostproc +UVM_TESTNAME=chip_base_
test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.4103036536
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1864527997
Short name T888
Test name
Test status
Simulation time 14280350635 ps
CPU time 3946.58 seconds
Started Aug 04 07:21:47 PM PDT 24
Finished Aug 04 08:27:34 PM PDT 24
Peak memory 610152 kb
Host smart-db19a680-f4f0-4f21-8259-da6d7a7734fa
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864527997 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1864527997
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3974993278
Short name T48
Test name
Test status
Simulation time 14310674727 ps
CPU time 3607.85 seconds
Started Aug 04 07:23:35 PM PDT 24
Finished Aug 04 08:23:43 PM PDT 24
Peak memory 610428 kb
Host smart-748d9b95-8f14-4ba2-8dbd-509296998288
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974993278 -assert nopostproc +UVM_TESTNAME=chip_base
_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3974993278
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.15270768
Short name T927
Test name
Test status
Simulation time 10758353680 ps
CPU time 3025.9 seconds
Started Aug 04 07:22:10 PM PDT 24
Finished Aug 04 08:12:37 PM PDT 24
Peak memory 610472 kb
Host smart-bacf4f6e-bae0-416b-a70d-b5cd8cdeb21e
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15270768 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.15270768
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3165856
Short name T582
Test name
Test status
Simulation time 14815540252 ps
CPU time 4059.94 seconds
Started Aug 04 07:22:10 PM PDT 24
Finished Aug 04 08:29:51 PM PDT 24
Peak memory 609372 kb
Host smart-2c297293-4c77-4cc0-b3b9-62f5e595f42d
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165856 -assert nopostproc +UVM_TESTNAME=chip_base_tes
t +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3165856
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1855959179
Short name T887
Test name
Test status
Simulation time 15387310810 ps
CPU time 4157.12 seconds
Started Aug 04 07:20:48 PM PDT 24
Finished Aug 04 08:30:06 PM PDT 24
Peak memory 610296 kb
Host smart-be6313e1-4049-4a85-a523-cdcb299096cc
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855959179 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1855959179
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1932399494
Short name T285
Test name
Test status
Simulation time 14520080332 ps
CPU time 3752.75 seconds
Started Aug 04 07:24:57 PM PDT 24
Finished Aug 04 08:27:31 PM PDT 24
Peak memory 611276 kb
Host smart-1d5925e9-b7f9-49da-a98d-88ef450f3f50
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932399494 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1932399494
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2521421647
Short name T651
Test name
Test status
Simulation time 14409619571 ps
CPU time 3380.91 seconds
Started Aug 04 07:22:48 PM PDT 24
Finished Aug 04 08:19:10 PM PDT 24
Peak memory 609180 kb
Host smart-7b706e6c-d3ff-463e-bb98-8c09c481a974
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521421647 -assert nopostproc +UVM_TESTNAME=chip_base
_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2521421647
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2881528499
Short name T982
Test name
Test status
Simulation time 10523436957 ps
CPU time 3460.58 seconds
Started Aug 04 07:25:56 PM PDT 24
Finished Aug 04 08:23:37 PM PDT 24
Peak memory 610464 kb
Host smart-344edeff-6e8c-4d49-8762-37d9e5f721c4
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881528499 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2881528499
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_smoke.1225211199
Short name T939
Test name
Test status
Simulation time 14729620816 ps
CPU time 5151.65 seconds
Started Aug 04 07:25:48 PM PDT 24
Finished Aug 04 08:51:41 PM PDT 24
Peak memory 610136 kb
Host smart-2948f52e-fd9a-4541-aa4d-241e2b874f8f
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img
_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to
p/hw/dv/tools/sim.tcl +ntb_random_seed=1225211199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.1225211199
Directory /workspace/0.rom_e2e_smoke/latest

Test location /workspace/coverage/default/0.rom_e2e_static_critical.2975491646
Short name T923
Test name
Test status
Simulation time 16989771050 ps
CPU time 4210.53 seconds
Started Aug 04 07:24:16 PM PDT 24
Finished Aug 04 08:34:27 PM PDT 24
Peak memory 609852 kb
Host smart-93797d3e-df93-4162-9cb4-22987649f883
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul
es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975491646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.2975491646
Directory /workspace/0.rom_e2e_static_critical/latest

Test location /workspace/coverage/default/0.rom_keymgr_functest.2449385504
Short name T577
Test name
Test status
Simulation time 4208541704 ps
CPU time 561.26 seconds
Started Aug 04 07:19:47 PM PDT 24
Finished Aug 04 07:29:09 PM PDT 24
Peak memory 610260 kb
Host smart-9af0cd40-eec8-44f3-be24-7232f48fae17
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449385504 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.2449385504
Directory /workspace/0.rom_keymgr_functest/latest

Test location /workspace/coverage/default/0.rom_volatile_raw_unlock.2709508790
Short name T425
Test name
Test status
Simulation time 2354124013 ps
CPU time 102.41 seconds
Started Aug 04 07:19:37 PM PDT 24
Finished Aug 04 07:21:20 PM PDT 24
Peak memory 616976 kb
Host smart-c3be9725-2b6e-4934-a89d-044fe1e9d69e
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1
+sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709508790 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.2709508790
Directory /workspace/0.rom_volatile_raw_unlock/latest

Test location /workspace/coverage/default/1.chip_jtag_mem_access.3191298987
Short name T150
Test name
Test status
Simulation time 13377419755 ps
CPU time 1602.97 seconds
Started Aug 04 07:24:34 PM PDT 24
Finished Aug 04 07:51:18 PM PDT 24
Peak memory 607924 kb
Host smart-003af662-2d7c-4fe1-884e-7c291b2e403e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191298987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_
mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.3
191298987
Directory /workspace/1.chip_jtag_mem_access/latest

Test location /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2852331946
Short name T148
Test name
Test status
Simulation time 4007756368 ps
CPU time 343.68 seconds
Started Aug 04 07:32:02 PM PDT 24
Finished Aug 04 07:37:46 PM PDT 24
Peak memory 620056 kb
Host smart-33f9cba3-2e7b-489c-8b83-2fc4ab29cf3b
User root
Command /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2
852331946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.2852331946
Directory /workspace/1.chip_rv_dm_ndm_reset_req/latest

Test location /workspace/coverage/default/1.chip_sival_flash_info_access.3881286939
Short name T204
Test name
Test status
Simulation time 3908084400 ps
CPU time 252.65 seconds
Started Aug 04 07:21:39 PM PDT 24
Finished Aug 04 07:25:52 PM PDT 24
Peak memory 610000 kb
Host smart-97529546-7fc8-49ea-be74-3bb4839645b7
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=3881286939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.3881286939
Directory /workspace/1.chip_sival_flash_info_access/latest

Test location /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2918934659
Short name T332
Test name
Test status
Simulation time 19378822552 ps
CPU time 676.28 seconds
Started Aug 04 07:28:06 PM PDT 24
Finished Aug 04 07:39:23 PM PDT 24
Peak memory 619144 kb
Host smart-23912e3b-ab24-4b7d-a080-ad354e4a214c
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2918934659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2918934659
Directory /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_aes_enc.627914162
Short name T942
Test name
Test status
Simulation time 3177819614 ps
CPU time 358.58 seconds
Started Aug 04 07:29:32 PM PDT 24
Finished Aug 04 07:35:30 PM PDT 24
Peak memory 609428 kb
Host smart-8f34b9cd-db8a-4907-b28b-4d6e745b018b
User root
Command /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627914162 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.627914162
Directory /workspace/1.chip_sw_aes_enc/latest

Test location /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.513977273
Short name T769
Test name
Test status
Simulation time 3058587765 ps
CPU time 287.9 seconds
Started Aug 04 07:28:27 PM PDT 24
Finished Aug 04 07:33:15 PM PDT 24
Peak memory 608412 kb
Host smart-955e8571-8ac0-4b41-bb43-7ec191949b39
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5139
77273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.513977273
Directory /workspace/1.chip_sw_aes_enc_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2989406856
Short name T592
Test name
Test status
Simulation time 3309739728 ps
CPU time 337.92 seconds
Started Aug 04 07:32:55 PM PDT 24
Finished Aug 04 07:38:33 PM PDT 24
Peak memory 609744 kb
Host smart-0f16d86e-3955-4746-9a2d-cf3f5281070b
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2989406856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.2989406856
Directory /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_aes_entropy.2976777239
Short name T611
Test name
Test status
Simulation time 2778383032 ps
CPU time 194.24 seconds
Started Aug 04 07:29:15 PM PDT 24
Finished Aug 04 07:32:29 PM PDT 24
Peak memory 609220 kb
Host smart-505199d7-413b-4273-8ef6-0daed45a133f
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976777239 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.2976777239
Directory /workspace/1.chip_sw_aes_entropy/latest

Test location /workspace/coverage/default/1.chip_sw_aes_idle.955353330
Short name T783
Test name
Test status
Simulation time 2753597832 ps
CPU time 250.87 seconds
Started Aug 04 07:32:05 PM PDT 24
Finished Aug 04 07:36:16 PM PDT 24
Peak memory 609476 kb
Host smart-5a8b2f99-90e9-46ba-bb4a-7060c4a8ac3b
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955353330 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.955353330
Directory /workspace/1.chip_sw_aes_idle/latest

Test location /workspace/coverage/default/1.chip_sw_aes_masking_off.1697353593
Short name T590
Test name
Test status
Simulation time 3082875362 ps
CPU time 296.12 seconds
Started Aug 04 07:32:06 PM PDT 24
Finished Aug 04 07:37:02 PM PDT 24
Peak memory 610484 kb
Host smart-ec2df20b-d147-4638-8584-8657f036ef46
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697353593 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.1697353593
Directory /workspace/1.chip_sw_aes_masking_off/latest

Test location /workspace/coverage/default/1.chip_sw_aes_smoketest.2843401397
Short name T663
Test name
Test status
Simulation time 3373374422 ps
CPU time 329.31 seconds
Started Aug 04 07:33:58 PM PDT 24
Finished Aug 04 07:39:27 PM PDT 24
Peak memory 608460 kb
Host smart-0511d6b7-ea2f-4394-8be4-d8cf83569e3b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843401397 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_aes_smoketest.2843401397
Directory /workspace/1.chip_sw_aes_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_entropy.174400602
Short name T96
Test name
Test status
Simulation time 3893782787 ps
CPU time 396.12 seconds
Started Aug 04 07:29:22 PM PDT 24
Finished Aug 04 07:35:59 PM PDT 24
Peak memory 609520 kb
Host smart-8e077634-a3e2-4605-a2c1-924017d904c4
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=174400602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.174400602
Directory /workspace/1.chip_sw_alert_handler_entropy/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_escalation.2766211534
Short name T984
Test name
Test status
Simulation time 6078782872 ps
CPU time 497.49 seconds
Started Aug 04 07:32:02 PM PDT 24
Finished Aug 04 07:40:19 PM PDT 24
Peak memory 619660 kb
Host smart-8c3e8f4c-b944-4300-9504-99cb89ec7381
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=2766211534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.2766211534
Directory /workspace/1.chip_sw_alert_handler_escalation/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.677563867
Short name T851
Test name
Test status
Simulation time 9265511150 ps
CPU time 2128.53 seconds
Started Aug 04 07:29:24 PM PDT 24
Finished Aug 04 08:04:52 PM PDT 24
Peak memory 610280 kb
Host smart-7a46da95-e48c-448a-ab80-3742c592454c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=677563867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.677563867
Directory /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3491418503
Short name T98
Test name
Test status
Simulation time 8208044140 ps
CPU time 1970.11 seconds
Started Aug 04 07:28:52 PM PDT 24
Finished Aug 04 08:01:43 PM PDT 24
Peak memory 610224 kb
Host smart-d113a3b2-cde1-452d-b179-22a61e37eaef
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3491418503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg
le.3491418503
Directory /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2436759616
Short name T276
Test name
Test status
Simulation time 11208949900 ps
CPU time 1291.03 seconds
Started Aug 04 07:31:00 PM PDT 24
Finished Aug 04 07:52:31 PM PDT 24
Peak memory 610948 kb
Host smart-7751e2ce-e8c0-4b66-aad1-8badfcbde4e4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler
_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436759616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han
dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.chip_sw_alert_handler_lpg_sleep_mode_pings.2436759616
Directory /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.4026023316
Short name T841
Test name
Test status
Simulation time 7948159656 ps
CPU time 1701.48 seconds
Started Aug 04 07:28:44 PM PDT 24
Finished Aug 04 07:57:06 PM PDT 24
Peak memory 610088 kb
Host smart-1b02562b-0c92-4ad0-b444-127ff9ff37b1
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=4026023316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.4026023316
Directory /workspace/1.chip_sw_alert_handler_ping_ok/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2861106763
Short name T941
Test name
Test status
Simulation time 4656415944 ps
CPU time 544.65 seconds
Started Aug 04 07:28:36 PM PDT 24
Finished Aug 04 07:37:41 PM PDT 24
Peak memory 609880 kb
Host smart-1b2a65f5-ebe0-455c-b4ca-4e81560430ca
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2861106763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.2861106763
Directory /workspace/1.chip_sw_alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1972674667
Short name T1000
Test name
Test status
Simulation time 256307198512 ps
CPU time 13295.2 seconds
Started Aug 04 07:28:34 PM PDT 24
Finished Aug 04 11:10:10 PM PDT 24
Peak memory 610852 kb
Host smart-49525a98-b132-4aa0-86d3-c95806e2c922
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972674667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1972674667
Directory /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location /workspace/coverage/default/1.chip_sw_alert_test.1618890253
Short name T105
Test name
Test status
Simulation time 3177372346 ps
CPU time 289.98 seconds
Started Aug 04 07:27:55 PM PDT 24
Finished Aug 04 07:32:46 PM PDT 24
Peak memory 609928 kb
Host smart-65e1c0fc-3e54-4f8f-baa5-4ffad99e2f07
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618890253 -assert nopostproc +UVM_TESTNAME=chip_ba
se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.chip_sw_alert_test.1618890253
Directory /workspace/1.chip_sw_alert_test/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_irq.2921744801
Short name T728
Test name
Test status
Simulation time 3314445752 ps
CPU time 405.73 seconds
Started Aug 04 07:29:16 PM PDT 24
Finished Aug 04 07:36:01 PM PDT 24
Peak memory 609548 kb
Host smart-375d7ba7-55a8-4169-8e16-185fd91f70ec
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921744801 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.2921744801
Directory /workspace/1.chip_sw_aon_timer_irq/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2037225152
Short name T752
Test name
Test status
Simulation time 7111266744 ps
CPU time 420.85 seconds
Started Aug 04 07:27:44 PM PDT 24
Finished Aug 04 07:34:45 PM PDT 24
Peak memory 610552 kb
Host smart-1ce04a9f-e375-470d-8e3b-f6cf27d26c3c
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2037225152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2037225152
Directory /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2517625050
Short name T918
Test name
Test status
Simulation time 2927673136 ps
CPU time 331.63 seconds
Started Aug 04 07:34:04 PM PDT 24
Finished Aug 04 07:39:36 PM PDT 24
Peak memory 609640 kb
Host smart-7594153f-e47b-48fc-92ef-f5c779f1bbaa
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517625050 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_aon_timer_smoketest.2517625050
Directory /workspace/1.chip_sw_aon_timer_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.38992360
Short name T1016
Test name
Test status
Simulation time 7342705050 ps
CPU time 529.51 seconds
Started Aug 04 07:26:40 PM PDT 24
Finished Aug 04 07:35:29 PM PDT 24
Peak memory 609220 kb
Host smart-ccd5e84d-93c5-4736-b82e-910adf24284e
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
38992360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.38992360
Directory /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.661505830
Short name T956
Test name
Test status
Simulation time 5338247800 ps
CPU time 569.61 seconds
Started Aug 04 07:28:12 PM PDT 24
Finished Aug 04 07:37:42 PM PDT 24
Peak memory 610348 kb
Host smart-acd1bdbd-2193-47f2-963e-1739efff26d0
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=661505830 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.661505830
Directory /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2292541320
Short name T233
Test name
Test status
Simulation time 5340514212 ps
CPU time 506.3 seconds
Started Aug 04 07:31:52 PM PDT 24
Finished Aug 04 07:40:19 PM PDT 24
Peak memory 624588 kb
Host smart-69d5e9f6-8400-4193-8b00-ce5a8edf6827
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=2292541320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.2292541320
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.51345593
Short name T844
Test name
Test status
Simulation time 3751152140 ps
CPU time 591.61 seconds
Started Aug 04 07:33:48 PM PDT 24
Finished Aug 04 07:43:39 PM PDT 24
Peak memory 612076 kb
Host smart-1d68dde1-1226-4fd5-8ea2-576af4abde05
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51345593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clk
mgr_external_clk_src_for_sw_fast_dev.51345593
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2649431543
Short name T134
Test name
Test status
Simulation time 4373105784 ps
CPU time 636.96 seconds
Started Aug 04 07:31:12 PM PDT 24
Finished Aug 04 07:41:49 PM PDT 24
Peak memory 612140 kb
Host smart-be3bebcb-75ec-4260-a572-f1ad223a8d55
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649431543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_rma.2649431543
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.702705518
Short name T634
Test name
Test status
Simulation time 4273212926 ps
CPU time 714.01 seconds
Started Aug 04 07:30:44 PM PDT 24
Finished Aug 04 07:42:38 PM PDT 24
Peak memory 613144 kb
Host smart-4218734a-4e7b-4b22-aa9b-4ab135148af8
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702705518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM
_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.702705518
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4153670258
Short name T67
Test name
Test status
Simulation time 4239083272 ps
CPU time 602.94 seconds
Started Aug 04 07:31:46 PM PDT 24
Finished Aug 04 07:41:49 PM PDT 24
Peak memory 612924 kb
Host smart-58b71485-5c94-4ad0-9aca-3affa9ab3c4c
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153670258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_dev.4153670258
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3154297366
Short name T999
Test name
Test status
Simulation time 4871505496 ps
CPU time 867.58 seconds
Started Aug 04 07:30:51 PM PDT 24
Finished Aug 04 07:45:19 PM PDT 24
Peak memory 613168 kb
Host smart-e5eb4d28-fa7c-44bb-981c-059a73256d8d
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154297366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_rma.3154297366
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.470054061
Short name T977
Test name
Test status
Simulation time 4520310290 ps
CPU time 539.67 seconds
Started Aug 04 07:33:43 PM PDT 24
Finished Aug 04 07:42:43 PM PDT 24
Peak memory 613152 kb
Host smart-e117fbf9-a0f9-4d68-9ad5-aae1c4a00644
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470054061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM
_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.470054061
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_jitter.37385893
Short name T961
Test name
Test status
Simulation time 3636589664 ps
CPU time 258.42 seconds
Started Aug 04 07:32:19 PM PDT 24
Finished Aug 04 07:36:38 PM PDT 24
Peak memory 608408 kb
Host smart-0791507a-b764-4f15-8b19-999fc7a9b95f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37385893 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.chip_sw_clkmgr_jitter.37385893
Directory /workspace/1.chip_sw_clkmgr_jitter/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3748370581
Short name T865
Test name
Test status
Simulation time 3376438252 ps
CPU time 383.32 seconds
Started Aug 04 07:33:53 PM PDT 24
Finished Aug 04 07:40:16 PM PDT 24
Peak memory 609460 kb
Host smart-47b56bf0-560f-4994-9a2a-311edf72c97a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748370581 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.3748370581
Directory /workspace/1.chip_sw_clkmgr_jitter_frequency/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.747589178
Short name T629
Test name
Test status
Simulation time 2301667361 ps
CPU time 257.16 seconds
Started Aug 04 07:36:05 PM PDT 24
Finished Aug 04 07:40:24 PM PDT 24
Peak memory 609596 kb
Host smart-6eb72168-39c7-4ae8-aba4-d3fa8dc646f6
User root
Command /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747589178 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.747589178
Directory /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.789687577
Short name T965
Test name
Test status
Simulation time 4616094784 ps
CPU time 506.94 seconds
Started Aug 04 07:33:21 PM PDT 24
Finished Aug 04 07:41:49 PM PDT 24
Peak memory 610336 kb
Host smart-c6375b0b-ae30-4ca2-a3e3-cb619cc96282
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789687577 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.789687577
Directory /workspace/1.chip_sw_clkmgr_off_aes_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.4079324938
Short name T947
Test name
Test status
Simulation time 4604362616 ps
CPU time 382.48 seconds
Started Aug 04 07:31:54 PM PDT 24
Finished Aug 04 07:38:17 PM PDT 24
Peak memory 610384 kb
Host smart-2501ceec-d8ff-401e-8ae4-dd772280d4cd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079324938 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.4079324938
Directory /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3208949564
Short name T169
Test name
Test status
Simulation time 4580959508 ps
CPU time 630.86 seconds
Started Aug 04 07:30:59 PM PDT 24
Finished Aug 04 07:41:30 PM PDT 24
Peak memory 609268 kb
Host smart-8b94acf2-ebde-4d87-bda8-985fc6b1f43d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208949564 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.3208949564
Directory /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.864982249
Short name T170
Test name
Test status
Simulation time 5095008632 ps
CPU time 506.56 seconds
Started Aug 04 07:31:43 PM PDT 24
Finished Aug 04 07:40:10 PM PDT 24
Peak memory 609264 kb
Host smart-05bd7819-8e3c-4d07-a18c-993f74cded48
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864982249 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.864982249
Directory /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3703956275
Short name T595
Test name
Test status
Simulation time 10583687448 ps
CPU time 1193.48 seconds
Started Aug 04 07:32:17 PM PDT 24
Finished Aug 04 07:52:11 PM PDT 24
Peak memory 610552 kb
Host smart-aa0029e1-0388-49cf-bf29-d0fe12054367
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703956275
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.3703956275
Directory /workspace/1.chip_sw_clkmgr_off_peri/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1959286420
Short name T141
Test name
Test status
Simulation time 3865766728 ps
CPU time 433.69 seconds
Started Aug 04 07:31:09 PM PDT 24
Finished Aug 04 07:38:23 PM PDT 24
Peak memory 609912 kb
Host smart-6b1a69e9-8a74-4c4b-bfa7-ead3d944da7b
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959286420 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.1959286420
Directory /workspace/1.chip_sw_clkmgr_reset_frequency/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2758950892
Short name T755
Test name
Test status
Simulation time 4724152840 ps
CPU time 703.56 seconds
Started Aug 04 07:32:46 PM PDT 24
Finished Aug 04 07:44:30 PM PDT 24
Peak memory 610048 kb
Host smart-fe29f239-34e1-4c2a-bf01-d51ef204d734
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758950892 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.2758950892
Directory /workspace/1.chip_sw_clkmgr_sleep_frequency/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1228088986
Short name T529
Test name
Test status
Simulation time 3473754808 ps
CPU time 242.91 seconds
Started Aug 04 07:34:27 PM PDT 24
Finished Aug 04 07:38:30 PM PDT 24
Peak memory 609672 kb
Host smart-1f917acc-83ec-4cff-a8b3-646a6dae2acb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228088986 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.chip_sw_clkmgr_smoketest.1228088986
Directory /workspace/1.chip_sw_clkmgr_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2163459219
Short name T644
Test name
Test status
Simulation time 17156477544 ps
CPU time 4257.44 seconds
Started Aug 04 07:30:50 PM PDT 24
Finished Aug 04 08:41:48 PM PDT 24
Peak memory 610368 kb
Host smart-5812b07f-fdf1-40bc-b037-18a909d560b3
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163459219 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.2163459219
Directory /workspace/1.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2516859099
Short name T75
Test name
Test status
Simulation time 9658487931 ps
CPU time 1682.76 seconds
Started Aug 04 07:32:22 PM PDT 24
Finished Aug 04 08:00:25 PM PDT 24
Peak memory 610184 kb
Host smart-291cc75b-d493-4245-9f28-3ac2e3c1ccc9
User root
Command /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_
cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2516859099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.2516859099
Directory /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1536060355
Short name T224
Test name
Test status
Simulation time 3644063398 ps
CPU time 392.58 seconds
Started Aug 04 07:29:00 PM PDT 24
Finished Aug 04 07:35:33 PM PDT 24
Peak memory 610548 kb
Host smart-328a5a75-6c88-47f2-915b-59eb4c89e7c8
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15360
60355 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.1536060355
Directory /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_kat_test.5736825
Short name T304
Test name
Test status
Simulation time 3343237268 ps
CPU time 279.32 seconds
Started Aug 04 07:31:19 PM PDT 24
Finished Aug 04 07:35:58 PM PDT 24
Peak memory 609844 kb
Host smart-4d8ce92b-40fa-4f26-bc9e-95e771e21fae
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5736825 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.5736825
Directory /workspace/1.chip_sw_csrng_kat_test/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.134973131
Short name T172
Test name
Test status
Simulation time 5249120692 ps
CPU time 614.43 seconds
Started Aug 04 07:28:46 PM PDT 24
Finished Aug 04 07:39:01 PM PDT 24
Peak memory 611352 kb
Host smart-96ab6bcf-522d-4d0a-a852-b40a31c8f0a9
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima
ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134973131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l
c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrn
g_lc_hw_debug_en_test.134973131
Directory /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_smoketest.910276136
Short name T171
Test name
Test status
Simulation time 2487785020 ps
CPU time 231.53 seconds
Started Aug 04 07:34:04 PM PDT 24
Finished Aug 04 07:37:56 PM PDT 24
Peak memory 609632 kb
Host smart-febc766c-c4bf-4109-8ddd-10a49a19c326
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910276136 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_csrng_smoketest.910276136
Directory /workspace/1.chip_sw_csrng_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_data_integrity_escalation.2777555648
Short name T971
Test name
Test status
Simulation time 5790012504 ps
CPU time 777.43 seconds
Started Aug 04 07:21:03 PM PDT 24
Finished Aug 04 07:34:00 PM PDT 24
Peak memory 611024 kb
Host smart-82221347-3a6d-4bf8-8d84-221be402bb4c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2777555648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.2777555648
Directory /workspace/1.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/1.chip_sw_edn_auto_mode.1953798643
Short name T900
Test name
Test status
Simulation time 6444821976 ps
CPU time 1716.74 seconds
Started Aug 04 07:28:25 PM PDT 24
Finished Aug 04 07:57:02 PM PDT 24
Peak memory 610244 kb
Host smart-757fcb07-fc97-4048-b992-2d29d649afbc
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953798643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_
auto_mode.1953798643
Directory /workspace/1.chip_sw_edn_auto_mode/latest

Test location /workspace/coverage/default/1.chip_sw_edn_boot_mode.823630964
Short name T409
Test name
Test status
Simulation time 3291264978 ps
CPU time 616.21 seconds
Started Aug 04 07:32:02 PM PDT 24
Finished Aug 04 07:42:18 PM PDT 24
Peak memory 610264 kb
Host smart-2cfccec6-1c09-46ff-86b0-e23b12e46d34
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823630964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_b
oot_mode.823630964
Directory /workspace/1.chip_sw_edn_boot_mode/latest

Test location /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.979514130
Short name T814
Test name
Test status
Simulation time 7452121426 ps
CPU time 1090.98 seconds
Started Aug 04 07:29:53 PM PDT 24
Finished Aug 04 07:48:04 PM PDT 24
Peak memory 610940 kb
Host smart-65f5314b-7909-498c-8c12-7c7e8ab7f083
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed
n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=979514130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.979514130
Directory /workspace/1.chip_sw_edn_entropy_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1222668236
Short name T986
Test name
Test status
Simulation time 6565223776 ps
CPU time 1053.91 seconds
Started Aug 04 07:29:18 PM PDT 24
Finished Aug 04 07:46:52 PM PDT 24
Peak memory 610964 kb
Host smart-52b68f4a-4749-4ad3-bc35-103433158679
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e
ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222668236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.1222668236
Directory /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest

Test location /workspace/coverage/default/1.chip_sw_edn_kat.523015363
Short name T599
Test name
Test status
Simulation time 3877077828 ps
CPU time 648.01 seconds
Started Aug 04 07:28:59 PM PDT 24
Finished Aug 04 07:39:47 PM PDT 24
Peak memory 615520 kb
Host smart-860d5e06-48b0-4197-998d-6b8655fe7a35
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3
+accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523015363 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_edn_kat.523015363
Directory /workspace/1.chip_sw_edn_kat/latest

Test location /workspace/coverage/default/1.chip_sw_edn_sw_mode.3129498120
Short name T683
Test name
Test status
Simulation time 8172907138 ps
CPU time 1744.86 seconds
Started Aug 04 07:28:47 PM PDT 24
Finished Aug 04 07:57:52 PM PDT 24
Peak memory 609844 kb
Host smart-a571d65b-a76d-44d6-8c2b-9d62c820844e
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129498120 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.3129498120
Directory /workspace/1.chip_sw_edn_sw_mode/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.4108961479
Short name T933
Test name
Test status
Simulation time 2860693882 ps
CPU time 258.68 seconds
Started Aug 04 07:29:19 PM PDT 24
Finished Aug 04 07:33:38 PM PDT 24
Peak memory 609720 kb
Host smart-8ae716f1-0a46-4202-b59d-a57d86b580b9
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41
08961479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.4108961479
Directory /workspace/1.chip_sw_entropy_src_ast_rng_req/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_csrng.909000329
Short name T374
Test name
Test status
Simulation time 5761750276 ps
CPU time 1109.04 seconds
Started Aug 04 07:29:04 PM PDT 24
Finished Aug 04 07:47:33 PM PDT 24
Peak memory 609268 kb
Host smart-eb842b88-5322-447c-bd09-24ac32dcbfa7
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_
csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=909000329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.909000329
Directory /workspace/1.chip_sw_entropy_src_csrng/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2750461725
Short name T901
Test name
Test status
Simulation time 2881786232 ps
CPU time 270.22 seconds
Started Aug 04 07:28:44 PM PDT 24
Finished Aug 04 07:33:15 PM PDT 24
Peak memory 608744 kb
Host smart-89202ab5-e0ed-4147-b003-b3e35d07e8fa
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750461725
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.2750461725
Directory /workspace/1.chip_sw_entropy_src_kat_test/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1329780433
Short name T711
Test name
Test status
Simulation time 3413476960 ps
CPU time 596.23 seconds
Started Aug 04 07:39:55 PM PDT 24
Finished Aug 04 07:49:52 PM PDT 24
Peak memory 609852 kb
Host smart-9b104434-cc96-4686-ab8f-3d9ee94b6628
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1329780433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.1329780433
Directory /workspace/1.chip_sw_entropy_src_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_example_concurrency.2102568338
Short name T712
Test name
Test status
Simulation time 2662402108 ps
CPU time 250.68 seconds
Started Aug 04 07:22:36 PM PDT 24
Finished Aug 04 07:26:47 PM PDT 24
Peak memory 609608 kb
Host smart-417b29e9-494e-496a-bc21-a8c98c689eb0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102568338 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.chip_sw_example_concurrency.2102568338
Directory /workspace/1.chip_sw_example_concurrency/latest

Test location /workspace/coverage/default/1.chip_sw_example_flash.3143934608
Short name T613
Test name
Test status
Simulation time 3398633800 ps
CPU time 233.69 seconds
Started Aug 04 07:20:51 PM PDT 24
Finished Aug 04 07:24:45 PM PDT 24
Peak memory 608356 kb
Host smart-7095f096-cf82-45d9-9873-f4e4da4e09b8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143934608 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_example_flash.3143934608
Directory /workspace/1.chip_sw_example_flash/latest

Test location /workspace/coverage/default/1.chip_sw_example_manufacturer.3542755065
Short name T541
Test name
Test status
Simulation time 2748146540 ps
CPU time 245.7 seconds
Started Aug 04 07:20:53 PM PDT 24
Finished Aug 04 07:24:59 PM PDT 24
Peak memory 609648 kb
Host smart-bbd03ae9-eac6-4f4d-b3e3-8e4d154cbd5d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542755065 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_example_manufacturer.3542755065
Directory /workspace/1.chip_sw_example_manufacturer/latest

Test location /workspace/coverage/default/1.chip_sw_example_rom.3016723368
Short name T605
Test name
Test status
Simulation time 3099166104 ps
CPU time 99.36 seconds
Started Aug 04 07:19:48 PM PDT 24
Finished Aug 04 07:21:27 PM PDT 24
Peak memory 610156 kb
Host smart-e776f90d-847b-4f90-a636-9763d340876f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016723368 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_example_rom.3016723368
Directory /workspace/1.chip_sw_example_rom/latest

Test location /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2257595661
Short name T991
Test name
Test status
Simulation time 57269290695 ps
CPU time 11312 seconds
Started Aug 04 07:22:59 PM PDT 24
Finished Aug 04 10:31:32 PM PDT 24
Peak memory 624780 kb
Host smart-58ab4dbe-683c-4f9c-a435-1d0c72e87c2c
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=2257595661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.2257595661
Directory /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest

Test location /workspace/coverage/default/1.chip_sw_flash_crash_alert.3404533601
Short name T259
Test name
Test status
Simulation time 5083941792 ps
CPU time 651.51 seconds
Started Aug 04 07:33:26 PM PDT 24
Finished Aug 04 07:44:18 PM PDT 24
Peak memory 610928 kb
Host smart-9a2f8605-9d2b-4a80-b50a-15fafb6f4fe7
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:
new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=3404533601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.3404533601
Directory /workspace/1.chip_sw_flash_crash_alert/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_access.620750756
Short name T136
Test name
Test status
Simulation time 5457186920 ps
CPU time 1013.01 seconds
Started Aug 04 07:27:13 PM PDT 24
Finished Aug 04 07:44:07 PM PDT 24
Peak memory 608900 kb
Host smart-6b5deba5-3a81-4722-afca-10a868213f99
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620750756 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_flash_ctrl_access.620750756
Directory /workspace/1.chip_sw_flash_ctrl_access/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1808540954
Short name T766
Test name
Test status
Simulation time 6445121550 ps
CPU time 1065.18 seconds
Started Aug 04 07:25:00 PM PDT 24
Finished Aug 04 07:42:45 PM PDT 24
Peak memory 610068 kb
Host smart-3bc0c6e0-6139-4e92-9d2b-06cb25f32e66
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808540954 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.1808540954
Directory /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4202889745
Short name T418
Test name
Test status
Simulation time 7138471729 ps
CPU time 1300.93 seconds
Started Aug 04 07:32:34 PM PDT 24
Finished Aug 04 07:54:16 PM PDT 24
Peak memory 610196 kb
Host smart-d3c32b27-4fa8-4b30-ac35-07dea2774545
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202889745 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4202889745
Directory /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3281414021
Short name T857
Test name
Test status
Simulation time 5730924904 ps
CPU time 1148.02 seconds
Started Aug 04 07:24:35 PM PDT 24
Finished Aug 04 07:43:44 PM PDT 24
Peak memory 610096 kb
Host smart-9e78dcaa-5ba0-4332-8c3d-c9351e18dbad
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281414021 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.3281414021
Directory /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1830036338
Short name T838
Test name
Test status
Simulation time 3214469864 ps
CPU time 336.31 seconds
Started Aug 04 07:27:18 PM PDT 24
Finished Aug 04 07:32:55 PM PDT 24
Peak memory 609904 kb
Host smart-b158ea36-6a60-4102-9564-8dba03437402
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830036338 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.1830036338
Directory /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.924712862
Short name T526
Test name
Test status
Simulation time 5676759750 ps
CPU time 1323.22 seconds
Started Aug 04 07:33:34 PM PDT 24
Finished Aug 04 07:55:38 PM PDT 24
Peak memory 610120 kb
Host smart-04b3c3ec-6868-43f9-8382-e50f20336020
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924712862 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.924712862
Directory /workspace/1.chip_sw_flash_ctrl_mem_protection/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1447736719
Short name T258
Test name
Test status
Simulation time 3977742520 ps
CPU time 536.32 seconds
Started Aug 04 07:24:32 PM PDT 24
Finished Aug 04 07:33:29 PM PDT 24
Peak memory 609944 kb
Host smart-6318de21-c90f-4a14-a175-ce0fa077f32d
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447736719
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.1447736719
Directory /workspace/1.chip_sw_flash_ctrl_ops/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1055512167
Short name T255
Test name
Test status
Simulation time 5413113614 ps
CPU time 734.8 seconds
Started Aug 04 07:36:33 PM PDT 24
Finished Aug 04 07:48:48 PM PDT 24
Peak memory 610268 kb
Host smart-acc946db-a154-4d5c-8dc7-c7dee4cfaba5
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_
rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1055512167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1055512167
Directory /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1713205475
Short name T557
Test name
Test status
Simulation time 2535662720 ps
CPU time 320.58 seconds
Started Aug 04 07:33:46 PM PDT 24
Finished Aug 04 07:39:07 PM PDT 24
Peak memory 608524 kb
Host smart-c8e53cbf-6007-4571-b9f9-103a250851a7
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713205
475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.1713205475
Directory /workspace/1.chip_sw_flash_ctrl_write_clear/latest

Test location /workspace/coverage/default/1.chip_sw_flash_init.1397396488
Short name T215
Test name
Test status
Simulation time 23242829960 ps
CPU time 2529 seconds
Started Aug 04 07:26:26 PM PDT 24
Finished Aug 04 08:08:36 PM PDT 24
Peak memory 611484 kb
Host smart-7f297582-223d-468f-858f-d5a6f9d663f5
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397396488 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.1397396488
Directory /workspace/1.chip_sw_flash_init/latest

Test location /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.4069090359
Short name T819
Test name
Test status
Simulation time 22987850817 ps
CPU time 2073.88 seconds
Started Aug 04 07:35:00 PM PDT 24
Finished Aug 04 08:09:35 PM PDT 24
Peak memory 613752 kb
Host smart-cad62795-f64f-47a6-9b25-347112481217
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4069090359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.4069090359
Directory /workspace/1.chip_sw_flash_init_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3534724633
Short name T910
Test name
Test status
Simulation time 2194486184 ps
CPU time 258.67 seconds
Started Aug 04 07:37:49 PM PDT 24
Finished Aug 04 07:42:08 PM PDT 24
Peak memory 609620 kb
Host smart-3197b63f-d428-4f33-b5b8-6b259a58cd40
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket
est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3534724633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.3534724633
Directory /workspace/1.chip_sw_flash_scrambling_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_gpio_smoketest.3438934362
Short name T832
Test name
Test status
Simulation time 3003636031 ps
CPU time 343.89 seconds
Started Aug 04 07:33:38 PM PDT 24
Finished Aug 04 07:39:22 PM PDT 24
Peak memory 608964 kb
Host smart-154dc8c7-e952-4f93-9a4a-33f64ace8aee
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438934362 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_sw_gpio_smoketest.3438934362
Directory /workspace/1.chip_sw_gpio_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc.2411863887
Short name T693
Test name
Test status
Simulation time 2609216608 ps
CPU time 197.67 seconds
Started Aug 04 07:28:43 PM PDT 24
Finished Aug 04 07:32:01 PM PDT 24
Peak memory 609708 kb
Host smart-ec65f369-1ea1-4a89-a1a4-c6904495a2b2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411863887 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_hmac_enc.2411863887
Directory /workspace/1.chip_sw_hmac_enc/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc_idle.652945663
Short name T694
Test name
Test status
Simulation time 3181682496 ps
CPU time 282.76 seconds
Started Aug 04 07:29:00 PM PDT 24
Finished Aug 04 07:33:43 PM PDT 24
Peak memory 609728 kb
Host smart-d7d68cb1-e1ff-4661-965a-a99dff3c47b1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652945663 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_hmac_enc_idle.652945663
Directory /workspace/1.chip_sw_hmac_enc_idle/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.4292538508
Short name T161
Test name
Test status
Simulation time 3384605516 ps
CPU time 295.92 seconds
Started Aug 04 07:29:30 PM PDT 24
Finished Aug 04 07:34:26 PM PDT 24
Peak memory 609812 kb
Host smart-6bdd4ae9-bf34-4e49-86a1-a45e90cc8ed4
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292538508 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.4292538508
Directory /workspace/1.chip_sw_hmac_enc_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2223432673
Short name T162
Test name
Test status
Simulation time 2531036281 ps
CPU time 268.36 seconds
Started Aug 04 07:33:51 PM PDT 24
Finished Aug 04 07:38:20 PM PDT 24
Peak memory 609808 kb
Host smart-9c98847f-abaa-400f-8975-881dcf9c089f
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223432673 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.2223432673
Directory /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_multistream.87815095
Short name T917
Test name
Test status
Simulation time 7412852790 ps
CPU time 1720.86 seconds
Started Aug 04 07:29:31 PM PDT 24
Finished Aug 04 07:58:13 PM PDT 24
Peak memory 610004 kb
Host smart-2ae1bf73-0667-43fc-880f-1930918d8c85
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87815095 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_hmac_multistream.87815095
Directory /workspace/1.chip_sw_hmac_multistream/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_oneshot.353385250
Short name T1012
Test name
Test status
Simulation time 2924721320 ps
CPU time 257.84 seconds
Started Aug 04 07:29:55 PM PDT 24
Finished Aug 04 07:34:13 PM PDT 24
Peak memory 608516 kb
Host smart-2e2658ab-b327-414f-8ead-324b8910272f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353385250 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_hmac_oneshot.353385250
Directory /workspace/1.chip_sw_hmac_oneshot/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_smoketest.969155752
Short name T868
Test name
Test status
Simulation time 3383686248 ps
CPU time 340.49 seconds
Started Aug 04 07:34:43 PM PDT 24
Finished Aug 04 07:40:24 PM PDT 24
Peak memory 609692 kb
Host smart-274da6bf-1878-4421-92cf-475775de2b98
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969155752 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_hmac_smoketest.969155752
Directory /workspace/1.chip_sw_hmac_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1842629358
Short name T377
Test name
Test status
Simulation time 4138273770 ps
CPU time 653.26 seconds
Started Aug 04 07:22:59 PM PDT 24
Finished Aug 04 07:33:53 PM PDT 24
Peak memory 609552 kb
Host smart-53eeeb97-e791-4125-8fd0-13b972664373
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842629358 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.1842629358
Directory /workspace/1.chip_sw_i2c_device_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1190944590
Short name T227
Test name
Test status
Simulation time 5068062226 ps
CPU time 689.57 seconds
Started Aug 04 07:23:04 PM PDT 24
Finished Aug 04 07:34:34 PM PDT 24
Peak memory 610056 kb
Host smart-24ccbc59-6072-44d0-a69a-285db0b1ff44
User root
Command /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190944590 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.1190944590
Directory /workspace/1.chip_sw_i2c_host_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3099270613
Short name T378
Test name
Test status
Simulation time 4691334412 ps
CPU time 558.86 seconds
Started Aug 04 07:23:55 PM PDT 24
Finished Aug 04 07:33:14 PM PDT 24
Peak memory 609956 kb
Host smart-0aef1b0f-052c-4152-8157-9c741db284bc
User root
Command /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099270613 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.3099270613
Directory /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest

Test location /workspace/coverage/default/1.chip_sw_inject_scramble_seed.3795089481
Short name T796
Test name
Test status
Simulation time 63417903346 ps
CPU time 12528.8 seconds
Started Aug 04 07:24:54 PM PDT 24
Finished Aug 04 10:53:44 PM PDT 24
Peak memory 624912 kb
Host smart-c1490470-7b47-458a-a773-cb9f5e4d73dc
User root
Command /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3795089481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.3795089481
Directory /workspace/1.chip_sw_inject_scramble_seed/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2414122229
Short name T337
Test name
Test status
Simulation time 6557715736 ps
CPU time 848.41 seconds
Started Aug 04 07:29:42 PM PDT 24
Finished Aug 04 07:43:50 PM PDT 24
Peak memory 618192 kb
Host smart-2e6e6f30-f1be-4b95-889a-70036213a67d
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414
122229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.2414122229
Directory /workspace/1.chip_sw_keymgr_key_derivation/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1092538219
Short name T342
Test name
Test status
Simulation time 10715736903 ps
CPU time 2121.16 seconds
Started Aug 04 07:30:35 PM PDT 24
Finished Aug 04 08:05:56 PM PDT 24
Peak memory 617972 kb
Host smart-ffa2cd52-bfe4-42e4-9779-b1a7e506c238
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1092538219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.1092538219
Directory /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1773833528
Short name T65
Test name
Test status
Simulation time 8355738316 ps
CPU time 1365.28 seconds
Started Aug 04 07:33:40 PM PDT 24
Finished Aug 04 07:56:25 PM PDT 24
Peak memory 617608 kb
Host smart-4ff49cb4-fd89-46e6-abd0-ff330ef05f52
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1773833528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en
_reduced_freq.1773833528
Directory /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1663861505
Short name T773
Test name
Test status
Simulation time 9216401480 ps
CPU time 2145.95 seconds
Started Aug 04 07:30:45 PM PDT 24
Finished Aug 04 08:06:31 PM PDT 24
Peak memory 617900 kb
Host smart-1d17f496-1f7a-4174-b1aa-9433620c1819
User root
Command /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1663861505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.1663861505
Directory /workspace/1.chip_sw_keymgr_key_derivation_prod/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.625133936
Short name T343
Test name
Test status
Simulation time 12119721200 ps
CPU time 2366.54 seconds
Started Aug 04 07:31:23 PM PDT 24
Finished Aug 04 08:10:50 PM PDT 24
Peak memory 611288 kb
Host smart-f2171945-cbf1-4cca-8e1e-89841954c39b
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625133
936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.625133936
Directory /workspace/1.chip_sw_keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.4268204767
Short name T738
Test name
Test status
Simulation time 8133996884 ps
CPU time 1755.54 seconds
Started Aug 04 07:32:40 PM PDT 24
Finished Aug 04 08:01:56 PM PDT 24
Peak memory 611256 kb
Host smart-8a645950-e9c4-469e-ba87-aef5e9b833a8
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42682
04767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.4268204767
Directory /workspace/1.chip_sw_keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3367981704
Short name T344
Test name
Test status
Simulation time 15603834920 ps
CPU time 3882.06 seconds
Started Aug 04 07:29:28 PM PDT 24
Finished Aug 04 08:34:11 PM PDT 24
Peak memory 610648 kb
Host smart-d1a271c7-393a-4721-8e01-f352157122b0
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33679
81704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.3367981704
Directory /workspace/1.chip_sw_keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_app_rom.1252610790
Short name T156
Test name
Test status
Simulation time 2879332402 ps
CPU time 192.66 seconds
Started Aug 04 07:30:42 PM PDT 24
Finished Aug 04 07:33:55 PM PDT 24
Peak memory 609648 kb
Host smart-a0458a29-f691-4d2b-b3c8-bbb41a1e8bbf
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252610790 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_kmac_app_rom.1252610790
Directory /workspace/1.chip_sw_kmac_app_rom/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_entropy.356029834
Short name T360
Test name
Test status
Simulation time 1954700220 ps
CPU time 248.61 seconds
Started Aug 04 07:25:21 PM PDT 24
Finished Aug 04 07:29:31 PM PDT 24
Peak memory 609604 kb
Host smart-062f83a6-e899-4450-bd42-93bd0950776e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356029834 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.chip_sw_kmac_entropy.356029834
Directory /workspace/1.chip_sw_kmac_entropy/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_idle.272459317
Short name T612
Test name
Test status
Simulation time 2880307440 ps
CPU time 215.16 seconds
Started Aug 04 07:30:08 PM PDT 24
Finished Aug 04 07:33:44 PM PDT 24
Peak memory 608484 kb
Host smart-a9b82e92-70e7-4f72-84db-d72caa2044f6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272459317 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_kmac_idle.272459317
Directory /workspace/1.chip_sw_kmac_idle/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.1296554375
Short name T672
Test name
Test status
Simulation time 2377312092 ps
CPU time 182.3 seconds
Started Aug 04 07:30:00 PM PDT 24
Finished Aug 04 07:33:03 PM PDT 24
Peak memory 608428 kb
Host smart-c0df81e0-fee5-4f6e-98a0-0078fd91b7e7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296554375 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.chip_sw_kmac_mode_cshake.1296554375
Directory /workspace/1.chip_sw_kmac_mode_cshake/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2425508893
Short name T944
Test name
Test status
Simulation time 2857902920 ps
CPU time 376.46 seconds
Started Aug 04 07:32:51 PM PDT 24
Finished Aug 04 07:39:08 PM PDT 24
Peak memory 608644 kb
Host smart-99f1f5f1-1dec-4976-9dce-be290a9d52a0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425508893 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_kmac_mode_kmac.2425508893
Directory /workspace/1.chip_sw_kmac_mode_kmac/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.801919729
Short name T609
Test name
Test status
Simulation time 3840383593 ps
CPU time 328.32 seconds
Started Aug 04 07:30:54 PM PDT 24
Finished Aug 04 07:36:23 PM PDT 24
Peak memory 609696 kb
Host smart-e74d5fe9-8cd0-4ffd-899a-4e0d9f855e5e
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801919729 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.801919729
Directory /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3644190772
Short name T758
Test name
Test status
Simulation time 3135992356 ps
CPU time 232.34 seconds
Started Aug 04 07:35:28 PM PDT 24
Finished Aug 04 07:39:21 PM PDT 24
Peak memory 609884 kb
Host smart-e93405e7-8296-45ad-a1f7-731906b570d0
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36441907
72 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3644190772
Directory /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_smoketest.692722259
Short name T706
Test name
Test status
Simulation time 3480931502 ps
CPU time 396.27 seconds
Started Aug 04 07:35:14 PM PDT 24
Finished Aug 04 07:41:50 PM PDT 24
Peak memory 608384 kb
Host smart-b2a799f6-502b-4755-a2a5-acc4e7ca5c18
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692722259 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_kmac_smoketest.692722259
Directory /workspace/1.chip_sw_kmac_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2766669894
Short name T403
Test name
Test status
Simulation time 3757579728 ps
CPU time 297.25 seconds
Started Aug 04 07:23:44 PM PDT 24
Finished Aug 04 07:28:42 PM PDT 24
Peak memory 609620 kb
Host smart-f7a8ba49-8777-46bf-a7fa-af786d1bcfe4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766669894 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.2766669894
Directory /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.11726718
Short name T209
Test name
Test status
Simulation time 4336936600 ps
CPU time 508.51 seconds
Started Aug 04 07:31:24 PM PDT 24
Finished Aug 04 07:39:53 PM PDT 24
Peak memory 610812 kb
Host smart-44eb69f0-6a1d-406d-aeaf-a47521157eda
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=11726718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.11726718
Directory /workspace/1.chip_sw_lc_ctrl_program_error/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3743982517
Short name T424
Test name
Test status
Simulation time 3313845669 ps
CPU time 180.63 seconds
Started Aug 04 07:25:31 PM PDT 24
Finished Aug 04 07:28:32 PM PDT 24
Peak memory 621372 kb
Host smart-5d3e7f4b-6d15-46db-bde9-13ebc505818d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37439825
17 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.3743982517
Directory /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3150647687
Short name T543
Test name
Test status
Simulation time 4908937400 ps
CPU time 521.81 seconds
Started Aug 04 07:24:59 PM PDT 24
Finished Aug 04 07:33:42 PM PDT 24
Peak memory 620576 kb
Host smart-cd5d7d93-997b-4125-9259-791b05e7f84c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150647687 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.3150647687
Directory /workspace/1.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.397898594
Short name T112
Test name
Test status
Simulation time 2486652756 ps
CPU time 123.23 seconds
Started Aug 04 07:28:24 PM PDT 24
Finished Aug 04 07:30:28 PM PDT 24
Peak memory 617064 kb
Host smart-ac53e610-0f9b-4612-a6f4-243e1292413c
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes
t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=397898594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.397898594
Directory /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2298563616
Short name T423
Test name
Test status
Simulation time 2518317689 ps
CPU time 106.66 seconds
Started Aug 04 07:25:57 PM PDT 24
Finished Aug 04 07:27:44 PM PDT 24
Peak memory 617072 kb
Host smart-ac7efffd-7db6-4c17-9d69-e7393ac6b781
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s
im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298563616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2298563616
Directory /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.294739529
Short name T969
Test name
Test status
Simulation time 50961467850 ps
CPU time 6494.46 seconds
Started Aug 04 07:25:21 PM PDT 24
Finished Aug 04 09:13:37 PM PDT 24
Peak memory 619588 kb
Host smart-9e904e8a-44b0-4bb2-9af7-8bce84e10b2d
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294739529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch
ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_
sw_lc_walkthrough_dev.294739529
Directory /workspace/1.chip_sw_lc_walkthrough_dev/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2320736868
Short name T891
Test name
Test status
Simulation time 50351242479 ps
CPU time 5679.19 seconds
Started Aug 04 07:26:41 PM PDT 24
Finished Aug 04 09:01:22 PM PDT 24
Peak memory 620836 kb
Host smart-9b946ad9-4ecf-490a-9b2b-453a75886c08
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d
evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320736868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi
p_sw_lc_walkthrough_prod.2320736868
Directory /workspace/1.chip_sw_lc_walkthrough_prod/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3994166098
Short name T742
Test name
Test status
Simulation time 10459810340 ps
CPU time 982.5 seconds
Started Aug 04 07:25:50 PM PDT 24
Finished Aug 04 07:42:13 PM PDT 24
Peak memory 620272 kb
Host smart-48644805-cb4e-400a-ae7f-8387b60e47b1
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa
lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994166098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.3994166098
Directory /workspace/1.chip_sw_lc_walkthrough_prodend/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3267390902
Short name T250
Test name
Test status
Simulation time 44874720400 ps
CPU time 5467.51 seconds
Started Aug 04 07:25:23 PM PDT 24
Finished Aug 04 08:56:31 PM PDT 24
Peak memory 619296 kb
Host smart-a233828f-2e07-4658-9f35-8ffd83acd115
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267390902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip
_sw_lc_walkthrough_rma.3267390902
Directory /workspace/1.chip_sw_lc_walkthrough_rma/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.580652246
Short name T657
Test name
Test status
Simulation time 29934747790 ps
CPU time 2341.67 seconds
Started Aug 04 07:26:31 PM PDT 24
Finished Aug 04 08:05:33 PM PDT 24
Peak memory 620144 kb
Host smart-ee2ffb83-8bca-45f6-aa4f-8ca68d7a3b27
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks
_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=580652246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testunl
ocks.580652246
Directory /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.4129893297
Short name T196
Test name
Test status
Simulation time 17683734328 ps
CPU time 4058.68 seconds
Started Aug 04 07:30:02 PM PDT 24
Finished Aug 04 08:37:42 PM PDT 24
Peak memory 610404 kb
Host smart-0d9913d5-3872-475c-bf99-46ed2b75ddc7
User root
Command /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_
rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4129893297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.4129893297
Directory /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.122366992
Short name T727
Test name
Test status
Simulation time 18750697858 ps
CPU time 3722.13 seconds
Started Aug 04 07:28:49 PM PDT 24
Finished Aug 04 08:30:52 PM PDT 24
Peak memory 610300 kb
Host smart-314bde63-c3d3-41fb-96d1-4ee142f662f3
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne
w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=122366992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.122366992
Directory /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2174551006
Short name T768
Test name
Test status
Simulation time 25025929616 ps
CPU time 3536.86 seconds
Started Aug 04 07:36:35 PM PDT 24
Finished Aug 04 08:35:32 PM PDT 24
Peak memory 610376 kb
Host smart-06f8db00-4eed-4c70-8a72-395a980964c9
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e
cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174551006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu
ced_freq.2174551006
Directory /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.532441092
Short name T913
Test name
Test status
Simulation time 3587530592 ps
CPU time 551.08 seconds
Started Aug 04 07:27:41 PM PDT 24
Finished Aug 04 07:36:52 PM PDT 24
Peak memory 609852 kb
Host smart-9824c034-4340-447b-a68a-2cef04e9a3b1
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn
_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532441092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.532441092
Directory /workspace/1.chip_sw_otbn_mem_scramble/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_randomness.4023648436
Short name T828
Test name
Test status
Simulation time 6040425100 ps
CPU time 822.76 seconds
Started Aug 04 07:27:34 PM PDT 24
Finished Aug 04 07:41:17 PM PDT 24
Peak memory 610252 kb
Host smart-47474c38-2ad8-4c67-bf37-4109af663def
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4023648436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.4023648436
Directory /workspace/1.chip_sw_otbn_randomness/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_smoketest.3630419462
Short name T762
Test name
Test status
Simulation time 7484522520 ps
CPU time 1952.94 seconds
Started Aug 04 07:40:06 PM PDT 24
Finished Aug 04 08:12:39 PM PDT 24
Peak memory 608976 kb
Host smart-63831206-85bd-4192-8832-436fead13885
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630419462 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_otbn_smoketest.3630419462
Directory /workspace/1.chip_sw_otbn_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2968720099
Short name T293
Test name
Test status
Simulation time 2957387016 ps
CPU time 209.74 seconds
Started Aug 04 07:24:28 PM PDT 24
Finished Aug 04 07:27:58 PM PDT 24
Peak memory 609360 kb
Host smart-b871eea9-5c08-40c2-8ba5-732f2b1c3c39
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968720099 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.2968720099
Directory /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2705329698
Short name T177
Test name
Test status
Simulation time 8603072778 ps
CPU time 1520.75 seconds
Started Aug 04 07:24:33 PM PDT 24
Finished Aug 04 07:49:54 PM PDT 24
Peak memory 610712 kb
Host smart-b75ed478-71dc-40d5-bb60-a7a55d700197
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2705329698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.2705329698
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.4261261810
Short name T704
Test name
Test status
Simulation time 6174290200 ps
CPU time 1295.01 seconds
Started Aug 04 07:24:49 PM PDT 24
Finished Aug 04 07:46:24 PM PDT 24
Peak memory 610684 kb
Host smart-a964b9e2-5278-46e1-8a12-eda45c441d8e
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4261261810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.4261261810
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.474359357
Short name T701
Test name
Test status
Simulation time 7365087638 ps
CPU time 1545.39 seconds
Started Aug 04 07:25:47 PM PDT 24
Finished Aug 04 07:51:33 PM PDT 24
Peak memory 610656 kb
Host smart-ae4576f9-1680-4fe8-a048-10282cbbb2a7
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=474359357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.474359357
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2898687726
Short name T575
Test name
Test status
Simulation time 4261367448 ps
CPU time 752.56 seconds
Started Aug 04 07:25:35 PM PDT 24
Finished Aug 04 07:38:08 PM PDT 24
Peak memory 608816 kb
Host smart-1758af2a-359d-4bcf-90fa-ab439c6d1536
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=2898687726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2898687726
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1183347174
Short name T576
Test name
Test status
Simulation time 3136426776 ps
CPU time 221.74 seconds
Started Aug 04 07:34:17 PM PDT 24
Finished Aug 04 07:37:59 PM PDT 24
Peak memory 609616 kb
Host smart-3fb1c951-1ff0-4f5b-907b-8ef5765d277b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183347174 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_otp_ctrl_smoketest.1183347174
Directory /workspace/1.chip_sw_otp_ctrl_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_pattgen_ios.2980116838
Short name T385
Test name
Test status
Simulation time 2693542300 ps
CPU time 262.86 seconds
Started Aug 04 07:21:31 PM PDT 24
Finished Aug 04 07:25:55 PM PDT 24
Peak memory 610344 kb
Host smart-019f7f7e-2fc0-4c2a-bc76-5af031bf56d2
User root
Command /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980116838 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.2980116838
Directory /workspace/1.chip_sw_pattgen_ios/latest

Test location /workspace/coverage/default/1.chip_sw_plic_sw_irq.1804819706
Short name T271
Test name
Test status
Simulation time 3794418568 ps
CPU time 341.22 seconds
Started Aug 04 07:31:04 PM PDT 24
Finished Aug 04 07:36:45 PM PDT 24
Peak memory 609668 kb
Host smart-97b37c9c-95d8-4fb2-9178-e0b7d7607b16
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804819706 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.chip_sw_plic_sw_irq.1804819706
Directory /workspace/1.chip_sw_plic_sw_irq/latest

Test location /workspace/coverage/default/1.chip_sw_power_idle_load.4117187115
Short name T739
Test name
Test status
Simulation time 4154073264 ps
CPU time 590.59 seconds
Started Aug 04 07:33:28 PM PDT 24
Finished Aug 04 07:43:19 PM PDT 24
Peak memory 608848 kb
Host smart-9da47ddb-573d-4a0f-8dd8-8e235b995d61
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117187115 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.4117187115
Directory /workspace/1.chip_sw_power_idle_load/latest

Test location /workspace/coverage/default/1.chip_sw_power_sleep_load.568577243
Short name T400
Test name
Test status
Simulation time 4771588310 ps
CPU time 526.54 seconds
Started Aug 04 07:36:31 PM PDT 24
Finished Aug 04 07:45:18 PM PDT 24
Peak memory 609192 kb
Host smart-7c389d80-3bf7-48ad-b6cf-09ef258d2f4b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568577243 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.568577243
Directory /workspace/1.chip_sw_power_sleep_load/latest

Test location /workspace/coverage/default/1.chip_sw_power_virus.770923029
Short name T45
Test name
Test status
Simulation time 5362045106 ps
CPU time 1407.86 seconds
Started Aug 04 07:36:33 PM PDT 24
Finished Aug 04 08:00:01 PM PDT 24
Peak memory 624992 kb
Host smart-a1172d7b-151f-4a02-b0ec-ea7cb26d1866
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_
power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes
t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=770923029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.770923029
Directory /workspace/1.chip_sw_power_virus/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1854374683
Short name T710
Test name
Test status
Simulation time 10396475891 ps
CPU time 1676.36 seconds
Started Aug 04 07:26:13 PM PDT 24
Finished Aug 04 07:54:10 PM PDT 24
Peak memory 611188 kb
Host smart-892ab45d-4b5a-4321-b4d1-965956250b3a
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854
374683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.1854374683
Directory /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3815478755
Short name T792
Test name
Test status
Simulation time 30092823413 ps
CPU time 2485.49 seconds
Started Aug 04 07:30:26 PM PDT 24
Finished Aug 04 08:11:52 PM PDT 24
Peak memory 611208 kb
Host smart-94faece6-79ae-4b4f-ad84-dd70f4411513
User root
Command /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381
5478755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.3815478755
Directory /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.554446203
Short name T833
Test name
Test status
Simulation time 13517289926 ps
CPU time 1510.69 seconds
Started Aug 04 07:26:59 PM PDT 24
Finished Aug 04 07:52:10 PM PDT 24
Peak memory 611512 kb
Host smart-9b7aae11-46bd-4fd5-8347-b2aa8f62abf9
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=554446203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.554446203
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1271220895
Short name T140
Test name
Test status
Simulation time 21676271082 ps
CPU time 1694.13 seconds
Started Aug 04 07:31:41 PM PDT 24
Finished Aug 04 07:59:56 PM PDT 24
Peak memory 610596 kb
Host smart-4b6109c5-c804-4078-97b3-67bf4f3579c8
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1271220895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1271220895
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.4160242310
Short name T870
Test name
Test status
Simulation time 7868449800 ps
CPU time 827.43 seconds
Started Aug 04 07:28:11 PM PDT 24
Finished Aug 04 07:41:58 PM PDT 24
Peak memory 610816 kb
Host smart-542c2f57-3454-4f34-8ffe-730097f40c4d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160242310 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.4160242310
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3048306803
Short name T853
Test name
Test status
Simulation time 5637101304 ps
CPU time 421.77 seconds
Started Aug 04 07:26:14 PM PDT 24
Finished Aug 04 07:33:16 PM PDT 24
Peak memory 616404 kb
Host smart-83344071-9870-4967-8a0c-c82c0917cc78
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3048306803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3048306803
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3646446861
Short name T780
Test name
Test status
Simulation time 7140606630 ps
CPU time 433.15 seconds
Started Aug 04 07:26:38 PM PDT 24
Finished Aug 04 07:33:52 PM PDT 24
Peak memory 610808 kb
Host smart-7b4baf04-9928-4591-b28a-32b2deb24c5d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646446861 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.3646446861
Directory /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3485829949
Short name T732
Test name
Test status
Simulation time 3946546343 ps
CPU time 342.75 seconds
Started Aug 04 07:25:26 PM PDT 24
Finished Aug 04 07:31:09 PM PDT 24
Peak memory 617324 kb
Host smart-e8148a2e-5957-412c-853f-ab6247f2e0ab
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3485829949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.3485829949
Directory /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.193626481
Short name T534
Test name
Test status
Simulation time 10489676290 ps
CPU time 1186.27 seconds
Started Aug 04 07:27:08 PM PDT 24
Finished Aug 04 07:46:55 PM PDT 24
Peak memory 611272 kb
Host smart-cc60758b-97cc-4a19-839f-06229d4c47e6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193626481 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.193626481
Directory /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2620044059
Short name T16
Test name
Test status
Simulation time 7373910368 ps
CPU time 392.73 seconds
Started Aug 04 07:33:18 PM PDT 24
Finished Aug 04 07:39:51 PM PDT 24
Peak memory 609664 kb
Host smart-104dc127-307a-4e74-b83b-638be1d0f922
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620044059 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2620044059
Directory /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2210583568
Short name T567
Test name
Test status
Simulation time 6136323742 ps
CPU time 813.89 seconds
Started Aug 04 07:29:26 PM PDT 24
Finished Aug 04 07:43:00 PM PDT 24
Peak memory 609564 kb
Host smart-1b3ef75e-bc97-459b-94df-18b07c851e91
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210583568 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.2210583568
Directory /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.171392937
Short name T829
Test name
Test status
Simulation time 20455056172 ps
CPU time 2402.38 seconds
Started Aug 04 07:25:57 PM PDT 24
Finished Aug 04 08:06:00 PM PDT 24
Peak memory 611544 kb
Host smart-1dd969d4-f003-42e8-9352-138ffa20ad82
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=171392937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.171392937
Directory /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.513623651
Short name T426
Test name
Test status
Simulation time 24206237734 ps
CPU time 1704.51 seconds
Started Aug 04 07:32:31 PM PDT 24
Finished Aug 04 08:00:56 PM PDT 24
Peak memory 610816 kb
Host smart-ab7477db-d212-4bfa-8e54-7e4ef8f482c1
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=513623651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.513623651
Directory /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3358492175
Short name T610
Test name
Test status
Simulation time 38891111751 ps
CPU time 4054.02 seconds
Started Aug 04 07:26:53 PM PDT 24
Finished Aug 04 08:34:28 PM PDT 24
Peak memory 611996 kb
Host smart-2afa378e-f950-4f5c-b130-deb85997ef3a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power
_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358492175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit
ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s
leep_power_glitch_reset.3358492175
Directory /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2914466658
Short name T183
Test name
Test status
Simulation time 6643907160 ps
CPU time 416.64 seconds
Started Aug 04 07:33:00 PM PDT 24
Finished Aug 04 07:39:57 PM PDT 24
Peak memory 611096 kb
Host smart-33b875c8-0453-4ce5-b33a-3cc1791b3145
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul
es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2914466658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s
leep_wake_up.2914466658
Directory /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.673957683
Short name T346
Test name
Test status
Simulation time 2724901100 ps
CPU time 291.13 seconds
Started Aug 04 07:28:51 PM PDT 24
Finished Aug 04 07:33:43 PM PDT 24
Peak memory 609688 kb
Host smart-3fb7ff51-3374-484a-a707-09643d2462d3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673957683 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.673957683
Directory /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1663731687
Short name T591
Test name
Test status
Simulation time 5513241076 ps
CPU time 628.13 seconds
Started Aug 04 07:27:09 PM PDT 24
Finished Aug 04 07:37:38 PM PDT 24
Peak memory 616792 kb
Host smart-8b61174f-a84c-41da-ae0c-0aa642ed7cc8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=1663731687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.1663731687
Directory /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4027236849
Short name T83
Test name
Test status
Simulation time 5635477400 ps
CPU time 460.02 seconds
Started Aug 04 07:30:29 PM PDT 24
Finished Aug 04 07:38:09 PM PDT 24
Peak memory 609980 kb
Host smart-24b5d981-8c92-4e0f-bbde-78ca235905cf
User root
Command /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40272368
49 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4027236849
Directory /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1772947701
Short name T429
Test name
Test status
Simulation time 6456029936 ps
CPU time 371.15 seconds
Started Aug 04 07:31:16 PM PDT 24
Finished Aug 04 07:37:27 PM PDT 24
Peak memory 610736 kb
Host smart-22cfd3da-d323-4489-8197-28e8e03b3cb9
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1772947701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.1772947701
Directory /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2075900352
Short name T840
Test name
Test status
Simulation time 6003179244 ps
CPU time 454.26 seconds
Started Aug 04 07:35:17 PM PDT 24
Finished Aug 04 07:42:51 PM PDT 24
Peak memory 610420 kb
Host smart-88f2be39-33c4-412c-8b3a-5702af658bbf
User root
Command /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075900352 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.2075900352
Directory /workspace/1.chip_sw_pwrmgr_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.9027434
Short name T627
Test name
Test status
Simulation time 6965934140 ps
CPU time 843.78 seconds
Started Aug 04 07:26:09 PM PDT 24
Finished Aug 04 07:40:13 PM PDT 24
Peak memory 610860 kb
Host smart-66d95d06-4ea8-46c1-92e2-6d0ca0911228
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9027434 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.9027434
Directory /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.4289950992
Short name T749
Test name
Test status
Simulation time 4457059232 ps
CPU time 422.77 seconds
Started Aug 04 07:28:43 PM PDT 24
Finished Aug 04 07:35:46 PM PDT 24
Peak memory 610448 kb
Host smart-f4919aae-6d5e-49e5-99bc-cf218f7efda1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289950992 -assert no
postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.4289950992
Directory /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2365267633
Short name T952
Test name
Test status
Simulation time 6200142440 ps
CPU time 526.11 seconds
Started Aug 04 07:35:07 PM PDT 24
Finished Aug 04 07:43:53 PM PDT 24
Peak memory 610300 kb
Host smart-022551cd-e669-4435-a704-cc58ff1099ce
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365267633 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.2365267633
Directory /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.4065295062
Short name T972
Test name
Test status
Simulation time 4587453130 ps
CPU time 547.7 seconds
Started Aug 04 07:27:08 PM PDT 24
Finished Aug 04 07:36:15 PM PDT 24
Peak memory 609200 kb
Host smart-eb3c54a6-db11-4a6d-b9be-8e68079c11e6
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406
5295062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.4065295062
Directory /workspace/1.chip_sw_pwrmgr_wdog_reset/latest

Test location /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2000719360
Short name T669
Test name
Test status
Simulation time 8422319935 ps
CPU time 663.51 seconds
Started Aug 04 07:29:59 PM PDT 24
Finished Aug 04 07:41:03 PM PDT 24
Peak memory 610280 kb
Host smart-6542df48-7562-4b8e-bc20-a7841de7dc59
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000719360 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.2000719360
Directory /workspace/1.chip_sw_rom_ctrl_integrity_check/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3301215152
Short name T373
Test name
Test status
Simulation time 11517524340 ps
CPU time 1575.19 seconds
Started Aug 04 07:28:42 PM PDT 24
Finished Aug 04 07:54:58 PM PDT 24
Peak memory 610976 kb
Host smart-308842ce-b53a-4cfc-83a9-16c6580e585f
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=3301215152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.3301215152
Directory /workspace/1.chip_sw_rstmgr_alert_info/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3985979931
Short name T565
Test name
Test status
Simulation time 4922851482 ps
CPU time 644.11 seconds
Started Aug 04 07:21:11 PM PDT 24
Finished Aug 04 07:31:55 PM PDT 24
Peak memory 641708 kb
Host smart-da49a912-591e-4fea-9ab7-fdbda87ea31f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3985979931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.3985979931
Directory /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.859081881
Short name T849
Test name
Test status
Simulation time 2663234136 ps
CPU time 211.88 seconds
Started Aug 04 07:34:14 PM PDT 24
Finished Aug 04 07:37:46 PM PDT 24
Peak memory 609680 kb
Host smart-2d8c881e-7d20-49a6-b85b-7faeeb891a18
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859081881 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.chip_sw_rstmgr_smoketest.859081881
Directory /workspace/1.chip_sw_rstmgr_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.772265886
Short name T300
Test name
Test status
Simulation time 4433539164 ps
CPU time 478.34 seconds
Started Aug 04 07:27:49 PM PDT 24
Finished Aug 04 07:35:47 PM PDT 24
Peak memory 610436 kb
Host smart-cb75ebee-681f-4104-9b4e-6d9cc593f74e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772265886 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_rstmgr_sw_req.772265886
Directory /workspace/1.chip_sw_rstmgr_sw_req/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1097932045
Short name T723
Test name
Test status
Simulation time 2772957664 ps
CPU time 271.52 seconds
Started Aug 04 07:26:11 PM PDT 24
Finished Aug 04 07:30:43 PM PDT 24
Peak memory 609708 kb
Host smart-a048dca4-2b87-4277-b861-8965e7cfcda1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097932045 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.1097932045
Directory /workspace/1.chip_sw_rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1767138802
Short name T222
Test name
Test status
Simulation time 2968856842 ps
CPU time 301.75 seconds
Started Aug 04 07:33:25 PM PDT 24
Finished Aug 04 07:38:27 PM PDT 24
Peak memory 609836 kb
Host smart-431f8f4d-4234-4663-979f-e54167ec57f6
User root
Command /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1767138802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.1767138802
Directory /workspace/1.chip_sw_rv_core_ibex_address_translation/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1424764573
Short name T315
Test name
Test status
Simulation time 2687122514 ps
CPU time 247.54 seconds
Started Aug 04 07:34:43 PM PDT 24
Finished Aug 04 07:38:51 PM PDT 24
Peak memory 609764 kb
Host smart-2e92a444-9851-41e2-9afe-a53c42e5c6fc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424764573 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.1424764573
Directory /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2015027153
Short name T366
Test name
Test status
Simulation time 5171132336 ps
CPU time 856.93 seconds
Started Aug 04 07:29:59 PM PDT 24
Finished Aug 04 07:44:16 PM PDT 24
Peak memory 610292 kb
Host smart-e46509f5-e234-452f-ab71-4f76c4bceb7d
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20150
27153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.2015027153
Directory /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3308807460
Short name T812
Test name
Test status
Simulation time 6027544728 ps
CPU time 1266.65 seconds
Started Aug 04 07:28:26 PM PDT 24
Finished Aug 04 07:49:33 PM PDT 24
Peak memory 610084 kb
Host smart-5383948b-0d05-45df-a569-95f7004603e5
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3308807460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.3308807460
Directory /workspace/1.chip_sw_rv_core_ibex_rnd/latest

Test location /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.183494057
Short name T421
Test name
Test status
Simulation time 4158675387 ps
CPU time 464.08 seconds
Started Aug 04 07:34:42 PM PDT 24
Finished Aug 04 07:42:26 PM PDT 24
Peak memory 624432 kb
Host smart-0cfa4ccf-6169-46fc-aa05-c030e2da6d41
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183494057 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.183494057
Directory /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1597049975
Short name T115
Test name
Test status
Simulation time 5689164120 ps
CPU time 471.66 seconds
Started Aug 04 07:33:36 PM PDT 24
Finished Aug 04 07:41:28 PM PDT 24
Peak memory 620016 kb
Host smart-1cf0de0e-08c5-4271-9af9-b73ee306d059
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597049975 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.1597049975
Directory /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.528166516
Short name T330
Test name
Test status
Simulation time 4892992068 ps
CPU time 541.73 seconds
Started Aug 04 07:31:28 PM PDT 24
Finished Aug 04 07:40:30 PM PDT 24
Peak memory 621376 kb
Host smart-757ee49f-75a9-4da6-9f04-66ac76bb5da1
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528166
516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.528166516
Directory /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2583838639
Short name T761
Test name
Test status
Simulation time 2866474588 ps
CPU time 214.72 seconds
Started Aug 04 07:39:39 PM PDT 24
Finished Aug 04 07:43:14 PM PDT 24
Peak memory 608476 kb
Host smart-0af799e8-b964-485e-969e-10add3fe33e3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583838639 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_rv_plic_smoketest.2583838639
Directory /workspace/1.chip_sw_rv_plic_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_rv_timer_irq.116955398
Short name T273
Test name
Test status
Simulation time 2617522652 ps
CPU time 234.07 seconds
Started Aug 04 07:27:18 PM PDT 24
Finished Aug 04 07:31:12 PM PDT 24
Peak memory 608464 kb
Host smart-a722fb1b-caad-4f77-b926-c34234ecca85
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116955398 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_rv_timer_irq.116955398
Directory /workspace/1.chip_sw_rv_timer_irq/latest

Test location /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.942940577
Short name T272
Test name
Test status
Simulation time 2625365340 ps
CPU time 267.53 seconds
Started Aug 04 07:35:14 PM PDT 24
Finished Aug 04 07:39:42 PM PDT 24
Peak memory 609656 kb
Host smart-70e2aef7-ebed-49c5-9fff-a7954ba8d0f8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942940577 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_rv_timer_smoketest.942940577
Directory /workspace/1.chip_sw_rv_timer_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1622799628
Short name T771
Test name
Test status
Simulation time 3335798288 ps
CPU time 305.63 seconds
Started Aug 04 07:30:09 PM PDT 24
Finished Aug 04 07:35:15 PM PDT 24
Peak memory 609716 kb
Host smart-d311f1f5-0692-48f9-ab10-82deacb465b0
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622799
628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.1622799628
Directory /workspace/1.chip_sw_sensor_ctrl_status/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pin_wake.4216427549
Short name T132
Test name
Test status
Simulation time 5999556000 ps
CPU time 485.68 seconds
Started Aug 04 07:23:19 PM PDT 24
Finished Aug 04 07:31:25 PM PDT 24
Peak memory 610916 kb
Host smart-d8c3e946-4293-46f7-807d-4dc5df4d5314
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216427549
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.4216427549
Directory /workspace/1.chip_sw_sleep_pin_wake/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2944967485
Short name T323
Test name
Test status
Simulation time 9376836970 ps
CPU time 1317.22 seconds
Started Aug 04 07:21:19 PM PDT 24
Finished Aug 04 07:43:16 PM PDT 24
Peak memory 610796 kb
Host smart-b33205dd-d19e-4cc6-8aa4-0099941d4e50
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944967485 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.2944967485
Directory /workspace/1.chip_sw_sleep_pwm_pulses/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.402277321
Short name T653
Test name
Test status
Simulation time 6729153050 ps
CPU time 559.87 seconds
Started Aug 04 07:30:45 PM PDT 24
Finished Aug 04 07:40:05 PM PDT 24
Peak memory 610672 kb
Host smart-7325abb8-134a-47cc-aa10-f12c55a5f396
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402277321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sle
ep_sram_ret_contents_no_scramble.402277321
Directory /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3666760597
Short name T847
Test name
Test status
Simulation time 7998016054 ps
CPU time 841.68 seconds
Started Aug 04 07:31:18 PM PDT 24
Finished Aug 04 07:45:20 PM PDT 24
Peak memory 610676 kb
Host smart-8b143ac6-da92-4f7a-92a7-4aa73e97a37e
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666760597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep
_sram_ret_contents_scramble.3666760597
Directory /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_pass_through.4248541081
Short name T241
Test name
Test status
Simulation time 6603370052 ps
CPU time 780.51 seconds
Started Aug 04 07:22:28 PM PDT 24
Finished Aug 04 07:35:29 PM PDT 24
Peak memory 624868 kb
Host smart-604c40c1-f0b4-4c1c-8d3f-aaada1df90b2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248541081 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.4248541081
Directory /workspace/1.chip_sw_spi_device_pass_through/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1905132895
Short name T101
Test name
Test status
Simulation time 4913842360 ps
CPU time 652.56 seconds
Started Aug 04 07:23:28 PM PDT 24
Finished Aug 04 07:34:21 PM PDT 24
Peak memory 624856 kb
Host smart-a1cfad4f-4ea7-4a93-9ed1-29304f6d8d6c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905132895 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.1905132895
Directory /workspace/1.chip_sw_spi_device_pass_through_collision/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.1545389407
Short name T108
Test name
Test status
Simulation time 3391875355 ps
CPU time 316.69 seconds
Started Aug 04 07:23:58 PM PDT 24
Finished Aug 04 07:29:16 PM PDT 24
Peak memory 618056 kb
Host smart-7c34496b-6af4-4825-beb9-d5826264e19c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545389407 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.1545389407
Directory /workspace/1.chip_sw_spi_device_pinmux_sleep_retention/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_tpm.3218666447
Short name T42
Test name
Test status
Simulation time 3460346271 ps
CPU time 358.59 seconds
Started Aug 04 07:23:17 PM PDT 24
Finished Aug 04 07:29:15 PM PDT 24
Peak memory 618100 kb
Host smart-11e87919-9d0a-4364-be96-bcd6e759f0b1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218666447 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.3218666447
Directory /workspace/1.chip_sw_spi_device_tpm/latest

Test location /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3941619996
Short name T36
Test name
Test status
Simulation time 3158815048 ps
CPU time 280.55 seconds
Started Aug 04 07:23:05 PM PDT 24
Finished Aug 04 07:27:46 PM PDT 24
Peak memory 610144 kb
Host smart-eb739de1-a8a9-4dcd-9be3-8e06611c52ad
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941619996 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.3941619996
Directory /workspace/1.chip_sw_spi_host_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3871513119
Short name T182
Test name
Test status
Simulation time 8837928072 ps
CPU time 944.36 seconds
Started Aug 04 07:30:44 PM PDT 24
Finished Aug 04 07:46:29 PM PDT 24
Peak memory 610376 kb
Host smart-337dcf8b-ce3f-4c31-9641-ae14f3d4e0fc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871513119 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.3871513119
Directory /workspace/1.chip_sw_sram_ctrl_execution_main/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2830524598
Short name T179
Test name
Test status
Simulation time 5807748920 ps
CPU time 713.67 seconds
Started Aug 04 07:32:43 PM PDT 24
Finished Aug 04 07:44:37 PM PDT 24
Peak memory 611408 kb
Host smart-ff0f8a2a-8e80-49cd-9fc2-e8935c8400df
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830524598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr
l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw
_sram_ctrl_scrambled_access.2830524598
Directory /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1489033198
Short name T297
Test name
Test status
Simulation time 4258530003 ps
CPU time 565.29 seconds
Started Aug 04 07:30:51 PM PDT 24
Finished Aug 04 07:40:17 PM PDT 24
Peak memory 610984 kb
Host smart-fc917c1d-1419-457c-af12-bc1be1c355b0
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s
w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489033198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1489033198
Directory /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3067362068
Short name T903
Test name
Test status
Simulation time 5472179651 ps
CPU time 644.88 seconds
Started Aug 04 07:32:18 PM PDT 24
Finished Aug 04 07:43:03 PM PDT 24
Peak memory 611164 kb
Host smart-81d36c11-21c0-43fd-946e-99c03c676d8f
User root
Command /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk
_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067362068 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3067362068
Directory /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3010396476
Short name T1001
Test name
Test status
Simulation time 2894725420 ps
CPU time 256.25 seconds
Started Aug 04 07:35:57 PM PDT 24
Finished Aug 04 07:40:13 PM PDT 24
Peak memory 609836 kb
Host smart-01753ae4-5da9-445a-bcc7-66493d41f5a2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010396476 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.3010396476
Directory /workspace/1.chip_sw_sram_ctrl_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.4120539751
Short name T660
Test name
Test status
Simulation time 20686182546 ps
CPU time 3827.32 seconds
Started Aug 04 07:27:10 PM PDT 24
Finished Aug 04 08:30:58 PM PDT 24
Peak memory 609364 kb
Host smart-bcd71ddf-469c-4986-a5a3-043799b67f46
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120539751 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.4120539751
Directory /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1341237804
Short name T138
Test name
Test status
Simulation time 4636872901 ps
CPU time 749.84 seconds
Started Aug 04 07:29:39 PM PDT 24
Finished Aug 04 07:42:12 PM PDT 24
Peak memory 614824 kb
Host smart-e7b61e7c-970a-4153-9cfe-c93ae3328494
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341237804 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.1341237804
Directory /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1763639173
Short name T848
Test name
Test status
Simulation time 2955208947 ps
CPU time 251.86 seconds
Started Aug 04 07:26:34 PM PDT 24
Finished Aug 04 07:30:47 PM PDT 24
Peak memory 613260 kb
Host smart-0110e241-d6ee-4974-b0a6-60e557910506
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763639173 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.1763639173
Directory /workspace/1.chip_sw_sysrst_ctrl_inputs/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3592956555
Short name T243
Test name
Test status
Simulation time 3871897432 ps
CPU time 436.94 seconds
Started Aug 04 07:27:29 PM PDT 24
Finished Aug 04 07:34:47 PM PDT 24
Peak memory 609228 kb
Host smart-07890cdb-4c3b-4838-8d5a-b459c1a63f09
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592956555 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.3592956555
Directory /workspace/1.chip_sw_sysrst_ctrl_outputs/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4211709300
Short name T874
Test name
Test status
Simulation time 21686150400 ps
CPU time 1695.06 seconds
Started Aug 04 07:26:39 PM PDT 24
Finished Aug 04 07:54:55 PM PDT 24
Peak memory 613912 kb
Host smart-c6d398da-84b0-4f91-b019-a9ec2eaef053
User root
Command /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42117093
00 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.4211709300
Directory /workspace/1.chip_sw_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1680021299
Short name T37
Test name
Test status
Simulation time 5437453014 ps
CPU time 483.89 seconds
Started Aug 04 07:28:48 PM PDT 24
Finished Aug 04 07:36:52 PM PDT 24
Peak memory 610756 kb
Host smart-9e2decb1-2db6-442c-92df-99aecb865e61
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680021299 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1680021299
Directory /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1027943469
Short name T772
Test name
Test status
Simulation time 3996139040 ps
CPU time 750.25 seconds
Started Aug 04 07:23:14 PM PDT 24
Finished Aug 04 07:35:45 PM PDT 24
Peak memory 624504 kb
Host smart-7c0c2fbf-9a9f-45b7-a638-ece87c81278f
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1027943469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.1027943469
Directory /workspace/1.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/1.chip_sw_uart_smoketest.1654770875
Short name T587
Test name
Test status
Simulation time 2545049316 ps
CPU time 260.22 seconds
Started Aug 04 07:35:32 PM PDT 24
Finished Aug 04 07:39:52 PM PDT 24
Peak memory 615024 kb
Host smart-9280c4de-b2e0-487b-a3b4-7a204778a88e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654770875 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_sw_uart_smoketest.1654770875
Directory /workspace/1.chip_sw_uart_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx.1949811335
Short name T650
Test name
Test status
Simulation time 4280416744 ps
CPU time 615.41 seconds
Started Aug 04 07:21:47 PM PDT 24
Finished Aug 04 07:32:03 PM PDT 24
Peak memory 623656 kb
Host smart-8f6da3b9-e8e0-46ff-b46f-ac356835b233
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949811335 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.1949811335
Directory /workspace/1.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2956723870
Short name T988
Test name
Test status
Simulation time 4126991294 ps
CPU time 478.5 seconds
Started Aug 04 07:22:30 PM PDT 24
Finished Aug 04 07:30:29 PM PDT 24
Peak memory 623288 kb
Host smart-81549f36-37ba-489a-a6df-407b401a906d
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956723870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx
_alt_clk_freq.2956723870
Directory /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2799389986
Short name T726
Test name
Test status
Simulation time 8458865238 ps
CPU time 1060.5 seconds
Started Aug 04 07:21:52 PM PDT 24
Finished Aug 04 07:39:33 PM PDT 24
Peak memory 624520 kb
Host smart-57ce3e6b-498a-4e54-bbc1-6cd45b9f5dba
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799389986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.2799389986
Directory /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.28471530
Short name T656
Test name
Test status
Simulation time 78430620950 ps
CPU time 13738.9 seconds
Started Aug 04 07:25:25 PM PDT 24
Finished Aug 04 11:14:26 PM PDT 24
Peak memory 634188 kb
Host smart-e6576c0e-e406-4d4b-9644-3af237ea8f71
User root
Command /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=28471530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.28471530
Directory /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.4043617923
Short name T948
Test name
Test status
Simulation time 4141447368 ps
CPU time 659.62 seconds
Started Aug 04 07:25:02 PM PDT 24
Finished Aug 04 07:36:03 PM PDT 24
Peak memory 624076 kb
Host smart-9f568927-563c-45fe-92dc-98ab040c7896
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043617923 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.4043617923
Directory /workspace/1.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.4081790415
Short name T823
Test name
Test status
Simulation time 5144819608 ps
CPU time 637.62 seconds
Started Aug 04 07:23:18 PM PDT 24
Finished Aug 04 07:33:56 PM PDT 24
Peak memory 624244 kb
Host smart-9e68f63a-bdfe-44bb-9b14-20e5065ed194
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081790415 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.4081790415
Directory /workspace/1.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3775647595
Short name T606
Test name
Test status
Simulation time 4441969990 ps
CPU time 537.05 seconds
Started Aug 04 07:23:01 PM PDT 24
Finished Aug 04 07:31:59 PM PDT 24
Peak memory 624260 kb
Host smart-60fcc306-6115-45bc-949f-946c9d1dfd22
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775647595 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.3775647595
Directory /workspace/1.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/1.chip_tap_straps_prod.4039664807
Short name T892
Test name
Test status
Simulation time 2367802314 ps
CPU time 146.28 seconds
Started Aug 04 07:32:38 PM PDT 24
Finished Aug 04 07:35:05 PM PDT 24
Peak memory 623404 kb
Host smart-ab495aeb-963c-4b83-ac89-5924c3e32c57
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4039664807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.4039664807
Directory /workspace/1.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/1.chip_tap_straps_rma.858564324
Short name T91
Test name
Test status
Simulation time 3652373810 ps
CPU time 255.14 seconds
Started Aug 04 07:32:02 PM PDT 24
Finished Aug 04 07:36:17 PM PDT 24
Peak memory 624268 kb
Host smart-11588559-523d-4aad-8742-a86f667e5371
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858564324 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.858564324
Directory /workspace/1.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/1.chip_tap_straps_testunlock0.351466992
Short name T795
Test name
Test status
Simulation time 5247794294 ps
CPU time 421.79 seconds
Started Aug 04 07:33:02 PM PDT 24
Finished Aug 04 07:40:04 PM PDT 24
Peak memory 631824 kb
Host smart-7348a807-aa66-4fd5-9ebf-80fa3f340ebd
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351466992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.351466992
Directory /workspace/1.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_dev.39514865
Short name T537
Test name
Test status
Simulation time 15571191170 ps
CPU time 3809.21 seconds
Started Aug 04 07:37:34 PM PDT 24
Finished Aug 04 08:41:04 PM PDT 24
Peak memory 610972 kb
Host smart-458771d0-a5f5-4141-83a9-726d648c15d8
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39514865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
rom_e2e_asm_init_dev.39514865
Directory /workspace/1.rom_e2e_asm_init_dev/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_prod.3876372749
Short name T707
Test name
Test status
Simulation time 16158735232 ps
CPU time 3553.63 seconds
Started Aug 04 07:38:15 PM PDT 24
Finished Aug 04 08:37:29 PM PDT 24
Peak memory 610324 kb
Host smart-164f4076-098d-4d14-992e-7ea1985b5be2
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876372749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_
SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rom_e2e_asm_init_prod.3876372749
Directory /workspace/1.rom_e2e_asm_init_prod/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2790082635
Short name T632
Test name
Test status
Simulation time 15701245586 ps
CPU time 4319.34 seconds
Started Aug 04 07:37:31 PM PDT 24
Finished Aug 04 08:49:31 PM PDT 24
Peak memory 610276 kb
Host smart-f4ab4560-e4c7-4266-a673-55552709717a
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790082635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_e2e_asm_init_prod_end.2790082635
Directory /workspace/1.rom_e2e_asm_init_prod_end/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_rma.1492138228
Short name T532
Test name
Test status
Simulation time 15038553334 ps
CPU time 4177.63 seconds
Started Aug 04 07:38:25 PM PDT 24
Finished Aug 04 08:48:03 PM PDT 24
Peak memory 610276 kb
Host smart-174928d6-b71e-497e-b1ba-df9d7ef96bc7
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492138228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rom_e2e_asm_init_rma.1492138228
Directory /workspace/1.rom_e2e_asm_init_rma/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2683358324
Short name T966
Test name
Test status
Simulation time 11483825288 ps
CPU time 2973.44 seconds
Started Aug 04 07:38:04 PM PDT 24
Finished Aug 04 08:27:38 PM PDT 24
Peak memory 610556 kb
Host smart-e9249cb1-ec4a-4ebc-95f2-4e271c32ffcb
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683358324 -assert nopostproc +UVM_TESTNAME=chip_base_te
st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.rom_e2e_asm_init_test_unlocked0.2683358324
Directory /workspace/1.rom_e2e_asm_init_test_unlocked0/latest

Test location /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1008513315
Short name T718
Test name
Test status
Simulation time 14802236488 ps
CPU time 3748.71 seconds
Started Aug 04 07:37:58 PM PDT 24
Finished Aug 04 08:40:28 PM PDT 24
Peak memory 609784 kb
Host smart-d8bb0791-6442-46b0-ac43-27d30e18d77c
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid
_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008513315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip
_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in
it_rom_ext_invalid_meas.1008513315
Directory /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2582529772
Short name T51
Test name
Test status
Simulation time 14919943720 ps
CPU time 3374.35 seconds
Started Aug 04 07:38:15 PM PDT 24
Finished Aug 04 08:34:29 PM PDT 24
Peak memory 610200 kb
Host smart-df46abe4-c286-4164-b374-60531977f37d
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:
new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582529772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.2582529772
Directory /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2122732399
Short name T806
Test name
Test status
Simulation time 15535819634 ps
CPU time 3853.43 seconds
Started Aug 04 07:37:08 PM PDT 24
Finished Aug 04 08:41:22 PM PDT 24
Peak memory 610156 kb
Host smart-bbc8f655-5bf8-4e16-81e1-6b20c129cfcd
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas
:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122732399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext
_no_meas.2122732399
Directory /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location /workspace/coverage/default/1.rom_e2e_self_hash.1136267790
Short name T358
Test name
Test status
Simulation time 25661593336 ps
CPU time 5440.13 seconds
Started Aug 04 07:37:47 PM PDT 24
Finished Aug 04 09:08:27 PM PDT 24
Peak memory 610164 kb
Host smart-f4fbff37-dc35-4739-84e4-ba659a04907f
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r
ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136267790 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.1136267790
Directory /workspace/1.rom_e2e_self_hash/latest

Test location /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2211881165
Short name T697
Test name
Test status
Simulation time 14856905856 ps
CPU time 3766.21 seconds
Started Aug 04 07:37:09 PM PDT 24
Finished Aug 04 08:39:55 PM PDT 24
Peak memory 611128 kb
Host smart-51ad1f47-3e1c-4f65-84b2-0e26188fd2b2
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne
w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211881165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu
tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_
shutdown_exception_c.2211881165
Directory /workspace/1.rom_e2e_shutdown_exception_c/latest

Test location /workspace/coverage/default/1.rom_e2e_shutdown_output.403592570
Short name T754
Test name
Test status
Simulation time 29231670600 ps
CPU time 3678.93 seconds
Started Aug 04 07:36:34 PM PDT 24
Finished Aug 04 08:37:53 PM PDT 24
Peak memory 611240 kb
Host smart-aa5f1f59-5ddb-4ef8-8444-ee1f88e1f9d5
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f
lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403592570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip
_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rom_e2e_shutdown_output.403592570
Directory /workspace/1.rom_e2e_shutdown_output/latest

Test location /workspace/coverage/default/1.rom_e2e_smoke.2969881603
Short name T743
Test name
Test status
Simulation time 15417703680 ps
CPU time 3498.97 seconds
Started Aug 04 07:38:59 PM PDT 24
Finished Aug 04 08:37:18 PM PDT 24
Peak memory 610128 kb
Host smart-0c32aef5-e940-4426-8c85-0da5ec242346
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img
_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to
p/hw/dv/tools/sim.tcl +ntb_random_seed=2969881603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.2969881603
Directory /workspace/1.rom_e2e_smoke/latest

Test location /workspace/coverage/default/1.rom_e2e_static_critical.868107335
Short name T290
Test name
Test status
Simulation time 17565295566 ps
CPU time 4379.04 seconds
Started Aug 04 07:39:06 PM PDT 24
Finished Aug 04 08:52:05 PM PDT 24
Peak memory 610148 kb
Host smart-8592e172-0776-4329-a5cc-886eb89fe125
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul
es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868107335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.868107335
Directory /workspace/1.rom_e2e_static_critical/latest

Test location /workspace/coverage/default/1.rom_keymgr_functest.1291320760
Short name T1013
Test name
Test status
Simulation time 4551203752 ps
CPU time 634.91 seconds
Started Aug 04 07:35:17 PM PDT 24
Finished Aug 04 07:45:52 PM PDT 24
Peak memory 610608 kb
Host smart-5824f464-bde1-4ca6-b8dc-726ff94c550f
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291320760 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.1291320760
Directory /workspace/1.rom_keymgr_functest/latest

Test location /workspace/coverage/default/1.rom_raw_unlock.1504002994
Short name T198
Test name
Test status
Simulation time 5900330313 ps
CPU time 272.9 seconds
Started Aug 04 07:34:35 PM PDT 24
Finished Aug 04 07:39:08 PM PDT 24
Peak memory 623720 kb
Host smart-3f5880ec-e7c6-493c-9e8b-afca21608d83
User root
Command /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE
xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1504002994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.1504002994
Directory /workspace/1.rom_raw_unlock/latest

Test location /workspace/coverage/default/1.rom_volatile_raw_unlock.2544939161
Short name T790
Test name
Test status
Simulation time 2828310901 ps
CPU time 108.76 seconds
Started Aug 04 07:33:49 PM PDT 24
Finished Aug 04 07:35:38 PM PDT 24
Peak memory 617012 kb
Host smart-8b7bb4a0-1f3c-4aff-b374-67bf7f014e68
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1
+sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544939161 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.2544939161
Directory /workspace/1.rom_volatile_raw_unlock/latest

Test location /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.250148358
Short name T659
Test name
Test status
Simulation time 9881701655 ps
CPU time 808.68 seconds
Started Aug 04 07:51:58 PM PDT 24
Finished Aug 04 08:05:27 PM PDT 24
Peak memory 620428 kb
Host smart-a4bb10ee-c087-4436-bda3-278d0b1933d7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250148358 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.250148358
Directory /workspace/10.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2047472182
Short name T703
Test name
Test status
Simulation time 4815134430 ps
CPU time 543.15 seconds
Started Aug 04 07:51:13 PM PDT 24
Finished Aug 04 08:00:16 PM PDT 24
Peak memory 624488 kb
Host smart-b7789565-8bb5-4621-be61-3b6147de21e0
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2047472182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.2047472182
Directory /workspace/10.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.330874615
Short name T528
Test name
Test status
Simulation time 10949290177 ps
CPU time 683.06 seconds
Started Aug 04 07:51:39 PM PDT 24
Finished Aug 04 08:03:03 PM PDT 24
Peak memory 620328 kb
Host smart-76818a6e-4cd4-486a-b62b-87c4265d3cdd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330874615 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.330874615
Directory /workspace/11.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1007500606
Short name T808
Test name
Test status
Simulation time 13660718200 ps
CPU time 2568.47 seconds
Started Aug 04 07:52:08 PM PDT 24
Finished Aug 04 08:34:57 PM PDT 24
Peak memory 624644 kb
Host smart-9ffec2f2-911a-455d-ade3-35513aa5df9e
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1007500606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.1007500606
Directory /workspace/11.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2929547706
Short name T55
Test name
Test status
Simulation time 4705302109 ps
CPU time 382.25 seconds
Started Aug 04 07:52:58 PM PDT 24
Finished Aug 04 07:59:21 PM PDT 24
Peak memory 620440 kb
Host smart-ba3431d4-2bb5-43dd-8c76-937ee781816f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929547706 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.2929547706
Directory /workspace/12.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3232813586
Short name T305
Test name
Test status
Simulation time 8041275176 ps
CPU time 1948.03 seconds
Started Aug 04 07:51:49 PM PDT 24
Finished Aug 04 08:24:17 PM PDT 24
Peak memory 623248 kb
Host smart-03961fbc-9568-4ed2-8e9b-eb890f5cc189
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3232813586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.3232813586
Directory /workspace/12.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.340617232
Short name T993
Test name
Test status
Simulation time 12796434383 ps
CPU time 1172.16 seconds
Started Aug 04 07:52:14 PM PDT 24
Finished Aug 04 08:11:47 PM PDT 24
Peak memory 620388 kb
Host smart-1d022099-7c34-40a9-94bf-52f6af6c9ea4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340617232 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.340617232
Directory /workspace/13.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2735239322
Short name T349
Test name
Test status
Simulation time 4357535150 ps
CPU time 670.84 seconds
Started Aug 04 07:51:58 PM PDT 24
Finished Aug 04 08:03:10 PM PDT 24
Peak memory 624484 kb
Host smart-e0e9ca7e-2063-40fc-9052-47cdbbb07c27
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2735239322 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.2735239322
Directory /workspace/13.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1206443715
Short name T617
Test name
Test status
Simulation time 12395235632 ps
CPU time 962.72 seconds
Started Aug 04 07:52:28 PM PDT 24
Finished Aug 04 08:08:31 PM PDT 24
Peak memory 621276 kb
Host smart-c170c6a6-61d2-4d6f-aa15-7aed398de0d4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206443715 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.1206443715
Directory /workspace/14.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.839226213
Short name T585
Test name
Test status
Simulation time 8543218872 ps
CPU time 1240.03 seconds
Started Aug 04 07:53:47 PM PDT 24
Finished Aug 04 08:14:28 PM PDT 24
Peak memory 624520 kb
Host smart-4253616d-d1f4-43cd-afee-34e404b34101
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=839226213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.839226213
Directory /workspace/14.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3284551212
Short name T363
Test name
Test status
Simulation time 4816584776 ps
CPU time 541.12 seconds
Started Aug 04 07:52:20 PM PDT 24
Finished Aug 04 08:01:22 PM PDT 24
Peak memory 623220 kb
Host smart-d6f95a9a-b869-46a2-a12e-a691441d0ae4
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3284551212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.3284551212
Directory /workspace/15.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.168352503
Short name T435
Test name
Test status
Simulation time 3708118664 ps
CPU time 349 seconds
Started Aug 04 07:53:52 PM PDT 24
Finished Aug 04 07:59:41 PM PDT 24
Peak memory 649248 kb
Host smart-a8d83cc9-c004-4346-a920-27edeae13fc2
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168352503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_s
w_alert_handler_lpg_sleep_mode_alerts.168352503
Directory /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/16.chip_sw_all_escalation_resets.1618099961
Short name T432
Test name
Test status
Simulation time 5485866648 ps
CPU time 460.01 seconds
Started Aug 04 07:53:55 PM PDT 24
Finished Aug 04 08:01:35 PM PDT 24
Peak memory 650032 kb
Host smart-d5ba6497-ea29-4fb7-9e78-6025468a17d0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1618099961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.1618099961
Directory /workspace/16.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.732241682
Short name T569
Test name
Test status
Simulation time 4437601524 ps
CPU time 557.03 seconds
Started Aug 04 07:54:07 PM PDT 24
Finished Aug 04 08:03:24 PM PDT 24
Peak memory 624520 kb
Host smart-dab47dda-9cc4-484b-aaea-226b8bef2e84
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=732241682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.732241682
Directory /workspace/16.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/17.chip_sw_all_escalation_resets.1185304587
Short name T309
Test name
Test status
Simulation time 5454709692 ps
CPU time 645.33 seconds
Started Aug 04 07:53:16 PM PDT 24
Finished Aug 04 08:04:01 PM PDT 24
Peak memory 650276 kb
Host smart-8078becb-1462-41a4-a04f-767cbd3a4218
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1185304587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.1185304587
Directory /workspace/17.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.869962236
Short name T620
Test name
Test status
Simulation time 8101094780 ps
CPU time 1819.78 seconds
Started Aug 04 07:54:20 PM PDT 24
Finished Aug 04 08:24:41 PM PDT 24
Peak memory 624500 kb
Host smart-ff583ffa-20d7-48da-8f3f-6ad5daf00289
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=869962236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.869962236
Directory /workspace/17.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3720621415
Short name T93
Test name
Test status
Simulation time 13206576800 ps
CPU time 2737.6 seconds
Started Aug 04 07:54:01 PM PDT 24
Finished Aug 04 08:39:40 PM PDT 24
Peak memory 624508 kb
Host smart-6e631f68-2e86-44d4-8fee-6d7bed4072e5
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3720621415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.3720621415
Directory /workspace/18.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.386033127
Short name T625
Test name
Test status
Simulation time 3633230518 ps
CPU time 430.96 seconds
Started Aug 04 07:53:39 PM PDT 24
Finished Aug 04 08:00:50 PM PDT 24
Peak memory 622188 kb
Host smart-d96d70ee-653f-437c-93fa-4e345d38c837
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=386033127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.386033127
Directory /workspace/19.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/2.chip_jtag_mem_access.158290930
Short name T174
Test name
Test status
Simulation time 13795220888 ps
CPU time 1277 seconds
Started Aug 04 07:37:57 PM PDT 24
Finished Aug 04 07:59:14 PM PDT 24
Peak memory 607964 kb
Host smart-d3a99ddd-df13-4a49-b645-6b841c329f91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158290930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m
em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.158290930
Directory /workspace/2.chip_jtag_mem_access/latest

Test location /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3198509130
Short name T333
Test name
Test status
Simulation time 3826113064 ps
CPU time 480.54 seconds
Started Aug 04 07:46:06 PM PDT 24
Finished Aug 04 07:54:07 PM PDT 24
Peak memory 620056 kb
Host smart-7e2910b9-a3a4-4f79-8763-867f8080d5c6
User root
Command /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3
198509130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.3198509130
Directory /workspace/2.chip_rv_dm_ndm_reset_req/latest

Test location /workspace/coverage/default/2.chip_sival_flash_info_access.1481918581
Short name T631
Test name
Test status
Simulation time 3637861656 ps
CPU time 352.3 seconds
Started Aug 04 07:36:47 PM PDT 24
Finished Aug 04 07:42:40 PM PDT 24
Peak memory 609688 kb
Host smart-a4a38edd-9653-4204-8521-f5b17c933443
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=1481918581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.1481918581
Directory /workspace/2.chip_sival_flash_info_access/latest

Test location /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1401232190
Short name T873
Test name
Test status
Simulation time 19594446168 ps
CPU time 567.85 seconds
Started Aug 04 07:41:43 PM PDT 24
Finished Aug 04 07:51:11 PM PDT 24
Peak memory 619332 kb
Host smart-5e95fa72-67c4-4d1d-a3e2-beffe7e08e48
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1401232190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1401232190
Directory /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_aes_enc.4122469708
Short name T994
Test name
Test status
Simulation time 3204432980 ps
CPU time 346.11 seconds
Started Aug 04 07:39:43 PM PDT 24
Finished Aug 04 07:45:29 PM PDT 24
Peak memory 609712 kb
Host smart-1f6ce997-4d94-4808-ba7b-617a17fd50b1
User root
Command /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122469708 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.4122469708
Directory /workspace/2.chip_sw_aes_enc/latest

Test location /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1518547117
Short name T658
Test name
Test status
Simulation time 3015763153 ps
CPU time 259.11 seconds
Started Aug 04 07:40:24 PM PDT 24
Finished Aug 04 07:44:44 PM PDT 24
Peak memory 608476 kb
Host smart-4d81e2d5-377d-40af-90bf-a73775b4b961
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518
547117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.1518547117
Directory /workspace/2.chip_sw_aes_enc_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1758356320
Short name T639
Test name
Test status
Simulation time 2554337668 ps
CPU time 306.12 seconds
Started Aug 04 07:46:38 PM PDT 24
Finished Aug 04 07:51:45 PM PDT 24
Peak memory 608532 kb
Host smart-f8a9bcce-d25d-455d-8f41-e10fe929cdea
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1758356320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.1758356320
Directory /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_aes_entropy.2692857025
Short name T931
Test name
Test status
Simulation time 3058974764 ps
CPU time 278.72 seconds
Started Aug 04 07:42:00 PM PDT 24
Finished Aug 04 07:46:38 PM PDT 24
Peak memory 609800 kb
Host smart-a6a802a8-ae77-43d9-b18f-e0ee10775294
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692857025 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.2692857025
Directory /workspace/2.chip_sw_aes_entropy/latest

Test location /workspace/coverage/default/2.chip_sw_aes_idle.514949985
Short name T940
Test name
Test status
Simulation time 2612295576 ps
CPU time 295.38 seconds
Started Aug 04 07:40:43 PM PDT 24
Finished Aug 04 07:45:38 PM PDT 24
Peak memory 609656 kb
Host smart-556c97e7-995f-417f-b68f-274ab56aea11
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514949985 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.514949985
Directory /workspace/2.chip_sw_aes_idle/latest

Test location /workspace/coverage/default/2.chip_sw_aes_masking_off.479100770
Short name T643
Test name
Test status
Simulation time 2744579439 ps
CPU time 342.36 seconds
Started Aug 04 07:41:00 PM PDT 24
Finished Aug 04 07:46:43 PM PDT 24
Peak memory 609400 kb
Host smart-a8d02e4e-6213-40d3-8903-12790781f927
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479100770 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.479100770
Directory /workspace/2.chip_sw_aes_masking_off/latest

Test location /workspace/coverage/default/2.chip_sw_aes_smoketest.3556568220
Short name T691
Test name
Test status
Simulation time 3459512504 ps
CPU time 311.81 seconds
Started Aug 04 07:48:08 PM PDT 24
Finished Aug 04 07:53:20 PM PDT 24
Peak memory 609672 kb
Host smart-f412046e-1759-4e03-aa1c-f5b80b83ea34
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556568220 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_aes_smoketest.3556568220
Directory /workspace/2.chip_sw_aes_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_entropy.3905269924
Short name T974
Test name
Test status
Simulation time 3368362439 ps
CPU time 247.93 seconds
Started Aug 04 07:41:36 PM PDT 24
Finished Aug 04 07:45:45 PM PDT 24
Peak memory 609736 kb
Host smart-308a497e-f88b-45b6-9f2d-a3df54f742bb
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3905269924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.3905269924
Directory /workspace/2.chip_sw_alert_handler_entropy/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_escalation.756784426
Short name T175
Test name
Test status
Simulation time 5463876120 ps
CPU time 613.82 seconds
Started Aug 04 07:40:06 PM PDT 24
Finished Aug 04 07:50:20 PM PDT 24
Peak memory 619656 kb
Host smart-b8c87793-24f3-4e19-bebf-4e50585ca593
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=756784426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.756784426
Directory /workspace/2.chip_sw_alert_handler_escalation/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2769330564
Short name T648
Test name
Test status
Simulation time 8901656840 ps
CPU time 1779.21 seconds
Started Aug 04 07:41:07 PM PDT 24
Finished Aug 04 08:10:47 PM PDT 24
Peak memory 610272 kb
Host smart-c4000e01-968d-4a64-8802-95928d5f1c33
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2769330564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.2769330564
Directory /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.261485187
Short name T690
Test name
Test status
Simulation time 8981815280 ps
CPU time 2085.88 seconds
Started Aug 04 07:42:10 PM PDT 24
Finished Aug 04 08:16:56 PM PDT 24
Peak memory 610180 kb
Host smart-5bc1435e-7f41-4151-933b-b79ce48891f7
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=261485187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_toggle.261485187
Directory /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3815280630
Short name T700
Test name
Test status
Simulation time 8220457856 ps
CPU time 1229.26 seconds
Started Aug 04 07:42:11 PM PDT 24
Finished Aug 04 08:02:41 PM PDT 24
Peak memory 609996 kb
Host smart-00e09e06-3145-410c-817d-cf9cb2f25725
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=3815280630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.3815280630
Directory /workspace/2.chip_sw_alert_handler_ping_ok/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3014952386
Short name T571
Test name
Test status
Simulation time 4759897214 ps
CPU time 574.34 seconds
Started Aug 04 07:41:27 PM PDT 24
Finished Aug 04 07:51:02 PM PDT 24
Peak memory 610140 kb
Host smart-02ec5d95-893f-4bc0-aeeb-f8b9045df02e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3014952386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.3014952386
Directory /workspace/2.chip_sw_alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1357052311
Short name T638
Test name
Test status
Simulation time 256412116848 ps
CPU time 11049.5 seconds
Started Aug 04 07:42:17 PM PDT 24
Finished Aug 04 10:46:28 PM PDT 24
Peak memory 610820 kb
Host smart-cb79c370-df55-4d01-9da9-7981234a745a
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357052311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1357052311
Directory /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location /workspace/coverage/default/2.chip_sw_all_escalation_resets.3094010802
Short name T722
Test name
Test status
Simulation time 4446979288 ps
CPU time 541.44 seconds
Started Aug 04 07:35:49 PM PDT 24
Finished Aug 04 07:44:51 PM PDT 24
Peak memory 616956 kb
Host smart-ed6eba44-84ce-4857-a168-d89475e75b0b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3094010802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.3094010802
Directory /workspace/2.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_irq.852714928
Short name T324
Test name
Test status
Simulation time 4303369080 ps
CPU time 429.49 seconds
Started Aug 04 07:39:20 PM PDT 24
Finished Aug 04 07:46:30 PM PDT 24
Peak memory 609952 kb
Host smart-28236f01-436d-45f9-8393-03985a315198
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852714928 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.852714928
Directory /workspace/2.chip_sw_aon_timer_irq/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3819745635
Short name T825
Test name
Test status
Simulation time 7178725090 ps
CPU time 458.96 seconds
Started Aug 04 07:40:29 PM PDT 24
Finished Aug 04 07:48:08 PM PDT 24
Peak memory 610236 kb
Host smart-3dfc4414-feb4-42c0-90d5-feb3fd07e56f
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3819745635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3819745635
Directory /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2579733171
Short name T842
Test name
Test status
Simulation time 3345038964 ps
CPU time 359.55 seconds
Started Aug 04 07:49:50 PM PDT 24
Finished Aug 04 07:55:49 PM PDT 24
Peak memory 609700 kb
Host smart-da858670-571b-406a-ae92-1e008a68f0d4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579733171 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_aon_timer_smoketest.2579733171
Directory /workspace/2.chip_sw_aon_timer_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2613451792
Short name T287
Test name
Test status
Simulation time 7445309892 ps
CPU time 709.9 seconds
Started Aug 04 07:38:53 PM PDT 24
Finished Aug 04 07:50:43 PM PDT 24
Peak memory 610484 kb
Host smart-38b03d7e-1649-4aa1-9387-ce1366182417
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2613451792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.2613451792
Directory /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.4222343706
Short name T544
Test name
Test status
Simulation time 4444617468 ps
CPU time 732.42 seconds
Started Aug 04 07:39:40 PM PDT 24
Finished Aug 04 07:51:52 PM PDT 24
Peak memory 610668 kb
Host smart-c2ca3c12-fc57-4ca0-822c-67b1b24890ec
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4222343706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.4222343706
Directory /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location /workspace/coverage/default/2.chip_sw_ast_clk_outputs.608741286
Short name T442
Test name
Test status
Simulation time 7392304000 ps
CPU time 1134.22 seconds
Started Aug 04 07:46:38 PM PDT 24
Finished Aug 04 08:05:32 PM PDT 24
Peak memory 616340 kb
Host smart-e5cdc6a8-1cbc-44cc-a94d-9bea5bf8ed79
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608741286 -assert nopos
tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.608741286
Directory /workspace/2.chip_sw_ast_clk_outputs/latest

Test location /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1482372036
Short name T88
Test name
Test status
Simulation time 14766130486 ps
CPU time 2164.47 seconds
Started Aug 04 07:48:04 PM PDT 24
Finished Aug 04 08:24:09 PM PDT 24
Peak memory 611092 kb
Host smart-ae8d42f0-f47a-4a42-b20b-eea5c26436a9
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482372036
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.1482372036
Directory /workspace/2.chip_sw_ast_clk_rst_inputs/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2311149013
Short name T633
Test name
Test status
Simulation time 6864479750 ps
CPU time 551.36 seconds
Started Aug 04 07:44:27 PM PDT 24
Finished Aug 04 07:53:39 PM PDT 24
Peak memory 620444 kb
Host smart-31cd0a6b-6ee9-47cb-8576-d86580b9de86
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=2311149013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.2311149013
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.671957225
Short name T69
Test name
Test status
Simulation time 3500200470 ps
CPU time 727.42 seconds
Started Aug 04 07:45:51 PM PDT 24
Finished Aug 04 07:58:00 PM PDT 24
Peak memory 612876 kb
Host smart-0f1c28ce-3ee8-40db-81b7-899c89f29048
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671957225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl
kmgr_external_clk_src_for_sw_fast_dev.671957225
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1929505391
Short name T677
Test name
Test status
Simulation time 4188545308 ps
CPU time 701.84 seconds
Started Aug 04 07:44:10 PM PDT 24
Finished Aug 04 07:55:52 PM PDT 24
Peak memory 612124 kb
Host smart-55b68413-0bad-4f00-bdfd-d31ee8097a06
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929505391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_rma.1929505391
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2597378184
Short name T642
Test name
Test status
Simulation time 4082759370 ps
CPU time 694.94 seconds
Started Aug 04 07:46:08 PM PDT 24
Finished Aug 04 07:57:44 PM PDT 24
Peak memory 613172 kb
Host smart-3a241369-4993-4782-8f11-aad61bfeb6bd
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597378184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2597378184
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1011536021
Short name T602
Test name
Test status
Simulation time 4697041868 ps
CPU time 634.68 seconds
Started Aug 04 07:45:12 PM PDT 24
Finished Aug 04 07:55:47 PM PDT 24
Peak memory 612896 kb
Host smart-61d8b531-1599-48ff-b655-489e412b408e
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011536021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_dev.1011536021
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3937587784
Short name T803
Test name
Test status
Simulation time 4507018200 ps
CPU time 540.33 seconds
Started Aug 04 07:44:34 PM PDT 24
Finished Aug 04 07:53:34 PM PDT 24
Peak memory 612088 kb
Host smart-535d552e-d29f-4910-bfb1-93fb720e5ae7
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937587784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_rma.3937587784
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.759730593
Short name T831
Test name
Test status
Simulation time 4473342972 ps
CPU time 609.03 seconds
Started Aug 04 07:44:26 PM PDT 24
Finished Aug 04 07:54:35 PM PDT 24
Peak memory 613176 kb
Host smart-d2b05941-bf34-46b9-8062-77fa35eef3da
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759730593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM
_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.759730593
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2370717171
Short name T782
Test name
Test status
Simulation time 2067028647 ps
CPU time 210.54 seconds
Started Aug 04 07:45:48 PM PDT 24
Finished Aug 04 07:49:19 PM PDT 24
Peak memory 609556 kb
Host smart-dcf42d76-508b-4c69-a726-f99b6df189d7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370717171 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_clkmgr_jitter.2370717171
Directory /workspace/2.chip_sw_clkmgr_jitter/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1909971698
Short name T946
Test name
Test status
Simulation time 4123471764 ps
CPU time 586.83 seconds
Started Aug 04 07:44:35 PM PDT 24
Finished Aug 04 07:54:23 PM PDT 24
Peak memory 609740 kb
Host smart-f3eb5310-a49c-4402-990c-df584c6ebae7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909971698 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.1909971698
Directory /workspace/2.chip_sw_clkmgr_jitter_frequency/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2676375730
Short name T871
Test name
Test status
Simulation time 2363560090 ps
CPU time 192.53 seconds
Started Aug 04 07:45:39 PM PDT 24
Finished Aug 04 07:48:52 PM PDT 24
Peak memory 609652 kb
Host smart-959278bc-96af-49a1-9364-32cbf6d53660
User root
Command /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676375730 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.2676375730
Directory /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.785606387
Short name T607
Test name
Test status
Simulation time 4776004936 ps
CPU time 536.24 seconds
Started Aug 04 07:44:23 PM PDT 24
Finished Aug 04 07:53:20 PM PDT 24
Peak memory 610104 kb
Host smart-90d0fec1-80ee-4bbf-a3a4-e57eb834c3ff
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785606387 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.785606387
Directory /workspace/2.chip_sw_clkmgr_off_aes_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2262393804
Short name T668
Test name
Test status
Simulation time 4715903276 ps
CPU time 691.45 seconds
Started Aug 04 07:45:00 PM PDT 24
Finished Aug 04 07:56:32 PM PDT 24
Peak memory 610396 kb
Host smart-668ba50d-bf9a-4617-9541-d9cc6ad6fc3f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262393804 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.2262393804
Directory /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2530396413
Short name T702
Test name
Test status
Simulation time 4968734824 ps
CPU time 604.82 seconds
Started Aug 04 07:44:30 PM PDT 24
Finished Aug 04 07:54:36 PM PDT 24
Peak memory 610416 kb
Host smart-a73a3e27-c204-4868-8d84-f63b90c1ea4f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530396413 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.2530396413
Directory /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1310789080
Short name T861
Test name
Test status
Simulation time 4583956188 ps
CPU time 633.77 seconds
Started Aug 04 07:45:20 PM PDT 24
Finished Aug 04 07:55:54 PM PDT 24
Peak memory 610080 kb
Host smart-7501952c-c2a3-4cc3-b9c2-e484e575c17e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310789080 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.1310789080
Directory /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.2785197933
Short name T741
Test name
Test status
Simulation time 13920914924 ps
CPU time 1566.43 seconds
Started Aug 04 07:43:57 PM PDT 24
Finished Aug 04 08:10:04 PM PDT 24
Peak memory 610216 kb
Host smart-5f9a6fce-f056-44a2-9820-01c726f25cb4
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785197933
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.2785197933
Directory /workspace/2.chip_sw_clkmgr_off_peri/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3619949428
Short name T791
Test name
Test status
Simulation time 3585066660 ps
CPU time 361.16 seconds
Started Aug 04 07:44:04 PM PDT 24
Finished Aug 04 07:50:05 PM PDT 24
Peak memory 609848 kb
Host smart-85a0e6da-b81f-484d-9b5f-da4f64ef785e
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619949428 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.3619949428
Directory /workspace/2.chip_sw_clkmgr_reset_frequency/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1633496834
Short name T824
Test name
Test status
Simulation time 4507971120 ps
CPU time 567.3 seconds
Started Aug 04 07:44:53 PM PDT 24
Finished Aug 04 07:54:20 PM PDT 24
Peak memory 610276 kb
Host smart-80f377d3-0d9c-4b23-ac80-fa100e2f6f11
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633496834 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.1633496834
Directory /workspace/2.chip_sw_clkmgr_sleep_frequency/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.507049966
Short name T536
Test name
Test status
Simulation time 2283968660 ps
CPU time 164.35 seconds
Started Aug 04 07:47:31 PM PDT 24
Finished Aug 04 07:50:15 PM PDT 24
Peak memory 608492 kb
Host smart-d545085f-ab49-49ac-8910-a33d67d09125
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507049966 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.chip_sw_clkmgr_smoketest.507049966
Directory /workspace/2.chip_sw_clkmgr_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1235836760
Short name T1024
Test name
Test status
Simulation time 14772805696 ps
CPU time 3030.72 seconds
Started Aug 04 07:41:27 PM PDT 24
Finished Aug 04 08:31:58 PM PDT 24
Peak memory 610436 kb
Host smart-5bfb2863-83de-4cd1-b935-df3e0fa52a2d
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235836760 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.1235836760
Directory /workspace/2.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.671125541
Short name T225
Test name
Test status
Simulation time 5015025282 ps
CPU time 345.93 seconds
Started Aug 04 07:42:08 PM PDT 24
Finished Aug 04 07:47:54 PM PDT 24
Peak memory 610784 kb
Host smart-bde0923c-5a18-41b2-aad9-233973407850
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67112
5541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.671125541
Directory /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_kat_test.4164905270
Short name T821
Test name
Test status
Simulation time 2483895548 ps
CPU time 220.1 seconds
Started Aug 04 07:41:59 PM PDT 24
Finished Aug 04 07:45:39 PM PDT 24
Peak memory 609724 kb
Host smart-b536d16c-7226-47e0-926b-723f34cae906
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164905270 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.4164905270
Directory /workspace/2.chip_sw_csrng_kat_test/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3914115471
Short name T173
Test name
Test status
Simulation time 6232231575 ps
CPU time 825.36 seconds
Started Aug 04 07:41:49 PM PDT 24
Finished Aug 04 07:55:35 PM PDT 24
Peak memory 610972 kb
Host smart-0124ced9-bfa5-4c21-a837-db11ad494896
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima
ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914115471 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_
lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr
ng_lc_hw_debug_en_test.3914115471
Directory /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_smoketest.1085057986
Short name T292
Test name
Test status
Simulation time 2133663768 ps
CPU time 174.97 seconds
Started Aug 04 07:47:44 PM PDT 24
Finished Aug 04 07:50:39 PM PDT 24
Peak memory 608348 kb
Host smart-aa6e2287-57a0-45a0-9f29-0d5291081210
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085057986 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.chip_sw_csrng_smoketest.1085057986
Directory /workspace/2.chip_sw_csrng_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_edn_auto_mode.4185317216
Short name T737
Test name
Test status
Simulation time 6607387500 ps
CPU time 1912.59 seconds
Started Aug 04 07:43:34 PM PDT 24
Finished Aug 04 08:15:27 PM PDT 24
Peak memory 610244 kb
Host smart-09b028fa-d96d-468c-9711-8a9638c56b34
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185317216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_
auto_mode.4185317216
Directory /workspace/2.chip_sw_edn_auto_mode/latest

Test location /workspace/coverage/default/2.chip_sw_edn_boot_mode.227401462
Short name T186
Test name
Test status
Simulation time 2797984120 ps
CPU time 791.55 seconds
Started Aug 04 07:42:10 PM PDT 24
Finished Aug 04 07:55:21 PM PDT 24
Peak memory 610000 kb
Host smart-a1555d53-581a-4e87-9ddc-f49ded46dff2
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227401462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_b
oot_mode.227401462
Directory /workspace/2.chip_sw_edn_boot_mode/latest

Test location /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3170106802
Short name T817
Test name
Test status
Simulation time 6834317944 ps
CPU time 1621.59 seconds
Started Aug 04 07:42:21 PM PDT 24
Finished Aug 04 08:09:23 PM PDT 24
Peak memory 611000 kb
Host smart-689d7cb1-1d0d-4deb-9e3e-f3eb0b9a3100
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed
n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170106802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.3170106802
Directory /workspace/2.chip_sw_edn_entropy_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1491719792
Short name T800
Test name
Test status
Simulation time 6200034369 ps
CPU time 784.43 seconds
Started Aug 04 07:42:26 PM PDT 24
Finished Aug 04 07:55:31 PM PDT 24
Peak memory 610984 kb
Host smart-fb4d956d-19d2-4e66-81b6-60868fa59463
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e
ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491719792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.1491719792
Directory /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest

Test location /workspace/coverage/default/2.chip_sw_edn_kat.668429677
Short name T73
Test name
Test status
Simulation time 2933006806 ps
CPU time 580.79 seconds
Started Aug 04 07:42:06 PM PDT 24
Finished Aug 04 07:51:47 PM PDT 24
Peak memory 616580 kb
Host smart-4a1efca6-034c-4a7d-9d70-f50af76d1c88
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3
+accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668429677 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_edn_kat.668429677
Directory /workspace/2.chip_sw_edn_kat/latest

Test location /workspace/coverage/default/2.chip_sw_edn_sw_mode.149742357
Short name T408
Test name
Test status
Simulation time 8501785428 ps
CPU time 1779.97 seconds
Started Aug 04 07:42:06 PM PDT 24
Finished Aug 04 08:11:47 PM PDT 24
Peak memory 609980 kb
Host smart-547786a2-a177-4f67-8a8a-87e4328cc9d0
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149742357 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.149742357
Directory /workspace/2.chip_sw_edn_sw_mode/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3619432302
Short name T717
Test name
Test status
Simulation time 2880330642 ps
CPU time 190.44 seconds
Started Aug 04 07:41:30 PM PDT 24
Finished Aug 04 07:44:40 PM PDT 24
Peak memory 609724 kb
Host smart-c52bc01c-8dcd-435e-ac9a-e13083593202
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36
19432302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.3619432302
Directory /workspace/2.chip_sw_entropy_src_ast_rng_req/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_csrng.1565112823
Short name T72
Test name
Test status
Simulation time 6668202644 ps
CPU time 1681.69 seconds
Started Aug 04 07:43:15 PM PDT 24
Finished Aug 04 08:11:17 PM PDT 24
Peak memory 610372 kb
Host smart-be420447-e438-407d-ba9a-d173e46238ac
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_
csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1565112823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.1565112823
Directory /workspace/2.chip_sw_entropy_src_csrng/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1233679559
Short name T716
Test name
Test status
Simulation time 2662098950 ps
CPU time 199.25 seconds
Started Aug 04 07:41:31 PM PDT 24
Finished Aug 04 07:44:51 PM PDT 24
Peak memory 609856 kb
Host smart-c0213888-0653-4f27-80dd-959347175f10
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233679559
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.1233679559
Directory /workspace/2.chip_sw_entropy_src_kat_test/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3426700130
Short name T527
Test name
Test status
Simulation time 3700793704 ps
CPU time 332.39 seconds
Started Aug 04 07:47:24 PM PDT 24
Finished Aug 04 07:52:56 PM PDT 24
Peak memory 608800 kb
Host smart-dbde754f-78b2-4888-8f7d-28c9386d713f
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3426700130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.3426700130
Directory /workspace/2.chip_sw_entropy_src_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_example_concurrency.89477011
Short name T1020
Test name
Test status
Simulation time 2844253636 ps
CPU time 284.69 seconds
Started Aug 04 07:35:08 PM PDT 24
Finished Aug 04 07:39:53 PM PDT 24
Peak memory 608452 kb
Host smart-7aff2b55-d17b-4b44-94a8-a52f19299b8b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89477011 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_example_concurrency.89477011
Directory /workspace/2.chip_sw_example_concurrency/latest

Test location /workspace/coverage/default/2.chip_sw_example_flash.3148454070
Short name T765
Test name
Test status
Simulation time 3192734150 ps
CPU time 278.22 seconds
Started Aug 04 07:35:54 PM PDT 24
Finished Aug 04 07:40:32 PM PDT 24
Peak memory 608456 kb
Host smart-56caeea3-a61f-4c33-905f-2b46d156d80d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148454070 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_example_flash.3148454070
Directory /workspace/2.chip_sw_example_flash/latest

Test location /workspace/coverage/default/2.chip_sw_example_manufacturer.2394244762
Short name T533
Test name
Test status
Simulation time 3547947400 ps
CPU time 224.45 seconds
Started Aug 04 07:36:09 PM PDT 24
Finished Aug 04 07:39:54 PM PDT 24
Peak memory 609716 kb
Host smart-aed3f5f4-eed4-4b15-acc9-26c4c87a9205
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394244762 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_example_manufacturer.2394244762
Directory /workspace/2.chip_sw_example_manufacturer/latest

Test location /workspace/coverage/default/2.chip_sw_example_rom.3354952366
Short name T665
Test name
Test status
Simulation time 2394789304 ps
CPU time 143.36 seconds
Started Aug 04 07:36:11 PM PDT 24
Finished Aug 04 07:38:34 PM PDT 24
Peak memory 609116 kb
Host smart-80e5d138-e1de-4926-9818-c0bff22ae686
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354952366 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_example_rom.3354952366
Directory /workspace/2.chip_sw_example_rom/latest

Test location /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3319743565
Short name T197
Test name
Test status
Simulation time 58103307004 ps
CPU time 10013.6 seconds
Started Aug 04 07:36:02 PM PDT 24
Finished Aug 04 10:22:56 PM PDT 24
Peak memory 624796 kb
Host smart-44c177c3-90eb-4dfb-9c16-921bb64f3764
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=3319743565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.3319743565
Directory /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest

Test location /workspace/coverage/default/2.chip_sw_flash_crash_alert.3495663060
Short name T836
Test name
Test status
Simulation time 5566791660 ps
CPU time 651.05 seconds
Started Aug 04 07:47:04 PM PDT 24
Finished Aug 04 07:57:55 PM PDT 24
Peak memory 611228 kb
Host smart-32c4bf5d-4174-40ae-9519-c7be8c669f71
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:
new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=3495663060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.3495663060
Directory /workspace/2.chip_sw_flash_crash_alert/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_access.33632586
Short name T649
Test name
Test status
Simulation time 5685987500 ps
CPU time 1091.49 seconds
Started Aug 04 07:37:57 PM PDT 24
Finished Aug 04 07:56:09 PM PDT 24
Peak memory 610136 kb
Host smart-3bf150fe-c7e3-462a-80bc-c2bf8b70e9bc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33632586 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_flash_ctrl_access.33632586
Directory /workspace/2.chip_sw_flash_ctrl_access/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.4252463826
Short name T540
Test name
Test status
Simulation time 6415469217 ps
CPU time 991.46 seconds
Started Aug 04 07:36:33 PM PDT 24
Finished Aug 04 07:53:05 PM PDT 24
Peak memory 610108 kb
Host smart-919e6b7c-b50e-4b6d-b50e-447b118ed2a4
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252463826 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.4252463826
Directory /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2154161163
Short name T568
Test name
Test status
Simulation time 7470687746 ps
CPU time 1074.11 seconds
Started Aug 04 07:45:30 PM PDT 24
Finished Aug 04 08:03:24 PM PDT 24
Peak memory 610248 kb
Host smart-bdf9ff05-4593-4943-8a53-29777ac653a8
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154161163 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2154161163
Directory /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.870398285
Short name T530
Test name
Test status
Simulation time 5796875363 ps
CPU time 1311.1 seconds
Started Aug 04 07:38:37 PM PDT 24
Finished Aug 04 08:00:28 PM PDT 24
Peak memory 610020 kb
Host smart-f97d6580-6e0e-48ea-9a23-bd91521de4a5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870398285 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.870398285
Directory /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.692874760
Short name T905
Test name
Test status
Simulation time 2923086308 ps
CPU time 460.52 seconds
Started Aug 04 07:37:53 PM PDT 24
Finished Aug 04 07:45:35 PM PDT 24
Peak memory 609908 kb
Host smart-e37ddb08-611f-4f96-b062-2f8e451ad72f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692874760 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.692874760
Directory /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2469422909
Short name T785
Test name
Test status
Simulation time 4329965180 ps
CPU time 537.65 seconds
Started Aug 04 07:37:48 PM PDT 24
Finished Aug 04 07:46:46 PM PDT 24
Peak memory 610584 kb
Host smart-64b95299-e194-4367-946f-2accff3f3ecd
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24
69422909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.2469422909
Directory /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1653370538
Short name T854
Test name
Test status
Simulation time 5531059804 ps
CPU time 1108.1 seconds
Started Aug 04 07:48:00 PM PDT 24
Finished Aug 04 08:06:28 PM PDT 24
Peak memory 610040 kb
Host smart-fc9c9e8f-5dd4-4d0b-9743-79fd66a6a246
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653370538 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.1653370538
Directory /workspace/2.chip_sw_flash_ctrl_mem_protection/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1463077717
Short name T395
Test name
Test status
Simulation time 3557359780 ps
CPU time 659.53 seconds
Started Aug 04 07:37:02 PM PDT 24
Finished Aug 04 07:48:02 PM PDT 24
Peak memory 609892 kb
Host smart-7af3869a-bbf6-4e64-a31d-6eb82090ce8a
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463077717
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.1463077717
Directory /workspace/2.chip_sw_flash_ctrl_ops/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.646519969
Short name T381
Test name
Test status
Simulation time 4594399247 ps
CPU time 624.65 seconds
Started Aug 04 07:38:24 PM PDT 24
Finished Aug 04 07:48:49 PM PDT 24
Peak memory 610152 kb
Host smart-b91af51c-dc5e-4333-a5b8-8b442ab149fb
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=646519969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.646519969
Directory /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3808672011
Short name T394
Test name
Test status
Simulation time 4773374586 ps
CPU time 702.58 seconds
Started Aug 04 07:46:20 PM PDT 24
Finished Aug 04 07:58:02 PM PDT 24
Peak memory 608928 kb
Host smart-e8f8d583-a445-48af-b428-70eafc22fd94
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_
rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3808672011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3808672011
Directory /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.783638399
Short name T525
Test name
Test status
Simulation time 2726639800 ps
CPU time 339.19 seconds
Started Aug 04 07:45:44 PM PDT 24
Finished Aug 04 07:51:24 PM PDT 24
Peak memory 608516 kb
Host smart-d3c9302f-9a19-46cd-8fe5-cfe783049978
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7836383
99 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.783638399
Directory /workspace/2.chip_sw_flash_ctrl_write_clear/latest

Test location /workspace/coverage/default/2.chip_sw_flash_init.1293135305
Short name T878
Test name
Test status
Simulation time 18397051028 ps
CPU time 1866.56 seconds
Started Aug 04 07:36:25 PM PDT 24
Finished Aug 04 08:07:33 PM PDT 24
Peak memory 612768 kb
Host smart-9b012e1b-365a-471b-aeea-152332e6d7bc
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293135305 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.1293135305
Directory /workspace/2.chip_sw_flash_init/latest

Test location /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.985541274
Short name T251
Test name
Test status
Simulation time 22034927663 ps
CPU time 2198.61 seconds
Started Aug 04 07:46:44 PM PDT 24
Finished Aug 04 08:23:23 PM PDT 24
Peak memory 614516 kb
Host smart-b2f3fb7b-6c85-4405-a5eb-fc3f484b7995
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=985541274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.985541274
Directory /workspace/2.chip_sw_flash_init_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3266038247
Short name T294
Test name
Test status
Simulation time 2735092296 ps
CPU time 261.08 seconds
Started Aug 04 07:50:58 PM PDT 24
Finished Aug 04 07:55:19 PM PDT 24
Peak memory 609768 kb
Host smart-17d9ba6c-8174-4678-a37d-fc020a7f22fc
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket
est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3266038247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.3266038247
Directory /workspace/2.chip_sw_flash_scrambling_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc.3950053480
Short name T774
Test name
Test status
Simulation time 3000827000 ps
CPU time 256.17 seconds
Started Aug 04 07:41:42 PM PDT 24
Finished Aug 04 07:45:59 PM PDT 24
Peak memory 609768 kb
Host smart-e1c0ee87-ee0d-444c-8dbd-7a1751db66c7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950053480 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_hmac_enc.3950053480
Directory /workspace/2.chip_sw_hmac_enc/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc_idle.2695186087
Short name T746
Test name
Test status
Simulation time 2591045440 ps
CPU time 285.71 seconds
Started Aug 04 07:41:24 PM PDT 24
Finished Aug 04 07:46:10 PM PDT 24
Peak memory 609728 kb
Host smart-d43541ae-79fc-4b01-9276-3bdb4b8f4bc4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695186087 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_hmac_enc_idle.2695186087
Directory /workspace/2.chip_sw_hmac_enc_idle/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2135858141
Short name T734
Test name
Test status
Simulation time 2575530874 ps
CPU time 279.01 seconds
Started Aug 04 07:42:29 PM PDT 24
Finished Aug 04 07:47:08 PM PDT 24
Peak memory 609760 kb
Host smart-a3532913-b81e-4b5d-b17d-0c6ba86919c6
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135858141 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.2135858141
Directory /workspace/2.chip_sw_hmac_enc_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3518443403
Short name T396
Test name
Test status
Simulation time 2831912342 ps
CPU time 222.33 seconds
Started Aug 04 07:46:26 PM PDT 24
Finished Aug 04 07:50:08 PM PDT 24
Peak memory 608920 kb
Host smart-36fc1b03-f6e8-40c4-8e07-3d3ea680c4cd
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518443403 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.3518443403
Directory /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_multistream.666885070
Short name T983
Test name
Test status
Simulation time 7643645044 ps
CPU time 1806.19 seconds
Started Aug 04 07:42:08 PM PDT 24
Finished Aug 04 08:12:14 PM PDT 24
Peak memory 610128 kb
Host smart-495e2c35-72e4-4f56-a1e2-2e2564b76db1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666885070 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.chip_sw_hmac_multistream.666885070
Directory /workspace/2.chip_sw_hmac_multistream/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_oneshot.696225761
Short name T950
Test name
Test status
Simulation time 3594953024 ps
CPU time 339.71 seconds
Started Aug 04 07:43:47 PM PDT 24
Finished Aug 04 07:49:27 PM PDT 24
Peak memory 608444 kb
Host smart-bb7f5ca6-2733-4429-ad2c-e8812b83d173
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696225761 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_hmac_oneshot.696225761
Directory /workspace/2.chip_sw_hmac_oneshot/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_smoketest.2875581643
Short name T684
Test name
Test status
Simulation time 3311122512 ps
CPU time 375.97 seconds
Started Aug 04 07:47:40 PM PDT 24
Finished Aug 04 07:53:56 PM PDT 24
Peak memory 609688 kb
Host smart-cfc98892-ac6d-4dd1-b3ec-65db0ddfc829
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875581643 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_hmac_smoketest.2875581643
Directory /workspace/2.chip_sw_hmac_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1474777470
Short name T379
Test name
Test status
Simulation time 4157072852 ps
CPU time 618.79 seconds
Started Aug 04 07:37:45 PM PDT 24
Finished Aug 04 07:48:05 PM PDT 24
Peak memory 609504 kb
Host smart-99af2788-2f4f-4808-843f-c9ced149ac2c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474777470 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.1474777470
Directory /workspace/2.chip_sw_i2c_device_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3571609735
Short name T231
Test name
Test status
Simulation time 5150607032 ps
CPU time 871.71 seconds
Started Aug 04 07:36:27 PM PDT 24
Finished Aug 04 07:51:00 PM PDT 24
Peak memory 610212 kb
Host smart-230e94eb-a9d7-40d0-b5b2-27481316b9e0
User root
Command /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571609735 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.3571609735
Directory /workspace/2.chip_sw_i2c_host_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.308676209
Short name T729
Test name
Test status
Simulation time 5500249652 ps
CPU time 841.64 seconds
Started Aug 04 07:36:38 PM PDT 24
Finished Aug 04 07:50:40 PM PDT 24
Peak memory 609180 kb
Host smart-b585bb99-0e93-4d30-a145-79403e2b69d1
User root
Command /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308676209 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.308676209
Directory /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.333387045
Short name T376
Test name
Test status
Simulation time 4998958640 ps
CPU time 719.05 seconds
Started Aug 04 07:36:19 PM PDT 24
Finished Aug 04 07:48:19 PM PDT 24
Peak memory 610024 kb
Host smart-1a92555a-292b-4e17-8c66-6238d227c1b7
User root
Command /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333387045 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.333387045
Directory /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest

Test location /workspace/coverage/default/2.chip_sw_inject_scramble_seed.455970170
Short name T802
Test name
Test status
Simulation time 63645747845 ps
CPU time 11438.6 seconds
Started Aug 04 07:37:27 PM PDT 24
Finished Aug 04 10:48:08 PM PDT 24
Peak memory 624744 kb
Host smart-15527d43-ac46-4682-a0c6-7018bbb61ff9
User root
Command /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=455970170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.455970170
Directory /workspace/2.chip_sw_inject_scramble_seed/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2972463701
Short name T635
Test name
Test status
Simulation time 8409642968 ps
CPU time 1533.86 seconds
Started Aug 04 07:42:00 PM PDT 24
Finished Aug 04 08:07:34 PM PDT 24
Peak memory 617900 kb
Host smart-dd7d693c-f37b-4b6d-89f7-e4d6d408b691
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972
463701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.2972463701
Directory /workspace/2.chip_sw_keymgr_key_derivation/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2533308001
Short name T843
Test name
Test status
Simulation time 6213074573 ps
CPU time 1037.92 seconds
Started Aug 04 07:42:38 PM PDT 24
Finished Aug 04 07:59:56 PM PDT 24
Peak memory 618212 kb
Host smart-199e3d89-aa54-40f6-a673-b2d8d2507dfb
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2533308001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.2533308001
Directory /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1040785726
Short name T615
Test name
Test status
Simulation time 9031992674 ps
CPU time 1624.43 seconds
Started Aug 04 07:46:44 PM PDT 24
Finished Aug 04 08:13:49 PM PDT 24
Peak memory 617928 kb
Host smart-2a5cba68-56ca-47c9-bed0-5baaaa5f7b7f
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1040785726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en
_reduced_freq.1040785726
Directory /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3378284913
Short name T890
Test name
Test status
Simulation time 13070150260 ps
CPU time 2019.17 seconds
Started Aug 04 07:42:47 PM PDT 24
Finished Aug 04 08:16:27 PM PDT 24
Peak memory 617228 kb
Host smart-85388551-e9ef-4315-86c2-28bfdef5adf8
User root
Command /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3378284913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.3378284913
Directory /workspace/2.chip_sw_keymgr_key_derivation_prod/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1821624042
Short name T597
Test name
Test status
Simulation time 12838202224 ps
CPU time 2586.62 seconds
Started Aug 04 07:42:04 PM PDT 24
Finished Aug 04 08:25:11 PM PDT 24
Peak memory 611116 kb
Host smart-0b510c62-a0c7-4212-9f60-6d387a084c12
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18216
24042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.1821624042
Directory /workspace/2.chip_sw_keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.4145716964
Short name T345
Test name
Test status
Simulation time 15270647336 ps
CPU time 3673.76 seconds
Started Aug 04 07:42:33 PM PDT 24
Finished Aug 04 08:43:48 PM PDT 24
Peak memory 610632 kb
Host smart-2e48a77c-6598-4861-834f-5aea9ffb44d4
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41457
16964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.4145716964
Directory /workspace/2.chip_sw_keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_app_rom.3473695956
Short name T695
Test name
Test status
Simulation time 2383460048 ps
CPU time 256.99 seconds
Started Aug 04 07:43:10 PM PDT 24
Finished Aug 04 07:47:28 PM PDT 24
Peak memory 609676 kb
Host smart-dba755f5-7438-42d3-9b54-e4312cfac811
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473695956 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_kmac_app_rom.3473695956
Directory /workspace/2.chip_sw_kmac_app_rom/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_entropy.2642079617
Short name T618
Test name
Test status
Simulation time 3565726524 ps
CPU time 286.61 seconds
Started Aug 04 07:36:49 PM PDT 24
Finished Aug 04 07:41:36 PM PDT 24
Peak memory 609652 kb
Host smart-623f0aef-1036-4819-8f7e-9a25ac514003
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642079617 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_kmac_entropy.2642079617
Directory /workspace/2.chip_sw_kmac_entropy/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_idle.2054957035
Short name T735
Test name
Test status
Simulation time 2331229656 ps
CPU time 238.33 seconds
Started Aug 04 07:42:35 PM PDT 24
Finished Aug 04 07:46:33 PM PDT 24
Peak memory 609708 kb
Host smart-a857cee9-d76c-4b73-b1da-0cc8135d05b6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054957035 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_kmac_idle.2054957035
Directory /workspace/2.chip_sw_kmac_idle/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.738897805
Short name T596
Test name
Test status
Simulation time 2517802296 ps
CPU time 273.96 seconds
Started Aug 04 07:42:29 PM PDT 24
Finished Aug 04 07:47:03 PM PDT 24
Peak memory 608448 kb
Host smart-562b0d0e-bed3-47d4-84af-d7c14eaa497f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738897805 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_sw_kmac_mode_cshake.738897805
Directory /workspace/2.chip_sw_kmac_mode_cshake/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1844389242
Short name T777
Test name
Test status
Simulation time 2585938220 ps
CPU time 237.75 seconds
Started Aug 04 07:41:48 PM PDT 24
Finished Aug 04 07:45:46 PM PDT 24
Peak memory 609688 kb
Host smart-8444a4c4-a24e-47e1-ad25-5935dbe93fd2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844389242 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_kmac_mode_kmac.1844389242
Directory /workspace/2.chip_sw_kmac_mode_kmac/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.584720898
Short name T928
Test name
Test status
Simulation time 2788600858 ps
CPU time 315.32 seconds
Started Aug 04 07:42:57 PM PDT 24
Finished Aug 04 07:48:12 PM PDT 24
Peak memory 609624 kb
Host smart-d72d65c3-5976-4553-b9be-91514217d831
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584720898 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.584720898
Directory /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2268900383
Short name T805
Test name
Test status
Simulation time 3145665221 ps
CPU time 363.55 seconds
Started Aug 04 07:46:59 PM PDT 24
Finished Aug 04 07:53:03 PM PDT 24
Peak memory 609808 kb
Host smart-f5ee0573-00b9-4885-8c46-57dd1723761f
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22689003
83 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2268900383
Directory /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_smoketest.2615245125
Short name T570
Test name
Test status
Simulation time 3550679486 ps
CPU time 436.6 seconds
Started Aug 04 07:48:51 PM PDT 24
Finished Aug 04 07:56:07 PM PDT 24
Peak memory 609872 kb
Host smart-4cd17008-4819-4f9c-beda-7f3e381839a4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615245125 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_kmac_smoketest.2615245125
Directory /workspace/2.chip_sw_kmac_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2362546349
Short name T759
Test name
Test status
Simulation time 2261379554 ps
CPU time 276.86 seconds
Started Aug 04 07:38:15 PM PDT 24
Finished Aug 04 07:42:52 PM PDT 24
Peak memory 609224 kb
Host smart-d5edf686-e4f0-4533-85ba-975908950225
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362546349 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.2362546349
Directory /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.851267011
Short name T210
Test name
Test status
Simulation time 3593842500 ps
CPU time 506.06 seconds
Started Aug 04 07:46:22 PM PDT 24
Finished Aug 04 07:54:48 PM PDT 24
Peak memory 610972 kb
Host smart-53fafbb9-736c-42a9-b268-2944b07461bc
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=851267011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.851267011
Directory /workspace/2.chip_sw_lc_ctrl_program_error/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1563153525
Short name T218
Test name
Test status
Simulation time 3178830095 ps
CPU time 119.51 seconds
Started Aug 04 07:42:07 PM PDT 24
Finished Aug 04 07:44:06 PM PDT 24
Peak memory 620060 kb
Host smart-809239b1-1ad2-47c3-b527-cbd15e9e6c18
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15631535
25 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.1563153525
Directory /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2056126724
Short name T645
Test name
Test status
Simulation time 4882907466 ps
CPU time 511.89 seconds
Started Aug 04 07:36:54 PM PDT 24
Finished Aug 04 07:45:26 PM PDT 24
Peak memory 624720 kb
Host smart-caa463f6-ef67-4bda-814b-21b719be46f6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056126724 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.2056126724
Directory /workspace/2.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1080868653
Short name T996
Test name
Test status
Simulation time 2676541450 ps
CPU time 122.32 seconds
Started Aug 04 07:38:40 PM PDT 24
Finished Aug 04 07:40:43 PM PDT 24
Peak memory 618004 kb
Host smart-38160f4c-8121-4f1a-888e-ab9f89c4657e
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes
t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1080868653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.1080868653
Directory /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2920354278
Short name T949
Test name
Test status
Simulation time 2836454581 ps
CPU time 121.92 seconds
Started Aug 04 07:39:12 PM PDT 24
Finished Aug 04 07:41:14 PM PDT 24
Peak memory 617032 kb
Host smart-5b756752-8d05-464f-a68f-bf0039189491
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s
im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920354278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2920354278
Directory /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1940311587
Short name T852
Test name
Test status
Simulation time 46555980642 ps
CPU time 5524.93 seconds
Started Aug 04 07:37:41 PM PDT 24
Finished Aug 04 09:09:48 PM PDT 24
Peak memory 620572 kb
Host smart-625e9b5a-6af5-4343-af74-32c99c66bd7f
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940311587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip
_sw_lc_walkthrough_dev.1940311587
Directory /workspace/2.chip_sw_lc_walkthrough_dev/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3544018942
Short name T248
Test name
Test status
Simulation time 47651919928 ps
CPU time 5151.19 seconds
Started Aug 04 07:38:09 PM PDT 24
Finished Aug 04 09:04:01 PM PDT 24
Peak memory 620328 kb
Host smart-1961feab-cb6d-4fbf-b145-afe6ee4ca19e
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d
evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544018942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi
p_sw_lc_walkthrough_prod.3544018942
Directory /workspace/2.chip_sw_lc_walkthrough_prod/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.921249163
Short name T674
Test name
Test status
Simulation time 7943090696 ps
CPU time 1107.11 seconds
Started Aug 04 07:38:45 PM PDT 24
Finished Aug 04 07:57:13 PM PDT 24
Peak memory 619060 kb
Host smart-c33932f0-c627-4570-a3b2-019dad6308bb
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa
lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=921249163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.921249163
Directory /workspace/2.chip_sw_lc_walkthrough_prodend/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.735659535
Short name T203
Test name
Test status
Simulation time 46603770550 ps
CPU time 4851.82 seconds
Started Aug 04 07:37:53 PM PDT 24
Finished Aug 04 08:58:45 PM PDT 24
Peak memory 620660 kb
Host smart-8ee40a51-7e38-4a12-b4ec-8e475d93316f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735659535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch
ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_
sw_lc_walkthrough_rma.735659535
Directory /workspace/2.chip_sw_lc_walkthrough_rma/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1106187793
Short name T731
Test name
Test status
Simulation time 30442678568 ps
CPU time 2158.38 seconds
Started Aug 04 07:38:56 PM PDT 24
Finished Aug 04 08:14:55 PM PDT 24
Peak memory 621432 kb
Host smart-127afdbe-4a76-4598-9d96-9310d4464de6
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks
_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1106187793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun
locks.1106187793
Directory /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.4257214675
Short name T195
Test name
Test status
Simulation time 17605510700 ps
CPU time 3495.45 seconds
Started Aug 04 07:40:26 PM PDT 24
Finished Aug 04 08:38:43 PM PDT 24
Peak memory 610276 kb
Host smart-b64e05bc-cefc-4c82-b9d8-32dfb25417f4
User root
Command /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_
rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4257214675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.4257214675
Directory /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2473045362
Short name T859
Test name
Test status
Simulation time 18619709417 ps
CPU time 2866.13 seconds
Started Aug 04 07:40:21 PM PDT 24
Finished Aug 04 08:28:07 PM PDT 24
Peak memory 609280 kb
Host smart-3dc0ab51-0e5e-4f1b-94c4-200ed6d9124f
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne
w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2473045362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2473045362
Directory /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4125137202
Short name T63
Test name
Test status
Simulation time 24739930168 ps
CPU time 3479.53 seconds
Started Aug 04 07:46:03 PM PDT 24
Finished Aug 04 08:44:03 PM PDT 24
Peak memory 610372 kb
Host smart-98a9de6e-f6b6-4d1c-b9b1-90ec5acb5f0b
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e
cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125137202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu
ced_freq.4125137202
Directory /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.967208024
Short name T299
Test name
Test status
Simulation time 3616293380 ps
CPU time 484.02 seconds
Started Aug 04 07:40:36 PM PDT 24
Finished Aug 04 07:48:41 PM PDT 24
Peak memory 609780 kb
Host smart-5ce22a47-adb5-4aab-aa94-9f5bf64eb9a8
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn
_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967208024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.967208024
Directory /workspace/2.chip_sw_otbn_mem_scramble/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_randomness.1062945557
Short name T907
Test name
Test status
Simulation time 5534406516 ps
CPU time 978.59 seconds
Started Aug 04 07:40:20 PM PDT 24
Finished Aug 04 07:56:39 PM PDT 24
Peak memory 609072 kb
Host smart-ba7365b4-cc7e-49c4-83ef-e54246d03880
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1062945557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.1062945557
Directory /workspace/2.chip_sw_otbn_randomness/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_smoketest.2703975946
Short name T897
Test name
Test status
Simulation time 9389890548 ps
CPU time 1753.94 seconds
Started Aug 04 07:49:26 PM PDT 24
Finished Aug 04 08:18:41 PM PDT 24
Peak memory 608928 kb
Host smart-895b65b3-1a88-4237-9878-99c0131ce821
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703975946 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_otbn_smoketest.2703975946
Directory /workspace/2.chip_sw_otbn_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2692041925
Short name T827
Test name
Test status
Simulation time 2814571271 ps
CPU time 290.57 seconds
Started Aug 04 07:38:03 PM PDT 24
Finished Aug 04 07:42:54 PM PDT 24
Peak memory 609780 kb
Host smart-5d95bd2b-73ce-4741-87bf-26f012218435
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692041925 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.2692041925
Directory /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.4166432405
Short name T906
Test name
Test status
Simulation time 7547428700 ps
CPU time 1333.84 seconds
Started Aug 04 07:37:11 PM PDT 24
Finished Aug 04 07:59:26 PM PDT 24
Peak memory 610636 kb
Host smart-e2b29031-0bb8-4c16-b7ef-2320c954dd51
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=4166432405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.4166432405
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1093798926
Short name T176
Test name
Test status
Simulation time 6968141536 ps
CPU time 1204.53 seconds
Started Aug 04 07:38:21 PM PDT 24
Finished Aug 04 07:58:25 PM PDT 24
Peak memory 610736 kb
Host smart-35e82cfa-e183-4e05-9b13-834005fc1555
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1093798926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.1093798926
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1528598307
Short name T786
Test name
Test status
Simulation time 6199293000 ps
CPU time 1253.54 seconds
Started Aug 04 07:38:20 PM PDT 24
Finished Aug 04 07:59:14 PM PDT 24
Peak memory 610724 kb
Host smart-faae6cfd-3265-497a-9ef5-b86d7a73242f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1528598307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.1528598307
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4044583170
Short name T692
Test name
Test status
Simulation time 3612429776 ps
CPU time 847.67 seconds
Started Aug 04 07:39:17 PM PDT 24
Finished Aug 04 07:53:25 PM PDT 24
Peak memory 608812 kb
Host smart-06e28448-b5bc-4988-81ba-4d2b12b5452c
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=4044583170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4044583170
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.199940104
Short name T550
Test name
Test status
Simulation time 3251773510 ps
CPU time 229.69 seconds
Started Aug 04 07:47:45 PM PDT 24
Finished Aug 04 07:51:34 PM PDT 24
Peak memory 609592 kb
Host smart-8926016f-917b-4808-a5d7-936889d6d84c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199940104 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_otp_ctrl_smoketest.199940104
Directory /workspace/2.chip_sw_otp_ctrl_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_pattgen_ios.958395712
Short name T978
Test name
Test status
Simulation time 3207867782 ps
CPU time 284.03 seconds
Started Aug 04 07:35:59 PM PDT 24
Finished Aug 04 07:40:44 PM PDT 24
Peak memory 610340 kb
Host smart-4bd8e948-864c-4a7b-9dfd-7c96ffc8e3d6
User root
Command /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958395712 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.958395712
Directory /workspace/2.chip_sw_pattgen_ios/latest

Test location /workspace/coverage/default/2.chip_sw_plic_sw_irq.4147909295
Short name T269
Test name
Test status
Simulation time 3235002348 ps
CPU time 271.47 seconds
Started Aug 04 07:43:10 PM PDT 24
Finished Aug 04 07:47:41 PM PDT 24
Peak memory 608436 kb
Host smart-0ecf0fb8-2642-4dba-93c4-1a78af666ac0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147909295 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.chip_sw_plic_sw_irq.4147909295
Directory /workspace/2.chip_sw_plic_sw_irq/latest

Test location /workspace/coverage/default/2.chip_sw_power_idle_load.2304230971
Short name T94
Test name
Test status
Simulation time 4258929080 ps
CPU time 609.65 seconds
Started Aug 04 07:46:07 PM PDT 24
Finished Aug 04 07:56:17 PM PDT 24
Peak memory 609356 kb
Host smart-7e5e416f-54cf-4d75-9c40-53072511f555
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304230971 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.2304230971
Directory /workspace/2.chip_sw_power_idle_load/latest

Test location /workspace/coverage/default/2.chip_sw_power_sleep_load.1828578333
Short name T325
Test name
Test status
Simulation time 10784093070 ps
CPU time 559.32 seconds
Started Aug 04 07:45:44 PM PDT 24
Finished Aug 04 07:55:04 PM PDT 24
Peak memory 610716 kb
Host smart-3e5a180d-7057-45df-bc7f-d712f3dc0444
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828578333 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.1828578333
Directory /workspace/2.chip_sw_power_sleep_load/latest

Test location /workspace/coverage/default/2.chip_sw_power_virus.2500475594
Short name T12
Test name
Test status
Simulation time 5708379480 ps
CPU time 1431.03 seconds
Started Aug 04 07:52:02 PM PDT 24
Finished Aug 04 08:15:53 PM PDT 24
Peak memory 624968 kb
Host smart-7d77614c-d872-49cc-b947-113eeafc813b
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_
power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes
t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2500475594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.2500475594
Directory /workspace/2.chip_sw_power_virus/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1246675928
Short name T368
Test name
Test status
Simulation time 10070153569 ps
CPU time 1602.37 seconds
Started Aug 04 07:39:53 PM PDT 24
Finished Aug 04 08:06:36 PM PDT 24
Peak memory 611508 kb
Host smart-a968123a-cd8c-48d8-af35-eb7897d20e42
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246
675928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.1246675928
Directory /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1464137233
Short name T699
Test name
Test status
Simulation time 20630196878 ps
CPU time 1932.12 seconds
Started Aug 04 07:43:49 PM PDT 24
Finished Aug 04 08:16:02 PM PDT 24
Peak memory 610996 kb
Host smart-f09e72ea-9e05-483a-8357-31c05592bd74
User root
Command /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146
4137233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.1464137233
Directory /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2566156460
Short name T705
Test name
Test status
Simulation time 15699437149 ps
CPU time 1358.73 seconds
Started Aug 04 07:39:03 PM PDT 24
Finished Aug 04 08:01:41 PM PDT 24
Peak memory 611540 kb
Host smart-4bc0b248-c2c7-4b61-b249-7b4cc71bc5c1
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2566156460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2566156460
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.904899742
Short name T876
Test name
Test status
Simulation time 10172792340 ps
CPU time 716.89 seconds
Started Aug 04 07:38:36 PM PDT 24
Finished Aug 04 07:50:33 PM PDT 24
Peak memory 610608 kb
Host smart-517525a0-333a-434a-a14b-8e08ae1d11a4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904899742 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.904899742
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1365090742
Short name T787
Test name
Test status
Simulation time 8410032200 ps
CPU time 611.04 seconds
Started Aug 04 07:39:24 PM PDT 24
Finished Aug 04 07:49:35 PM PDT 24
Peak memory 616732 kb
Host smart-1b264df0-954f-486a-ae4b-76abe1aabd5f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1365090742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1365090742
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.745815295
Short name T1009
Test name
Test status
Simulation time 7620882455 ps
CPU time 779.31 seconds
Started Aug 04 07:38:48 PM PDT 24
Finished Aug 04 07:51:47 PM PDT 24
Peak memory 610820 kb
Host smart-75ae5aee-10eb-40ba-a826-d301c5d072ce
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745815295 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.745815295
Directory /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1684578694
Short name T61
Test name
Test status
Simulation time 4877151707 ps
CPU time 434.34 seconds
Started Aug 04 07:38:40 PM PDT 24
Finished Aug 04 07:45:54 PM PDT 24
Peak memory 616608 kb
Host smart-7d3dea74-2818-4969-8264-76706ab4edcf
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1684578694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.1684578694
Directory /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2098410339
Short name T393
Test name
Test status
Simulation time 9651698196 ps
CPU time 1096.88 seconds
Started Aug 04 07:39:56 PM PDT 24
Finished Aug 04 07:58:14 PM PDT 24
Peak memory 611236 kb
Host smart-ac5d0340-ab6a-4411-b882-45dba8e3954d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098410339 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2098410339
Directory /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3131628151
Short name T18
Test name
Test status
Simulation time 7761272568 ps
CPU time 364.41 seconds
Started Aug 04 07:46:38 PM PDT 24
Finished Aug 04 07:52:42 PM PDT 24
Peak memory 610560 kb
Host smart-3c51e468-81c0-42e9-b14e-1ecd43285b92
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131628151 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3131628151
Directory /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3896953971
Short name T326
Test name
Test status
Simulation time 7797030978 ps
CPU time 739.08 seconds
Started Aug 04 07:38:47 PM PDT 24
Finished Aug 04 07:51:07 PM PDT 24
Peak memory 610828 kb
Host smart-dc16b553-a696-45cf-9618-1469fa7a47dc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896953971 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.3896953971
Directory /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.80718740
Short name T721
Test name
Test status
Simulation time 26538900852 ps
CPU time 2559.05 seconds
Started Aug 04 07:39:26 PM PDT 24
Finished Aug 04 08:22:05 PM PDT 24
Peak memory 611300 kb
Host smart-fd1376f6-e0e9-425a-b849-307b1d8cf171
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=80718740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.80718740
Directory /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.869464945
Short name T146
Test name
Test status
Simulation time 24826385332 ps
CPU time 1607.83 seconds
Started Aug 04 07:46:18 PM PDT 24
Finished Aug 04 08:13:07 PM PDT 24
Peak memory 611096 kb
Host smart-d05e88a5-e959-4f6a-b428-441a3f50d1bc
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=869464945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.869464945
Directory /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3340600313
Short name T327
Test name
Test status
Simulation time 35182590472 ps
CPU time 2744.47 seconds
Started Aug 04 07:39:02 PM PDT 24
Finished Aug 04 08:24:47 PM PDT 24
Peak memory 612016 kb
Host smart-5fba8d2b-9207-4092-9360-eafe3b6fa7c8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power
_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340600313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit
ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s
leep_power_glitch_reset.3340600313
Directory /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.889460817
Short name T84
Test name
Test status
Simulation time 5662495766 ps
CPU time 461.38 seconds
Started Aug 04 07:44:37 PM PDT 24
Finished Aug 04 07:52:19 PM PDT 24
Peak memory 610736 kb
Host smart-4ca758c5-c9a2-4b23-8491-ea8929a7e1b1
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul
es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=889460817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_sl
eep_wake_up.889460817
Directory /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2653703485
Short name T959
Test name
Test status
Simulation time 3205765724 ps
CPU time 267.23 seconds
Started Aug 04 07:40:08 PM PDT 24
Finished Aug 04 07:44:35 PM PDT 24
Peak memory 609552 kb
Host smart-54aed525-9665-479e-a751-47610456279d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653703485 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.2653703485
Directory /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3139643667
Short name T688
Test name
Test status
Simulation time 6772495493 ps
CPU time 609.7 seconds
Started Aug 04 07:40:10 PM PDT 24
Finished Aug 04 07:50:20 PM PDT 24
Peak memory 616736 kb
Host smart-ed85fc46-a3e7-4829-a47f-74c440e170fb
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=3139643667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.3139643667
Directory /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4001456840
Short name T80
Test name
Test status
Simulation time 4864830624 ps
CPU time 362.27 seconds
Started Aug 04 07:42:58 PM PDT 24
Finished Aug 04 07:49:01 PM PDT 24
Peak memory 608716 kb
Host smart-2f661294-7305-467f-9301-0b74e8d19b7b
User root
Command /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40014568
40 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4001456840
Directory /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1819418647
Short name T666
Test name
Test status
Simulation time 6553514774 ps
CPU time 626.82 seconds
Started Aug 04 07:44:59 PM PDT 24
Finished Aug 04 07:55:27 PM PDT 24
Peak memory 610776 kb
Host smart-56aaabec-5469-4430-a61d-f98b70f0f280
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1819418647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.1819418647
Directory /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.237379368
Short name T696
Test name
Test status
Simulation time 5330956012 ps
CPU time 292.1 seconds
Started Aug 04 07:47:24 PM PDT 24
Finished Aug 04 07:52:16 PM PDT 24
Peak memory 610432 kb
Host smart-85069486-199c-425d-b06f-11b7e63dddcb
User root
Command /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237379368 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.237379368
Directory /workspace/2.chip_sw_pwrmgr_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.10584707
Short name T608
Test name
Test status
Simulation time 5247997042 ps
CPU time 510.63 seconds
Started Aug 04 07:38:24 PM PDT 24
Finished Aug 04 07:46:55 PM PDT 24
Peak memory 610160 kb
Host smart-6530d431-98ea-47b0-a695-fa514cd7c22e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10584707 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.10584707
Directory /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.4039886762
Short name T775
Test name
Test status
Simulation time 5016544994 ps
CPU time 502.63 seconds
Started Aug 04 07:47:50 PM PDT 24
Finished Aug 04 07:56:13 PM PDT 24
Peak memory 610444 kb
Host smart-38b4651b-3116-4eef-8580-ea0401235cc3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039886762 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.4039886762
Directory /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.230931291
Short name T555
Test name
Test status
Simulation time 4594345728 ps
CPU time 547.44 seconds
Started Aug 04 07:39:34 PM PDT 24
Finished Aug 04 07:48:41 PM PDT 24
Peak memory 610472 kb
Host smart-f295d582-e958-4cc1-9dfd-143c5504701d
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230
931291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.230931291
Directory /workspace/2.chip_sw_pwrmgr_wdog_reset/latest

Test location /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1340907104
Short name T153
Test name
Test status
Simulation time 8307595822 ps
CPU time 707.4 seconds
Started Aug 04 07:42:33 PM PDT 24
Finished Aug 04 07:54:20 PM PDT 24
Peak memory 624724 kb
Host smart-e6ff3da9-acdd-4f82-b702-8306fac573ca
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340907104 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.1340907104
Directory /workspace/2.chip_sw_rom_ctrl_integrity_check/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1417839310
Short name T277
Test name
Test status
Simulation time 5585481216 ps
CPU time 502.2 seconds
Started Aug 04 07:38:43 PM PDT 24
Finished Aug 04 07:47:05 PM PDT 24
Peak memory 610556 kb
Host smart-21f12114-98a3-460a-9f01-50e4c1cb6797
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417839310 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.1417839310
Directory /workspace/2.chip_sw_rstmgr_cpu_info/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.4070628821
Short name T850
Test name
Test status
Simulation time 6382749784 ps
CPU time 875.46 seconds
Started Aug 04 07:35:56 PM PDT 24
Finished Aug 04 07:50:31 PM PDT 24
Peak memory 641656 kb
Host smart-4bec2c52-75b9-4638-8077-e916a1d0ca9c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4070628821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.4070628821
Directory /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.397547606
Short name T524
Test name
Test status
Simulation time 2924495220 ps
CPU time 180.74 seconds
Started Aug 04 07:49:05 PM PDT 24
Finished Aug 04 07:52:06 PM PDT 24
Peak memory 609640 kb
Host smart-25d99055-01a5-4b72-8ee4-eca2cc1b25e5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397547606 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.chip_sw_rstmgr_smoketest.397547606
Directory /workspace/2.chip_sw_rstmgr_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.4214936934
Short name T545
Test name
Test status
Simulation time 4520005420 ps
CPU time 350.91 seconds
Started Aug 04 07:38:03 PM PDT 24
Finished Aug 04 07:43:54 PM PDT 24
Peak memory 609092 kb
Host smart-03daf450-785b-4677-a10b-f5dbb435d79b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214936934 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_rstmgr_sw_req.4214936934
Directory /workspace/2.chip_sw_rstmgr_sw_req/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2596229988
Short name T229
Test name
Test status
Simulation time 2490376950 ps
CPU time 192.13 seconds
Started Aug 04 07:39:52 PM PDT 24
Finished Aug 04 07:43:05 PM PDT 24
Peak memory 608404 kb
Host smart-c4c499e7-6f0f-409d-80fe-92dd6058fd2d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596229988 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.2596229988
Directory /workspace/2.chip_sw_rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1449872155
Short name T223
Test name
Test status
Simulation time 2479858630 ps
CPU time 297.34 seconds
Started Aug 04 07:45:55 PM PDT 24
Finished Aug 04 07:50:53 PM PDT 24
Peak memory 609688 kb
Host smart-9272dfb5-ca18-42ed-9040-ffd2206c1de1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449872155 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.1449872155
Directory /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3073187806
Short name T427
Test name
Test status
Simulation time 4866974678 ps
CPU time 1065.79 seconds
Started Aug 04 07:40:26 PM PDT 24
Finished Aug 04 07:58:12 PM PDT 24
Peak memory 610228 kb
Host smart-1fd98c86-dbc3-465c-a7b6-a7a45ce1ea18
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30731
87806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.3073187806
Directory /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2232284293
Short name T275
Test name
Test status
Simulation time 6076166500 ps
CPU time 1038.28 seconds
Started Aug 04 07:39:56 PM PDT 24
Finished Aug 04 07:57:15 PM PDT 24
Peak memory 609016 kb
Host smart-fbd7a5fd-a43d-495a-a603-7936bbdb82e2
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2232284293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.2232284293
Directory /workspace/2.chip_sw_rv_core_ibex_rnd/latest

Test location /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2814725978
Short name T338
Test name
Test status
Simulation time 4586415346 ps
CPU time 620.58 seconds
Started Aug 04 07:44:58 PM PDT 24
Finished Aug 04 07:55:19 PM PDT 24
Peak memory 624268 kb
Host smart-820eae9d-cfb8-4225-b1d9-4097fa29461e
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814725978 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.2814725978
Directory /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3057659152
Short name T889
Test name
Test status
Simulation time 6680886128 ps
CPU time 520.26 seconds
Started Aug 04 07:45:47 PM PDT 24
Finished Aug 04 07:54:28 PM PDT 24
Peak memory 620520 kb
Host smart-2de85464-bc0d-47d5-80c2-f9c3f3738a11
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057659152 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.3057659152
Directory /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1980641904
Short name T329
Test name
Test status
Simulation time 4798032494 ps
CPU time 477.67 seconds
Started Aug 04 07:45:12 PM PDT 24
Finished Aug 04 07:53:09 PM PDT 24
Peak memory 619332 kb
Host smart-f6b75b30-45c4-4cbd-b6ff-36c961696439
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198064
1904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1980641904
Directory /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.835819472
Short name T553
Test name
Test status
Simulation time 2981858260 ps
CPU time 277.72 seconds
Started Aug 04 07:47:50 PM PDT 24
Finished Aug 04 07:52:28 PM PDT 24
Peak memory 608440 kb
Host smart-bf2e6262-c350-4b18-b6ba-3659ac03fa9d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835819472 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.chip_sw_rv_plic_smoketest.835819472
Directory /workspace/2.chip_sw_rv_plic_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_rv_timer_irq.2510769121
Short name T945
Test name
Test status
Simulation time 2946109170 ps
CPU time 280.58 seconds
Started Aug 04 07:38:31 PM PDT 24
Finished Aug 04 07:43:12 PM PDT 24
Peak memory 609680 kb
Host smart-226a64bc-ea65-430e-8f49-0465db4b5657
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510769121 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_rv_timer_irq.2510769121
Directory /workspace/2.chip_sw_rv_timer_irq/latest

Test location /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3386243982
Short name T751
Test name
Test status
Simulation time 2354475848 ps
CPU time 229.43 seconds
Started Aug 04 07:50:18 PM PDT 24
Finished Aug 04 07:54:07 PM PDT 24
Peak memory 608468 kb
Host smart-a5c8b76b-0f10-41bf-9fcd-0b2b12f8d59b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386243982 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_rv_timer_smoketest.3386243982
Directory /workspace/2.chip_sw_rv_timer_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.321626446
Short name T59
Test name
Test status
Simulation time 2475898477 ps
CPU time 179.88 seconds
Started Aug 04 07:45:02 PM PDT 24
Finished Aug 04 07:48:02 PM PDT 24
Peak memory 610512 kb
Host smart-3bf8d6c8-f9ad-41be-8304-9eb4d4ad5101
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216264
46 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.321626446
Directory /workspace/2.chip_sw_sensor_ctrl_status/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pin_retention.3270288894
Short name T24
Test name
Test status
Simulation time 3675466744 ps
CPU time 360.82 seconds
Started Aug 04 07:36:11 PM PDT 24
Finished Aug 04 07:42:12 PM PDT 24
Peak memory 610184 kb
Host smart-3fea587f-e848-4fdb-ba9d-83e97e444cf3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270288894 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.3270288894
Directory /workspace/2.chip_sw_sleep_pin_retention/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1614803074
Short name T818
Test name
Test status
Simulation time 8531618010 ps
CPU time 1523.31 seconds
Started Aug 04 07:35:53 PM PDT 24
Finished Aug 04 08:01:17 PM PDT 24
Peak memory 610756 kb
Host smart-263038e0-f0a2-46c9-9fec-e02e0995e904
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614803074 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.1614803074
Directory /workspace/2.chip_sw_sleep_pwm_pulses/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1409002980
Short name T764
Test name
Test status
Simulation time 7713876240 ps
CPU time 801.11 seconds
Started Aug 04 07:42:42 PM PDT 24
Finished Aug 04 07:56:04 PM PDT 24
Peak memory 610380 kb
Host smart-6bfca46d-a3bb-41e6-aba3-685b05c868ef
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409002980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl
eep_sram_ret_contents_no_scramble.1409002980
Directory /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1647608701
Short name T1008
Test name
Test status
Simulation time 9194992360 ps
CPU time 895.12 seconds
Started Aug 04 07:43:18 PM PDT 24
Finished Aug 04 07:58:14 PM PDT 24
Peak memory 610352 kb
Host smart-4b56dd39-5881-487b-9a49-e4f72ac7d942
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647608701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep
_sram_ret_contents_scramble.1647608701
Directory /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3554111649
Short name T10
Test name
Test status
Simulation time 7201348452 ps
CPU time 897.99 seconds
Started Aug 04 07:37:49 PM PDT 24
Finished Aug 04 07:52:47 PM PDT 24
Peak memory 624716 kb
Host smart-e42f4bcb-9166-448b-8679-0a1a214152e4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554111649 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.3554111649
Directory /workspace/2.chip_sw_spi_device_pass_through/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.656830071
Short name T100
Test name
Test status
Simulation time 4738414236 ps
CPU time 747.14 seconds
Started Aug 04 07:37:02 PM PDT 24
Finished Aug 04 07:49:29 PM PDT 24
Peak memory 624812 kb
Host smart-83f3d8f2-8dfd-4a4a-9e89-85de0e3fc96e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656830071 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.656830071
Directory /workspace/2.chip_sw_spi_device_pass_through_collision/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.3147597557
Short name T107
Test name
Test status
Simulation time 3467692322 ps
CPU time 310.72 seconds
Started Aug 04 07:37:23 PM PDT 24
Finished Aug 04 07:42:34 PM PDT 24
Peak memory 617904 kb
Host smart-1d406e08-8a64-44d2-bb31-8620ee616fe0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147597557 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.3147597557
Directory /workspace/2.chip_sw_spi_device_pinmux_sleep_retention/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_tpm.260411813
Short name T41
Test name
Test status
Simulation time 4208654819 ps
CPU time 525.12 seconds
Started Aug 04 07:37:09 PM PDT 24
Finished Aug 04 07:45:54 PM PDT 24
Peak memory 619700 kb
Host smart-e070d881-bbf7-4132-b300-d77a513d260f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260411813 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.260411813
Directory /workspace/2.chip_sw_spi_device_tpm/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3605277882
Short name T318
Test name
Test status
Simulation time 7442609828 ps
CPU time 624.82 seconds
Started Aug 04 07:43:22 PM PDT 24
Finished Aug 04 07:53:48 PM PDT 24
Peak memory 610392 kb
Host smart-1e10bdec-1352-4378-8bf4-d5cf90af671c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605277882 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.3605277882
Directory /workspace/2.chip_sw_sram_ctrl_execution_main/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.170944965
Short name T834
Test name
Test status
Simulation time 4390671464 ps
CPU time 529.11 seconds
Started Aug 04 07:42:34 PM PDT 24
Finished Aug 04 07:51:24 PM PDT 24
Peak memory 611264 kb
Host smart-95b1bd9c-df79-47ff-8285-be83c3f2ef76
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170944965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl
_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_
sram_ctrl_scrambled_access.170944965
Directory /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.4243484222
Short name T219
Test name
Test status
Simulation time 3569621065 ps
CPU time 496.91 seconds
Started Aug 04 07:44:29 PM PDT 24
Finished Aug 04 07:52:46 PM PDT 24
Peak memory 609628 kb
Host smart-e447a485-84d9-4366-80b2-5cb2427e5192
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s
w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243484222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.4243484222
Directory /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4286567686
Short name T298
Test name
Test status
Simulation time 4148359307 ps
CPU time 618.88 seconds
Started Aug 04 07:46:51 PM PDT 24
Finished Aug 04 07:57:10 PM PDT 24
Peak memory 610588 kb
Host smart-ab88e45f-7ae3-4073-a867-9712172f127b
User root
Command /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk
_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286567686 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4286567686
Directory /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1391133207
Short name T180
Test name
Test status
Simulation time 2650697028 ps
CPU time 190.31 seconds
Started Aug 04 07:49:45 PM PDT 24
Finished Aug 04 07:52:56 PM PDT 24
Peak memory 609832 kb
Host smart-9714a968-7a24-4705-94a3-fa8ce5c1b873
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391133207 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.1391133207
Directory /workspace/2.chip_sw_sram_ctrl_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2250436222
Short name T845
Test name
Test status
Simulation time 20933931138 ps
CPU time 3239.99 seconds
Started Aug 04 07:42:52 PM PDT 24
Finished Aug 04 08:36:52 PM PDT 24
Peak memory 610824 kb
Host smart-4b07235b-9dcf-4259-a844-a4ba675fe61e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250436222 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.2250436222
Directory /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1361948651
Short name T364
Test name
Test status
Simulation time 4064638722 ps
CPU time 589.33 seconds
Started Aug 04 07:39:23 PM PDT 24
Finished Aug 04 07:49:14 PM PDT 24
Peak memory 613116 kb
Host smart-fbe84a44-ab97-4977-80b9-3112fe8eb61a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361948651 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.1361948651
Directory /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.1192521002
Short name T22
Test name
Test status
Simulation time 3251308456 ps
CPU time 378.76 seconds
Started Aug 04 07:40:38 PM PDT 24
Finished Aug 04 07:46:58 PM PDT 24
Peak memory 610136 kb
Host smart-dbebb314-52b4-4696-b4b7-9ecd7263bce6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192521002 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.1192521002
Directory /workspace/2.chip_sw_sysrst_ctrl_outputs/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1785330817
Short name T245
Test name
Test status
Simulation time 23966276316 ps
CPU time 1465.09 seconds
Started Aug 04 07:40:12 PM PDT 24
Finished Aug 04 08:04:38 PM PDT 24
Peak memory 613852 kb
Host smart-2973ffa7-ca38-4adc-85bb-eea0a4287024
User root
Command /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17853308
17 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.1785330817
Directory /workspace/2.chip_sw_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1584716072
Short name T39
Test name
Test status
Simulation time 6664869056 ps
CPU time 514.07 seconds
Started Aug 04 07:39:23 PM PDT 24
Finished Aug 04 07:47:58 PM PDT 24
Peak memory 610516 kb
Host smart-39216462-01e9-496f-a98f-020956ced43b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584716072 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1584716072
Directory /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.767642611
Short name T316
Test name
Test status
Simulation time 8994203020 ps
CPU time 1479.11 seconds
Started Aug 04 07:36:50 PM PDT 24
Finished Aug 04 08:01:29 PM PDT 24
Peak memory 622400 kb
Host smart-6ab6a923-d9b9-4cb8-bd4d-5163f92835ac
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=767642611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.767642611
Directory /workspace/2.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/2.chip_sw_uart_smoketest.1177346954
Short name T589
Test name
Test status
Simulation time 2945151778 ps
CPU time 351.09 seconds
Started Aug 04 07:48:04 PM PDT 24
Finished Aug 04 07:53:55 PM PDT 24
Peak memory 615084 kb
Host smart-bae3591f-61de-416a-92bd-ea7c4693398e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177346954 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_sw_uart_smoketest.1177346954
Directory /workspace/2.chip_sw_uart_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx.1066666621
Short name T914
Test name
Test status
Simulation time 4562688144 ps
CPU time 638.65 seconds
Started Aug 04 07:35:34 PM PDT 24
Finished Aug 04 07:46:13 PM PDT 24
Peak memory 624248 kb
Host smart-e6dcb1f3-a0f6-45f5-ab26-c6d3ec79be94
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066666621 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.1066666621
Directory /workspace/2.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.4150751360
Short name T955
Test name
Test status
Simulation time 3597301587 ps
CPU time 513.33 seconds
Started Aug 04 07:35:36 PM PDT 24
Finished Aug 04 07:44:10 PM PDT 24
Peak memory 623544 kb
Host smart-11445517-d3ec-438f-9f0b-549df6db4e11
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150751360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx
_alt_clk_freq.4150751360
Directory /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.810863187
Short name T879
Test name
Test status
Simulation time 13436035208 ps
CPU time 1451.48 seconds
Started Aug 04 07:36:52 PM PDT 24
Finished Aug 04 08:01:04 PM PDT 24
Peak memory 622516 kb
Host smart-7e2600f9-bd37-43ff-a0bc-4b4aa30a9e60
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810863187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba
udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_
alt_clk_freq_low_speed.810863187
Directory /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2615864160
Short name T740
Test name
Test status
Simulation time 4106138562 ps
CPU time 612.02 seconds
Started Aug 04 07:36:50 PM PDT 24
Finished Aug 04 07:47:02 PM PDT 24
Peak memory 623816 kb
Host smart-403fe02b-b6a1-40fd-8c46-c2d3c69119c9
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615864160 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.2615864160
Directory /workspace/2.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3357943441
Short name T92
Test name
Test status
Simulation time 4725662424 ps
CPU time 731.6 seconds
Started Aug 04 07:37:41 PM PDT 24
Finished Aug 04 07:49:53 PM PDT 24
Peak memory 624208 kb
Host smart-ad5bcbb1-96e1-49a5-94e3-6184c4a172cb
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357943441 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.3357943441
Directory /workspace/2.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.906731518
Short name T747
Test name
Test status
Simulation time 4045789328 ps
CPU time 656.93 seconds
Started Aug 04 07:36:07 PM PDT 24
Finished Aug 04 07:47:05 PM PDT 24
Peak memory 623916 kb
Host smart-73c301b3-c563-4f46-8e74-e646d686eb20
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906731518 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.906731518
Directory /workspace/2.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/2.chip_tap_straps_dev.2599070698
Short name T574
Test name
Test status
Simulation time 1971459405 ps
CPU time 155.96 seconds
Started Aug 04 07:45:00 PM PDT 24
Finished Aug 04 07:47:36 PM PDT 24
Peak memory 621908 kb
Host smart-2a473798-0000-4aac-a868-21810966e8b5
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2599070698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.2599070698
Directory /workspace/2.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/2.chip_tap_straps_prod.2158670077
Short name T119
Test name
Test status
Simulation time 17467875852 ps
CPU time 2138.6 seconds
Started Aug 04 07:45:45 PM PDT 24
Finished Aug 04 08:21:24 PM PDT 24
Peak memory 624488 kb
Host smart-a64e6fcc-1fb3-4c8e-9fa1-90c8f0b4286f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2158670077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.2158670077
Directory /workspace/2.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/2.chip_tap_straps_rma.2595161419
Short name T117
Test name
Test status
Simulation time 3101473936 ps
CPU time 208.13 seconds
Started Aug 04 07:45:43 PM PDT 24
Finished Aug 04 07:49:12 PM PDT 24
Peak memory 621004 kb
Host smart-3945be4b-2524-4589-9867-c849552b4715
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595161419 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.2595161419
Directory /workspace/2.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/2.chip_tap_straps_testunlock0.72372583
Short name T864
Test name
Test status
Simulation time 3117633152 ps
CPU time 278.77 seconds
Started Aug 04 07:45:06 PM PDT 24
Finished Aug 04 07:49:45 PM PDT 24
Peak memory 621044 kb
Host smart-b14217be-8f9c-4192-8bab-b6d2536dfde2
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72372583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.72372583
Directory /workspace/2.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_dev.2990762391
Short name T561
Test name
Test status
Simulation time 15404044399 ps
CPU time 3576.49 seconds
Started Aug 04 07:50:12 PM PDT 24
Finished Aug 04 08:49:49 PM PDT 24
Peak memory 610304 kb
Host smart-3e11b516-65f4-4a95-addc-0ced87d86864
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990762391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rom_e2e_asm_init_dev.2990762391
Directory /workspace/2.rom_e2e_asm_init_dev/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_prod.1380221843
Short name T542
Test name
Test status
Simulation time 15194754709 ps
CPU time 3182.4 seconds
Started Aug 04 07:52:17 PM PDT 24
Finished Aug 04 08:45:20 PM PDT 24
Peak memory 610232 kb
Host smart-229e5447-be95-4dc0-9673-6f85825fe04c
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380221843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_
SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rom_e2e_asm_init_prod.1380221843
Directory /workspace/2.rom_e2e_asm_init_prod/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2055225943
Short name T402
Test name
Test status
Simulation time 14959293817 ps
CPU time 3701.89 seconds
Started Aug 04 07:51:50 PM PDT 24
Finished Aug 04 08:53:32 PM PDT 24
Peak memory 610276 kb
Host smart-904e0ce3-d6ed-4ab2-a265-a2bace4f7edc
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055225943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_e2e_asm_init_prod_end.2055225943
Directory /workspace/2.rom_e2e_asm_init_prod_end/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_rma.3751975513
Short name T912
Test name
Test status
Simulation time 14333330340 ps
CPU time 3216.44 seconds
Started Aug 04 07:50:27 PM PDT 24
Finished Aug 04 08:44:04 PM PDT 24
Peak memory 610524 kb
Host smart-f3056197-277f-4403-8d7e-953d2a4c0b07
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751975513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rom_e2e_asm_init_rma.3751975513
Directory /workspace/2.rom_e2e_asm_init_rma/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1407863682
Short name T979
Test name
Test status
Simulation time 11620540184 ps
CPU time 2527.2 seconds
Started Aug 04 07:52:32 PM PDT 24
Finished Aug 04 08:34:40 PM PDT 24
Peak memory 610608 kb
Host smart-3928a211-16b5-403a-94f3-82db6860da21
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407863682 -assert nopostproc +UVM_TESTNAME=chip_base_te
st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.rom_e2e_asm_init_test_unlocked0.1407863682
Directory /workspace/2.rom_e2e_asm_init_test_unlocked0/latest

Test location /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1079417277
Short name T50
Test name
Test status
Simulation time 15271559980 ps
CPU time 3953.33 seconds
Started Aug 04 07:53:55 PM PDT 24
Finished Aug 04 08:59:49 PM PDT 24
Peak memory 609912 kb
Host smart-d49408d0-46b8-4525-bc0c-9459101d4355
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid
_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079417277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip
_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in
it_rom_ext_invalid_meas.1079417277
Directory /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2365953329
Short name T962
Test name
Test status
Simulation time 15194562030 ps
CPU time 3713.11 seconds
Started Aug 04 07:51:30 PM PDT 24
Finished Aug 04 08:53:23 PM PDT 24
Peak memory 609964 kb
Host smart-eefbb120-ffd3-4312-b7a6-48ec3c9bb1f9
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas
:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365953329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext
_no_meas.2365953329
Directory /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location /workspace/coverage/default/2.rom_e2e_self_hash.1836143653
Short name T163
Test name
Test status
Simulation time 27359088968 ps
CPU time 6047.87 seconds
Started Aug 04 07:53:40 PM PDT 24
Finished Aug 04 09:34:28 PM PDT 24
Peak memory 610152 kb
Host smart-a04a4e69-15e0-4fb1-8a78-3abad8cbdc1c
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r
ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836143653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.1836143653
Directory /workspace/2.rom_e2e_self_hash/latest

Test location /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2230044524
Short name T997
Test name
Test status
Simulation time 14792099688 ps
CPU time 3113.11 seconds
Started Aug 04 07:52:03 PM PDT 24
Finished Aug 04 08:43:57 PM PDT 24
Peak memory 611144 kb
Host smart-e57f94d3-11ae-42ef-85a3-5edc532564f5
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne
w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230044524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu
tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_
shutdown_exception_c.2230044524
Directory /workspace/2.rom_e2e_shutdown_exception_c/latest

Test location /workspace/coverage/default/2.rom_e2e_shutdown_output.3211854539
Short name T811
Test name
Test status
Simulation time 31317236720 ps
CPU time 4214.19 seconds
Started Aug 04 07:50:21 PM PDT 24
Finished Aug 04 09:00:36 PM PDT 24
Peak memory 611504 kb
Host smart-eca2d639-20b0-46f3-9203-29ab3fdec24d
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f
lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211854539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rom_e2e_shutdown_output.3211854539
Directory /workspace/2.rom_e2e_shutdown_output/latest

Test location /workspace/coverage/default/2.rom_e2e_smoke.2152350164
Short name T930
Test name
Test status
Simulation time 15229884320 ps
CPU time 3219.17 seconds
Started Aug 04 07:50:56 PM PDT 24
Finished Aug 04 08:44:36 PM PDT 24
Peak memory 610100 kb
Host smart-6f1abc35-b71d-4a53-b0c4-e655358c9a17
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img
_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to
p/hw/dv/tools/sim.tcl +ntb_random_seed=2152350164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.2152350164
Directory /workspace/2.rom_e2e_smoke/latest

Test location /workspace/coverage/default/2.rom_e2e_static_critical.1767213488
Short name T909
Test name
Test status
Simulation time 17349094484 ps
CPU time 3433.52 seconds
Started Aug 04 07:53:04 PM PDT 24
Finished Aug 04 08:50:18 PM PDT 24
Peak memory 610168 kb
Host smart-9618995d-1dac-4b63-a597-8a3ae0286326
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul
es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767213488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.1767213488
Directory /workspace/2.rom_e2e_static_critical/latest

Test location /workspace/coverage/default/2.rom_keymgr_functest.2092759693
Short name T858
Test name
Test status
Simulation time 3852728052 ps
CPU time 401.8 seconds
Started Aug 04 07:50:15 PM PDT 24
Finished Aug 04 07:56:57 PM PDT 24
Peak memory 610344 kb
Host smart-ba332549-eb03-4234-b23d-22596b13a613
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092759693 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.2092759693
Directory /workspace/2.rom_keymgr_functest/latest

Test location /workspace/coverage/default/2.rom_raw_unlock.3961086678
Short name T288
Test name
Test status
Simulation time 5182900644 ps
CPU time 320.9 seconds
Started Aug 04 07:48:47 PM PDT 24
Finished Aug 04 07:54:08 PM PDT 24
Peak memory 619848 kb
Host smart-8ad20c9f-0c8d-4bd2-bf61-94b35aec8fa3
User root
Command /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE
xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3961086678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.3961086678
Directory /workspace/2.rom_raw_unlock/latest

Test location /workspace/coverage/default/2.rom_volatile_raw_unlock.2855862458
Short name T284
Test name
Test status
Simulation time 2258653433 ps
CPU time 111.46 seconds
Started Aug 04 07:47:51 PM PDT 24
Finished Aug 04 07:49:42 PM PDT 24
Peak memory 616996 kb
Host smart-3d04659c-faca-45aa-bc68-2732c573a985
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1
+sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855862458 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.2855862458
Directory /workspace/2.rom_volatile_raw_unlock/latest

Test location /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.225562412
Short name T199
Test name
Test status
Simulation time 4048274340 ps
CPU time 502.12 seconds
Started Aug 04 07:54:25 PM PDT 24
Finished Aug 04 08:02:47 PM PDT 24
Peak memory 649176 kb
Host smart-eb3fabf3-de1f-424d-981f-21029c2712b9
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225562412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_s
w_alert_handler_lpg_sleep_mode_alerts.225562412
Directory /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3541498437
Short name T462
Test name
Test status
Simulation time 3575090538 ps
CPU time 369.44 seconds
Started Aug 04 07:54:05 PM PDT 24
Finished Aug 04 08:00:15 PM PDT 24
Peak memory 649428 kb
Host smart-2b88de1c-09f3-4e33-975f-267d5ba16bd5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541498437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3541498437
Directory /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/24.chip_sw_all_escalation_resets.1451895049
Short name T451
Test name
Test status
Simulation time 5604980916 ps
CPU time 520.01 seconds
Started Aug 04 07:54:11 PM PDT 24
Finished Aug 04 08:02:51 PM PDT 24
Peak memory 650388 kb
Host smart-1bd200d3-b547-4dcc-af30-8c00e737fd08
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1451895049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.1451895049
Directory /workspace/24.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.4062773655
Short name T311
Test name
Test status
Simulation time 4018127228 ps
CPU time 326.45 seconds
Started Aug 04 07:54:33 PM PDT 24
Finished Aug 04 07:59:59 PM PDT 24
Peak memory 648752 kb
Host smart-3009933e-d25a-4259-b745-47c170a40ef0
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062773655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4062773655
Directory /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/25.chip_sw_all_escalation_resets.2999199868
Short name T502
Test name
Test status
Simulation time 4965759076 ps
CPU time 611.85 seconds
Started Aug 04 07:54:39 PM PDT 24
Finished Aug 04 08:04:51 PM PDT 24
Peak memory 649872 kb
Host smart-1981c5ce-4aab-4c8b-8d5b-de2d34fc8d0b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2999199868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.2999199868
Directory /workspace/25.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3673921362
Short name T505
Test name
Test status
Simulation time 3568713900 ps
CPU time 334.81 seconds
Started Aug 04 07:53:54 PM PDT 24
Finished Aug 04 07:59:29 PM PDT 24
Peak memory 648724 kb
Host smart-5250db70-641b-4262-8355-0af83e3d78c4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673921362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3673921362
Directory /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/27.chip_sw_all_escalation_resets.2181355588
Short name T480
Test name
Test status
Simulation time 5023179790 ps
CPU time 622.36 seconds
Started Aug 04 07:54:13 PM PDT 24
Finished Aug 04 08:04:36 PM PDT 24
Peak memory 650356 kb
Host smart-53412edc-2c17-4ab6-90ea-1d0b43d5e713
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2181355588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.2181355588
Directory /workspace/27.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.612345530
Short name T128
Test name
Test status
Simulation time 3829473860 ps
CPU time 408.35 seconds
Started Aug 04 07:54:31 PM PDT 24
Finished Aug 04 08:01:20 PM PDT 24
Peak memory 649636 kb
Host smart-510c8dda-f5be-4699-97f5-3f1b4ba0746e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612345530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_s
w_alert_handler_lpg_sleep_mode_alerts.612345530
Directory /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.609386663
Short name T472
Test name
Test status
Simulation time 3986561620 ps
CPU time 409.79 seconds
Started Aug 04 07:55:01 PM PDT 24
Finished Aug 04 08:01:51 PM PDT 24
Peak memory 649096 kb
Host smart-254cbee3-2e1f-40c9-a5a1-e45242868ec1
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609386663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_s
w_alert_handler_lpg_sleep_mode_alerts.609386663
Directory /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1870124338
Short name T301
Test name
Test status
Simulation time 6790153432 ps
CPU time 525.48 seconds
Started Aug 04 07:48:28 PM PDT 24
Finished Aug 04 07:57:13 PM PDT 24
Peak memory 610480 kb
Host smart-9630a60b-5e5d-4648-8682-811bd9fd5ef7
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1870124338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1870124338
Directory /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3478767156
Short name T598
Test name
Test status
Simulation time 27367705080 ps
CPU time 5529.73 seconds
Started Aug 04 07:50:01 PM PDT 24
Finished Aug 04 09:22:12 PM PDT 24
Peak memory 610336 kb
Host smart-e3928930-bd7a-4a37-a200-0ad6e25a767b
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478767156 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.3478767156
Directory /workspace/3.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/3.chip_sw_data_integrity_escalation.324191340
Short name T750
Test name
Test status
Simulation time 6361629200 ps
CPU time 657.3 seconds
Started Aug 04 07:50:26 PM PDT 24
Finished Aug 04 08:01:24 PM PDT 24
Peak memory 611120 kb
Host smart-69e451d6-0c94-4638-b876-c0959ce9c281
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=324191340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.324191340
Directory /workspace/3.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1174353375
Short name T678
Test name
Test status
Simulation time 13206333142 ps
CPU time 1093.03 seconds
Started Aug 04 07:48:02 PM PDT 24
Finished Aug 04 08:06:16 PM PDT 24
Peak memory 620588 kb
Host smart-63d6db35-f885-413e-9282-21f7c001ddab
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174353375 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.1174353375
Directory /workspace/3.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1188458287
Short name T85
Test name
Test status
Simulation time 4500301482 ps
CPU time 565.91 seconds
Started Aug 04 07:49:15 PM PDT 24
Finished Aug 04 07:58:42 PM PDT 24
Peak memory 610548 kb
Host smart-3e33e1e7-55bf-4fd4-adb3-8e1e7e59520e
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11884582
87 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.1188458287
Directory /workspace/3.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.337384203
Short name T14
Test name
Test status
Simulation time 8471116056 ps
CPU time 1718.64 seconds
Started Aug 04 07:49:22 PM PDT 24
Finished Aug 04 08:18:01 PM PDT 24
Peak memory 623148 kb
Host smart-9a7ba688-7add-4461-b709-2c5fd5bbee96
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=337384203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.337384203
Directory /workspace/3.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx.1351584462
Short name T938
Test name
Test status
Simulation time 4530151000 ps
CPU time 585.44 seconds
Started Aug 04 07:50:03 PM PDT 24
Finished Aug 04 07:59:49 PM PDT 24
Peak memory 623984 kb
Host smart-a9136ae8-ebcd-4219-b42e-3e7f9e8865e3
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351584462 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.1351584462
Directory /workspace/3.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.562998982
Short name T862
Test name
Test status
Simulation time 8314029209 ps
CPU time 1620.28 seconds
Started Aug 04 07:48:11 PM PDT 24
Finished Aug 04 08:15:12 PM PDT 24
Peak memory 618992 kb
Host smart-e62abb42-7d8e-49f7-92bc-ee367b470815
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562998982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba
udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_
alt_clk_freq.562998982
Directory /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3940515904
Short name T744
Test name
Test status
Simulation time 7717979634 ps
CPU time 1107.1 seconds
Started Aug 04 07:49:06 PM PDT 24
Finished Aug 04 08:07:34 PM PDT 24
Peak memory 624528 kb
Host smart-3f501dff-4de5-4c18-8a91-49d29f63ad18
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940515904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.3940515904
Directory /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1311362740
Short name T549
Test name
Test status
Simulation time 4202677764 ps
CPU time 600.82 seconds
Started Aug 04 07:50:14 PM PDT 24
Finished Aug 04 08:00:15 PM PDT 24
Peak memory 623704 kb
Host smart-cfdd7fdf-6235-4037-8d9c-b72c3bbfdf33
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311362740 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.1311362740
Directory /workspace/3.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.75031075
Short name T321
Test name
Test status
Simulation time 4326266182 ps
CPU time 563.65 seconds
Started Aug 04 07:48:04 PM PDT 24
Finished Aug 04 07:57:28 PM PDT 24
Peak memory 624188 kb
Host smart-008f0f99-763f-4a5e-b2a8-5388d99ba395
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75031075 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.75031075
Directory /workspace/3.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1923561561
Short name T548
Test name
Test status
Simulation time 4572791800 ps
CPU time 745.85 seconds
Started Aug 04 07:48:06 PM PDT 24
Finished Aug 04 08:00:32 PM PDT 24
Peak memory 624116 kb
Host smart-1d49638e-6e20-4830-8f72-db6890cb8863
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923561561 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.1923561561
Directory /workspace/3.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/3.chip_tap_straps_dev.1945363566
Short name T636
Test name
Test status
Simulation time 7984890107 ps
CPU time 906.81 seconds
Started Aug 04 07:50:02 PM PDT 24
Finished Aug 04 08:05:09 PM PDT 24
Peak memory 624500 kb
Host smart-b785bb72-b09d-4b7e-918d-1abe68698d3f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1945363566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.1945363566
Directory /workspace/3.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/3.chip_tap_straps_prod.2208912334
Short name T137
Test name
Test status
Simulation time 2361398909 ps
CPU time 172.96 seconds
Started Aug 04 07:48:38 PM PDT 24
Finished Aug 04 07:51:31 PM PDT 24
Peak memory 624260 kb
Host smart-5b709c3a-ead8-447b-ae5c-fbd384e866cf
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2208912334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.2208912334
Directory /workspace/3.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/3.chip_tap_straps_testunlock0.984793063
Short name T89
Test name
Test status
Simulation time 8443351547 ps
CPU time 919.83 seconds
Started Aug 04 07:48:46 PM PDT 24
Finished Aug 04 08:04:06 PM PDT 24
Peak memory 632812 kb
Host smart-d106a902-9dd5-41ea-9aa2-54e4dd162fee
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984793063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.984793063
Directory /workspace/3.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.113138327
Short name T445
Test name
Test status
Simulation time 4051692800 ps
CPU time 369.93 seconds
Started Aug 04 07:55:54 PM PDT 24
Finished Aug 04 08:02:04 PM PDT 24
Peak memory 649500 kb
Host smart-08f96987-bac8-40fe-beb1-6bff2c021da6
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113138327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_s
w_alert_handler_lpg_sleep_mode_alerts.113138327
Directory /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1868814446
Short name T303
Test name
Test status
Simulation time 4042483400 ps
CPU time 426.45 seconds
Started Aug 04 07:55:17 PM PDT 24
Finished Aug 04 08:02:24 PM PDT 24
Peak memory 649084 kb
Host smart-3cac9401-1be5-429f-bcee-6b6f6d9adbc0
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868814446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1868814446
Directory /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/32.chip_sw_all_escalation_resets.604867464
Short name T756
Test name
Test status
Simulation time 4402295014 ps
CPU time 673.26 seconds
Started Aug 04 07:56:18 PM PDT 24
Finished Aug 04 08:07:32 PM PDT 24
Peak memory 650288 kb
Host smart-1cdbe6cd-cc4c-4c28-8e62-7d7ec84b8495
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
604867464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.604867464
Directory /workspace/32.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3859941153
Short name T882
Test name
Test status
Simulation time 3879713848 ps
CPU time 368.01 seconds
Started Aug 04 07:55:37 PM PDT 24
Finished Aug 04 08:01:45 PM PDT 24
Peak memory 649052 kb
Host smart-56f651fd-21c8-4a3b-ae91-3ae52c253d2b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859941153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3859941153
Directory /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/33.chip_sw_all_escalation_resets.770428726
Short name T386
Test name
Test status
Simulation time 6049486624 ps
CPU time 783.37 seconds
Started Aug 04 07:55:57 PM PDT 24
Finished Aug 04 08:09:01 PM PDT 24
Peak memory 650492 kb
Host smart-18721deb-3612-4da8-9879-b42e129fe2b0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
770428726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.770428726
Directory /workspace/33.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/34.chip_sw_all_escalation_resets.154863833
Short name T371
Test name
Test status
Simulation time 5801472920 ps
CPU time 670.32 seconds
Started Aug 04 07:55:29 PM PDT 24
Finished Aug 04 08:06:40 PM PDT 24
Peak memory 650080 kb
Host smart-c597fcc8-8c7d-4796-b97e-71cb7932bb0c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
154863833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.154863833
Directory /workspace/34.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3140362016
Short name T616
Test name
Test status
Simulation time 4527572692 ps
CPU time 413.57 seconds
Started Aug 04 07:55:57 PM PDT 24
Finished Aug 04 08:02:51 PM PDT 24
Peak memory 649692 kb
Host smart-426008ed-b50d-4b37-8d93-70c29be62248
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140362016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3140362016
Directory /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.350476429
Short name T479
Test name
Test status
Simulation time 3676339564 ps
CPU time 428.28 seconds
Started Aug 04 07:54:56 PM PDT 24
Finished Aug 04 08:02:05 PM PDT 24
Peak memory 649316 kb
Host smart-0b838cd2-6efc-45f0-91de-a3ce3d1e2b40
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350476429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_s
w_alert_handler_lpg_sleep_mode_alerts.350476429
Directory /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/36.chip_sw_all_escalation_resets.133666138
Short name T937
Test name
Test status
Simulation time 6123500300 ps
CPU time 634.74 seconds
Started Aug 04 07:56:21 PM PDT 24
Finished Aug 04 08:06:56 PM PDT 24
Peak memory 650712 kb
Host smart-fe52b9e8-b8f9-4834-a03c-6d2abbf4dbe7
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
133666138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.133666138
Directory /workspace/36.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1071221779
Short name T334
Test name
Test status
Simulation time 3656659236 ps
CPU time 318.52 seconds
Started Aug 04 07:58:23 PM PDT 24
Finished Aug 04 08:03:42 PM PDT 24
Peak memory 649032 kb
Host smart-09da525d-3a0a-4739-9bc8-dc8d72feb18f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071221779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1071221779
Directory /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.704749284
Short name T875
Test name
Test status
Simulation time 3320261048 ps
CPU time 364.6 seconds
Started Aug 04 07:49:59 PM PDT 24
Finished Aug 04 07:56:04 PM PDT 24
Peak memory 648968 kb
Host smart-0d5c20ec-eae1-411a-82e8-1910d3113f38
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704749284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw
_alert_handler_lpg_sleep_mode_alerts.704749284
Directory /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2669932256
Short name T686
Test name
Test status
Simulation time 21215683000 ps
CPU time 4508.75 seconds
Started Aug 04 07:49:51 PM PDT 24
Finished Aug 04 09:05:00 PM PDT 24
Peak memory 610400 kb
Host smart-8c8a15e1-49df-43aa-9385-12c815db5280
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669932256 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.2669932256
Directory /workspace/4.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3715429621
Short name T547
Test name
Test status
Simulation time 13945406584 ps
CPU time 997.01 seconds
Started Aug 04 07:49:38 PM PDT 24
Finished Aug 04 08:06:15 PM PDT 24
Peak memory 620444 kb
Host smart-78fe4476-6690-42c3-a22c-a660a3ba8bd7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715429621 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.3715429621
Directory /workspace/4.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.568762059
Short name T82
Test name
Test status
Simulation time 7585073990 ps
CPU time 951.88 seconds
Started Aug 04 07:49:36 PM PDT 24
Finished Aug 04 08:05:28 PM PDT 24
Peak memory 609320 kb
Host smart-89c0ad5e-63ae-4410-b9d5-34666c6378c6
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56876205
9 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.568762059
Directory /workspace/4.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.713986610
Short name T1021
Test name
Test status
Simulation time 4832136568 ps
CPU time 581.14 seconds
Started Aug 04 07:49:22 PM PDT 24
Finished Aug 04 07:59:03 PM PDT 24
Peak memory 624492 kb
Host smart-d371c157-cbb8-4029-866a-7237690ef9c2
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=713986610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.713986610
Directory /workspace/4.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx.623610731
Short name T794
Test name
Test status
Simulation time 3957145750 ps
CPU time 552.55 seconds
Started Aug 04 07:51:02 PM PDT 24
Finished Aug 04 08:00:15 PM PDT 24
Peak memory 623940 kb
Host smart-e66cb759-fd84-4d76-b430-173e742695b1
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623610731 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.623610731
Directory /workspace/4.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.4106257036
Short name T564
Test name
Test status
Simulation time 8347695340 ps
CPU time 1434.58 seconds
Started Aug 04 07:49:46 PM PDT 24
Finished Aug 04 08:13:41 PM PDT 24
Peak memory 619332 kb
Host smart-5d304311-0b5c-4e3c-9e8a-4ba208d2ac2f
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106257036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx
_alt_clk_freq.4106257036
Directory /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1921391864
Short name T676
Test name
Test status
Simulation time 5005083524 ps
CPU time 656.99 seconds
Started Aug 04 07:49:04 PM PDT 24
Finished Aug 04 08:00:02 PM PDT 24
Peak memory 623508 kb
Host smart-7167b7c0-8afd-479a-8304-f08486ea642e
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921391864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.1921391864
Directory /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.30023756
Short name T320
Test name
Test status
Simulation time 3619731040 ps
CPU time 510.64 seconds
Started Aug 04 07:48:50 PM PDT 24
Finished Aug 04 07:57:21 PM PDT 24
Peak memory 622892 kb
Host smart-17b1af1c-5517-4f47-ab98-48e92589cb4f
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30023756 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.30023756
Directory /workspace/4.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2893867305
Short name T558
Test name
Test status
Simulation time 4962374680 ps
CPU time 671.92 seconds
Started Aug 04 07:49:12 PM PDT 24
Finished Aug 04 08:00:24 PM PDT 24
Peak memory 624000 kb
Host smart-c32ba0d1-c97a-4cef-87c8-33790b512dda
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893867305 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.2893867305
Directory /workspace/4.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.722386345
Short name T916
Test name
Test status
Simulation time 3940077176 ps
CPU time 621.02 seconds
Started Aug 04 07:50:31 PM PDT 24
Finished Aug 04 08:00:53 PM PDT 24
Peak memory 623924 kb
Host smart-4ecdf320-5a40-4ee7-b757-01be402eef11
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722386345 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.722386345
Directory /workspace/4.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/4.chip_tap_straps_dev.3864355743
Short name T970
Test name
Test status
Simulation time 10347485691 ps
CPU time 998.38 seconds
Started Aug 04 07:49:44 PM PDT 24
Finished Aug 04 08:06:23 PM PDT 24
Peak memory 621076 kb
Host smart-fae762da-1e57-45b6-a95b-9b06af192920
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3864355743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.3864355743
Directory /workspace/4.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/4.chip_tap_straps_prod.3155900107
Short name T894
Test name
Test status
Simulation time 2549481849 ps
CPU time 128.17 seconds
Started Aug 04 07:49:19 PM PDT 24
Finished Aug 04 07:51:27 PM PDT 24
Peak memory 623320 kb
Host smart-c3d37a43-25d9-45fd-bb84-5c967f0b9914
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3155900107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.3155900107
Directory /workspace/4.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/4.chip_tap_straps_testunlock0.3310028482
Short name T863
Test name
Test status
Simulation time 4161904776 ps
CPU time 327.28 seconds
Started Aug 04 07:49:18 PM PDT 24
Finished Aug 04 07:54:46 PM PDT 24
Peak memory 623612 kb
Host smart-c421b5ff-34c5-4710-b721-5e283de86255
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310028482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.3310028482
Directory /workspace/4.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.576274859
Short name T581
Test name
Test status
Simulation time 3947235824 ps
CPU time 311.44 seconds
Started Aug 04 07:56:03 PM PDT 24
Finished Aug 04 08:01:15 PM PDT 24
Peak memory 619000 kb
Host smart-93de92d2-1565-4869-a037-2cb0206b2f1e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576274859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_s
w_alert_handler_lpg_sleep_mode_alerts.576274859
Directory /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.386062011
Short name T339
Test name
Test status
Simulation time 4433739160 ps
CPU time 494.12 seconds
Started Aug 04 07:58:38 PM PDT 24
Finished Aug 04 08:06:52 PM PDT 24
Peak memory 649416 kb
Host smart-41ef8b41-54bc-4190-b42f-e88574848177
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386062011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_s
w_alert_handler_lpg_sleep_mode_alerts.386062011
Directory /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/41.chip_sw_all_escalation_resets.672755410
Short name T438
Test name
Test status
Simulation time 6106595640 ps
CPU time 489.46 seconds
Started Aug 04 07:55:47 PM PDT 24
Finished Aug 04 08:03:57 PM PDT 24
Peak memory 616944 kb
Host smart-c5af2286-07bb-4e26-bb45-cc458243956f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
672755410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.672755410
Directory /workspace/41.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/42.chip_sw_all_escalation_resets.836196671
Short name T460
Test name
Test status
Simulation time 6412892774 ps
CPU time 826.08 seconds
Started Aug 04 07:55:37 PM PDT 24
Finished Aug 04 08:09:23 PM PDT 24
Peak memory 650348 kb
Host smart-c4cf84de-1f6e-497d-97e8-a7e968430195
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
836196671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.836196671
Directory /workspace/42.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3904783285
Short name T767
Test name
Test status
Simulation time 3183452820 ps
CPU time 345.16 seconds
Started Aug 04 07:56:15 PM PDT 24
Finished Aug 04 08:02:00 PM PDT 24
Peak memory 649208 kb
Host smart-646b144c-41c9-44e6-a0b7-20b6392f0cc7
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904783285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3904783285
Directory /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/43.chip_sw_all_escalation_resets.3199766553
Short name T388
Test name
Test status
Simulation time 4477497372 ps
CPU time 697.76 seconds
Started Aug 04 07:55:31 PM PDT 24
Finished Aug 04 08:07:09 PM PDT 24
Peak memory 650388 kb
Host smart-f087ecef-6221-431b-837e-1ef6be7e6d30
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3199766553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.3199766553
Directory /workspace/43.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.4278939300
Short name T822
Test name
Test status
Simulation time 3664298472 ps
CPU time 413.58 seconds
Started Aug 04 07:56:39 PM PDT 24
Finished Aug 04 08:03:33 PM PDT 24
Peak memory 649060 kb
Host smart-d08a2292-5c15-48b9-bffc-281cd0e35f81
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278939300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4278939300
Directory /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/44.chip_sw_all_escalation_resets.92937803
Short name T3
Test name
Test status
Simulation time 5126576584 ps
CPU time 662.65 seconds
Started Aug 04 07:58:32 PM PDT 24
Finished Aug 04 08:09:35 PM PDT 24
Peak memory 650352 kb
Host smart-2e68f633-dfec-4470-aee5-a9c9c2a89b78
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
92937803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.92937803
Directory /workspace/44.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1026779345
Short name T515
Test name
Test status
Simulation time 3715007896 ps
CPU time 380.33 seconds
Started Aug 04 07:57:02 PM PDT 24
Finished Aug 04 08:03:23 PM PDT 24
Peak memory 649044 kb
Host smart-3742c92e-5f76-4d27-b7a9-138167073d18
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026779345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1026779345
Directory /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/45.chip_sw_all_escalation_resets.4088812315
Short name T491
Test name
Test status
Simulation time 4734300750 ps
CPU time 519.03 seconds
Started Aug 04 07:57:02 PM PDT 24
Finished Aug 04 08:05:41 PM PDT 24
Peak memory 650288 kb
Host smart-35f3ced6-44f4-473f-b834-1e62770c6252
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4088812315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.4088812315
Directory /workspace/45.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/46.chip_sw_all_escalation_resets.1800877243
Short name T158
Test name
Test status
Simulation time 6637107512 ps
CPU time 742.55 seconds
Started Aug 04 07:56:44 PM PDT 24
Finished Aug 04 08:09:07 PM PDT 24
Peak memory 650664 kb
Host smart-2e8483f3-1b0d-4265-834c-6580bd9d38ac
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1800877243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.1800877243
Directory /workspace/46.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/47.chip_sw_all_escalation_resets.3233564774
Short name T685
Test name
Test status
Simulation time 4847756364 ps
CPU time 587.83 seconds
Started Aug 04 07:57:05 PM PDT 24
Finished Aug 04 08:06:53 PM PDT 24
Peak memory 650036 kb
Host smart-c1de8b46-5449-4905-bccb-d64a1c5187d2
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3233564774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.3233564774
Directory /workspace/47.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/48.chip_sw_all_escalation_resets.2048276315
Short name T262
Test name
Test status
Simulation time 5330700016 ps
CPU time 511.27 seconds
Started Aug 04 07:56:26 PM PDT 24
Finished Aug 04 08:04:58 PM PDT 24
Peak memory 650472 kb
Host smart-6a1ec479-7698-4784-9259-537e7d82f6d2
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2048276315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.2048276315
Directory /workspace/48.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1966806093
Short name T973
Test name
Test status
Simulation time 3326411296 ps
CPU time 344.33 seconds
Started Aug 04 07:57:04 PM PDT 24
Finished Aug 04 08:02:49 PM PDT 24
Peak memory 649408 kb
Host smart-4b8b89bd-64b0-4760-ab0d-66bf6e379d57
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966806093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1966806093
Directory /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/5.chip_sw_all_escalation_resets.802775295
Short name T1003
Test name
Test status
Simulation time 4785683500 ps
CPU time 662.33 seconds
Started Aug 04 07:50:23 PM PDT 24
Finished Aug 04 08:01:26 PM PDT 24
Peak memory 650240 kb
Host smart-ee4626d8-8e44-4a2e-9dac-1dcc874dcd00
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
802775295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.802775295
Directory /workspace/5.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3819080623
Short name T881
Test name
Test status
Simulation time 39046889154 ps
CPU time 7968.09 seconds
Started Aug 04 07:50:52 PM PDT 24
Finished Aug 04 10:03:41 PM PDT 24
Peak memory 609380 kb
Host smart-bf319944-393c-4be8-aaa1-71f89d5abfbb
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819080623 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.3819080623
Directory /workspace/5.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2986815449
Short name T268
Test name
Test status
Simulation time 5317257320 ps
CPU time 750.67 seconds
Started Aug 04 07:50:58 PM PDT 24
Finished Aug 04 08:03:29 PM PDT 24
Peak memory 611128 kb
Host smart-a5ece1ce-3973-43fd-9714-c10ef749a6ac
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2986815449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.2986815449
Directory /workspace/5.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3981391068
Short name T925
Test name
Test status
Simulation time 6708044733 ps
CPU time 550.25 seconds
Started Aug 04 07:50:41 PM PDT 24
Finished Aug 04 07:59:52 PM PDT 24
Peak memory 620376 kb
Host smart-a38a52a3-8fff-44e0-a7b3-626e48a3ebd3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981391068 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.3981391068
Directory /workspace/5.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3619580839
Short name T579
Test name
Test status
Simulation time 4647782880 ps
CPU time 707.77 seconds
Started Aug 04 07:52:12 PM PDT 24
Finished Aug 04 08:04:00 PM PDT 24
Peak memory 624476 kb
Host smart-987e9f92-971f-430e-9b98-55a6ed77b2de
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3619580839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.3619580839
Directory /workspace/5.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1280192556
Short name T457
Test name
Test status
Simulation time 3314094002 ps
CPU time 341.77 seconds
Started Aug 04 07:57:38 PM PDT 24
Finished Aug 04 08:03:20 PM PDT 24
Peak memory 648716 kb
Host smart-8cbea43c-94a9-4563-af4e-8ce25fc743d0
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280192556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1280192556
Directory /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.480698699
Short name T516
Test name
Test status
Simulation time 3070985350 ps
CPU time 314.47 seconds
Started Aug 04 07:57:43 PM PDT 24
Finished Aug 04 08:02:57 PM PDT 24
Peak memory 648744 kb
Host smart-f979e49c-98e3-4020-84c6-c9bdc3c763ed
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480698699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_s
w_alert_handler_lpg_sleep_mode_alerts.480698699
Directory /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/51.chip_sw_all_escalation_resets.2630239347
Short name T967
Test name
Test status
Simulation time 5404493506 ps
CPU time 606.64 seconds
Started Aug 04 07:56:31 PM PDT 24
Finished Aug 04 08:06:38 PM PDT 24
Peak memory 619664 kb
Host smart-f6f6f252-217f-443b-a10e-9842089723a5
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2630239347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.2630239347
Directory /workspace/51.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1809071736
Short name T263
Test name
Test status
Simulation time 3902150868 ps
CPU time 302.97 seconds
Started Aug 04 07:57:42 PM PDT 24
Finished Aug 04 08:02:45 PM PDT 24
Peak memory 648812 kb
Host smart-2155d164-1da9-4b3d-821b-90e5e1978b73
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809071736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1809071736
Directory /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/52.chip_sw_all_escalation_resets.2862923182
Short name T1005
Test name
Test status
Simulation time 4641806448 ps
CPU time 745.97 seconds
Started Aug 04 07:56:42 PM PDT 24
Finished Aug 04 08:09:08 PM PDT 24
Peak memory 650284 kb
Host smart-bc7dcd69-ca51-4b79-9580-6d113a5afd33
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2862923182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.2862923182
Directory /workspace/52.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.678902814
Short name T488
Test name
Test status
Simulation time 3875760822 ps
CPU time 447.86 seconds
Started Aug 04 07:57:30 PM PDT 24
Finished Aug 04 08:04:58 PM PDT 24
Peak memory 649064 kb
Host smart-53428781-d7f9-404d-ae49-2bac79f0676b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678902814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_s
w_alert_handler_lpg_sleep_mode_alerts.678902814
Directory /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/53.chip_sw_all_escalation_resets.1803543626
Short name T127
Test name
Test status
Simulation time 4228043308 ps
CPU time 510.23 seconds
Started Aug 04 07:57:49 PM PDT 24
Finished Aug 04 08:06:20 PM PDT 24
Peak memory 650752 kb
Host smart-935d12b3-daef-4af1-b71f-d12de43e8f10
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1803543626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.1803543626
Directory /workspace/53.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3581550892
Short name T352
Test name
Test status
Simulation time 3762738152 ps
CPU time 415.92 seconds
Started Aug 04 07:57:22 PM PDT 24
Finished Aug 04 08:04:18 PM PDT 24
Peak memory 649276 kb
Host smart-be706d62-254c-473b-bc43-9bde62f4c5ac
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581550892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3581550892
Directory /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.4196140425
Short name T354
Test name
Test status
Simulation time 3299073816 ps
CPU time 400.31 seconds
Started Aug 04 07:58:35 PM PDT 24
Finished Aug 04 08:05:16 PM PDT 24
Peak memory 649140 kb
Host smart-dc2da6ad-8559-41e2-a305-13f486f7205e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196140425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4196140425
Directory /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/56.chip_sw_all_escalation_resets.2679324419
Short name T779
Test name
Test status
Simulation time 6484018856 ps
CPU time 626.03 seconds
Started Aug 04 08:00:43 PM PDT 24
Finished Aug 04 08:11:10 PM PDT 24
Peak memory 650368 kb
Host smart-5580ff0b-f20b-4270-991b-33546dd3714d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2679324419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.2679324419
Directory /workspace/56.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1114287797
Short name T469
Test name
Test status
Simulation time 3764608820 ps
CPU time 392.12 seconds
Started Aug 04 07:57:31 PM PDT 24
Finished Aug 04 08:04:04 PM PDT 24
Peak memory 648988 kb
Host smart-330dc5d6-459e-4052-958c-febb802a205d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114287797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1114287797
Directory /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/57.chip_sw_all_escalation_resets.3414734563
Short name T507
Test name
Test status
Simulation time 4334381040 ps
CPU time 533.22 seconds
Started Aug 04 07:57:36 PM PDT 24
Finished Aug 04 08:06:30 PM PDT 24
Peak memory 650320 kb
Host smart-cb8e69e9-1fe1-451a-86d8-5f0dc0a5ce20
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3414734563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.3414734563
Directory /workspace/57.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2886269540
Short name T213
Test name
Test status
Simulation time 3602315424 ps
CPU time 353.8 seconds
Started Aug 04 07:57:51 PM PDT 24
Finished Aug 04 08:03:45 PM PDT 24
Peak memory 649124 kb
Host smart-47232708-8b4e-4ba0-ba45-95f8b27c95c2
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886269540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2886269540
Directory /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/58.chip_sw_all_escalation_resets.1807421206
Short name T455
Test name
Test status
Simulation time 4791086894 ps
CPU time 384.97 seconds
Started Aug 04 07:57:39 PM PDT 24
Finished Aug 04 08:04:04 PM PDT 24
Peak memory 650308 kb
Host smart-30498a04-dd3f-4724-afdb-86f9c67940c3
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1807421206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.1807421206
Directory /workspace/58.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1191492389
Short name T430
Test name
Test status
Simulation time 3837377254 ps
CPU time 355.17 seconds
Started Aug 04 07:57:31 PM PDT 24
Finished Aug 04 08:03:26 PM PDT 24
Peak memory 649032 kb
Host smart-6063a964-08d0-4d43-8768-d0ea536527b0
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191492389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1191492389
Directory /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/59.chip_sw_all_escalation_resets.4097829694
Short name T307
Test name
Test status
Simulation time 4472782530 ps
CPU time 451.11 seconds
Started Aug 04 07:57:11 PM PDT 24
Finished Aug 04 08:04:42 PM PDT 24
Peak memory 649908 kb
Host smart-92c2fc2b-15d9-4833-a3b6-5585280e196d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4097829694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.4097829694
Directory /workspace/59.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.4169432015
Short name T518
Test name
Test status
Simulation time 4214459030 ps
CPU time 382.98 seconds
Started Aug 04 07:51:45 PM PDT 24
Finished Aug 04 07:58:08 PM PDT 24
Peak memory 648736 kb
Host smart-4876649c-88d8-4f72-9bf7-74e278f4885f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169432015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s
w_alert_handler_lpg_sleep_mode_alerts.4169432015
Directory /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/6.chip_sw_all_escalation_resets.2548262886
Short name T208
Test name
Test status
Simulation time 6196828194 ps
CPU time 586.3 seconds
Started Aug 04 07:50:20 PM PDT 24
Finished Aug 04 08:00:06 PM PDT 24
Peak memory 616904 kb
Host smart-7c9c8164-d420-404d-bac6-d16b7c937cb0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2548262886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.2548262886
Directory /workspace/6.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.876803196
Short name T760
Test name
Test status
Simulation time 26453828030 ps
CPU time 5713.34 seconds
Started Aug 04 07:51:22 PM PDT 24
Finished Aug 04 09:26:35 PM PDT 24
Peak memory 610216 kb
Host smart-126bf1e4-4aab-4eba-bb33-03273f993a89
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876803196 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.876803196
Directory /workspace/6.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2299049140
Short name T562
Test name
Test status
Simulation time 4048262932 ps
CPU time 670.51 seconds
Started Aug 04 07:51:41 PM PDT 24
Finished Aug 04 08:02:52 PM PDT 24
Peak memory 618960 kb
Host smart-f51963ad-b4ac-4a3b-a0c7-f7d8f05a6cdd
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2299049140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.2299049140
Directory /workspace/6.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3177743210
Short name T436
Test name
Test status
Simulation time 3668518468 ps
CPU time 347.01 seconds
Started Aug 04 07:57:48 PM PDT 24
Finished Aug 04 08:03:36 PM PDT 24
Peak memory 649108 kb
Host smart-c1012dc7-d4e5-48c3-8878-d0a97694a2fd
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177743210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3177743210
Directory /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/60.chip_sw_all_escalation_resets.3187238240
Short name T398
Test name
Test status
Simulation time 4815582600 ps
CPU time 547.11 seconds
Started Aug 04 07:58:38 PM PDT 24
Finished Aug 04 08:07:45 PM PDT 24
Peak memory 611112 kb
Host smart-27a8116a-f827-4eb0-b725-56303e9ab8a3
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3187238240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.3187238240
Directory /workspace/60.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/61.chip_sw_all_escalation_resets.1527367797
Short name T992
Test name
Test status
Simulation time 5564250880 ps
CPU time 562.64 seconds
Started Aug 04 07:57:52 PM PDT 24
Finished Aug 04 08:07:15 PM PDT 24
Peak memory 650356 kb
Host smart-2a9fa0f4-569b-4674-a611-ece2d8b145ac
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1527367797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.1527367797
Directory /workspace/61.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3154814865
Short name T514
Test name
Test status
Simulation time 3911576062 ps
CPU time 459.54 seconds
Started Aug 04 07:59:05 PM PDT 24
Finished Aug 04 08:06:45 PM PDT 24
Peak memory 649036 kb
Host smart-68cb23d5-7ef3-4e7b-9aea-2902240c23a0
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154814865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3154814865
Directory /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2733192291
Short name T312
Test name
Test status
Simulation time 3561376168 ps
CPU time 429.58 seconds
Started Aug 04 07:59:29 PM PDT 24
Finished Aug 04 08:06:38 PM PDT 24
Peak memory 649036 kb
Host smart-2800fe2c-7426-48b6-a901-4368b8410379
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733192291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2733192291
Directory /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/63.chip_sw_all_escalation_resets.2206773414
Short name T113
Test name
Test status
Simulation time 5866246000 ps
CPU time 695.7 seconds
Started Aug 04 07:58:40 PM PDT 24
Finished Aug 04 08:10:16 PM PDT 24
Peak memory 616928 kb
Host smart-b09afe2a-8ccd-45ca-a739-91fd194a4d2d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2206773414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.2206773414
Directory /workspace/63.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2890880863
Short name T443
Test name
Test status
Simulation time 4447270384 ps
CPU time 484.12 seconds
Started Aug 04 07:58:43 PM PDT 24
Finished Aug 04 08:06:47 PM PDT 24
Peak memory 649544 kb
Host smart-b1d8fdb1-c0f4-4e6c-81ea-4ee85ab9856e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890880863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2890880863
Directory /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/64.chip_sw_all_escalation_resets.3541497534
Short name T482
Test name
Test status
Simulation time 5376874528 ps
CPU time 726.1 seconds
Started Aug 04 07:59:10 PM PDT 24
Finished Aug 04 08:11:17 PM PDT 24
Peak memory 650064 kb
Host smart-8c5f8a7c-54a6-4e71-b34b-2cd698d40b25
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3541497534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.3541497534
Directory /workspace/64.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/65.chip_sw_all_escalation_resets.3937164569
Short name T884
Test name
Test status
Simulation time 4450187898 ps
CPU time 714.06 seconds
Started Aug 04 07:59:13 PM PDT 24
Finished Aug 04 08:11:07 PM PDT 24
Peak memory 650284 kb
Host smart-e6c8987c-1c89-4588-a24c-6578a319f960
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3937164569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.3937164569
Directory /workspace/65.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.298876867
Short name T130
Test name
Test status
Simulation time 3278293276 ps
CPU time 331.88 seconds
Started Aug 04 07:58:52 PM PDT 24
Finished Aug 04 08:04:24 PM PDT 24
Peak memory 649316 kb
Host smart-b0e8950a-608b-42d6-b20c-d5f78cbdf585
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298876867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_s
w_alert_handler_lpg_sleep_mode_alerts.298876867
Directory /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/66.chip_sw_all_escalation_resets.3759362314
Short name T866
Test name
Test status
Simulation time 5434139120 ps
CPU time 554.68 seconds
Started Aug 04 08:01:53 PM PDT 24
Finished Aug 04 08:11:08 PM PDT 24
Peak memory 650252 kb
Host smart-949f1871-7555-47f8-997d-61c94857fbbf
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3759362314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.3759362314
Directory /workspace/66.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3887476618
Short name T1022
Test name
Test status
Simulation time 4362568300 ps
CPU time 406.69 seconds
Started Aug 04 07:58:35 PM PDT 24
Finished Aug 04 08:05:22 PM PDT 24
Peak memory 649512 kb
Host smart-1e15b7a6-c07a-4ef7-9726-bd46dfee640d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887476618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3887476618
Directory /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/67.chip_sw_all_escalation_resets.3830567773
Short name T302
Test name
Test status
Simulation time 5787822116 ps
CPU time 629.1 seconds
Started Aug 04 07:58:54 PM PDT 24
Finished Aug 04 08:09:23 PM PDT 24
Peak memory 649908 kb
Host smart-dc13bc2e-9ee7-48c5-837a-66417d4c44c1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3830567773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.3830567773
Directory /workspace/67.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/68.chip_sw_all_escalation_resets.2285007467
Short name T477
Test name
Test status
Simulation time 5811077120 ps
CPU time 461.47 seconds
Started Aug 04 07:58:32 PM PDT 24
Finished Aug 04 08:06:14 PM PDT 24
Peak memory 650328 kb
Host smart-65337e31-16c6-4342-95ba-7eb17a0260af
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2285007467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.2285007467
Directory /workspace/68.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/69.chip_sw_all_escalation_resets.2734596409
Short name T470
Test name
Test status
Simulation time 4568320964 ps
CPU time 600.48 seconds
Started Aug 04 07:58:34 PM PDT 24
Finished Aug 04 08:08:34 PM PDT 24
Peak memory 650376 kb
Host smart-f85cebe9-f900-4866-a2dc-decaaff6142d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2734596409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.2734596409
Directory /workspace/69.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2422575415
Short name T357
Test name
Test status
Simulation time 4056388200 ps
CPU time 363.51 seconds
Started Aug 04 07:51:37 PM PDT 24
Finished Aug 04 07:57:40 PM PDT 24
Peak memory 649228 kb
Host smart-d804f91b-b507-4f01-a9b9-7cb1733b3bde
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422575415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s
w_alert_handler_lpg_sleep_mode_alerts.2422575415
Directory /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/7.chip_sw_all_escalation_resets.4068376323
Short name T503
Test name
Test status
Simulation time 6534468158 ps
CPU time 860.09 seconds
Started Aug 04 07:50:58 PM PDT 24
Finished Aug 04 08:05:19 PM PDT 24
Peak memory 650292 kb
Host smart-016e6d39-4e8e-4e9b-86c0-747d23622b7a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4068376323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.4068376323
Directory /workspace/7.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3332316368
Short name T1014
Test name
Test status
Simulation time 21166683032 ps
CPU time 4693.62 seconds
Started Aug 04 07:51:11 PM PDT 24
Finished Aug 04 09:09:25 PM PDT 24
Peak memory 610044 kb
Host smart-dbb449ca-d366-4568-9a5f-89a499173bb8
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332316368 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.3332316368
Directory /workspace/7.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1876520467
Short name T960
Test name
Test status
Simulation time 11442204526 ps
CPU time 1112.5 seconds
Started Aug 04 07:51:33 PM PDT 24
Finished Aug 04 08:10:06 PM PDT 24
Peak memory 624756 kb
Host smart-921879cb-66c2-4204-8d6f-f256e0b1c99f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876520467 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.1876520467
Directory /workspace/7.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1505666743
Short name T886
Test name
Test status
Simulation time 12957066232 ps
CPU time 2565.73 seconds
Started Aug 04 07:50:50 PM PDT 24
Finished Aug 04 08:33:36 PM PDT 24
Peak memory 624496 kb
Host smart-9cdeafea-d135-4fe2-84c5-b81acb7b2dc6
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1505666743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.1505666743
Directory /workspace/7.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/71.chip_sw_all_escalation_resets.2345179013
Short name T282
Test name
Test status
Simulation time 5183825100 ps
CPU time 583.31 seconds
Started Aug 04 08:00:02 PM PDT 24
Finished Aug 04 08:09:48 PM PDT 24
Peak memory 650252 kb
Host smart-95c72217-704e-49a8-b187-e783faf7d83a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2345179013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.2345179013
Directory /workspace/71.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/72.chip_sw_all_escalation_resets.703630756
Short name T306
Test name
Test status
Simulation time 5284984084 ps
CPU time 515 seconds
Started Aug 04 07:59:24 PM PDT 24
Finished Aug 04 08:07:59 PM PDT 24
Peak memory 650264 kb
Host smart-67249115-6014-41ed-a4bc-fb349289a690
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
703630756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.703630756
Directory /workspace/72.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3565380048
Short name T440
Test name
Test status
Simulation time 4104717912 ps
CPU time 336.75 seconds
Started Aug 04 07:58:48 PM PDT 24
Finished Aug 04 08:04:25 PM PDT 24
Peak memory 648928 kb
Host smart-dd2f30f3-3800-4e16-9a25-bb94d0ff1530
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565380048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3565380048
Directory /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/74.chip_sw_all_escalation_resets.847565451
Short name T419
Test name
Test status
Simulation time 5535750200 ps
CPU time 668.99 seconds
Started Aug 04 08:00:03 PM PDT 24
Finished Aug 04 08:11:14 PM PDT 24
Peak memory 650004 kb
Host smart-fa301b8f-ed10-4496-9600-1f8b809a8635
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
847565451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.847565451
Directory /workspace/74.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.683663243
Short name T437
Test name
Test status
Simulation time 3507590230 ps
CPU time 362.95 seconds
Started Aug 04 07:59:54 PM PDT 24
Finished Aug 04 08:05:57 PM PDT 24
Peak memory 648996 kb
Host smart-5371ae0a-f4f1-42cc-a09f-fe8d66f9a8f2
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683663243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_s
w_alert_handler_lpg_sleep_mode_alerts.683663243
Directory /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.42424960
Short name T500
Test name
Test status
Simulation time 4574972152 ps
CPU time 324.85 seconds
Started Aug 04 08:00:09 PM PDT 24
Finished Aug 04 08:05:34 PM PDT 24
Peak memory 649356 kb
Host smart-c56ca892-18ef-4a63-9d61-bb412ad202ed
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42424960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_
escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw
_alert_handler_lpg_sleep_mode_alerts.42424960
Directory /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/76.chip_sw_all_escalation_resets.153494329
Short name T448
Test name
Test status
Simulation time 6334736048 ps
CPU time 662.98 seconds
Started Aug 04 08:00:51 PM PDT 24
Finished Aug 04 08:11:54 PM PDT 24
Peak memory 650092 kb
Host smart-64dbda89-fdff-4bf6-9aa8-7a441723fc72
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
153494329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.153494329
Directory /workspace/76.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2075671621
Short name T353
Test name
Test status
Simulation time 3374286834 ps
CPU time 340.03 seconds
Started Aug 04 08:00:07 PM PDT 24
Finished Aug 04 08:05:48 PM PDT 24
Peak memory 649300 kb
Host smart-fa4f12f7-e393-452b-9bfd-9e607c1d5dbd
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075671621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2075671621
Directory /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2779729903
Short name T310
Test name
Test status
Simulation time 2968669916 ps
CPU time 342.92 seconds
Started Aug 04 08:00:47 PM PDT 24
Finished Aug 04 08:06:30 PM PDT 24
Peak memory 649104 kb
Host smart-0e73cf76-7f25-4cc3-85df-0ed3557bf891
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779729903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2779729903
Directory /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1631280959
Short name T508
Test name
Test status
Simulation time 3344238700 ps
CPU time 323.58 seconds
Started Aug 04 07:51:37 PM PDT 24
Finished Aug 04 07:57:01 PM PDT 24
Peak memory 649184 kb
Host smart-dc85cdab-42a0-45f3-b37a-df78f0695ea4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631280959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s
w_alert_handler_lpg_sleep_mode_alerts.1631280959
Directory /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/8.chip_sw_all_escalation_resets.1006309508
Short name T522
Test name
Test status
Simulation time 5821813958 ps
CPU time 604.63 seconds
Started Aug 04 07:51:26 PM PDT 24
Finished Aug 04 08:01:31 PM PDT 24
Peak memory 650092 kb
Host smart-28972377-240f-432d-8647-0ffa5ecf6e42
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1006309508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.1006309508
Directory /workspace/8.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.287720536
Short name T954
Test name
Test status
Simulation time 5499709027 ps
CPU time 584.14 seconds
Started Aug 04 07:52:07 PM PDT 24
Finished Aug 04 08:01:51 PM PDT 24
Peak memory 620404 kb
Host smart-e45c0fcf-f7f0-42cb-97a6-f879fd025a7d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287720536 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.287720536
Directory /workspace/8.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3056735370
Short name T671
Test name
Test status
Simulation time 4412623064 ps
CPU time 463.17 seconds
Started Aug 04 07:50:59 PM PDT 24
Finished Aug 04 07:58:42 PM PDT 24
Peak memory 624464 kb
Host smart-2609a50c-33f6-4069-b52a-5eecab749871
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3056735370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.3056735370
Directory /workspace/8.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1395346985
Short name T446
Test name
Test status
Simulation time 4163700704 ps
CPU time 342.83 seconds
Started Aug 04 08:00:18 PM PDT 24
Finished Aug 04 08:06:01 PM PDT 24
Peak memory 649272 kb
Host smart-606223d4-3c82-49fa-ac48-bf2dd0b94f63
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395346985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1395346985
Directory /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2138717311
Short name T486
Test name
Test status
Simulation time 3667854880 ps
CPU time 298.32 seconds
Started Aug 04 07:59:36 PM PDT 24
Finished Aug 04 08:04:35 PM PDT 24
Peak memory 649120 kb
Host smart-614c145a-39cc-499d-957d-8f7084bf7ab8
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138717311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2138717311
Directory /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/81.chip_sw_all_escalation_resets.2628164027
Short name T154
Test name
Test status
Simulation time 5009779580 ps
CPU time 558.28 seconds
Started Aug 04 08:00:07 PM PDT 24
Finished Aug 04 08:09:26 PM PDT 24
Peak memory 650452 kb
Host smart-3157583e-4fb2-46c7-8fe2-e04c932f6b2f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2628164027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.2628164027
Directory /workspace/81.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2784488852
Short name T431
Test name
Test status
Simulation time 3288379364 ps
CPU time 336 seconds
Started Aug 04 08:00:32 PM PDT 24
Finished Aug 04 08:06:08 PM PDT 24
Peak memory 648824 kb
Host smart-f7dfce8e-78b0-4040-a4a5-b1741921facc
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784488852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2784488852
Directory /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/82.chip_sw_all_escalation_resets.3710755714
Short name T461
Test name
Test status
Simulation time 4994527356 ps
CPU time 559.54 seconds
Started Aug 04 08:01:27 PM PDT 24
Finished Aug 04 08:10:46 PM PDT 24
Peak memory 650512 kb
Host smart-9e96cd66-7a60-4494-a9cf-0a1783db7cae
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3710755714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.3710755714
Directory /workspace/82.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3558211767
Short name T816
Test name
Test status
Simulation time 4040502858 ps
CPU time 335.77 seconds
Started Aug 04 08:01:25 PM PDT 24
Finished Aug 04 08:07:00 PM PDT 24
Peak memory 648816 kb
Host smart-3072cd5b-682e-4f4c-b341-fc0c6b0c5ad4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558211767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3558211767
Directory /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/83.chip_sw_all_escalation_resets.2337669764
Short name T281
Test name
Test status
Simulation time 5165810664 ps
CPU time 576.13 seconds
Started Aug 04 08:00:24 PM PDT 24
Finished Aug 04 08:10:00 PM PDT 24
Peak memory 650632 kb
Host smart-231d4e14-c67c-4064-9ee1-c1ae799ba345
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2337669764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.2337669764
Directory /workspace/83.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1618292891
Short name T452
Test name
Test status
Simulation time 3569942400 ps
CPU time 396.21 seconds
Started Aug 04 08:01:21 PM PDT 24
Finished Aug 04 08:07:58 PM PDT 24
Peak memory 648880 kb
Host smart-1e2e966c-d5d0-4dda-b6a1-662095c57d0b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618292891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1618292891
Directory /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/84.chip_sw_all_escalation_resets.456520590
Short name T439
Test name
Test status
Simulation time 4931139592 ps
CPU time 620.78 seconds
Started Aug 04 08:01:07 PM PDT 24
Finished Aug 04 08:11:28 PM PDT 24
Peak memory 616848 kb
Host smart-9409be41-97c9-48e3-bc83-e6c597d9d3bd
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
456520590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.456520590
Directory /workspace/84.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/85.chip_sw_all_escalation_resets.1542991893
Short name T453
Test name
Test status
Simulation time 6250781368 ps
CPU time 572.75 seconds
Started Aug 04 08:00:45 PM PDT 24
Finished Aug 04 08:10:18 PM PDT 24
Peak memory 650340 kb
Host smart-c008ec23-1e5a-489b-a265-3969fb6d0a67
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1542991893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.1542991893
Directory /workspace/85.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.829383373
Short name T493
Test name
Test status
Simulation time 3291380750 ps
CPU time 356.36 seconds
Started Aug 04 08:01:22 PM PDT 24
Finished Aug 04 08:07:18 PM PDT 24
Peak memory 648736 kb
Host smart-84893ce7-d939-4e6e-a77a-fcc274c7a818
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829383373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_s
w_alert_handler_lpg_sleep_mode_alerts.829383373
Directory /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.17336207
Short name T295
Test name
Test status
Simulation time 3808892962 ps
CPU time 357.8 seconds
Started Aug 04 08:00:21 PM PDT 24
Finished Aug 04 08:06:19 PM PDT 24
Peak memory 649212 kb
Host smart-40d36e84-13a8-4eaa-b930-91cf1ee764c0
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17336207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_
escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw
_alert_handler_lpg_sleep_mode_alerts.17336207
Directory /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/87.chip_sw_all_escalation_resets.1482360368
Short name T399
Test name
Test status
Simulation time 4242081160 ps
CPU time 475.31 seconds
Started Aug 04 08:00:22 PM PDT 24
Finished Aug 04 08:08:18 PM PDT 24
Peak memory 610796 kb
Host smart-8116c7d5-0f3f-427b-8f0b-2527b4851510
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1482360368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.1482360368
Directory /workspace/87.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2912368270
Short name T490
Test name
Test status
Simulation time 3093812968 ps
CPU time 277.77 seconds
Started Aug 04 08:01:11 PM PDT 24
Finished Aug 04 08:05:49 PM PDT 24
Peak memory 649124 kb
Host smart-ced6561c-6209-4eca-a505-162682d06bbc
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912368270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2912368270
Directory /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3437834054
Short name T520
Test name
Test status
Simulation time 4307401196 ps
CPU time 374.7 seconds
Started Aug 04 08:01:09 PM PDT 24
Finished Aug 04 08:07:24 PM PDT 24
Peak memory 649468 kb
Host smart-02ab743f-ed3a-403b-a8e2-5cbc6e65a802
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437834054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3437834054
Directory /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/89.chip_sw_all_escalation_resets.544299579
Short name T484
Test name
Test status
Simulation time 5904432884 ps
CPU time 535 seconds
Started Aug 04 08:00:45 PM PDT 24
Finished Aug 04 08:09:41 PM PDT 24
Peak memory 650304 kb
Host smart-4f855e64-2ff4-46ed-82ff-ef07a1a74978
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
544299579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.544299579
Directory /workspace/89.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2021709058
Short name T264
Test name
Test status
Simulation time 3726467986 ps
CPU time 489.58 seconds
Started Aug 04 07:51:37 PM PDT 24
Finished Aug 04 07:59:47 PM PDT 24
Peak memory 649056 kb
Host smart-fb03d495-a9e5-4684-b635-575f571398a7
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021709058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s
w_alert_handler_lpg_sleep_mode_alerts.2021709058
Directory /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/9.chip_sw_all_escalation_resets.2332578768
Short name T521
Test name
Test status
Simulation time 5447537704 ps
CPU time 710.06 seconds
Started Aug 04 07:52:44 PM PDT 24
Finished Aug 04 08:04:35 PM PDT 24
Peak memory 650056 kb
Host smart-2f7d5dee-e58a-445b-a21f-b8563ec2cd4d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2332578768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.2332578768
Directory /workspace/9.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2414245461
Short name T407
Test name
Test status
Simulation time 26573920336 ps
CPU time 5514.12 seconds
Started Aug 04 07:51:57 PM PDT 24
Finished Aug 04 09:23:51 PM PDT 24
Peak memory 610372 kb
Host smart-fc133337-46af-42b3-b48b-42fc495ff673
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414245461 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.2414245461
Directory /workspace/9.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1196772174
Short name T980
Test name
Test status
Simulation time 6227872319 ps
CPU time 472.57 seconds
Started Aug 04 07:50:43 PM PDT 24
Finished Aug 04 07:58:35 PM PDT 24
Peak memory 624664 kb
Host smart-50febfc5-6b8a-4347-ad93-d54f8302cc8b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196772174 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.1196772174
Directory /workspace/9.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1641002274
Short name T860
Test name
Test status
Simulation time 8667350636 ps
CPU time 1474.39 seconds
Started Aug 04 07:51:08 PM PDT 24
Finished Aug 04 08:15:43 PM PDT 24
Peak memory 623204 kb
Host smart-86272814-4aef-401e-bf6d-98014a1deb01
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1641002274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.1641002274
Directory /workspace/9.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/90.chip_sw_all_escalation_resets.2810718304
Short name T985
Test name
Test status
Simulation time 5390536300 ps
CPU time 524.07 seconds
Started Aug 04 08:01:22 PM PDT 24
Finished Aug 04 08:10:06 PM PDT 24
Peak memory 649960 kb
Host smart-36997516-3328-4edb-83c1-68cd18200bad
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2810718304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.2810718304
Directory /workspace/90.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/91.chip_sw_all_escalation_resets.188974983
Short name T510
Test name
Test status
Simulation time 6321903640 ps
CPU time 462.88 seconds
Started Aug 04 08:01:21 PM PDT 24
Finished Aug 04 08:09:04 PM PDT 24
Peak memory 650368 kb
Host smart-c7efea95-0247-428d-ac07-ae7009ee43d4
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
188974983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.188974983
Directory /workspace/91.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/92.chip_sw_all_escalation_resets.3915428061
Short name T447
Test name
Test status
Simulation time 5728884040 ps
CPU time 582.81 seconds
Started Aug 04 08:01:33 PM PDT 24
Finished Aug 04 08:11:16 PM PDT 24
Peak memory 650384 kb
Host smart-a1ff77c3-fe32-4b59-8740-d27c56c1c0c8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3915428061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.3915428061
Directory /workspace/92.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/93.chip_sw_all_escalation_resets.4113621345
Short name T481
Test name
Test status
Simulation time 5127582800 ps
CPU time 522.49 seconds
Started Aug 04 08:02:06 PM PDT 24
Finished Aug 04 08:10:49 PM PDT 24
Peak memory 650468 kb
Host smart-2887db0c-ed89-4d1f-8acc-e9d771b1b23a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4113621345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.4113621345
Directory /workspace/93.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/96.chip_sw_all_escalation_resets.2523873452
Short name T748
Test name
Test status
Simulation time 4923617352 ps
CPU time 490.48 seconds
Started Aug 04 08:01:40 PM PDT 24
Finished Aug 04 08:09:51 PM PDT 24
Peak memory 650216 kb
Host smart-7400ed71-3e5a-4f3c-92ec-ff8c3b1d5586
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2523873452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.2523873452
Directory /workspace/96.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/97.chip_sw_all_escalation_resets.1853796734
Short name T904
Test name
Test status
Simulation time 4794687408 ps
CPU time 564.43 seconds
Started Aug 04 08:02:45 PM PDT 24
Finished Aug 04 08:12:10 PM PDT 24
Peak memory 649940 kb
Host smart-0f81d50e-d943-4bdb-92ac-8795e63d6d5a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1853796734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.1853796734
Directory /workspace/97.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/98.chip_sw_all_escalation_resets.1236007686
Short name T149
Test name
Test status
Simulation time 5010719296 ps
CPU time 467.18 seconds
Started Aug 04 08:01:22 PM PDT 24
Finished Aug 04 08:09:09 PM PDT 24
Peak memory 650196 kb
Host smart-e55ae1aa-9e06-483e-af0e-11c1e30fceea
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1236007686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.1236007686
Directory /workspace/98.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/99.chip_sw_all_escalation_resets.2115158928
Short name T387
Test name
Test status
Simulation time 4555641748 ps
CPU time 533.72 seconds
Started Aug 04 08:01:44 PM PDT 24
Finished Aug 04 08:10:38 PM PDT 24
Peak memory 650220 kb
Host smart-5342abda-5090-480e-93c9-310ccce97c01
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2115158928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.2115158928
Directory /workspace/99.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3632494374
Short name T239
Test name
Test status
Simulation time 5225866541 ps
CPU time 298.43 seconds
Started Aug 04 07:06:26 PM PDT 24
Finished Aug 04 07:11:25 PM PDT 24
Peak memory 657364 kb
Host smart-0f7c9be6-57d9-4802-81ff-f9f3de014921
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632494374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 2.chip_padctrl_attributes.3632494374
Directory /workspace/2.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2245265714
Short name T237
Test name
Test status
Simulation time 4660298891 ps
CPU time 279.12 seconds
Started Aug 04 07:06:26 PM PDT 24
Finished Aug 04 07:11:06 PM PDT 24
Peak memory 649160 kb
Host smart-3f77ba83-ffeb-4d34-96e2-95ae3cdfe91d
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245265714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 3.chip_padctrl_attributes.2245265714
Directory /workspace/3.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2129899363
Short name T31
Test name
Test status
Simulation time 5109307950 ps
CPU time 270.44 seconds
Started Aug 04 07:06:23 PM PDT 24
Finished Aug 04 07:10:54 PM PDT 24
Peak memory 653056 kb
Host smart-39eb79f9-03a0-4da5-b421-510c78181337
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129899363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 5.chip_padctrl_attributes.2129899363
Directory /workspace/5.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1954381189
Short name T236
Test name
Test status
Simulation time 4515311632 ps
CPU time 232.41 seconds
Started Aug 04 07:06:30 PM PDT 24
Finished Aug 04 07:10:23 PM PDT 24
Peak memory 649168 kb
Host smart-67c7c1e1-285d-441f-bb80-81c2fc448553
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954381189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 6.chip_padctrl_attributes.1954381189
Directory /workspace/6.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.506914179
Short name T30
Test name
Test status
Simulation time 3752378691 ps
CPU time 200.68 seconds
Started Aug 04 07:06:22 PM PDT 24
Finished Aug 04 07:09:43 PM PDT 24
Peak memory 652540 kb
Host smart-fec8421b-4f4d-4903-96a5-ed94c7c40e83
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506914179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n
ull -cm_name 7.chip_padctrl_attributes.506914179
Directory /workspace/7.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.545822328
Short name T235
Test name
Test status
Simulation time 5107117745 ps
CPU time 265.43 seconds
Started Aug 04 07:06:22 PM PDT 24
Finished Aug 04 07:10:48 PM PDT 24
Peak memory 657332 kb
Host smart-d33e59d2-3995-4602-9421-99d9d328fc71
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545822328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n
ull -cm_name 8.chip_padctrl_attributes.545822328
Directory /workspace/8.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1177379512
Short name T238
Test name
Test status
Simulation time 4528064330 ps
CPU time 234.31 seconds
Started Aug 04 07:06:23 PM PDT 24
Finished Aug 04 07:10:17 PM PDT 24
Peak memory 657364 kb
Host smart-953bf30f-b92d-4faa-b01f-e99edee2cc3f
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177379512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 9.chip_padctrl_attributes.1177379512
Directory /workspace/9.chip_padctrl_attributes/latest
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