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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.21 95.58 94.17 95.38 95.01 97.53 99.60


Total test records in report: 2944
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T876 /workspace/coverage/default/3.chip_tap_straps_prod.1791464058 Aug 05 08:34:46 PM PDT 24 Aug 05 08:37:31 PM PDT 24 2368423872 ps
T877 /workspace/coverage/default/0.chip_sw_hmac_smoketest.1467423141 Aug 05 08:09:14 PM PDT 24 Aug 05 08:14:58 PM PDT 24 3028777448 ps
T236 /workspace/coverage/default/23.chip_sw_all_escalation_resets.185651885 Aug 05 08:37:17 PM PDT 24 Aug 05 08:46:36 PM PDT 24 5732607230 ps
T219 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2570004971 Aug 05 08:17:44 PM PDT 24 Aug 05 08:51:46 PM PDT 24 10755632880 ps
T321 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.223509793 Aug 05 08:12:49 PM PDT 24 Aug 05 08:24:14 PM PDT 24 3666791008 ps
T296 /workspace/coverage/default/1.chip_plic_all_irqs_0.1486551156 Aug 05 08:16:43 PM PDT 24 Aug 05 08:39:02 PM PDT 24 5709472500 ps
T878 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.772177700 Aug 05 08:28:54 PM PDT 24 Aug 05 08:47:41 PM PDT 24 6954217304 ps
T326 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2521797765 Aug 05 08:22:29 PM PDT 24 Aug 05 08:55:10 PM PDT 24 8840299348 ps
T86 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.2716496248 Aug 05 08:18:01 PM PDT 24 Aug 05 08:23:39 PM PDT 24 3477505745 ps
T630 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2331171298 Aug 05 08:19:28 PM PDT 24 Aug 05 08:27:29 PM PDT 24 4650035066 ps
T879 /workspace/coverage/default/2.chip_sw_edn_sw_mode.756770585 Aug 05 08:25:42 PM PDT 24 Aug 05 09:02:01 PM PDT 24 11017524784 ps
T880 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3139441052 Aug 05 08:28:03 PM PDT 24 Aug 05 08:37:36 PM PDT 24 5281146608 ps
T73 /workspace/coverage/default/3.chip_tap_straps_testunlock0.3966632633 Aug 05 08:33:06 PM PDT 24 Aug 05 08:48:13 PM PDT 24 8121109872 ps
T881 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.21392812 Aug 05 08:16:54 PM PDT 24 Aug 05 09:00:58 PM PDT 24 27350178819 ps
T882 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2932575516 Aug 05 08:13:46 PM PDT 24 Aug 05 09:15:14 PM PDT 24 14599189140 ps
T883 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1010727006 Aug 05 08:07:09 PM PDT 24 Aug 05 08:39:33 PM PDT 24 22875203472 ps
T222 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3628633803 Aug 05 08:26:30 PM PDT 24 Aug 05 09:32:43 PM PDT 24 16130611992 ps
T884 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2162723232 Aug 05 08:03:50 PM PDT 24 Aug 05 08:11:34 PM PDT 24 18588432360 ps
T885 /workspace/coverage/default/1.chip_sw_hmac_smoketest.3769647575 Aug 05 08:28:24 PM PDT 24 Aug 05 08:36:00 PM PDT 24 3522463164 ps
T664 /workspace/coverage/default/20.chip_sw_all_escalation_resets.2928399658 Aug 05 08:39:22 PM PDT 24 Aug 05 08:47:36 PM PDT 24 5450278040 ps
T421 /workspace/coverage/default/2.chip_sw_edn_auto_mode.3627087352 Aug 05 08:26:41 PM PDT 24 Aug 05 08:47:34 PM PDT 24 5810040196 ps
T725 /workspace/coverage/default/17.chip_sw_all_escalation_resets.3221348841 Aug 05 08:38:06 PM PDT 24 Aug 05 08:50:24 PM PDT 24 4900385004 ps
T13 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2867398977 Aug 05 08:03:21 PM PDT 24 Aug 05 08:08:29 PM PDT 24 3428642232 ps
T886 /workspace/coverage/default/1.chip_tap_straps_dev.2330314749 Aug 05 08:17:49 PM PDT 24 Aug 05 08:20:40 PM PDT 24 3150888199 ps
T336 /workspace/coverage/default/61.chip_sw_all_escalation_resets.2452891871 Aug 05 08:40:27 PM PDT 24 Aug 05 08:49:40 PM PDT 24 5090781060 ps
T887 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1567286368 Aug 05 08:24:45 PM PDT 24 Aug 05 09:05:53 PM PDT 24 22193309613 ps
T741 /workspace/coverage/default/98.chip_sw_all_escalation_resets.1781497793 Aug 05 08:43:04 PM PDT 24 Aug 05 08:54:06 PM PDT 24 5938628690 ps
T888 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.30477748 Aug 05 08:28:27 PM PDT 24 Aug 05 08:31:20 PM PDT 24 2805718654 ps
T889 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2289132733 Aug 05 08:10:47 PM PDT 24 Aug 05 08:29:06 PM PDT 24 6811855576 ps
T890 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.821834425 Aug 05 08:06:32 PM PDT 24 Aug 05 08:43:44 PM PDT 24 10225184900 ps
T180 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3488026230 Aug 05 08:28:15 PM PDT 24 Aug 05 08:40:43 PM PDT 24 8337097020 ps
T170 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.627845732 Aug 05 08:13:09 PM PDT 24 Aug 05 09:41:50 PM PDT 24 50946236600 ps
T891 /workspace/coverage/default/2.rom_e2e_self_hash.2697559425 Aug 05 08:35:40 PM PDT 24 Aug 05 10:01:00 PM PDT 24 25772562220 ps
T892 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1354725957 Aug 05 08:28:34 PM PDT 24 Aug 05 08:36:52 PM PDT 24 5130307380 ps
T893 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.4395859 Aug 05 08:19:18 PM PDT 24 Aug 05 08:25:49 PM PDT 24 3645496646 ps
T254 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1770944306 Aug 05 08:15:55 PM PDT 24 Aug 05 09:07:43 PM PDT 24 14832640810 ps
T894 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.762686761 Aug 05 08:18:36 PM PDT 24 Aug 05 08:29:04 PM PDT 24 4669534834 ps
T682 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1729398901 Aug 05 08:35:55 PM PDT 24 Aug 05 08:42:25 PM PDT 24 3389243960 ps
T101 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.602912047 Aug 05 08:04:55 PM PDT 24 Aug 05 08:12:43 PM PDT 24 7570843180 ps
T338 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1867763396 Aug 05 08:14:27 PM PDT 24 Aug 05 09:03:51 PM PDT 24 37722852656 ps
T895 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3647802443 Aug 05 08:28:44 PM PDT 24 Aug 05 08:40:17 PM PDT 24 5707667068 ps
T896 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1189274011 Aug 05 08:13:28 PM PDT 24 Aug 05 09:15:41 PM PDT 24 15691213236 ps
T722 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1237164092 Aug 05 08:43:38 PM PDT 24 Aug 05 08:49:15 PM PDT 24 3766875488 ps
T156 /workspace/coverage/default/1.chip_plic_all_irqs_10.1192530596 Aug 05 08:17:43 PM PDT 24 Aug 05 08:28:28 PM PDT 24 4930901768 ps
T897 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.806403749 Aug 05 08:12:09 PM PDT 24 Aug 05 08:20:24 PM PDT 24 3812943856 ps
T294 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2890241669 Aug 05 08:35:48 PM PDT 24 Aug 05 08:44:41 PM PDT 24 4427775200 ps
T74 /workspace/coverage/default/0.chip_tap_straps_dev.1000981893 Aug 05 08:04:00 PM PDT 24 Aug 05 08:29:20 PM PDT 24 14829631217 ps
T898 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2308183189 Aug 05 08:30:12 PM PDT 24 Aug 05 09:21:24 PM PDT 24 14653835313 ps
T760 /workspace/coverage/default/7.chip_sw_all_escalation_resets.2335989897 Aug 05 08:34:51 PM PDT 24 Aug 05 08:46:19 PM PDT 24 4917130098 ps
T89 /workspace/coverage/default/0.chip_sw_all_escalation_resets.1062275959 Aug 05 08:02:03 PM PDT 24 Aug 05 08:10:06 PM PDT 24 5035750144 ps
T304 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3826102257 Aug 05 08:06:23 PM PDT 24 Aug 05 08:21:12 PM PDT 24 5453100688 ps
T899 /workspace/coverage/default/2.chip_sw_aes_enc.176434028 Aug 05 08:26:33 PM PDT 24 Aug 05 08:32:11 PM PDT 24 3315738608 ps
T773 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3653463184 Aug 05 08:41:56 PM PDT 24 Aug 05 08:48:08 PM PDT 24 3955745036 ps
T900 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1168854619 Aug 05 08:02:35 PM PDT 24 Aug 05 08:11:21 PM PDT 24 4637792288 ps
T901 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1432562113 Aug 05 08:25:39 PM PDT 24 Aug 05 08:36:19 PM PDT 24 6137875542 ps
T177 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2860457221 Aug 05 08:11:30 PM PDT 24 Aug 05 08:54:17 PM PDT 24 24210957751 ps
T902 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.3336229217 Aug 05 08:31:02 PM PDT 24 Aug 05 08:35:34 PM PDT 24 2426826436 ps
T903 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1145321795 Aug 05 08:04:58 PM PDT 24 Aug 05 08:11:48 PM PDT 24 4228600798 ps
T706 /workspace/coverage/default/55.chip_sw_all_escalation_resets.1711338167 Aug 05 08:41:19 PM PDT 24 Aug 05 08:55:03 PM PDT 24 6257472232 ps
T255 /workspace/coverage/default/0.rom_volatile_raw_unlock.3717671842 Aug 05 08:10:04 PM PDT 24 Aug 05 08:12:30 PM PDT 24 2891588312 ps
T419 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3408851646 Aug 05 08:16:08 PM PDT 24 Aug 05 08:29:46 PM PDT 24 6553857019 ps
T295 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3435035873 Aug 05 08:39:15 PM PDT 24 Aug 05 08:59:35 PM PDT 24 8371177630 ps
T303 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3789608577 Aug 05 08:17:11 PM PDT 24 Aug 05 08:45:08 PM PDT 24 7364982472 ps
T904 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1789569182 Aug 05 08:24:50 PM PDT 24 Aug 05 09:22:41 PM PDT 24 15120203288 ps
T22 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.4091395793 Aug 05 08:25:28 PM PDT 24 Aug 05 08:52:50 PM PDT 24 23409457512 ps
T905 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.353188592 Aug 05 08:16:28 PM PDT 24 Aug 05 08:19:44 PM PDT 24 2179061600 ps
T29 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3842940844 Aug 05 08:21:41 PM PDT 24 Aug 05 08:27:01 PM PDT 24 3091461160 ps
T665 /workspace/coverage/default/75.chip_sw_all_escalation_resets.273993841 Aug 05 08:41:20 PM PDT 24 Aug 05 08:50:34 PM PDT 24 4956814622 ps
T9 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2518798220 Aug 05 08:12:58 PM PDT 24 Aug 05 08:17:26 PM PDT 24 3424803079 ps
T130 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.4134466332 Aug 05 08:27:54 PM PDT 24 Aug 05 08:40:01 PM PDT 24 6852947868 ps
T906 /workspace/coverage/default/2.chip_sw_power_sleep_load.1772417351 Aug 05 08:32:41 PM PDT 24 Aug 05 08:42:18 PM PDT 24 9909190888 ps
T733 /workspace/coverage/default/90.chip_sw_all_escalation_resets.2466508311 Aug 05 08:42:27 PM PDT 24 Aug 05 08:52:55 PM PDT 24 5947591760 ps
T738 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1258532394 Aug 05 08:38:11 PM PDT 24 Aug 05 08:46:13 PM PDT 24 4022730138 ps
T907 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.1352400413 Aug 05 08:04:11 PM PDT 24 Aug 05 08:46:12 PM PDT 24 7979125394 ps
T908 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.511119834 Aug 05 08:33:39 PM PDT 24 Aug 05 08:45:22 PM PDT 24 4432000306 ps
T418 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.1175286698 Aug 05 08:25:18 PM PDT 24 Aug 05 08:30:57 PM PDT 24 2857564983 ps
T261 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3957402042 Aug 05 08:27:19 PM PDT 24 Aug 05 08:37:02 PM PDT 24 4644745687 ps
T909 /workspace/coverage/default/0.rom_e2e_self_hash.3314714742 Aug 05 08:13:17 PM PDT 24 Aug 05 09:52:46 PM PDT 24 25965453900 ps
T209 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.439904315 Aug 05 08:02:27 PM PDT 24 Aug 05 08:08:03 PM PDT 24 2748604250 ps
T910 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3531559242 Aug 05 08:18:07 PM PDT 24 Aug 05 08:38:38 PM PDT 24 7033665896 ps
T911 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2104753978 Aug 05 08:36:13 PM PDT 24 Aug 05 08:46:21 PM PDT 24 5707557505 ps
T23 /workspace/coverage/default/0.chip_sw_usbdev_config_host.198437349 Aug 05 08:03:16 PM PDT 24 Aug 05 08:34:21 PM PDT 24 7572168948 ps
T912 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1041667470 Aug 05 08:09:49 PM PDT 24 Aug 05 08:14:23 PM PDT 24 3320359620 ps
T285 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1912092300 Aug 05 08:07:01 PM PDT 24 Aug 05 08:14:26 PM PDT 24 4780899400 ps
T913 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2725872089 Aug 05 08:07:24 PM PDT 24 Aug 05 08:13:41 PM PDT 24 2858740866 ps
T726 /workspace/coverage/default/40.chip_sw_all_escalation_resets.3921845339 Aug 05 08:39:55 PM PDT 24 Aug 05 08:49:31 PM PDT 24 6066699248 ps
T702 /workspace/coverage/default/54.chip_sw_all_escalation_resets.1068595702 Aug 05 08:40:33 PM PDT 24 Aug 05 08:49:52 PM PDT 24 6449849480 ps
T914 /workspace/coverage/default/0.chip_sw_hmac_multistream.3115194234 Aug 05 08:03:37 PM PDT 24 Aug 05 08:38:48 PM PDT 24 8928667656 ps
T915 /workspace/coverage/default/1.chip_sw_csrng_kat_test.2247329929 Aug 05 08:19:41 PM PDT 24 Aug 05 08:24:17 PM PDT 24 2468627860 ps
T160 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.948494987 Aug 05 08:13:29 PM PDT 24 Aug 05 08:14:55 PM PDT 24 2022251438 ps
T916 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.892235410 Aug 05 08:27:42 PM PDT 24 Aug 05 08:37:01 PM PDT 24 7318641120 ps
T766 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4265205704 Aug 05 08:42:44 PM PDT 24 Aug 05 08:48:17 PM PDT 24 3604818344 ps
T917 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3137079662 Aug 05 08:24:29 PM PDT 24 Aug 05 08:45:01 PM PDT 24 5887360861 ps
T225 /workspace/coverage/default/0.chip_sw_flash_init.1621556129 Aug 05 08:01:08 PM PDT 24 Aug 05 08:38:17 PM PDT 24 21471005108 ps
T505 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1673470097 Aug 05 08:05:19 PM PDT 24 Aug 05 08:35:00 PM PDT 24 11214736903 ps
T918 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1509344856 Aug 05 08:16:33 PM PDT 24 Aug 05 08:31:38 PM PDT 24 11433746744 ps
T680 /workspace/coverage/default/15.chip_sw_all_escalation_resets.3116690596 Aug 05 08:37:02 PM PDT 24 Aug 05 08:48:49 PM PDT 24 4956320252 ps
T767 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2861081472 Aug 05 08:40:34 PM PDT 24 Aug 05 08:46:29 PM PDT 24 4452792264 ps
T151 /workspace/coverage/default/1.rom_raw_unlock.451238141 Aug 05 08:21:21 PM PDT 24 Aug 05 08:26:15 PM PDT 24 5902892812 ps
T919 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.902647682 Aug 05 08:21:03 PM PDT 24 Aug 05 08:27:27 PM PDT 24 2710266240 ps
T920 /workspace/coverage/default/0.chip_sw_otbn_randomness.4277961018 Aug 05 08:02:41 PM PDT 24 Aug 05 08:18:12 PM PDT 24 5827308154 ps
T921 /workspace/coverage/default/1.chip_sw_rv_timer_irq.45275451 Aug 05 08:13:02 PM PDT 24 Aug 05 08:16:37 PM PDT 24 3142861400 ps
T743 /workspace/coverage/default/10.chip_sw_all_escalation_resets.3577332017 Aug 05 08:35:42 PM PDT 24 Aug 05 08:46:43 PM PDT 24 5707989730 ps
T727 /workspace/coverage/default/3.chip_sw_all_escalation_resets.2687602991 Aug 05 08:32:08 PM PDT 24 Aug 05 08:42:57 PM PDT 24 5952301450 ps
T922 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.902364701 Aug 05 08:17:34 PM PDT 24 Aug 05 08:28:15 PM PDT 24 5857370905 ps
T923 /workspace/coverage/default/0.chip_sw_aes_masking_off.2715780535 Aug 05 08:04:17 PM PDT 24 Aug 05 08:08:28 PM PDT 24 2651428485 ps
T745 /workspace/coverage/default/67.chip_sw_all_escalation_resets.2791900599 Aug 05 08:42:42 PM PDT 24 Aug 05 08:51:17 PM PDT 24 4423307100 ps
T220 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.12535163 Aug 05 08:05:25 PM PDT 24 Aug 05 08:26:31 PM PDT 24 6367932832 ps
T125 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3048201324 Aug 05 08:18:06 PM PDT 24 Aug 05 08:28:57 PM PDT 24 4984800656 ps
T924 /workspace/coverage/default/1.chip_sw_example_concurrency.2494963433 Aug 05 08:10:01 PM PDT 24 Aug 05 08:14:47 PM PDT 24 2693863718 ps
T694 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4063851277 Aug 05 08:37:07 PM PDT 24 Aug 05 08:44:36 PM PDT 24 4107421130 ps
T925 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.2868722890 Aug 05 08:18:33 PM PDT 24 Aug 05 08:24:21 PM PDT 24 3447495192 ps
T693 /workspace/coverage/default/83.chip_sw_all_escalation_resets.2747449808 Aug 05 08:43:55 PM PDT 24 Aug 05 08:56:11 PM PDT 24 4948988980 ps
T329 /workspace/coverage/default/87.chip_sw_all_escalation_resets.3941397729 Aug 05 08:42:22 PM PDT 24 Aug 05 08:52:13 PM PDT 24 4738142796 ps
T55 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3832551608 Aug 05 08:12:57 PM PDT 24 Aug 05 08:18:15 PM PDT 24 3433671100 ps
T61 /workspace/coverage/default/4.chip_tap_straps_rma.1874499434 Aug 05 08:33:41 PM PDT 24 Aug 05 08:36:45 PM PDT 24 3239523725 ps
T243 /workspace/coverage/default/0.chip_sw_power_sleep_load.3113058480 Aug 05 08:05:56 PM PDT 24 Aug 05 08:12:01 PM PDT 24 4482153092 ps
T926 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1887452128 Aug 05 08:10:50 PM PDT 24 Aug 05 09:11:30 PM PDT 24 15551476496 ps
T927 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.396048357 Aug 05 08:27:10 PM PDT 24 Aug 05 08:33:08 PM PDT 24 3380203726 ps
T674 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3081900023 Aug 05 08:41:05 PM PDT 24 Aug 05 08:48:42 PM PDT 24 3691993468 ps
T928 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.15266967 Aug 05 08:29:04 PM PDT 24 Aug 05 08:37:01 PM PDT 24 4458070552 ps
T422 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.4081971011 Aug 05 08:26:37 PM PDT 24 Aug 05 09:04:00 PM PDT 24 10147636712 ps
T929 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2991967105 Aug 05 08:03:58 PM PDT 24 Aug 05 08:22:15 PM PDT 24 11891759129 ps
T930 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3139013013 Aug 05 08:02:32 PM PDT 24 Aug 05 08:08:05 PM PDT 24 3474203102 ps
T931 /workspace/coverage/default/2.chip_sw_otbn_randomness.3866810585 Aug 05 08:25:44 PM PDT 24 Aug 05 08:43:25 PM PDT 24 5973455608 ps
T707 /workspace/coverage/default/94.chip_sw_all_escalation_resets.1553519983 Aug 05 08:44:21 PM PDT 24 Aug 05 08:53:53 PM PDT 24 5667416758 ps
T932 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1775654737 Aug 05 08:03:01 PM PDT 24 Aug 05 08:11:53 PM PDT 24 3634446801 ps
T162 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2565436750 Aug 05 08:03:25 PM PDT 24 Aug 05 08:07:09 PM PDT 24 2751814629 ps
T933 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1087282438 Aug 05 08:19:13 PM PDT 24 Aug 05 08:37:08 PM PDT 24 12904627523 ps
T166 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.653475429 Aug 05 08:29:19 PM PDT 24 Aug 05 08:36:57 PM PDT 24 4499694574 ps
T934 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.4090617506 Aug 05 08:28:19 PM PDT 24 Aug 05 08:55:01 PM PDT 24 7850506360 ps
T935 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3276780277 Aug 05 08:29:34 PM PDT 24 Aug 05 08:36:35 PM PDT 24 5351709228 ps
T189 /workspace/coverage/default/0.chip_sw_power_virus.1484833663 Aug 05 08:10:55 PM PDT 24 Aug 05 08:35:54 PM PDT 24 6106016600 ps
T936 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3665102288 Aug 05 08:18:28 PM PDT 24 Aug 05 08:25:43 PM PDT 24 6650702610 ps
T937 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2685329996 Aug 05 08:02:22 PM PDT 24 Aug 05 08:26:23 PM PDT 24 9304662220 ps
T226 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3182886940 Aug 05 08:03:01 PM PDT 24 Aug 05 09:35:49 PM PDT 24 45863092458 ps
T716 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.431767489 Aug 05 08:43:09 PM PDT 24 Aug 05 08:50:24 PM PDT 24 3784326316 ps
T717 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1772812259 Aug 05 08:40:01 PM PDT 24 Aug 05 08:45:41 PM PDT 24 3417793388 ps
T420 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2118472998 Aug 05 08:26:39 PM PDT 24 Aug 05 08:51:46 PM PDT 24 7508321076 ps
T938 /workspace/coverage/default/1.chip_sw_kmac_idle.1857220120 Aug 05 08:16:15 PM PDT 24 Aug 05 08:19:57 PM PDT 24 2177503880 ps
T939 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.522020617 Aug 05 08:24:22 PM PDT 24 Aug 05 08:32:21 PM PDT 24 4113739000 ps
T728 /workspace/coverage/default/36.chip_sw_all_escalation_resets.4136487068 Aug 05 08:38:49 PM PDT 24 Aug 05 08:48:26 PM PDT 24 5453750330 ps
T940 /workspace/coverage/default/2.chip_sw_otbn_smoketest.1823713027 Aug 05 08:33:07 PM PDT 24 Aug 05 09:01:08 PM PDT 24 9466772624 ps
T683 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1234547838 Aug 05 08:39:19 PM PDT 24 Aug 05 08:47:25 PM PDT 24 3613942932 ps
T501 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3449901697 Aug 05 08:26:26 PM PDT 24 Aug 05 08:43:15 PM PDT 24 4892271872 ps
T941 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2771256638 Aug 05 08:27:06 PM PDT 24 Aug 05 08:46:46 PM PDT 24 14136584183 ps
T942 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1626756898 Aug 05 08:07:15 PM PDT 24 Aug 05 08:10:59 PM PDT 24 3095039400 ps
T943 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.3707112948 Aug 05 08:16:29 PM PDT 24 Aug 05 08:25:15 PM PDT 24 4729009590 ps
T102 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.558779600 Aug 05 08:18:21 PM PDT 24 Aug 05 08:26:18 PM PDT 24 7321667540 ps
T944 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.4137580576 Aug 05 08:14:30 PM PDT 24 Aug 05 09:20:45 PM PDT 24 20635923350 ps
T676 /workspace/coverage/default/25.chip_sw_all_escalation_resets.4112038286 Aug 05 08:36:45 PM PDT 24 Aug 05 08:49:21 PM PDT 24 5833634064 ps
T945 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.130415003 Aug 05 08:06:27 PM PDT 24 Aug 05 08:10:29 PM PDT 24 3073141216 ps
T946 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2521435865 Aug 05 08:09:52 PM PDT 24 Aug 05 09:05:16 PM PDT 24 11068846244 ps
T751 /workspace/coverage/default/48.chip_sw_all_escalation_resets.2048861972 Aug 05 08:40:00 PM PDT 24 Aug 05 08:50:18 PM PDT 24 5778342164 ps
T759 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1358031316 Aug 05 08:38:41 PM PDT 24 Aug 05 08:46:53 PM PDT 24 3626822260 ps
T698 /workspace/coverage/default/26.chip_sw_all_escalation_resets.3397363635 Aug 05 08:37:58 PM PDT 24 Aug 05 08:49:01 PM PDT 24 5267941220 ps
T947 /workspace/coverage/default/1.chip_sw_power_sleep_load.752050070 Aug 05 08:20:43 PM PDT 24 Aug 05 08:30:49 PM PDT 24 9878486854 ps
T948 /workspace/coverage/default/2.chip_sw_uart_tx_rx.1992504509 Aug 05 08:22:09 PM PDT 24 Aug 05 08:35:14 PM PDT 24 4058461312 ps
T90 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1633047484 Aug 05 08:39:46 PM PDT 24 Aug 05 08:46:41 PM PDT 24 3992454700 ps
T949 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2062643319 Aug 05 08:04:16 PM PDT 24 Aug 05 08:10:06 PM PDT 24 4586445272 ps
T126 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3770674358 Aug 05 08:03:56 PM PDT 24 Aug 05 08:13:41 PM PDT 24 4157337682 ps
T950 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.4276388988 Aug 05 08:38:03 PM PDT 24 Aug 05 08:47:26 PM PDT 24 3872611662 ps
T502 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1424833192 Aug 05 08:08:33 PM PDT 24 Aug 05 08:22:46 PM PDT 24 4637408704 ps
T322 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3520022091 Aug 05 08:04:27 PM PDT 24 Aug 05 08:15:25 PM PDT 24 3920263107 ps
T951 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1615867744 Aug 05 08:33:10 PM PDT 24 Aug 05 09:11:24 PM PDT 24 13589754260 ps
T184 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.633306624 Aug 05 08:15:27 PM PDT 24 Aug 05 08:25:25 PM PDT 24 4654986110 ps
T952 /workspace/coverage/default/1.chip_sw_edn_kat.3291496401 Aug 05 08:18:23 PM PDT 24 Aug 05 08:28:13 PM PDT 24 3904398156 ps
T953 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3654529640 Aug 05 08:10:46 PM PDT 24 Aug 05 09:10:35 PM PDT 24 14283036492 ps
T339 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1077690727 Aug 05 08:23:58 PM PDT 24 Aug 05 08:31:29 PM PDT 24 2853301260 ps
T954 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2482584424 Aug 05 08:04:56 PM PDT 24 Aug 05 08:21:39 PM PDT 24 8234088614 ps
T127 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4069597991 Aug 05 08:04:49 PM PDT 24 Aug 05 08:13:52 PM PDT 24 3928680950 ps
T735 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4251648389 Aug 05 08:38:53 PM PDT 24 Aug 05 08:45:30 PM PDT 24 3503341384 ps
T955 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.4063932150 Aug 05 08:18:36 PM PDT 24 Aug 05 08:45:54 PM PDT 24 8752291560 ps
T956 /workspace/coverage/default/0.chip_sw_hmac_oneshot.1502843578 Aug 05 08:04:36 PM PDT 24 Aug 05 08:08:40 PM PDT 24 2481925050 ps
T957 /workspace/coverage/default/2.chip_sw_hmac_multistream.495131429 Aug 05 08:26:30 PM PDT 24 Aug 05 08:58:00 PM PDT 24 9023582086 ps
T958 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3151956767 Aug 05 08:33:26 PM PDT 24 Aug 05 08:52:55 PM PDT 24 6110728592 ps
T959 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1415879291 Aug 05 08:34:02 PM PDT 24 Aug 05 08:38:51 PM PDT 24 2931850620 ps
T960 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.2921899926 Aug 05 08:05:51 PM PDT 24 Aug 05 08:46:07 PM PDT 24 9739290890 ps
T961 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3188559242 Aug 05 08:31:01 PM PDT 24 Aug 05 08:35:35 PM PDT 24 3125550447 ps
T962 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1385412691 Aug 05 08:37:57 PM PDT 24 Aug 05 09:18:22 PM PDT 24 10640788320 ps
T963 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2181752803 Aug 05 08:06:55 PM PDT 24 Aug 05 08:17:19 PM PDT 24 4681752884 ps
T964 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.4285871112 Aug 05 08:17:59 PM PDT 24 Aug 05 08:22:03 PM PDT 24 2591222932 ps
T965 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2205651735 Aug 05 08:09:47 PM PDT 24 Aug 05 08:15:30 PM PDT 24 5762229444 ps
T633 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.11471836 Aug 05 08:02:45 PM PDT 24 Aug 05 08:04:34 PM PDT 24 2742454708 ps
T966 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.488689480 Aug 05 08:11:26 PM PDT 24 Aug 05 09:36:53 PM PDT 24 22851867282 ps
T774 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2656543451 Aug 05 08:25:18 PM PDT 24 Aug 05 08:32:46 PM PDT 24 4014741672 ps
T967 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2291788170 Aug 05 08:12:02 PM PDT 24 Aug 05 09:44:41 PM PDT 24 42547260496 ps
T968 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.866482534 Aug 05 08:36:30 PM PDT 24 Aug 05 09:32:55 PM PDT 24 14691297136 ps
T969 /workspace/coverage/default/0.chip_sw_aes_entropy.730781368 Aug 05 08:04:58 PM PDT 24 Aug 05 08:09:25 PM PDT 24 3286278968 ps
T70 /workspace/coverage/default/1.chip_tap_straps_testunlock0.2116305656 Aug 05 08:17:30 PM PDT 24 Aug 05 08:21:47 PM PDT 24 4018755046 ps
T970 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3116209034 Aug 05 08:29:01 PM PDT 24 Aug 05 08:34:06 PM PDT 24 3266670870 ps
T185 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3456217815 Aug 05 08:26:19 PM PDT 24 Aug 05 08:33:09 PM PDT 24 4115180648 ps
T167 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.392689320 Aug 05 08:18:50 PM PDT 24 Aug 05 08:28:50 PM PDT 24 4569481092 ps
T755 /workspace/coverage/default/66.chip_sw_all_escalation_resets.2897957736 Aug 05 08:41:52 PM PDT 24 Aug 05 08:51:45 PM PDT 24 5461595836 ps
T971 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.437262084 Aug 05 08:04:38 PM PDT 24 Aug 05 08:08:05 PM PDT 24 2413506416 ps
T410 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.183694512 Aug 05 08:12:25 PM PDT 24 Aug 05 08:53:13 PM PDT 24 33350344256 ps
T747 /workspace/coverage/default/72.chip_sw_all_escalation_resets.110011297 Aug 05 08:41:22 PM PDT 24 Aug 05 08:52:06 PM PDT 24 5803395684 ps
T81 /workspace/coverage/default/1.chip_jtag_csr_rw.1853864280 Aug 05 08:11:31 PM PDT 24 Aug 05 08:33:20 PM PDT 24 9857486192 ps
T197 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3779933030 Aug 05 08:01:56 PM PDT 24 Aug 05 08:10:32 PM PDT 24 4453418679 ps
T621 /workspace/coverage/default/0.chip_sw_edn_boot_mode.1866256025 Aug 05 08:06:26 PM PDT 24 Aug 05 08:15:22 PM PDT 24 2743905500 ps
T972 /workspace/coverage/default/14.chip_sw_all_escalation_resets.167146585 Aug 05 08:37:05 PM PDT 24 Aug 05 08:54:34 PM PDT 24 6260254200 ps
T973 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3971709627 Aug 05 08:29:26 PM PDT 24 Aug 05 08:32:29 PM PDT 24 2911286726 ps
T974 /workspace/coverage/default/1.chip_sw_power_idle_load.1586715899 Aug 05 08:19:39 PM PDT 24 Aug 05 08:31:04 PM PDT 24 4094079266 ps
T282 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.813354283 Aug 05 08:18:47 PM PDT 24 Aug 05 08:28:32 PM PDT 24 6673092452 ps
T306 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3835413991 Aug 05 08:03:16 PM PDT 24 Aug 05 08:36:05 PM PDT 24 8165138597 ps
T975 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2360956987 Aug 05 08:13:21 PM PDT 24 Aug 05 08:34:49 PM PDT 24 8441365692 ps
T47 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.539811071 Aug 05 08:11:55 PM PDT 24 Aug 05 08:16:48 PM PDT 24 2782122440 ps
T228 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3355767231 Aug 05 08:30:10 PM PDT 24 Aug 05 09:07:19 PM PDT 24 25073135525 ps
T227 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3762693561 Aug 05 08:05:30 PM PDT 24 Aug 05 09:43:40 PM PDT 24 48507520616 ps
T976 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2280826605 Aug 05 08:04:52 PM PDT 24 Aug 05 09:09:22 PM PDT 24 18742127244 ps
T753 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2671561102 Aug 05 08:35:53 PM PDT 24 Aug 05 08:42:12 PM PDT 24 4068113112 ps
T52 /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2551400931 Aug 05 08:23:32 PM PDT 24 Aug 05 08:28:57 PM PDT 24 3826660139 ps
T749 /workspace/coverage/default/13.chip_sw_all_escalation_resets.1310395223 Aug 05 08:36:59 PM PDT 24 Aug 05 08:48:39 PM PDT 24 5553133936 ps
T977 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2407230391 Aug 05 08:38:09 PM PDT 24 Aug 05 08:42:56 PM PDT 24 2576295582 ps
T978 /workspace/coverage/default/2.chip_sw_example_manufacturer.449533116 Aug 05 08:21:26 PM PDT 24 Aug 05 08:25:06 PM PDT 24 2420295288 ps
T327 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1255188603 Aug 05 08:22:20 PM PDT 24 Aug 05 08:37:07 PM PDT 24 5401670640 ps
T979 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3139409770 Aug 05 08:36:51 PM PDT 24 Aug 05 09:30:10 PM PDT 24 15454922900 ps
T980 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.2009037290 Aug 05 08:01:57 PM PDT 24 Aug 05 08:21:10 PM PDT 24 5092945272 ps
T981 /workspace/coverage/default/0.rom_e2e_asm_init_rma.203722628 Aug 05 08:14:31 PM PDT 24 Aug 05 09:16:15 PM PDT 24 14746655865 ps
T634 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.124059082 Aug 05 08:11:44 PM PDT 24 Aug 05 08:13:27 PM PDT 24 3129077082 ps
T711 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2086114412 Aug 05 08:39:55 PM PDT 24 Aug 05 08:47:05 PM PDT 24 3858073096 ps
T262 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.956406979 Aug 05 08:05:47 PM PDT 24 Aug 05 08:13:57 PM PDT 24 4568263535 ps
T982 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.949820422 Aug 05 08:27:11 PM PDT 24 Aug 05 08:52:35 PM PDT 24 14153820330 ps
T983 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2639699958 Aug 05 08:12:13 PM PDT 24 Aug 05 08:42:54 PM PDT 24 8626106200 ps
T984 /workspace/coverage/default/5.chip_sw_all_escalation_resets.494576135 Aug 05 08:33:46 PM PDT 24 Aug 05 08:47:11 PM PDT 24 4944723496 ps
T229 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3988638253 Aug 05 08:23:14 PM PDT 24 Aug 05 09:49:25 PM PDT 24 48913006210 ps
T62 /workspace/coverage/default/1.chip_tap_straps_rma.3255925853 Aug 05 08:18:03 PM PDT 24 Aug 05 08:26:47 PM PDT 24 6205833840 ps
T985 /workspace/coverage/default/0.chip_sw_edn_auto_mode.1667849584 Aug 05 08:03:45 PM PDT 24 Aug 05 08:34:59 PM PDT 24 5517159592 ps
T986 /workspace/coverage/default/1.chip_sw_uart_smoketest.4180940921 Aug 05 08:20:44 PM PDT 24 Aug 05 08:24:26 PM PDT 24 3060897112 ps
T638 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1927014951 Aug 05 08:05:36 PM PDT 24 Aug 05 08:10:03 PM PDT 24 2973533700 ps
T503 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2175482294 Aug 05 08:16:28 PM PDT 24 Aug 05 08:30:14 PM PDT 24 5134684048 ps
T198 /workspace/coverage/default/1.chip_sw_power_virus.2353188439 Aug 05 08:25:14 PM PDT 24 Aug 05 08:48:08 PM PDT 24 5962794312 ps
T246 /workspace/coverage/default/9.chip_sw_all_escalation_resets.3433188222 Aug 05 08:35:22 PM PDT 24 Aug 05 08:44:55 PM PDT 24 4445237900 ps
T987 /workspace/coverage/default/0.chip_sw_hmac_enc.1183665389 Aug 05 08:04:04 PM PDT 24 Aug 05 08:07:45 PM PDT 24 2165588362 ps
T988 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2550464513 Aug 05 08:04:12 PM PDT 24 Aug 05 08:08:00 PM PDT 24 2846179192 ps
T989 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3292753285 Aug 05 08:30:54 PM PDT 24 Aug 05 08:54:42 PM PDT 24 7187975900 ps
T990 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2729006049 Aug 05 08:21:32 PM PDT 24 Aug 05 08:25:27 PM PDT 24 3331849788 ps
T991 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3855048542 Aug 05 08:30:58 PM PDT 24 Aug 05 08:56:36 PM PDT 24 10411116597 ps
T312 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.109511887 Aug 05 08:12:58 PM PDT 24 Aug 05 08:20:05 PM PDT 24 3988777768 ps
T992 /workspace/coverage/default/2.rom_e2e_asm_init_dev.3824028702 Aug 05 08:35:17 PM PDT 24 Aug 05 09:27:46 PM PDT 24 15233863743 ps
T307 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2643237627 Aug 05 08:21:06 PM PDT 24 Aug 05 08:33:40 PM PDT 24 4501013912 ps
T993 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2410541571 Aug 05 08:15:02 PM PDT 24 Aug 05 08:21:25 PM PDT 24 5052586974 ps
T994 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3604478055 Aug 05 08:29:55 PM PDT 24 Aug 05 08:38:25 PM PDT 24 5326053820 ps
T995 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.958782031 Aug 05 08:06:40 PM PDT 24 Aug 05 08:27:21 PM PDT 24 5950361386 ps
T996 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1748700296 Aug 05 08:13:48 PM PDT 24 Aug 05 09:47:48 PM PDT 24 23175799061 ps
T273 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.4245246349 Aug 05 08:05:29 PM PDT 24 Aug 05 08:09:55 PM PDT 24 2858190793 ps
T75 /workspace/coverage/default/0.chip_sw_usbdev_pullup.3827409379 Aug 05 08:01:53 PM PDT 24 Aug 05 08:05:24 PM PDT 24 2746137450 ps
T708 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.4128243685 Aug 05 08:41:45 PM PDT 24 Aug 05 08:47:39 PM PDT 24 3612941640 ps
T997 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2388442248 Aug 05 08:27:10 PM PDT 24 Aug 05 08:49:51 PM PDT 24 7565188242 ps
T998 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.50210446 Aug 05 08:39:04 PM PDT 24 Aug 05 08:44:52 PM PDT 24 3048332410 ps
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