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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.21 95.58 94.17 95.38 95.01 97.53 99.60


Total test records in report: 2944
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T1330 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4171820082 Aug 05 08:02:54 PM PDT 24 Aug 05 08:55:29 PM PDT 24 37056884280 ps
T1331 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1569488801 Aug 05 08:28:18 PM PDT 24 Aug 05 08:32:25 PM PDT 24 2118258514 ps
T1332 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1028388992 Aug 05 08:42:33 PM PDT 24 Aug 05 08:49:44 PM PDT 24 3714161258 ps
T1333 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1088355393 Aug 05 08:12:37 PM PDT 24 Aug 05 09:31:39 PM PDT 24 18232103276 ps
T1334 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3071696778 Aug 05 08:32:57 PM PDT 24 Aug 05 08:43:05 PM PDT 24 4003394478 ps
T1335 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3104355712 Aug 05 08:11:44 PM PDT 24 Aug 05 11:53:29 PM PDT 24 77753592920 ps
T1336 /workspace/coverage/default/0.chip_sw_example_rom.132379801 Aug 05 08:00:52 PM PDT 24 Aug 05 08:02:40 PM PDT 24 2651240720 ps
T1337 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2457452094 Aug 05 08:13:04 PM PDT 24 Aug 05 08:23:32 PM PDT 24 4240556596 ps
T1338 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2766529590 Aug 05 08:05:12 PM PDT 24 Aug 05 08:15:30 PM PDT 24 7325318524 ps
T93 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.831019454 Aug 05 08:40:42 PM PDT 24 Aug 05 08:46:26 PM PDT 24 3348620760 ps
T1339 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2538398035 Aug 05 08:17:28 PM PDT 24 Aug 05 08:25:05 PM PDT 24 4962378792 ps
T1340 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3823370592 Aug 05 08:03:31 PM PDT 24 Aug 05 11:24:16 PM PDT 24 64814702403 ps
T1341 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3757854829 Aug 05 08:10:52 PM PDT 24 Aug 05 09:07:08 PM PDT 24 14459495886 ps
T1342 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.144801608 Aug 05 08:26:16 PM PDT 24 Aug 05 08:32:55 PM PDT 24 3612158008 ps
T1343 /workspace/coverage/default/1.chip_sw_kmac_smoketest.1932919881 Aug 05 08:29:45 PM PDT 24 Aug 05 08:34:37 PM PDT 24 2546849564 ps
T1344 /workspace/coverage/default/2.chip_sw_hmac_smoketest.2337071073 Aug 05 08:33:26 PM PDT 24 Aug 05 08:42:06 PM PDT 24 3690074300 ps
T1345 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1666042096 Aug 05 08:09:56 PM PDT 24 Aug 05 08:14:08 PM PDT 24 2400309540 ps
T1346 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.632691687 Aug 05 08:22:57 PM PDT 24 Aug 05 08:26:41 PM PDT 24 2510227080 ps
T739 /workspace/coverage/default/88.chip_sw_all_escalation_resets.3766823685 Aug 05 08:42:26 PM PDT 24 Aug 05 08:51:25 PM PDT 24 4782484032 ps
T1347 /workspace/coverage/default/0.chip_tap_straps_prod.2236765152 Aug 05 08:07:52 PM PDT 24 Aug 05 08:39:39 PM PDT 24 16442905416 ps
T1348 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3499646259 Aug 05 08:36:30 PM PDT 24 Aug 05 08:51:04 PM PDT 24 10475647803 ps
T1349 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1672903366 Aug 05 08:28:46 PM PDT 24 Aug 05 08:56:00 PM PDT 24 7595973466 ps
T1350 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1947919891 Aug 05 08:17:10 PM PDT 24 Aug 05 08:29:12 PM PDT 24 8514581656 ps
T1351 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2599587884 Aug 05 08:20:16 PM PDT 24 Aug 05 08:23:47 PM PDT 24 2834149552 ps
T1352 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3473109756 Aug 05 08:04:45 PM PDT 24 Aug 05 08:08:16 PM PDT 24 2730049770 ps
T77 /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.422718563 Aug 05 07:34:41 PM PDT 24 Aug 05 07:35:37 PM PDT 24 3617640734 ps
T78 /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.4251269635 Aug 05 07:41:00 PM PDT 24 Aug 05 07:41:28 PM PDT 24 341410021 ps
T79 /workspace/coverage/cover_reg_top/26.xbar_access_same_device.1348878880 Aug 05 07:41:01 PM PDT 24 Aug 05 07:41:27 PM PDT 24 561172768 ps
T82 /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.2468532813 Aug 05 07:41:01 PM PDT 24 Aug 05 07:41:17 PM PDT 24 104110558 ps
T242 /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.96753251 Aug 05 07:31:59 PM PDT 24 Aug 05 07:41:08 PM PDT 24 13909513220 ps
T153 /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.3636990985 Aug 05 07:47:39 PM PDT 24 Aug 05 07:48:07 PM PDT 24 252913038 ps
T217 /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.491588881 Aug 05 07:53:31 PM PDT 24 Aug 05 07:59:51 PM PDT 24 3737621051 ps
T240 /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.126621548 Aug 05 07:34:02 PM PDT 24 Aug 05 07:37:44 PM PDT 24 637068796 ps
T506 /workspace/coverage/cover_reg_top/75.xbar_access_same_device.1899368812 Aug 05 07:49:51 PM PDT 24 Aug 05 07:50:49 PM PDT 24 1449405459 ps
T517 /workspace/coverage/cover_reg_top/23.xbar_same_source.697994504 Aug 05 07:38:05 PM PDT 24 Aug 05 07:38:14 PM PDT 24 164499280 ps
T513 /workspace/coverage/cover_reg_top/70.xbar_smoke.3522935531 Aug 05 07:48:42 PM PDT 24 Aug 05 07:48:48 PM PDT 24 36710189 ps
T241 /workspace/coverage/cover_reg_top/47.xbar_access_same_device.1875357987 Aug 05 07:44:06 PM PDT 24 Aug 05 07:44:30 PM PDT 24 788560496 ps
T507 /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.3496929629 Aug 05 07:41:19 PM PDT 24 Aug 05 08:01:56 PM PDT 24 75496739284 ps
T509 /workspace/coverage/cover_reg_top/92.xbar_random.1225175523 Aug 05 07:53:08 PM PDT 24 Aug 05 07:53:31 PM PDT 24 250577684 ps
T514 /workspace/coverage/cover_reg_top/45.xbar_random.3451388268 Aug 05 07:43:50 PM PDT 24 Aug 05 07:44:16 PM PDT 24 830107516 ps
T518 /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.493473767 Aug 05 07:50:17 PM PDT 24 Aug 05 07:51:35 PM PDT 24 4685172038 ps
T423 /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.904552401 Aug 05 07:32:11 PM PDT 24 Aug 05 07:35:23 PM PDT 24 2905117399 ps
T403 /workspace/coverage/cover_reg_top/90.xbar_same_source.1574210417 Aug 05 07:52:57 PM PDT 24 Aug 05 07:53:35 PM PDT 24 565930337 ps
T510 /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.4229963818 Aug 05 07:48:19 PM PDT 24 Aug 05 07:52:08 PM PDT 24 6915779536 ps
T405 /workspace/coverage/cover_reg_top/28.xbar_smoke.1393047609 Aug 05 07:41:01 PM PDT 24 Aug 05 07:41:08 PM PDT 24 39995744 ps
T404 /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.787898147 Aug 05 07:50:51 PM PDT 24 Aug 05 08:04:14 PM PDT 24 17067696206 ps
T512 /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.598163419 Aug 05 07:49:32 PM PDT 24 Aug 05 07:50:01 PM PDT 24 752548445 ps
T515 /workspace/coverage/cover_reg_top/67.xbar_access_same_device.2535749839 Aug 05 07:48:21 PM PDT 24 Aug 05 07:49:29 PM PDT 24 914982631 ps
T516 /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.1993754179 Aug 05 07:43:04 PM PDT 24 Aug 05 07:54:34 PM PDT 24 42240982195 ps
T525 /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.2805521657 Aug 05 07:43:39 PM PDT 24 Aug 05 07:57:56 PM PDT 24 84085451164 ps
T810 /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.2614049645 Aug 05 07:41:23 PM PDT 24 Aug 05 07:42:44 PM PDT 24 538511014 ps
T432 /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1885527303 Aug 05 07:34:34 PM PDT 24 Aug 05 07:41:45 PM PDT 24 3622991052 ps
T132 /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1034145556 Aug 05 07:32:20 PM PDT 24 Aug 05 07:37:47 PM PDT 24 8123401936 ps
T1353 /workspace/coverage/cover_reg_top/35.xbar_error_random.1288921977 Aug 05 07:41:50 PM PDT 24 Aug 05 07:42:39 PM PDT 24 1367556072 ps
T568 /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.3981690952 Aug 05 07:52:47 PM PDT 24 Aug 05 07:53:49 PM PDT 24 1311568363 ps
T511 /workspace/coverage/cover_reg_top/65.xbar_access_same_device.2786374883 Aug 05 07:47:49 PM PDT 24 Aug 05 07:49:06 PM PDT 24 1806085380 ps
T406 /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.849534116 Aug 05 07:43:47 PM PDT 24 Aug 05 07:44:09 PM PDT 24 246361145 ps
T428 /workspace/coverage/cover_reg_top/50.xbar_stress_all.4013920859 Aug 05 07:44:49 PM PDT 24 Aug 05 07:51:36 PM PDT 24 11350731685 ps
T540 /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.3102012775 Aug 05 07:51:14 PM PDT 24 Aug 05 07:53:05 PM PDT 24 11258735985 ps
T550 /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.3153833593 Aug 05 07:47:40 PM PDT 24 Aug 05 07:47:48 PM PDT 24 54086090 ps
T495 /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.2449983428 Aug 05 07:44:07 PM PDT 24 Aug 05 07:44:46 PM PDT 24 316588953 ps
T530 /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.156302891 Aug 05 07:53:46 PM PDT 24 Aug 05 08:09:05 PM PDT 24 83802568300 ps
T539 /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.853903329 Aug 05 07:52:47 PM PDT 24 Aug 05 07:53:19 PM PDT 24 304646525 ps
T1354 /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.2039196973 Aug 05 07:42:53 PM PDT 24 Aug 05 07:44:42 PM PDT 24 10981903497 ps
T659 /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.3169714755 Aug 05 07:44:50 PM PDT 24 Aug 05 07:50:01 PM PDT 24 4702984890 ps
T563 /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.2898383018 Aug 05 07:41:14 PM PDT 24 Aug 05 07:42:47 PM PDT 24 5545586948 ps
T569 /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.1034397401 Aug 05 07:47:31 PM PDT 24 Aug 05 07:49:09 PM PDT 24 5972019189 ps
T532 /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.2050188138 Aug 05 07:49:00 PM PDT 24 Aug 05 07:49:47 PM PDT 24 556714441 ps
T441 /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.436447952 Aug 05 07:33:45 PM PDT 24 Aug 05 07:35:29 PM PDT 24 9961868487 ps
T806 /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.51167540 Aug 05 07:31:40 PM PDT 24 Aug 05 07:34:25 PM PDT 24 9899059292 ps
T446 /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.3221476611 Aug 05 07:32:13 PM PDT 24 Aug 05 07:42:06 PM PDT 24 9197909495 ps
T531 /workspace/coverage/cover_reg_top/62.xbar_smoke.3610176426 Aug 05 07:47:13 PM PDT 24 Aug 05 07:47:23 PM PDT 24 246015535 ps
T781 /workspace/coverage/cover_reg_top/29.xbar_access_same_device.3185144030 Aug 05 07:41:21 PM PDT 24 Aug 05 07:42:28 PM PDT 24 1578650291 ps
T542 /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.891983541 Aug 05 07:48:32 PM PDT 24 Aug 05 07:48:39 PM PDT 24 47617816 ps
T792 /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.3803907735 Aug 05 07:51:58 PM PDT 24 Aug 05 07:54:27 PM PDT 24 4747478092 ps
T1355 /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.1430661582 Aug 05 07:49:43 PM PDT 24 Aug 05 07:49:55 PM PDT 24 111237479 ps
T778 /workspace/coverage/cover_reg_top/17.xbar_access_same_device.4116852380 Aug 05 07:36:16 PM PDT 24 Aug 05 07:36:38 PM PDT 24 316141040 ps
T636 /workspace/coverage/cover_reg_top/5.xbar_access_same_device.3204391930 Aug 05 07:33:46 PM PDT 24 Aug 05 07:34:25 PM PDT 24 981336417 ps
T534 /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.2842436748 Aug 05 07:49:53 PM PDT 24 Aug 05 07:56:57 PM PDT 24 42623963721 ps
T1356 /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.879655666 Aug 05 07:49:58 PM PDT 24 Aug 05 07:50:27 PM PDT 24 252328189 ps
T1357 /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.3931991534 Aug 05 07:43:48 PM PDT 24 Aug 05 07:43:54 PM PDT 24 61497409 ps
T780 /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.967151813 Aug 05 07:49:51 PM PDT 24 Aug 05 08:06:55 PM PDT 24 61782570857 ps
T544 /workspace/coverage/cover_reg_top/16.xbar_same_source.1356184871 Aug 05 07:36:17 PM PDT 24 Aug 05 07:36:37 PM PDT 24 262067267 ps
T588 /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.3287817887 Aug 05 07:48:23 PM PDT 24 Aug 05 07:57:37 PM PDT 24 16751847147 ps
T429 /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.3335596936 Aug 05 07:52:47 PM PDT 24 Aug 05 07:54:12 PM PDT 24 7936379754 ps
T583 /workspace/coverage/cover_reg_top/71.xbar_random.2620765308 Aug 05 07:49:00 PM PDT 24 Aug 05 07:49:26 PM PDT 24 701674977 ps
T536 /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.2732020495 Aug 05 07:48:30 PM PDT 24 Aug 05 07:54:11 PM PDT 24 19925729148 ps
T529 /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.748070293 Aug 05 07:45:28 PM PDT 24 Aug 05 07:46:31 PM PDT 24 3700723178 ps
T402 /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.299251832 Aug 05 07:46:40 PM PDT 24 Aug 05 08:06:08 PM PDT 24 60127841824 ps
T1358 /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.3418196706 Aug 05 07:34:07 PM PDT 24 Aug 05 07:34:15 PM PDT 24 50077835 ps
T785 /workspace/coverage/cover_reg_top/91.xbar_access_same_device.399712259 Aug 05 07:53:08 PM PDT 24 Aug 05 07:53:55 PM PDT 24 523927570 ps
T572 /workspace/coverage/cover_reg_top/84.xbar_random.287958979 Aug 05 07:51:48 PM PDT 24 Aug 05 07:52:23 PM PDT 24 394491286 ps
T791 /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.648848680 Aug 05 07:53:09 PM PDT 24 Aug 05 08:19:40 PM PDT 24 92874378613 ps
T1359 /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.2676739132 Aug 05 07:41:00 PM PDT 24 Aug 05 07:41:30 PM PDT 24 2904857554 ps
T567 /workspace/coverage/cover_reg_top/40.xbar_stress_all.325700358 Aug 05 07:42:54 PM PDT 24 Aug 05 07:44:02 PM PDT 24 848847769 ps
T442 /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.1239381612 Aug 05 07:42:13 PM PDT 24 Aug 05 07:51:14 PM PDT 24 51583796786 ps
T1360 /workspace/coverage/cover_reg_top/99.xbar_smoke.3399577294 Aug 05 07:54:30 PM PDT 24 Aug 05 07:54:39 PM PDT 24 195819904 ps
T497 /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.2992445553 Aug 05 07:36:09 PM PDT 24 Aug 05 07:37:21 PM PDT 24 6700938909 ps
T391 /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.1794235180 Aug 05 07:35:36 PM PDT 24 Aug 05 07:36:26 PM PDT 24 1269103837 ps
T801 /workspace/coverage/cover_reg_top/8.xbar_access_same_device.3987797305 Aug 05 07:34:00 PM PDT 24 Aug 05 07:34:11 PM PDT 24 132959117 ps
T552 /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.3218563067 Aug 05 07:41:24 PM PDT 24 Aug 05 07:51:55 PM PDT 24 61251124367 ps
T628 /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.1202381941 Aug 05 07:40:54 PM PDT 24 Aug 05 07:45:48 PM PDT 24 8096628649 ps
T1361 /workspace/coverage/cover_reg_top/24.xbar_smoke.3723277697 Aug 05 07:38:06 PM PDT 24 Aug 05 07:38:14 PM PDT 24 192234171 ps
T574 /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.1813870595 Aug 05 07:50:24 PM PDT 24 Aug 05 07:50:38 PM PDT 24 106317312 ps
T478 /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1139669961 Aug 05 07:51:37 PM PDT 24 Aug 05 07:51:52 PM PDT 24 167809646 ps
T790 /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.372940229 Aug 05 07:51:20 PM PDT 24 Aug 05 08:06:08 PM PDT 24 55127250906 ps
T1362 /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.2389599865 Aug 05 07:47:26 PM PDT 24 Aug 05 07:47:51 PM PDT 24 36707290 ps
T627 /workspace/coverage/cover_reg_top/37.xbar_error_random.1195877467 Aug 05 07:42:33 PM PDT 24 Aug 05 07:42:55 PM PDT 24 281215824 ps
T660 /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.994328885 Aug 05 07:36:09 PM PDT 24 Aug 05 07:36:57 PM PDT 24 1188962914 ps
T430 /workspace/coverage/cover_reg_top/80.xbar_stress_all.2294612150 Aug 05 07:51:01 PM PDT 24 Aug 05 07:57:19 PM PDT 24 9533413794 ps
T653 /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.1576115833 Aug 05 07:53:56 PM PDT 24 Aug 05 07:54:02 PM PDT 24 44080485 ps
T409 /workspace/coverage/cover_reg_top/58.xbar_same_source.2617455200 Aug 05 07:46:32 PM PDT 24 Aug 05 07:47:13 PM PDT 24 1355607967 ps
T528 /workspace/coverage/cover_reg_top/85.xbar_stress_all.239584112 Aug 05 07:51:52 PM PDT 24 Aug 05 07:57:16 PM PDT 24 8786925548 ps
T793 /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.2794804015 Aug 05 07:54:26 PM PDT 24 Aug 05 08:12:55 PM PDT 24 56145753029 ps
T1363 /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3979790619 Aug 05 07:31:40 PM PDT 24 Aug 05 07:39:18 PM PDT 24 10758248365 ps
T1364 /workspace/coverage/cover_reg_top/50.xbar_error_random.2911202315 Aug 05 07:44:36 PM PDT 24 Aug 05 07:45:00 PM PDT 24 627175861 ps
T584 /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.1868545222 Aug 05 07:32:10 PM PDT 24 Aug 05 07:39:38 PM PDT 24 26053793010 ps
T782 /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2396668754 Aug 05 07:34:57 PM PDT 24 Aug 05 08:16:50 PM PDT 24 142966896828 ps
T812 /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.101310547 Aug 05 07:52:28 PM PDT 24 Aug 05 07:55:18 PM PDT 24 794230550 ps
T548 /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.1153656249 Aug 05 07:33:45 PM PDT 24 Aug 05 07:34:09 PM PDT 24 278598764 ps
T543 /workspace/coverage/cover_reg_top/24.xbar_same_source.4126851266 Aug 05 07:38:21 PM PDT 24 Aug 05 07:39:18 PM PDT 24 2022242890 ps
T408 /workspace/coverage/cover_reg_top/85.xbar_access_same_device.1002976913 Aug 05 07:51:48 PM PDT 24 Aug 05 07:52:13 PM PDT 24 371889703 ps
T1365 /workspace/coverage/cover_reg_top/22.xbar_same_source.3221986367 Aug 05 07:37:37 PM PDT 24 Aug 05 07:37:45 PM PDT 24 78271256 ps
T1366 /workspace/coverage/cover_reg_top/71.xbar_access_same_device.3317021231 Aug 05 07:49:00 PM PDT 24 Aug 05 07:49:21 PM PDT 24 212546256 ps
T479 /workspace/coverage/cover_reg_top/42.xbar_same_source.1851672730 Aug 05 07:43:11 PM PDT 24 Aug 05 07:43:39 PM PDT 24 1048099817 ps
T593 /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1504992534 Aug 05 07:34:57 PM PDT 24 Aug 05 07:35:12 PM PDT 24 301835458 ps
T811 /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1812831018 Aug 05 07:49:51 PM PDT 24 Aug 05 07:50:16 PM PDT 24 100466901 ps
T783 /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.339668385 Aug 05 07:33:58 PM PDT 24 Aug 05 07:41:42 PM PDT 24 14046904157 ps
T1367 /workspace/coverage/cover_reg_top/49.xbar_error_random.3307597102 Aug 05 07:44:27 PM PDT 24 Aug 05 07:45:12 PM PDT 24 645973254 ps
T466 /workspace/coverage/cover_reg_top/94.xbar_random.594537138 Aug 05 07:53:39 PM PDT 24 Aug 05 07:54:03 PM PDT 24 626673895 ps
T779 /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2559407129 Aug 05 07:50:25 PM PDT 24 Aug 05 08:18:34 PM PDT 24 98311580979 ps
T795 /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.2718659567 Aug 05 07:51:16 PM PDT 24 Aug 05 08:12:24 PM PDT 24 72382542191 ps
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T541 /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.3714989933 Aug 05 07:40:54 PM PDT 24 Aug 05 07:41:28 PM PDT 24 330700456 ps
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T1377 /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.3922769715 Aug 05 07:51:56 PM PDT 24 Aug 05 07:52:54 PM PDT 24 5642718268 ps
T1378 /workspace/coverage/cover_reg_top/92.xbar_smoke.3004780131 Aug 05 07:53:07 PM PDT 24 Aug 05 07:53:15 PM PDT 24 194505078 ps
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T565 /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.2543133156 Aug 05 07:49:58 PM PDT 24 Aug 05 07:52:44 PM PDT 24 935843485 ps
T616 /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.2358308251 Aug 05 07:52:27 PM PDT 24 Aug 05 07:52:45 PM PDT 24 187036996 ps
T1379 /workspace/coverage/cover_reg_top/80.xbar_same_source.124878387 Aug 05 07:51:01 PM PDT 24 Aug 05 07:51:20 PM PDT 24 636876501 ps
T576 /workspace/coverage/cover_reg_top/4.xbar_random.451201274 Aug 05 07:33:42 PM PDT 24 Aug 05 07:34:59 PM PDT 24 2040125526 ps
T564 /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.3781774991 Aug 05 07:44:25 PM PDT 24 Aug 05 07:44:55 PM PDT 24 332711717 ps
T427 /workspace/coverage/cover_reg_top/97.xbar_stress_all.3033374058 Aug 05 07:54:17 PM PDT 24 Aug 05 07:59:49 PM PDT 24 8874415431 ps
T570 /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.436443473 Aug 05 07:51:50 PM PDT 24 Aug 05 07:52:13 PM PDT 24 266855787 ps
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T1380 /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.1358631013 Aug 05 07:52:41 PM PDT 24 Aug 05 07:54:09 PM PDT 24 5372292171 ps
T547 /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.1125765914 Aug 05 07:51:52 PM PDT 24 Aug 05 07:53:03 PM PDT 24 4231877255 ps
T1381 /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.1421982950 Aug 05 07:53:12 PM PDT 24 Aug 05 07:55:25 PM PDT 24 1688320253 ps
T533 /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.459024298 Aug 05 07:51:59 PM PDT 24 Aug 05 07:52:16 PM PDT 24 150715585 ps
T148 /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1365152247 Aug 05 07:36:18 PM PDT 24 Aug 05 08:40:36 PM PDT 24 30709654706 ps
T786 /workspace/coverage/cover_reg_top/56.xbar_access_same_device.1762538017 Aug 05 07:45:51 PM PDT 24 Aug 05 07:46:57 PM PDT 24 1926443247 ps
T603 /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.3469282492 Aug 05 07:41:35 PM PDT 24 Aug 05 07:41:48 PM PDT 24 132605143 ps
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T1382 /workspace/coverage/cover_reg_top/65.xbar_smoke.2247030899 Aug 05 07:47:40 PM PDT 24 Aug 05 07:47:49 PM PDT 24 210215936 ps
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T1383 /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.2336298185 Aug 05 07:43:05 PM PDT 24 Aug 05 07:44:19 PM PDT 24 4311241559 ps
T1384 /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.4025015809 Aug 05 07:34:05 PM PDT 24 Aug 05 07:35:57 PM PDT 24 6988148261 ps
T797 /workspace/coverage/cover_reg_top/55.xbar_access_same_device.1078980335 Aug 05 07:45:38 PM PDT 24 Aug 05 07:47:14 PM PDT 24 2247921536 ps
T437 /workspace/coverage/cover_reg_top/11.xbar_stress_all.92348649 Aug 05 07:34:33 PM PDT 24 Aug 05 07:39:52 PM PDT 24 3501539146 ps
T582 /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3548988109 Aug 05 07:31:45 PM PDT 24 Aug 05 07:43:03 PM PDT 24 15427260061 ps
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T817 /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.3317741597 Aug 05 07:51:58 PM PDT 24 Aug 05 07:54:10 PM PDT 24 458745062 ps
T1385 /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.2186736608 Aug 05 07:37:36 PM PDT 24 Aug 05 07:38:13 PM PDT 24 865051214 ps
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T555 /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.1613052265 Aug 05 07:46:02 PM PDT 24 Aug 05 07:47:29 PM PDT 24 5351847338 ps
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T1386 /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.3843648326 Aug 05 07:36:02 PM PDT 24 Aug 05 07:37:15 PM PDT 24 7316690410 ps
T787 /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.1513226766 Aug 05 07:51:46 PM PDT 24 Aug 05 08:16:33 PM PDT 24 80011208376 ps
T600 /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.1857370819 Aug 05 07:51:51 PM PDT 24 Aug 05 07:59:30 PM PDT 24 28109723135 ps
T1387 /workspace/coverage/cover_reg_top/29.xbar_error_random.100607141 Aug 05 07:41:19 PM PDT 24 Aug 05 07:41:29 PM PDT 24 195483482 ps
T1388 /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.1353867369 Aug 05 07:45:01 PM PDT 24 Aug 05 07:45:12 PM PDT 24 90442866 ps
T571 /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.3932265211 Aug 05 07:33:45 PM PDT 24 Aug 05 07:36:40 PM PDT 24 390303834 ps
T549 /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.4065284582 Aug 05 07:54:42 PM PDT 24 Aug 05 08:03:12 PM PDT 24 28935829587 ps
T601 /workspace/coverage/cover_reg_top/35.xbar_random.3312160911 Aug 05 07:41:37 PM PDT 24 Aug 05 07:41:55 PM PDT 24 455602933 ps
T523 /workspace/coverage/cover_reg_top/16.chip_tl_errors.2248106526 Aug 05 07:36:01 PM PDT 24 Aug 05 07:40:24 PM PDT 24 3741582560 ps
T1389 /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.1922797419 Aug 05 07:51:38 PM PDT 24 Aug 05 07:53:02 PM PDT 24 8360473760 ps
T802 /workspace/coverage/cover_reg_top/44.xbar_access_same_device.3865424388 Aug 05 07:43:39 PM PDT 24 Aug 05 07:44:41 PM PDT 24 985596120 ps
T618 /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.285317733 Aug 05 07:48:41 PM PDT 24 Aug 05 07:52:39 PM PDT 24 15122277819 ps
T1390 /workspace/coverage/cover_reg_top/24.xbar_error_random.2950468138 Aug 05 07:38:17 PM PDT 24 Aug 05 07:39:09 PM PDT 24 1538228299 ps
T1391 /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.642073999 Aug 05 07:33:58 PM PDT 24 Aug 05 07:36:18 PM PDT 24 2032585706 ps
T804 /workspace/coverage/cover_reg_top/48.xbar_access_same_device.2302857743 Aug 05 07:44:16 PM PDT 24 Aug 05 07:45:37 PM PDT 24 997658115 ps
T608 /workspace/coverage/cover_reg_top/91.xbar_same_source.4224284889 Aug 05 07:53:07 PM PDT 24 Aug 05 07:53:41 PM PDT 24 489664197 ps
T492 /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.3704639911 Aug 05 07:50:16 PM PDT 24 Aug 05 07:50:56 PM PDT 24 493787998 ps
T1392 /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2137503963 Aug 05 07:32:00 PM PDT 24 Aug 05 07:38:17 PM PDT 24 11255113020 ps
T1393 /workspace/coverage/cover_reg_top/40.xbar_error_random.2380539312 Aug 05 07:42:54 PM PDT 24 Aug 05 07:43:48 PM PDT 24 1731594427 ps
T629 /workspace/coverage/cover_reg_top/90.xbar_error_random.969541581 Aug 05 07:52:59 PM PDT 24 Aug 05 07:54:13 PM PDT 24 2075666004 ps
T349 /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.4164179465 Aug 05 07:31:49 PM PDT 24 Aug 05 09:13:31 PM PDT 24 59252462521 ps
T1394 /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.2705736024 Aug 05 07:48:58 PM PDT 24 Aug 05 07:49:21 PM PDT 24 330112039 ps
T527 /workspace/coverage/cover_reg_top/26.chip_tl_errors.2550267203 Aug 05 07:40:55 PM PDT 24 Aug 05 07:43:55 PM PDT 24 3573549356 ps
T476 /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.4228100623 Aug 05 07:48:20 PM PDT 24 Aug 05 07:51:34 PM PDT 24 1116804290 ps
T488 /workspace/coverage/cover_reg_top/29.xbar_same_source.1343976572 Aug 05 07:41:22 PM PDT 24 Aug 05 07:42:08 PM PDT 24 1630842806 ps
T440 /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.1035937923 Aug 05 07:50:37 PM PDT 24 Aug 05 07:51:01 PM PDT 24 254726770 ps
T824 /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.4052756004 Aug 05 07:32:01 PM PDT 24 Aug 05 07:34:04 PM PDT 24 1186283631 ps
T447 /workspace/coverage/cover_reg_top/72.xbar_access_same_device.2824921059 Aug 05 07:49:09 PM PDT 24 Aug 05 07:50:27 PM PDT 24 1092976033 ps
T1395 /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.1633662923 Aug 05 07:49:51 PM PDT 24 Aug 05 07:50:21 PM PDT 24 702564152 ps
T619 /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.4241869886 Aug 05 07:34:01 PM PDT 24 Aug 05 07:47:43 PM PDT 24 84532497047 ps
T1396 /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.2061978500 Aug 05 07:41:26 PM PDT 24 Aug 05 07:43:17 PM PDT 24 6538895078 ps
T788 /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.2282422766 Aug 05 07:46:21 PM PDT 24 Aug 05 07:50:37 PM PDT 24 3189312737 ps
T1397 /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1804086606 Aug 05 07:35:41 PM PDT 24 Aug 05 07:35:57 PM PDT 24 37279191 ps
T1398 /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.2778224226 Aug 05 07:33:44 PM PDT 24 Aug 05 07:34:19 PM PDT 24 976354484 ps
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T1400 /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.3956725279 Aug 05 07:32:13 PM PDT 24 Aug 05 07:32:42 PM PDT 24 286435102 ps
T452 /workspace/coverage/cover_reg_top/46.xbar_stress_all.3688432804 Aug 05 07:43:56 PM PDT 24 Aug 05 07:47:36 PM PDT 24 2914804977 ps
T595 /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.227631101 Aug 05 07:36:37 PM PDT 24 Aug 05 07:37:04 PM PDT 24 275855184 ps
T1401 /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2612440301 Aug 05 07:34:05 PM PDT 24 Aug 05 07:34:11 PM PDT 24 35784953 ps
T828 /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.392081656 Aug 05 07:54:17 PM PDT 24 Aug 05 07:58:16 PM PDT 24 770583556 ps
T1402 /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.392741317 Aug 05 07:38:08 PM PDT 24 Aug 05 07:38:15 PM PDT 24 43670881 ps
T586 /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.2573785880 Aug 05 07:51:00 PM PDT 24 Aug 05 07:58:00 PM PDT 24 25289610231 ps
T1403 /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.3031229422 Aug 05 07:47:01 PM PDT 24 Aug 05 07:47:18 PM PDT 24 150026729 ps
T383 /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.3392186575 Aug 05 07:36:58 PM PDT 24 Aug 05 07:51:22 PM PDT 24 8904620368 ps
T524 /workspace/coverage/cover_reg_top/22.chip_tl_errors.3651423644 Aug 05 07:37:27 PM PDT 24 Aug 05 07:42:37 PM PDT 24 4409729372 ps
T1404 /workspace/coverage/cover_reg_top/39.xbar_same_source.3733090534 Aug 05 07:42:46 PM PDT 24 Aug 05 07:43:28 PM PDT 24 1369210266 ps
T1405 /workspace/coverage/cover_reg_top/66.xbar_error_random.1703646326 Aug 05 07:48:01 PM PDT 24 Aug 05 07:48:25 PM PDT 24 331331000 ps
T1406 /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.1722475644 Aug 05 07:46:54 PM PDT 24 Aug 05 07:47:12 PM PDT 24 188274769 ps
T613 /workspace/coverage/cover_reg_top/42.xbar_random.2867753820 Aug 05 07:43:04 PM PDT 24 Aug 05 07:44:17 PM PDT 24 2171713783 ps
T833 /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2206588531 Aug 05 07:41:32 PM PDT 24 Aug 05 07:43:54 PM PDT 24 333618595 ps
T1407 /workspace/coverage/cover_reg_top/57.xbar_random.2771562045 Aug 05 07:46:01 PM PDT 24 Aug 05 07:46:34 PM PDT 24 352408156 ps
T581 /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.12309881 Aug 05 07:42:24 PM PDT 24 Aug 05 07:43:06 PM PDT 24 550582118 ps
T535 /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.2753195748 Aug 05 07:46:37 PM PDT 24 Aug 05 07:57:47 PM PDT 24 66571391414 ps
T559 /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.446170616 Aug 05 07:41:28 PM PDT 24 Aug 05 07:43:03 PM PDT 24 9076335726 ps
T1408 /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.2465545807 Aug 05 07:50:52 PM PDT 24 Aug 05 07:51:53 PM PDT 24 3575897350 ps
T438 /workspace/coverage/cover_reg_top/41.xbar_access_same_device.2358448944 Aug 05 07:43:02 PM PDT 24 Aug 05 07:44:13 PM PDT 24 1021995827 ps
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