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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.21 95.58 94.17 95.38 95.01 97.53 99.60


Total test records in report: 2944
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T289 /workspace/coverage/default/76.chip_sw_all_escalation_resets.3955031489 Aug 05 08:41:34 PM PDT 24 Aug 05 08:52:42 PM PDT 24 5876698344 ps
T999 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.4105705853 Aug 05 08:19:31 PM PDT 24 Aug 05 08:23:41 PM PDT 24 2900564412 ps
T1000 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.4155655988 Aug 05 08:02:21 PM PDT 24 Aug 05 08:12:43 PM PDT 24 5820025860 ps
T230 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.4253103729 Aug 05 08:23:00 PM PDT 24 Aug 05 08:34:34 PM PDT 24 5123888112 ps
T1001 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.261848414 Aug 05 08:03:58 PM PDT 24 Aug 05 08:36:04 PM PDT 24 13570265640 ps
T1002 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.818969337 Aug 05 08:11:31 PM PDT 24 Aug 05 08:50:40 PM PDT 24 26435364342 ps
T723 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3777024674 Aug 05 08:35:04 PM PDT 24 Aug 05 08:41:35 PM PDT 24 3346451620 ps
T1003 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3744771075 Aug 05 08:15:08 PM PDT 24 Aug 05 08:48:21 PM PDT 24 11689271720 ps
T1004 /workspace/coverage/default/2.chip_sw_hmac_oneshot.4293055497 Aug 05 08:26:07 PM PDT 24 Aug 05 08:33:59 PM PDT 24 3255924824 ps
T110 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3850891536 Aug 05 08:19:31 PM PDT 24 Aug 05 08:29:52 PM PDT 24 4924264832 ps
T1005 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3914269652 Aug 05 08:34:42 PM PDT 24 Aug 05 09:35:04 PM PDT 24 17536635736 ps
T710 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.120790496 Aug 05 08:37:58 PM PDT 24 Aug 05 08:45:23 PM PDT 24 3509805344 ps
T297 /workspace/coverage/default/1.chip_plic_all_irqs_20.1839165563 Aug 05 08:17:07 PM PDT 24 Aug 05 08:34:50 PM PDT 24 4752471800 ps
T1006 /workspace/coverage/default/2.chip_sw_rv_timer_irq.683164905 Aug 05 08:24:20 PM PDT 24 Aug 05 08:28:43 PM PDT 24 2940105828 ps
T1007 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1744016976 Aug 05 08:05:29 PM PDT 24 Aug 05 08:16:17 PM PDT 24 4940159476 ps
T1008 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2159262903 Aug 05 08:34:08 PM PDT 24 Aug 05 08:43:40 PM PDT 24 4380248402 ps
T340 /workspace/coverage/default/0.chip_sw_aon_timer_irq.3418363495 Aug 05 08:04:39 PM PDT 24 Aug 05 08:13:11 PM PDT 24 4168823344 ps
T1009 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.163642245 Aug 05 08:04:52 PM PDT 24 Aug 05 08:35:28 PM PDT 24 8156971794 ps
T244 /workspace/coverage/default/0.chip_sw_plic_sw_irq.154556534 Aug 05 08:04:33 PM PDT 24 Aug 05 08:09:36 PM PDT 24 3159003810 ps
T1010 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3604161438 Aug 05 08:16:09 PM PDT 24 Aug 05 08:45:33 PM PDT 24 9195300997 ps
T152 /workspace/coverage/default/2.rom_raw_unlock.2820798628 Aug 05 08:31:38 PM PDT 24 Aug 05 08:36:14 PM PDT 24 5231584967 ps
T1011 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1975797671 Aug 05 08:13:09 PM PDT 24 Aug 05 09:10:48 PM PDT 24 14474711376 ps
T1012 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.604582442 Aug 05 08:03:20 PM PDT 24 Aug 05 08:15:35 PM PDT 24 4249291276 ps
T1013 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1563321491 Aug 05 08:02:01 PM PDT 24 Aug 05 08:11:20 PM PDT 24 4206564124 ps
T1014 /workspace/coverage/default/43.chip_sw_all_escalation_resets.605973535 Aug 05 08:39:39 PM PDT 24 Aug 05 08:50:16 PM PDT 24 5813027024 ps
T1015 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2934427991 Aug 05 08:28:47 PM PDT 24 Aug 05 08:53:28 PM PDT 24 8088299370 ps
T1016 /workspace/coverage/default/2.rom_e2e_static_critical.2529524211 Aug 05 08:35:44 PM PDT 24 Aug 05 09:36:21 PM PDT 24 17035494284 ps
T689 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1262000977 Aug 05 08:42:18 PM PDT 24 Aug 05 08:47:19 PM PDT 24 3074377358 ps
T210 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1034003378 Aug 05 08:03:57 PM PDT 24 Aug 05 08:09:48 PM PDT 24 3646340844 ps
T1017 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.924378379 Aug 05 08:05:02 PM PDT 24 Aug 05 08:22:59 PM PDT 24 6596505110 ps
T1018 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.297584461 Aug 05 08:41:40 PM PDT 24 Aug 05 08:49:24 PM PDT 24 4005552876 ps
T1019 /workspace/coverage/default/0.chip_sw_gpio_smoketest.3945661122 Aug 05 08:07:11 PM PDT 24 Aug 05 08:11:27 PM PDT 24 3136716421 ps
T1020 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2655233150 Aug 05 08:19:55 PM PDT 24 Aug 05 08:32:09 PM PDT 24 5087169700 ps
T1021 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.434316461 Aug 05 08:24:55 PM PDT 24 Aug 05 09:26:28 PM PDT 24 18964833041 ps
T1022 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3269568142 Aug 05 08:34:00 PM PDT 24 Aug 05 08:39:21 PM PDT 24 7787955600 ps
T1023 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1519968724 Aug 05 08:18:16 PM PDT 24 Aug 05 08:28:04 PM PDT 24 4231862146 ps
T1024 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3619902181 Aug 05 08:19:52 PM PDT 24 Aug 05 08:25:02 PM PDT 24 3022630515 ps
T740 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.358823337 Aug 05 08:41:42 PM PDT 24 Aug 05 08:47:49 PM PDT 24 3680774424 ps
T1025 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.419413616 Aug 05 08:34:15 PM PDT 24 Aug 05 09:37:34 PM PDT 24 20391365920 ps
T263 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2107414721 Aug 05 08:19:58 PM PDT 24 Aug 05 08:30:18 PM PDT 24 4259061907 ps
T300 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1152758675 Aug 05 08:25:00 PM PDT 24 Aug 05 08:54:52 PM PDT 24 11175168984 ps
T35 /workspace/coverage/default/0.chip_sw_spi_device_tpm.1524523320 Aug 05 08:02:29 PM PDT 24 Aug 05 08:08:25 PM PDT 24 3607499239 ps
T1026 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1257232929 Aug 05 08:04:38 PM PDT 24 Aug 05 08:14:51 PM PDT 24 5033767620 ps
T1027 /workspace/coverage/default/2.chip_sw_aes_idle.868599672 Aug 05 08:27:00 PM PDT 24 Aug 05 08:32:15 PM PDT 24 2338189720 ps
T696 /workspace/coverage/default/18.chip_sw_all_escalation_resets.4281242411 Aug 05 08:37:50 PM PDT 24 Aug 05 08:46:13 PM PDT 24 5118846160 ps
T324 /workspace/coverage/default/1.chip_sival_flash_info_access.3176373124 Aug 05 08:09:59 PM PDT 24 Aug 05 08:15:46 PM PDT 24 3338912358 ps
T1028 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1845108484 Aug 05 08:36:05 PM PDT 24 Aug 05 08:45:04 PM PDT 24 6079648638 ps
T1029 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1570366695 Aug 05 08:14:56 PM PDT 24 Aug 05 08:39:20 PM PDT 24 7924123812 ps
T174 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.881045736 Aug 05 08:10:50 PM PDT 24 Aug 05 08:14:11 PM PDT 24 3623301565 ps
T264 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.450839478 Aug 05 08:27:16 PM PDT 24 Aug 05 08:39:18 PM PDT 24 5796937768 ps
T734 /workspace/coverage/default/77.chip_sw_all_escalation_resets.906644657 Aug 05 08:41:14 PM PDT 24 Aug 05 08:50:14 PM PDT 24 5872439828 ps
T1030 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2026853795 Aug 05 08:36:33 PM PDT 24 Aug 05 08:58:33 PM PDT 24 8827225640 ps
T212 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.552689678 Aug 05 08:21:55 PM PDT 24 Aug 05 11:09:57 PM PDT 24 57269827560 ps
T117 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1133887093 Aug 05 08:31:54 PM PDT 24 Aug 06 01:58:10 AM PDT 24 146358324419 ps
T1031 /workspace/coverage/default/2.chip_sival_flash_info_access.1128425133 Aug 05 08:21:11 PM PDT 24 Aug 05 08:27:22 PM PDT 24 3030491106 ps
T1032 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3588720185 Aug 05 08:16:44 PM PDT 24 Aug 05 08:21:49 PM PDT 24 2738323027 ps
T140 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1749344816 Aug 05 08:32:29 PM PDT 24 Aug 05 09:26:54 PM PDT 24 24173329052 ps
T1033 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2201271219 Aug 05 08:35:56 PM PDT 24 Aug 05 08:48:08 PM PDT 24 4406682086 ps
T1034 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2722035628 Aug 05 08:30:00 PM PDT 24 Aug 05 08:34:59 PM PDT 24 3024902867 ps
T1035 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3201056535 Aug 05 08:29:33 PM PDT 24 Aug 05 08:41:36 PM PDT 24 5245695240 ps
T1036 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.148217440 Aug 05 08:21:22 PM PDT 24 Aug 05 08:49:21 PM PDT 24 9781610530 ps
T1037 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3722414489 Aug 05 08:03:30 PM PDT 24 Aug 05 08:21:41 PM PDT 24 5586946781 ps
T1038 /workspace/coverage/default/1.chip_sw_uart_tx_rx.2123529370 Aug 05 08:10:50 PM PDT 24 Aug 05 08:19:47 PM PDT 24 4506329530 ps
T1039 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.1685646947 Aug 05 08:34:04 PM PDT 24 Aug 05 09:23:38 PM PDT 24 15105104070 ps
T692 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3602308107 Aug 05 08:40:28 PM PDT 24 Aug 05 08:47:43 PM PDT 24 3532223608 ps
T1040 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.4031278937 Aug 05 08:05:31 PM PDT 24 Aug 05 08:10:25 PM PDT 24 2687513508 ps
T1041 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.4278306847 Aug 05 08:19:55 PM PDT 24 Aug 05 08:43:59 PM PDT 24 5585463024 ps
T1042 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2697662462 Aug 05 08:11:14 PM PDT 24 Aug 05 09:04:07 PM PDT 24 10878000274 ps
T341 /workspace/coverage/default/1.chip_sw_aon_timer_irq.2155363493 Aug 05 08:13:47 PM PDT 24 Aug 05 08:20:18 PM PDT 24 3661513568 ps
T1043 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.4206478097 Aug 05 08:25:06 PM PDT 24 Aug 05 08:38:50 PM PDT 24 4041686423 ps
T1044 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.902137547 Aug 05 08:25:29 PM PDT 24 Aug 05 08:37:49 PM PDT 24 4412050640 ps
T639 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1364731284 Aug 05 08:24:31 PM PDT 24 Aug 05 08:28:26 PM PDT 24 2856942894 ps
T1045 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3624664768 Aug 05 08:25:37 PM PDT 24 Aug 05 09:26:58 PM PDT 24 15462336442 ps
T756 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.304274758 Aug 05 08:39:52 PM PDT 24 Aug 05 08:47:05 PM PDT 24 4171521168 ps
T131 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1588714293 Aug 05 08:19:05 PM PDT 24 Aug 05 08:28:38 PM PDT 24 5684333960 ps
T1046 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3257364549 Aug 05 08:10:44 PM PDT 24 Aug 05 09:19:11 PM PDT 24 15220368960 ps
T742 /workspace/coverage/default/69.chip_sw_all_escalation_resets.385017052 Aug 05 08:41:09 PM PDT 24 Aug 05 08:51:18 PM PDT 24 4384703732 ps
T1047 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.4033658917 Aug 05 08:11:47 PM PDT 24 Aug 05 08:17:54 PM PDT 24 3137321460 ps
T1048 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2003889653 Aug 05 08:25:51 PM PDT 24 Aug 05 08:30:32 PM PDT 24 3077259196 ps
T1049 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2611079750 Aug 05 08:30:06 PM PDT 24 Aug 05 08:39:56 PM PDT 24 4515442852 ps
T1050 /workspace/coverage/default/1.chip_sw_example_manufacturer.2064538517 Aug 05 08:08:36 PM PDT 24 Aug 05 08:13:01 PM PDT 24 2871959510 ps
T1051 /workspace/coverage/default/1.rom_e2e_static_critical.972233861 Aug 05 08:26:27 PM PDT 24 Aug 05 09:34:37 PM PDT 24 17139016618 ps
T247 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2619775270 Aug 05 08:02:27 PM PDT 24 Aug 05 08:12:23 PM PDT 24 4866242264 ps
T1052 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3276810271 Aug 05 08:38:05 PM PDT 24 Aug 05 09:01:45 PM PDT 24 8944442624 ps
T134 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2390830786 Aug 05 08:03:22 PM PDT 24 Aug 05 08:13:29 PM PDT 24 8604285284 ps
T1053 /workspace/coverage/default/2.chip_sw_csrng_kat_test.3824061913 Aug 05 08:26:05 PM PDT 24 Aug 05 08:30:35 PM PDT 24 2518970200 ps
T1054 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.4069033812 Aug 05 08:18:08 PM PDT 24 Aug 05 08:51:01 PM PDT 24 9258650248 ps
T1055 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1251869352 Aug 05 08:11:19 PM PDT 24 Aug 05 09:22:05 PM PDT 24 15016776800 ps
T301 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2828676565 Aug 05 08:05:25 PM PDT 24 Aug 05 08:42:12 PM PDT 24 15927798694 ps
T1056 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3682384375 Aug 05 08:12:40 PM PDT 24 Aug 05 08:32:33 PM PDT 24 9579877158 ps
T1057 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.401757906 Aug 05 08:36:49 PM PDT 24 Aug 05 08:48:51 PM PDT 24 4109142216 ps
T1058 /workspace/coverage/default/0.rom_e2e_asm_init_prod.4207265402 Aug 05 08:11:40 PM PDT 24 Aug 05 09:21:06 PM PDT 24 15068936715 ps
T764 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1978345989 Aug 05 08:41:55 PM PDT 24 Aug 05 08:48:26 PM PDT 24 3921346376 ps
T1059 /workspace/coverage/default/0.rom_keymgr_functest.1994285572 Aug 05 08:09:04 PM PDT 24 Aug 05 08:16:40 PM PDT 24 4813609972 ps
T1060 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1825909443 Aug 05 08:16:01 PM PDT 24 Aug 05 08:24:29 PM PDT 24 7675572760 ps
T718 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3885231290 Aug 05 08:41:10 PM PDT 24 Aug 05 08:48:00 PM PDT 24 3687633350 ps
T231 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3632207814 Aug 05 08:20:36 PM PDT 24 Aug 05 08:50:50 PM PDT 24 22535859341 ps
T310 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1590466732 Aug 05 08:11:14 PM PDT 24 Aug 05 08:24:30 PM PDT 24 5166476680 ps
T1061 /workspace/coverage/default/0.chip_sw_edn_kat.3004974075 Aug 05 08:08:21 PM PDT 24 Aug 05 08:17:03 PM PDT 24 3163611160 ps
T317 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4106551752 Aug 05 08:32:01 PM PDT 24 Aug 05 08:43:13 PM PDT 24 4408028242 ps
T1062 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3139585082 Aug 05 08:02:28 PM PDT 24 Aug 05 08:10:35 PM PDT 24 7009021640 ps
T1063 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.910364000 Aug 05 08:06:21 PM PDT 24 Aug 05 08:15:20 PM PDT 24 5351941862 ps
T286 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4049767415 Aug 05 08:29:22 PM PDT 24 Aug 05 08:36:32 PM PDT 24 5331468600 ps
T662 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.801960698 Aug 05 08:35:43 PM PDT 24 Aug 05 08:41:14 PM PDT 24 3438905798 ps
T1064 /workspace/coverage/default/1.rom_e2e_shutdown_output.1760121108 Aug 05 08:23:08 PM PDT 24 Aug 05 09:21:22 PM PDT 24 32912060034 ps
T712 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2248577003 Aug 05 08:06:20 PM PDT 24 Aug 05 08:12:52 PM PDT 24 3863114712 ps
T685 /workspace/coverage/default/58.chip_sw_all_escalation_resets.3280281641 Aug 05 08:40:41 PM PDT 24 Aug 05 08:50:05 PM PDT 24 6597258888 ps
T1065 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1963239930 Aug 05 08:24:30 PM PDT 24 Aug 05 08:29:18 PM PDT 24 3071892880 ps
T265 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.345797276 Aug 05 08:17:19 PM PDT 24 Aug 05 08:29:28 PM PDT 24 5517629146 ps
T1066 /workspace/coverage/default/0.chip_sw_edn_sw_mode.621240925 Aug 05 08:03:26 PM PDT 24 Aug 05 08:29:25 PM PDT 24 6457280108 ps
T71 /workspace/coverage/default/0.chip_tap_straps_testunlock0.2368981519 Aug 05 08:05:41 PM PDT 24 Aug 05 08:12:11 PM PDT 24 4058711679 ps
T1067 /workspace/coverage/default/4.chip_sw_uart_tx_rx.4181327937 Aug 05 08:34:38 PM PDT 24 Aug 05 08:44:55 PM PDT 24 4263651584 ps
T1068 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3172246912 Aug 05 08:27:02 PM PDT 24 Aug 05 08:49:28 PM PDT 24 7988218300 ps
T666 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1706266660 Aug 05 08:42:22 PM PDT 24 Aug 05 08:48:36 PM PDT 24 3829644200 ps
T1069 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.1737510574 Aug 05 08:05:20 PM PDT 24 Aug 05 08:10:50 PM PDT 24 3249439548 ps
T768 /workspace/coverage/default/84.chip_sw_all_escalation_resets.2713783248 Aug 05 08:42:35 PM PDT 24 Aug 05 08:51:53 PM PDT 24 4877495458 ps
T1070 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.2901991452 Aug 05 08:25:24 PM PDT 24 Aug 05 08:38:36 PM PDT 24 5858890504 ps
T775 /workspace/coverage/default/37.chip_sw_all_escalation_resets.1820264574 Aug 05 08:38:59 PM PDT 24 Aug 05 08:49:06 PM PDT 24 5919931632 ps
T213 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1133426382 Aug 05 08:01:44 PM PDT 24 Aug 05 11:50:17 PM PDT 24 78134070620 ps
T46 /workspace/coverage/default/0.chip_sw_alert_test.2999765541 Aug 05 08:05:03 PM PDT 24 Aug 05 08:10:06 PM PDT 24 3086164688 ps
T1071 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1578217544 Aug 05 08:27:47 PM PDT 24 Aug 05 08:32:54 PM PDT 24 3347839680 ps
T1072 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3032177600 Aug 05 08:32:07 PM PDT 24 Aug 05 08:39:18 PM PDT 24 6323610846 ps
T752 /workspace/coverage/default/46.chip_sw_all_escalation_resets.1624180097 Aug 05 08:39:42 PM PDT 24 Aug 05 08:48:13 PM PDT 24 5483499548 ps
T199 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.2153161002 Aug 05 08:02:25 PM PDT 24 Aug 05 08:11:36 PM PDT 24 5729926839 ps
T1073 /workspace/coverage/default/0.chip_sw_rv_timer_irq.3714352906 Aug 05 08:07:56 PM PDT 24 Aug 05 08:11:15 PM PDT 24 2943391450 ps
T53 /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.499968064 Aug 05 08:06:21 PM PDT 24 Aug 05 08:11:22 PM PDT 24 3577913727 ps
T318 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.976167076 Aug 05 08:19:34 PM PDT 24 Aug 05 08:29:23 PM PDT 24 4959614832 ps
T49 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1941947958 Aug 05 08:22:31 PM PDT 24 Aug 05 08:28:25 PM PDT 24 4534799284 ps
T1074 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.947674382 Aug 05 08:03:00 PM PDT 24 Aug 05 09:38:14 PM PDT 24 51140235049 ps
T765 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3026047252 Aug 05 08:40:43 PM PDT 24 Aug 05 08:47:14 PM PDT 24 3571307452 ps
T1075 /workspace/coverage/default/74.chip_sw_all_escalation_resets.581681357 Aug 05 08:41:17 PM PDT 24 Aug 05 08:48:57 PM PDT 24 4566586260 ps
T1076 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.475697496 Aug 05 08:34:36 PM PDT 24 Aug 05 08:45:04 PM PDT 24 4086948782 ps
T1077 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.641347790 Aug 05 08:04:08 PM PDT 24 Aug 05 08:16:11 PM PDT 24 7655728596 ps
T1078 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1352509259 Aug 05 08:13:09 PM PDT 24 Aug 05 08:31:13 PM PDT 24 6209519393 ps
T1079 /workspace/coverage/default/2.chip_sw_uart_smoketest.260014644 Aug 05 08:32:57 PM PDT 24 Aug 05 08:36:55 PM PDT 24 2510634624 ps
T332 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.176581721 Aug 05 08:02:33 PM PDT 24 Aug 05 08:17:38 PM PDT 24 6137847054 ps
T776 /workspace/coverage/default/30.chip_sw_all_escalation_resets.1065577351 Aug 05 08:39:03 PM PDT 24 Aug 05 08:50:10 PM PDT 24 5367696400 ps
T1080 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.4127208668 Aug 05 08:35:31 PM PDT 24 Aug 05 08:44:43 PM PDT 24 5069473830 ps
T149 /workspace/coverage/default/0.chip_sw_usbdev_dpi.3505949464 Aug 05 08:05:33 PM PDT 24 Aug 05 08:57:25 PM PDT 24 12549946288 ps
T1081 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1163134727 Aug 05 08:41:15 PM PDT 24 Aug 05 08:49:31 PM PDT 24 3882239384 ps
T1082 /workspace/coverage/default/1.chip_sw_flash_init.4205158914 Aug 05 08:10:59 PM PDT 24 Aug 05 08:46:02 PM PDT 24 24698924780 ps
T1083 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1463097596 Aug 05 08:03:47 PM PDT 24 Aug 05 08:13:12 PM PDT 24 4794865720 ps
T1084 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3109696782 Aug 05 08:33:00 PM PDT 24 Aug 05 08:45:04 PM PDT 24 4269820424 ps
T1085 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1430798600 Aug 05 08:05:18 PM PDT 24 Aug 05 08:11:10 PM PDT 24 3689173118 ps
T266 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2494274790 Aug 05 08:15:49 PM PDT 24 Aug 05 08:23:15 PM PDT 24 4332983479 ps
T684 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.62819295 Aug 05 08:37:18 PM PDT 24 Aug 05 08:43:40 PM PDT 24 4167454322 ps
T1086 /workspace/coverage/default/4.chip_tap_straps_dev.3384493146 Aug 05 08:32:48 PM PDT 24 Aug 05 08:38:23 PM PDT 24 3470764339 ps
T686 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1195060796 Aug 05 08:42:36 PM PDT 24 Aug 05 08:48:46 PM PDT 24 4120515032 ps
T1087 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3678964549 Aug 05 08:04:32 PM PDT 24 Aug 05 08:10:01 PM PDT 24 3563495694 ps
T1088 /workspace/coverage/default/2.chip_sw_gpio_smoketest.444518734 Aug 05 08:32:03 PM PDT 24 Aug 05 08:36:36 PM PDT 24 2514260471 ps
T1089 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3009698150 Aug 05 08:41:04 PM PDT 24 Aug 05 08:47:51 PM PDT 24 3537456088 ps
T342 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.155811020 Aug 05 08:13:11 PM PDT 24 Aug 05 08:26:38 PM PDT 24 4941679458 ps
T1090 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.882480505 Aug 05 08:13:13 PM PDT 24 Aug 05 09:57:37 PM PDT 24 23819994625 ps
T1091 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3339276224 Aug 05 08:25:36 PM PDT 24 Aug 05 08:40:49 PM PDT 24 9744750952 ps
T1092 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.840156860 Aug 05 08:05:22 PM PDT 24 Aug 05 08:25:46 PM PDT 24 8403628157 ps
T1093 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.522907446 Aug 05 08:06:01 PM PDT 24 Aug 05 08:49:36 PM PDT 24 12178452787 ps
T1094 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.2593372825 Aug 05 08:30:13 PM PDT 24 Aug 05 08:51:40 PM PDT 24 12777765286 ps
T51 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2829180238 Aug 05 08:03:41 PM PDT 24 Aug 05 08:08:23 PM PDT 24 3237039760 ps
T392 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1370533440 Aug 05 08:29:22 PM PDT 24 Aug 05 08:38:21 PM PDT 24 7838304550 ps
T1095 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.126546324 Aug 05 08:07:58 PM PDT 24 Aug 05 08:44:37 PM PDT 24 11153414756 ps
T1096 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.236198446 Aug 05 08:30:27 PM PDT 24 Aug 05 08:43:04 PM PDT 24 4949566440 ps
T1097 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1938498849 Aug 05 08:07:31 PM PDT 24 Aug 05 08:14:32 PM PDT 24 5101223720 ps
T1098 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2407097201 Aug 05 08:10:16 PM PDT 24 Aug 05 08:16:15 PM PDT 24 5696570908 ps
T175 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3766845156 Aug 05 08:02:52 PM PDT 24 Aug 05 08:05:44 PM PDT 24 3167563525 ps
T690 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2226326418 Aug 05 08:40:22 PM PDT 24 Aug 05 08:47:03 PM PDT 24 4296392360 ps
T1099 /workspace/coverage/default/0.chip_sw_csrng_smoketest.1069074545 Aug 05 08:09:01 PM PDT 24 Aug 05 08:13:48 PM PDT 24 3408351876 ps
T248 /workspace/coverage/default/96.chip_sw_all_escalation_resets.1540063743 Aug 05 08:45:09 PM PDT 24 Aug 05 08:53:02 PM PDT 24 5623735200 ps
T1100 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.243159623 Aug 05 08:25:38 PM PDT 24 Aug 05 08:42:13 PM PDT 24 5209677236 ps
T1101 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2391519690 Aug 05 08:17:32 PM PDT 24 Aug 05 08:27:41 PM PDT 24 3563958900 ps
T343 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3108360263 Aug 05 08:22:12 PM PDT 24 Aug 05 08:33:19 PM PDT 24 4504415775 ps
T697 /workspace/coverage/default/27.chip_sw_all_escalation_resets.1989842035 Aug 05 08:37:35 PM PDT 24 Aug 05 08:48:27 PM PDT 24 5213057528 ps
T31 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2677157501 Aug 05 08:03:43 PM PDT 24 Aug 05 08:12:16 PM PDT 24 6048462080 ps
T1102 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2419659015 Aug 05 08:26:38 PM PDT 24 Aug 05 08:31:15 PM PDT 24 2904384520 ps
T1103 /workspace/coverage/default/2.chip_sw_aes_smoketest.764517460 Aug 05 08:31:50 PM PDT 24 Aug 05 08:37:13 PM PDT 24 2981757640 ps
T1104 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.908975876 Aug 05 08:24:35 PM PDT 24 Aug 05 08:29:08 PM PDT 24 3101270965 ps
T163 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.4020897104 Aug 05 08:01:47 PM PDT 24 Aug 05 08:12:17 PM PDT 24 4783885604 ps
T754 /workspace/coverage/default/19.chip_sw_all_escalation_resets.3143366345 Aug 05 08:36:57 PM PDT 24 Aug 05 08:45:14 PM PDT 24 5396538500 ps
T1105 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1918589432 Aug 05 08:33:38 PM PDT 24 Aug 05 08:44:38 PM PDT 24 7797583784 ps
T1106 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2218492840 Aug 05 08:05:24 PM PDT 24 Aug 05 09:20:58 PM PDT 24 18615624120 ps
T1107 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2863895629 Aug 05 08:20:19 PM PDT 24 Aug 05 08:39:55 PM PDT 24 8033670438 ps
T1108 /workspace/coverage/default/1.rom_e2e_asm_init_rma.521905150 Aug 05 08:30:28 PM PDT 24 Aug 05 09:30:50 PM PDT 24 14939810480 ps
T730 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2312429163 Aug 05 08:39:21 PM PDT 24 Aug 05 08:44:42 PM PDT 24 3544015240 ps
T1109 /workspace/coverage/default/0.rom_e2e_asm_init_dev.3639105649 Aug 05 08:12:30 PM PDT 24 Aug 05 09:18:53 PM PDT 24 15589659260 ps
T380 /workspace/coverage/default/0.chip_sw_kmac_app_rom.3234767681 Aug 05 08:04:10 PM PDT 24 Aug 05 08:07:47 PM PDT 24 2409765976 ps
T1110 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2925313328 Aug 05 08:02:40 PM PDT 24 Aug 05 08:19:59 PM PDT 24 5459739948 ps
T176 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3171412461 Aug 05 08:02:27 PM PDT 24 Aug 05 08:08:16 PM PDT 24 4171194097 ps
T1111 /workspace/coverage/default/3.chip_tap_straps_dev.1101550841 Aug 05 08:34:47 PM PDT 24 Aug 05 08:40:53 PM PDT 24 3169459553 ps
T635 /workspace/coverage/default/1.rom_volatile_raw_unlock.1478540880 Aug 05 08:19:46 PM PDT 24 Aug 05 08:21:30 PM PDT 24 2681538821 ps
T1112 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1533127557 Aug 05 08:26:53 PM PDT 24 Aug 05 08:29:12 PM PDT 24 2593118369 ps
T1113 /workspace/coverage/default/2.chip_sw_aon_timer_irq.2421262559 Aug 05 08:24:35 PM PDT 24 Aug 05 08:32:10 PM PDT 24 3665310180 ps
T761 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.4083381958 Aug 05 08:40:41 PM PDT 24 Aug 05 08:46:33 PM PDT 24 3453150314 ps
T112 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2003837070 Aug 05 08:29:36 PM PDT 24 Aug 05 08:52:39 PM PDT 24 22956834736 ps
T704 /workspace/coverage/default/91.chip_sw_all_escalation_resets.1188653802 Aug 05 08:43:25 PM PDT 24 Aug 05 08:51:59 PM PDT 24 4807833982 ps
T1114 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3972682382 Aug 05 08:14:54 PM PDT 24 Aug 05 08:45:12 PM PDT 24 6694386816 ps
T731 /workspace/coverage/default/49.chip_sw_all_escalation_resets.3855775839 Aug 05 08:40:41 PM PDT 24 Aug 05 08:51:08 PM PDT 24 6176637120 ps
T1115 /workspace/coverage/default/80.chip_sw_all_escalation_resets.644431783 Aug 05 08:40:52 PM PDT 24 Aug 05 08:47:32 PM PDT 24 4721436790 ps
T1116 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3842005292 Aug 05 08:21:56 PM PDT 24 Aug 05 08:34:44 PM PDT 24 5572793820 ps
T1117 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2665023184 Aug 05 08:40:55 PM PDT 24 Aug 05 08:47:08 PM PDT 24 3218863384 ps
T748 /workspace/coverage/default/78.chip_sw_all_escalation_resets.4166465874 Aug 05 08:42:09 PM PDT 24 Aug 05 08:50:24 PM PDT 24 5174635248 ps
T393 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.588494375 Aug 05 08:29:59 PM PDT 24 Aug 05 08:54:48 PM PDT 24 26358311792 ps
T1118 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.4031228270 Aug 05 08:37:36 PM PDT 24 Aug 05 09:12:10 PM PDT 24 12672510228 ps
T1119 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3664574288 Aug 05 08:04:14 PM PDT 24 Aug 05 08:11:27 PM PDT 24 3659641364 ps
T1120 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2826572505 Aug 05 08:14:13 PM PDT 24 Aug 05 08:26:11 PM PDT 24 6047537991 ps
T1121 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2038792391 Aug 05 08:32:31 PM PDT 24 Aug 05 08:36:07 PM PDT 24 2363647140 ps
T1122 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1818035816 Aug 05 08:18:19 PM PDT 24 Aug 05 08:25:43 PM PDT 24 3391720600 ps
T699 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3405269134 Aug 05 08:39:07 PM PDT 24 Aug 05 08:45:07 PM PDT 24 4188338408 ps
T146 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2503368651 Aug 05 08:24:58 PM PDT 24 Aug 05 08:33:38 PM PDT 24 9047328030 ps
T1123 /workspace/coverage/default/0.chip_sw_otbn_smoketest.2316637153 Aug 05 08:07:28 PM PDT 24 Aug 05 08:43:37 PM PDT 24 9219161400 ps
T1124 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2158275687 Aug 05 08:05:30 PM PDT 24 Aug 05 08:09:02 PM PDT 24 2490294919 ps
T1125 /workspace/coverage/default/0.chip_sival_flash_info_access.2593364525 Aug 05 08:01:56 PM PDT 24 Aug 05 08:06:48 PM PDT 24 3306627152 ps
T1126 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2227478164 Aug 05 08:24:45 PM PDT 24 Aug 05 08:31:58 PM PDT 24 18653974264 ps
T1127 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.710890304 Aug 05 08:06:12 PM PDT 24 Aug 05 08:10:39 PM PDT 24 3513021044 ps
T1128 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.275485858 Aug 05 08:21:43 PM PDT 24 Aug 05 08:26:23 PM PDT 24 2760170992 ps
T1129 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3396664329 Aug 05 08:05:11 PM PDT 24 Aug 05 08:51:34 PM PDT 24 26610199062 ps
T1130 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2419923954 Aug 05 08:29:31 PM PDT 24 Aug 05 08:36:49 PM PDT 24 3002416448 ps
T1131 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2842108415 Aug 05 08:10:01 PM PDT 24 Aug 05 08:14:26 PM PDT 24 3210246650 ps
T736 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2501991237 Aug 05 08:41:26 PM PDT 24 Aug 05 08:48:50 PM PDT 24 3774852504 ps
T1132 /workspace/coverage/default/95.chip_sw_all_escalation_resets.687304319 Aug 05 08:43:42 PM PDT 24 Aug 05 08:52:31 PM PDT 24 5731537248 ps
T1133 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.4083846530 Aug 05 08:08:19 PM PDT 24 Aug 05 08:17:33 PM PDT 24 3000871530 ps
T315 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.4287236439 Aug 05 08:19:46 PM PDT 24 Aug 05 08:28:13 PM PDT 24 4504621564 ps
T1134 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2166845498 Aug 05 08:13:28 PM PDT 24 Aug 05 08:32:22 PM PDT 24 10257722884 ps
T1135 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.110920947 Aug 05 08:23:52 PM PDT 24 Aug 05 08:27:32 PM PDT 24 2898579040 ps
T316 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1177828526 Aug 05 08:07:19 PM PDT 24 Aug 05 08:15:23 PM PDT 24 3622873864 ps
T1136 /workspace/coverage/default/3.chip_tap_straps_rma.1855518452 Aug 05 08:33:11 PM PDT 24 Aug 05 08:51:40 PM PDT 24 9980748090 ps
T1137 /workspace/coverage/default/0.chip_sw_uart_smoketest.483723584 Aug 05 08:09:12 PM PDT 24 Aug 05 08:13:36 PM PDT 24 2806502120 ps
T249 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2496859033 Aug 05 08:13:15 PM PDT 24 Aug 05 08:25:07 PM PDT 24 4896370168 ps
T1138 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3373659352 Aug 05 08:31:38 PM PDT 24 Aug 05 08:36:28 PM PDT 24 2680810071 ps
T345 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3065247521 Aug 05 08:12:56 PM PDT 24 Aug 05 11:08:59 PM PDT 24 58986754732 ps
T274 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1508398654 Aug 05 08:05:14 PM PDT 24 Aug 05 08:09:52 PM PDT 24 3044961522 ps
T1139 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.4066610607 Aug 05 08:08:05 PM PDT 24 Aug 05 08:18:32 PM PDT 24 7741298875 ps
T1140 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3169386535 Aug 05 08:12:02 PM PDT 24 Aug 05 09:25:40 PM PDT 24 15142505304 ps
T91 /workspace/coverage/default/45.chip_sw_all_escalation_resets.714261364 Aug 05 08:40:32 PM PDT 24 Aug 05 08:50:11 PM PDT 24 4888715584 ps
T1141 /workspace/coverage/default/2.chip_sw_kmac_entropy.109878700 Aug 05 08:22:39 PM PDT 24 Aug 05 08:27:00 PM PDT 24 2581981496 ps
T1142 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2809371069 Aug 05 08:03:46 PM PDT 24 Aug 05 08:08:13 PM PDT 24 3092766798 ps
T1143 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2741615474 Aug 05 08:32:44 PM PDT 24 Aug 05 09:16:26 PM PDT 24 13177980935 ps
T135 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2886422810 Aug 05 08:16:20 PM PDT 24 Aug 05 08:34:50 PM PDT 24 6575349024 ps
T1144 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3813988451 Aug 05 08:04:26 PM PDT 24 Aug 05 08:35:30 PM PDT 24 7939537676 ps
T1145 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3049898870 Aug 05 08:10:50 PM PDT 24 Aug 05 08:21:22 PM PDT 24 4622938440 ps
T657 /workspace/coverage/default/0.chip_sw_pattgen_ios.1901790059 Aug 05 08:02:44 PM PDT 24 Aug 05 08:07:49 PM PDT 24 2358336860 ps
T1146 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3949368958 Aug 05 08:01:49 PM PDT 24 Aug 05 09:27:47 PM PDT 24 43360620299 ps
T1147 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3630684209 Aug 05 08:13:25 PM PDT 24 Aug 05 08:21:14 PM PDT 24 3615424988 ps
T1148 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.705036147 Aug 05 08:40:49 PM PDT 24 Aug 05 08:46:44 PM PDT 24 3690397150 ps
T1149 /workspace/coverage/default/1.rom_e2e_asm_init_prod.1854847129 Aug 05 08:23:48 PM PDT 24 Aug 05 09:21:54 PM PDT 24 16065333370 ps
T1150 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.796266279 Aug 05 08:12:57 PM PDT 24 Aug 05 08:21:24 PM PDT 24 6700070160 ps
T275 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2074192445 Aug 05 08:29:25 PM PDT 24 Aug 05 08:33:19 PM PDT 24 3673802708 ps
T1151 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3244311927 Aug 05 08:28:01 PM PDT 24 Aug 05 09:07:57 PM PDT 24 29943417014 ps
T1152 /workspace/coverage/default/0.chip_sw_kmac_entropy.3067466199 Aug 05 08:05:44 PM PDT 24 Aug 05 08:09:07 PM PDT 24 2617416056 ps
T1153 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3201916305 Aug 05 08:20:58 PM PDT 24 Aug 05 08:27:09 PM PDT 24 3528778087 ps
T1154 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.723120989 Aug 05 08:18:08 PM PDT 24 Aug 05 08:28:57 PM PDT 24 4684730944 ps
T333 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.68020731 Aug 05 08:10:54 PM PDT 24 Aug 05 08:22:42 PM PDT 24 4808656012 ps
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