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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.21 95.58 94.17 95.38 95.01 97.53 99.60


Total test records in report: 2944
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T1155 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.855414700 Aug 05 08:28:18 PM PDT 24 Aug 05 08:36:06 PM PDT 24 9045244072 ps
T1156 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3535797571 Aug 05 08:28:04 PM PDT 24 Aug 05 08:32:03 PM PDT 24 3003059433 ps
T1157 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2204254426 Aug 05 08:13:35 PM PDT 24 Aug 05 09:18:19 PM PDT 24 18447282116 ps
T1158 /workspace/coverage/default/2.chip_sw_edn_kat.769373463 Aug 05 08:27:28 PM PDT 24 Aug 05 08:39:51 PM PDT 24 3138861192 ps
T200 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2697893274 Aug 05 08:13:33 PM PDT 24 Aug 05 08:24:00 PM PDT 24 5123822590 ps
T1159 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1708239679 Aug 05 08:22:55 PM PDT 24 Aug 05 08:25:42 PM PDT 24 4065490222 ps
T1160 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.573940745 Aug 05 08:04:18 PM PDT 24 Aug 05 08:20:49 PM PDT 24 5788991116 ps
T1161 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.4235451491 Aug 05 08:34:07 PM PDT 24 Aug 05 08:46:33 PM PDT 24 12244109838 ps
T654 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.4085862130 Aug 05 08:10:20 PM PDT 24 Aug 05 09:01:28 PM PDT 24 31998201086 ps
T1162 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.2317040772 Aug 05 08:11:41 PM PDT 24 Aug 05 09:37:34 PM PDT 24 45144884901 ps
T1163 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3285973216 Aug 05 08:39:38 PM PDT 24 Aug 05 08:48:42 PM PDT 24 3668190400 ps
T1164 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.257291347 Aug 05 08:03:23 PM PDT 24 Aug 05 08:05:39 PM PDT 24 3086847866 ps
T1165 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1105293840 Aug 05 08:24:18 PM PDT 24 Aug 05 08:43:25 PM PDT 24 6120081592 ps
T1166 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1135169816 Aug 05 08:10:29 PM PDT 24 Aug 05 09:07:51 PM PDT 24 14209819055 ps
T1167 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3181771896 Aug 05 08:34:07 PM PDT 24 Aug 05 08:58:30 PM PDT 24 7583824058 ps
T1168 /workspace/coverage/default/0.chip_sw_example_concurrency.2522705650 Aug 05 08:02:12 PM PDT 24 Aug 05 08:06:44 PM PDT 24 2899416592 ps
T1169 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3003862749 Aug 05 08:24:30 PM PDT 24 Aug 05 08:35:42 PM PDT 24 4129046488 ps
T1170 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1247132422 Aug 05 08:26:30 PM PDT 24 Aug 05 08:32:21 PM PDT 24 2398324609 ps
T1171 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1501792685 Aug 05 08:05:14 PM PDT 24 Aug 05 08:12:38 PM PDT 24 3051355906 ps
T1172 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.159177597 Aug 05 08:21:46 PM PDT 24 Aug 05 08:26:57 PM PDT 24 5742405984 ps
T772 /workspace/coverage/default/52.chip_sw_all_escalation_resets.2554485153 Aug 05 08:40:27 PM PDT 24 Aug 05 08:52:14 PM PDT 24 6208448964 ps
T1173 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1099431855 Aug 05 08:38:19 PM PDT 24 Aug 05 09:54:53 PM PDT 24 19780188590 ps
T640 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3600819821 Aug 05 08:15:06 PM PDT 24 Aug 05 08:20:11 PM PDT 24 3637408102 ps
T688 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.4089441671 Aug 05 08:15:25 PM PDT 24 Aug 05 08:24:15 PM PDT 24 3422393192 ps
T319 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1734941774 Aug 05 08:05:40 PM PDT 24 Aug 05 08:17:20 PM PDT 24 5260308532 ps
T1174 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.4162238727 Aug 05 08:14:56 PM PDT 24 Aug 05 09:03:25 PM PDT 24 11356509440 ps
T201 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2124235203 Aug 05 08:22:23 PM PDT 24 Aug 05 08:35:02 PM PDT 24 4713775134 ps
T269 /workspace/coverage/default/38.chip_sw_all_escalation_resets.358863589 Aug 05 08:42:12 PM PDT 24 Aug 05 08:57:01 PM PDT 24 5644361680 ps
T1175 /workspace/coverage/default/2.chip_sw_kmac_smoketest.1953346732 Aug 05 08:32:27 PM PDT 24 Aug 05 08:37:52 PM PDT 24 3724593848 ps
T1176 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2855714752 Aug 05 08:35:06 PM PDT 24 Aug 05 09:15:17 PM PDT 24 12827383564 ps
T1177 /workspace/coverage/default/2.chip_sw_aes_masking_off.477754739 Aug 05 08:27:55 PM PDT 24 Aug 05 08:33:51 PM PDT 24 3004985016 ps
T656 /workspace/coverage/default/2.chip_sw_pattgen_ios.2665643776 Aug 05 08:22:39 PM PDT 24 Aug 05 08:26:18 PM PDT 24 2577610840 ps
T1178 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2768659100 Aug 05 08:42:49 PM PDT 24 Aug 05 08:48:38 PM PDT 24 3622984200 ps
T1179 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2801205152 Aug 05 08:03:36 PM PDT 24 Aug 05 08:28:13 PM PDT 24 16002719860 ps
T290 /workspace/coverage/default/39.chip_sw_all_escalation_resets.399807395 Aug 05 08:39:19 PM PDT 24 Aug 05 08:49:53 PM PDT 24 5550959804 ps
T250 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1157347775 Aug 05 08:24:21 PM PDT 24 Aug 05 08:35:50 PM PDT 24 7051481032 ps
T298 /workspace/coverage/default/2.chip_plic_all_irqs_20.20712122 Aug 05 08:30:25 PM PDT 24 Aug 05 08:47:40 PM PDT 24 5068330750 ps
T732 /workspace/coverage/default/82.chip_sw_all_escalation_resets.2682870021 Aug 05 08:43:02 PM PDT 24 Aug 05 08:53:18 PM PDT 24 5628749968 ps
T1180 /workspace/coverage/default/1.chip_sw_csrng_smoketest.2123653145 Aug 05 08:20:38 PM PDT 24 Aug 05 08:24:29 PM PDT 24 2493922398 ps
T1181 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4038707732 Aug 05 08:18:59 PM PDT 24 Aug 05 08:28:48 PM PDT 24 3814910888 ps
T1182 /workspace/coverage/default/2.chip_sw_flash_init.3988485438 Aug 05 08:21:33 PM PDT 24 Aug 05 08:52:47 PM PDT 24 15739847000 ps
T1183 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.754686424 Aug 05 08:11:05 PM PDT 24 Aug 05 08:18:54 PM PDT 24 5806003530 ps
T1184 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2846174938 Aug 05 08:20:24 PM PDT 24 Aug 05 08:24:38 PM PDT 24 3344818349 ps
T1185 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.4105856371 Aug 05 08:35:51 PM PDT 24 Aug 05 08:44:05 PM PDT 24 6059153791 ps
T1186 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2764555883 Aug 05 08:34:30 PM PDT 24 Aug 05 08:41:59 PM PDT 24 6744022079 ps
T1187 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1653673316 Aug 05 08:09:47 PM PDT 24 Aug 05 08:17:09 PM PDT 24 2868691792 ps
T1188 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2109347105 Aug 05 08:03:19 PM PDT 24 Aug 05 08:11:40 PM PDT 24 5844852759 ps
T1189 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.4224599406 Aug 05 08:35:42 PM PDT 24 Aug 05 08:39:17 PM PDT 24 2782028312 ps
T138 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3012315121 Aug 05 08:05:49 PM PDT 24 Aug 05 08:13:10 PM PDT 24 4884436200 ps
T270 /workspace/coverage/default/12.chip_sw_all_escalation_resets.1469262279 Aug 05 08:37:22 PM PDT 24 Aug 05 08:46:56 PM PDT 24 4738876220 ps
T1190 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2462322541 Aug 05 08:37:08 PM PDT 24 Aug 05 08:45:39 PM PDT 24 4330616790 ps
T1191 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3265003115 Aug 05 08:36:26 PM PDT 24 Aug 05 09:29:47 PM PDT 24 14935638730 ps
T1192 /workspace/coverage/default/2.chip_sw_csrng_smoketest.767788199 Aug 05 08:31:59 PM PDT 24 Aug 05 08:35:18 PM PDT 24 2942298856 ps
T769 /workspace/coverage/default/92.chip_sw_all_escalation_resets.3305143867 Aug 05 08:43:53 PM PDT 24 Aug 05 08:52:55 PM PDT 24 5472433352 ps
T1193 /workspace/coverage/default/2.chip_sw_example_concurrency.2477995633 Aug 05 08:20:24 PM PDT 24 Aug 05 08:24:45 PM PDT 24 2653707844 ps
T1194 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1027000054 Aug 05 08:12:44 PM PDT 24 Aug 05 08:20:57 PM PDT 24 7163819128 ps
T1195 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2790396905 Aug 05 08:05:21 PM PDT 24 Aug 05 08:26:17 PM PDT 24 6630001264 ps
T291 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.381269730 Aug 05 08:42:29 PM PDT 24 Aug 05 08:47:46 PM PDT 24 3213819962 ps
T1196 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.4180726031 Aug 05 08:16:21 PM PDT 24 Aug 05 08:26:02 PM PDT 24 6981593084 ps
T1197 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1339534170 Aug 05 08:29:03 PM PDT 24 Aug 05 08:37:28 PM PDT 24 5886127300 ps
T770 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.4190936957 Aug 05 08:38:15 PM PDT 24 Aug 05 08:43:26 PM PDT 24 4312500120 ps
T394 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1295323000 Aug 05 08:07:28 PM PDT 24 Aug 05 08:37:29 PM PDT 24 23037852464 ps
T32 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.334002205 Aug 05 08:14:18 PM PDT 24 Aug 05 08:23:28 PM PDT 24 6368160844 ps
T1198 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3366470618 Aug 05 08:03:01 PM PDT 24 Aug 05 08:20:02 PM PDT 24 9711131532 ps
T1199 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.430019203 Aug 05 08:37:13 PM PDT 24 Aug 05 08:44:17 PM PDT 24 3370315958 ps
T1200 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2227822163 Aug 05 08:21:34 PM PDT 24 Aug 05 09:36:19 PM PDT 24 42375747852 ps
T346 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.3828043409 Aug 05 08:12:34 PM PDT 24 Aug 05 11:33:04 PM PDT 24 64458476537 ps
T186 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1343535163 Aug 05 08:04:32 PM PDT 24 Aug 05 08:12:55 PM PDT 24 5647898498 ps
T1201 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.4076250301 Aug 05 08:25:57 PM PDT 24 Aug 05 08:50:27 PM PDT 24 8715246122 ps
T223 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.4211992299 Aug 05 08:16:37 PM PDT 24 Aug 05 09:28:07 PM PDT 24 16420670982 ps
T1202 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2858895523 Aug 05 08:12:37 PM PDT 24 Aug 05 08:26:17 PM PDT 24 8851994700 ps
T10 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1246008911 Aug 05 08:21:45 PM PDT 24 Aug 05 08:27:10 PM PDT 24 2445768979 ps
T1203 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.4257136323 Aug 05 08:24:39 PM PDT 24 Aug 05 08:38:41 PM PDT 24 5016723600 ps
T1204 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3148494717 Aug 05 08:17:41 PM PDT 24 Aug 05 08:23:35 PM PDT 24 4405050188 ps
T668 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.320565863 Aug 05 08:41:31 PM PDT 24 Aug 05 08:48:38 PM PDT 24 3487425160 ps
T757 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1735873015 Aug 05 08:46:44 PM PDT 24 Aug 05 08:51:59 PM PDT 24 3527175752 ps
T1205 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2083815298 Aug 05 08:15:28 PM PDT 24 Aug 05 08:31:23 PM PDT 24 5243108352 ps
T1206 /workspace/coverage/default/1.chip_sw_aes_entropy.1414038905 Aug 05 08:15:10 PM PDT 24 Aug 05 08:19:45 PM PDT 24 2563912488 ps
T1207 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.756967952 Aug 05 08:21:50 PM PDT 24 Aug 05 08:32:28 PM PDT 24 3897409072 ps
T687 /workspace/coverage/default/97.chip_sw_all_escalation_resets.3106202653 Aug 05 08:44:15 PM PDT 24 Aug 05 08:54:40 PM PDT 24 5895281208 ps
T1208 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.425169098 Aug 05 08:40:58 PM PDT 24 Aug 05 08:45:58 PM PDT 24 4338849036 ps
T1209 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2386152521 Aug 05 08:34:07 PM PDT 24 Aug 05 09:02:41 PM PDT 24 13418976470 ps
T1210 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1997528999 Aug 05 08:36:12 PM PDT 24 Aug 05 08:44:09 PM PDT 24 6426384079 ps
T1211 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.469933232 Aug 05 08:14:44 PM PDT 24 Aug 05 08:45:59 PM PDT 24 24990300298 ps
T703 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.76870955 Aug 05 08:40:18 PM PDT 24 Aug 05 08:46:51 PM PDT 24 3416793260 ps
T1212 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3133482867 Aug 05 08:33:07 PM PDT 24 Aug 05 10:09:03 PM PDT 24 26993037886 ps
T1213 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2558794007 Aug 05 08:06:48 PM PDT 24 Aug 05 08:17:32 PM PDT 24 4687821470 ps
T1214 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.4218164272 Aug 05 08:30:18 PM PDT 24 Aug 05 08:36:29 PM PDT 24 5247955469 ps
T283 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.446076230 Aug 05 08:04:00 PM PDT 24 Aug 05 08:17:32 PM PDT 24 7169938847 ps
T777 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.268976547 Aug 05 08:43:25 PM PDT 24 Aug 05 08:49:44 PM PDT 24 3366312760 ps
T1215 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2521847388 Aug 05 08:12:37 PM PDT 24 Aug 05 09:46:24 PM PDT 24 24242085121 ps
T1216 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2935472763 Aug 05 08:13:34 PM PDT 24 Aug 05 08:17:11 PM PDT 24 2588873757 ps
T1217 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1716377872 Aug 05 08:03:06 PM PDT 24 Aug 05 08:10:21 PM PDT 24 9596348770 ps
T1218 /workspace/coverage/default/2.chip_tap_straps_rma.3739212177 Aug 05 08:29:24 PM PDT 24 Aug 05 08:33:35 PM PDT 24 2679070395 ps
T1219 /workspace/coverage/default/0.chip_sw_uart_tx_rx.1783874457 Aug 05 08:03:16 PM PDT 24 Aug 05 08:15:14 PM PDT 24 4405240250 ps
T713 /workspace/coverage/default/33.chip_sw_all_escalation_resets.2944901962 Aug 05 08:38:09 PM PDT 24 Aug 05 08:47:25 PM PDT 24 4476515832 ps
T1220 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.318375028 Aug 05 08:05:32 PM PDT 24 Aug 05 08:28:39 PM PDT 24 10103672345 ps
T164 /workspace/coverage/default/29.chip_sw_all_escalation_resets.662541297 Aug 05 08:40:38 PM PDT 24 Aug 05 08:52:28 PM PDT 24 5545753064 ps
T1221 /workspace/coverage/default/1.chip_sw_hmac_multistream.311205258 Aug 05 08:17:45 PM PDT 24 Aug 05 08:44:35 PM PDT 24 7406267658 ps
T1222 /workspace/coverage/default/0.rom_e2e_static_critical.3597564865 Aug 05 08:16:48 PM PDT 24 Aug 05 09:24:50 PM PDT 24 16420948380 ps
T1223 /workspace/coverage/default/2.rom_volatile_raw_unlock.925889375 Aug 05 08:33:19 PM PDT 24 Aug 05 08:35:06 PM PDT 24 1938772053 ps
T1224 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.86399294 Aug 05 08:36:40 PM PDT 24 Aug 05 08:41:36 PM PDT 24 5815065968 ps
T1225 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.777240607 Aug 05 08:21:24 PM PDT 24 Aug 05 08:29:38 PM PDT 24 4520011528 ps
T1226 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.649610287 Aug 05 08:04:57 PM PDT 24 Aug 05 08:25:34 PM PDT 24 7031949978 ps
T1227 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.546928184 Aug 05 08:21:38 PM PDT 24 Aug 05 08:33:31 PM PDT 24 3865598128 ps
T1228 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2876532252 Aug 05 08:19:19 PM PDT 24 Aug 05 08:28:35 PM PDT 24 6497003444 ps
T714 /workspace/coverage/default/85.chip_sw_all_escalation_resets.3872380793 Aug 05 08:42:17 PM PDT 24 Aug 05 08:52:48 PM PDT 24 4373412040 ps
T1229 /workspace/coverage/default/1.chip_sw_pattgen_ios.1058998075 Aug 05 08:12:36 PM PDT 24 Aug 05 08:16:17 PM PDT 24 3090269824 ps
T1230 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2973155741 Aug 05 08:26:22 PM PDT 24 Aug 05 09:18:38 PM PDT 24 20434699324 ps
T1231 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.538803320 Aug 05 08:10:06 PM PDT 24 Aug 05 09:16:09 PM PDT 24 14798630150 ps
T1232 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2648333436 Aug 05 08:37:15 PM PDT 24 Aug 05 09:04:17 PM PDT 24 9248023640 ps
T1233 /workspace/coverage/default/0.chip_sw_usbdev_vbus.3158284906 Aug 05 08:01:54 PM PDT 24 Aug 05 08:05:44 PM PDT 24 2671414836 ps
T92 /workspace/coverage/default/41.chip_sw_all_escalation_resets.2237665061 Aug 05 08:38:55 PM PDT 24 Aug 05 08:47:54 PM PDT 24 5283484192 ps
T165 /workspace/coverage/default/62.chip_sw_all_escalation_resets.3131894721 Aug 05 08:41:46 PM PDT 24 Aug 05 08:50:36 PM PDT 24 5367739736 ps
T1234 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1545874768 Aug 05 08:32:06 PM PDT 24 Aug 05 08:36:35 PM PDT 24 3473303100 ps
T1235 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3054433245 Aug 05 08:22:30 PM PDT 24 Aug 05 08:43:04 PM PDT 24 6129579544 ps
T1236 /workspace/coverage/default/1.chip_sw_edn_sw_mode.71207209 Aug 05 08:15:14 PM PDT 24 Aug 05 08:41:35 PM PDT 24 7544472788 ps
T1237 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2464631448 Aug 05 08:38:03 PM PDT 24 Aug 05 09:28:48 PM PDT 24 15228150150 ps
T1238 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3376263240 Aug 05 08:32:36 PM PDT 24 Aug 05 08:38:04 PM PDT 24 2964842190 ps
T271 /workspace/coverage/default/99.chip_sw_all_escalation_resets.3016106255 Aug 05 08:42:27 PM PDT 24 Aug 05 08:51:27 PM PDT 24 5602355320 ps
T1239 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.3371169615 Aug 05 08:21:19 PM PDT 24 Aug 05 11:31:45 PM PDT 24 64866929754 ps
T1240 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.57509628 Aug 05 08:13:11 PM PDT 24 Aug 05 08:27:19 PM PDT 24 10122916868 ps
T724 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.853467633 Aug 05 08:34:58 PM PDT 24 Aug 05 08:44:33 PM PDT 24 4116742392 ps
T1241 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4283837460 Aug 05 08:28:41 PM PDT 24 Aug 05 08:40:49 PM PDT 24 4158019312 ps
T1242 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.4227390215 Aug 05 08:08:36 PM PDT 24 Aug 05 08:12:00 PM PDT 24 2853068640 ps
T1243 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.882143907 Aug 05 08:13:19 PM PDT 24 Aug 05 08:17:56 PM PDT 24 3231141562 ps
T1244 /workspace/coverage/default/1.chip_sw_kmac_entropy.2388081716 Aug 05 08:13:41 PM PDT 24 Aug 05 08:18:26 PM PDT 24 2553363600 ps
T1245 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.4099287628 Aug 05 08:12:30 PM PDT 24 Aug 05 08:22:20 PM PDT 24 3905384096 ps
T631 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.4088982367 Aug 05 08:30:07 PM PDT 24 Aug 05 08:38:13 PM PDT 24 5453697534 ps
T1246 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.4081732700 Aug 05 08:04:12 PM PDT 24 Aug 05 08:14:34 PM PDT 24 4704814120 ps
T1247 /workspace/coverage/default/0.chip_sw_kmac_smoketest.505924597 Aug 05 08:06:58 PM PDT 24 Aug 05 08:12:00 PM PDT 24 3567985884 ps
T202 /workspace/coverage/default/2.chip_sw_power_virus.2149390406 Aug 05 08:38:57 PM PDT 24 Aug 05 08:59:47 PM PDT 24 5693596728 ps
T1248 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3155781074 Aug 05 08:14:15 PM PDT 24 Aug 05 08:32:19 PM PDT 24 6171802197 ps
T1249 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3103015064 Aug 05 08:17:12 PM PDT 24 Aug 05 11:49:38 PM PDT 24 254860878124 ps
T1250 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.71217407 Aug 05 08:37:34 PM PDT 24 Aug 05 09:01:39 PM PDT 24 7887272044 ps
T1251 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3137386732 Aug 05 08:03:33 PM PDT 24 Aug 05 08:16:10 PM PDT 24 4837483155 ps
T203 /workspace/coverage/default/1.chip_jtag_mem_access.233892692 Aug 05 08:11:32 PM PDT 24 Aug 05 08:43:45 PM PDT 24 14113466376 ps
T111 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1403899179 Aug 05 08:05:15 PM PDT 24 Aug 05 08:14:00 PM PDT 24 4919728264 ps
T1252 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1696544397 Aug 05 08:28:11 PM PDT 24 Aug 05 08:32:53 PM PDT 24 3070075582 ps
T113 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.2836285815 Aug 05 08:22:39 PM PDT 24 Aug 05 08:28:41 PM PDT 24 5676903500 ps
T1253 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3514333379 Aug 05 08:03:41 PM PDT 24 Aug 05 09:04:54 PM PDT 24 16868285978 ps
T1254 /workspace/coverage/default/1.chip_sw_gpio_smoketest.1960965165 Aug 05 08:21:26 PM PDT 24 Aug 05 08:25:16 PM PDT 24 3120798954 ps
T1255 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2268459496 Aug 05 08:29:35 PM PDT 24 Aug 05 08:42:57 PM PDT 24 4339802158 ps
T1256 /workspace/coverage/default/81.chip_sw_all_escalation_resets.4199711288 Aug 05 08:41:38 PM PDT 24 Aug 05 08:52:10 PM PDT 24 5633681500 ps
T1257 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2591617665 Aug 05 08:14:00 PM PDT 24 Aug 05 08:18:31 PM PDT 24 2350232538 ps
T1258 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3873791380 Aug 05 08:02:32 PM PDT 24 Aug 05 08:59:32 PM PDT 24 20563603732 ps
T1259 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.147143283 Aug 05 08:03:29 PM PDT 24 Aug 05 08:11:38 PM PDT 24 4085722466 ps
T1260 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.572562955 Aug 05 08:35:28 PM PDT 24 Aug 05 10:10:32 PM PDT 24 22410392480 ps
T1261 /workspace/coverage/default/1.chip_tap_straps_prod.1348591480 Aug 05 08:18:30 PM PDT 24 Aug 05 08:58:10 PM PDT 24 18845995175 ps
T1262 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1518859008 Aug 05 08:04:46 PM PDT 24 Aug 05 08:43:11 PM PDT 24 23582136170 ps
T168 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2160619226 Aug 05 08:07:06 PM PDT 24 Aug 05 08:15:34 PM PDT 24 5205941080 ps
T758 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3483315236 Aug 05 08:36:05 PM PDT 24 Aug 05 08:42:51 PM PDT 24 3578536432 ps
T1263 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2145595130 Aug 05 08:05:26 PM PDT 24 Aug 05 08:15:43 PM PDT 24 5276594264 ps
T251 /workspace/coverage/default/60.chip_sw_all_escalation_resets.973274036 Aug 05 08:40:58 PM PDT 24 Aug 05 08:50:22 PM PDT 24 4608769108 ps
T204 /workspace/coverage/default/0.chip_jtag_mem_access.1089355910 Aug 05 07:57:20 PM PDT 24 Aug 05 08:18:48 PM PDT 24 13502038500 ps
T1264 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3269671979 Aug 05 08:42:36 PM PDT 24 Aug 05 08:49:39 PM PDT 24 4381415264 ps
T1265 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.3344148272 Aug 05 08:24:14 PM PDT 24 Aug 05 09:21:12 PM PDT 24 15188875362 ps
T1266 /workspace/coverage/default/1.rom_keymgr_functest.4117055663 Aug 05 08:22:04 PM PDT 24 Aug 05 08:33:56 PM PDT 24 5512066804 ps
T1267 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3668098964 Aug 05 08:11:07 PM PDT 24 Aug 05 09:14:54 PM PDT 24 14423993416 ps
T1268 /workspace/coverage/default/0.chip_sw_coremark.2805384893 Aug 05 08:07:30 PM PDT 24 Aug 05 11:49:16 PM PDT 24 71618647912 ps
T667 /workspace/coverage/default/8.chip_sw_all_escalation_resets.3918003001 Aug 05 08:35:42 PM PDT 24 Aug 05 08:44:35 PM PDT 24 5463857720 ps
T361 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.165028885 Aug 05 08:09:07 PM PDT 24 Aug 05 08:13:59 PM PDT 24 2801184024 ps
T245 /workspace/coverage/default/1.chip_sw_plic_sw_irq.3781363560 Aug 05 08:17:24 PM PDT 24 Aug 05 08:22:16 PM PDT 24 2733918020 ps
T1269 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.4205136153 Aug 05 08:03:06 PM PDT 24 Aug 05 08:05:46 PM PDT 24 2948839793 ps
T641 /workspace/coverage/default/2.chip_sw_plic_sw_irq.564372256 Aug 05 08:27:51 PM PDT 24 Aug 05 08:31:59 PM PDT 24 2422990684 ps
T1270 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1179377771 Aug 05 08:10:36 PM PDT 24 Aug 05 08:15:15 PM PDT 24 3025667544 ps
T1271 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.195397986 Aug 05 08:14:14 PM PDT 24 Aug 05 08:22:45 PM PDT 24 3267195298 ps
T1272 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.442025155 Aug 05 08:04:46 PM PDT 24 Aug 05 08:23:14 PM PDT 24 7794673618 ps
T632 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1500016512 Aug 05 08:04:13 PM PDT 24 Aug 05 08:13:07 PM PDT 24 5607931654 ps
T1273 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1571051348 Aug 05 08:02:03 PM PDT 24 Aug 05 08:11:55 PM PDT 24 5498554000 ps
T763 /workspace/coverage/default/71.chip_sw_all_escalation_resets.2690719371 Aug 05 08:45:47 PM PDT 24 Aug 05 08:55:09 PM PDT 24 5423500472 ps
T1274 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.1660431072 Aug 05 08:18:36 PM PDT 24 Aug 05 08:33:11 PM PDT 24 8103821116 ps
T744 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2866361705 Aug 05 08:41:19 PM PDT 24 Aug 05 08:47:42 PM PDT 24 3723780100 ps
T1275 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1398474129 Aug 05 08:24:56 PM PDT 24 Aug 05 08:48:59 PM PDT 24 10524630735 ps
T1276 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1734751539 Aug 05 08:21:18 PM PDT 24 Aug 05 09:28:57 PM PDT 24 24796923081 ps
T719 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2248148342 Aug 05 08:38:20 PM PDT 24 Aug 05 08:45:28 PM PDT 24 3734670676 ps
T1277 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.2227448157 Aug 05 08:08:04 PM PDT 24 Aug 05 08:12:26 PM PDT 24 2765358902 ps
T1278 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3623522642 Aug 05 08:28:36 PM PDT 24 Aug 05 08:38:39 PM PDT 24 4043685848 ps
T1279 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.419449822 Aug 05 08:02:23 PM PDT 24 Aug 05 08:15:04 PM PDT 24 8367189886 ps
T720 /workspace/coverage/default/50.chip_sw_all_escalation_resets.3958908426 Aug 05 08:39:54 PM PDT 24 Aug 05 08:49:39 PM PDT 24 4503785712 ps
T1280 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.532290058 Aug 05 08:03:25 PM PDT 24 Aug 05 08:12:24 PM PDT 24 6669477510 ps
T695 /workspace/coverage/default/2.chip_sw_all_escalation_resets.916402381 Aug 05 08:22:29 PM PDT 24 Aug 05 08:40:27 PM PDT 24 6385611444 ps
T1281 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2075455335 Aug 05 08:12:35 PM PDT 24 Aug 05 08:21:25 PM PDT 24 4086271537 ps
T1282 /workspace/coverage/default/1.chip_sw_aes_enc.749391488 Aug 05 08:14:19 PM PDT 24 Aug 05 08:18:41 PM PDT 24 3380398276 ps
T1283 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3549478258 Aug 05 08:09:37 PM PDT 24 Aug 05 08:14:54 PM PDT 24 2572013458 ps
T161 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.120061686 Aug 05 08:22:52 PM PDT 24 Aug 05 08:26:17 PM PDT 24 2883206049 ps
T1284 /workspace/coverage/default/2.rom_keymgr_functest.3943257443 Aug 05 08:34:12 PM PDT 24 Aug 05 08:43:02 PM PDT 24 4828065536 ps
T1285 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3936517513 Aug 05 08:33:34 PM PDT 24 Aug 05 08:44:38 PM PDT 24 4960523552 ps
T1286 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.4253738913 Aug 05 08:36:53 PM PDT 24 Aug 05 08:44:09 PM PDT 24 4020839056 ps
T1287 /workspace/coverage/default/2.chip_sw_kmac_app_rom.3030854729 Aug 05 08:27:45 PM PDT 24 Aug 05 08:30:27 PM PDT 24 2110911124 ps
T1288 /workspace/coverage/default/1.chip_sw_aes_idle.1852839111 Aug 05 08:16:08 PM PDT 24 Aug 05 08:20:49 PM PDT 24 2916209400 ps
T1289 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1615650163 Aug 05 08:28:13 PM PDT 24 Aug 05 08:55:46 PM PDT 24 9037091576 ps
T1290 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1318719283 Aug 05 08:23:45 PM PDT 24 Aug 05 09:07:40 PM PDT 24 34287405506 ps
T1291 /workspace/coverage/default/2.chip_sw_aes_entropy.548979017 Aug 05 08:27:46 PM PDT 24 Aug 05 08:32:38 PM PDT 24 2874555008 ps
T54 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.1937150155 Aug 05 08:02:14 PM PDT 24 Aug 05 08:07:33 PM PDT 24 5578719000 ps
T1292 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2117619269 Aug 05 08:40:44 PM PDT 24 Aug 05 08:46:23 PM PDT 24 3634379516 ps
T411 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3843648472 Aug 05 08:12:22 PM PDT 24 Aug 05 09:20:44 PM PDT 24 31172198885 ps
T622 /workspace/coverage/default/2.chip_sw_edn_boot_mode.3104624491 Aug 05 08:25:34 PM PDT 24 Aug 05 08:35:15 PM PDT 24 3418495614 ps
T663 /workspace/coverage/default/64.chip_sw_all_escalation_resets.378107432 Aug 05 08:41:00 PM PDT 24 Aug 05 08:50:24 PM PDT 24 5868351892 ps
T284 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1495245493 Aug 05 08:27:08 PM PDT 24 Aug 05 08:44:52 PM PDT 24 7707057530 ps
T313 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3836964089 Aug 05 08:02:52 PM PDT 24 Aug 05 08:11:02 PM PDT 24 3464090052 ps
T1293 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1553447961 Aug 05 08:33:28 PM PDT 24 Aug 05 08:37:26 PM PDT 24 3112142320 ps
T1294 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3254274142 Aug 05 08:13:54 PM PDT 24 Aug 05 09:07:08 PM PDT 24 13721965556 ps
T1295 /workspace/coverage/default/1.rom_e2e_smoke.362263597 Aug 05 08:24:01 PM PDT 24 Aug 05 09:25:26 PM PDT 24 15108798412 ps
T1296 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3518737333 Aug 05 08:11:32 PM PDT 24 Aug 05 08:22:52 PM PDT 24 4187451460 ps
T1297 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1733544585 Aug 05 08:03:38 PM PDT 24 Aug 05 08:45:48 PM PDT 24 22839431248 ps
T1298 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3646172684 Aug 05 08:25:11 PM PDT 24 Aug 05 08:32:01 PM PDT 24 6051294454 ps
T1299 /workspace/coverage/default/2.chip_sw_flash_crash_alert.2349019898 Aug 05 08:30:59 PM PDT 24 Aug 05 08:41:55 PM PDT 24 5118664380 ps
T1300 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3113809450 Aug 05 08:12:10 PM PDT 24 Aug 05 08:16:17 PM PDT 24 2585408520 ps
T701 /workspace/coverage/default/89.chip_sw_all_escalation_resets.2346188217 Aug 05 08:42:31 PM PDT 24 Aug 05 08:49:55 PM PDT 24 5281545272 ps
T1301 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3423082729 Aug 05 08:14:46 PM PDT 24 Aug 05 09:33:49 PM PDT 24 18321132600 ps
T1302 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.4275886424 Aug 05 08:24:52 PM PDT 24 Aug 05 08:33:35 PM PDT 24 4075374300 ps
T746 /workspace/coverage/default/70.chip_sw_all_escalation_resets.1307358619 Aug 05 08:43:13 PM PDT 24 Aug 05 08:54:33 PM PDT 24 4780762592 ps
T737 /workspace/coverage/default/47.chip_sw_all_escalation_resets.77725379 Aug 05 08:39:55 PM PDT 24 Aug 05 08:50:44 PM PDT 24 4511808310 ps
T1303 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3304663037 Aug 05 08:19:32 PM PDT 24 Aug 05 08:42:34 PM PDT 24 9595742165 ps
T1304 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1616841031 Aug 05 08:07:54 PM PDT 24 Aug 05 08:17:36 PM PDT 24 5749531304 ps
T63 /workspace/coverage/default/2.chip_tap_straps_testunlock0.261371725 Aug 05 08:30:48 PM PDT 24 Aug 05 08:40:25 PM PDT 24 5803279576 ps
T1305 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3219775110 Aug 05 08:05:01 PM PDT 24 Aug 05 08:15:25 PM PDT 24 4618712790 ps
T1306 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2111473889 Aug 05 08:34:47 PM PDT 24 Aug 05 08:44:24 PM PDT 24 3268240276 ps
T1307 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1188362465 Aug 05 08:15:33 PM PDT 24 Aug 05 08:34:07 PM PDT 24 5414397486 ps
T1308 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.501523044 Aug 05 08:34:37 PM PDT 24 Aug 05 08:44:23 PM PDT 24 5332732560 ps
T1309 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.70587693 Aug 05 08:14:44 PM PDT 24 Aug 05 09:25:38 PM PDT 24 15047192034 ps
T252 /workspace/coverage/default/28.chip_sw_all_escalation_resets.811657090 Aug 05 08:38:22 PM PDT 24 Aug 05 08:51:13 PM PDT 24 6646803420 ps
T705 /workspace/coverage/default/4.chip_sw_all_escalation_resets.355948866 Aug 05 08:32:47 PM PDT 24 Aug 05 08:45:18 PM PDT 24 5724159400 ps
T1310 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1260776041 Aug 05 08:02:52 PM PDT 24 Aug 05 08:20:20 PM PDT 24 5662201440 ps
T1311 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2739819866 Aug 05 08:23:38 PM PDT 24 Aug 05 09:12:57 PM PDT 24 40501077280 ps
T1312 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.353653877 Aug 05 08:15:10 PM PDT 24 Aug 05 08:50:04 PM PDT 24 17439198998 ps
T750 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1143067777 Aug 05 08:37:08 PM PDT 24 Aug 05 08:44:13 PM PDT 24 3928410126 ps
T1313 /workspace/coverage/default/1.chip_sw_edn_auto_mode.1830795036 Aug 05 08:15:41 PM PDT 24 Aug 05 08:31:26 PM PDT 24 4039152840 ps
T700 /workspace/coverage/default/57.chip_sw_all_escalation_resets.2390875195 Aug 05 08:40:54 PM PDT 24 Aug 05 08:48:40 PM PDT 24 4728568890 ps
T1314 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1465822496 Aug 05 08:22:56 PM PDT 24 Aug 05 09:54:23 PM PDT 24 49674876455 ps
T715 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2765695277 Aug 05 08:41:30 PM PDT 24 Aug 05 08:46:48 PM PDT 24 3476449144 ps
T1315 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1802769203 Aug 05 08:13:10 PM PDT 24 Aug 05 08:32:32 PM PDT 24 5379772827 ps
T205 /workspace/coverage/default/2.chip_jtag_mem_access.1776076646 Aug 05 08:22:20 PM PDT 24 Aug 05 08:46:30 PM PDT 24 13349889436 ps
T1316 /workspace/coverage/default/0.chip_sw_example_flash.1110550019 Aug 05 08:01:07 PM PDT 24 Aug 05 08:05:20 PM PDT 24 2811061552 ps
T1317 /workspace/coverage/default/1.chip_sw_hmac_enc.2643371705 Aug 05 08:15:12 PM PDT 24 Aug 05 08:19:45 PM PDT 24 3030916724 ps
T1318 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2283500418 Aug 05 08:03:13 PM PDT 24 Aug 05 11:08:19 PM PDT 24 58878967184 ps
T1319 /workspace/coverage/default/0.chip_tap_straps_rma.2168307360 Aug 05 08:08:25 PM PDT 24 Aug 05 08:12:48 PM PDT 24 3485886636 ps
T1320 /workspace/coverage/default/0.rom_e2e_shutdown_output.1497630488 Aug 05 08:13:36 PM PDT 24 Aug 05 09:16:54 PM PDT 24 28883510966 ps
T1321 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1646346052 Aug 05 08:06:17 PM PDT 24 Aug 05 08:17:14 PM PDT 24 3931526778 ps
T623 /workspace/coverage/default/1.chip_sw_edn_boot_mode.1646878441 Aug 05 08:15:07 PM PDT 24 Aug 05 08:23:27 PM PDT 24 2932918374 ps
T1322 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.4107040562 Aug 05 08:10:15 PM PDT 24 Aug 05 09:09:35 PM PDT 24 14908740708 ps
T1323 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.4263350593 Aug 05 08:22:36 PM PDT 24 Aug 05 08:35:21 PM PDT 24 5969587716 ps
T1324 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2040935024 Aug 05 08:24:18 PM PDT 24 Aug 05 09:15:25 PM PDT 24 11756484739 ps
T1325 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2395498255 Aug 05 08:11:28 PM PDT 24 Aug 05 09:17:43 PM PDT 24 14768884240 ps
T1326 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1077058409 Aug 05 08:40:50 PM PDT 24 Aug 05 08:46:52 PM PDT 24 3711611070 ps
T1327 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.156227763 Aug 05 08:05:57 PM PDT 24 Aug 05 08:25:36 PM PDT 24 6237697747 ps
T272 /workspace/coverage/default/31.chip_sw_all_escalation_resets.2666795405 Aug 05 08:40:29 PM PDT 24 Aug 05 08:49:35 PM PDT 24 5360318052 ps
T1328 /workspace/coverage/default/2.chip_sw_example_rom.2382248291 Aug 05 08:20:27 PM PDT 24 Aug 05 08:22:40 PM PDT 24 2747016660 ps
T1329 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1481923582 Aug 05 08:14:15 PM PDT 24 Aug 05 08:20:40 PM PDT 24 4202106568 ps
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