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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.28 95.50 94.47 95.47 95.36 97.35 99.52


Total test records in report: 2940
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T877 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.751386431 Aug 08 08:34:37 PM PDT 24 Aug 08 08:44:51 PM PDT 24 6121133448 ps
T304 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.463447196 Aug 08 08:47:53 PM PDT 24 Aug 08 08:57:45 PM PDT 24 3993357278 ps
T711 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2465992001 Aug 08 08:52:45 PM PDT 24 Aug 08 08:59:14 PM PDT 24 4338589888 ps
T878 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.249188 Aug 08 08:46:48 PM PDT 24 Aug 08 08:55:25 PM PDT 24 3849707696 ps
T330 /workspace/coverage/default/0.chip_sw_uart_tx_rx.2953794827 Aug 08 08:18:55 PM PDT 24 Aug 08 08:30:19 PM PDT 24 4403480644 ps
T879 /workspace/coverage/default/2.chip_sw_edn_kat.164634849 Aug 08 08:40:13 PM PDT 24 Aug 08 08:50:10 PM PDT 24 3045265820 ps
T880 /workspace/coverage/default/2.chip_sw_example_manufacturer.4197115958 Aug 08 08:37:08 PM PDT 24 Aug 08 08:40:14 PM PDT 24 2828494234 ps
T881 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2899021348 Aug 08 08:19:07 PM PDT 24 Aug 08 08:39:23 PM PDT 24 6152135524 ps
T699 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.407928169 Aug 08 08:55:50 PM PDT 24 Aug 08 09:02:28 PM PDT 24 3024770260 ps
T249 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.707490123 Aug 08 08:46:57 PM PDT 24 Aug 08 08:59:50 PM PDT 24 5099187810 ps
T882 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2080514145 Aug 08 08:28:04 PM PDT 24 Aug 08 08:37:41 PM PDT 24 4428578600 ps
T316 /workspace/coverage/default/2.chip_plic_all_irqs_20.2375453425 Aug 08 08:42:16 PM PDT 24 Aug 08 08:54:16 PM PDT 24 5230852380 ps
T883 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.613752968 Aug 08 08:23:39 PM PDT 24 Aug 08 08:43:39 PM PDT 24 6467893973 ps
T884 /workspace/coverage/default/2.chip_sw_example_concurrency.4211622055 Aug 08 08:35:10 PM PDT 24 Aug 08 08:39:57 PM PDT 24 2718813736 ps
T885 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.4140601694 Aug 08 08:43:51 PM PDT 24 Aug 08 08:47:39 PM PDT 24 3234103394 ps
T109 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.730626461 Aug 08 08:43:04 PM PDT 24 Aug 08 08:51:34 PM PDT 24 7718075884 ps
T188 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.637234761 Aug 08 08:17:38 PM PDT 24 Aug 08 08:28:04 PM PDT 24 5076312986 ps
T886 /workspace/coverage/default/0.chip_sw_edn_kat.1934569700 Aug 08 08:16:27 PM PDT 24 Aug 08 08:27:38 PM PDT 24 3621012350 ps
T887 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.4169276974 Aug 08 08:52:08 PM PDT 24 Aug 08 10:03:10 PM PDT 24 15059009960 ps
T307 /workspace/coverage/default/1.chip_plic_all_irqs_20.3255584729 Aug 08 08:31:34 PM PDT 24 Aug 08 08:43:47 PM PDT 24 4239077414 ps
T888 /workspace/coverage/default/0.rom_e2e_asm_init_rma.2521565887 Aug 08 08:24:42 PM PDT 24 Aug 08 09:33:16 PM PDT 24 14627510136 ps
T889 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3475715066 Aug 08 08:51:47 PM PDT 24 Aug 08 09:56:47 PM PDT 24 15611215487 ps
T890 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3380907675 Aug 08 08:25:13 PM PDT 24 Aug 08 08:30:07 PM PDT 24 7625541914 ps
T692 /workspace/coverage/default/62.chip_sw_all_escalation_resets.752266004 Aug 08 08:55:55 PM PDT 24 Aug 08 09:06:31 PM PDT 24 5525324860 ps
T891 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1266268164 Aug 08 08:26:39 PM PDT 24 Aug 08 08:33:48 PM PDT 24 3352201184 ps
T230 /workspace/coverage/default/0.chip_sw_plic_sw_irq.99558954 Aug 08 08:21:45 PM PDT 24 Aug 08 08:26:10 PM PDT 24 2541725892 ps
T510 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.843562597 Aug 08 08:17:37 PM PDT 24 Aug 08 08:29:43 PM PDT 24 4998520608 ps
T238 /workspace/coverage/default/43.chip_sw_all_escalation_resets.3498438479 Aug 08 08:53:29 PM PDT 24 Aug 08 09:03:28 PM PDT 24 5344664408 ps
T733 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.366851686 Aug 08 08:50:46 PM PDT 24 Aug 08 08:57:05 PM PDT 24 4188164712 ps
T653 /workspace/coverage/default/1.chip_sw_power_sleep_load.78927325 Aug 08 08:32:36 PM PDT 24 Aug 08 08:42:50 PM PDT 24 10831107200 ps
T746 /workspace/coverage/default/71.chip_sw_all_escalation_resets.2107411834 Aug 08 08:55:21 PM PDT 24 Aug 08 09:04:28 PM PDT 24 5766868100 ps
T892 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1728641371 Aug 08 08:16:58 PM PDT 24 Aug 08 08:26:35 PM PDT 24 4790622128 ps
T893 /workspace/coverage/default/0.chip_sw_hmac_multistream.232490792 Aug 08 08:17:39 PM PDT 24 Aug 08 08:48:14 PM PDT 24 6549155864 ps
T361 /workspace/coverage/default/1.chip_sw_edn_boot_mode.539004357 Aug 08 08:28:13 PM PDT 24 Aug 08 08:38:09 PM PDT 24 3227573992 ps
T894 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3181278351 Aug 08 08:45:15 PM PDT 24 Aug 08 08:49:25 PM PDT 24 2744082434 ps
T157 /workspace/coverage/default/2.chip_plic_all_irqs_10.2627638614 Aug 08 08:41:36 PM PDT 24 Aug 08 08:49:00 PM PDT 24 4225330086 ps
T895 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3039425551 Aug 08 08:31:29 PM PDT 24 Aug 08 09:49:17 PM PDT 24 14903773525 ps
T731 /workspace/coverage/default/63.chip_sw_all_escalation_resets.2896354565 Aug 08 08:55:11 PM PDT 24 Aug 08 09:03:20 PM PDT 24 4565838692 ps
T679 /workspace/coverage/default/15.chip_sw_all_escalation_resets.3403912712 Aug 08 08:50:11 PM PDT 24 Aug 08 09:04:22 PM PDT 24 6377487872 ps
T233 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2371694044 Aug 08 08:20:20 PM PDT 24 Aug 08 08:59:31 PM PDT 24 24526143116 ps
T706 /workspace/coverage/default/29.chip_sw_all_escalation_resets.3090805490 Aug 08 08:53:09 PM PDT 24 Aug 08 09:02:31 PM PDT 24 5023760088 ps
T896 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3702060833 Aug 08 08:35:52 PM PDT 24 Aug 08 08:40:23 PM PDT 24 3067137566 ps
T654 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2302843488 Aug 08 08:16:43 PM PDT 24 Aug 08 08:36:48 PM PDT 24 9203512888 ps
T897 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2833242203 Aug 08 08:24:17 PM PDT 24 Aug 08 09:01:01 PM PDT 24 29871843254 ps
T759 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.4081332063 Aug 08 08:46:56 PM PDT 24 Aug 08 08:53:59 PM PDT 24 4347830880 ps
T317 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3085215165 Aug 08 08:22:25 PM PDT 24 Aug 08 08:33:55 PM PDT 24 5362684584 ps
T747 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.817827802 Aug 08 08:48:16 PM PDT 24 Aug 08 08:55:14 PM PDT 24 4095764496 ps
T160 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.227782087 Aug 08 08:29:49 PM PDT 24 Aug 08 11:45:39 PM PDT 24 255689649776 ps
T637 /workspace/coverage/default/2.chip_sw_power_idle_load.3195671263 Aug 08 08:45:09 PM PDT 24 Aug 08 08:58:19 PM PDT 24 4048456480 ps
T898 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1446072891 Aug 08 08:20:07 PM PDT 24 Aug 08 08:31:02 PM PDT 24 3661435170 ps
T693 /workspace/coverage/default/40.chip_sw_all_escalation_resets.1504717382 Aug 08 08:54:08 PM PDT 24 Aug 08 09:05:10 PM PDT 24 6241172210 ps
T23 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1486336612 Aug 08 08:19:03 PM PDT 24 Aug 08 08:56:35 PM PDT 24 22844573600 ps
T899 /workspace/coverage/default/1.chip_sw_csrng_kat_test.619623896 Aug 08 08:28:18 PM PDT 24 Aug 08 08:33:33 PM PDT 24 3070662068 ps
T900 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2085206761 Aug 08 08:27:34 PM PDT 24 Aug 08 10:03:40 PM PDT 24 23718325108 ps
T901 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1777392700 Aug 08 08:16:54 PM PDT 24 Aug 08 08:57:59 PM PDT 24 22907958147 ps
T902 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1876313153 Aug 08 08:52:48 PM PDT 24 Aug 08 09:39:42 PM PDT 24 14657511563 ps
T414 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.997909472 Aug 08 08:28:41 PM PDT 24 Aug 08 08:48:29 PM PDT 24 5357480356 ps
T903 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3094392707 Aug 08 08:24:24 PM PDT 24 Aug 08 08:55:20 PM PDT 24 13122089011 ps
T904 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1094490004 Aug 08 08:30:31 PM PDT 24 Aug 08 08:56:33 PM PDT 24 7952885000 ps
T905 /workspace/coverage/default/0.chip_sw_otbn_randomness.2391609756 Aug 08 08:20:39 PM PDT 24 Aug 08 08:35:43 PM PDT 24 6506812960 ps
T906 /workspace/coverage/default/0.chip_sw_hmac_enc.858944815 Aug 08 08:17:41 PM PDT 24 Aug 08 08:21:19 PM PDT 24 3174486480 ps
T907 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.2265154911 Aug 08 08:18:32 PM PDT 24 Aug 08 08:39:54 PM PDT 24 5760842540 ps
T908 /workspace/coverage/default/0.chip_sw_hmac_smoketest.2612461123 Aug 08 08:22:29 PM PDT 24 Aug 08 08:27:46 PM PDT 24 3368382432 ps
T909 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2820448123 Aug 08 08:24:49 PM PDT 24 Aug 08 08:51:12 PM PDT 24 15038037293 ps
T341 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.345269809 Aug 08 08:37:03 PM PDT 24 Aug 08 09:24:34 PM PDT 24 38736295490 ps
T910 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3425105729 Aug 08 08:45:38 PM PDT 24 Aug 08 08:48:54 PM PDT 24 2563586592 ps
T363 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3522996701 Aug 08 08:25:59 PM PDT 24 Aug 08 09:47:47 PM PDT 24 18247363408 ps
T911 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2038395272 Aug 08 08:50:31 PM PDT 24 Aug 08 09:48:24 PM PDT 24 15858374500 ps
T416 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1132830159 Aug 08 08:41:05 PM PDT 24 Aug 08 09:05:56 PM PDT 24 7103755568 ps
T912 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2275166911 Aug 08 08:40:37 PM PDT 24 Aug 08 09:21:03 PM PDT 24 12339468316 ps
T729 /workspace/coverage/default/17.chip_sw_all_escalation_resets.729021213 Aug 08 08:51:30 PM PDT 24 Aug 08 09:01:47 PM PDT 24 5087715468 ps
T913 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.255824194 Aug 08 08:27:11 PM PDT 24 Aug 08 09:20:08 PM PDT 24 10710791810 ps
T744 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2890275474 Aug 08 08:50:12 PM PDT 24 Aug 08 08:58:10 PM PDT 24 3995567960 ps
T914 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3569557962 Aug 08 08:22:32 PM PDT 24 Aug 08 08:25:39 PM PDT 24 2609149900 ps
T183 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.586418617 Aug 08 08:25:08 PM PDT 24 Aug 08 09:56:42 PM PDT 24 44240539544 ps
T915 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3915016242 Aug 08 08:21:32 PM PDT 24 Aug 08 08:27:23 PM PDT 24 5932205952 ps
T916 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.517830157 Aug 08 08:50:31 PM PDT 24 Aug 08 08:59:38 PM PDT 24 4447486420 ps
T917 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3647017628 Aug 08 08:34:16 PM PDT 24 Aug 08 08:39:19 PM PDT 24 3177667642 ps
T14 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1339122429 Aug 08 08:35:56 PM PDT 24 Aug 08 08:40:01 PM PDT 24 3465623400 ps
T918 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3281806436 Aug 08 08:35:31 PM PDT 24 Aug 08 08:54:56 PM PDT 24 8370474018 ps
T919 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3109241174 Aug 08 08:15:37 PM PDT 24 Aug 08 08:31:36 PM PDT 24 7798550364 ps
T920 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2338194440 Aug 08 08:19:53 PM PDT 24 Aug 08 08:58:17 PM PDT 24 26003624432 ps
T278 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1898942944 Aug 08 08:18:35 PM PDT 24 Aug 08 08:54:10 PM PDT 24 19275027512 ps
T302 /workspace/coverage/default/0.chip_plic_all_irqs_20.1990341563 Aug 08 08:19:16 PM PDT 24 Aug 08 08:32:15 PM PDT 24 4237668784 ps
T921 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1017486755 Aug 08 08:17:45 PM PDT 24 Aug 08 08:43:59 PM PDT 24 13140647551 ps
T922 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3981393921 Aug 08 08:45:15 PM PDT 24 Aug 08 08:51:39 PM PDT 24 3058260192 ps
T923 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1471666413 Aug 08 08:49:15 PM PDT 24 Aug 08 09:55:57 PM PDT 24 19099869150 ps
T924 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2511988613 Aug 08 08:48:35 PM PDT 24 Aug 08 10:06:09 PM PDT 24 18938805104 ps
T207 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2266931097 Aug 08 08:21:59 PM PDT 24 Aug 08 11:29:38 PM PDT 24 58251159981 ps
T925 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2268418379 Aug 08 08:28:18 PM PDT 24 Aug 08 08:32:00 PM PDT 24 2978816539 ps
T926 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1588743639 Aug 08 08:48:46 PM PDT 24 Aug 08 09:02:39 PM PDT 24 9756855103 ps
T707 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.858656540 Aug 08 08:57:17 PM PDT 24 Aug 08 09:03:36 PM PDT 24 3653853064 ps
T927 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1375232102 Aug 08 08:16:15 PM PDT 24 Aug 08 08:36:55 PM PDT 24 9583180094 ps
T417 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1459947113 Aug 08 08:28:49 PM PDT 24 Aug 08 08:43:28 PM PDT 24 6891458984 ps
T225 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.343762408 Aug 08 08:15:35 PM PDT 24 Aug 08 08:23:40 PM PDT 24 5899454280 ps
T928 /workspace/coverage/default/0.chip_sw_kmac_idle.4010307652 Aug 08 08:20:25 PM PDT 24 Aug 08 08:25:20 PM PDT 24 2956497388 ps
T15 /workspace/coverage/default/2.chip_sw_power_virus.838887118 Aug 08 08:52:40 PM PDT 24 Aug 08 09:15:17 PM PDT 24 5601896310 ps
T929 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.3590217771 Aug 08 08:38:59 PM PDT 24 Aug 08 08:55:46 PM PDT 24 8507827724 ps
T189 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1727615454 Aug 08 08:40:27 PM PDT 24 Aug 08 08:45:27 PM PDT 24 3813792184 ps
T318 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.4258721583 Aug 08 08:36:11 PM PDT 24 Aug 08 08:52:08 PM PDT 24 4179465208 ps
T659 /workspace/coverage/default/1.rom_raw_unlock.4082996772 Aug 08 08:33:41 PM PDT 24 Aug 08 08:38:26 PM PDT 24 6523940847 ps
T930 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.4513391 Aug 08 08:46:10 PM PDT 24 Aug 08 08:50:17 PM PDT 24 2289752744 ps
T931 /workspace/coverage/default/2.chip_sw_edn_auto_mode.3670504900 Aug 08 08:39:17 PM PDT 24 Aug 08 08:55:52 PM PDT 24 4843752620 ps
T932 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.792795732 Aug 08 08:33:07 PM PDT 24 Aug 08 08:36:44 PM PDT 24 3296844356 ps
T632 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.437719707 Aug 08 08:16:05 PM PDT 24 Aug 08 08:18:30 PM PDT 24 2786293471 ps
T933 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.4285945130 Aug 08 08:49:10 PM PDT 24 Aug 08 09:42:18 PM PDT 24 14877611912 ps
T934 /workspace/coverage/default/1.rom_e2e_smoke.4156062394 Aug 08 08:37:39 PM PDT 24 Aug 08 09:39:14 PM PDT 24 15150533426 ps
T181 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.891568664 Aug 08 08:31:27 PM PDT 24 Aug 08 08:35:51 PM PDT 24 2754731120 ps
T374 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3497219242 Aug 08 08:49:25 PM PDT 24 Aug 08 08:54:21 PM PDT 24 3380761552 ps
T375 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.343790877 Aug 08 08:17:11 PM PDT 24 Aug 08 08:40:23 PM PDT 24 8013840104 ps
T376 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.843020151 Aug 08 08:37:45 PM PDT 24 Aug 08 08:52:39 PM PDT 24 5736718490 ps
T377 /workspace/coverage/default/1.chip_sw_aes_idle.3908044266 Aug 08 08:29:31 PM PDT 24 Aug 08 08:33:25 PM PDT 24 2762083422 ps
T378 /workspace/coverage/default/7.chip_sw_all_escalation_resets.449349079 Aug 08 08:50:10 PM PDT 24 Aug 08 08:57:32 PM PDT 24 4875433944 ps
T379 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1222111054 Aug 08 08:44:28 PM PDT 24 Aug 08 08:56:21 PM PDT 24 4392074638 ps
T118 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3532498779 Aug 08 08:45:01 PM PDT 24 Aug 08 09:39:20 PM PDT 24 24015921144 ps
T380 /workspace/coverage/default/9.chip_sw_all_escalation_resets.1787369104 Aug 08 08:49:30 PM PDT 24 Aug 08 09:04:51 PM PDT 24 6369702840 ps
T381 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3335853801 Aug 08 08:20:51 PM PDT 24 Aug 08 08:26:49 PM PDT 24 3684673606 ps
T935 /workspace/coverage/default/2.chip_sw_csrng_smoketest.2416386422 Aug 08 08:45:32 PM PDT 24 Aug 08 08:49:50 PM PDT 24 2426232068 ps
T936 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3175182171 Aug 08 08:30:51 PM PDT 24 Aug 08 08:38:02 PM PDT 24 4910429037 ps
T98 /workspace/coverage/default/91.chip_sw_all_escalation_resets.2247204723 Aug 08 08:58:50 PM PDT 24 Aug 08 09:08:29 PM PDT 24 5158935038 ps
T937 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2506923117 Aug 08 08:29:23 PM PDT 24 Aug 08 09:26:18 PM PDT 24 12085990656 ps
T938 /workspace/coverage/default/2.rom_e2e_asm_init_prod.2165581849 Aug 08 08:51:05 PM PDT 24 Aug 08 09:45:14 PM PDT 24 15584131250 ps
T384 /workspace/coverage/default/66.chip_sw_all_escalation_resets.790978623 Aug 08 08:55:52 PM PDT 24 Aug 08 09:04:28 PM PDT 24 5839068008 ps
T765 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3854409923 Aug 08 08:58:06 PM PDT 24 Aug 08 09:03:43 PM PDT 24 3255305080 ps
T939 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2987997323 Aug 08 08:37:57 PM PDT 24 Aug 08 09:32:20 PM PDT 24 15976085178 ps
T940 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2899623241 Aug 08 08:42:41 PM PDT 24 Aug 08 08:49:04 PM PDT 24 4436919470 ps
T941 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.10664887 Aug 08 08:37:42 PM PDT 24 Aug 08 08:42:54 PM PDT 24 3042540596 ps
T78 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3846637876 Aug 08 08:17:01 PM PDT 24 Aug 08 08:25:31 PM PDT 24 3839230536 ps
T942 /workspace/coverage/default/2.rom_e2e_asm_init_dev.4155639892 Aug 08 08:49:54 PM PDT 24 Aug 08 09:43:34 PM PDT 24 16174026746 ps
T943 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.3140791269 Aug 08 08:32:36 PM PDT 24 Aug 08 08:39:24 PM PDT 24 2737621512 ps
T944 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.4031733457 Aug 08 08:25:37 PM PDT 24 Aug 08 08:42:40 PM PDT 24 8411711960 ps
T945 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.832816433 Aug 08 08:27:34 PM PDT 24 Aug 08 09:29:31 PM PDT 24 19168706156 ps
T136 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1524897739 Aug 08 08:18:16 PM PDT 24 Aug 08 08:35:48 PM PDT 24 7590064656 ps
T946 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1714219190 Aug 08 08:48:59 PM PDT 24 Aug 08 09:18:25 PM PDT 24 9227919456 ps
T132 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.4026260134 Aug 08 08:40:55 PM PDT 24 Aug 08 08:54:37 PM PDT 24 5146160204 ps
T947 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1483075938 Aug 08 08:25:05 PM PDT 24 Aug 08 09:26:34 PM PDT 24 15057975808 ps
T760 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1400108250 Aug 08 08:56:25 PM PDT 24 Aug 08 09:01:56 PM PDT 24 3677585424 ps
T948 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3021152228 Aug 08 08:15:46 PM PDT 24 Aug 08 08:22:36 PM PDT 24 5171814460 ps
T284 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2878601415 Aug 08 08:17:11 PM PDT 24 Aug 08 09:47:02 PM PDT 24 45452995098 ps
T742 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.378539888 Aug 08 08:55:48 PM PDT 24 Aug 08 09:01:59 PM PDT 24 4205346292 ps
T178 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.14380084 Aug 08 08:18:37 PM PDT 24 Aug 08 08:27:22 PM PDT 24 5036676040 ps
T709 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3220451977 Aug 08 08:52:48 PM PDT 24 Aug 08 09:00:22 PM PDT 24 3581119496 ps
T949 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.4176993651 Aug 08 08:36:09 PM PDT 24 Aug 08 08:47:00 PM PDT 24 4629789660 ps
T383 /workspace/coverage/default/1.chip_sw_kmac_app_rom.1391983448 Aug 08 08:35:25 PM PDT 24 Aug 08 08:40:11 PM PDT 24 2684380352 ps
T950 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.631847409 Aug 08 08:50:54 PM PDT 24 Aug 08 09:05:08 PM PDT 24 12260897845 ps
T951 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1846121967 Aug 08 08:23:19 PM PDT 24 Aug 08 08:27:12 PM PDT 24 2359277596 ps
T952 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1382138337 Aug 08 08:37:09 PM PDT 24 Aug 08 08:47:11 PM PDT 24 4580352460 ps
T953 /workspace/coverage/default/2.chip_sw_kmac_entropy.3539765378 Aug 08 08:35:21 PM PDT 24 Aug 08 08:40:43 PM PDT 24 2941811336 ps
T25 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.929787293 Aug 08 08:17:09 PM PDT 24 Aug 08 08:25:52 PM PDT 24 3951981730 ps
T954 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.17190291 Aug 08 08:38:05 PM PDT 24 Aug 08 08:47:06 PM PDT 24 5628432400 ps
T955 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.500113978 Aug 08 08:38:42 PM PDT 24 Aug 08 08:43:12 PM PDT 24 3016632656 ps
T956 /workspace/coverage/default/2.chip_sw_rv_timer_irq.1214805097 Aug 08 08:38:09 PM PDT 24 Aug 08 08:41:36 PM PDT 24 2506470260 ps
T30 /workspace/coverage/default/2.chip_sw_gpio.3529016954 Aug 08 08:35:39 PM PDT 24 Aug 08 08:45:02 PM PDT 24 3481280304 ps
T957 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1175686147 Aug 08 08:36:25 PM PDT 24 Aug 08 08:48:33 PM PDT 24 4540713966 ps
T211 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.703252541 Aug 08 08:16:39 PM PDT 24 Aug 08 08:21:14 PM PDT 24 2929668894 ps
T958 /workspace/coverage/default/1.rom_e2e_asm_init_dev.916774424 Aug 08 08:37:45 PM PDT 24 Aug 08 09:45:19 PM PDT 24 14948936367 ps
T959 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3628306198 Aug 08 08:47:37 PM PDT 24 Aug 08 08:55:11 PM PDT 24 5426137672 ps
T960 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3637738490 Aug 08 08:18:03 PM PDT 24 Aug 08 08:22:35 PM PDT 24 3147224970 ps
T45 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2791799333 Aug 08 08:25:09 PM PDT 24 Aug 08 08:35:07 PM PDT 24 4567133917 ps
T208 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.4108494910 Aug 08 08:36:29 PM PDT 24 Aug 08 11:37:02 PM PDT 24 64073086743 ps
T722 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.930028083 Aug 08 08:29:15 PM PDT 24 Aug 08 08:34:36 PM PDT 24 3719785408 ps
T305 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3673615190 Aug 08 08:35:06 PM PDT 24 Aug 08 08:48:03 PM PDT 24 5128669100 ps
T961 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.4293773555 Aug 08 08:16:56 PM PDT 24 Aug 08 08:20:06 PM PDT 24 2582224160 ps
T962 /workspace/coverage/default/2.chip_sw_otbn_smoketest.3296402327 Aug 08 08:46:45 PM PDT 24 Aug 08 09:10:47 PM PDT 24 7250924596 ps
T719 /workspace/coverage/default/37.chip_sw_all_escalation_resets.1916986600 Aug 08 08:52:35 PM PDT 24 Aug 08 08:59:53 PM PDT 24 4997548504 ps
T758 /workspace/coverage/default/33.chip_sw_all_escalation_resets.690322650 Aug 08 08:52:32 PM PDT 24 Aug 08 09:02:27 PM PDT 24 5084349700 ps
T963 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3926164650 Aug 08 08:25:23 PM PDT 24 Aug 08 09:16:59 PM PDT 24 11039718144 ps
T964 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3653268138 Aug 08 08:26:33 PM PDT 24 Aug 08 09:41:11 PM PDT 24 14767121070 ps
T250 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.1010603933 Aug 08 08:36:42 PM PDT 24 Aug 08 08:47:52 PM PDT 24 5956023160 ps
T965 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.4045323605 Aug 08 08:49:08 PM PDT 24 Aug 08 08:56:37 PM PDT 24 3361571728 ps
T966 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.514374686 Aug 08 08:15:23 PM PDT 24 Aug 08 09:38:03 PM PDT 24 28337106758 ps
T40 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1545670321 Aug 08 08:28:23 PM PDT 24 Aug 08 08:36:12 PM PDT 24 5042901920 ps
T275 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2313981578 Aug 08 08:36:42 PM PDT 24 Aug 08 10:07:38 PM PDT 24 47633965492 ps
T967 /workspace/coverage/default/0.chip_sw_power_idle_load.2457541674 Aug 08 08:20:39 PM PDT 24 Aug 08 08:31:21 PM PDT 24 4045018588 ps
T697 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1360562581 Aug 08 08:52:48 PM PDT 24 Aug 08 08:58:51 PM PDT 24 4385342784 ps
T251 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3662011162 Aug 08 08:38:44 PM PDT 24 Aug 08 08:47:38 PM PDT 24 4025435406 ps
T968 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.343462407 Aug 08 08:32:13 PM PDT 24 Aug 08 08:43:31 PM PDT 24 5332115816 ps
T234 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.634433723 Aug 08 08:21:18 PM PDT 24 Aug 08 09:06:35 PM PDT 24 24434198566 ps
T969 /workspace/coverage/default/0.chip_sw_example_concurrency.774729539 Aug 08 08:15:57 PM PDT 24 Aug 08 08:20:07 PM PDT 24 2666878112 ps
T970 /workspace/coverage/default/5.chip_sw_all_escalation_resets.117929435 Aug 08 08:48:59 PM PDT 24 Aug 08 08:57:18 PM PDT 24 4459835728 ps
T227 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.206198315 Aug 08 08:54:11 PM PDT 24 Aug 08 09:00:25 PM PDT 24 3423738480 ps
T971 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2041314332 Aug 08 08:18:47 PM PDT 24 Aug 08 09:02:26 PM PDT 24 12452502000 ps
T972 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.4116219082 Aug 08 08:18:06 PM PDT 24 Aug 08 08:33:08 PM PDT 24 8470180520 ps
T335 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2357028264 Aug 08 08:25:16 PM PDT 24 Aug 08 08:36:29 PM PDT 24 3659372308 ps
T184 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1403616122 Aug 08 08:35:50 PM PDT 24 Aug 08 09:59:59 PM PDT 24 44345016206 ps
T182 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2128620944 Aug 08 08:45:16 PM PDT 24 Aug 08 08:50:56 PM PDT 24 3065586768 ps
T704 /workspace/coverage/default/79.chip_sw_all_escalation_resets.1191403146 Aug 08 08:56:52 PM PDT 24 Aug 08 09:06:09 PM PDT 24 5197060170 ps
T973 /workspace/coverage/default/1.chip_sw_csrng_smoketest.680465856 Aug 08 08:35:09 PM PDT 24 Aug 08 08:39:43 PM PDT 24 2080486296 ps
T64 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.2578523589 Aug 08 08:37:14 PM PDT 24 Aug 08 08:45:00 PM PDT 24 5028217426 ps
T974 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1094672385 Aug 08 08:38:38 PM PDT 24 Aug 08 09:38:56 PM PDT 24 19161932583 ps
T975 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2685150362 Aug 08 08:18:10 PM PDT 24 Aug 08 08:40:32 PM PDT 24 10399172135 ps
T37 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2843908593 Aug 08 08:22:57 PM PDT 24 Aug 08 08:26:53 PM PDT 24 3255026550 ps
T738 /workspace/coverage/default/6.chip_sw_all_escalation_resets.2187779017 Aug 08 08:47:48 PM PDT 24 Aug 08 08:58:17 PM PDT 24 5264214914 ps
T976 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.4036423354 Aug 08 08:51:14 PM PDT 24 Aug 08 09:54:37 PM PDT 24 14667335504 ps
T186 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2219728763 Aug 08 08:42:49 PM PDT 24 Aug 08 08:58:08 PM PDT 24 8427861193 ps
T110 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1922534267 Aug 08 08:20:36 PM PDT 24 Aug 08 08:57:56 PM PDT 24 21876701506 ps
T977 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.788290785 Aug 08 08:18:29 PM PDT 24 Aug 08 08:41:47 PM PDT 24 8793592710 ps
T705 /workspace/coverage/default/35.chip_sw_all_escalation_resets.51467974 Aug 08 08:53:12 PM PDT 24 Aug 08 09:03:24 PM PDT 24 5182144692 ps
T978 /workspace/coverage/default/2.chip_sw_uart_smoketest.3477775150 Aug 08 08:45:58 PM PDT 24 Aug 08 08:51:00 PM PDT 24 3160523804 ps
T199 /workspace/coverage/default/1.chip_sw_power_virus.4007241768 Aug 08 08:39:26 PM PDT 24 Aug 08 09:06:07 PM PDT 24 5618546858 ps
T979 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3355752285 Aug 08 08:34:02 PM PDT 24 Aug 08 08:55:30 PM PDT 24 5128861196 ps
T980 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.668001222 Aug 08 08:46:07 PM PDT 24 Aug 08 08:50:50 PM PDT 24 3582883880 ps
T981 /workspace/coverage/default/1.chip_sw_aes_masking_off.1831652282 Aug 08 08:26:43 PM PDT 24 Aug 08 08:30:37 PM PDT 24 3261438095 ps
T982 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.3310975192 Aug 08 08:21:38 PM PDT 24 Aug 08 08:43:21 PM PDT 24 9248196502 ps
T983 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1568664234 Aug 08 08:47:58 PM PDT 24 Aug 08 08:58:08 PM PDT 24 3684858451 ps
T984 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2470503269 Aug 08 08:25:25 PM PDT 24 Aug 08 09:39:26 PM PDT 24 14742130744 ps
T985 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3798116976 Aug 08 08:48:18 PM PDT 24 Aug 08 08:57:40 PM PDT 24 4586264440 ps
T986 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1875894333 Aug 08 08:50:27 PM PDT 24 Aug 08 09:00:26 PM PDT 24 4336290120 ps
T342 /workspace/coverage/default/1.chip_sw_aon_timer_irq.4032029703 Aug 08 08:27:23 PM PDT 24 Aug 08 08:34:43 PM PDT 24 4367197392 ps
T987 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.446459722 Aug 08 08:30:39 PM PDT 24 Aug 08 08:37:52 PM PDT 24 3249448026 ps
T252 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.716627698 Aug 08 08:33:29 PM PDT 24 Aug 08 08:45:21 PM PDT 24 4909040208 ps
T988 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3552666249 Aug 08 08:49:51 PM PDT 24 Aug 08 08:58:41 PM PDT 24 4302968916 ps
T694 /workspace/coverage/default/38.chip_sw_all_escalation_resets.4232626080 Aug 08 08:52:05 PM PDT 24 Aug 08 09:00:40 PM PDT 24 4221033404 ps
T366 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.552805578 Aug 08 08:22:37 PM PDT 24 Aug 08 08:25:00 PM PDT 24 3093784162 ps
T86 /workspace/coverage/default/1.chip_jtag_mem_access.2565621214 Aug 08 08:24:21 PM PDT 24 Aug 08 08:53:02 PM PDT 24 13546604440 ps
T276 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.948654668 Aug 08 08:44:00 PM PDT 24 Aug 08 09:11:48 PM PDT 24 19925273725 ps
T712 /workspace/coverage/default/47.chip_sw_all_escalation_resets.465482917 Aug 08 08:53:49 PM PDT 24 Aug 08 09:02:37 PM PDT 24 5210458728 ps
T734 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3844121425 Aug 08 08:52:25 PM PDT 24 Aug 08 08:58:52 PM PDT 24 3983516376 ps
T512 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2359949682 Aug 08 08:29:18 PM PDT 24 Aug 08 08:39:57 PM PDT 24 4133892450 ps
T989 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3035526102 Aug 08 08:42:59 PM PDT 24 Aug 08 08:53:28 PM PDT 24 3800349370 ps
T713 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.4039229074 Aug 08 08:55:37 PM PDT 24 Aug 08 09:04:08 PM PDT 24 3604166824 ps
T990 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.213504867 Aug 08 08:37:51 PM PDT 24 Aug 08 09:37:14 PM PDT 24 15278813930 ps
T991 /workspace/coverage/default/2.chip_sw_hmac_oneshot.813281409 Aug 08 08:39:51 PM PDT 24 Aug 08 08:44:44 PM PDT 24 3280642166 ps
T285 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3551992858 Aug 08 08:25:43 PM PDT 24 Aug 08 09:58:58 PM PDT 24 50729446538 ps
T992 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.694985997 Aug 08 08:45:18 PM PDT 24 Aug 08 09:03:36 PM PDT 24 5518024108 ps
T993 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.816737683 Aug 08 08:30:27 PM PDT 24 Aug 08 08:40:52 PM PDT 24 5364926600 ps
T228 /workspace/coverage/default/70.chip_sw_all_escalation_resets.4224085960 Aug 08 08:58:01 PM PDT 24 Aug 08 09:06:40 PM PDT 24 4162098400 ps
T994 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.234693746 Aug 08 08:48:02 PM PDT 24 Aug 08 09:01:40 PM PDT 24 5656730168 ps
T995 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1112672058 Aug 08 08:16:26 PM PDT 24 Aug 08 08:24:58 PM PDT 24 5030453040 ps
T996 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2429378257 Aug 08 08:23:18 PM PDT 24 Aug 08 09:21:28 PM PDT 24 14493697048 ps
T997 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.4261478284 Aug 08 08:26:54 PM PDT 24 Aug 08 08:38:49 PM PDT 24 5877453612 ps
T614 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.984181828 Aug 08 08:52:45 PM PDT 24 Aug 08 08:59:51 PM PDT 24 3731370136 ps
T998 /workspace/coverage/default/0.rom_e2e_static_critical.3088345421 Aug 08 08:26:31 PM PDT 24 Aug 08 09:49:19 PM PDT 24 17180502374 ps
T612 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2203572110 Aug 08 08:34:42 PM PDT 24 Aug 08 10:08:01 PM PDT 24 30770486976 ps
T999 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2579496505 Aug 08 08:16:11 PM PDT 24 Aug 08 08:22:57 PM PDT 24 6521207576 ps
T1000 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3413029829 Aug 08 08:28:06 PM PDT 24 Aug 08 09:17:20 PM PDT 24 37075722960 ps
T223 /workspace/coverage/default/52.chip_sw_all_escalation_resets.3234162102 Aug 08 08:55:23 PM PDT 24 Aug 08 09:05:47 PM PDT 24 6176962944 ps
T1001 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3120645705 Aug 08 08:47:37 PM PDT 24 Aug 08 08:56:16 PM PDT 24 3539573210 ps
T686 /workspace/coverage/default/26.chip_sw_all_escalation_resets.2221381367 Aug 08 08:51:46 PM PDT 24 Aug 08 09:01:55 PM PDT 24 4821436000 ps
T1002 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1657251094 Aug 08 08:16:54 PM PDT 24 Aug 08 08:35:48 PM PDT 24 12831067482 ps
T1003 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2759454608 Aug 08 08:32:40 PM PDT 24 Aug 08 08:36:45 PM PDT 24 2559443778 ps
T1004 /workspace/coverage/default/2.chip_sw_aes_idle.637983062 Aug 08 08:39:02 PM PDT 24 Aug 08 08:43:04 PM PDT 24 3333780896 ps
T319 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1812660026 Aug 08 08:22:16 PM PDT 24 Aug 08 08:34:11 PM PDT 24 5806277632 ps
T1005 /workspace/coverage/default/2.rom_e2e_self_hash.3531797476 Aug 08 08:49:22 PM PDT 24 Aug 08 10:21:53 PM PDT 24 26075457734 ps
T1006 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2491504816 Aug 08 08:24:53 PM PDT 24 Aug 08 08:38:24 PM PDT 24 5299835700 ps
T1007 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1093070190 Aug 08 08:16:02 PM PDT 24 Aug 08 08:30:23 PM PDT 24 5597232524 ps
T1008 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2833238970 Aug 08 08:36:20 PM PDT 24 Aug 08 08:50:11 PM PDT 24 10196345222 ps
T166 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3339596196 Aug 08 08:31:10 PM PDT 24 Aug 08 08:38:36 PM PDT 24 4899209892 ps
T1009 /workspace/coverage/default/1.chip_sw_kmac_idle.2294870525 Aug 08 08:35:38 PM PDT 24 Aug 08 08:39:18 PM PDT 24 2701250756 ps
T1010 /workspace/coverage/default/0.chip_sw_example_manufacturer.3386301692 Aug 08 08:17:15 PM PDT 24 Aug 08 08:20:49 PM PDT 24 2043749416 ps
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