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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.28 95.50 94.47 95.47 95.36 97.35 99.52


Total test records in report: 2940
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T1155 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3685059649 Aug 08 08:35:16 PM PDT 24 Aug 08 08:57:27 PM PDT 24 8224255350 ps
T730 /workspace/coverage/default/36.chip_sw_all_escalation_resets.2893769353 Aug 08 08:52:39 PM PDT 24 Aug 08 09:01:01 PM PDT 24 4597728146 ps
T1156 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3042088238 Aug 08 08:17:06 PM PDT 24 Aug 08 11:41:04 PM PDT 24 64451500991 ps
T664 /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.3387959047 Aug 08 08:23:24 PM PDT 24 Aug 08 09:03:24 PM PDT 24 10465643495 ps
T99 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1473170800 Aug 08 08:57:52 PM PDT 24 Aug 08 09:04:27 PM PDT 24 3691716992 ps
T1157 /workspace/coverage/default/0.chip_sw_example_rom.1587065655 Aug 08 08:15:03 PM PDT 24 Aug 08 08:17:14 PM PDT 24 2402260760 ps
T1158 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3062233071 Aug 08 08:18:37 PM PDT 24 Aug 08 09:17:33 PM PDT 24 20380478932 ps
T43 /workspace/coverage/default/2.chip_sw_spi_device_tpm.1759461053 Aug 08 08:35:24 PM PDT 24 Aug 08 08:43:10 PM PDT 24 3466202410 ps
T345 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3933904269 Aug 08 08:42:58 PM PDT 24 Aug 08 08:54:12 PM PDT 24 6367007104 ps
T1159 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1082176144 Aug 08 08:19:52 PM PDT 24 Aug 08 08:39:58 PM PDT 24 7710612692 ps
T1160 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2823911029 Aug 08 08:41:21 PM PDT 24 Aug 08 09:12:24 PM PDT 24 22372885594 ps
T1161 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3477011919 Aug 08 08:17:26 PM PDT 24 Aug 08 08:21:22 PM PDT 24 2613944864 ps
T1162 /workspace/coverage/default/69.chip_sw_all_escalation_resets.3031922223 Aug 08 08:56:26 PM PDT 24 Aug 08 09:07:31 PM PDT 24 5817910108 ps
T1163 /workspace/coverage/default/2.chip_sw_example_flash.1818686411 Aug 08 08:34:20 PM PDT 24 Aug 08 08:38:39 PM PDT 24 3307248802 ps
T1164 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2763453479 Aug 08 08:18:39 PM PDT 24 Aug 08 08:53:16 PM PDT 24 8804015874 ps
T1165 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.833874515 Aug 08 08:39:15 PM PDT 24 Aug 08 09:02:03 PM PDT 24 9938183292 ps
T1166 /workspace/coverage/default/0.chip_sw_usbdev_dpi.2611770226 Aug 08 08:15:37 PM PDT 24 Aug 08 09:01:50 PM PDT 24 11870187378 ps
T1167 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.930403317 Aug 08 08:18:05 PM PDT 24 Aug 08 08:37:07 PM PDT 24 7675587530 ps
T1168 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.15962544 Aug 08 08:36:46 PM PDT 24 Aug 08 08:48:30 PM PDT 24 4265052564 ps
T1169 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2290124782 Aug 08 08:57:57 PM PDT 24 Aug 08 09:02:56 PM PDT 24 3480913400 ps
T683 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1623203386 Aug 08 08:51:17 PM PDT 24 Aug 08 08:57:51 PM PDT 24 4184400906 ps
T1170 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.2684427551 Aug 08 08:46:02 PM PDT 24 Aug 08 08:50:28 PM PDT 24 2952399428 ps
T1171 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1587757224 Aug 08 08:48:24 PM PDT 24 Aug 08 08:58:28 PM PDT 24 4408361918 ps
T1172 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2334627247 Aug 08 08:30:38 PM PDT 24 Aug 08 08:44:41 PM PDT 24 7739306616 ps
T1173 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1741994080 Aug 08 08:31:35 PM PDT 24 Aug 08 10:34:03 PM PDT 24 24031494888 ps
T1174 /workspace/coverage/default/4.chip_tap_straps_rma.4285707391 Aug 08 08:46:52 PM PDT 24 Aug 08 08:55:36 PM PDT 24 7060825686 ps
T1175 /workspace/coverage/default/87.chip_sw_all_escalation_resets.3919547089 Aug 08 08:57:20 PM PDT 24 Aug 08 09:08:05 PM PDT 24 6450134936 ps
T1176 /workspace/coverage/default/0.chip_sw_usbdev_vbus.889238168 Aug 08 08:16:44 PM PDT 24 Aug 08 08:20:34 PM PDT 24 2810575440 ps
T1177 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3646690071 Aug 08 08:31:32 PM PDT 24 Aug 08 08:43:39 PM PDT 24 5111912074 ps
T1178 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.5229817 Aug 08 08:28:03 PM PDT 24 Aug 08 08:33:59 PM PDT 24 3926660676 ps
T1179 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1726382433 Aug 08 08:46:58 PM PDT 24 Aug 08 08:56:26 PM PDT 24 4654289606 ps
T1180 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1878388410 Aug 08 08:17:55 PM PDT 24 Aug 08 08:20:51 PM PDT 24 2611203284 ps
T761 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4072582765 Aug 08 08:58:07 PM PDT 24 Aug 08 09:04:57 PM PDT 24 3341709072 ps
T749 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2570746397 Aug 08 08:53:43 PM PDT 24 Aug 08 09:00:12 PM PDT 24 3474097228 ps
T751 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.4182198815 Aug 08 08:55:21 PM PDT 24 Aug 08 09:01:12 PM PDT 24 3332826268 ps
T1181 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1369218802 Aug 08 08:20:37 PM PDT 24 Aug 08 08:26:33 PM PDT 24 3008236200 ps
T1182 /workspace/coverage/default/0.chip_sw_csrng_kat_test.4188935981 Aug 08 08:17:10 PM PDT 24 Aug 08 08:22:16 PM PDT 24 3412600012 ps
T684 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1465088766 Aug 08 08:53:55 PM PDT 24 Aug 08 09:01:40 PM PDT 24 3836772920 ps
T1183 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2745409112 Aug 08 08:29:35 PM PDT 24 Aug 08 10:02:12 PM PDT 24 15068488052 ps
T723 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1906782957 Aug 08 08:56:23 PM PDT 24 Aug 08 09:03:22 PM PDT 24 3264061010 ps
T1184 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.863291425 Aug 08 08:23:45 PM PDT 24 Aug 08 09:35:55 PM PDT 24 14855013120 ps
T1185 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1431697692 Aug 08 08:27:54 PM PDT 24 Aug 08 08:41:55 PM PDT 24 7735890116 ps
T1186 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2495765910 Aug 08 08:37:40 PM PDT 24 Aug 08 09:11:29 PM PDT 24 23947782906 ps
T1187 /workspace/coverage/default/1.chip_sw_hmac_multistream.3087967677 Aug 08 08:30:40 PM PDT 24 Aug 08 08:58:29 PM PDT 24 7480983384 ps
T58 /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.4106325604 Aug 08 08:15:54 PM PDT 24 Aug 08 08:20:27 PM PDT 24 3607252193 ps
T1188 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.163358495 Aug 08 08:19:42 PM PDT 24 Aug 08 08:38:47 PM PDT 24 12474805780 ps
T1189 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3293761658 Aug 08 08:49:38 PM PDT 24 Aug 08 08:53:56 PM PDT 24 2360434510 ps
T1190 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.266502151 Aug 08 08:39:46 PM PDT 24 Aug 08 08:48:12 PM PDT 24 5521479232 ps
T1191 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2683680111 Aug 08 08:18:35 PM PDT 24 Aug 08 08:24:46 PM PDT 24 3154425400 ps
T1192 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2565489303 Aug 08 08:29:30 PM PDT 24 Aug 08 08:35:15 PM PDT 24 3334837428 ps
T1193 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.948023182 Aug 08 08:47:23 PM PDT 24 Aug 08 08:52:10 PM PDT 24 3263157128 ps
T685 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.300229453 Aug 08 08:55:45 PM PDT 24 Aug 08 09:03:16 PM PDT 24 4162073660 ps
T1194 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.218831320 Aug 08 08:19:18 PM PDT 24 Aug 08 08:43:56 PM PDT 24 8716021060 ps
T682 /workspace/coverage/default/23.chip_sw_all_escalation_resets.3468758954 Aug 08 08:51:50 PM PDT 24 Aug 08 09:03:03 PM PDT 24 5240616446 ps
T1195 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3778036487 Aug 08 08:36:39 PM PDT 24 Aug 08 09:01:31 PM PDT 24 8263912399 ps
T1196 /workspace/coverage/default/0.chip_tap_straps_prod.104249601 Aug 08 08:19:59 PM PDT 24 Aug 08 08:22:22 PM PDT 24 2570937888 ps
T1197 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3525523589 Aug 08 08:23:06 PM PDT 24 Aug 08 09:29:25 PM PDT 24 15290955340 ps
T1198 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1460544561 Aug 08 08:26:06 PM PDT 24 Aug 08 09:28:05 PM PDT 24 14444602678 ps
T1199 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2577873302 Aug 08 08:19:33 PM PDT 24 Aug 08 08:28:02 PM PDT 24 6431834388 ps
T162 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3475576793 Aug 08 08:35:29 PM PDT 24 Aug 08 08:37:01 PM PDT 24 2135577727 ps
T1200 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.429042958 Aug 08 08:48:32 PM PDT 24 Aug 08 08:53:33 PM PDT 24 4885249956 ps
T676 /workspace/coverage/default/14.chip_sw_all_escalation_resets.3371762600 Aug 08 08:50:10 PM PDT 24 Aug 08 09:03:40 PM PDT 24 5671830562 ps
T1201 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1354714343 Aug 08 08:25:51 PM PDT 24 Aug 08 10:08:16 PM PDT 24 48038648245 ps
T1202 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3645265964 Aug 08 08:23:15 PM PDT 24 Aug 09 12:30:57 AM PDT 24 78219154592 ps
T351 /workspace/coverage/default/96.chip_sw_all_escalation_resets.2859837896 Aug 08 08:57:47 PM PDT 24 Aug 08 09:05:25 PM PDT 24 4523093420 ps
T1203 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.4115665067 Aug 08 08:26:26 PM PDT 24 Aug 08 09:44:19 PM PDT 24 15330550262 ps
T762 /workspace/coverage/default/64.chip_sw_all_escalation_resets.2358613841 Aug 08 08:55:25 PM PDT 24 Aug 08 09:03:33 PM PDT 24 5775832568 ps
T1204 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3984809435 Aug 08 08:35:44 PM PDT 24 Aug 08 08:52:04 PM PDT 24 5572795860 ps
T1205 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2688149452 Aug 08 08:17:43 PM PDT 24 Aug 08 08:52:23 PM PDT 24 10207373150 ps
T1206 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2620959255 Aug 08 08:20:21 PM PDT 24 Aug 08 08:28:06 PM PDT 24 3796896274 ps
T763 /workspace/coverage/default/30.chip_sw_all_escalation_resets.2061440633 Aug 08 08:54:17 PM PDT 24 Aug 08 09:06:04 PM PDT 24 5478593270 ps
T1207 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.236757057 Aug 08 08:31:25 PM PDT 24 Aug 08 08:46:30 PM PDT 24 4230335612 ps
T309 /workspace/coverage/default/0.chip_plic_all_irqs_0.3882387008 Aug 08 08:17:20 PM PDT 24 Aug 08 08:35:27 PM PDT 24 6138179848 ps
T665 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2017536777 Aug 08 08:20:58 PM PDT 24 Aug 08 08:55:01 PM PDT 24 11070423716 ps
T68 /workspace/coverage/default/0.chip_sw_alert_test.2192960868 Aug 08 08:18:09 PM PDT 24 Aug 08 08:23:39 PM PDT 24 2727647688 ps
T1208 /workspace/coverage/default/4.chip_tap_straps_dev.467201168 Aug 08 08:48:16 PM PDT 24 Aug 08 08:54:01 PM PDT 24 4268763040 ps
T1209 /workspace/coverage/default/2.chip_sw_kmac_idle.1778774697 Aug 08 08:41:46 PM PDT 24 Aug 08 08:47:37 PM PDT 24 3127155304 ps
T1210 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2927103571 Aug 08 08:40:53 PM PDT 24 Aug 08 08:54:03 PM PDT 24 7267335542 ps
T262 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1527744898 Aug 08 08:43:26 PM PDT 24 Aug 08 08:47:43 PM PDT 24 2800355568 ps
T1211 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2242255870 Aug 08 08:25:29 PM PDT 24 Aug 08 08:30:08 PM PDT 24 3560434382 ps
T1212 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2184520568 Aug 08 08:48:46 PM PDT 24 Aug 08 10:11:33 PM PDT 24 23575979348 ps
T1213 /workspace/coverage/default/2.chip_sw_example_rom.3178476551 Aug 08 08:36:01 PM PDT 24 Aug 08 08:37:56 PM PDT 24 2514253888 ps
T281 /workspace/coverage/default/0.chip_sw_flash_init.405204683 Aug 08 08:15:13 PM PDT 24 Aug 08 08:52:35 PM PDT 24 19796754060 ps
T677 /workspace/coverage/default/98.chip_sw_all_escalation_resets.3115916619 Aug 08 08:58:33 PM PDT 24 Aug 08 09:09:12 PM PDT 24 5064147528 ps
T1214 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2417256734 Aug 08 08:52:14 PM PDT 24 Aug 08 08:58:06 PM PDT 24 3178213814 ps
T312 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1575197803 Aug 08 08:37:45 PM PDT 24 Aug 08 09:04:49 PM PDT 24 12325803826 ps
T61 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3994584329 Aug 08 08:18:17 PM PDT 24 Aug 08 08:22:15 PM PDT 24 2776887630 ps
T1215 /workspace/coverage/default/2.chip_sw_kmac_smoketest.676350799 Aug 08 08:46:19 PM PDT 24 Aug 08 08:51:15 PM PDT 24 3046829720 ps
T1216 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.912153712 Aug 08 08:23:07 PM PDT 24 Aug 08 09:23:25 PM PDT 24 13868906972 ps
T158 /workspace/coverage/default/1.chip_plic_all_irqs_10.3033024360 Aug 08 08:31:41 PM PDT 24 Aug 08 08:45:17 PM PDT 24 4207896938 ps
T1217 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3508972326 Aug 08 08:41:12 PM PDT 24 Aug 08 08:46:36 PM PDT 24 3038863340 ps
T1218 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.478932492 Aug 08 08:25:54 PM PDT 24 Aug 08 09:32:05 PM PDT 24 16045414316 ps
T1219 /workspace/coverage/default/97.chip_sw_all_escalation_resets.75673444 Aug 08 08:59:25 PM PDT 24 Aug 08 09:10:14 PM PDT 24 4631252600 ps
T1220 /workspace/coverage/default/1.chip_sw_flash_init.2297310490 Aug 08 08:24:13 PM PDT 24 Aug 08 08:54:06 PM PDT 24 19958223062 ps
T187 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.4078265226 Aug 08 08:29:56 PM PDT 24 Aug 08 08:47:20 PM PDT 24 7143590018 ps
T1221 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3052495603 Aug 08 08:17:50 PM PDT 24 Aug 08 09:53:20 PM PDT 24 51765575975 ps
T748 /workspace/coverage/default/2.chip_sw_all_escalation_resets.1525812603 Aug 08 08:36:40 PM PDT 24 Aug 08 08:46:17 PM PDT 24 5358719062 ps
T1222 /workspace/coverage/default/0.chip_sw_hmac_oneshot.346741799 Aug 08 08:19:09 PM PDT 24 Aug 08 08:24:26 PM PDT 24 3496256228 ps
T1223 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.916391677 Aug 08 08:15:51 PM PDT 24 Aug 08 08:27:40 PM PDT 24 5063230584 ps
T1224 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.4251466483 Aug 08 08:40:53 PM PDT 24 Aug 08 08:46:14 PM PDT 24 2818431486 ps
T401 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1773535819 Aug 08 08:19:51 PM PDT 24 Aug 08 08:48:47 PM PDT 24 20952446696 ps
T1225 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4070237555 Aug 08 08:48:16 PM PDT 24 Aug 08 08:56:11 PM PDT 24 8042511914 ps
T1226 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2635140596 Aug 08 08:21:27 PM PDT 24 Aug 08 08:32:46 PM PDT 24 4023149994 ps
T1227 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.4145538668 Aug 08 08:48:46 PM PDT 24 Aug 08 08:57:15 PM PDT 24 4041445330 ps
T100 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2296688920 Aug 08 08:53:23 PM PDT 24 Aug 08 08:59:54 PM PDT 24 4291832920 ps
T657 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3014060054 Aug 08 08:38:23 PM PDT 24 Aug 08 08:49:07 PM PDT 24 5091642170 ps
T1228 /workspace/coverage/default/1.chip_sw_uart_smoketest.2537753856 Aug 08 08:34:09 PM PDT 24 Aug 08 08:38:28 PM PDT 24 3011259836 ps
T1229 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2941258324 Aug 08 08:44:50 PM PDT 24 Aug 08 09:00:14 PM PDT 24 4487341164 ps
T243 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1448000056 Aug 08 08:18:48 PM PDT 24 Aug 08 08:29:41 PM PDT 24 6742031752 ps
T1230 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1344985420 Aug 08 08:19:07 PM PDT 24 Aug 08 08:28:26 PM PDT 24 8569665308 ps
T1231 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2397510230 Aug 08 08:22:14 PM PDT 24 Aug 08 08:36:32 PM PDT 24 4099747228 ps
T1232 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2052196559 Aug 08 08:58:42 PM PDT 24 Aug 08 09:04:38 PM PDT 24 3056108856 ps
T1233 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3709368033 Aug 08 08:33:23 PM PDT 24 Aug 08 08:36:28 PM PDT 24 2605309816 ps
T1234 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3108801265 Aug 08 08:18:09 PM PDT 24 Aug 08 08:24:51 PM PDT 24 7556782296 ps
T1235 /workspace/coverage/default/1.chip_sw_hmac_oneshot.3797158008 Aug 08 08:29:15 PM PDT 24 Aug 08 08:34:27 PM PDT 24 3186067148 ps
T1236 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.642355176 Aug 08 08:31:58 PM PDT 24 Aug 08 09:38:37 PM PDT 24 25243558935 ps
T1237 /workspace/coverage/default/1.rom_e2e_asm_init_prod.2641773739 Aug 08 08:36:04 PM PDT 24 Aug 08 09:46:24 PM PDT 24 15878526335 ps
T754 /workspace/coverage/default/45.chip_sw_all_escalation_resets.3619597362 Aug 08 08:52:55 PM PDT 24 Aug 08 09:02:15 PM PDT 24 5632668360 ps
T736 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3965148425 Aug 08 08:54:58 PM PDT 24 Aug 08 09:01:21 PM PDT 24 3961582744 ps
T10 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1643285832 Aug 08 08:24:03 PM PDT 24 Aug 08 08:28:33 PM PDT 24 3252819997 ps
T1238 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.244793012 Aug 08 08:18:37 PM PDT 24 Aug 08 08:23:56 PM PDT 24 2942825153 ps
T610 /workspace/coverage/default/2.chip_sw_edn_boot_mode.2454181580 Aug 08 08:39:21 PM PDT 24 Aug 08 08:49:38 PM PDT 24 2902281370 ps
T1239 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.131072731 Aug 08 08:35:49 PM PDT 24 Aug 08 08:44:58 PM PDT 24 3755008054 ps
T1240 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2078430160 Aug 08 08:37:44 PM PDT 24 Aug 08 08:43:48 PM PDT 24 3504958004 ps
T1241 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1167604909 Aug 08 08:40:26 PM PDT 24 Aug 08 09:07:09 PM PDT 24 8824566678 ps
T1242 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3438936236 Aug 08 08:28:25 PM PDT 24 Aug 08 08:35:51 PM PDT 24 4091308218 ps
T1243 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1586987856 Aug 08 08:23:15 PM PDT 24 Aug 08 08:26:09 PM PDT 24 2496138920 ps
T1244 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2991612793 Aug 08 08:48:35 PM PDT 24 Aug 08 08:56:26 PM PDT 24 4496426820 ps
T1245 /workspace/coverage/default/2.chip_tap_straps_rma.205001399 Aug 08 08:43:01 PM PDT 24 Aug 08 08:45:59 PM PDT 24 2666691345 ps
T1246 /workspace/coverage/default/0.rom_volatile_raw_unlock.1263116185 Aug 08 08:19:42 PM PDT 24 Aug 08 08:21:22 PM PDT 24 2230639720 ps
T630 /workspace/coverage/default/1.chip_tap_straps_dev.567001475 Aug 08 08:32:37 PM PDT 24 Aug 08 08:47:46 PM PDT 24 7349446117 ps
T1247 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2393842462 Aug 08 08:18:45 PM PDT 24 Aug 08 08:28:19 PM PDT 24 8756242170 ps
T1248 /workspace/coverage/default/0.chip_sw_aes_smoketest.999530235 Aug 08 08:20:34 PM PDT 24 Aug 08 08:24:32 PM PDT 24 3398698622 ps
T1249 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3062807887 Aug 08 08:41:58 PM PDT 24 Aug 08 08:48:13 PM PDT 24 4827000528 ps
T1250 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.447118617 Aug 08 08:15:54 PM PDT 24 Aug 08 08:19:43 PM PDT 24 2584442296 ps
T137 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1611360655 Aug 08 08:29:38 PM PDT 24 Aug 08 08:41:32 PM PDT 24 8025069712 ps
T680 /workspace/coverage/default/4.chip_sw_all_escalation_resets.1358962098 Aug 08 08:47:31 PM PDT 24 Aug 08 08:57:28 PM PDT 24 4802199184 ps
T168 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1432894194 Aug 08 08:20:34 PM PDT 24 Aug 08 08:30:00 PM PDT 24 5254946200 ps
T1251 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3027865993 Aug 08 08:18:43 PM PDT 24 Aug 08 08:25:56 PM PDT 24 3993355640 ps
T38 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1964848243 Aug 08 08:15:36 PM PDT 24 Aug 08 08:20:19 PM PDT 24 3156100894 ps
T1252 /workspace/coverage/default/28.chip_sw_all_escalation_resets.4209666949 Aug 08 08:54:08 PM PDT 24 Aug 08 09:06:39 PM PDT 24 5058486176 ps
T298 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2238828062 Aug 08 08:20:25 PM PDT 24 Aug 08 08:31:01 PM PDT 24 4490775032 ps
T44 /workspace/coverage/default/1.chip_sw_spi_device_tpm.812902997 Aug 08 08:22:23 PM PDT 24 Aug 08 08:30:16 PM PDT 24 3136727908 ps
T1253 /workspace/coverage/default/22.chip_sw_all_escalation_resets.3935730697 Aug 08 08:52:09 PM PDT 24 Aug 08 09:03:40 PM PDT 24 5570443208 ps
T1254 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.4258612198 Aug 08 08:37:21 PM PDT 24 Aug 08 08:44:42 PM PDT 24 6997903030 ps
T1255 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3256961220 Aug 08 08:31:47 PM PDT 24 Aug 08 09:02:34 PM PDT 24 25833618380 ps
T1256 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.36063770 Aug 08 08:56:26 PM PDT 24 Aug 08 09:01:40 PM PDT 24 4091455254 ps
T1257 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3762937757 Aug 08 08:31:57 PM PDT 24 Aug 08 08:44:49 PM PDT 24 3803451590 ps
T1258 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1650154929 Aug 08 08:34:51 PM PDT 24 Aug 08 08:39:20 PM PDT 24 2800998218 ps
T410 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3425970350 Aug 08 08:43:55 PM PDT 24 Aug 08 08:51:18 PM PDT 24 3663060072 ps
T101 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.297290908 Aug 08 08:55:51 PM PDT 24 Aug 08 09:02:25 PM PDT 24 3353078568 ps
T1259 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4006478911 Aug 08 08:17:14 PM PDT 24 Aug 08 11:34:28 PM PDT 24 255819832964 ps
T1260 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4223410220 Aug 08 08:24:47 PM PDT 24 Aug 08 08:39:50 PM PDT 24 11351274390 ps
T1261 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1499465361 Aug 08 08:37:55 PM PDT 24 Aug 08 09:05:58 PM PDT 24 13627055746 ps
T11 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2396898157 Aug 08 08:35:05 PM PDT 24 Aug 08 08:41:42 PM PDT 24 3360354424 ps
T1262 /workspace/coverage/default/1.chip_sw_example_manufacturer.2728753697 Aug 08 08:21:28 PM PDT 24 Aug 08 08:24:28 PM PDT 24 2439131708 ps
T263 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1805525571 Aug 08 08:33:24 PM PDT 24 Aug 08 08:36:01 PM PDT 24 2323338062 ps
T1263 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.4061865837 Aug 08 08:28:18 PM PDT 24 Aug 08 08:33:48 PM PDT 24 2693711342 ps
T1264 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3959711637 Aug 08 08:41:18 PM PDT 24 Aug 08 08:44:23 PM PDT 24 3092826047 ps
T1265 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.997835923 Aug 08 08:50:55 PM PDT 24 Aug 08 08:58:05 PM PDT 24 4139107266 ps
T1266 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.4257331131 Aug 08 08:25:02 PM PDT 24 Aug 08 09:27:34 PM PDT 24 15266718840 ps
T1267 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.919063567 Aug 08 08:40:15 PM PDT 24 Aug 08 09:03:15 PM PDT 24 8369160516 ps
T757 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3289395000 Aug 08 08:54:05 PM PDT 24 Aug 08 09:01:46 PM PDT 24 3716870288 ps
T1268 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2567299994 Aug 08 08:15:14 PM PDT 24 Aug 08 08:17:07 PM PDT 24 2829286492 ps
T769 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.951733122 Aug 08 08:54:55 PM PDT 24 Aug 08 09:00:38 PM PDT 24 3510396640 ps
T163 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.854907359 Aug 08 08:26:55 PM PDT 24 Aug 08 08:30:51 PM PDT 24 3251815692 ps
T1269 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3494993203 Aug 08 08:31:59 PM PDT 24 Aug 08 08:36:41 PM PDT 24 2245042454 ps
T756 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1980559149 Aug 08 08:53:22 PM PDT 24 Aug 08 09:01:11 PM PDT 24 4159221948 ps
T1270 /workspace/coverage/default/2.chip_sw_csrng_kat_test.2945392807 Aug 08 08:39:15 PM PDT 24 Aug 08 08:44:36 PM PDT 24 2749420376 ps
T1271 /workspace/coverage/default/2.chip_sw_aon_timer_irq.1539968576 Aug 08 08:38:54 PM PDT 24 Aug 08 08:47:17 PM PDT 24 4290272600 ps
T1272 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.317649807 Aug 08 08:48:12 PM PDT 24 Aug 08 08:57:51 PM PDT 24 6825956868 ps
T627 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.56367101 Aug 08 08:20:33 PM PDT 24 Aug 08 08:31:39 PM PDT 24 5362881089 ps
T1273 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3817623441 Aug 08 08:31:21 PM PDT 24 Aug 08 09:21:44 PM PDT 24 27749244139 ps
T102 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.53708607 Aug 08 08:48:31 PM PDT 24 Aug 08 08:55:05 PM PDT 24 4398628616 ps
T1274 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.498616858 Aug 08 08:21:43 PM PDT 24 Aug 08 08:26:00 PM PDT 24 2791494196 ps
T737 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.441654620 Aug 08 08:54:38 PM PDT 24 Aug 08 08:59:49 PM PDT 24 3537358052 ps
T1275 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3500430447 Aug 08 08:48:58 PM PDT 24 Aug 08 08:59:27 PM PDT 24 4259957431 ps
T1276 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1784396811 Aug 08 08:35:19 PM PDT 24 Aug 08 08:54:50 PM PDT 24 6473994965 ps
T1277 /workspace/coverage/default/0.chip_sw_rv_timer_irq.2322258466 Aug 08 08:18:22 PM PDT 24 Aug 08 08:22:54 PM PDT 24 3356293184 ps
T1278 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.4166912856 Aug 08 08:29:53 PM PDT 24 Aug 08 08:33:49 PM PDT 24 2851671428 ps
T1279 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3839710771 Aug 08 08:31:36 PM PDT 24 Aug 08 08:40:10 PM PDT 24 4122062254 ps
T1280 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.265955641 Aug 08 08:37:25 PM PDT 24 Aug 08 08:49:49 PM PDT 24 7810659362 ps
T1281 /workspace/coverage/default/0.chip_sw_kmac_entropy.3438762844 Aug 08 08:16:47 PM PDT 24 Aug 08 08:21:49 PM PDT 24 3064692344 ps
T1282 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2419460462 Aug 08 08:40:27 PM PDT 24 Aug 08 08:56:49 PM PDT 24 6798869102 ps
T646 /workspace/coverage/default/2.chip_sw_plic_sw_irq.3233737061 Aug 08 08:41:19 PM PDT 24 Aug 08 08:46:29 PM PDT 24 3251988964 ps
T1283 /workspace/coverage/default/0.chip_tap_straps_rma.3608681599 Aug 08 08:19:11 PM PDT 24 Aug 08 08:25:11 PM PDT 24 3641653023 ps
T1284 /workspace/coverage/default/1.chip_sw_aes_enc.781773100 Aug 08 08:27:04 PM PDT 24 Aug 08 08:31:47 PM PDT 24 3069491474 ps
T1285 /workspace/coverage/default/16.chip_sw_all_escalation_resets.2639683062 Aug 08 08:50:38 PM PDT 24 Aug 08 09:03:30 PM PDT 24 6231883564 ps
T1286 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2037264124 Aug 08 08:40:01 PM PDT 24 Aug 08 09:33:10 PM PDT 24 11547640563 ps
T1287 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3863135746 Aug 08 08:37:53 PM PDT 24 Aug 08 08:43:58 PM PDT 24 3577851095 ps
T1288 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.395442116 Aug 08 08:43:42 PM PDT 24 Aug 08 08:56:28 PM PDT 24 10780910062 ps
T1289 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.4244073263 Aug 08 08:28:04 PM PDT 24 Aug 08 08:37:20 PM PDT 24 4176629440 ps
T1290 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2386441232 Aug 08 08:30:32 PM PDT 24 Aug 08 08:40:21 PM PDT 24 4766934070 ps
T1291 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3141885032 Aug 08 08:44:06 PM PDT 24 Aug 08 08:49:14 PM PDT 24 2937849217 ps
T1292 /workspace/coverage/default/0.chip_sw_kmac_app_rom.1146403019 Aug 08 08:16:20 PM PDT 24 Aug 08 08:19:12 PM PDT 24 2678206572 ps
T1293 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1177718346 Aug 08 08:31:54 PM PDT 24 Aug 08 09:03:50 PM PDT 24 17775030657 ps
T1294 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2928743763 Aug 08 08:29:21 PM PDT 24 Aug 08 08:57:53 PM PDT 24 8207666012 ps
T768 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3051974834 Aug 08 08:48:05 PM PDT 24 Aug 08 08:56:01 PM PDT 24 3419137200 ps
T1295 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3762576768 Aug 08 08:26:13 PM PDT 24 Aug 08 08:41:21 PM PDT 24 10005304088 ps
T1296 /workspace/coverage/default/0.chip_sival_flash_info_access.2575649127 Aug 08 08:15:07 PM PDT 24 Aug 08 08:19:34 PM PDT 24 2646658784 ps
T1297 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2976594770 Aug 08 08:24:28 PM PDT 24 Aug 08 09:14:46 PM PDT 24 10837160120 ps
T1298 /workspace/coverage/default/1.chip_sw_kmac_smoketest.2324571943 Aug 08 08:34:25 PM PDT 24 Aug 08 08:40:04 PM PDT 24 3101139656 ps
T1299 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2433117625 Aug 08 08:25:12 PM PDT 24 Aug 08 08:52:32 PM PDT 24 7327543982 ps
T1300 /workspace/coverage/default/0.chip_sw_kmac_smoketest.3183951014 Aug 08 08:22:04 PM PDT 24 Aug 08 08:28:09 PM PDT 24 3363635800 ps
T1301 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.1266997158 Aug 08 08:22:00 PM PDT 24 Aug 08 08:37:29 PM PDT 24 4910271120 ps
T1302 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1383031014 Aug 08 08:51:09 PM PDT 24 Aug 08 09:26:33 PM PDT 24 12733148196 ps
T635 /workspace/coverage/default/10.chip_sw_all_escalation_resets.3150299888 Aug 08 08:51:20 PM PDT 24 Aug 08 09:02:54 PM PDT 24 5075910156 ps
T1303 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2138305365 Aug 08 08:48:53 PM PDT 24 Aug 08 08:57:55 PM PDT 24 3813814712 ps
T1304 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.790280326 Aug 08 08:23:38 PM PDT 24 Aug 08 08:26:54 PM PDT 24 2294888695 ps
T1305 /workspace/coverage/default/1.rom_e2e_asm_init_rma.1949609444 Aug 08 08:38:17 PM PDT 24 Aug 08 09:42:30 PM PDT 24 15016166924 ps
T1306 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2198549894 Aug 08 08:49:09 PM PDT 24 Aug 08 08:59:40 PM PDT 24 4648613800 ps
T681 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1601589177 Aug 08 08:51:21 PM PDT 24 Aug 08 08:56:38 PM PDT 24 3762757528 ps
T1307 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.4210804207 Aug 08 08:27:10 PM PDT 24 Aug 08 08:36:03 PM PDT 24 5131293092 ps
T142 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.3005867310 Aug 08 08:24:08 PM PDT 24 Aug 08 09:19:33 PM PDT 24 21709010150 ps
T1308 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3675972949 Aug 08 08:54:03 PM PDT 24 Aug 08 08:59:41 PM PDT 24 3927785046 ps
T12 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1841509729 Aug 08 08:15:51 PM PDT 24 Aug 08 08:21:58 PM PDT 24 3532036584 ps
T1309 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2856039399 Aug 08 08:17:49 PM PDT 24 Aug 08 08:54:25 PM PDT 24 23592755982 ps
T1310 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2368051421 Aug 08 08:42:28 PM PDT 24 Aug 08 08:53:12 PM PDT 24 4897444610 ps
T1311 /workspace/coverage/default/1.rom_volatile_raw_unlock.1962491407 Aug 08 08:35:52 PM PDT 24 Aug 08 08:37:43 PM PDT 24 2164987162 ps
T1312 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.76583474 Aug 08 08:33:59 PM PDT 24 Aug 08 08:37:42 PM PDT 24 2923933680 ps
T1313 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.4045154450 Aug 08 08:35:02 PM PDT 24 Aug 08 09:04:03 PM PDT 24 8741586194 ps
T628 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3628321352 Aug 08 08:31:58 PM PDT 24 Aug 08 08:40:03 PM PDT 24 4086005310 ps
T645 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.118330585 Aug 08 08:26:07 PM PDT 24 Aug 08 08:29:47 PM PDT 24 3455199480 ps
T1314 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2718624345 Aug 08 08:37:32 PM PDT 24 Aug 08 09:39:55 PM PDT 24 15766193118 ps
T741 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.861819183 Aug 08 08:54:25 PM PDT 24 Aug 08 09:00:10 PM PDT 24 4191209544 ps
T1315 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1215229638 Aug 08 08:37:24 PM PDT 24 Aug 08 08:45:02 PM PDT 24 5492128225 ps
T1316 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.217061778 Aug 08 08:39:32 PM PDT 24 Aug 08 09:00:56 PM PDT 24 9516732790 ps
T1317 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3792697849 Aug 08 08:18:20 PM PDT 24 Aug 08 08:26:40 PM PDT 24 5107528408 ps
T1318 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.4185279599 Aug 08 08:16:11 PM PDT 24 Aug 08 08:34:12 PM PDT 24 13056143110 ps
T282 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.676693783 Aug 08 08:16:56 PM PDT 24 Aug 08 09:52:36 PM PDT 24 51727489624 ps
T1319 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1172085181 Aug 08 08:46:30 PM PDT 24 Aug 08 08:57:29 PM PDT 24 3929942246 ps
T325 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.3429705643 Aug 08 08:43:19 PM PDT 24 Aug 08 08:50:47 PM PDT 24 3736983320 ps
T1320 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1645334449 Aug 08 08:47:25 PM PDT 24 Aug 08 08:57:36 PM PDT 24 4213427048 ps
T1321 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2368787799 Aug 08 08:51:53 PM PDT 24 Aug 08 08:59:19 PM PDT 24 3211604446 ps
T1322 /workspace/coverage/default/4.chip_tap_straps_testunlock0.2977075021 Aug 08 08:47:36 PM PDT 24 Aug 08 08:58:37 PM PDT 24 7620431734 ps
T1323 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3874842978 Aug 08 08:57:37 PM PDT 24 Aug 08 09:03:31 PM PDT 24 3560965478 ps
T1324 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1308658701 Aug 08 08:55:06 PM PDT 24 Aug 08 09:00:58 PM PDT 24 3332235620 ps
T204 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3172040063 Aug 08 08:34:14 PM PDT 24 Aug 08 08:44:14 PM PDT 24 7459754399 ps
T326 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.791451200 Aug 08 08:31:54 PM PDT 24 Aug 08 08:41:42 PM PDT 24 3676656104 ps
T1325 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.728546468 Aug 08 08:43:14 PM PDT 24 Aug 08 08:51:08 PM PDT 24 4632394988 ps
T1326 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.4175115789 Aug 08 08:48:51 PM PDT 24 Aug 08 09:01:20 PM PDT 24 11035494465 ps
T1327 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1954057912 Aug 08 08:23:55 PM PDT 24 Aug 08 09:44:52 PM PDT 24 15153981636 ps
T1328 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1914026247 Aug 08 08:39:28 PM PDT 24 Aug 08 08:50:02 PM PDT 24 4443534188 ps
T1329 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3122282639 Aug 08 08:29:48 PM PDT 24 Aug 08 08:38:13 PM PDT 24 10149613825 ps
T1330 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1019392340 Aug 08 08:25:10 PM PDT 24 Aug 08 10:06:22 PM PDT 24 23718983540 ps
T1331 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3027099658 Aug 08 08:53:57 PM PDT 24 Aug 08 09:02:10 PM PDT 24 3158632100 ps
T1332 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2366100202 Aug 08 08:21:31 PM PDT 24 Aug 08 08:29:31 PM PDT 24 3553869400 ps
T750 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3526590425 Aug 08 08:53:33 PM PDT 24 Aug 08 09:00:46 PM PDT 24 3300688038 ps
T728 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1736982302 Aug 08 08:58:04 PM PDT 24 Aug 08 09:05:39 PM PDT 24 4376326040 ps
T1333 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2149413540 Aug 08 08:50:44 PM PDT 24 Aug 08 09:02:01 PM PDT 24 4786299432 ps
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