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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.28 95.50 94.47 95.47 95.36 97.35 99.52


Total test records in report: 2940
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T1011 /workspace/coverage/default/0.chip_sw_uart_smoketest.2075702560 Aug 08 08:20:39 PM PDT 24 Aug 08 08:24:58 PM PDT 24 2872934184 ps
T700 /workspace/coverage/default/13.chip_sw_all_escalation_resets.3279831821 Aug 08 08:50:05 PM PDT 24 Aug 08 09:01:33 PM PDT 24 5968653346 ps
T146 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1987618149 Aug 08 08:15:23 PM PDT 24 Aug 08 08:24:35 PM PDT 24 6731140960 ps
T1012 /workspace/coverage/default/0.chip_sw_aes_enc.2760027904 Aug 08 08:19:01 PM PDT 24 Aug 08 08:24:36 PM PDT 24 3529000658 ps
T1013 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3916649323 Aug 08 08:43:18 PM PDT 24 Aug 08 08:56:22 PM PDT 24 4002089798 ps
T323 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.82740307 Aug 08 08:23:10 PM PDT 24 Aug 08 08:33:09 PM PDT 24 4057116568 ps
T710 /workspace/coverage/default/60.chip_sw_all_escalation_resets.4174556798 Aug 08 08:55:53 PM PDT 24 Aug 08 09:05:59 PM PDT 24 5898310270 ps
T253 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.5444066 Aug 08 08:57:08 PM PDT 24 Aug 08 09:04:16 PM PDT 24 3756549620 ps
T1014 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1303401166 Aug 08 08:27:12 PM PDT 24 Aug 08 08:45:40 PM PDT 24 7200278416 ps
T1015 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.264375410 Aug 08 08:27:18 PM PDT 24 Aug 08 08:51:19 PM PDT 24 7731699532 ps
T1016 /workspace/coverage/default/2.chip_sw_aes_smoketest.4260813121 Aug 08 08:47:10 PM PDT 24 Aug 08 08:51:47 PM PDT 24 2483908712 ps
T313 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2774913571 Aug 08 08:40:44 PM PDT 24 Aug 08 09:02:10 PM PDT 24 5679350630 ps
T200 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.1329425319 Aug 08 08:15:58 PM PDT 24 Aug 08 08:24:07 PM PDT 24 6680746052 ps
T720 /workspace/coverage/default/27.chip_sw_all_escalation_resets.2973525898 Aug 08 08:52:47 PM PDT 24 Aug 08 09:01:14 PM PDT 24 4936017720 ps
T1017 /workspace/coverage/default/0.rom_keymgr_functest.3166448422 Aug 08 08:22:37 PM PDT 24 Aug 08 08:30:35 PM PDT 24 4281328180 ps
T1018 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.829025137 Aug 08 08:39:59 PM PDT 24 Aug 08 08:54:13 PM PDT 24 5888710999 ps
T24 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2839142342 Aug 08 08:26:34 PM PDT 24 Aug 08 09:21:58 PM PDT 24 20566350979 ps
T1019 /workspace/coverage/default/0.chip_sw_all_escalation_resets.2347994624 Aug 08 08:15:58 PM PDT 24 Aug 08 08:25:49 PM PDT 24 5628592452 ps
T1020 /workspace/coverage/default/2.chip_sival_flash_info_access.189852476 Aug 08 08:35:13 PM PDT 24 Aug 08 08:40:05 PM PDT 24 3385790084 ps
T702 /workspace/coverage/default/50.chip_sw_all_escalation_resets.1782619592 Aug 08 08:53:17 PM PDT 24 Aug 08 09:03:51 PM PDT 24 5520080426 ps
T26 /workspace/coverage/default/0.chip_sw_usbdev_stream.1392267814 Aug 08 08:15:32 PM PDT 24 Aug 08 09:33:40 PM PDT 24 18360061520 ps
T1021 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3516321217 Aug 08 08:19:01 PM PDT 24 Aug 08 08:24:55 PM PDT 24 5358001020 ps
T695 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.642326803 Aug 08 08:52:11 PM PDT 24 Aug 08 08:58:05 PM PDT 24 2967367216 ps
T150 /workspace/coverage/default/0.chip_sw_usbdev_config_host.1652235100 Aug 08 08:15:45 PM PDT 24 Aug 08 08:43:49 PM PDT 24 7784261200 ps
T1022 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1142033088 Aug 08 08:34:08 PM PDT 24 Aug 08 08:41:46 PM PDT 24 3785718478 ps
T1023 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.4271466260 Aug 08 08:17:15 PM PDT 24 Aug 08 08:31:06 PM PDT 24 5914976836 ps
T1024 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.237112280 Aug 08 08:26:28 PM PDT 24 Aug 08 09:33:59 PM PDT 24 14794454055 ps
T1025 /workspace/coverage/default/1.chip_sw_aes_smoketest.1163517374 Aug 08 08:33:39 PM PDT 24 Aug 08 08:38:33 PM PDT 24 2764653948 ps
T1026 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1078469596 Aug 08 08:25:04 PM PDT 24 Aug 08 09:30:45 PM PDT 24 15082195252 ps
T1027 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3258380093 Aug 08 08:21:13 PM PDT 24 Aug 08 08:52:28 PM PDT 24 7683572344 ps
T296 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1713631348 Aug 08 08:31:49 PM PDT 24 Aug 08 08:38:39 PM PDT 24 5310885128 ps
T1028 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3938242157 Aug 08 08:49:02 PM PDT 24 Aug 08 09:00:04 PM PDT 24 4546227096 ps
T1029 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1310401197 Aug 08 08:20:24 PM PDT 24 Aug 08 08:37:08 PM PDT 24 6971949973 ps
T1030 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1039394367 Aug 08 08:49:09 PM PDT 24 Aug 08 09:05:46 PM PDT 24 12865914809 ps
T1031 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.1806256610 Aug 08 08:25:07 PM PDT 24 Aug 08 08:44:18 PM PDT 24 6045777240 ps
T1032 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.513478214 Aug 08 08:50:53 PM PDT 24 Aug 08 09:26:37 PM PDT 24 12243123812 ps
T1033 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1102595116 Aug 08 08:29:50 PM PDT 24 Aug 08 08:34:53 PM PDT 24 2887494465 ps
T239 /workspace/coverage/default/65.chip_sw_all_escalation_resets.1353579185 Aug 08 08:56:08 PM PDT 24 Aug 08 09:06:00 PM PDT 24 4524751296 ps
T1034 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.941926314 Aug 08 08:29:51 PM PDT 24 Aug 08 09:58:48 PM PDT 24 15864271930 ps
T297 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3855252290 Aug 08 08:43:53 PM PDT 24 Aug 08 08:51:57 PM PDT 24 3688560456 ps
T219 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.29919823 Aug 08 08:37:27 PM PDT 24 Aug 08 09:26:16 PM PDT 24 20536444065 ps
T74 /workspace/coverage/default/2.chip_tap_straps_testunlock0.2181184673 Aug 08 08:43:29 PM PDT 24 Aug 08 08:47:30 PM PDT 24 4069913751 ps
T1035 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1556114521 Aug 08 08:52:12 PM PDT 24 Aug 08 09:32:51 PM PDT 24 13125303338 ps
T660 /workspace/coverage/default/0.rom_raw_unlock.23805743 Aug 08 08:21:34 PM PDT 24 Aug 08 08:25:48 PM PDT 24 4511099291 ps
T675 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2166527369 Aug 08 08:56:46 PM PDT 24 Aug 08 09:03:27 PM PDT 24 4128534616 ps
T1036 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3022901034 Aug 08 08:15:28 PM PDT 24 Aug 08 08:26:13 PM PDT 24 4496646768 ps
T678 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.833951807 Aug 08 08:56:09 PM PDT 24 Aug 08 09:02:45 PM PDT 24 4210535996 ps
T1037 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3053585962 Aug 08 08:16:35 PM PDT 24 Aug 08 08:26:41 PM PDT 24 4673876112 ps
T1038 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3146544345 Aug 08 08:47:13 PM PDT 24 Aug 08 08:55:56 PM PDT 24 6040090053 ps
T1039 /workspace/coverage/default/0.rom_e2e_asm_init_dev.2526540413 Aug 08 08:23:57 PM PDT 24 Aug 08 09:33:53 PM PDT 24 15898559864 ps
T1040 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.720909291 Aug 08 08:23:46 PM PDT 24 Aug 08 08:29:57 PM PDT 24 3589961572 ps
T1041 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.562579508 Aug 08 08:18:42 PM PDT 24 Aug 08 08:28:39 PM PDT 24 5190537640 ps
T716 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3721582106 Aug 08 08:55:05 PM PDT 24 Aug 08 09:01:53 PM PDT 24 3760303434 ps
T159 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2849805985 Aug 08 08:19:15 PM PDT 24 Aug 08 08:40:15 PM PDT 24 11411245240 ps
T79 /workspace/coverage/default/0.chip_sw_usbdev_pullup.1520996713 Aug 08 08:14:33 PM PDT 24 Aug 08 08:18:31 PM PDT 24 3254988584 ps
T240 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.4028862258 Aug 08 08:25:54 PM PDT 24 Aug 08 08:34:20 PM PDT 24 6115770084 ps
T714 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3853068633 Aug 08 08:56:39 PM PDT 24 Aug 08 09:03:27 PM PDT 24 3785833722 ps
T1042 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.411772536 Aug 08 08:17:22 PM PDT 24 Aug 08 08:40:28 PM PDT 24 7323235796 ps
T1043 /workspace/coverage/default/1.chip_sw_edn_kat.129447233 Aug 08 08:28:27 PM PDT 24 Aug 08 08:39:14 PM PDT 24 3246445480 ps
T740 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.756446988 Aug 08 08:55:30 PM PDT 24 Aug 08 09:01:42 PM PDT 24 3641526800 ps
T291 /workspace/coverage/default/76.chip_sw_all_escalation_resets.4253539610 Aug 08 08:56:59 PM PDT 24 Aug 08 09:07:22 PM PDT 24 4676468940 ps
T1044 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.983462445 Aug 08 08:24:41 PM PDT 24 Aug 08 08:31:30 PM PDT 24 4732383400 ps
T280 /workspace/coverage/default/2.chip_sw_flash_init.2647388473 Aug 08 08:35:54 PM PDT 24 Aug 08 09:07:53 PM PDT 24 18358650779 ps
T1045 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2812659609 Aug 08 08:50:34 PM PDT 24 Aug 08 09:37:44 PM PDT 24 11340826650 ps
T55 /workspace/coverage/default/2.chip_jtag_csr_rw.2444428481 Aug 08 08:35:46 PM PDT 24 Aug 08 09:11:47 PM PDT 24 20929894195 ps
T394 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1359856338 Aug 08 08:41:18 PM PDT 24 Aug 08 08:52:51 PM PDT 24 9051103760 ps
T395 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.4230112634 Aug 08 08:41:02 PM PDT 24 Aug 08 08:52:36 PM PDT 24 4494082488 ps
T322 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3685761158 Aug 08 08:18:15 PM PDT 24 Aug 08 08:26:55 PM PDT 24 4377458682 ps
T396 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3084288732 Aug 08 08:23:09 PM PDT 24 Aug 08 09:24:06 PM PDT 24 15393104740 ps
T397 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2183852606 Aug 08 08:54:08 PM PDT 24 Aug 08 09:01:14 PM PDT 24 4086064676 ps
T398 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2151366921 Aug 08 08:33:10 PM PDT 24 Aug 08 08:54:02 PM PDT 24 7012516888 ps
T344 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1368005249 Aug 08 08:20:56 PM PDT 24 Aug 08 08:28:43 PM PDT 24 6489634592 ps
T399 /workspace/coverage/default/81.chip_sw_all_escalation_resets.3928425117 Aug 08 08:57:52 PM PDT 24 Aug 08 09:08:07 PM PDT 24 5349283536 ps
T400 /workspace/coverage/default/1.chip_sw_uart_tx_rx.2972475473 Aug 08 08:22:42 PM PDT 24 Aug 08 08:30:15 PM PDT 24 4048533736 ps
T1046 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.4039988760 Aug 08 08:26:14 PM PDT 24 Aug 08 09:38:22 PM PDT 24 17656547642 ps
T1047 /workspace/coverage/default/2.rom_keymgr_functest.1605222093 Aug 08 08:46:10 PM PDT 24 Aug 08 08:52:31 PM PDT 24 5413755080 ps
T1048 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1933755099 Aug 08 08:41:21 PM PDT 24 Aug 08 09:34:53 PM PDT 24 17298010710 ps
T201 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3993125855 Aug 08 08:24:06 PM PDT 24 Aug 08 08:35:48 PM PDT 24 6489095762 ps
T66 /workspace/coverage/default/1.chip_sw_alert_test.297417954 Aug 08 08:29:12 PM PDT 24 Aug 08 08:35:14 PM PDT 24 2900825788 ps
T1049 /workspace/coverage/default/1.chip_sw_flash_crash_alert.175836029 Aug 08 08:32:33 PM PDT 24 Aug 08 08:42:38 PM PDT 24 5173083856 ps
T1050 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.102550671 Aug 08 08:35:59 PM PDT 24 Aug 09 12:15:47 AM PDT 24 77636362983 ps
T1051 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1824244925 Aug 08 08:19:19 PM PDT 24 Aug 08 08:28:16 PM PDT 24 5026841376 ps
T1052 /workspace/coverage/default/1.chip_sw_power_idle_load.1400509357 Aug 08 08:32:46 PM PDT 24 Aug 08 08:44:03 PM PDT 24 4998806246 ps
T337 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3464981339 Aug 08 08:19:25 PM PDT 24 Aug 08 08:35:53 PM PDT 24 5525514230 ps
T1053 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1933522299 Aug 08 08:20:54 PM PDT 24 Aug 08 08:57:23 PM PDT 24 8875293720 ps
T1054 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1307247701 Aug 08 08:30:39 PM PDT 24 Aug 08 09:43:53 PM PDT 24 15313864260 ps
T1055 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3887648589 Aug 08 08:39:48 PM PDT 24 Aug 08 08:58:40 PM PDT 24 8378270710 ps
T1056 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1239794256 Aug 08 08:49:37 PM PDT 24 Aug 08 09:10:02 PM PDT 24 13872872930 ps
T65 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2707879428 Aug 08 08:16:45 PM PDT 24 Aug 08 08:21:36 PM PDT 24 4024867752 ps
T328 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1535102073 Aug 08 08:37:30 PM PDT 24 Aug 08 08:49:07 PM PDT 24 3652601840 ps
T613 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2034348537 Aug 08 08:18:54 PM PDT 24 Aug 08 09:30:23 PM PDT 24 25002845164 ps
T1057 /workspace/coverage/default/1.chip_sw_example_flash.410405077 Aug 08 08:21:39 PM PDT 24 Aug 08 08:25:37 PM PDT 24 2915634028 ps
T753 /workspace/coverage/default/31.chip_sw_all_escalation_resets.607858336 Aug 08 08:53:39 PM PDT 24 Aug 08 09:02:22 PM PDT 24 5617503648 ps
T1058 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2847851792 Aug 08 08:16:38 PM PDT 24 Aug 08 08:24:39 PM PDT 24 19217827000 ps
T1059 /workspace/coverage/default/2.chip_sw_aes_enc.1262843245 Aug 08 08:39:57 PM PDT 24 Aug 08 08:45:10 PM PDT 24 3026349630 ps
T202 /workspace/coverage/default/0.chip_sw_power_virus.3015977932 Aug 08 08:24:20 PM PDT 24 Aug 08 08:51:43 PM PDT 24 6178428064 ps
T254 /workspace/coverage/default/67.chip_sw_all_escalation_resets.4002525009 Aug 08 08:55:38 PM PDT 24 Aug 08 09:05:24 PM PDT 24 5640804684 ps
T1060 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1173252308 Aug 08 08:21:06 PM PDT 24 Aug 08 08:36:57 PM PDT 24 6296370760 ps
T1061 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1566449530 Aug 08 08:39:01 PM PDT 24 Aug 08 09:58:02 PM PDT 24 19646293928 ps
T743 /workspace/coverage/default/54.chip_sw_all_escalation_resets.3058847008 Aug 08 08:53:30 PM PDT 24 Aug 08 09:03:38 PM PDT 24 5524385632 ps
T1062 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3734165500 Aug 08 08:15:55 PM PDT 24 Aug 08 08:28:56 PM PDT 24 6432141909 ps
T615 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1348480392 Aug 08 08:18:27 PM PDT 24 Aug 08 08:23:16 PM PDT 24 2626510707 ps
T346 /workspace/coverage/default/84.chip_sw_all_escalation_resets.2988143920 Aug 08 08:57:38 PM PDT 24 Aug 08 09:08:46 PM PDT 24 5812237668 ps
T352 /workspace/coverage/default/0.rom_e2e_asm_init_prod.2128108199 Aug 08 08:31:24 PM PDT 24 Aug 08 09:58:15 PM PDT 24 15369240196 ps
T353 /workspace/coverage/default/92.chip_sw_all_escalation_resets.3115311300 Aug 08 08:57:40 PM PDT 24 Aug 08 09:06:32 PM PDT 24 5443375292 ps
T354 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3705270450 Aug 08 08:15:36 PM PDT 24 Aug 08 08:22:42 PM PDT 24 3684489512 ps
T347 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.4032492823 Aug 08 08:54:19 PM PDT 24 Aug 08 09:03:44 PM PDT 24 4048604584 ps
T355 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1720380719 Aug 08 08:18:37 PM PDT 24 Aug 08 08:26:56 PM PDT 24 3566780266 ps
T356 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2074746825 Aug 08 08:31:01 PM PDT 24 Aug 08 08:54:46 PM PDT 24 10025997296 ps
T133 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1334317560 Aug 08 08:31:19 PM PDT 24 Aug 08 08:37:36 PM PDT 24 5793789178 ps
T357 /workspace/coverage/default/2.chip_sw_hmac_multistream.2434888127 Aug 08 08:39:44 PM PDT 24 Aug 08 09:07:35 PM PDT 24 7948293096 ps
T358 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3357464018 Aug 08 08:40:08 PM PDT 24 Aug 08 09:08:00 PM PDT 24 8373508052 ps
T1063 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1685385707 Aug 08 08:18:14 PM PDT 24 Aug 08 08:33:14 PM PDT 24 8494134577 ps
T1064 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2644260800 Aug 08 08:16:52 PM PDT 24 Aug 08 08:34:19 PM PDT 24 6075041199 ps
T1065 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2196991017 Aug 08 08:18:27 PM PDT 24 Aug 08 08:23:37 PM PDT 24 3323278049 ps
T1066 /workspace/coverage/default/3.chip_tap_straps_rma.1714690466 Aug 08 08:46:03 PM PDT 24 Aug 08 08:49:02 PM PDT 24 3059579844 ps
T1067 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4117150879 Aug 08 08:16:24 PM PDT 24 Aug 08 08:25:49 PM PDT 24 4421986922 ps
T1068 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2547559978 Aug 08 08:33:34 PM PDT 24 Aug 08 09:06:51 PM PDT 24 10064468463 ps
T1069 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.4033443070 Aug 08 08:23:14 PM PDT 24 Aug 08 08:26:21 PM PDT 24 3251053048 ps
T1070 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1119688151 Aug 08 08:24:57 PM PDT 24 Aug 08 09:17:17 PM PDT 24 12019561143 ps
T273 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3132331367 Aug 08 08:29:21 PM PDT 24 Aug 08 09:50:08 PM PDT 24 15930213592 ps
T1071 /workspace/coverage/default/2.chip_sw_otbn_randomness.366554329 Aug 08 08:38:27 PM PDT 24 Aug 08 08:54:32 PM PDT 24 6494326750 ps
T735 /workspace/coverage/default/32.chip_sw_all_escalation_resets.1341919215 Aug 08 08:51:50 PM PDT 24 Aug 08 09:01:11 PM PDT 24 4810824492 ps
T1072 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3305987150 Aug 08 08:18:43 PM PDT 24 Aug 08 09:14:46 PM PDT 24 43484008209 ps
T1073 /workspace/coverage/default/2.rom_e2e_static_critical.1326120169 Aug 08 08:50:53 PM PDT 24 Aug 08 10:07:18 PM PDT 24 16828434316 ps
T42 /workspace/coverage/default/0.chip_sw_spi_device_tpm.1370941744 Aug 08 08:16:26 PM PDT 24 Aug 08 08:21:27 PM PDT 24 3471129014 ps
T766 /workspace/coverage/default/61.chip_sw_all_escalation_resets.743528815 Aug 08 08:55:38 PM PDT 24 Aug 08 09:05:24 PM PDT 24 6521169320 ps
T1074 /workspace/coverage/default/2.rom_e2e_shutdown_output.1816246919 Aug 08 08:51:47 PM PDT 24 Aug 08 09:46:01 PM PDT 24 27567684679 ps
T1075 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2480543740 Aug 08 08:40:56 PM PDT 24 Aug 08 08:46:09 PM PDT 24 2994446616 ps
T1076 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2990744858 Aug 08 08:21:12 PM PDT 24 Aug 08 08:24:49 PM PDT 24 2920099546 ps
T1077 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2122083929 Aug 08 08:27:29 PM PDT 24 Aug 08 09:27:01 PM PDT 24 14657455275 ps
T412 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.3427659998 Aug 08 08:21:00 PM PDT 24 Aug 08 08:54:05 PM PDT 24 12083784055 ps
T212 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1520865940 Aug 08 08:27:24 PM PDT 24 Aug 08 08:58:56 PM PDT 24 22669905672 ps
T752 /workspace/coverage/default/99.chip_sw_all_escalation_resets.3578826838 Aug 08 08:58:08 PM PDT 24 Aug 08 09:07:25 PM PDT 24 5348568968 ps
T385 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1332227491 Aug 08 08:32:21 PM PDT 24 Aug 08 08:40:18 PM PDT 24 7321762520 ps
T1078 /workspace/coverage/default/4.chip_sw_uart_tx_rx.2197808739 Aug 08 08:47:37 PM PDT 24 Aug 08 08:55:35 PM PDT 24 4296909192 ps
T1079 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3938888228 Aug 08 08:17:56 PM PDT 24 Aug 08 08:25:51 PM PDT 24 2938731702 ps
T56 /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.1855226450 Aug 08 08:35:14 PM PDT 24 Aug 08 08:39:08 PM PDT 24 2873582327 ps
T1080 /workspace/coverage/default/1.rom_keymgr_functest.4207384030 Aug 08 08:33:48 PM PDT 24 Aug 08 08:43:57 PM PDT 24 4655142488 ps
T274 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2858031908 Aug 08 08:18:53 PM PDT 24 Aug 08 09:34:20 PM PDT 24 15220493926 ps
T1081 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3268483442 Aug 08 08:50:05 PM PDT 24 Aug 08 10:00:03 PM PDT 24 17886160180 ps
T41 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3836940359 Aug 08 08:17:52 PM PDT 24 Aug 08 08:24:50 PM PDT 24 5829116208 ps
T629 /workspace/coverage/default/2.chip_tap_straps_dev.3805489114 Aug 08 08:43:28 PM PDT 24 Aug 08 08:53:34 PM PDT 24 6626638990 ps
T767 /workspace/coverage/default/42.chip_sw_all_escalation_resets.1219250571 Aug 08 08:52:28 PM PDT 24 Aug 08 09:03:34 PM PDT 24 5962929948 ps
T1082 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2237217980 Aug 08 08:29:18 PM PDT 24 Aug 08 09:00:48 PM PDT 24 9668643793 ps
T338 /workspace/coverage/default/0.chip_sw_pattgen_ios.4133145448 Aug 08 08:14:48 PM PDT 24 Aug 08 08:18:25 PM PDT 24 2939905272 ps
T255 /workspace/coverage/default/74.chip_sw_all_escalation_resets.2874064494 Aug 08 08:58:22 PM PDT 24 Aug 08 09:06:51 PM PDT 24 5550088536 ps
T1083 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2132726674 Aug 08 08:30:47 PM PDT 24 Aug 08 08:39:56 PM PDT 24 5870337832 ps
T1084 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1473281995 Aug 08 08:29:09 PM PDT 24 Aug 08 08:34:54 PM PDT 24 17871035936 ps
T1085 /workspace/coverage/default/1.chip_sival_flash_info_access.1537074063 Aug 08 08:23:44 PM PDT 24 Aug 08 08:28:06 PM PDT 24 2805778360 ps
T739 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3046929779 Aug 08 08:51:19 PM PDT 24 Aug 08 08:57:10 PM PDT 24 3911902120 ps
T1086 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.292207232 Aug 08 08:38:01 PM PDT 24 Aug 08 09:01:07 PM PDT 24 6166916568 ps
T1087 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1471162502 Aug 08 08:31:28 PM PDT 24 Aug 08 09:20:47 PM PDT 24 11334437971 ps
T644 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2372602914 Aug 08 08:18:52 PM PDT 24 Aug 08 08:23:54 PM PDT 24 3344615396 ps
T1088 /workspace/coverage/default/2.chip_sw_uart_tx_rx.2975128566 Aug 08 08:34:02 PM PDT 24 Aug 08 08:42:50 PM PDT 24 4225258740 ps
T1089 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3230999629 Aug 08 08:46:48 PM PDT 24 Aug 08 08:51:44 PM PDT 24 2343035900 ps
T1090 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3144249287 Aug 08 08:23:37 PM PDT 24 Aug 08 10:01:51 PM PDT 24 22887678880 ps
T1091 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2345155738 Aug 08 08:49:49 PM PDT 24 Aug 08 08:56:56 PM PDT 24 3769925320 ps
T1092 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3999429506 Aug 08 08:50:17 PM PDT 24 Aug 08 09:14:00 PM PDT 24 8212117880 ps
T1093 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.1007612297 Aug 08 08:39:43 PM PDT 24 Aug 08 08:44:08 PM PDT 24 2913458331 ps
T292 /workspace/coverage/default/48.chip_sw_all_escalation_resets.2963319554 Aug 08 08:53:28 PM PDT 24 Aug 08 09:01:28 PM PDT 24 4130795600 ps
T348 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2639497085 Aug 08 08:49:49 PM PDT 24 Aug 08 08:57:39 PM PDT 24 3327180610 ps
T1094 /workspace/coverage/default/2.chip_sw_hmac_smoketest.4226977958 Aug 08 08:46:36 PM PDT 24 Aug 08 08:52:49 PM PDT 24 3542282912 ps
T1095 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2156787074 Aug 08 08:19:13 PM PDT 24 Aug 08 09:32:29 PM PDT 24 17834492544 ps
T1096 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2982813927 Aug 08 08:35:14 PM PDT 24 Aug 08 08:47:18 PM PDT 24 3942160072 ps
T293 /workspace/coverage/default/75.chip_sw_all_escalation_resets.508918 Aug 08 08:55:28 PM PDT 24 Aug 08 09:04:43 PM PDT 24 4384661188 ps
T59 /workspace/coverage/default/1.chip_jtag_csr_rw.675442415 Aug 08 08:24:15 PM PDT 24 Aug 08 08:45:37 PM PDT 24 12609537852 ps
T1097 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3373739699 Aug 08 08:31:59 PM PDT 24 Aug 08 08:37:16 PM PDT 24 2873461732 ps
T1098 /workspace/coverage/default/59.chip_sw_all_escalation_resets.3304048892 Aug 08 08:54:11 PM PDT 24 Aug 08 09:02:16 PM PDT 24 4863911080 ps
T1099 /workspace/coverage/default/0.chip_sw_aon_timer_irq.3845261504 Aug 08 08:16:39 PM PDT 24 Aug 08 08:24:06 PM PDT 24 4386220636 ps
T1100 /workspace/coverage/default/0.chip_tap_straps_dev.2369834311 Aug 08 08:20:00 PM PDT 24 Aug 08 08:37:37 PM PDT 24 12257812847 ps
T1101 /workspace/coverage/default/1.chip_sw_edn_sw_mode.4259044837 Aug 08 08:28:32 PM PDT 24 Aug 08 09:18:14 PM PDT 24 11225521840 ps
T725 /workspace/coverage/default/95.chip_sw_all_escalation_resets.1237878098 Aug 08 08:59:17 PM PDT 24 Aug 08 09:08:53 PM PDT 24 6086146138 ps
T279 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.391770855 Aug 08 08:24:51 PM PDT 24 Aug 08 10:05:48 PM PDT 24 47329416260 ps
T1102 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1681139540 Aug 08 08:50:14 PM PDT 24 Aug 08 09:08:14 PM PDT 24 9627519382 ps
T1103 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.4252642304 Aug 08 08:46:45 PM PDT 24 Aug 08 09:02:10 PM PDT 24 9086786386 ps
T703 /workspace/coverage/default/73.chip_sw_all_escalation_resets.2869063144 Aug 08 08:55:22 PM PDT 24 Aug 08 09:04:43 PM PDT 24 5091894104 ps
T1104 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3282755281 Aug 08 08:33:42 PM PDT 24 Aug 08 08:38:18 PM PDT 24 2857076188 ps
T1105 /workspace/coverage/default/0.chip_sw_example_flash.3127476542 Aug 08 08:14:54 PM PDT 24 Aug 08 08:18:50 PM PDT 24 3079462216 ps
T1106 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2841770750 Aug 08 08:48:33 PM PDT 24 Aug 08 09:31:40 PM PDT 24 12919137900 ps
T203 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1800347619 Aug 08 08:16:07 PM PDT 24 Aug 08 08:23:50 PM PDT 24 4033428832 ps
T1107 /workspace/coverage/default/0.chip_sw_power_sleep_load.31301605 Aug 08 08:19:01 PM PDT 24 Aug 08 08:31:25 PM PDT 24 11403249234 ps
T1108 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.376038329 Aug 08 08:20:08 PM PDT 24 Aug 08 08:41:17 PM PDT 24 7186029760 ps
T1109 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.623557081 Aug 08 08:31:34 PM PDT 24 Aug 08 08:39:32 PM PDT 24 6731397010 ps
T1110 /workspace/coverage/default/1.chip_sw_example_rom.3260558758 Aug 08 08:21:11 PM PDT 24 Aug 08 08:23:17 PM PDT 24 1995291096 ps
T1111 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.522179904 Aug 08 08:48:44 PM PDT 24 Aug 08 09:02:06 PM PDT 24 10440892442 ps
T1112 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3620644770 Aug 08 08:36:32 PM PDT 24 Aug 08 08:54:54 PM PDT 24 5691764646 ps
T1113 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2273813253 Aug 08 08:36:47 PM PDT 24 Aug 08 08:47:09 PM PDT 24 6050914164 ps
T364 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.68868669 Aug 08 08:29:01 PM PDT 24 Aug 08 10:23:36 PM PDT 24 24248384460 ps
T57 /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2345168534 Aug 08 08:24:44 PM PDT 24 Aug 08 08:29:19 PM PDT 24 3620318641 ps
T1114 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1978323540 Aug 08 08:18:13 PM PDT 24 Aug 08 10:15:53 PM PDT 24 42167061390 ps
T1115 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1190429659 Aug 08 08:25:49 PM PDT 24 Aug 08 08:35:21 PM PDT 24 8301997544 ps
T205 /workspace/coverage/default/0.chip_jtag_mem_access.906753205 Aug 08 08:10:33 PM PDT 24 Aug 08 08:33:36 PM PDT 24 13362364110 ps
T67 /workspace/coverage/default/2.chip_sw_alert_test.330498597 Aug 08 08:39:52 PM PDT 24 Aug 08 08:43:54 PM PDT 24 3609938630 ps
T294 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1390852149 Aug 08 08:53:27 PM PDT 24 Aug 08 09:00:14 PM PDT 24 3248817800 ps
T1116 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.765332552 Aug 08 08:50:45 PM PDT 24 Aug 08 08:58:06 PM PDT 24 6039166202 ps
T241 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.334116578 Aug 08 08:37:50 PM PDT 24 Aug 08 08:47:04 PM PDT 24 5234364440 ps
T513 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.4006210733 Aug 08 08:40:43 PM PDT 24 Aug 08 08:49:34 PM PDT 24 5278091955 ps
T1117 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3472520611 Aug 08 08:42:26 PM PDT 24 Aug 08 09:09:18 PM PDT 24 6721194448 ps
T687 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2105629130 Aug 08 08:53:16 PM PDT 24 Aug 08 08:59:49 PM PDT 24 3956734264 ps
T1118 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3713969247 Aug 08 08:29:59 PM PDT 24 Aug 08 09:06:53 PM PDT 24 9489007990 ps
T1119 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2410762774 Aug 08 08:40:35 PM PDT 24 Aug 08 08:46:41 PM PDT 24 3541905760 ps
T277 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.791253037 Aug 08 08:38:18 PM PDT 24 Aug 08 10:03:07 PM PDT 24 51324668312 ps
T349 /workspace/coverage/default/53.chip_sw_all_escalation_resets.1160060458 Aug 08 08:54:40 PM PDT 24 Aug 08 09:02:47 PM PDT 24 4719417084 ps
T1120 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2237859482 Aug 08 08:21:02 PM PDT 24 Aug 08 08:26:25 PM PDT 24 5650326860 ps
T311 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2148883535 Aug 08 08:25:00 PM PDT 24 Aug 08 08:53:17 PM PDT 24 15101806760 ps
T1121 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2697140981 Aug 08 08:25:23 PM PDT 24 Aug 08 08:32:01 PM PDT 24 5937124160 ps
T634 /workspace/coverage/default/20.chip_sw_all_escalation_resets.3077214113 Aug 08 08:52:43 PM PDT 24 Aug 08 09:01:05 PM PDT 24 5341759992 ps
T1122 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1252122954 Aug 08 08:35:45 PM PDT 24 Aug 08 08:40:33 PM PDT 24 3672944800 ps
T1123 /workspace/coverage/default/1.rom_e2e_shutdown_output.1374996385 Aug 08 08:36:48 PM PDT 24 Aug 08 09:39:27 PM PDT 24 27493540159 ps
T1124 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1332725706 Aug 08 08:16:07 PM PDT 24 Aug 08 08:25:51 PM PDT 24 7110343170 ps
T1125 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.941391246 Aug 08 08:48:42 PM PDT 24 Aug 08 09:56:08 PM PDT 24 17221194600 ps
T1126 /workspace/coverage/default/25.chip_sw_all_escalation_resets.1689415394 Aug 08 08:52:24 PM PDT 24 Aug 08 09:02:22 PM PDT 24 5211634280 ps
T1127 /workspace/coverage/default/1.chip_tap_straps_rma.2150458608 Aug 08 08:31:15 PM PDT 24 Aug 08 08:41:19 PM PDT 24 5986118772 ps
T1128 /workspace/coverage/default/0.chip_sw_aes_entropy.1294818645 Aug 08 08:17:13 PM PDT 24 Aug 08 08:22:24 PM PDT 24 2661966520 ps
T1129 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.104153607 Aug 08 08:42:37 PM PDT 24 Aug 08 08:45:58 PM PDT 24 2765235383 ps
T1130 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.241885720 Aug 08 08:18:30 PM PDT 24 Aug 08 08:30:54 PM PDT 24 4980021212 ps
T1131 /workspace/coverage/default/1.chip_sw_example_concurrency.490348698 Aug 08 08:22:18 PM PDT 24 Aug 08 08:26:04 PM PDT 24 2183475534 ps
T727 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.844158137 Aug 08 08:59:26 PM PDT 24 Aug 08 09:05:01 PM PDT 24 3757234696 ps
T1132 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3227988014 Aug 08 08:25:24 PM PDT 24 Aug 08 08:31:51 PM PDT 24 8998332517 ps
T167 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.4180706968 Aug 08 08:42:25 PM PDT 24 Aug 08 08:53:12 PM PDT 24 5813380986 ps
T1133 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1386694262 Aug 08 08:52:45 PM PDT 24 Aug 08 09:00:15 PM PDT 24 4598422552 ps
T633 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1289497559 Aug 08 08:36:50 PM PDT 24 Aug 08 08:38:33 PM PDT 24 2275705368 ps
T1134 /workspace/coverage/default/1.chip_tap_straps_prod.1507393934 Aug 08 08:32:04 PM PDT 24 Aug 08 09:00:03 PM PDT 24 14448127518 ps
T1135 /workspace/coverage/default/2.chip_sw_hmac_enc.127468862 Aug 08 08:40:28 PM PDT 24 Aug 08 08:45:27 PM PDT 24 3369229564 ps
T1136 /workspace/coverage/default/1.rom_e2e_static_critical.567187279 Aug 08 08:38:29 PM PDT 24 Aug 08 09:54:05 PM PDT 24 17447493882 ps
T755 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1851259411 Aug 08 08:53:40 PM PDT 24 Aug 08 09:01:21 PM PDT 24 4061568590 ps
T1137 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1465952168 Aug 08 08:27:19 PM PDT 24 Aug 08 08:37:22 PM PDT 24 4702147911 ps
T1138 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3892020709 Aug 08 08:25:51 PM PDT 24 Aug 08 08:31:45 PM PDT 24 7037411048 ps
T1139 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.763827112 Aug 08 08:40:10 PM PDT 24 Aug 08 09:11:43 PM PDT 24 24589671856 ps
T365 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.643753307 Aug 08 08:27:06 PM PDT 24 Aug 08 10:09:24 PM PDT 24 24467619596 ps
T1140 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2479198086 Aug 08 08:18:50 PM PDT 24 Aug 08 08:28:01 PM PDT 24 3898557780 ps
T1141 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.966203144 Aug 08 08:38:05 PM PDT 24 Aug 08 09:41:10 PM PDT 24 15271167108 ps
T1142 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2517599404 Aug 08 08:39:23 PM PDT 24 Aug 08 08:53:47 PM PDT 24 5326318755 ps
T1143 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1152595887 Aug 08 08:34:27 PM PDT 24 Aug 08 08:39:16 PM PDT 24 3556017404 ps
T1144 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3375372665 Aug 08 08:18:52 PM PDT 24 Aug 08 08:27:45 PM PDT 24 5926627010 ps
T1145 /workspace/coverage/default/0.rom_e2e_self_hash.1025059976 Aug 08 08:26:38 PM PDT 24 Aug 08 10:27:59 PM PDT 24 26744477960 ps
T242 /workspace/coverage/default/56.chip_sw_all_escalation_resets.4176007080 Aug 08 08:54:56 PM PDT 24 Aug 08 09:03:09 PM PDT 24 4327986460 ps
T689 /workspace/coverage/default/77.chip_sw_all_escalation_resets.623743273 Aug 08 08:57:09 PM PDT 24 Aug 08 09:07:51 PM PDT 24 5637539920 ps
T1146 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1028432829 Aug 08 08:32:07 PM PDT 24 Aug 08 08:40:18 PM PDT 24 5445527870 ps
T1147 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1207107631 Aug 08 08:27:48 PM PDT 24 Aug 08 08:30:59 PM PDT 24 3187160412 ps
T1148 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.765860071 Aug 08 08:37:38 PM PDT 24 Aug 08 08:54:44 PM PDT 24 10400446400 ps
T350 /workspace/coverage/default/86.chip_sw_all_escalation_resets.329813370 Aug 08 08:57:33 PM PDT 24 Aug 08 09:05:27 PM PDT 24 5299924958 ps
T1149 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2983002907 Aug 08 08:16:32 PM PDT 24 Aug 08 08:22:08 PM PDT 24 3687405000 ps
T1150 /workspace/coverage/default/1.chip_sw_otbn_smoketest.883335621 Aug 08 08:34:09 PM PDT 24 Aug 08 09:02:25 PM PDT 24 7443217104 ps
T1151 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2230706026 Aug 08 08:15:53 PM PDT 24 Aug 08 08:18:04 PM PDT 24 3202570573 ps
T1152 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2721845373 Aug 08 08:17:36 PM PDT 24 Aug 08 08:26:34 PM PDT 24 4468193548 ps
T656 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2504905542 Aug 08 08:27:03 PM PDT 24 Aug 08 08:41:53 PM PDT 24 5313055570 ps
T1153 /workspace/coverage/default/2.rom_e2e_smoke.2706925055 Aug 08 08:53:10 PM PDT 24 Aug 08 09:49:09 PM PDT 24 15134786424 ps
T1154 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3272859153 Aug 08 08:42:19 PM PDT 24 Aug 08 08:47:56 PM PDT 24 3654675140 ps
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