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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.28 95.50 94.47 95.47 95.36 97.35 99.52


Total test records in report: 2940
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T2762 /workspace/coverage/cover_reg_top/8.xbar_same_source.2121235332 Aug 08 07:51:00 PM PDT 24 Aug 08 07:51:26 PM PDT 24 333304899 ps
T2763 /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.1945282110 Aug 08 07:58:40 PM PDT 24 Aug 08 07:59:43 PM PDT 24 1405040728 ps
T2764 /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.2273195473 Aug 08 08:03:14 PM PDT 24 Aug 08 08:04:08 PM PDT 24 1325558092 ps
T2765 /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.910624039 Aug 08 08:03:41 PM PDT 24 Aug 08 08:04:53 PM PDT 24 7114124441 ps
T2766 /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.2568267870 Aug 08 08:05:37 PM PDT 24 Aug 08 08:06:27 PM PDT 24 2914122492 ps
T2767 /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.203758786 Aug 08 07:53:01 PM PDT 24 Aug 08 07:54:23 PM PDT 24 4771872698 ps
T2768 /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.2482417083 Aug 08 08:03:09 PM PDT 24 Aug 08 08:03:54 PM PDT 24 537812028 ps
T2769 /workspace/coverage/cover_reg_top/26.xbar_access_same_device.2590612468 Aug 08 07:55:09 PM PDT 24 Aug 08 07:55:27 PM PDT 24 158072973 ps
T2770 /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.1302013685 Aug 08 08:02:12 PM PDT 24 Aug 08 08:16:16 PM PDT 24 80420979204 ps
T2771 /workspace/coverage/cover_reg_top/7.xbar_error_random.3751563443 Aug 08 07:50:47 PM PDT 24 Aug 08 07:52:00 PM PDT 24 2497892960 ps
T2772 /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.3355842156 Aug 08 07:54:56 PM PDT 24 Aug 08 07:55:07 PM PDT 24 116176438 ps
T2773 /workspace/coverage/cover_reg_top/72.xbar_same_source.1199592540 Aug 08 08:03:59 PM PDT 24 Aug 08 08:04:11 PM PDT 24 111670142 ps
T2774 /workspace/coverage/cover_reg_top/39.xbar_smoke.147989195 Aug 08 07:57:50 PM PDT 24 Aug 08 07:57:59 PM PDT 24 218197197 ps
T2775 /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.2998827682 Aug 08 07:50:27 PM PDT 24 Aug 08 07:51:04 PM PDT 24 396737444 ps
T2776 /workspace/coverage/cover_reg_top/39.xbar_error_random.3415429544 Aug 08 07:58:04 PM PDT 24 Aug 08 07:58:39 PM PDT 24 1216154338 ps
T2777 /workspace/coverage/cover_reg_top/36.xbar_access_same_device.1124580089 Aug 08 07:57:18 PM PDT 24 Aug 08 07:58:25 PM PDT 24 1757036181 ps
T2778 /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.4024861323 Aug 08 08:00:17 PM PDT 24 Aug 08 08:06:21 PM PDT 24 5822774619 ps
T2779 /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.4127684829 Aug 08 08:07:55 PM PDT 24 Aug 08 08:08:37 PM PDT 24 1168945407 ps
T2780 /workspace/coverage/cover_reg_top/98.xbar_same_source.666845424 Aug 08 08:08:07 PM PDT 24 Aug 08 08:09:07 PM PDT 24 2037552252 ps
T2781 /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.3379391685 Aug 08 08:05:42 PM PDT 24 Aug 08 08:10:46 PM PDT 24 29037379726 ps
T2782 /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.708835234 Aug 08 08:07:06 PM PDT 24 Aug 08 08:08:43 PM PDT 24 268919355 ps
T2783 /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.2257738364 Aug 08 08:00:18 PM PDT 24 Aug 08 08:01:29 PM PDT 24 6731125043 ps
T2784 /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.2545743409 Aug 08 07:50:35 PM PDT 24 Aug 08 07:51:06 PM PDT 24 301301848 ps
T2785 /workspace/coverage/cover_reg_top/48.xbar_access_same_device.2945449224 Aug 08 07:59:59 PM PDT 24 Aug 08 08:01:26 PM PDT 24 2213646077 ps
T2786 /workspace/coverage/cover_reg_top/66.xbar_error_random.503312960 Aug 08 08:02:48 PM PDT 24 Aug 08 08:03:16 PM PDT 24 905207161 ps
T2787 /workspace/coverage/cover_reg_top/21.xbar_random.1152312098 Aug 08 07:53:58 PM PDT 24 Aug 08 07:54:20 PM PDT 24 246181683 ps
T2788 /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.2189071652 Aug 08 08:05:31 PM PDT 24 Aug 08 08:12:03 PM PDT 24 6141374736 ps
T2789 /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.4242757204 Aug 08 07:50:11 PM PDT 24 Aug 08 07:51:04 PM PDT 24 574907392 ps
T2790 /workspace/coverage/cover_reg_top/41.xbar_access_same_device.4262576282 Aug 08 07:58:17 PM PDT 24 Aug 08 07:59:27 PM PDT 24 1122250924 ps
T2791 /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1792489972 Aug 08 08:03:59 PM PDT 24 Aug 08 08:04:57 PM PDT 24 3348740725 ps
T2792 /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.833865702 Aug 08 07:56:35 PM PDT 24 Aug 08 08:15:09 PM PDT 24 104009796215 ps
T2793 /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.1069729360 Aug 08 07:53:50 PM PDT 24 Aug 08 07:54:10 PM PDT 24 168100364 ps
T2794 /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.2973030851 Aug 08 08:06:56 PM PDT 24 Aug 08 08:41:38 PM PDT 24 118064696514 ps
T2795 /workspace/coverage/cover_reg_top/9.xbar_access_same_device.906455868 Aug 08 07:51:18 PM PDT 24 Aug 08 07:51:50 PM PDT 24 709762545 ps
T2796 /workspace/coverage/cover_reg_top/76.xbar_random.4267922365 Aug 08 08:04:28 PM PDT 24 Aug 08 08:04:54 PM PDT 24 247490161 ps
T2797 /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.923044331 Aug 08 07:50:11 PM PDT 24 Aug 08 07:50:57 PM PDT 24 2637658397 ps
T2798 /workspace/coverage/cover_reg_top/18.xbar_access_same_device.1931286075 Aug 08 07:53:21 PM PDT 24 Aug 08 07:54:33 PM PDT 24 1049747359 ps
T2799 /workspace/coverage/cover_reg_top/73.xbar_random.3335594987 Aug 08 08:04:00 PM PDT 24 Aug 08 08:04:53 PM PDT 24 1536071925 ps
T2800 /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.2064218383 Aug 08 08:05:57 PM PDT 24 Aug 08 08:06:32 PM PDT 24 940845141 ps
T2801 /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.3459046775 Aug 08 07:57:16 PM PDT 24 Aug 08 08:01:09 PM PDT 24 1864100019 ps
T2802 /workspace/coverage/cover_reg_top/48.xbar_error_random.861371780 Aug 08 08:00:00 PM PDT 24 Aug 08 08:01:02 PM PDT 24 1922954670 ps
T2803 /workspace/coverage/cover_reg_top/7.xbar_access_same_device.4115241098 Aug 08 07:50:46 PM PDT 24 Aug 08 07:52:06 PM PDT 24 1768127201 ps
T2804 /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.2151334488 Aug 08 07:59:57 PM PDT 24 Aug 08 08:00:07 PM PDT 24 65747399 ps
T2805 /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.1797157456 Aug 08 08:06:45 PM PDT 24 Aug 08 08:06:51 PM PDT 24 42493992 ps
T2806 /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.1399354090 Aug 08 07:54:53 PM PDT 24 Aug 08 07:55:09 PM PDT 24 289613197 ps
T2807 /workspace/coverage/cover_reg_top/45.xbar_stress_all.2433147897 Aug 08 07:58:55 PM PDT 24 Aug 08 08:00:08 PM PDT 24 803671530 ps
T2808 /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.4275269537 Aug 08 08:01:17 PM PDT 24 Aug 08 08:02:34 PM PDT 24 7665419850 ps
T2809 /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.1985117801 Aug 08 08:02:48 PM PDT 24 Aug 08 08:03:30 PM PDT 24 1013882020 ps
T2810 /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.3347778714 Aug 08 08:04:15 PM PDT 24 Aug 08 08:08:59 PM PDT 24 16102232202 ps
T2811 /workspace/coverage/cover_reg_top/19.chip_tl_errors.696460301 Aug 08 07:53:31 PM PDT 24 Aug 08 07:57:04 PM PDT 24 3571177948 ps
T2812 /workspace/coverage/cover_reg_top/83.xbar_random.4077648867 Aug 08 08:05:38 PM PDT 24 Aug 08 08:07:06 PM PDT 24 2389043516 ps
T2813 /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.542033612 Aug 08 07:51:17 PM PDT 24 Aug 08 08:09:52 PM PDT 24 64193001560 ps
T2814 /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.3480668810 Aug 08 08:07:39 PM PDT 24 Aug 08 08:08:55 PM PDT 24 4466150816 ps
T2815 /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1733924334 Aug 08 08:05:38 PM PDT 24 Aug 08 08:05:44 PM PDT 24 56330790 ps
T2816 /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.4077388426 Aug 08 07:50:43 PM PDT 24 Aug 08 07:56:18 PM PDT 24 7120339112 ps
T2817 /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.32920711 Aug 08 07:58:17 PM PDT 24 Aug 08 07:59:10 PM PDT 24 104759464 ps
T2818 /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2902716109 Aug 08 07:51:50 PM PDT 24 Aug 08 07:52:33 PM PDT 24 1046185162 ps
T2819 /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2315998083 Aug 08 07:51:54 PM PDT 24 Aug 08 07:59:08 PM PDT 24 26872727768 ps
T2820 /workspace/coverage/cover_reg_top/34.xbar_smoke.1103041380 Aug 08 07:56:34 PM PDT 24 Aug 08 07:56:44 PM PDT 24 236448001 ps
T2821 /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1350985920 Aug 08 07:53:10 PM PDT 24 Aug 08 08:02:22 PM PDT 24 30852143878 ps
T2822 /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.2004681490 Aug 08 08:03:12 PM PDT 24 Aug 08 08:37:21 PM PDT 24 115843245353 ps
T2823 /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.1753452186 Aug 08 07:54:03 PM PDT 24 Aug 08 07:56:35 PM PDT 24 4036423210 ps
T2824 /workspace/coverage/cover_reg_top/74.xbar_smoke.3311146207 Aug 08 08:04:00 PM PDT 24 Aug 08 08:04:06 PM PDT 24 51276171 ps
T2825 /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1469440076 Aug 08 08:04:23 PM PDT 24 Aug 08 08:48:13 PM PDT 24 152786439767 ps
T2826 /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.988482072 Aug 08 07:53:47 PM PDT 24 Aug 08 07:55:21 PM PDT 24 5403372254 ps
T2827 /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3746419765 Aug 08 08:03:10 PM PDT 24 Aug 08 08:04:26 PM PDT 24 89274387 ps
T2828 /workspace/coverage/cover_reg_top/88.xbar_smoke.3937935097 Aug 08 08:06:21 PM PDT 24 Aug 08 08:06:31 PM PDT 24 248805625 ps
T2829 /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.2984986240 Aug 08 07:58:03 PM PDT 24 Aug 08 07:58:17 PM PDT 24 305833460 ps
T2830 /workspace/coverage/cover_reg_top/31.xbar_error_random.2270234836 Aug 08 07:56:16 PM PDT 24 Aug 08 07:57:22 PM PDT 24 1718991806 ps
T2831 /workspace/coverage/cover_reg_top/55.xbar_smoke.1236561976 Aug 08 08:00:40 PM PDT 24 Aug 08 08:00:49 PM PDT 24 214720206 ps
T2832 /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.1246711848 Aug 08 08:04:43 PM PDT 24 Aug 08 08:05:12 PM PDT 24 363713788 ps
T2833 /workspace/coverage/cover_reg_top/15.xbar_same_source.1280818693 Aug 08 07:52:38 PM PDT 24 Aug 08 07:53:21 PM PDT 24 1397571440 ps
T2834 /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1092801157 Aug 08 07:49:59 PM PDT 24 Aug 08 07:58:55 PM PDT 24 4981425331 ps
T2835 /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.3785571022 Aug 08 08:03:34 PM PDT 24 Aug 08 08:19:45 PM PDT 24 86416510416 ps
T2836 /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.2178831996 Aug 08 08:04:01 PM PDT 24 Aug 08 08:06:46 PM PDT 24 9544624568 ps
T2837 /workspace/coverage/cover_reg_top/57.xbar_same_source.1032708421 Aug 08 08:01:18 PM PDT 24 Aug 08 08:02:18 PM PDT 24 2060395903 ps
T2838 /workspace/coverage/cover_reg_top/9.xbar_same_source.824547454 Aug 08 07:51:21 PM PDT 24 Aug 08 07:52:04 PM PDT 24 1446497705 ps
T2839 /workspace/coverage/cover_reg_top/94.xbar_random.776054002 Aug 08 08:07:18 PM PDT 24 Aug 08 08:07:40 PM PDT 24 208722640 ps
T2840 /workspace/coverage/cover_reg_top/96.xbar_access_same_device.2836288665 Aug 08 08:07:40 PM PDT 24 Aug 08 08:08:34 PM PDT 24 694493047 ps
T2841 /workspace/coverage/cover_reg_top/71.xbar_smoke.49442424 Aug 08 08:03:39 PM PDT 24 Aug 08 08:03:46 PM PDT 24 53015455 ps
T2842 /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1756789150 Aug 08 07:50:32 PM PDT 24 Aug 08 07:51:03 PM PDT 24 277063959 ps
T2843 /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.902196725 Aug 08 07:50:27 PM PDT 24 Aug 08 08:30:15 PM PDT 24 131738491913 ps
T2844 /workspace/coverage/cover_reg_top/70.xbar_stress_all.277148684 Aug 08 08:03:21 PM PDT 24 Aug 08 08:07:48 PM PDT 24 3197653267 ps
T2845 /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.2770069884 Aug 08 08:01:48 PM PDT 24 Aug 08 08:05:01 PM PDT 24 19454556397 ps
T2846 /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1599513905 Aug 08 07:59:57 PM PDT 24 Aug 08 08:01:11 PM PDT 24 4127903021 ps
T2847 /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.2063107007 Aug 08 07:56:14 PM PDT 24 Aug 08 07:56:21 PM PDT 24 45088609 ps
T2848 /workspace/coverage/cover_reg_top/45.xbar_random.4159279642 Aug 08 07:58:54 PM PDT 24 Aug 08 07:59:22 PM PDT 24 853080991 ps
T2849 /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.223781684 Aug 08 07:52:15 PM PDT 24 Aug 08 07:54:06 PM PDT 24 6308739557 ps
T2850 /workspace/coverage/cover_reg_top/4.xbar_same_source.3946278680 Aug 08 07:50:23 PM PDT 24 Aug 08 07:51:12 PM PDT 24 1808601238 ps
T2851 /workspace/coverage/cover_reg_top/59.xbar_same_source.2537467483 Aug 08 08:01:47 PM PDT 24 Aug 08 08:01:55 PM PDT 24 58543890 ps
T2852 /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.145300889 Aug 08 07:49:59 PM PDT 24 Aug 08 07:51:28 PM PDT 24 5434113430 ps
T2853 /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.4173774889 Aug 08 07:51:36 PM PDT 24 Aug 08 09:09:03 PM PDT 24 28341117716 ps
T2854 /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.1955202785 Aug 08 07:56:34 PM PDT 24 Aug 08 07:57:34 PM PDT 24 3712977544 ps
T2855 /workspace/coverage/cover_reg_top/32.xbar_smoke.2835050894 Aug 08 07:56:15 PM PDT 24 Aug 08 07:56:22 PM PDT 24 44765478 ps
T2856 /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.735779986 Aug 08 08:02:28 PM PDT 24 Aug 08 08:04:00 PM PDT 24 5327863809 ps
T2857 /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.804065812 Aug 08 08:08:18 PM PDT 24 Aug 08 08:08:58 PM PDT 24 1072415815 ps
T2858 /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.1924380425 Aug 08 07:57:05 PM PDT 24 Aug 08 08:07:36 PM PDT 24 55763492430 ps
T2859 /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.40858238 Aug 08 08:00:19 PM PDT 24 Aug 08 08:06:11 PM PDT 24 20505348779 ps
T2860 /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.694132188 Aug 08 07:52:24 PM PDT 24 Aug 08 08:05:45 PM PDT 24 9728700020 ps
T2861 /workspace/coverage/cover_reg_top/71.xbar_error_random.892451334 Aug 08 08:03:42 PM PDT 24 Aug 08 08:04:07 PM PDT 24 285873069 ps
T2862 /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2138175564 Aug 08 07:50:03 PM PDT 24 Aug 08 07:50:37 PM PDT 24 417992375 ps
T2863 /workspace/coverage/cover_reg_top/86.xbar_error_random.3582526343 Aug 08 08:05:55 PM PDT 24 Aug 08 08:06:07 PM PDT 24 289781339 ps
T2864 /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3642801523 Aug 08 07:51:50 PM PDT 24 Aug 08 07:52:59 PM PDT 24 4370845995 ps
T2865 /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.3329108107 Aug 08 08:00:39 PM PDT 24 Aug 08 08:36:09 PM PDT 24 122269935503 ps
T2866 /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.2960565420 Aug 08 08:07:06 PM PDT 24 Aug 08 08:07:25 PM PDT 24 359856163 ps
T2867 /workspace/coverage/cover_reg_top/82.xbar_same_source.32138416 Aug 08 08:05:29 PM PDT 24 Aug 08 08:06:01 PM PDT 24 1120504120 ps
T2868 /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.4169527704 Aug 08 08:00:55 PM PDT 24 Aug 08 08:04:39 PM PDT 24 610112012 ps
T2869 /workspace/coverage/cover_reg_top/13.xbar_smoke.2591625849 Aug 08 07:52:05 PM PDT 24 Aug 08 07:52:11 PM PDT 24 40381630 ps
T2870 /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2297958063 Aug 08 07:55:18 PM PDT 24 Aug 08 08:33:28 PM PDT 24 139560455253 ps
T2871 /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.4153803134 Aug 08 07:58:54 PM PDT 24 Aug 08 08:12:00 PM PDT 24 72765787599 ps
T2872 /workspace/coverage/cover_reg_top/43.xbar_smoke.1319062959 Aug 08 07:58:29 PM PDT 24 Aug 08 07:58:36 PM PDT 24 50024115 ps
T2873 /workspace/coverage/cover_reg_top/62.xbar_stress_all.1467133857 Aug 08 08:02:11 PM PDT 24 Aug 08 08:06:37 PM PDT 24 2845058475 ps
T2874 /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.3044123500 Aug 08 07:57:20 PM PDT 24 Aug 08 07:58:54 PM PDT 24 1219345891 ps
T2875 /workspace/coverage/cover_reg_top/68.xbar_smoke.447359559 Aug 08 08:03:07 PM PDT 24 Aug 08 08:03:15 PM PDT 24 172561651 ps
T2876 /workspace/coverage/cover_reg_top/2.xbar_stress_all.3733743658 Aug 08 07:50:07 PM PDT 24 Aug 08 08:02:09 PM PDT 24 19008310817 ps
T2877 /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.2120052731 Aug 08 07:54:50 PM PDT 24 Aug 08 07:55:23 PM PDT 24 307021506 ps
T2878 /workspace/coverage/cover_reg_top/23.xbar_random.2455704415 Aug 08 07:54:39 PM PDT 24 Aug 08 07:56:08 PM PDT 24 2600721443 ps
T2879 /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.2387559342 Aug 08 08:07:26 PM PDT 24 Aug 08 08:08:24 PM PDT 24 476289686 ps
T2880 /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1475188038 Aug 08 07:52:26 PM PDT 24 Aug 08 08:23:43 PM PDT 24 109872260363 ps
T2881 /workspace/coverage/cover_reg_top/67.xbar_smoke.856224391 Aug 08 08:02:53 PM PDT 24 Aug 08 08:03:01 PM PDT 24 181839069 ps
T2882 /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.1055759315 Aug 08 08:07:46 PM PDT 24 Aug 08 08:09:10 PM PDT 24 5166549135 ps
T2883 /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.1618375402 Aug 08 08:05:23 PM PDT 24 Aug 08 08:07:15 PM PDT 24 1530739205 ps
T2884 /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2194201312 Aug 08 07:52:03 PM PDT 24 Aug 08 07:55:29 PM PDT 24 2193446266 ps
T2885 /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.3881815704 Aug 08 07:50:12 PM PDT 24 Aug 08 08:00:35 PM PDT 24 60832955579 ps
T2886 /workspace/coverage/cover_reg_top/74.xbar_access_same_device.2101602552 Aug 08 08:04:13 PM PDT 24 Aug 08 08:04:47 PM PDT 24 853314788 ps
T2887 /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.3329365593 Aug 08 08:03:12 PM PDT 24 Aug 08 08:05:56 PM PDT 24 4491776200 ps
T2888 /workspace/coverage/cover_reg_top/94.xbar_smoke.1791152369 Aug 08 08:07:18 PM PDT 24 Aug 08 08:07:24 PM PDT 24 45869881 ps
T2889 /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.1524704466 Aug 08 08:02:11 PM PDT 24 Aug 08 08:02:43 PM PDT 24 853957501 ps
T2890 /workspace/coverage/cover_reg_top/9.chip_tl_errors.3422368313 Aug 08 07:51:06 PM PDT 24 Aug 08 07:55:37 PM PDT 24 4415634585 ps
T2891 /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.642614629 Aug 08 08:02:11 PM PDT 24 Aug 08 08:29:11 PM PDT 24 84632249357 ps
T2892 /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.3707000800 Aug 08 07:56:44 PM PDT 24 Aug 08 07:59:25 PM PDT 24 9186409818 ps
T2893 /workspace/coverage/cover_reg_top/8.xbar_access_same_device.2778994088 Aug 08 07:50:50 PM PDT 24 Aug 08 07:52:03 PM PDT 24 2004150980 ps
T2894 /workspace/coverage/cover_reg_top/90.xbar_access_same_device.1932182194 Aug 08 08:06:46 PM PDT 24 Aug 08 08:06:59 PM PDT 24 252599320 ps
T2895 /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.4259833131 Aug 08 08:07:26 PM PDT 24 Aug 08 08:09:27 PM PDT 24 1673878900 ps
T2896 /workspace/coverage/cover_reg_top/90.xbar_error_random.3576189592 Aug 08 08:06:50 PM PDT 24 Aug 08 08:08:06 PM PDT 24 2206220589 ps
T2897 /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.973684788 Aug 08 08:02:39 PM PDT 24 Aug 08 08:03:04 PM PDT 24 239720675 ps
T2898 /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.2686140414 Aug 08 08:05:05 PM PDT 24 Aug 08 08:23:47 PM PDT 24 104432992924 ps
T2899 /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.42605068 Aug 08 07:50:27 PM PDT 24 Aug 08 08:20:14 PM PDT 24 104138615142 ps
T2900 /workspace/coverage/cover_reg_top/20.xbar_smoke.2328167851 Aug 08 07:53:47 PM PDT 24 Aug 08 07:53:55 PM PDT 24 49619754 ps
T2901 /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.1555303562 Aug 08 08:07:56 PM PDT 24 Aug 08 08:21:35 PM PDT 24 45297826838 ps
T2902 /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2210140771 Aug 08 07:49:57 PM PDT 24 Aug 08 08:21:44 PM PDT 24 114020850415 ps
T2903 /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.1444794527 Aug 08 07:57:29 PM PDT 24 Aug 08 08:03:42 PM PDT 24 23065737413 ps
T2904 /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.3912384347 Aug 08 08:06:56 PM PDT 24 Aug 08 08:16:26 PM PDT 24 6095367948 ps
T2905 /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.179411518 Aug 08 07:53:47 PM PDT 24 Aug 08 07:56:26 PM PDT 24 1249225773 ps
T2906 /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.2138309022 Aug 08 07:50:31 PM PDT 24 Aug 08 08:08:05 PM PDT 24 9664564389 ps
T2907 /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.2439922927 Aug 08 08:03:09 PM PDT 24 Aug 08 08:04:29 PM PDT 24 1063655731 ps
T2908 /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.150866138 Aug 08 08:02:22 PM PDT 24 Aug 08 08:03:00 PM PDT 24 837560990 ps
T2909 /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.1674411841 Aug 08 08:04:27 PM PDT 24 Aug 08 08:04:50 PM PDT 24 179104276 ps
T2910 /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.2080608720 Aug 08 08:05:20 PM PDT 24 Aug 08 08:29:54 PM PDT 24 80287245506 ps
T2911 /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.1470517809 Aug 08 08:03:09 PM PDT 24 Aug 08 08:03:46 PM PDT 24 917619192 ps
T2912 /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.2827031215 Aug 08 08:04:42 PM PDT 24 Aug 08 08:06:52 PM PDT 24 1701697845 ps
T2913 /workspace/coverage/cover_reg_top/57.xbar_smoke.40723786 Aug 08 08:01:12 PM PDT 24 Aug 08 08:01:23 PM PDT 24 253366859 ps
T2914 /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.1379223606 Aug 08 07:50:26 PM PDT 24 Aug 08 07:50:56 PM PDT 24 770155491 ps
T2915 /workspace/coverage/cover_reg_top/26.xbar_stress_all.3936840817 Aug 08 07:55:18 PM PDT 24 Aug 08 07:58:26 PM PDT 24 2088509088 ps
T2916 /workspace/coverage/cover_reg_top/19.xbar_smoke.1183060311 Aug 08 07:53:37 PM PDT 24 Aug 08 07:53:45 PM PDT 24 169529335 ps
T2917 /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.1305292876 Aug 08 07:53:41 PM PDT 24 Aug 08 08:03:00 PM PDT 24 4213135423 ps
T2918 /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.3410300199 Aug 08 08:02:48 PM PDT 24 Aug 08 08:03:36 PM PDT 24 500746562 ps
T2919 /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.1795624511 Aug 08 07:53:30 PM PDT 24 Aug 08 07:54:48 PM PDT 24 2276548976 ps
T642 /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3473060816 Aug 08 08:02:50 PM PDT 24 Aug 08 08:09:46 PM PDT 24 9618305436 ps
T2920 /workspace/coverage/cover_reg_top/28.chip_tl_errors.2490786943 Aug 08 07:55:36 PM PDT 24 Aug 08 07:58:59 PM PDT 24 2996321565 ps
T2921 /workspace/coverage/cover_reg_top/31.xbar_random.1931601787 Aug 08 07:56:05 PM PDT 24 Aug 08 07:56:13 PM PDT 24 135444052 ps
T2922 /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.2296856941 Aug 08 07:50:16 PM PDT 24 Aug 08 07:50:22 PM PDT 24 35072007 ps
T2923 /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.3784544545 Aug 08 07:54:58 PM PDT 24 Aug 08 08:05:41 PM PDT 24 14230035461 ps
T2924 /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.183733154 Aug 08 07:50:35 PM PDT 24 Aug 08 07:58:39 PM PDT 24 6600585478 ps
T2925 /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1619106388 Aug 08 07:50:10 PM PDT 24 Aug 08 07:56:50 PM PDT 24 11673156049 ps
T2926 /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.2939027359 Aug 08 08:08:19 PM PDT 24 Aug 08 08:08:29 PM PDT 24 78293343 ps
T2927 /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3671363508 Aug 08 07:56:35 PM PDT 24 Aug 08 07:58:53 PM PDT 24 211103238 ps
T2928 /workspace/coverage/cover_reg_top/7.xbar_smoke.109011664 Aug 08 07:50:31 PM PDT 24 Aug 08 07:50:42 PM PDT 24 244129768 ps
T2929 /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.541208374 Aug 08 08:00:39 PM PDT 24 Aug 08 08:00:46 PM PDT 24 55102865 ps
T2930 /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.2953274521 Aug 08 08:07:56 PM PDT 24 Aug 08 08:19:29 PM PDT 24 5203903802 ps
T2931 /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.2345047179 Aug 08 07:57:28 PM PDT 24 Aug 08 07:57:34 PM PDT 24 44917557 ps
T2932 /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.246968461 Aug 08 08:05:05 PM PDT 24 Aug 08 08:06:23 PM PDT 24 7525765976 ps
T2933 /workspace/coverage/cover_reg_top/20.xbar_access_same_device.3140632436 Aug 08 07:53:50 PM PDT 24 Aug 08 07:54:56 PM PDT 24 1546310142 ps
T2934 /workspace/coverage/cover_reg_top/11.xbar_same_source.2487825860 Aug 08 07:51:45 PM PDT 24 Aug 08 07:52:31 PM PDT 24 1739859453 ps
T2935 /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.720122565 Aug 08 08:02:23 PM PDT 24 Aug 08 08:22:17 PM PDT 24 67359923167 ps
T2936 /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.1805783524 Aug 08 08:07:47 PM PDT 24 Aug 08 08:09:54 PM PDT 24 2289706918 ps
T2937 /workspace/coverage/cover_reg_top/20.xbar_same_source.1252385982 Aug 08 07:53:49 PM PDT 24 Aug 08 07:54:26 PM PDT 24 1229497444 ps
T2938 /workspace/coverage/cover_reg_top/6.chip_csr_rw.3477330488 Aug 08 07:50:35 PM PDT 24 Aug 08 07:55:35 PM PDT 24 4017365400 ps
T2939 /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.2043927386 Aug 08 08:05:21 PM PDT 24 Aug 08 08:06:17 PM PDT 24 623740964 ps
T2940 /workspace/coverage/cover_reg_top/31.xbar_access_same_device.588408924 Aug 08 07:56:17 PM PDT 24 Aug 08 07:57:49 PM PDT 24 2086708694 ps
T31 /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3231691112 Aug 08 07:49:48 PM PDT 24 Aug 08 07:54:47 PM PDT 24 4393952867 ps
T32 /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1851739404 Aug 08 07:49:55 PM PDT 24 Aug 08 07:53:51 PM PDT 24 5019645988 ps
T33 /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.219820730 Aug 08 07:49:50 PM PDT 24 Aug 08 07:53:16 PM PDT 24 4376198491 ps
T190 /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1793758878 Aug 08 07:49:50 PM PDT 24 Aug 08 07:54:30 PM PDT 24 4356613992 ps
T191 /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3216452664 Aug 08 07:49:53 PM PDT 24 Aug 08 07:53:21 PM PDT 24 3958640540 ps
T192 /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3408872537 Aug 08 07:49:49 PM PDT 24 Aug 08 07:55:54 PM PDT 24 5657131496 ps
T193 /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.107155044 Aug 08 07:49:50 PM PDT 24 Aug 08 07:53:57 PM PDT 24 5050072836 ps
T196 /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.4238819953 Aug 08 07:49:53 PM PDT 24 Aug 08 07:54:14 PM PDT 24 4665639096 ps
T194 /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.4180290392 Aug 08 07:49:53 PM PDT 24 Aug 08 07:52:28 PM PDT 24 4023199880 ps
T197 /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3249991543 Aug 08 07:49:50 PM PDT 24 Aug 08 07:54:21 PM PDT 24 4341118359 ps

Test location /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2361046186
Short name T6
Test name
Test status
Simulation time 3991331900 ps
CPU time 426.54 seconds
Started Aug 08 08:57:06 PM PDT 24
Finished Aug 08 09:04:13 PM PDT 24
Peak memory 648692 kb
Host smart-ba579c9b-ab67-4f1c-81e0-f7cf0b3ad9ea
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361046186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2361046186
Directory /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/2.chip_jtag_csr_rw.2444428481
Short name T55
Test name
Test status
Simulation time 20929894195 ps
CPU time 2160.7 seconds
Started Aug 08 08:35:46 PM PDT 24
Finished Aug 08 09:11:47 PM PDT 24
Peak memory 608080 kb
Host smart-03b74508-6e5c-4b5b-bfef-507833b67983
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444428481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c
hip_jtag_csr_rw.2444428481
Directory /workspace/2.chip_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.1934357731
Short name T429
Test name
Test status
Simulation time 19034187915 ps
CPU time 1208.1 seconds
Started Aug 08 08:06:43 PM PDT 24
Finished Aug 08 08:26:51 PM PDT 24
Peak memory 575952 kb
Host smart-ee06f294-c815-4919-b1f2-a4e28532d873
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934357731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all
_with_rand_reset.1934357731
Directory /workspace/89.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.chip_plic_all_irqs_0.2769122595
Short name T301
Test name
Test status
Simulation time 6561315526 ps
CPU time 1327.24 seconds
Started Aug 08 08:29:55 PM PDT 24
Finished Aug 08 08:52:02 PM PDT 24
Peak memory 610132 kb
Host smart-234cbfc7-88c8-4075-a038-4ec260379d19
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769122595 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_plic_all_irqs_0.2769122595
Directory /workspace/1.chip_plic_all_irqs_0/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.2701780174
Short name T81
Test name
Test status
Simulation time 7291636092 ps
CPU time 284.09 seconds
Started Aug 08 07:51:23 PM PDT 24
Finished Aug 08 07:56:08 PM PDT 24
Peak memory 576808 kb
Host smart-2ac58d1d-19d9-4c1f-b843-8a333622835d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701780174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all
_with_reset_error.2701780174
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3231691112
Short name T31
Test name
Test status
Simulation time 4393952867 ps
CPU time 298.84 seconds
Started Aug 08 07:49:48 PM PDT 24
Finished Aug 08 07:54:47 PM PDT 24
Peak memory 649288 kb
Host smart-6080ac2a-55ac-4d94-88cb-6e90f763fde4
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231691112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 9.chip_padctrl_attributes.3231691112
Directory /workspace/9.chip_padctrl_attributes/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.792403767
Short name T796
Test name
Test status
Simulation time 152883260707 ps
CPU time 2814.16 seconds
Started Aug 08 08:07:27 PM PDT 24
Finished Aug 08 08:54:22 PM PDT 24
Peak memory 575964 kb
Host smart-27d09f9a-321f-4de0-83d0-f184c6f22581
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792403767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_d
evice_slow_rsp.792403767
Directory /workspace/95.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2701610941
Short name T173
Test name
Test status
Simulation time 15453029882 ps
CPU time 3408.7 seconds
Started Aug 08 08:40:48 PM PDT 24
Finished Aug 08 09:37:37 PM PDT 24
Peak memory 610924 kb
Host smart-803b122e-f8c7-4da5-9115-5b01fc7d040f
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27016
10941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.2701610941
Directory /workspace/2.chip_sw_keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2730338489
Short name T154
Test name
Test status
Simulation time 5021724346 ps
CPU time 610.93 seconds
Started Aug 08 08:18:38 PM PDT 24
Finished Aug 08 08:28:49 PM PDT 24
Peak memory 611196 kb
Host smart-90e9578f-fc86-40ce-8f78-6a22df8ff615
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2730338489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.2730338489
Directory /workspace/0.chip_sw_otp_ctrl_escalation/latest

Test location /workspace/coverage/cover_reg_top/12.chip_csr_rw.2243926434
Short name T148
Test name
Test status
Simulation time 5443566720 ps
CPU time 521.33 seconds
Started Aug 08 07:52:07 PM PDT 24
Finished Aug 08 08:00:49 PM PDT 24
Peak memory 598756 kb
Host smart-92e61635-3a9b-42ca-b5ef-d9ffaf8dc031
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243926434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.2243926434
Directory /workspace/12.chip_csr_rw/latest

Test location /workspace/coverage/default/1.rom_e2e_self_hash.4042426587
Short name T3
Test name
Test status
Simulation time 26245951278 ps
CPU time 5531.48 seconds
Started Aug 08 08:37:53 PM PDT 24
Finished Aug 08 10:10:05 PM PDT 24
Peak memory 609904 kb
Host smart-0f4f1016-450d-4056-9b6d-b91e454f1a02
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r
ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042426587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.4042426587
Directory /workspace/1.rom_e2e_self_hash/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.3837260629
Short name T777
Test name
Test status
Simulation time 108544163765 ps
CPU time 1818.64 seconds
Started Aug 08 08:00:46 PM PDT 24
Finished Aug 08 08:31:05 PM PDT 24
Peak memory 575916 kb
Host smart-f27c3d9a-e49f-440a-84c8-04e9cd9b6982
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837260629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_
device_slow_rsp.3837260629
Directory /workspace/55.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/2.chip_sw_power_virus.838887118
Short name T15
Test name
Test status
Simulation time 5601896310 ps
CPU time 1356.11 seconds
Started Aug 08 08:52:40 PM PDT 24
Finished Aug 08 09:15:17 PM PDT 24
Peak memory 624960 kb
Host smart-6fd78f8c-94f8-4285-ae9c-4c786a0f4e71
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_
power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes
t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=838887118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.838887118
Directory /workspace/2.chip_sw_power_virus/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.2065002332
Short name T773
Test name
Test status
Simulation time 60001358311 ps
CPU time 1045.58 seconds
Started Aug 08 08:02:34 PM PDT 24
Finished Aug 08 08:20:00 PM PDT 24
Peak memory 576056 kb
Host smart-6e012f9a-9ce3-4ece-bc6b-5b8dbfdae766
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065002332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_
device_slow_rsp.2065002332
Directory /workspace/63.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1692735963
Short name T164
Test name
Test status
Simulation time 11190688940 ps
CPU time 901.52 seconds
Started Aug 08 08:36:47 PM PDT 24
Finished Aug 08 08:51:50 PM PDT 24
Peak memory 620328 kb
Host smart-2f3e92ac-91ee-439a-9cdf-20492b2bb9c0
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa
lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692735963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.1692735963
Directory /workspace/2.chip_sw_lc_walkthrough_prodend/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.662662876
Short name T1731
Test name
Test status
Simulation time 81517246509 ps
CPU time 1434.61 seconds
Started Aug 08 08:03:40 PM PDT 24
Finished Aug 08 08:27:35 PM PDT 24
Peak memory 576012 kb
Host smart-d715ebdb-e742-4fa8-a0d7-079fd82bff2a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662662876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_d
evice_slow_rsp.662662876
Directory /workspace/71.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2396898157
Short name T11
Test name
Test status
Simulation time 3360354424 ps
CPU time 396.74 seconds
Started Aug 08 08:35:05 PM PDT 24
Finished Aug 08 08:41:42 PM PDT 24
Peak memory 610452 kb
Host smart-a56ac8df-2057-479b-be50-c32b1f6d025b
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396
898157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.2396898157
Directory /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest

Test location /workspace/coverage/default/2.chip_plic_all_irqs_20.2375453425
Short name T316
Test name
Test status
Simulation time 5230852380 ps
CPU time 720.4 seconds
Started Aug 08 08:42:16 PM PDT 24
Finished Aug 08 08:54:16 PM PDT 24
Peak memory 610096 kb
Host smart-5c0b886c-52ae-4756-84d1-6b5649d1351b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375453425 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.chip_plic_all_irqs_20.2375453425
Directory /workspace/2.chip_plic_all_irqs_20/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.391955705
Short name T264
Test name
Test status
Simulation time 3103880452 ps
CPU time 352.36 seconds
Started Aug 08 08:19:53 PM PDT 24
Finished Aug 08 08:25:46 PM PDT 24
Peak memory 609860 kb
Host smart-e6f31f14-6ede-4f22-acb7-1e8829faf8a7
User root
Command /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=391955705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.391955705
Directory /workspace/0.chip_sw_rv_core_ibex_address_translation/latest

Test location /workspace/coverage/default/1.chip_sw_gpio_smoketest.4238044080
Short name T16
Test name
Test status
Simulation time 3597219630 ps
CPU time 274.45 seconds
Started Aug 08 08:34:06 PM PDT 24
Finished Aug 08 08:38:41 PM PDT 24
Peak memory 609772 kb
Host smart-03d1abbc-4a15-4e49-8823-75a0e5335bc8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238044080 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_sw_gpio_smoketest.4238044080
Directory /workspace/1.chip_sw_gpio_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1075799536
Short name T90
Test name
Test status
Simulation time 12087449720 ps
CPU time 1487.09 seconds
Started Aug 08 08:29:14 PM PDT 24
Finished Aug 08 08:54:01 PM PDT 24
Peak memory 610676 kb
Host smart-01960e2d-e2f2-43ee-a139-2744aed00c57
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler
_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075799536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han
dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.chip_sw_alert_handler_lpg_sleep_mode_pings.1075799536
Directory /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_csrng.728837433
Short name T126
Test name
Test status
Simulation time 6059506368 ps
CPU time 1432.32 seconds
Started Aug 08 08:28:42 PM PDT 24
Finished Aug 08 08:52:35 PM PDT 24
Peak memory 609092 kb
Host smart-61051f9d-9aa4-4f96-bcbf-6e261b90f2c7
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_
csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=728837433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.728837433
Directory /workspace/1.chip_sw_entropy_src_csrng/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3037514802
Short name T809
Test name
Test status
Simulation time 98035707192 ps
CPU time 1659.7 seconds
Started Aug 08 08:00:27 PM PDT 24
Finished Aug 08 08:28:08 PM PDT 24
Peak memory 575968 kb
Host smart-a7fe28e3-4a62-4333-83a2-d6037fc8b926
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037514802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_
device_slow_rsp.3037514802
Directory /workspace/53.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.chip_tl_errors.1985919039
Short name T521
Test name
Test status
Simulation time 5012791700 ps
CPU time 497.84 seconds
Started Aug 08 07:52:54 PM PDT 24
Finished Aug 08 08:01:12 PM PDT 24
Peak memory 598660 kb
Host smart-d664e5cd-8dd4-4198-a6c2-0430caaa45aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985919039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.1985919039
Directory /workspace/16.chip_tl_errors/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4006644140
Short name T63
Test name
Test status
Simulation time 24212306148 ps
CPU time 1603.29 seconds
Started Aug 08 08:43:30 PM PDT 24
Finished Aug 08 09:10:14 PM PDT 24
Peak memory 610736 kb
Host smart-307de0ab-0524-4f5d-99e7-b3e7eda76b54
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4006644140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4006644140
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.2421845039
Short name T620
Test name
Test status
Simulation time 10940380591 ps
CPU time 458.14 seconds
Started Aug 08 08:06:59 PM PDT 24
Finished Aug 08 08:14:38 PM PDT 24
Peak memory 576668 kb
Host smart-e1a3c822-2680-4c35-a05c-3f2595213f60
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421845039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.2421845039
Directory /workspace/91.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.2927749514
Short name T771
Test name
Test status
Simulation time 113112877492 ps
CPU time 1965.72 seconds
Started Aug 08 08:02:22 PM PDT 24
Finished Aug 08 08:35:08 PM PDT 24
Peak memory 575956 kb
Host smart-424fada0-05a3-4682-87bb-4428ad300b31
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927749514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_
device_slow_rsp.2927749514
Directory /workspace/64.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/2.chip_plic_all_irqs_10.2627638614
Short name T157
Test name
Test status
Simulation time 4225330086 ps
CPU time 444.23 seconds
Started Aug 08 08:41:36 PM PDT 24
Finished Aug 08 08:49:00 PM PDT 24
Peak memory 608448 kb
Host smart-6df771ec-6922-4369-998a-a67dd911176d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627638614 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.chip_plic_all_irqs_10.2627638614
Directory /workspace/2.chip_plic_all_irqs_10/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2853371362
Short name T511
Test name
Test status
Simulation time 1929980648 ps
CPU time 224.71 seconds
Started Aug 08 07:56:12 PM PDT 24
Finished Aug 08 07:59:56 PM PDT 24
Peak memory 576764 kb
Host smart-12aa60b5-8ec6-425a-92ab-7bda596b6e79
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853371362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al
l_with_reset_error.2853371362
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/default/1.chip_jtag_csr_rw.675442415
Short name T59
Test name
Test status
Simulation time 12609537852 ps
CPU time 1280.97 seconds
Started Aug 08 08:24:15 PM PDT 24
Finished Aug 08 08:45:37 PM PDT 24
Peak memory 608092 kb
Host smart-4e6a4572-0970-4f7e-9238-43daac6e277b
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675442415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch
ip_jtag_csr_rw.675442415
Directory /workspace/1.chip_jtag_csr_rw/latest

Test location /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2501372158
Short name T69
Test name
Test status
Simulation time 58933314760 ps
CPU time 10535.6 seconds
Started Aug 08 08:36:00 PM PDT 24
Finished Aug 08 11:31:36 PM PDT 24
Peak memory 624772 kb
Host smart-30463fdc-4c5e-4f88-bf8e-981b4d165de5
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=2501372158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.2501372158
Directory /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.717860688
Short name T802
Test name
Test status
Simulation time 50855349498 ps
CPU time 876.43 seconds
Started Aug 08 07:54:27 PM PDT 24
Finished Aug 08 08:09:04 PM PDT 24
Peak memory 575892 kb
Host smart-2fc8c673-f1b4-4a74-8b52-fb88565db390
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717860688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_d
evice_slow_rsp.717860688
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3261497798
Short name T172
Test name
Test status
Simulation time 42795643172 ps
CPU time 5193.17 seconds
Started Aug 08 08:14:45 PM PDT 24
Finished Aug 08 09:41:19 PM PDT 24
Peak memory 623216 kb
Host smart-793481f3-062d-4bd9-a6d4-069ffdef706d
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_
rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3261497798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.3261497798
Directory /workspace/0.chip_sw_flash_rma_unlocked/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3332540522
Short name T9
Test name
Test status
Simulation time 4078681656 ps
CPU time 445.14 seconds
Started Aug 08 08:15:47 PM PDT 24
Finished Aug 08 08:23:13 PM PDT 24
Peak memory 610652 kb
Host smart-0f73aed0-93fc-4334-a198-b40f401186d2
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33
32540522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.3332540522
Directory /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3684335951
Short name T130
Test name
Test status
Simulation time 5303785788 ps
CPU time 416.64 seconds
Started Aug 08 08:17:49 PM PDT 24
Finished Aug 08 08:24:46 PM PDT 24
Peak memory 608972 kb
Host smart-98f97da8-d48d-4075-9c6d-4b0f09dfff7c
User root
Command /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36843359
51 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3684335951
Directory /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.858962037
Short name T80
Test name
Test status
Simulation time 8231299611 ps
CPU time 88.33 seconds
Started Aug 08 08:08:06 PM PDT 24
Finished Aug 08 08:09:35 PM PDT 24
Peak memory 574504 kb
Host smart-3535ce15-0332-4062-be10-fcfc3ee01536
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858962037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.858962037
Directory /workspace/99.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.765807935
Short name T147
Test name
Test status
Simulation time 17086076092 ps
CPU time 2038.06 seconds
Started Aug 08 07:49:50 PM PDT 24
Finished Aug 08 08:23:49 PM PDT 24
Peak memory 593324 kb
Host smart-f2f8a662-8736-4e1b-bdf8-2805cd2328ff
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765807935 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.chip_same_csr_outstanding.765807935
Directory /workspace/0.chip_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2727219461
Short name T71
Test name
Test status
Simulation time 10773244144 ps
CPU time 1412.34 seconds
Started Aug 08 08:25:11 PM PDT 24
Finished Aug 08 08:48:44 PM PDT 24
Peak memory 611216 kb
Host smart-95f3f23d-1715-4c6c-839c-c214e0b61944
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727
219461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.2727219461
Directory /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.125627846
Short name T120
Test name
Test status
Simulation time 3780587488 ps
CPU time 545.89 seconds
Started Aug 08 08:44:44 PM PDT 24
Finished Aug 08 08:53:50 PM PDT 24
Peak memory 610824 kb
Host smart-910c447f-5a96-4821-b9b8-c06dc54b7adb
User root
Command /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk
_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125627846 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.125627846
Directory /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1643285832
Short name T10
Test name
Test status
Simulation time 3252819997 ps
CPU time 269.81 seconds
Started Aug 08 08:24:03 PM PDT 24
Finished Aug 08 08:28:33 PM PDT 24
Peak memory 610272 kb
Host smart-e0c54f51-6a13-410f-a902-47ceacf5886c
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643
285832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.1643285832
Directory /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest

Test location /workspace/coverage/default/0.chip_sw_edn_sw_mode.1900447056
Short name T128
Test name
Test status
Simulation time 11247173700 ps
CPU time 2532.7 seconds
Started Aug 08 08:16:16 PM PDT 24
Finished Aug 08 08:58:30 PM PDT 24
Peak memory 609904 kb
Host smart-592cd269-af3f-4827-b7cf-df51bba18bd7
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900447056 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.1900447056
Directory /workspace/0.chip_sw_edn_sw_mode/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1486336612
Short name T23
Test name
Test status
Simulation time 22844573600 ps
CPU time 2251.04 seconds
Started Aug 08 08:19:03 PM PDT 24
Finished Aug 08 08:56:35 PM PDT 24
Peak memory 615240 kb
Host smart-068e8734-77d5-47c6-9868-3e47ed9d2bf0
User root
Command /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14863366
12 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.1486336612
Directory /workspace/0.chip_sw_sysrst_ctrl_reset/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3880719684
Short name T450
Test name
Test status
Simulation time 5809521380 ps
CPU time 654.14 seconds
Started Aug 08 08:03:58 PM PDT 24
Finished Aug 08 08:14:52 PM PDT 24
Peak memory 576712 kb
Host smart-9b374802-87f2-4d81-bd51-1c65834731b9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880719684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all
_with_rand_reset.3880719684
Directory /workspace/73.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pin_retention.2237220488
Short name T17
Test name
Test status
Simulation time 3775116730 ps
CPU time 367.41 seconds
Started Aug 08 08:35:15 PM PDT 24
Finished Aug 08 08:41:23 PM PDT 24
Peak memory 610244 kb
Host smart-bc674285-0827-4b20-86c0-07bedad9be09
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237220488 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.2237220488
Directory /workspace/2.chip_sw_sleep_pin_retention/latest

Test location /workspace/coverage/cover_reg_top/11.chip_tl_errors.3771310722
Short name T525
Test name
Test status
Simulation time 5166510150 ps
CPU time 314.02 seconds
Started Aug 08 07:51:35 PM PDT 24
Finished Aug 08 07:56:50 PM PDT 24
Peak memory 598688 kb
Host smart-07ce2008-96f7-4f8b-badf-3da03e65609a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771310722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.3771310722
Directory /workspace/11.chip_tl_errors/latest

Test location /workspace/coverage/default/1.chip_sw_alert_test.297417954
Short name T66
Test name
Test status
Simulation time 2900825788 ps
CPU time 361.04 seconds
Started Aug 08 08:29:12 PM PDT 24
Finished Aug 08 08:35:14 PM PDT 24
Peak memory 609348 kb
Host smart-7c6c7a9d-d1c9-4c13-8b8c-ed2b7a9f273f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297417954 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.chip_sw_alert_test.297417954
Directory /workspace/1.chip_sw_alert_test/latest

Test location /workspace/coverage/default/94.chip_sw_all_escalation_resets.2394419906
Short name T174
Test name
Test status
Simulation time 5586165148 ps
CPU time 768.92 seconds
Started Aug 08 08:57:28 PM PDT 24
Finished Aug 08 09:10:17 PM PDT 24
Peak memory 650180 kb
Host smart-276e8f72-4193-431c-9c26-5d16fa1e293b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2394419906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.2394419906
Directory /workspace/94.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3490167778
Short name T105
Test name
Test status
Simulation time 2939815717 ps
CPU time 269.05 seconds
Started Aug 08 08:36:40 PM PDT 24
Finished Aug 08 08:41:09 PM PDT 24
Peak memory 621252 kb
Host smart-425b64b5-0041-402a-b063-5a39cc75bea3
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34901677
78 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.3490167778
Directory /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location /workspace/coverage/default/11.chip_sw_all_escalation_resets.283026728
Short name T289
Test name
Test status
Simulation time 5425756000 ps
CPU time 685.77 seconds
Started Aug 08 08:51:14 PM PDT 24
Finished Aug 08 09:02:41 PM PDT 24
Peak memory 650088 kb
Host smart-0ebff2b1-abaf-46a7-83a3-ddd9af4fcf70
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
283026728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.283026728
Directory /workspace/11.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1841509729
Short name T12
Test name
Test status
Simulation time 3532036584 ps
CPU time 366.75 seconds
Started Aug 08 08:15:51 PM PDT 24
Finished Aug 08 08:21:58 PM PDT 24
Peak memory 609464 kb
Host smart-9b598a33-25da-48d1-8086-ad27d95fa051
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841
509729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.1841509729
Directory /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1973861746
Short name T434
Test name
Test status
Simulation time 2871237040 ps
CPU time 484.72 seconds
Started Aug 08 07:55:08 PM PDT 24
Finished Aug 08 08:03:13 PM PDT 24
Peak memory 576784 kb
Host smart-db0e856a-807c-45ce-b402-935121289dd7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973861746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all
_with_rand_reset.1973861746
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.4175788335
Short name T141
Test name
Test status
Simulation time 3900980164 ps
CPU time 245.68 seconds
Started Aug 08 07:49:56 PM PDT 24
Finished Aug 08 07:54:02 PM PDT 24
Peak memory 664448 kb
Host smart-2e7405fa-13e2-46a5-ae57-25ab899c855d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175788335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r
eset.4175788335
Directory /workspace/0.chip_csr_hw_reset/latest

Test location /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2639497085
Short name T348
Test name
Test status
Simulation time 3327180610 ps
CPU time 470.14 seconds
Started Aug 08 08:49:49 PM PDT 24
Finished Aug 08 08:57:39 PM PDT 24
Peak memory 648380 kb
Host smart-3af9faaf-35d4-4046-8b32-d1cbbdeff594
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639497085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2639497085
Directory /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/91.chip_sw_all_escalation_resets.2247204723
Short name T98
Test name
Test status
Simulation time 5158935038 ps
CPU time 578.9 seconds
Started Aug 08 08:58:50 PM PDT 24
Finished Aug 08 09:08:29 PM PDT 24
Peak memory 650388 kb
Host smart-06d2593f-aacc-468d-bd6b-722a8b67f64b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2247204723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.2247204723
Directory /workspace/91.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3218692770
Short name T256
Test name
Test status
Simulation time 3457063052 ps
CPU time 342.34 seconds
Started Aug 08 08:49:26 PM PDT 24
Finished Aug 08 08:55:09 PM PDT 24
Peak memory 648620 kb
Host smart-e0bf87db-6966-4b9b-89d9-4223f5126fa5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218692770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3218692770
Directory /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/cover_reg_top/10.chip_tl_errors.1105631450
Short name T370
Test name
Test status
Simulation time 5320003880 ps
CPU time 396.88 seconds
Started Aug 08 07:51:40 PM PDT 24
Finished Aug 08 07:58:17 PM PDT 24
Peak memory 598728 kb
Host smart-7ac8e6f1-8f4a-424d-bede-b590da21c7d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105631450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.1105631450
Directory /workspace/10.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3067422817
Short name T792
Test name
Test status
Simulation time 11946154035 ps
CPU time 537.66 seconds
Started Aug 08 07:57:48 PM PDT 24
Finished Aug 08 08:06:46 PM PDT 24
Peak memory 575936 kb
Host smart-07304a06-5d1e-4ae3-8fad-c3793121bd1f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067422817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al
l_with_reset_error.3067422817
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.586418617
Short name T183
Test name
Test status
Simulation time 44240539544 ps
CPU time 5492.97 seconds
Started Aug 08 08:25:08 PM PDT 24
Finished Aug 08 09:56:42 PM PDT 24
Peak memory 621828 kb
Host smart-457a35c4-b560-4873-b5a0-fb62c14ade32
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_
rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=586418617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.586418617
Directory /workspace/1.chip_sw_flash_rma_unlocked/latest

Test location /workspace/coverage/default/2.chip_tap_straps_testunlock0.2181184673
Short name T74
Test name
Test status
Simulation time 4069913751 ps
CPU time 241.04 seconds
Started Aug 08 08:43:29 PM PDT 24
Finished Aug 08 08:47:30 PM PDT 24
Peak memory 624908 kb
Host smart-b5d231cf-7c96-4bc9-9a20-4bd008f515e0
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181184673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.2181184673
Directory /workspace/2.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.124465532
Short name T8
Test name
Test status
Simulation time 77695912331 ps
CPU time 13622.1 seconds
Started Aug 08 08:16:26 PM PDT 24
Finished Aug 09 12:03:30 AM PDT 24
Peak memory 635008 kb
Host smart-1b1464a6-a07c-4311-be31-ead160eec96a
User root
Command /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=124465532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.124465532
Directory /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest

Test location /workspace/coverage/default/2.chip_plic_all_irqs_0.3734467542
Short name T306
Test name
Test status
Simulation time 5902999134 ps
CPU time 1287.37 seconds
Started Aug 08 08:41:44 PM PDT 24
Finished Aug 08 09:03:12 PM PDT 24
Peak memory 610124 kb
Host smart-5e17d135-7b48-4e10-b7f1-ab1dafa88d71
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734467542 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_plic_all_irqs_0.3734467542
Directory /workspace/2.chip_plic_all_irqs_0/latest

Test location /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.1728033384
Short name T425
Test name
Test status
Simulation time 29428436376 ps
CPU time 4538.83 seconds
Started Aug 08 07:53:01 PM PDT 24
Finished Aug 08 09:08:41 PM PDT 24
Peak memory 593724 kb
Host smart-83ac97bf-2944-4d4d-9c0f-a90e0c255a0f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728033384 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.1728033384
Directory /workspace/17.chip_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1524897739
Short name T136
Test name
Test status
Simulation time 7590064656 ps
CPU time 1051.72 seconds
Started Aug 08 08:18:16 PM PDT 24
Finished Aug 08 08:35:48 PM PDT 24
Peak memory 609300 kb
Host smart-c0e881f0-1d63-45e9-b546-b69f3b0c0aaf
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15248977
39 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.1524897739
Directory /workspace/0.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.4106325604
Short name T58
Test name
Test status
Simulation time 3607252193 ps
CPU time 273.12 seconds
Started Aug 08 08:15:54 PM PDT 24
Finished Aug 08 08:20:27 PM PDT 24
Peak memory 619060 kb
Host smart-0faebcdc-fa6e-42e5-b84a-ed1d5fbc1779
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106325604 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.4106325604
Directory /workspace/0.chip_sw_spi_device_pinmux_sleep_retention/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3846637876
Short name T78
Test name
Test status
Simulation time 3839230536 ps
CPU time 510.14 seconds
Started Aug 08 08:17:01 PM PDT 24
Finished Aug 08 08:25:31 PM PDT 24
Peak memory 608564 kb
Host smart-c91f0d41-0e30-4178-971d-c6c0c34ec875
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384663
7876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3846637876
Directory /workspace/0.chip_sw_usbdev_aon_pullup/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all.1474459095
Short name T465
Test name
Test status
Simulation time 7037939527 ps
CPU time 264.02 seconds
Started Aug 08 07:54:54 PM PDT 24
Finished Aug 08 07:59:18 PM PDT 24
Peak memory 576032 kb
Host smart-fa5376bf-6755-413a-890c-9c8a105259cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474459095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1474459095
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/default/0.chip_plic_all_irqs_20.1990341563
Short name T302
Test name
Test status
Simulation time 4237668784 ps
CPU time 777.62 seconds
Started Aug 08 08:19:16 PM PDT 24
Finished Aug 08 08:32:15 PM PDT 24
Peak memory 609352 kb
Host smart-7e8fbe7e-038c-4c36-895d-3618b784d08d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990341563 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.chip_plic_all_irqs_20.1990341563
Directory /workspace/0.chip_plic_all_irqs_20/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2885605817
Short name T180
Test name
Test status
Simulation time 10484054477 ps
CPU time 1052.65 seconds
Started Aug 08 08:19:42 PM PDT 24
Finished Aug 08 08:37:15 PM PDT 24
Peak memory 609316 kb
Host smart-ec49869d-99af-47f8-8536-a19284f91bbe
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885605817 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.2885605817
Directory /workspace/0.chip_sw_sram_ctrl_execution_main/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1079581041
Short name T431
Test name
Test status
Simulation time 4497551980 ps
CPU time 562.31 seconds
Started Aug 08 07:57:49 PM PDT 24
Finished Aug 08 08:07:12 PM PDT 24
Peak memory 576000 kb
Host smart-d0e757eb-4dc1-4469-9724-3fd7f1e62e3b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079581041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all
_with_rand_reset.1079581041
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.841273415
Short name T436
Test name
Test status
Simulation time 12045854720 ps
CPU time 683.92 seconds
Started Aug 08 07:52:13 PM PDT 24
Finished Aug 08 08:03:37 PM PDT 24
Peak memory 576676 kb
Host smart-80097da0-07e4-4872-838d-74b797760876
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841273415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_
with_rand_reset.841273415
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4213941918
Short name T121
Test name
Test status
Simulation time 4816280029 ps
CPU time 631.97 seconds
Started Aug 08 08:16:01 PM PDT 24
Finished Aug 08 08:26:34 PM PDT 24
Peak memory 619684 kb
Host smart-a6904ba3-db84-4122-a5cd-cfbd6b7e0324
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213941918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.4213941918
Directory /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/0.chip_plic_all_irqs_0.3882387008
Short name T309
Test name
Test status
Simulation time 6138179848 ps
CPU time 1086.53 seconds
Started Aug 08 08:17:20 PM PDT 24
Finished Aug 08 08:35:27 PM PDT 24
Peak memory 609288 kb
Host smart-53364731-9787-4cb6-99bb-7a5ef9d1d5db
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882387008 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_plic_all_irqs_0.3882387008
Directory /workspace/0.chip_plic_all_irqs_0/latest

Test location /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1990231455
Short name T116
Test name
Test status
Simulation time 18157964906 ps
CPU time 2645.67 seconds
Started Aug 08 08:32:29 PM PDT 24
Finished Aug 08 09:16:35 PM PDT 24
Peak memory 611068 kb
Host smart-689a3e20-4d5c-47ca-8ceb-2acc8e83bb81
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990231455
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.1990231455
Directory /workspace/1.chip_sw_ast_clk_rst_inputs/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2313981578
Short name T275
Test name
Test status
Simulation time 47633965492 ps
CPU time 5455.04 seconds
Started Aug 08 08:36:42 PM PDT 24
Finished Aug 08 10:07:38 PM PDT 24
Peak memory 620580 kb
Host smart-854d4124-05b2-47f1-b66d-70bd4915ea17
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313981578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip
_sw_lc_walkthrough_dev.2313981578
Directory /workspace/2.chip_sw_lc_walkthrough_dev/latest

Test location /workspace/coverage/cover_reg_top/27.chip_tl_errors.1574504337
Short name T544
Test name
Test status
Simulation time 4579468375 ps
CPU time 451.59 seconds
Started Aug 08 07:55:19 PM PDT 24
Finished Aug 08 08:02:50 PM PDT 24
Peak memory 603680 kb
Host smart-2274e09f-2e5a-464b-ae22-76037a012b97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574504337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.1574504337
Directory /workspace/27.chip_tl_errors/latest

Test location /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.107155044
Short name T193
Test name
Test status
Simulation time 5050072836 ps
CPU time 246.61 seconds
Started Aug 08 07:49:50 PM PDT 24
Finished Aug 08 07:53:57 PM PDT 24
Peak memory 650040 kb
Host smart-f77d60b6-14af-43b9-87c1-587f43289564
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107155044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n
ull -cm_name 0.chip_padctrl_attributes.107155044
Directory /workspace/0.chip_padctrl_attributes/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3994584329
Short name T61
Test name
Test status
Simulation time 2776887630 ps
CPU time 236.72 seconds
Started Aug 08 08:18:17 PM PDT 24
Finished Aug 08 08:22:15 PM PDT 24
Peak memory 610164 kb
Host smart-1de42418-f3e8-4f39-88d7-f865386f22fe
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994584329
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.3994584329
Directory /workspace/0.chip_sw_sleep_pin_wake/latest

Test location /workspace/coverage/default/0.rom_e2e_shutdown_output.2067233350
Short name T48
Test name
Test status
Simulation time 25748168660 ps
CPU time 4143.86 seconds
Started Aug 08 08:24:46 PM PDT 24
Finished Aug 08 09:33:51 PM PDT 24
Peak memory 611524 kb
Host smart-884baeaa-1c9a-4054-bbe5-1dba71df6bed
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f
lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067233350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rom_e2e_shutdown_output.2067233350
Directory /workspace/0.rom_e2e_shutdown_output/latest

Test location /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.4026260134
Short name T132
Test name
Test status
Simulation time 5146160204 ps
CPU time 822.19 seconds
Started Aug 08 08:40:55 PM PDT 24
Finished Aug 08 08:54:37 PM PDT 24
Peak memory 609428 kb
Host smart-9325f9e9-c634-4181-84df-8b6e29436763
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40262601
34 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.4026260134
Directory /workspace/2.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/55.chip_sw_all_escalation_resets.3714730173
Short name T195
Test name
Test status
Simulation time 4845328424 ps
CPU time 709.05 seconds
Started Aug 08 08:54:26 PM PDT 24
Finished Aug 08 09:06:15 PM PDT 24
Peak memory 650260 kb
Host smart-27aab9d1-ea6b-4d51-b4aa-f18e5de56592
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3714730173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.3714730173
Directory /workspace/55.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2960128078
Short name T451
Test name
Test status
Simulation time 4455047315 ps
CPU time 417.08 seconds
Started Aug 08 08:01:19 PM PDT 24
Finished Aug 08 08:08:16 PM PDT 24
Peak memory 575952 kb
Host smart-a8cd302a-7e98-4445-9ed7-a11d8da39fab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960128078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all
_with_rand_reset.2960128078
Directory /workspace/57.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.chip_tl_errors.674826544
Short name T522
Test name
Test status
Simulation time 4597148952 ps
CPU time 323.16 seconds
Started Aug 08 07:53:04 PM PDT 24
Finished Aug 08 07:58:27 PM PDT 24
Peak memory 600632 kb
Host smart-8e48cb4a-a11d-47f3-9862-2efaa6090d77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674826544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.674826544
Directory /workspace/17.chip_tl_errors/latest

Test location /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2843908593
Short name T37
Test name
Test status
Simulation time 3255026550 ps
CPU time 235.5 seconds
Started Aug 08 08:22:57 PM PDT 24
Finished Aug 08 08:26:53 PM PDT 24
Peak memory 610052 kb
Host smart-a837f152-3821-4586-819b-3fb70dc04fa6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843908593 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.2843908593
Directory /workspace/1.chip_sw_spi_host_tx_rx/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.64683994
Short name T139
Test name
Test status
Simulation time 7376979264 ps
CPU time 403.26 seconds
Started Aug 08 07:50:08 PM PDT 24
Finished Aug 08 07:56:51 PM PDT 24
Peak memory 665436 kb
Host smart-84667420-9cd2-4bb0-a181-65a6703b504d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64683994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_res
et.64683994
Directory /workspace/2.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3404668780
Short name T447
Test name
Test status
Simulation time 6707400192 ps
CPU time 736.81 seconds
Started Aug 08 07:58:55 PM PDT 24
Finished Aug 08 08:11:12 PM PDT 24
Peak memory 576788 kb
Host smart-196415e9-4b0c-414b-aeeb-d09a1522c94a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404668780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all
_with_rand_reset.3404668780
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.chip_sw_gpio.3529016954
Short name T30
Test name
Test status
Simulation time 3481280304 ps
CPU time 562.68 seconds
Started Aug 08 08:35:39 PM PDT 24
Finished Aug 08 08:45:02 PM PDT 24
Peak memory 609320 kb
Host smart-267c74a3-bdd0-450b-b074-b156009e3fe6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529016954 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.chip_sw_gpio.3529016954
Directory /workspace/2.chip_sw_gpio/latest

Test location /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1713631348
Short name T296
Test name
Test status
Simulation time 5310885128 ps
CPU time 409.54 seconds
Started Aug 08 08:31:49 PM PDT 24
Finished Aug 08 08:38:39 PM PDT 24
Peak memory 619488 kb
Host smart-15cec8bc-1c5b-4c6a-9c70-f212e19434c9
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171363
1348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1713631348
Directory /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.854907359
Short name T163
Test name
Test status
Simulation time 3251815692 ps
CPU time 235.4 seconds
Started Aug 08 08:26:55 PM PDT 24
Finished Aug 08 08:30:51 PM PDT 24
Peak memory 622584 kb
Host smart-dba565b4-6427-4ac3-bde3-2b466e376b59
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854907359 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.854907359
Directory /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1403616122
Short name T184
Test name
Test status
Simulation time 44345016206 ps
CPU time 5047.29 seconds
Started Aug 08 08:35:50 PM PDT 24
Finished Aug 08 09:59:59 PM PDT 24
Peak memory 620648 kb
Host smart-836f08d1-cb52-4512-8be1-ea826d7480e9
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_
rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1403616122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.1403616122
Directory /workspace/2.chip_sw_flash_rma_unlocked/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2423519048
Short name T327
Test name
Test status
Simulation time 4220045495 ps
CPU time 619.16 seconds
Started Aug 08 08:19:52 PM PDT 24
Finished Aug 08 08:30:12 PM PDT 24
Peak memory 609888 kb
Host smart-5ec05963-1baf-4a8b-ae0c-5e32f4a9cf03
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2423519048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.2423519048
Directory /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.3573649214
Short name T829
Test name
Test status
Simulation time 555722346 ps
CPU time 126.48 seconds
Started Aug 08 07:57:36 PM PDT 24
Finished Aug 08 07:59:42 PM PDT 24
Peak memory 575976 kb
Host smart-931efca6-f6f5-4fcc-9cda-1a45ada77810
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573649214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all
_with_rand_reset.3573649214
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2073379865
Short name T52
Test name
Test status
Simulation time 4992237920 ps
CPU time 685.84 seconds
Started Aug 08 08:31:51 PM PDT 24
Finished Aug 08 08:43:17 PM PDT 24
Peak memory 612156 kb
Host smart-0f83476f-2082-45f2-b47e-1b09524c47e8
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073379865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_dev.2073379865
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.3724244124
Short name T2516
Test name
Test status
Simulation time 2140646669 ps
CPU time 350.23 seconds
Started Aug 08 07:56:44 PM PDT 24
Finished Aug 08 08:02:34 PM PDT 24
Peak memory 576764 kb
Host smart-798c7168-2410-4296-a36f-65707b25516c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724244124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all
_with_rand_reset.3724244124
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.chip_csr_rw.3352172323
Short name T387
Test name
Test status
Simulation time 5691231962 ps
CPU time 569.01 seconds
Started Aug 08 07:52:26 PM PDT 24
Finished Aug 08 08:01:55 PM PDT 24
Peak memory 598488 kb
Host smart-de7b3311-0d1d-44a9-824a-ea65fd10b7e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352172323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.3352172323
Directory /workspace/14.chip_csr_rw/latest

Test location /workspace/coverage/default/0.chip_plic_all_irqs_10.2818478712
Short name T156
Test name
Test status
Simulation time 3781778920 ps
CPU time 526.8 seconds
Started Aug 08 08:19:52 PM PDT 24
Finished Aug 08 08:28:39 PM PDT 24
Peak memory 609724 kb
Host smart-b6889af2-00a7-4734-b38d-9272460dbaf9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818478712 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.chip_plic_all_irqs_10.2818478712
Directory /workspace/0.chip_plic_all_irqs_10/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.993092495
Short name T831
Test name
Test status
Simulation time 3742494249 ps
CPU time 286.6 seconds
Started Aug 08 07:54:12 PM PDT 24
Finished Aug 08 07:58:59 PM PDT 24
Peak memory 576792 kb
Host smart-e32355de-4c40-46a7-9b39-79eeeb20fdc8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993092495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all
_with_reset_error.993092495
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.3299058829
Short name T836
Test name
Test status
Simulation time 686094459 ps
CPU time 221.02 seconds
Started Aug 08 08:01:06 PM PDT 24
Finished Aug 08 08:04:48 PM PDT 24
Peak memory 576712 kb
Host smart-cf73817b-397c-4e7b-8885-e7841fe06c60
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299058829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all
_with_rand_reset.3299058829
Directory /workspace/56.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.11695907
Short name T18
Test name
Test status
Simulation time 3968669890 ps
CPU time 573.91 seconds
Started Aug 08 08:16:34 PM PDT 24
Finished Aug 08 08:26:08 PM PDT 24
Peak memory 623836 kb
Host smart-99b8bf2a-60a4-48a9-aaaa-c550a5fe43d5
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11695907 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.11695907
Directory /workspace/0.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1839162155
Short name T235
Test name
Test status
Simulation time 13529412440 ps
CPU time 3100.97 seconds
Started Aug 08 08:48:37 PM PDT 24
Finished Aug 08 09:40:19 PM PDT 24
Peak memory 610328 kb
Host smart-b08316bb-7136-4b9d-bf38-b36bfcede7cf
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839162155 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.1839162155
Directory /workspace/3.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3652227793
Short name T1845
Test name
Test status
Simulation time 14097434251 ps
CPU time 676.53 seconds
Started Aug 08 08:02:01 PM PDT 24
Finished Aug 08 08:13:18 PM PDT 24
Peak memory 575952 kb
Host smart-9c738126-9b34-4e0e-84a0-95b02c28c4dd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652227793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all
_with_rand_reset.3652227793
Directory /workspace/61.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1898942944
Short name T278
Test name
Test status
Simulation time 19275027512 ps
CPU time 2132.89 seconds
Started Aug 08 08:18:35 PM PDT 24
Finished Aug 08 08:54:10 PM PDT 24
Peak memory 613644 kb
Host smart-8bdb012c-7eb2-41e0-8923-f2485783d0b7
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1898942944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.1898942944
Directory /workspace/0.chip_sw_flash_init_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1873391562
Short name T216
Test name
Test status
Simulation time 4683913380 ps
CPU time 676.1 seconds
Started Aug 08 08:17:03 PM PDT 24
Finished Aug 08 08:28:20 PM PDT 24
Peak memory 624488 kb
Host smart-381d7322-9659-4f78-8992-2cfdb93324e1
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873391562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx
_alt_clk_freq.1873391562
Directory /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3391467284
Short name T75
Test name
Test status
Simulation time 2859423853 ps
CPU time 209.4 seconds
Started Aug 08 08:17:55 PM PDT 24
Finished Aug 08 08:21:25 PM PDT 24
Peak memory 622544 kb
Host smart-1db22255-114c-43a2-a7b7-53e51554f478
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391467284 -assert nopost
proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.3391467284
Directory /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3175182171
Short name T936
Test name
Test status
Simulation time 4910429037 ps
CPU time 430.09 seconds
Started Aug 08 08:30:51 PM PDT 24
Finished Aug 08 08:38:02 PM PDT 24
Peak memory 620404 kb
Host smart-6c439384-035d-4035-b868-a986cee96686
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=3175182171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.3175182171
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location /workspace/coverage/cover_reg_top/23.chip_tl_errors.1011049449
Short name T542
Test name
Test status
Simulation time 3933393556 ps
CPU time 373.89 seconds
Started Aug 08 07:54:40 PM PDT 24
Finished Aug 08 08:00:54 PM PDT 24
Peak memory 603672 kb
Host smart-d9a4ba66-a44c-4e47-9aa8-115b9200142f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011049449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.1011049449
Directory /workspace/23.chip_tl_errors/latest

Test location /workspace/coverage/default/1.chip_plic_all_irqs_20.3255584729
Short name T307
Test name
Test status
Simulation time 4239077414 ps
CPU time 732.95 seconds
Started Aug 08 08:31:34 PM PDT 24
Finished Aug 08 08:43:47 PM PDT 24
Peak memory 609304 kb
Host smart-a5eeb179-dde7-4fed-9b04-d62d63ec0494
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255584729 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.chip_plic_all_irqs_20.3255584729
Directory /workspace/1.chip_plic_all_irqs_20/latest

Test location /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1164275858
Short name T35
Test name
Test status
Simulation time 4162688885 ps
CPU time 484.83 seconds
Started Aug 08 08:44:40 PM PDT 24
Finished Aug 08 08:52:46 PM PDT 24
Peak memory 624188 kb
Host smart-ec2bade3-b6ec-4644-8c05-c4e4e21f0aab
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164275858 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.1164275858
Directory /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location /workspace/coverage/default/0.chip_sw_plic_sw_irq.99558954
Short name T230
Test name
Test status
Simulation time 2541725892 ps
CPU time 265.36 seconds
Started Aug 08 08:21:45 PM PDT 24
Finished Aug 08 08:26:10 PM PDT 24
Peak memory 609708 kb
Host smart-42bd1f20-7df2-480b-9384-60fe9068973a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99558954 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_plic_sw_irq.99558954
Directory /workspace/0.chip_sw_plic_sw_irq/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.3384984084
Short name T814
Test name
Test status
Simulation time 8359179300 ps
CPU time 314.35 seconds
Started Aug 08 07:59:57 PM PDT 24
Finished Aug 08 08:05:12 PM PDT 24
Peak memory 576712 kb
Host smart-80c9aa9a-85a9-4447-8e1a-4318e488fa99
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384984084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3384984084
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2148883535
Short name T311
Test name
Test status
Simulation time 15101806760 ps
CPU time 1696.82 seconds
Started Aug 08 08:25:00 PM PDT 24
Finished Aug 08 08:53:17 PM PDT 24
Peak memory 610932 kb
Host smart-49cba580-3ad7-4623-8c87-85196d4dcae7
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=2148883535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.2148883535
Directory /workspace/1.chip_sw_rstmgr_alert_info/latest

Test location /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3704307746
Short name T369
Test name
Test status
Simulation time 31037045967 ps
CPU time 4179.95 seconds
Started Aug 08 07:49:57 PM PDT 24
Finished Aug 08 08:59:37 PM PDT 24
Peak memory 592952 kb
Host smart-47b01f1f-0f46-4423-907b-df842e24bb69
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704307746 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.3704307746
Directory /workspace/1.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.319428852
Short name T469
Test name
Test status
Simulation time 8494916800 ps
CPU time 468.38 seconds
Started Aug 08 07:55:52 PM PDT 24
Finished Aug 08 08:03:40 PM PDT 24
Peak memory 575964 kb
Host smart-84334e03-9745-442d-a4bc-e07a1266bf18
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319428852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_
with_rand_reset.319428852
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all.1956764944
Short name T479
Test name
Test status
Simulation time 8020156428 ps
CPU time 269.35 seconds
Started Aug 08 07:58:06 PM PDT 24
Finished Aug 08 08:02:36 PM PDT 24
Peak memory 575964 kb
Host smart-aa35ef06-f697-4afe-80fe-1e9af87fcb05
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956764944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1956764944
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/default/1.chip_sw_gpio.659413969
Short name T29
Test name
Test status
Simulation time 4696403704 ps
CPU time 582.09 seconds
Started Aug 08 08:22:41 PM PDT 24
Finished Aug 08 08:32:24 PM PDT 24
Peak memory 609272 kb
Host smart-4bbe33fb-6f67-4af8-843d-32348d6550ec
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659413969 -assert nopostproc +UVM_TESTNAME=chip_base
_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.chip_sw_gpio.659413969
Directory /workspace/1.chip_sw_gpio/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_config_host.1652235100
Short name T150
Test name
Test status
Simulation time 7784261200 ps
CPU time 1684.03 seconds
Started Aug 08 08:15:45 PM PDT 24
Finished Aug 08 08:43:49 PM PDT 24
Peak memory 610132 kb
Host smart-d769ee87-fb81-4dbd-a9fc-e9e66e1b2a68
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16522
35100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.1652235100
Directory /workspace/0.chip_sw_usbdev_config_host/latest

Test location /workspace/coverage/cover_reg_top/13.chip_tl_errors.4130440526
Short name T691
Test name
Test status
Simulation time 2527106060 ps
CPU time 130.36 seconds
Started Aug 08 07:52:04 PM PDT 24
Finished Aug 08 07:54:14 PM PDT 24
Peak memory 600624 kb
Host smart-a5e71041-fbf4-45c8-9f26-32d0927cdc3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130440526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.4130440526
Directory /workspace/13.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.1901086816
Short name T838
Test name
Test status
Simulation time 203049802 ps
CPU time 115.29 seconds
Started Aug 08 07:54:57 PM PDT 24
Finished Aug 08 07:56:52 PM PDT 24
Peak memory 576696 kb
Host smart-bcc50658-0307-42cc-953c-923fc501b9ee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901086816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all
_with_rand_reset.1901086816
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2180228308
Short name T2
Test name
Test status
Simulation time 3343995986 ps
CPU time 597.34 seconds
Started Aug 08 08:16:49 PM PDT 24
Finished Aug 08 08:26:47 PM PDT 24
Peak memory 648360 kb
Host smart-8995a6d7-feea-4a3f-8f0f-f09f7d4e152b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180228308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s
w_alert_handler_lpg_sleep_mode_alerts.2180228308
Directory /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/0.chip_sw_all_escalation_resets.2347994624
Short name T1019
Test name
Test status
Simulation time 5628592452 ps
CPU time 590.74 seconds
Started Aug 08 08:15:58 PM PDT 24
Finished Aug 08 08:25:49 PM PDT 24
Peak memory 649864 kb
Host smart-118e5e03-d28a-4159-8f4c-e1ecf682e91c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2347994624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.2347994624
Directory /workspace/0.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.4244073263
Short name T1289
Test name
Test status
Simulation time 4176629440 ps
CPU time 555.96 seconds
Started Aug 08 08:28:04 PM PDT 24
Finished Aug 08 08:37:20 PM PDT 24
Peak memory 648560 kb
Host smart-30fc373c-1510-41f4-93f0-d5355be8c150
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244073263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s
w_alert_handler_lpg_sleep_mode_alerts.4244073263
Directory /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/1.chip_sw_all_escalation_resets.77782391
Short name T300
Test name
Test status
Simulation time 4641072280 ps
CPU time 788.74 seconds
Started Aug 08 08:24:48 PM PDT 24
Finished Aug 08 08:37:58 PM PDT 24
Peak memory 649724 kb
Host smart-919371bf-da65-434b-b9e0-91698d444721
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
77782391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.77782391
Directory /workspace/1.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/12.chip_sw_all_escalation_resets.3387062799
Short name T310
Test name
Test status
Simulation time 5193367550 ps
CPU time 584.03 seconds
Started Aug 08 08:50:06 PM PDT 24
Finished Aug 08 08:59:50 PM PDT 24
Peak memory 649588 kb
Host smart-3651b47e-f3f0-496b-9286-81cd4d26b93f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3387062799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.3387062799
Directory /workspace/12.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2890275474
Short name T744
Test name
Test status
Simulation time 3995567960 ps
CPU time 477.67 seconds
Started Aug 08 08:50:12 PM PDT 24
Finished Aug 08 08:58:10 PM PDT 24
Peak memory 648452 kb
Host smart-1ba15fb7-b3c3-43fe-bccc-56023e6ba44e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890275474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2890275474
Directory /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/14.chip_sw_all_escalation_resets.3371762600
Short name T676
Test name
Test status
Simulation time 5671830562 ps
CPU time 809.19 seconds
Started Aug 08 08:50:10 PM PDT 24
Finished Aug 08 09:03:40 PM PDT 24
Peak memory 650228 kb
Host smart-724ff682-9b5b-454c-a957-59d75ec54833
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3371762600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.3371762600
Directory /workspace/14.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3046929779
Short name T739
Test name
Test status
Simulation time 3911902120 ps
CPU time 350.79 seconds
Started Aug 08 08:51:19 PM PDT 24
Finished Aug 08 08:57:10 PM PDT 24
Peak memory 648656 kb
Host smart-39bad1c5-2b7c-44ce-bb3b-f095ef50f943
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046929779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3046929779
Directory /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/15.chip_sw_all_escalation_resets.3403912712
Short name T679
Test name
Test status
Simulation time 6377487872 ps
CPU time 850.5 seconds
Started Aug 08 08:50:11 PM PDT 24
Finished Aug 08 09:04:22 PM PDT 24
Peak memory 649916 kb
Host smart-1a0486b4-66b6-421e-ac74-4e46b74d9a63
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3403912712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.3403912712
Directory /workspace/15.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/16.chip_sw_all_escalation_resets.2639683062
Short name T1285
Test name
Test status
Simulation time 6231883564 ps
CPU time 771.11 seconds
Started Aug 08 08:50:38 PM PDT 24
Finished Aug 08 09:03:30 PM PDT 24
Peak memory 649776 kb
Host smart-3a8f8664-54b3-4d2e-8f56-cac371c3cbd6
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2639683062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.2639683062
Directory /workspace/16.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1238861730
Short name T97
Test name
Test status
Simulation time 4011946162 ps
CPU time 415.28 seconds
Started Aug 08 08:52:05 PM PDT 24
Finished Aug 08 08:59:01 PM PDT 24
Peak memory 648960 kb
Host smart-2b0d1a35-8e45-4490-84a8-571865f2593e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238861730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1238861730
Directory /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/17.chip_sw_all_escalation_resets.729021213
Short name T729
Test name
Test status
Simulation time 5087715468 ps
CPU time 616.08 seconds
Started Aug 08 08:51:30 PM PDT 24
Finished Aug 08 09:01:47 PM PDT 24
Peak memory 649944 kb
Host smart-7f28fd67-1947-4e99-b695-6022b4e8e5aa
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
729021213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.729021213
Directory /workspace/17.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/18.chip_sw_all_escalation_resets.2209776191
Short name T688
Test name
Test status
Simulation time 5219948132 ps
CPU time 624.63 seconds
Started Aug 08 08:51:27 PM PDT 24
Finished Aug 08 09:01:52 PM PDT 24
Peak memory 649692 kb
Host smart-b78d7bc9-cccf-4599-a6ec-582e5c95813f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2209776191 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.2209776191
Directory /workspace/18.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3176692430
Short name T367
Test name
Test status
Simulation time 3655836280 ps
CPU time 345.16 seconds
Started Aug 08 08:51:10 PM PDT 24
Finished Aug 08 08:56:55 PM PDT 24
Peak memory 648800 kb
Host smart-daf684f4-129e-4453-891d-f806d4772cfe
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176692430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3176692430
Directory /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3072350562
Short name T726
Test name
Test status
Simulation time 3418410840 ps
CPU time 439.84 seconds
Started Aug 08 08:38:39 PM PDT 24
Finished Aug 08 08:46:00 PM PDT 24
Peak memory 648448 kb
Host smart-c457cf81-6803-4a9a-9add-150b39b5c574
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072350562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s
w_alert_handler_lpg_sleep_mode_alerts.3072350562
Directory /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/2.chip_sw_all_escalation_resets.1525812603
Short name T748
Test name
Test status
Simulation time 5358719062 ps
CPU time 577.2 seconds
Started Aug 08 08:36:40 PM PDT 24
Finished Aug 08 08:46:17 PM PDT 24
Peak memory 649820 kb
Host smart-f3d24198-0f74-4643-a18d-26cee6166a44
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1525812603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.1525812603
Directory /workspace/2.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1875320140
Short name T724
Test name
Test status
Simulation time 3438422994 ps
CPU time 369.92 seconds
Started Aug 08 08:52:51 PM PDT 24
Finished Aug 08 08:59:01 PM PDT 24
Peak memory 648488 kb
Host smart-f2224a36-7a9e-46df-8e9c-7ac8c0ea0bdc
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875320140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1875320140
Directory /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2939721404
Short name T721
Test name
Test status
Simulation time 4013185692 ps
CPU time 448.52 seconds
Started Aug 08 08:52:02 PM PDT 24
Finished Aug 08 08:59:30 PM PDT 24
Peak memory 648472 kb
Host smart-4a0de4fc-223f-47be-b0ca-83d367949037
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939721404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2939721404
Directory /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/21.chip_sw_all_escalation_resets.3810526059
Short name T1335
Test name
Test status
Simulation time 5512482150 ps
CPU time 573.63 seconds
Started Aug 08 08:52:27 PM PDT 24
Finished Aug 08 09:02:01 PM PDT 24
Peak memory 649880 kb
Host smart-43fb2a70-b64d-4b13-8949-ea8ed5368f5a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3810526059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.3810526059
Directory /workspace/21.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2465992001
Short name T711
Test name
Test status
Simulation time 4338589888 ps
CPU time 388.44 seconds
Started Aug 08 08:52:45 PM PDT 24
Finished Aug 08 08:59:14 PM PDT 24
Peak memory 648800 kb
Host smart-7f98be95-645c-4fb3-afed-8e52ed2a01f2
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465992001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2465992001
Directory /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2735254973
Short name T674
Test name
Test status
Simulation time 3836298840 ps
CPU time 413.9 seconds
Started Aug 08 08:51:38 PM PDT 24
Finished Aug 08 08:58:32 PM PDT 24
Peak memory 648752 kb
Host smart-0c8cbefa-d85a-4d3b-9b8f-d2d7c974a9c5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735254973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2735254973
Directory /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/23.chip_sw_all_escalation_resets.3468758954
Short name T682
Test name
Test status
Simulation time 5240616446 ps
CPU time 672.78 seconds
Started Aug 08 08:51:50 PM PDT 24
Finished Aug 08 09:03:03 PM PDT 24
Peak memory 649788 kb
Host smart-9905c4c9-da6d-4b5b-9eb1-b191e90ed614
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3468758954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.3468758954
Directory /workspace/23.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.642326803
Short name T695
Test name
Test status
Simulation time 2967367216 ps
CPU time 354.17 seconds
Started Aug 08 08:52:11 PM PDT 24
Finished Aug 08 08:58:05 PM PDT 24
Peak memory 648644 kb
Host smart-29c247f1-3cf0-4ff0-9c9b-c275adea20da
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642326803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_s
w_alert_handler_lpg_sleep_mode_alerts.642326803
Directory /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/24.chip_sw_all_escalation_resets.3297700111
Short name T663
Test name
Test status
Simulation time 6116872488 ps
CPU time 665.54 seconds
Started Aug 08 08:52:41 PM PDT 24
Finished Aug 08 09:03:46 PM PDT 24
Peak memory 649924 kb
Host smart-5250e4fa-cebe-4509-a9d4-1a6590676562
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3297700111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.3297700111
Directory /workspace/24.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/25.chip_sw_all_escalation_resets.1689415394
Short name T1126
Test name
Test status
Simulation time 5211634280 ps
CPU time 597.98 seconds
Started Aug 08 08:52:24 PM PDT 24
Finished Aug 08 09:02:22 PM PDT 24
Peak memory 649948 kb
Host smart-63886c57-715b-4536-bef4-bb98969f96b8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1689415394 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.1689415394
Directory /workspace/25.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.206198315
Short name T227
Test name
Test status
Simulation time 3423738480 ps
CPU time 373.33 seconds
Started Aug 08 08:54:11 PM PDT 24
Finished Aug 08 09:00:25 PM PDT 24
Peak memory 648324 kb
Host smart-2825fbcf-24ee-4ab0-8b2b-310571a72b51
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206198315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_s
w_alert_handler_lpg_sleep_mode_alerts.206198315
Directory /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/27.chip_sw_all_escalation_resets.2973525898
Short name T720
Test name
Test status
Simulation time 4936017720 ps
CPU time 506.22 seconds
Started Aug 08 08:52:47 PM PDT 24
Finished Aug 08 09:01:14 PM PDT 24
Peak memory 649796 kb
Host smart-bed404f7-0af6-448d-bbad-8e8751591fb7
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2973525898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.2973525898
Directory /workspace/27.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1623203386
Short name T683
Test name
Test status
Simulation time 4184400906 ps
CPU time 393.65 seconds
Started Aug 08 08:51:17 PM PDT 24
Finished Aug 08 08:57:51 PM PDT 24
Peak memory 648656 kb
Host smart-b342da98-0b96-4f70-8424-195881de133b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623203386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1623203386
Directory /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.4081332063
Short name T759
Test name
Test status
Simulation time 4347830880 ps
CPU time 423.77 seconds
Started Aug 08 08:46:56 PM PDT 24
Finished Aug 08 08:53:59 PM PDT 24
Peak memory 648804 kb
Host smart-c368259e-13b5-4452-b8ee-ae86cced31cb
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081332063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s
w_alert_handler_lpg_sleep_mode_alerts.4081332063
Directory /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.539738980
Short name T611
Test name
Test status
Simulation time 3690577568 ps
CPU time 296.06 seconds
Started Aug 08 08:52:47 PM PDT 24
Finished Aug 08 08:57:44 PM PDT 24
Peak memory 648532 kb
Host smart-f674722f-4a4b-4be6-9613-5b69b0f1a2a9
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539738980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_s
w_alert_handler_lpg_sleep_mode_alerts.539738980
Directory /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/34.chip_sw_all_escalation_resets.1448889430
Short name T339
Test name
Test status
Simulation time 5207218904 ps
CPU time 926.97 seconds
Started Aug 08 08:51:54 PM PDT 24
Finished Aug 08 09:07:21 PM PDT 24
Peak memory 649816 kb
Host smart-30d97271-4d3e-4c2b-a245-d46cdcb624bc
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1448889430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.1448889430
Directory /workspace/34.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3220451977
Short name T709
Test name
Test status
Simulation time 3581119496 ps
CPU time 453.93 seconds
Started Aug 08 08:52:48 PM PDT 24
Finished Aug 08 09:00:22 PM PDT 24
Peak memory 648672 kb
Host smart-a9d20676-d9d2-4eac-9b8d-781cc4409e24
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220451977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3220451977
Directory /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/37.chip_sw_all_escalation_resets.1916986600
Short name T719
Test name
Test status
Simulation time 4997548504 ps
CPU time 438.45 seconds
Started Aug 08 08:52:35 PM PDT 24
Finished Aug 08 08:59:53 PM PDT 24
Peak memory 649968 kb
Host smart-530c0ac4-b6ee-4ac0-b57b-1063e6c2720b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1916986600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.1916986600
Directory /workspace/37.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1360562581
Short name T697
Test name
Test status
Simulation time 4385342784 ps
CPU time 362.27 seconds
Started Aug 08 08:52:48 PM PDT 24
Finished Aug 08 08:58:51 PM PDT 24
Peak memory 648996 kb
Host smart-a705068d-3f8b-4174-a6b0-0d5a7894bd1a
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360562581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1360562581
Directory /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1851259411
Short name T755
Test name
Test status
Simulation time 4061568590 ps
CPU time 460.51 seconds
Started Aug 08 08:53:40 PM PDT 24
Finished Aug 08 09:01:21 PM PDT 24
Peak memory 648596 kb
Host smart-bde7234e-227d-4201-be0c-ba5adb27fe13
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851259411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1851259411
Directory /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/41.chip_sw_all_escalation_resets.2093178912
Short name T290
Test name
Test status
Simulation time 4487695768 ps
CPU time 463.31 seconds
Started Aug 08 08:52:52 PM PDT 24
Finished Aug 08 09:00:36 PM PDT 24
Peak memory 650068 kb
Host smart-ae19f0e1-b4e6-420a-a996-662300988d5b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2093178912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.2093178912
Directory /workspace/41.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/42.chip_sw_all_escalation_resets.1219250571
Short name T767
Test name
Test status
Simulation time 5962929948 ps
CPU time 665.53 seconds
Started Aug 08 08:52:28 PM PDT 24
Finished Aug 08 09:03:34 PM PDT 24
Peak memory 649752 kb
Host smart-a4377490-98a6-4799-a339-10dd6e4bc4a4
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1219250571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.1219250571
Directory /workspace/42.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1841332110
Short name T650
Test name
Test status
Simulation time 3667565278 ps
CPU time 441.29 seconds
Started Aug 08 08:54:11 PM PDT 24
Finished Aug 08 09:01:33 PM PDT 24
Peak memory 648656 kb
Host smart-340d4f57-3718-435a-80a0-19be815c925e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841332110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1841332110
Directory /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/47.chip_sw_all_escalation_resets.465482917
Short name T712
Test name
Test status
Simulation time 5210458728 ps
CPU time 528.13 seconds
Started Aug 08 08:53:49 PM PDT 24
Finished Aug 08 09:02:37 PM PDT 24
Peak memory 649824 kb
Host smart-b047d820-cf50-4d52-9f42-5c3642142a40
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
465482917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.465482917
Directory /workspace/47.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3721582106
Short name T716
Test name
Test status
Simulation time 3760303434 ps
CPU time 408.33 seconds
Started Aug 08 08:55:05 PM PDT 24
Finished Aug 08 09:01:53 PM PDT 24
Peak memory 648584 kb
Host smart-3d466963-842e-4c3c-9ba5-2ac58155882e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721582106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3721582106
Directory /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/52.chip_sw_all_escalation_resets.3234162102
Short name T223
Test name
Test status
Simulation time 6176962944 ps
CPU time 624.28 seconds
Started Aug 08 08:55:23 PM PDT 24
Finished Aug 08 09:05:47 PM PDT 24
Peak memory 650012 kb
Host smart-452d1237-1e3f-402d-a973-f860a9c2dd81
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3234162102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.3234162102
Directory /workspace/52.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/53.chip_sw_all_escalation_resets.1160060458
Short name T349
Test name
Test status
Simulation time 4719417084 ps
CPU time 487.3 seconds
Started Aug 08 08:54:40 PM PDT 24
Finished Aug 08 09:02:47 PM PDT 24
Peak memory 649528 kb
Host smart-26850625-4b69-4542-9d68-3823b6c7e44b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1160060458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.1160060458
Directory /workspace/53.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/54.chip_sw_all_escalation_resets.3058847008
Short name T743
Test name
Test status
Simulation time 5524385632 ps
CPU time 608.27 seconds
Started Aug 08 08:53:30 PM PDT 24
Finished Aug 08 09:03:38 PM PDT 24
Peak memory 649924 kb
Host smart-8bdab544-35a0-42b2-90de-67e8a7b9857f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3058847008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.3058847008
Directory /workspace/54.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.951733122
Short name T769
Test name
Test status
Simulation time 3510396640 ps
CPU time 343.08 seconds
Started Aug 08 08:54:55 PM PDT 24
Finished Aug 08 09:00:38 PM PDT 24
Peak memory 648732 kb
Host smart-75092596-c992-45a9-8cc1-93c789d06ee1
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951733122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_s
w_alert_handler_lpg_sleep_mode_alerts.951733122
Directory /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/56.chip_sw_all_escalation_resets.4176007080
Short name T242
Test name
Test status
Simulation time 4327986460 ps
CPU time 492.57 seconds
Started Aug 08 08:54:56 PM PDT 24
Finished Aug 08 09:03:09 PM PDT 24
Peak memory 650264 kb
Host smart-a53fcff1-4538-462c-8687-4eac947c59cf
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4176007080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.4176007080
Directory /workspace/56.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/57.chip_sw_all_escalation_resets.1905739837
Short name T333
Test name
Test status
Simulation time 6325756960 ps
CPU time 765.51 seconds
Started Aug 08 08:55:24 PM PDT 24
Finished Aug 08 09:08:10 PM PDT 24
Peak memory 649564 kb
Host smart-2635abbb-9aec-4b1a-804f-82a12b78e052
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1905739837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.1905739837
Directory /workspace/57.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.441654620
Short name T737
Test name
Test status
Simulation time 3537358052 ps
CPU time 311.15 seconds
Started Aug 08 08:54:38 PM PDT 24
Finished Aug 08 08:59:49 PM PDT 24
Peak memory 648476 kb
Host smart-6a020a77-b0de-446c-bc85-0c1bcdc521a9
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441654620 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_s
w_alert_handler_lpg_sleep_mode_alerts.441654620
Directory /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/60.chip_sw_all_escalation_resets.4174556798
Short name T710
Test name
Test status
Simulation time 5898310270 ps
CPU time 605.61 seconds
Started Aug 08 08:55:53 PM PDT 24
Finished Aug 08 09:05:59 PM PDT 24
Peak memory 649796 kb
Host smart-502f3350-245c-4aae-b675-08970a61da88
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4174556798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.4174556798
Directory /workspace/60.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/61.chip_sw_all_escalation_resets.743528815
Short name T766
Test name
Test status
Simulation time 6521169320 ps
CPU time 585.62 seconds
Started Aug 08 08:55:38 PM PDT 24
Finished Aug 08 09:05:24 PM PDT 24
Peak memory 649732 kb
Host smart-19999a67-0d49-4550-8d93-070a2a2a63c7
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
743528815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.743528815
Directory /workspace/61.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.300229453
Short name T685
Test name
Test status
Simulation time 4162073660 ps
CPU time 451.19 seconds
Started Aug 08 08:55:45 PM PDT 24
Finished Aug 08 09:03:16 PM PDT 24
Peak memory 648780 kb
Host smart-44d2f7a4-96b1-41f4-af28-511e668a750e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300229453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_s
w_alert_handler_lpg_sleep_mode_alerts.300229453
Directory /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/63.chip_sw_all_escalation_resets.2896354565
Short name T731
Test name
Test status
Simulation time 4565838692 ps
CPU time 489.2 seconds
Started Aug 08 08:55:11 PM PDT 24
Finished Aug 08 09:03:20 PM PDT 24
Peak memory 650248 kb
Host smart-4e2062e8-7f2a-45d2-9c2a-fcf00ef633d7
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2896354565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.2896354565
Directory /workspace/63.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.4182198815
Short name T751
Test name
Test status
Simulation time 3332826268 ps
CPU time 350.73 seconds
Started Aug 08 08:55:21 PM PDT 24
Finished Aug 08 09:01:12 PM PDT 24
Peak memory 648932 kb
Host smart-bb85c483-ddd9-4417-a7c0-d63a2d1f1046
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182198815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4182198815
Directory /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3853068633
Short name T714
Test name
Test status
Simulation time 3785833722 ps
CPU time 408.05 seconds
Started Aug 08 08:56:39 PM PDT 24
Finished Aug 08 09:03:27 PM PDT 24
Peak memory 648568 kb
Host smart-4ec4f2ab-c823-4fc4-b753-a897f5681c6b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853068633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3853068633
Directory /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.833951807
Short name T678
Test name
Test status
Simulation time 4210535996 ps
CPU time 395.99 seconds
Started Aug 08 08:56:09 PM PDT 24
Finished Aug 08 09:02:45 PM PDT 24
Peak memory 648328 kb
Host smart-2bb7421a-5ddf-4c31-98a7-25431ead2fa6
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833951807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_s
w_alert_handler_lpg_sleep_mode_alerts.833951807
Directory /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/73.chip_sw_all_escalation_resets.2869063144
Short name T703
Test name
Test status
Simulation time 5091894104 ps
CPU time 561.11 seconds
Started Aug 08 08:55:22 PM PDT 24
Finished Aug 08 09:04:43 PM PDT 24
Peak memory 649856 kb
Host smart-5a312f56-95ee-4c1d-bbe9-0e68d4f3aa2c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2869063144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.2869063144
Directory /workspace/73.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/79.chip_sw_all_escalation_resets.1191403146
Short name T704
Test name
Test status
Simulation time 5197060170 ps
CPU time 556.52 seconds
Started Aug 08 08:56:52 PM PDT 24
Finished Aug 08 09:06:09 PM PDT 24
Peak memory 649896 kb
Host smart-6cf72c4e-5ab1-4021-b346-3e9461653798
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1191403146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.1191403146
Directory /workspace/79.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/8.chip_sw_all_escalation_resets.3895647680
Short name T220
Test name
Test status
Simulation time 5413942244 ps
CPU time 608.69 seconds
Started Aug 08 08:50:01 PM PDT 24
Finished Aug 08 09:00:09 PM PDT 24
Peak memory 649776 kb
Host smart-e5153687-6c70-48a3-affa-71f936ef1564
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3895647680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.3895647680
Directory /workspace/8.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1736982302
Short name T728
Test name
Test status
Simulation time 4376326040 ps
CPU time 454.45 seconds
Started Aug 08 08:58:04 PM PDT 24
Finished Aug 08 09:05:39 PM PDT 24
Peak memory 648980 kb
Host smart-340fad30-adb8-4961-b6b3-b4b48c9967ca
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736982302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1736982302
Directory /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3686411964
Short name T662
Test name
Test status
Simulation time 3692044536 ps
CPU time 336.44 seconds
Started Aug 08 08:58:09 PM PDT 24
Finished Aug 08 09:03:45 PM PDT 24
Peak memory 648352 kb
Host smart-2c9b3b64-aabe-47a2-8a4d-27ada3afe052
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686411964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3686411964
Directory /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2621034512
Short name T718
Test name
Test status
Simulation time 4322743218 ps
CPU time 561.54 seconds
Started Aug 08 08:49:15 PM PDT 24
Finished Aug 08 08:58:37 PM PDT 24
Peak memory 648924 kb
Host smart-acf4bdca-4f5e-4b8d-8fa3-91dd056ad377
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621034512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s
w_alert_handler_lpg_sleep_mode_alerts.2621034512
Directory /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/98.chip_sw_all_escalation_resets.3115916619
Short name T677
Test name
Test status
Simulation time 5064147528 ps
CPU time 638.86 seconds
Started Aug 08 08:58:33 PM PDT 24
Finished Aug 08 09:09:12 PM PDT 24
Peak memory 649484 kb
Host smart-d676c705-eec1-4c25-9a53-60a2f6d22bd4
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3115916619 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.3115916619
Directory /workspace/98.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all.2749501017
Short name T498
Test name
Test status
Simulation time 8447790470 ps
CPU time 305.41 seconds
Started Aug 08 07:56:04 PM PDT 24
Finished Aug 08 08:01:10 PM PDT 24
Peak memory 576268 kb
Host smart-afcbe75d-43ab-450a-b2f1-fee33449b04b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749501017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2749501017
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1368005249
Short name T344
Test name
Test status
Simulation time 6489634592 ps
CPU time 466.69 seconds
Started Aug 08 08:20:56 PM PDT 24
Finished Aug 08 08:28:43 PM PDT 24
Peak memory 611008 kb
Host smart-022b5aba-d1b7-4319-9f06-f0617648f3f7
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul
es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1368005249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s
leep_wake_up.1368005249
Directory /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx.2953794827
Short name T330
Test name
Test status
Simulation time 4403480644 ps
CPU time 682.09 seconds
Started Aug 08 08:18:55 PM PDT 24
Finished Aug 08 08:30:19 PM PDT 24
Peak memory 623848 kb
Host smart-0081ebc7-9080-4303-9ff8-8c5a1d2b6022
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953794827 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.2953794827
Directory /workspace/0.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/10.chip_sw_all_escalation_resets.3150299888
Short name T635
Test name
Test status
Simulation time 5075910156 ps
CPU time 693.25 seconds
Started Aug 08 08:51:20 PM PDT 24
Finished Aug 08 09:02:54 PM PDT 24
Peak memory 611112 kb
Host smart-78e83097-fa5d-48eb-b557-7e0564b5e551
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3150299888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.3150299888
Directory /workspace/10.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1800347619
Short name T203
Test name
Test status
Simulation time 4033428832 ps
CPU time 463.41 seconds
Started Aug 08 08:16:07 PM PDT 24
Finished Aug 08 08:23:50 PM PDT 24
Peak memory 624752 kb
Host smart-7fd444e5-caf8-497f-8e6b-0d76046fa183
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800347619 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.1800347619
Directory /workspace/0.chip_sw_spi_device_pass_through_collision/latest

Test location /workspace/coverage/default/0.chip_sw_flash_init.405204683
Short name T281
Test name
Test status
Simulation time 19796754060 ps
CPU time 2241.64 seconds
Started Aug 08 08:15:13 PM PDT 24
Finished Aug 08 08:52:35 PM PDT 24
Peak memory 612060 kb
Host smart-a5c1be99-11b6-4e7a-aa63-fb8224801201
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405204683 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.405204683
Directory /workspace/0.chip_sw_flash_init/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1987618149
Short name T146
Test name
Test status
Simulation time 6731140960 ps
CPU time 551.55 seconds
Started Aug 08 08:15:23 PM PDT 24
Finished Aug 08 08:24:35 PM PDT 24
Peak memory 610832 kb
Host smart-6a55f58b-9932-4a0b-afc2-30cf30a6086e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987618149 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.1987618149
Directory /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.4164697396
Short name T210
Test name
Test status
Simulation time 4443982467 ps
CPU time 419.71 seconds
Started Aug 08 08:15:18 PM PDT 24
Finished Aug 08 08:22:19 PM PDT 24
Peak memory 613680 kb
Host smart-850c9cca-d996-4b3b-938b-399a0794642d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164697396 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.4164697396
Directory /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3475576793
Short name T162
Test name
Test status
Simulation time 2135577727 ps
CPU time 92.7 seconds
Started Aug 08 08:35:29 PM PDT 24
Finished Aug 08 08:37:01 PM PDT 24
Peak memory 621692 kb
Host smart-bba4298a-f2c1-4e21-bcc9-02effaf80f7a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475576793 -assert nopost
proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.3475576793
Directory /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3855975859
Short name T134
Test name
Test status
Simulation time 4226817284 ps
CPU time 212.9 seconds
Started Aug 08 07:50:26 PM PDT 24
Finished Aug 08 07:53:59 PM PDT 24
Peak memory 659648 kb
Host smart-16ca0ed3-9df3-46b5-860a-ab17535519af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855975859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r
eset.3855975859
Directory /workspace/4.chip_csr_hw_reset/latest

Test location /workspace/coverage/default/1.chip_tap_straps_dev.567001475
Short name T630
Test name
Test status
Simulation time 7349446117 ps
CPU time 908.37 seconds
Started Aug 08 08:32:37 PM PDT 24
Finished Aug 08 08:47:46 PM PDT 24
Peak memory 620948 kb
Host smart-5c2789fb-40b6-48bb-bf5f-ae24a3582985
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=567001475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.567001475
Directory /workspace/1.chip_tap_straps_dev/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.1560825460
Short name T1989
Test name
Test status
Simulation time 65260213323 ps
CPU time 735.48 seconds
Started Aug 08 07:52:24 PM PDT 24
Finished Aug 08 08:04:39 PM PDT 24
Peak memory 575916 kb
Host smart-e296b9f7-5789-40e3-9ae5-354a4691b9f6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560825460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1560825460
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/8.chip_tl_errors.87483581
Short name T535
Test name
Test status
Simulation time 4200895885 ps
CPU time 288.61 seconds
Started Aug 08 07:50:39 PM PDT 24
Finished Aug 08 07:55:28 PM PDT 24
Peak memory 598744 kb
Host smart-d391062e-a9e2-40ab-9d9b-9f60d87a45d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87483581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.87483581
Directory /workspace/8.chip_tl_errors/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3086532784
Short name T324
Test name
Test status
Simulation time 3836662816 ps
CPU time 380.49 seconds
Started Aug 08 08:20:12 PM PDT 24
Finished Aug 08 08:26:33 PM PDT 24
Peak memory 609788 kb
Host smart-2b1386df-26e3-4c01-a2b7-8a253e6f83af
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086532784 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.3086532784
Directory /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1922988858
Short name T244
Test name
Test status
Simulation time 4764719248 ps
CPU time 750.85 seconds
Started Aug 08 08:25:19 PM PDT 24
Finished Aug 08 08:37:50 PM PDT 24
Peak memory 609884 kb
Host smart-3b5a97e3-1815-47f1-ab8a-aa259ffec4d7
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922988858
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.1922988858
Directory /workspace/1.chip_sw_flash_ctrl_ops/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3673615190
Short name T305
Test name
Test status
Simulation time 5128669100 ps
CPU time 776.84 seconds
Started Aug 08 08:35:06 PM PDT 24
Finished Aug 08 08:48:03 PM PDT 24
Peak memory 609452 kb
Host smart-259dcd65-4041-4d47-b50e-fedb136ce5dc
User root
Command /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673615190 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.3673615190
Directory /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest

Test location /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2847851792
Short name T1058
Test name
Test status
Simulation time 19217827000 ps
CPU time 480.42 seconds
Started Aug 08 08:16:38 PM PDT 24
Finished Aug 08 08:24:39 PM PDT 24
Peak memory 619736 kb
Host smart-af912cee-9694-4994-90e4-0227e2ce3f42
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2847851792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2847851792
Directory /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_idle.4010307652
Short name T928
Test name
Test status
Simulation time 2956497388 ps
CPU time 295.01 seconds
Started Aug 08 08:20:25 PM PDT 24
Finished Aug 08 08:25:20 PM PDT 24
Peak memory 609672 kb
Host smart-e3001850-83f3-4700-82c8-cc651c4eb10b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010307652 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_kmac_idle.4010307652
Directory /workspace/0.chip_sw_kmac_idle/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_irq.4032029703
Short name T342
Test name
Test status
Simulation time 4367197392 ps
CPU time 439.57 seconds
Started Aug 08 08:27:23 PM PDT 24
Finished Aug 08 08:34:43 PM PDT 24
Peak memory 609288 kb
Host smart-02f18c1a-f429-4191-813b-cd670c0d7485
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032029703 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.4032029703
Directory /workspace/1.chip_sw_aon_timer_irq/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2829361168
Short name T272
Test name
Test status
Simulation time 8134064720 ps
CPU time 1100.97 seconds
Started Aug 08 08:18:55 PM PDT 24
Finished Aug 08 08:37:17 PM PDT 24
Peak memory 610732 kb
Host smart-9af29832-9add-4a73-a971-83391bc974a9
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282936
1168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.2829361168
Directory /workspace/0.chip_sw_keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1432894194
Short name T168
Test name
Test status
Simulation time 5254946200 ps
CPU time 565.19 seconds
Started Aug 08 08:20:34 PM PDT 24
Finished Aug 08 08:30:00 PM PDT 24
Peak memory 610836 kb
Host smart-b6fc8dee-9391-4253-a70e-58c6a948a0ed
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1432894194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.1432894194
Directory /workspace/0.chip_sw_lc_ctrl_program_error/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2579496505
Short name T999
Test name
Test status
Simulation time 6521207576 ps
CPU time 405.31 seconds
Started Aug 08 08:16:11 PM PDT 24
Finished Aug 08 08:22:57 PM PDT 24
Peak memory 616408 kb
Host smart-341ad577-68a3-447d-b0a0-03b9fdf502fc
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2579496505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2579496505
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2203572110
Short name T612
Test name
Test status
Simulation time 30770486976 ps
CPU time 5598.5 seconds
Started Aug 08 08:34:42 PM PDT 24
Finished Aug 08 10:08:01 PM PDT 24
Peak memory 610324 kb
Host smart-20f5e23f-8123-4f63-84b0-8f4dcdedcdca
User root
Command /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_
cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2203572110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.2203572110
Directory /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1318030276
Short name T585
Test name
Test status
Simulation time 531837755 ps
CPU time 180.65 seconds
Started Aug 08 07:49:57 PM PDT 24
Finished Aug 08 07:52:58 PM PDT 24
Peak memory 576684 kb
Host smart-bf571abc-01a5-4581-bab1-6a3b93914147
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318030276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all
_with_reset_error.1318030276
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_error_random.1301963669
Short name T641
Test name
Test status
Simulation time 2337431689 ps
CPU time 80.07 seconds
Started Aug 08 07:55:56 PM PDT 24
Finished Aug 08 07:57:16 PM PDT 24
Peak memory 575712 kb
Host smart-5be9718a-1ac6-451a-87d6-08dd3e483ce2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301963669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1301963669
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.4254241195
Short name T640
Test name
Test status
Simulation time 5577353065 ps
CPU time 409.68 seconds
Started Aug 08 07:58:45 PM PDT 24
Finished Aug 08 08:05:34 PM PDT 24
Peak memory 576760 kb
Host smart-7ef51555-d044-42a8-b486-fac063174e2e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254241195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.4254241195
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.1628948119
Short name T597
Test name
Test status
Simulation time 9677553970 ps
CPU time 330.66 seconds
Started Aug 08 08:01:32 PM PDT 24
Finished Aug 08 08:07:02 PM PDT 24
Peak memory 576128 kb
Host smart-b4bb8621-6c93-4177-85f7-11d1399f581f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628948119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.1628948119
Directory /workspace/58.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.3728084734
Short name T639
Test name
Test status
Simulation time 5381729166 ps
CPU time 173.67 seconds
Started Aug 08 07:51:01 PM PDT 24
Finished Aug 08 07:53:55 PM PDT 24
Peak memory 576084 kb
Host smart-fcb0ebd9-32a4-4963-bc7d-e85848845d8d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728084734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3728084734
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.4179229383
Short name T588
Test name
Test status
Simulation time 14005323981 ps
CPU time 526.96 seconds
Started Aug 08 08:07:07 PM PDT 24
Finished Aug 08 08:15:54 PM PDT 24
Peak memory 575908 kb
Host smart-4c7c545c-11ca-4605-a49e-b2ad5f6ab638
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179229383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.4179229383
Directory /workspace/92.xbar_stress_all_with_error/latest

Test location /workspace/coverage/default/0.chip_sw_gpio.2648734561
Short name T28
Test name
Test status
Simulation time 3646740239 ps
CPU time 371.85 seconds
Started Aug 08 08:15:29 PM PDT 24
Finished Aug 08 08:21:41 PM PDT 24
Peak memory 609292 kb
Host smart-00c07701-ce65-496a-8fbb-4b4ad0ee604b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648734561 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.chip_sw_gpio.2648734561
Directory /workspace/0.chip_sw_gpio/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2881154566
Short name T161
Test name
Test status
Simulation time 10711256996 ps
CPU time 1576.57 seconds
Started Aug 08 08:16:58 PM PDT 24
Finished Aug 08 08:43:15 PM PDT 24
Peak memory 610908 kb
Host smart-0563a617-66de-4393-9d87-acab5ab476dd
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=2881154566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.2881154566
Directory /workspace/0.chip_sw_rstmgr_alert_info/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.843562597
Short name T510
Test name
Test status
Simulation time 4998520608 ps
CPU time 726.02 seconds
Started Aug 08 08:17:37 PM PDT 24
Finished Aug 08 08:29:43 PM PDT 24
Peak memory 610196 kb
Host smart-44e0456b-bbb7-474c-93d5-678a2a99c1ac
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84356
2597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.843562597
Directory /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1612096706
Short name T135
Test name
Test status
Simulation time 4958676850 ps
CPU time 202.24 seconds
Started Aug 08 07:50:10 PM PDT 24
Finished Aug 08 07:53:33 PM PDT 24
Peak memory 662644 kb
Host smart-c5b01242-c59c-4b90-9491-2f93601076e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612096706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r
eset.1612096706
Directory /workspace/1.chip_csr_hw_reset/latest

Test location /workspace/coverage/default/0.chip_sw_edn_boot_mode.707624057
Short name T236
Test name
Test status
Simulation time 3510919750 ps
CPU time 543.4 seconds
Started Aug 08 08:18:23 PM PDT 24
Finished Aug 08 08:27:27 PM PDT 24
Peak memory 610012 kb
Host smart-03fb57f9-4f2c-4ea3-adff-8ef1d1ec7ff3
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707624057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_b
oot_mode.707624057
Directory /workspace/0.chip_sw_edn_boot_mode/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1226228276
Short name T418
Test name
Test status
Simulation time 17259935944 ps
CPU time 3722.1 seconds
Started Aug 08 08:18:26 PM PDT 24
Finished Aug 08 09:20:29 PM PDT 24
Peak memory 610016 kb
Host smart-39cffa9f-7703-46d4-8bb9-baba5e854e58
User root
Command /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_
rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1226228276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.1226228276
Directory /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.552805578
Short name T366
Test name
Test status
Simulation time 3093784162 ps
CPU time 143.05 seconds
Started Aug 08 08:22:37 PM PDT 24
Finished Aug 08 08:25:00 PM PDT 24
Peak memory 616544 kb
Host smart-0b528044-b551-4e04-b894-7f40e9ae5be0
User root
Command /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552805578 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.552805578
Directory /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.637234761
Short name T188
Test name
Test status
Simulation time 5076312986 ps
CPU time 625.48 seconds
Started Aug 08 08:17:38 PM PDT 24
Finished Aug 08 08:28:04 PM PDT 24
Peak memory 610764 kb
Host smart-df8b2406-512f-4db6-899d-8dbc50ba6d5c
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63723
4761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.637234761
Directory /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.68868669
Short name T364
Test name
Test status
Simulation time 24248384460 ps
CPU time 6873.41 seconds
Started Aug 08 08:29:01 PM PDT 24
Finished Aug 08 10:23:36 PM PDT 24
Peak memory 610004 kb
Host smart-dbecbbda-cc9a-48b1-9721-11376cfd1309
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=68868669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.68868669
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.775709684
Short name T509
Test name
Test status
Simulation time 53722347954 ps
CPU time 9894.52 seconds
Started Aug 08 07:49:51 PM PDT 24
Finished Aug 08 10:34:46 PM PDT 24
Peak memory 638632 kb
Host smart-2c0358f7-cb2a-49f9-aba0-84be829ef287
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775709684 -assert nopostproc +UVM_TESTNAME=chip_b
ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.chip_csr_aliasing.775709684
Directory /workspace/0.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.104227543
Short name T2282
Test name
Test status
Simulation time 10859480573 ps
CPU time 932.19 seconds
Started Aug 08 07:49:48 PM PDT 24
Finished Aug 08 08:05:20 PM PDT 24
Peak memory 593496 kb
Host smart-51ed6236-a324-4b8b-8884-a624f24b3782
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104227543 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.104227543
Directory /workspace/0.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1934936964
Short name T622
Test name
Test status
Simulation time 5444670580 ps
CPU time 406.5 seconds
Started Aug 08 07:49:56 PM PDT 24
Finished Aug 08 07:56:43 PM PDT 24
Peak memory 639620 kb
Host smart-21ab394c-3109-4c8c-9e11-3dcd785ffc71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934936964 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.1934936964
Directory /workspace/0.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_rw.2716406623
Short name T2387
Test name
Test status
Simulation time 5671242913 ps
CPU time 529.59 seconds
Started Aug 08 07:50:03 PM PDT 24
Finished Aug 08 07:58:53 PM PDT 24
Peak memory 597356 kb
Host smart-6adca439-d6ba-4320-b170-b0a674a48d13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716406623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.2716406623
Directory /workspace/0.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1185773951
Short name T1351
Test name
Test status
Simulation time 8719897604 ps
CPU time 346.77 seconds
Started Aug 08 07:49:48 PM PDT 24
Finished Aug 08 07:55:35 PM PDT 24
Peak memory 591456 kb
Host smart-12522833-77b5-416b-bb8c-2cc0e209d0dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185773951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.chip_prim_tl_access.1185773951
Directory /workspace/0.chip_prim_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2508862221
Short name T2050
Test name
Test status
Simulation time 5206530414 ps
CPU time 260.63 seconds
Started Aug 08 07:49:55 PM PDT 24
Finished Aug 08 07:54:16 PM PDT 24
Peak memory 592296 kb
Host smart-2754dfee-cf56-42a8-9fb5-184df4db6208
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508862221 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.chip_rv_dm_lc_disabled.2508862221
Directory /workspace/0.chip_rv_dm_lc_disabled/latest

Test location /workspace/coverage/cover_reg_top/0.chip_tl_errors.1424444363
Short name T647
Test name
Test status
Simulation time 5184119848 ps
CPU time 424.64 seconds
Started Aug 08 07:49:53 PM PDT 24
Finished Aug 08 07:56:57 PM PDT 24
Peak memory 598620 kb
Host smart-8373d5f9-6f26-4786-bb8a-69f9c113e4e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424444363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.1424444363
Directory /workspace/0.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_access_same_device.2594419316
Short name T1623
Test name
Test status
Simulation time 1653310819 ps
CPU time 66.27 seconds
Started Aug 08 07:49:56 PM PDT 24
Finished Aug 08 07:51:03 PM PDT 24
Peak memory 575840 kb
Host smart-e5f1d21f-e7f9-4d2a-8799-94e185c05f22
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594419316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.
2594419316
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2210140771
Short name T2902
Test name
Test status
Simulation time 114020850415 ps
CPU time 1907.18 seconds
Started Aug 08 07:49:57 PM PDT 24
Finished Aug 08 08:21:44 PM PDT 24
Peak memory 575912 kb
Host smart-43a32005-f7b6-4007-a6fe-7d67e8865a75
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210140771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d
evice_slow_rsp.2210140771
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1321017730
Short name T619
Test name
Test status
Simulation time 1407344999 ps
CPU time 51.79 seconds
Started Aug 08 07:49:55 PM PDT 24
Finished Aug 08 07:50:47 PM PDT 24
Peak memory 575864 kb
Host smart-cb2579f7-3b5e-4855-b43a-f2cda548994e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321017730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr
.1321017730
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_error_random.1619864238
Short name T2690
Test name
Test status
Simulation time 338486669 ps
CPU time 27.97 seconds
Started Aug 08 07:50:03 PM PDT 24
Finished Aug 08 07:50:31 PM PDT 24
Peak memory 575896 kb
Host smart-173ee5bc-5a8f-43d0-be67-72fc558f3c83
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619864238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1619864238
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random.3124694689
Short name T2308
Test name
Test status
Simulation time 1423269078 ps
CPU time 49.24 seconds
Started Aug 08 07:49:56 PM PDT 24
Finished Aug 08 07:50:46 PM PDT 24
Peak memory 575896 kb
Host smart-9a1be333-dbd3-49f7-9579-e61c46235547
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124694689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.3124694689
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1130924057
Short name T1735
Test name
Test status
Simulation time 108106368351 ps
CPU time 1079.13 seconds
Started Aug 08 07:49:57 PM PDT 24
Finished Aug 08 08:07:56 PM PDT 24
Peak memory 576748 kb
Host smart-21669665-c590-49c4-8d83-e3ce34f42c0c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130924057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1130924057
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1443522862
Short name T2122
Test name
Test status
Simulation time 50580009556 ps
CPU time 803.96 seconds
Started Aug 08 07:50:02 PM PDT 24
Finished Aug 08 08:03:26 PM PDT 24
Peak memory 575868 kb
Host smart-ea188ad5-cb36-4bef-9613-f4b3b82203bb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443522862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1443522862
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2138175564
Short name T2862
Test name
Test status
Simulation time 417992375 ps
CPU time 33.56 seconds
Started Aug 08 07:50:03 PM PDT 24
Finished Aug 08 07:50:37 PM PDT 24
Peak memory 575824 kb
Host smart-a1169ac9-a5b2-4d6b-9aff-7a7b2447ffac
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138175564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela
ys.2138175564
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_same_source.3212125676
Short name T1968
Test name
Test status
Simulation time 2549016812 ps
CPU time 71.53 seconds
Started Aug 08 07:50:01 PM PDT 24
Finished Aug 08 07:51:13 PM PDT 24
Peak memory 575708 kb
Host smart-f7e00b45-47fb-4c06-8620-6e748f29c4b5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212125676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3212125676
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke.224235315
Short name T2036
Test name
Test status
Simulation time 60636072 ps
CPU time 7.16 seconds
Started Aug 08 07:49:48 PM PDT 24
Finished Aug 08 07:49:55 PM PDT 24
Peak memory 573780 kb
Host smart-44cb6860-7481-4148-9778-abfcda966e30
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224235315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.224235315
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2486606998
Short name T1413
Test name
Test status
Simulation time 6636528285 ps
CPU time 67.98 seconds
Started Aug 08 07:49:57 PM PDT 24
Finished Aug 08 07:51:05 PM PDT 24
Peak memory 574488 kb
Host smart-ef576fb6-d32a-48e6-8fc0-22c5f8ae6d13
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486606998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2486606998
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.669174151
Short name T2538
Test name
Test status
Simulation time 3919780426 ps
CPU time 63.19 seconds
Started Aug 08 07:50:01 PM PDT 24
Finished Aug 08 07:51:05 PM PDT 24
Peak memory 573776 kb
Host smart-12f28cba-bffd-4a07-a580-65f60f3fda56
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669174151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.669174151
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2589645103
Short name T1652
Test name
Test status
Simulation time 53010829 ps
CPU time 6.62 seconds
Started Aug 08 07:49:56 PM PDT 24
Finished Aug 08 07:50:03 PM PDT 24
Peak memory 574492 kb
Host smart-989a35d1-5efd-40f8-94bf-42d4f85da2da
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589645103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays
.2589645103
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all.3508419221
Short name T1667
Test name
Test status
Simulation time 1146150858 ps
CPU time 105.92 seconds
Started Aug 08 07:50:01 PM PDT 24
Finished Aug 08 07:51:47 PM PDT 24
Peak memory 575932 kb
Host smart-c34f5f72-cfb1-4eb6-bea4-a532c31e58f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508419221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3508419221
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3599855038
Short name T794
Test name
Test status
Simulation time 16332403711 ps
CPU time 552.6 seconds
Started Aug 08 07:49:55 PM PDT 24
Finished Aug 08 07:59:08 PM PDT 24
Peak memory 576124 kb
Host smart-34b641c4-1b20-49b8-9b7c-fe952bb9bc3b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599855038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3599855038
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1092801157
Short name T2834
Test name
Test status
Simulation time 4981425331 ps
CPU time 535.97 seconds
Started Aug 08 07:49:59 PM PDT 24
Finished Aug 08 07:58:55 PM PDT 24
Peak memory 576792 kb
Host smart-a4c3b082-2f03-4b97-914e-db332499abb8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092801157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_
with_rand_reset.1092801157
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1483367391
Short name T2493
Test name
Test status
Simulation time 350835314 ps
CPU time 15.77 seconds
Started Aug 08 07:50:00 PM PDT 24
Finished Aug 08 07:50:16 PM PDT 24
Peak memory 575868 kb
Host smart-b0872137-316d-4f41-96c4-64be02cbcaff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483367391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1483367391
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.1933397105
Short name T386
Test name
Test status
Simulation time 33207584324 ps
CPU time 6095.58 seconds
Started Aug 08 07:50:00 PM PDT 24
Finished Aug 08 09:31:37 PM PDT 24
Peak memory 593544 kb
Host smart-8c686fb6-a177-4b7b-87e6-95e17ef750f5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933397105 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.chip_csr_aliasing.1933397105
Directory /workspace/1.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3837127818
Short name T1835
Test name
Test status
Simulation time 42491662480 ps
CPU time 5510.85 seconds
Started Aug 08 07:50:00 PM PDT 24
Finished Aug 08 09:21:51 PM PDT 24
Peak memory 592704 kb
Host smart-0f419a10-1401-4baa-9356-93b43339628c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837127818 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.3837127818
Directory /workspace/1.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.669651596
Short name T623
Test name
Test status
Simulation time 12911158220 ps
CPU time 880.92 seconds
Started Aug 08 07:50:11 PM PDT 24
Finished Aug 08 08:04:52 PM PDT 24
Peak memory 651940 kb
Host smart-a8bfdd90-6983-4bcc-ae5b-312562dece73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669651596 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.669651596
Directory /workspace/1.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_rw.2792541843
Short name T2607
Test name
Test status
Simulation time 5513810472 ps
CPU time 518.88 seconds
Started Aug 08 07:50:12 PM PDT 24
Finished Aug 08 07:58:51 PM PDT 24
Peak memory 598468 kb
Host smart-4caadd10-34f8-446b-b454-15ec32a28abd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792541843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.2792541843
Directory /workspace/1.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.4033940051
Short name T2255
Test name
Test status
Simulation time 6631498370 ps
CPU time 279.64 seconds
Started Aug 08 07:50:02 PM PDT 24
Finished Aug 08 07:54:41 PM PDT 24
Peak memory 589924 kb
Host smart-eb6ea221-b98d-44b8-b76b-5a68e224888e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033940051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.chip_prim_tl_access.4033940051
Directory /workspace/1.chip_prim_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3621506427
Short name T2520
Test name
Test status
Simulation time 14829656072 ps
CPU time 501.73 seconds
Started Aug 08 07:49:58 PM PDT 24
Finished Aug 08 07:58:19 PM PDT 24
Peak memory 591444 kb
Host smart-2fcf6a2e-ffe9-48ed-9e44-ef5f1543386a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621506427 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.chip_rv_dm_lc_disabled.3621506427
Directory /workspace/1.chip_rv_dm_lc_disabled/latest

Test location /workspace/coverage/cover_reg_top/1.chip_tl_errors.1948886364
Short name T421
Test name
Test status
Simulation time 3443530960 ps
CPU time 165.54 seconds
Started Aug 08 07:49:59 PM PDT 24
Finished Aug 08 07:52:45 PM PDT 24
Peak memory 598676 kb
Host smart-37dc86a6-f37a-42d8-9fcc-9ecd5fbdf0a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948886364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.1948886364
Directory /workspace/1.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_access_same_device.2697114489
Short name T2280
Test name
Test status
Simulation time 2666791036 ps
CPU time 119.47 seconds
Started Aug 08 07:50:01 PM PDT 24
Finished Aug 08 07:52:01 PM PDT 24
Peak memory 575816 kb
Host smart-34e21f5a-b6dd-42b9-9c27-16078c969376
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697114489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.
2697114489
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2489481367
Short name T1912
Test name
Test status
Simulation time 92657374664 ps
CPU time 1726.03 seconds
Started Aug 08 07:50:01 PM PDT 24
Finished Aug 08 08:18:48 PM PDT 24
Peak memory 576040 kb
Host smart-3aba8688-c6fe-4b75-ad24-bf01a971e361
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489481367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d
evice_slow_rsp.2489481367
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3773152217
Short name T1372
Test name
Test status
Simulation time 138370750 ps
CPU time 8.35 seconds
Started Aug 08 07:49:59 PM PDT 24
Finished Aug 08 07:50:07 PM PDT 24
Peak memory 574432 kb
Host smart-3d853cbd-79cc-4013-b0f7-9c66db0bd099
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773152217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr
.3773152217
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_error_random.2684314025
Short name T2757
Test name
Test status
Simulation time 1498910209 ps
CPU time 51.29 seconds
Started Aug 08 07:49:59 PM PDT 24
Finished Aug 08 07:50:50 PM PDT 24
Peak memory 575704 kb
Host smart-afdbe049-f301-4b5a-bbc1-df3d3d6ccc38
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684314025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2684314025
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random.1311940516
Short name T443
Test name
Test status
Simulation time 1093049797 ps
CPU time 34.34 seconds
Started Aug 08 07:50:01 PM PDT 24
Finished Aug 08 07:50:35 PM PDT 24
Peak memory 575932 kb
Host smart-4d1c2ade-c5f8-4709-97cd-9e08204489fa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311940516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.1311940516
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3776091400
Short name T2104
Test name
Test status
Simulation time 79773871071 ps
CPU time 736.49 seconds
Started Aug 08 07:49:56 PM PDT 24
Finished Aug 08 08:02:13 PM PDT 24
Peak memory 576060 kb
Host smart-390dc7fa-f97f-4553-9fa2-dbf34e082ff5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776091400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3776091400
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3088701449
Short name T2090
Test name
Test status
Simulation time 38628489047 ps
CPU time 660.53 seconds
Started Aug 08 07:49:56 PM PDT 24
Finished Aug 08 08:00:57 PM PDT 24
Peak memory 575988 kb
Host smart-7fc2ab6b-e44e-4bfa-94a7-280f81f09d67
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088701449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3088701449
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.308474446
Short name T2200
Test name
Test status
Simulation time 368850501 ps
CPU time 30.78 seconds
Started Aug 08 07:50:00 PM PDT 24
Finished Aug 08 07:50:31 PM PDT 24
Peak memory 575892 kb
Host smart-8cd7141e-6666-4e13-a1d9-504e4ccd65f1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308474446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delay
s.308474446
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_same_source.3592647280
Short name T2420
Test name
Test status
Simulation time 2496376441 ps
CPU time 70.86 seconds
Started Aug 08 07:49:57 PM PDT 24
Finished Aug 08 07:51:08 PM PDT 24
Peak memory 575952 kb
Host smart-04e9b1f5-b495-48fd-8d5e-6e2a4471b134
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592647280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3592647280
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke.2396360909
Short name T2636
Test name
Test status
Simulation time 187988725 ps
CPU time 8.27 seconds
Started Aug 08 07:50:03 PM PDT 24
Finished Aug 08 07:50:12 PM PDT 24
Peak memory 573812 kb
Host smart-c6f97580-5cd5-420f-8649-08c03f7e6a11
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396360909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2396360909
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1166213496
Short name T1860
Test name
Test status
Simulation time 8947586666 ps
CPU time 88.26 seconds
Started Aug 08 07:50:02 PM PDT 24
Finished Aug 08 07:51:30 PM PDT 24
Peak memory 573860 kb
Host smart-63798695-6a51-4469-8b2f-5815d5ecb42c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166213496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1166213496
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.145300889
Short name T2852
Test name
Test status
Simulation time 5434113430 ps
CPU time 88.23 seconds
Started Aug 08 07:49:59 PM PDT 24
Finished Aug 08 07:51:28 PM PDT 24
Peak memory 573920 kb
Host smart-eb4c784b-fb64-4d3b-ad67-c1473d436636
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145300889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.145300889
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3323404671
Short name T2044
Test name
Test status
Simulation time 54747359 ps
CPU time 6.17 seconds
Started Aug 08 07:49:59 PM PDT 24
Finished Aug 08 07:50:05 PM PDT 24
Peak memory 574544 kb
Host smart-7d58f8e3-6676-4dff-b4a9-182a61399602
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323404671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays
.3323404671
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all.2470682058
Short name T528
Test name
Test status
Simulation time 6323611988 ps
CPU time 198.41 seconds
Started Aug 08 07:49:55 PM PDT 24
Finished Aug 08 07:53:13 PM PDT 24
Peak memory 576564 kb
Host smart-c3e91b87-91ab-4b14-ac12-796519516d88
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470682058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2470682058
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.521906016
Short name T1677
Test name
Test status
Simulation time 10213099923 ps
CPU time 328.08 seconds
Started Aug 08 07:49:58 PM PDT 24
Finished Aug 08 07:55:26 PM PDT 24
Peak memory 576116 kb
Host smart-ab994986-1438-4e9b-bec2-b1e3d1c22530
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521906016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.521906016
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3578398402
Short name T2595
Test name
Test status
Simulation time 398496627 ps
CPU time 93.43 seconds
Started Aug 08 07:49:56 PM PDT 24
Finished Aug 08 07:51:29 PM PDT 24
Peak memory 576636 kb
Host smart-e86786fc-8a26-4317-a343-7269d596adee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578398402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_
with_rand_reset.3578398402
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3381967531
Short name T517
Test name
Test status
Simulation time 1478274017 ps
CPU time 145.73 seconds
Started Aug 08 07:50:01 PM PDT 24
Finished Aug 08 07:52:27 PM PDT 24
Peak memory 576732 kb
Host smart-4b827b80-aef5-47c1-a0cc-24a3438abae0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381967531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all
_with_reset_error.3381967531
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2940888233
Short name T2452
Test name
Test status
Simulation time 166910765 ps
CPU time 20.6 seconds
Started Aug 08 07:50:01 PM PDT 24
Finished Aug 08 07:50:22 PM PDT 24
Peak memory 575864 kb
Host smart-66969801-b8e0-4b2b-aa04-9763c8a46899
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940888233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2940888233
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3924454151
Short name T2324
Test name
Test status
Simulation time 10950839730 ps
CPU time 633.42 seconds
Started Aug 08 07:51:36 PM PDT 24
Finished Aug 08 08:02:10 PM PDT 24
Peak memory 652836 kb
Host smart-205f4f45-395a-4d10-8f58-b2e0b86db40d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924454151 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.3924454151
Directory /workspace/10.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.chip_csr_rw.2006844293
Short name T1957
Test name
Test status
Simulation time 4648579925 ps
CPU time 302.15 seconds
Started Aug 08 07:51:40 PM PDT 24
Finished Aug 08 07:56:42 PM PDT 24
Peak memory 598432 kb
Host smart-4e8fd3e9-6aa2-43aa-879e-76c70b792a5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006844293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.2006844293
Directory /workspace/10.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2149852725
Short name T2649
Test name
Test status
Simulation time 27655603200 ps
CPU time 4597.24 seconds
Started Aug 08 07:51:27 PM PDT 24
Finished Aug 08 09:08:05 PM PDT 24
Peak memory 593308 kb
Host smart-50b52f7f-2abe-46fe-9d15-389674a51c43
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149852725 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.2149852725
Directory /workspace/10.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_access_same_device.968865423
Short name T2014
Test name
Test status
Simulation time 2445661193 ps
CPU time 87.62 seconds
Started Aug 08 07:51:39 PM PDT 24
Finished Aug 08 07:53:06 PM PDT 24
Peak memory 575984 kb
Host smart-1f42017a-5b19-4cd7-a86e-8416abd04d74
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968865423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.
968865423
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3155449639
Short name T2616
Test name
Test status
Simulation time 151693528572 ps
CPU time 2797.55 seconds
Started Aug 08 07:51:31 PM PDT 24
Finished Aug 08 08:38:09 PM PDT 24
Peak memory 575984 kb
Host smart-98542404-8b2b-491e-a3e4-830bdd91f432
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155449639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_
device_slow_rsp.3155449639
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.806915738
Short name T2660
Test name
Test status
Simulation time 1252371514 ps
CPU time 43.3 seconds
Started Aug 08 07:51:37 PM PDT 24
Finished Aug 08 07:52:20 PM PDT 24
Peak memory 575896 kb
Host smart-4db86a1f-cf49-4f50-96e6-25620a622345
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806915738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr
.806915738
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_error_random.35154783
Short name T2504
Test name
Test status
Simulation time 903986530 ps
CPU time 29.76 seconds
Started Aug 08 07:51:37 PM PDT 24
Finished Aug 08 07:52:07 PM PDT 24
Peak memory 575600 kb
Host smart-b5d4bf6a-2196-4491-9e6f-69aefeb1a72f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35154783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.35154783
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random.1274560107
Short name T553
Test name
Test status
Simulation time 719607094 ps
CPU time 26.1 seconds
Started Aug 08 07:51:30 PM PDT 24
Finished Aug 08 07:51:56 PM PDT 24
Peak memory 574604 kb
Host smart-a102e37c-138b-474c-9c01-99debeec18fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274560107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.1274560107
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2347859995
Short name T2298
Test name
Test status
Simulation time 63418248094 ps
CPU time 658.16 seconds
Started Aug 08 07:51:27 PM PDT 24
Finished Aug 08 08:02:25 PM PDT 24
Peak memory 575984 kb
Host smart-b7641ac8-e43f-4509-bdb0-a9eefa4b5f52
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347859995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2347859995
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.520070977
Short name T1881
Test name
Test status
Simulation time 38084050239 ps
CPU time 654.26 seconds
Started Aug 08 07:51:31 PM PDT 24
Finished Aug 08 08:02:25 PM PDT 24
Peak memory 575984 kb
Host smart-0cbc9632-caf2-48c4-aad7-8fe785281850
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520070977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.520070977
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.777486777
Short name T1561
Test name
Test status
Simulation time 562049563 ps
CPU time 43.42 seconds
Started Aug 08 07:51:27 PM PDT 24
Finished Aug 08 07:52:10 PM PDT 24
Peak memory 575864 kb
Host smart-654c8430-d5c7-46ce-b8d3-4c83db971750
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777486777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_dela
ys.777486777
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_same_source.3181631598
Short name T1524
Test name
Test status
Simulation time 375946297 ps
CPU time 27.25 seconds
Started Aug 08 07:51:35 PM PDT 24
Finished Aug 08 07:52:03 PM PDT 24
Peak memory 575860 kb
Host smart-f18e1346-ecaf-4d8c-9e19-8d3d4a3e87c5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181631598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3181631598
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke.3537565918
Short name T1530
Test name
Test status
Simulation time 228657905 ps
CPU time 9.06 seconds
Started Aug 08 07:51:40 PM PDT 24
Finished Aug 08 07:51:49 PM PDT 24
Peak memory 573840 kb
Host smart-734f67bb-7e50-45c9-acc3-e8d6e38da3de
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537565918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3537565918
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1781812873
Short name T2281
Test name
Test status
Simulation time 6800616920 ps
CPU time 66.75 seconds
Started Aug 08 07:51:40 PM PDT 24
Finished Aug 08 07:52:47 PM PDT 24
Peak memory 573860 kb
Host smart-317c080a-3652-41e6-9d0b-a3ebbdc8eeae
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781812873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1781812873
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3529736996
Short name T1494
Test name
Test status
Simulation time 4904542848 ps
CPU time 85.42 seconds
Started Aug 08 07:51:30 PM PDT 24
Finished Aug 08 07:52:55 PM PDT 24
Peak memory 572740 kb
Host smart-5da56c5b-b52f-43ff-9968-547656717d52
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529736996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3529736996
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1469114940
Short name T1784
Test name
Test status
Simulation time 33746879 ps
CPU time 5.3 seconds
Started Aug 08 07:51:39 PM PDT 24
Finished Aug 08 07:51:44 PM PDT 24
Peak memory 574476 kb
Host smart-2d4fbb5d-8325-45a8-8a2c-664221fffbb9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469114940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay
s.1469114940
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all.299027096
Short name T2502
Test name
Test status
Simulation time 3769986439 ps
CPU time 257.83 seconds
Started Aug 08 07:51:38 PM PDT 24
Finished Aug 08 07:55:56 PM PDT 24
Peak memory 576056 kb
Host smart-3b5638c8-8ee6-43d9-b1b7-28c0eba7e777
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299027096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.299027096
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2875615227
Short name T2453
Test name
Test status
Simulation time 1852537060 ps
CPU time 118.23 seconds
Started Aug 08 07:51:37 PM PDT 24
Finished Aug 08 07:53:35 PM PDT 24
Peak memory 576036 kb
Host smart-70e1bfb8-cbde-4c01-a976-19bbec4c119c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875615227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2875615227
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1445830487
Short name T505
Test name
Test status
Simulation time 9541425663 ps
CPU time 506.79 seconds
Started Aug 08 07:51:38 PM PDT 24
Finished Aug 08 08:00:05 PM PDT 24
Peak memory 576772 kb
Host smart-c51fcbc9-99c1-4304-86d3-a62c2ff1b94f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445830487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all
_with_rand_reset.1445830487
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2865487783
Short name T1625
Test name
Test status
Simulation time 318255419 ps
CPU time 93.76 seconds
Started Aug 08 07:51:37 PM PDT 24
Finished Aug 08 07:53:10 PM PDT 24
Peak memory 576720 kb
Host smart-1730775e-28b5-404b-87fb-938523141415
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865487783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al
l_with_reset_error.2865487783
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.365965659
Short name T537
Test name
Test status
Simulation time 119637015 ps
CPU time 12.99 seconds
Started Aug 08 07:51:37 PM PDT 24
Finished Aug 08 07:51:50 PM PDT 24
Peak memory 575992 kb
Host smart-2cf06c5b-bcf6-4591-a292-44eb7ab631b3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365965659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.365965659
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.3715333661
Short name T2155
Test name
Test status
Simulation time 6440955400 ps
CPU time 408.99 seconds
Started Aug 08 07:51:55 PM PDT 24
Finished Aug 08 07:58:44 PM PDT 24
Peak memory 643904 kb
Host smart-be71d501-b19f-4ba0-89cd-dba9ff352c51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715333661 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.3715333661
Directory /workspace/11.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.chip_csr_rw.2547965749
Short name T423
Test name
Test status
Simulation time 5476093560 ps
CPU time 526.02 seconds
Started Aug 08 07:51:57 PM PDT 24
Finished Aug 08 08:00:43 PM PDT 24
Peak memory 597376 kb
Host smart-3bce1d17-207e-42a3-9ebd-ffb236294b6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547965749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.2547965749
Directory /workspace/11.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.4173774889
Short name T2853
Test name
Test status
Simulation time 28341117716 ps
CPU time 4646.72 seconds
Started Aug 08 07:51:36 PM PDT 24
Finished Aug 08 09:09:03 PM PDT 24
Peak memory 592988 kb
Host smart-2b04575b-b762-4095-b42e-31d8512ffd95
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173774889 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.4173774889
Directory /workspace/11.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_access_same_device.403876346
Short name T1877
Test name
Test status
Simulation time 3575617657 ps
CPU time 150.18 seconds
Started Aug 08 07:51:45 PM PDT 24
Finished Aug 08 07:54:15 PM PDT 24
Peak memory 576024 kb
Host smart-22e777f9-c565-4316-a562-2c57d61fbece
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403876346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.
403876346
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3159181666
Short name T1887
Test name
Test status
Simulation time 5600921865 ps
CPU time 103.34 seconds
Started Aug 08 07:51:48 PM PDT 24
Finished Aug 08 07:53:32 PM PDT 24
Peak memory 575952 kb
Host smart-3ca04ffc-0ceb-4288-bf7c-083f926cb3e4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159181666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_
device_slow_rsp.3159181666
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1812649131
Short name T1502
Test name
Test status
Simulation time 819953605 ps
CPU time 34.87 seconds
Started Aug 08 07:51:52 PM PDT 24
Finished Aug 08 07:52:27 PM PDT 24
Peak memory 575716 kb
Host smart-4cd58307-d9e7-4fa6-afbf-0f9378d4f0dd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812649131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add
r.1812649131
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_error_random.724197414
Short name T2016
Test name
Test status
Simulation time 559367970 ps
CPU time 20.27 seconds
Started Aug 08 07:51:47 PM PDT 24
Finished Aug 08 07:52:08 PM PDT 24
Peak memory 575900 kb
Host smart-09af655a-273f-485d-94d0-b9eb28014a0c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724197414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.724197414
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random.1857323921
Short name T601
Test name
Test status
Simulation time 384292640 ps
CPU time 31.46 seconds
Started Aug 08 07:51:46 PM PDT 24
Finished Aug 08 07:52:18 PM PDT 24
Peak memory 575852 kb
Host smart-237f32e8-e5ac-4cf0-bda3-892e8bbe988c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857323921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.1857323921
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1911609939
Short name T486
Test name
Test status
Simulation time 39747306631 ps
CPU time 451.22 seconds
Started Aug 08 07:51:46 PM PDT 24
Finished Aug 08 07:59:17 PM PDT 24
Peak memory 576016 kb
Host smart-1330d8a7-deac-4744-81c9-9b040a865bec
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911609939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1911609939
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3642801523
Short name T2864
Test name
Test status
Simulation time 4370845995 ps
CPU time 68.66 seconds
Started Aug 08 07:51:50 PM PDT 24
Finished Aug 08 07:52:59 PM PDT 24
Peak memory 574628 kb
Host smart-d5e76312-1c6e-4ed9-a7ff-e791bc00dc2e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642801523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3642801523
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2102237992
Short name T2501
Test name
Test status
Simulation time 651395935 ps
CPU time 49.03 seconds
Started Aug 08 07:51:50 PM PDT 24
Finished Aug 08 07:52:39 PM PDT 24
Peak memory 575700 kb
Host smart-fd233dfb-513b-45c0-9867-aefdcc46eebc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102237992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del
ays.2102237992
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_same_source.2487825860
Short name T2934
Test name
Test status
Simulation time 1739859453 ps
CPU time 45.12 seconds
Started Aug 08 07:51:45 PM PDT 24
Finished Aug 08 07:52:31 PM PDT 24
Peak memory 575740 kb
Host smart-1358cdbc-9a19-4540-af6b-9e6ef4d78d80
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487825860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2487825860
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke.741470224
Short name T2487
Test name
Test status
Simulation time 197979610 ps
CPU time 8.32 seconds
Started Aug 08 07:51:36 PM PDT 24
Finished Aug 08 07:51:44 PM PDT 24
Peak memory 573792 kb
Host smart-483b0d89-b82e-44b5-97cb-ccc383cfbd48
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741470224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.741470224
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2347341660
Short name T1429
Test name
Test status
Simulation time 7612743989 ps
CPU time 77.9 seconds
Started Aug 08 07:51:36 PM PDT 24
Finished Aug 08 07:52:54 PM PDT 24
Peak memory 573856 kb
Host smart-2c887fe5-4676-460f-8c9c-bf35779f2cc8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347341660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2347341660
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.301913867
Short name T1831
Test name
Test status
Simulation time 5352517124 ps
CPU time 89.72 seconds
Started Aug 08 07:51:38 PM PDT 24
Finished Aug 08 07:53:08 PM PDT 24
Peak memory 573916 kb
Host smart-643deabc-fd4d-44e2-bc4c-5f9038b9eebb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301913867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.301913867
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.320654571
Short name T1963
Test name
Test status
Simulation time 43106085 ps
CPU time 6.38 seconds
Started Aug 08 07:51:36 PM PDT 24
Finished Aug 08 07:51:42 PM PDT 24
Peak memory 573804 kb
Host smart-91b15591-e9d1-4c1b-b96c-ba0c14ce611c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320654571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays
.320654571
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all.3956091607
Short name T779
Test name
Test status
Simulation time 20981506159 ps
CPU time 809 seconds
Started Aug 08 07:51:46 PM PDT 24
Finished Aug 08 08:05:15 PM PDT 24
Peak memory 576648 kb
Host smart-78db2ed0-20a0-42f2-934f-48085bb4d045
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956091607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3956091607
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1164916355
Short name T2570
Test name
Test status
Simulation time 14819906283 ps
CPU time 570.18 seconds
Started Aug 08 07:51:45 PM PDT 24
Finished Aug 08 08:01:16 PM PDT 24
Peak memory 576672 kb
Host smart-a938b3b8-3850-485d-ab8c-5db8ab70da23
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164916355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1164916355
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.4167098282
Short name T1816
Test name
Test status
Simulation time 12810937150 ps
CPU time 680.91 seconds
Started Aug 08 07:51:46 PM PDT 24
Finished Aug 08 08:03:07 PM PDT 24
Peak memory 576752 kb
Host smart-ba03dba6-8cca-460c-95c2-bebf95c1aceb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167098282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all
_with_rand_reset.4167098282
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2718553559
Short name T1792
Test name
Test status
Simulation time 264490756 ps
CPU time 108.83 seconds
Started Aug 08 07:51:54 PM PDT 24
Finished Aug 08 07:53:43 PM PDT 24
Peak memory 576704 kb
Host smart-2873a3ec-a925-45f5-9833-c07a4e5a9723
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718553559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al
l_with_reset_error.2718553559
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2902716109
Short name T2818
Test name
Test status
Simulation time 1046185162 ps
CPU time 43.24 seconds
Started Aug 08 07:51:50 PM PDT 24
Finished Aug 08 07:52:33 PM PDT 24
Peak memory 575824 kb
Host smart-0794ca08-ef70-4bcc-8b23-dafba5395fa4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902716109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2902716109
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.1932893102
Short name T2072
Test name
Test status
Simulation time 6342125064 ps
CPU time 421.87 seconds
Started Aug 08 07:52:04 PM PDT 24
Finished Aug 08 07:59:06 PM PDT 24
Peak memory 643504 kb
Host smart-104d0c11-5b0a-45a2-9be5-17d016b5c3d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932893102 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.1932893102
Directory /workspace/12.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.629901167
Short name T1903
Test name
Test status
Simulation time 15833670590 ps
CPU time 1653.66 seconds
Started Aug 08 07:51:54 PM PDT 24
Finished Aug 08 08:19:28 PM PDT 24
Peak memory 593288 kb
Host smart-9c65d872-5c59-41a3-97c5-ef3d962aee97
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629901167 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.chip_same_csr_outstanding.629901167
Directory /workspace/12.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.chip_tl_errors.2108668495
Short name T2469
Test name
Test status
Simulation time 3442569534 ps
CPU time 245.98 seconds
Started Aug 08 07:51:55 PM PDT 24
Finished Aug 08 07:56:01 PM PDT 24
Peak memory 603712 kb
Host smart-87aff18f-eece-461e-8f85-0df13331128a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108668495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.2108668495
Directory /workspace/12.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_access_same_device.2897202385
Short name T1769
Test name
Test status
Simulation time 991253386 ps
CPU time 46.84 seconds
Started Aug 08 07:51:54 PM PDT 24
Finished Aug 08 07:52:41 PM PDT 24
Peak memory 575952 kb
Host smart-58455151-46a8-42ff-8150-bc22dcc5883f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897202385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device
.2897202385
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2315998083
Short name T2819
Test name
Test status
Simulation time 26872727768 ps
CPU time 433.41 seconds
Started Aug 08 07:51:54 PM PDT 24
Finished Aug 08 07:59:08 PM PDT 24
Peak memory 575828 kb
Host smart-e8090339-0910-4556-8e09-03082a7ccd37
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315998083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_
device_slow_rsp.2315998083
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3251824129
Short name T1985
Test name
Test status
Simulation time 80219498 ps
CPU time 6.14 seconds
Started Aug 08 07:52:07 PM PDT 24
Finished Aug 08 07:52:13 PM PDT 24
Peak memory 573788 kb
Host smart-3f81841d-b708-4478-b4f9-88efcbba9f40
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251824129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add
r.3251824129
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_error_random.255869200
Short name T2136
Test name
Test status
Simulation time 402081876 ps
CPU time 35.84 seconds
Started Aug 08 07:52:03 PM PDT 24
Finished Aug 08 07:52:39 PM PDT 24
Peak memory 575564 kb
Host smart-ff2f1f96-c5aa-4e53-8577-4748c669909a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255869200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.255869200
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random.1392401692
Short name T1481
Test name
Test status
Simulation time 1766736718 ps
CPU time 58.06 seconds
Started Aug 08 07:51:55 PM PDT 24
Finished Aug 08 07:52:54 PM PDT 24
Peak memory 575852 kb
Host smart-1306daee-e39c-4f3d-92d8-f2262265d09c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392401692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.1392401692
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3168803901
Short name T2216
Test name
Test status
Simulation time 110617654961 ps
CPU time 1155.2 seconds
Started Aug 08 07:51:55 PM PDT 24
Finished Aug 08 08:11:10 PM PDT 24
Peak memory 575928 kb
Host smart-5e568bc3-67a8-49b4-ab33-a734060573d0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168803901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3168803901
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.514170606
Short name T478
Test name
Test status
Simulation time 62590639294 ps
CPU time 1002.73 seconds
Started Aug 08 07:51:57 PM PDT 24
Finished Aug 08 08:08:40 PM PDT 24
Peak memory 576040 kb
Host smart-944a7dcf-f403-4b7e-bb31-8562ccbfcf60
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514170606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.514170606
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2085761770
Short name T1452
Test name
Test status
Simulation time 32563784 ps
CPU time 6.15 seconds
Started Aug 08 07:51:54 PM PDT 24
Finished Aug 08 07:52:00 PM PDT 24
Peak memory 574488 kb
Host smart-acb8a048-23c3-4866-a326-f1a7f47c9147
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085761770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del
ays.2085761770
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_same_source.3104184354
Short name T2395
Test name
Test status
Simulation time 2497268295 ps
CPU time 75.57 seconds
Started Aug 08 07:51:56 PM PDT 24
Finished Aug 08 07:53:12 PM PDT 24
Peak memory 575860 kb
Host smart-b6c83b1b-6fdf-4ba6-b689-e068e75b9f8e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104184354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3104184354
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke.2528704255
Short name T1555
Test name
Test status
Simulation time 234211653 ps
CPU time 9.39 seconds
Started Aug 08 07:51:55 PM PDT 24
Finished Aug 08 07:52:04 PM PDT 24
Peak memory 573820 kb
Host smart-0fd6b706-fe42-40b7-920e-ff3654d663ab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528704255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2528704255
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3193720939
Short name T2154
Test name
Test status
Simulation time 7458794456 ps
CPU time 76.68 seconds
Started Aug 08 07:51:55 PM PDT 24
Finished Aug 08 07:53:12 PM PDT 24
Peak memory 574580 kb
Host smart-6a5d6934-c638-46c1-8010-c5cbeea06fc5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193720939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3193720939
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2330480622
Short name T480
Test name
Test status
Simulation time 4615716416 ps
CPU time 79.6 seconds
Started Aug 08 07:51:56 PM PDT 24
Finished Aug 08 07:53:16 PM PDT 24
Peak memory 574624 kb
Host smart-97788eda-4cd4-4e18-876e-ea23c870dbb6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330480622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2330480622
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.922982684
Short name T1474
Test name
Test status
Simulation time 46859877 ps
CPU time 6.35 seconds
Started Aug 08 07:51:55 PM PDT 24
Finished Aug 08 07:52:01 PM PDT 24
Peak memory 573764 kb
Host smart-8fc22c4e-6db6-4bc3-99fa-306debae607d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922982684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays
.922982684
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all.2317588312
Short name T545
Test name
Test status
Simulation time 12007954124 ps
CPU time 440.73 seconds
Started Aug 08 07:52:05 PM PDT 24
Finished Aug 08 07:59:26 PM PDT 24
Peak memory 575916 kb
Host smart-efe71311-cd23-45b8-af75-ce9050e8b1fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317588312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2317588312
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2194201312
Short name T2884
Test name
Test status
Simulation time 2193446266 ps
CPU time 205.8 seconds
Started Aug 08 07:52:03 PM PDT 24
Finished Aug 08 07:55:29 PM PDT 24
Peak memory 576052 kb
Host smart-83bb9c07-dd8c-4f90-bbb8-a28f6ad315aa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194201312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2194201312
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.699405408
Short name T459
Test name
Test status
Simulation time 914134898 ps
CPU time 324.81 seconds
Started Aug 08 07:52:06 PM PDT 24
Finished Aug 08 07:57:31 PM PDT 24
Peak memory 576676 kb
Host smart-dd04cd65-c1fd-4049-ab6a-6753ad397975
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699405408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_
with_rand_reset.699405408
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.266051463
Short name T780
Test name
Test status
Simulation time 192903265 ps
CPU time 92.05 seconds
Started Aug 08 07:52:03 PM PDT 24
Finished Aug 08 07:53:36 PM PDT 24
Peak memory 575896 kb
Host smart-1066fb02-e433-4f7c-9399-92820785e5ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266051463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all
_with_reset_error.266051463
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2960323898
Short name T2394
Test name
Test status
Simulation time 243388633 ps
CPU time 27.76 seconds
Started Aug 08 07:52:03 PM PDT 24
Finished Aug 08 07:52:31 PM PDT 24
Peak memory 576024 kb
Host smart-4b2f471a-40bb-486c-865c-1bae7d6fbe23
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960323898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2960323898
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3202478411
Short name T1646
Test name
Test status
Simulation time 9985361348 ps
CPU time 672.46 seconds
Started Aug 08 07:52:17 PM PDT 24
Finished Aug 08 08:03:30 PM PDT 24
Peak memory 652924 kb
Host smart-b6927c8f-ebe5-4d05-817c-7303acc7f5b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202478411 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.3202478411
Directory /workspace/13.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.chip_csr_rw.1341542940
Short name T1773
Test name
Test status
Simulation time 6178874150 ps
CPU time 627.51 seconds
Started Aug 08 07:52:13 PM PDT 24
Finished Aug 08 08:02:41 PM PDT 24
Peak memory 599148 kb
Host smart-5780a78f-a0da-49e2-be05-b387f59f2d96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341542940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.1341542940
Directory /workspace/13.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2038960603
Short name T2580
Test name
Test status
Simulation time 28832221004 ps
CPU time 5026.99 seconds
Started Aug 08 07:52:04 PM PDT 24
Finished Aug 08 09:15:52 PM PDT 24
Peak memory 593376 kb
Host smart-d82a7f49-3cfd-4c2c-8930-7cd99eb91f2d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038960603 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.2038960603
Directory /workspace/13.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_access_same_device.2638044636
Short name T441
Test name
Test status
Simulation time 1105625636 ps
CPU time 42.85 seconds
Started Aug 08 07:52:07 PM PDT 24
Finished Aug 08 07:52:50 PM PDT 24
Peak memory 575852 kb
Host smart-61ec8449-7434-4e79-979b-bc4aa6d2aff5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638044636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device
.2638044636
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.699901415
Short name T1833
Test name
Test status
Simulation time 10942744162 ps
CPU time 188.23 seconds
Started Aug 08 07:52:13 PM PDT 24
Finished Aug 08 07:55:22 PM PDT 24
Peak memory 573872 kb
Host smart-6327a9e7-b489-4bef-a749-559c9fb15653
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699901415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_d
evice_slow_rsp.699901415
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.514455785
Short name T2417
Test name
Test status
Simulation time 112968141 ps
CPU time 14.43 seconds
Started Aug 08 07:52:13 PM PDT 24
Finished Aug 08 07:52:28 PM PDT 24
Peak memory 575924 kb
Host smart-ea0fb450-fa4f-4695-9253-3414a2daab19
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514455785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr
.514455785
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_error_random.1769509867
Short name T2249
Test name
Test status
Simulation time 1736638517 ps
CPU time 65.56 seconds
Started Aug 08 07:52:15 PM PDT 24
Finished Aug 08 07:53:20 PM PDT 24
Peak memory 575632 kb
Host smart-72adfe63-2428-4298-a540-36355c9296f4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769509867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1769509867
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random.1576224964
Short name T1525
Test name
Test status
Simulation time 321288209 ps
CPU time 27.4 seconds
Started Aug 08 07:52:04 PM PDT 24
Finished Aug 08 07:52:31 PM PDT 24
Peak memory 575892 kb
Host smart-9ff81775-dee3-4274-8008-06d518f30f36
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576224964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.1576224964
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3213561168
Short name T2209
Test name
Test status
Simulation time 107343405366 ps
CPU time 1121.08 seconds
Started Aug 08 07:52:05 PM PDT 24
Finished Aug 08 08:10:46 PM PDT 24
Peak memory 575992 kb
Host smart-220d54ab-6b08-4767-815a-6e2ad2252def
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213561168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3213561168
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.781501480
Short name T1983
Test name
Test status
Simulation time 39348946191 ps
CPU time 680.91 seconds
Started Aug 08 07:52:03 PM PDT 24
Finished Aug 08 08:03:24 PM PDT 24
Peak memory 576036 kb
Host smart-ffab692e-38b0-4be8-b884-c42dbf0f74f2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781501480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.781501480
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3541755272
Short name T1454
Test name
Test status
Simulation time 430193776 ps
CPU time 40.59 seconds
Started Aug 08 07:52:05 PM PDT 24
Finished Aug 08 07:52:46 PM PDT 24
Peak memory 575964 kb
Host smart-8edb5ab3-11e7-4937-8b27-c03bc5417194
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541755272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del
ays.3541755272
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_same_source.3266879494
Short name T455
Test name
Test status
Simulation time 509345921 ps
CPU time 38.96 seconds
Started Aug 08 07:52:15 PM PDT 24
Finished Aug 08 07:52:54 PM PDT 24
Peak memory 575880 kb
Host smart-d5af1d79-555a-4c96-a25b-6d9846fdc912
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266879494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3266879494
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke.2591625849
Short name T2869
Test name
Test status
Simulation time 40381630 ps
CPU time 5.91 seconds
Started Aug 08 07:52:05 PM PDT 24
Finished Aug 08 07:52:11 PM PDT 24
Peak memory 574464 kb
Host smart-5229527a-9cd7-4b28-8c8a-69b8d0db7709
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591625849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2591625849
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2421141230
Short name T1937
Test name
Test status
Simulation time 10431366753 ps
CPU time 96.76 seconds
Started Aug 08 07:52:04 PM PDT 24
Finished Aug 08 07:53:41 PM PDT 24
Peak memory 574580 kb
Host smart-f4d82432-b158-419f-9f24-774e001e802b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421141230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2421141230
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3684564245
Short name T2128
Test name
Test status
Simulation time 5331945281 ps
CPU time 91.51 seconds
Started Aug 08 07:52:03 PM PDT 24
Finished Aug 08 07:53:35 PM PDT 24
Peak memory 574552 kb
Host smart-5a19625e-3988-41ab-8b2e-ad3b246c226f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684564245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3684564245
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3065067139
Short name T1411
Test name
Test status
Simulation time 48244980 ps
CPU time 6.02 seconds
Started Aug 08 07:52:07 PM PDT 24
Finished Aug 08 07:52:13 PM PDT 24
Peak memory 573784 kb
Host smart-a9df742e-48e1-4d20-8fe2-11cc9146e73d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065067139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay
s.3065067139
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all.369422104
Short name T2196
Test name
Test status
Simulation time 2243226698 ps
CPU time 168.77 seconds
Started Aug 08 07:52:18 PM PDT 24
Finished Aug 08 07:55:07 PM PDT 24
Peak memory 576036 kb
Host smart-85ad4b76-ab16-48ec-8755-421dbe10d807
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369422104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.369422104
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1274235883
Short name T825
Test name
Test status
Simulation time 16106054846 ps
CPU time 610.22 seconds
Started Aug 08 07:52:13 PM PDT 24
Finished Aug 08 08:02:23 PM PDT 24
Peak memory 576764 kb
Host smart-18d618be-6005-48cb-b9da-0d78e2a3c672
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274235883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1274235883
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1742972621
Short name T1540
Test name
Test status
Simulation time 1417068911 ps
CPU time 111.95 seconds
Started Aug 08 07:52:13 PM PDT 24
Finished Aug 08 07:54:05 PM PDT 24
Peak memory 576600 kb
Host smart-11ee7147-ebf1-4bd8-964f-d4f1fa1e0a9c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742972621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al
l_with_reset_error.1742972621
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1933965262
Short name T2366
Test name
Test status
Simulation time 422789354 ps
CPU time 18.35 seconds
Started Aug 08 07:52:14 PM PDT 24
Finished Aug 08 07:52:32 PM PDT 24
Peak memory 576012 kb
Host smart-2a0cafe9-542a-44ac-8798-18fc6539793a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933965262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1933965262
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.694132188
Short name T2860
Test name
Test status
Simulation time 9728700020 ps
CPU time 800.87 seconds
Started Aug 08 07:52:24 PM PDT 24
Finished Aug 08 08:05:45 PM PDT 24
Peak memory 646272 kb
Host smart-c52ba9d3-95bc-41ed-87a5-3fb7c4315294
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694132188 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.694132188
Directory /workspace/14.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3440517195
Short name T359
Test name
Test status
Simulation time 15614022266 ps
CPU time 2251.19 seconds
Started Aug 08 07:52:13 PM PDT 24
Finished Aug 08 08:29:45 PM PDT 24
Peak memory 593224 kb
Host smart-448a98a7-6f55-417b-b08c-2cc134fd77b9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440517195 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.3440517195
Directory /workspace/14.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.chip_tl_errors.892488858
Short name T624
Test name
Test status
Simulation time 4432969189 ps
CPU time 317.45 seconds
Started Aug 08 07:52:15 PM PDT 24
Finished Aug 08 07:57:32 PM PDT 24
Peak memory 603708 kb
Host smart-03ea64b6-f29c-49ae-a972-81b3311a3127
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892488858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.892488858
Directory /workspace/14.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_access_same_device.170065294
Short name T1603
Test name
Test status
Simulation time 987562010 ps
CPU time 73.44 seconds
Started Aug 08 07:52:24 PM PDT 24
Finished Aug 08 07:53:37 PM PDT 24
Peak memory 575764 kb
Host smart-26d838b5-5ed3-4915-912d-d1926e7de0aa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170065294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.
170065294
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1475188038
Short name T2880
Test name
Test status
Simulation time 109872260363 ps
CPU time 1877.16 seconds
Started Aug 08 07:52:26 PM PDT 24
Finished Aug 08 08:23:43 PM PDT 24
Peak memory 575888 kb
Host smart-c8a4d30f-0256-47e2-bdb7-e5d5c412709a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475188038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_
device_slow_rsp.1475188038
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1108991311
Short name T2333
Test name
Test status
Simulation time 437042046 ps
CPU time 18.85 seconds
Started Aug 08 07:52:23 PM PDT 24
Finished Aug 08 07:52:42 PM PDT 24
Peak memory 575928 kb
Host smart-18b2af3f-3687-403f-84dd-361c01b6747a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108991311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add
r.1108991311
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_error_random.1048055702
Short name T2199
Test name
Test status
Simulation time 723733641 ps
CPU time 25.8 seconds
Started Aug 08 07:52:23 PM PDT 24
Finished Aug 08 07:52:49 PM PDT 24
Peak memory 575852 kb
Host smart-f019332e-a447-4920-a857-4a669a8372ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048055702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1048055702
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random.691470639
Short name T1859
Test name
Test status
Simulation time 2392565061 ps
CPU time 82.51 seconds
Started Aug 08 07:52:15 PM PDT 24
Finished Aug 08 07:53:38 PM PDT 24
Peak memory 575964 kb
Host smart-0e331bcf-1b53-4cb8-9dae-80db1923f278
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691470639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.691470639
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.3601112764
Short name T607
Test name
Test status
Simulation time 32583638534 ps
CPU time 558.79 seconds
Started Aug 08 07:52:32 PM PDT 24
Finished Aug 08 08:01:51 PM PDT 24
Peak memory 575876 kb
Host smart-c5d415e7-dac4-4583-9877-454f56a322da
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601112764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3601112764
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.881631808
Short name T2345
Test name
Test status
Simulation time 242083411 ps
CPU time 21.97 seconds
Started Aug 08 07:52:26 PM PDT 24
Finished Aug 08 07:52:48 PM PDT 24
Peak memory 575688 kb
Host smart-14de18e7-de2b-4636-927f-56fcf9595ba8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881631808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_dela
ys.881631808
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_same_source.3656520872
Short name T2480
Test name
Test status
Simulation time 233796670 ps
CPU time 19.06 seconds
Started Aug 08 07:52:24 PM PDT 24
Finished Aug 08 07:52:43 PM PDT 24
Peak memory 575672 kb
Host smart-280b90e4-4097-45bb-b8f5-eafcc1fc5ef1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656520872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3656520872
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke.1351299659
Short name T1761
Test name
Test status
Simulation time 40830367 ps
CPU time 5.67 seconds
Started Aug 08 07:52:18 PM PDT 24
Finished Aug 08 07:52:24 PM PDT 24
Peak memory 573804 kb
Host smart-ef883c94-5e9a-4e16-8c63-43957d0d0020
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351299659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1351299659
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.106889401
Short name T2363
Test name
Test status
Simulation time 9796157156 ps
CPU time 101.82 seconds
Started Aug 08 07:52:13 PM PDT 24
Finished Aug 08 07:53:55 PM PDT 24
Peak memory 573828 kb
Host smart-dfdd38c4-d15f-460f-990e-cad2bc6fea2a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106889401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.106889401
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.223781684
Short name T2849
Test name
Test status
Simulation time 6308739557 ps
CPU time 111.18 seconds
Started Aug 08 07:52:15 PM PDT 24
Finished Aug 08 07:54:06 PM PDT 24
Peak memory 574536 kb
Host smart-9ab32ee2-d931-4fd6-b4e4-69ed0b795a25
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223781684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.223781684
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.755501700
Short name T1564
Test name
Test status
Simulation time 54511809 ps
CPU time 6.54 seconds
Started Aug 08 07:52:12 PM PDT 24
Finished Aug 08 07:52:19 PM PDT 24
Peak memory 574464 kb
Host smart-fdd32888-0816-4d03-8c53-ece7a1405d03
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755501700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays
.755501700
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all.1847873899
Short name T2102
Test name
Test status
Simulation time 2415116443 ps
CPU time 192.5 seconds
Started Aug 08 07:52:25 PM PDT 24
Finished Aug 08 07:55:37 PM PDT 24
Peak memory 576708 kb
Host smart-4bcfae97-6920-4ffb-8bbe-46edbf7b9de5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847873899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1847873899
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.2438694261
Short name T1602
Test name
Test status
Simulation time 849791693 ps
CPU time 69.33 seconds
Started Aug 08 07:52:26 PM PDT 24
Finished Aug 08 07:53:35 PM PDT 24
Peak memory 576088 kb
Host smart-d2b6b18f-9e83-4d4e-8b61-5fa22f01fb8c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438694261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2438694261
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3231097928
Short name T2183
Test name
Test status
Simulation time 79185090 ps
CPU time 38.57 seconds
Started Aug 08 07:52:26 PM PDT 24
Finished Aug 08 07:53:05 PM PDT 24
Peak memory 576040 kb
Host smart-fc2bd403-f386-4800-a12a-1e32b07488f4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231097928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all
_with_rand_reset.3231097928
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3976079224
Short name T2650
Test name
Test status
Simulation time 67118157 ps
CPU time 21.39 seconds
Started Aug 08 07:52:25 PM PDT 24
Finished Aug 08 07:52:47 PM PDT 24
Peak memory 575952 kb
Host smart-1fccc1bb-e49c-4673-b6b9-cf27f5e75b18
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976079224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al
l_with_reset_error.3976079224
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.4019174311
Short name T1483
Test name
Test status
Simulation time 1275642918 ps
CPU time 48.23 seconds
Started Aug 08 07:52:33 PM PDT 24
Finished Aug 08 07:53:21 PM PDT 24
Peak memory 575952 kb
Host smart-28835ce1-b43c-4423-a2c6-b5d00a6a94a9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019174311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.4019174311
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.1598425393
Short name T1622
Test name
Test status
Simulation time 5189819339 ps
CPU time 425.36 seconds
Started Aug 08 07:52:40 PM PDT 24
Finished Aug 08 07:59:45 PM PDT 24
Peak memory 639160 kb
Host smart-2177dae7-95cc-478b-a1d1-763d93e1ac22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598425393 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.1598425393
Directory /workspace/15.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.chip_csr_rw.2740384148
Short name T2246
Test name
Test status
Simulation time 4406037400 ps
CPU time 338.9 seconds
Started Aug 08 07:52:42 PM PDT 24
Finished Aug 08 07:58:21 PM PDT 24
Peak memory 597392 kb
Host smart-ef4735b9-c340-43a8-b182-4081eaf4aa6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740384148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.2740384148
Directory /workspace/15.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.2422736082
Short name T2365
Test name
Test status
Simulation time 29919744560 ps
CPU time 3739.27 seconds
Started Aug 08 07:52:35 PM PDT 24
Finished Aug 08 08:54:55 PM PDT 24
Peak memory 593592 kb
Host smart-9f87d41c-6b53-4ef5-ad80-f3420de595f7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422736082 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.2422736082
Directory /workspace/15.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.chip_tl_errors.1656808416
Short name T524
Test name
Test status
Simulation time 3161412596 ps
CPU time 156.2 seconds
Started Aug 08 07:52:35 PM PDT 24
Finished Aug 08 07:55:11 PM PDT 24
Peak memory 598536 kb
Host smart-4d7d44f2-0acd-41f6-ba62-1215dcdf0f65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656808416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.1656808416
Directory /workspace/15.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_access_same_device.3294121514
Short name T774
Test name
Test status
Simulation time 1721493857 ps
CPU time 57.3 seconds
Started Aug 08 07:52:32 PM PDT 24
Finished Aug 08 07:53:29 PM PDT 24
Peak memory 575788 kb
Host smart-250647f4-0b1d-45cb-90f2-8b4b7a55b0b9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294121514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device
.3294121514
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.4023679340
Short name T783
Test name
Test status
Simulation time 75150122265 ps
CPU time 1350.72 seconds
Started Aug 08 07:52:36 PM PDT 24
Finished Aug 08 08:15:07 PM PDT 24
Peak memory 575872 kb
Host smart-e6d24d60-579e-4f6f-926f-0653814d5e9c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023679340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_
device_slow_rsp.4023679340
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.1227996504
Short name T1777
Test name
Test status
Simulation time 367285090 ps
CPU time 15.89 seconds
Started Aug 08 07:52:38 PM PDT 24
Finished Aug 08 07:52:53 PM PDT 24
Peak memory 575884 kb
Host smart-11d5c8a4-8477-4181-99f3-c49ff092bbf4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227996504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add
r.1227996504
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_error_random.1861933380
Short name T2120
Test name
Test status
Simulation time 1169983599 ps
CPU time 36.84 seconds
Started Aug 08 07:52:35 PM PDT 24
Finished Aug 08 07:53:12 PM PDT 24
Peak memory 575860 kb
Host smart-95a7bb00-d1c3-4d9f-94cc-e7ce4265c79e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861933380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1861933380
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random.1370144172
Short name T2315
Test name
Test status
Simulation time 948175649 ps
CPU time 34.25 seconds
Started Aug 08 07:52:33 PM PDT 24
Finished Aug 08 07:53:07 PM PDT 24
Peak memory 575952 kb
Host smart-41d43e7a-c957-4fda-a1ae-a34912a9739f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370144172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.1370144172
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.1277334430
Short name T1430
Test name
Test status
Simulation time 12011414811 ps
CPU time 121.86 seconds
Started Aug 08 07:52:35 PM PDT 24
Finished Aug 08 07:54:37 PM PDT 24
Peak memory 575944 kb
Host smart-cc2e121b-9bf2-4043-9547-3cbb2e7e5ae0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277334430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1277334430
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.2248625498
Short name T598
Test name
Test status
Simulation time 13828558196 ps
CPU time 236 seconds
Started Aug 08 07:52:34 PM PDT 24
Finished Aug 08 07:56:30 PM PDT 24
Peak memory 575884 kb
Host smart-636d323c-6650-4aa7-8789-078c28c25295
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248625498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.2248625498
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.4062093742
Short name T2393
Test name
Test status
Simulation time 558079889 ps
CPU time 48.57 seconds
Started Aug 08 07:52:32 PM PDT 24
Finished Aug 08 07:53:21 PM PDT 24
Peak memory 575736 kb
Host smart-372555f8-9761-430a-9303-ecd4e5ab0ead
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062093742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del
ays.4062093742
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_same_source.1280818693
Short name T2833
Test name
Test status
Simulation time 1397571440 ps
CPU time 43 seconds
Started Aug 08 07:52:38 PM PDT 24
Finished Aug 08 07:53:21 PM PDT 24
Peak memory 575804 kb
Host smart-54dac87c-df9e-4f70-845d-e2ebb2e7d57b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280818693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1280818693
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke.1058981334
Short name T1471
Test name
Test status
Simulation time 152840614 ps
CPU time 8.02 seconds
Started Aug 08 07:52:33 PM PDT 24
Finished Aug 08 07:52:41 PM PDT 24
Peak memory 573812 kb
Host smart-8884d9e0-a7b2-46e5-b995-5e97787df005
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058981334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1058981334
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.2426209523
Short name T2627
Test name
Test status
Simulation time 8842843995 ps
CPU time 94.2 seconds
Started Aug 08 07:52:35 PM PDT 24
Finished Aug 08 07:54:09 PM PDT 24
Peak memory 574584 kb
Host smart-a2d63cee-6383-40f2-837f-0e3da3f48b78
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426209523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2426209523
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.396718983
Short name T1992
Test name
Test status
Simulation time 5447894950 ps
CPU time 91.65 seconds
Started Aug 08 07:52:36 PM PDT 24
Finished Aug 08 07:54:08 PM PDT 24
Peak memory 574536 kb
Host smart-08cdba82-2b85-43c4-9feb-8cfeb997a33a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396718983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.396718983
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.1129078702
Short name T2329
Test name
Test status
Simulation time 48834821 ps
CPU time 6.38 seconds
Started Aug 08 07:52:32 PM PDT 24
Finished Aug 08 07:52:38 PM PDT 24
Peak memory 573736 kb
Host smart-c7ea9036-a4b1-4e4c-8cda-6ecda1d9d8f3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129078702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay
s.1129078702
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all.2457442168
Short name T1582
Test name
Test status
Simulation time 878712303 ps
CPU time 42.6 seconds
Started Aug 08 07:52:41 PM PDT 24
Finished Aug 08 07:53:23 PM PDT 24
Peak memory 575756 kb
Host smart-235dd756-20ec-42ca-a971-c5f18b505217
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457442168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2457442168
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.777939637
Short name T2404
Test name
Test status
Simulation time 5822218894 ps
CPU time 194.34 seconds
Started Aug 08 07:52:42 PM PDT 24
Finished Aug 08 07:55:57 PM PDT 24
Peak memory 576152 kb
Host smart-4a158acc-1398-427a-9042-3dae1063848e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777939637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.777939637
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1943753486
Short name T570
Test name
Test status
Simulation time 4405021186 ps
CPU time 475.72 seconds
Started Aug 08 07:52:39 PM PDT 24
Finished Aug 08 08:00:35 PM PDT 24
Peak memory 575952 kb
Host smart-bc83756f-2fb9-42b8-b0fd-c319d3d44281
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943753486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all
_with_rand_reset.1943753486
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1380124342
Short name T1642
Test name
Test status
Simulation time 633258414 ps
CPU time 183.6 seconds
Started Aug 08 07:52:41 PM PDT 24
Finished Aug 08 07:55:45 PM PDT 24
Peak memory 575860 kb
Host smart-b1f9018a-79f9-4b7a-ae06-09c3cd86b659
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380124342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al
l_with_reset_error.1380124342
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.2277083541
Short name T1857
Test name
Test status
Simulation time 1235725749 ps
CPU time 59.71 seconds
Started Aug 08 07:52:33 PM PDT 24
Finished Aug 08 07:53:33 PM PDT 24
Peak memory 575832 kb
Host smart-9bf1d338-7b34-40b3-a8da-6ad989ed1b69
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277083541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2277083541
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.842748069
Short name T371
Test name
Test status
Simulation time 6409360266 ps
CPU time 479.47 seconds
Started Aug 08 07:52:59 PM PDT 24
Finished Aug 08 08:00:59 PM PDT 24
Peak memory 641756 kb
Host smart-15dd3ca3-1460-4af5-b4c8-a24b5b7e87df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842748069 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.842748069
Directory /workspace/16.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.chip_csr_rw.3607821208
Short name T2171
Test name
Test status
Simulation time 6036603504 ps
CPU time 552.4 seconds
Started Aug 08 07:53:00 PM PDT 24
Finished Aug 08 08:02:12 PM PDT 24
Peak memory 598268 kb
Host smart-e4a44c72-4d5a-4d11-a4f2-43416d494f0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607821208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.3607821208
Directory /workspace/16.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.1224029974
Short name T1565
Test name
Test status
Simulation time 30320716600 ps
CPU time 4192.67 seconds
Started Aug 08 07:52:41 PM PDT 24
Finished Aug 08 09:02:34 PM PDT 24
Peak memory 593340 kb
Host smart-0209bf76-26be-4e01-a5d0-2fb35b310969
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224029974 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.1224029974
Directory /workspace/16.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_access_same_device.2367468045
Short name T1743
Test name
Test status
Simulation time 3499813269 ps
CPU time 128.37 seconds
Started Aug 08 07:52:51 PM PDT 24
Finished Aug 08 07:55:00 PM PDT 24
Peak memory 576032 kb
Host smart-2498ee21-f95f-4f02-9b16-d326b8ec5f41
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367468045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device
.2367468045
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1417476902
Short name T2076
Test name
Test status
Simulation time 25963713042 ps
CPU time 455.48 seconds
Started Aug 08 07:52:51 PM PDT 24
Finished Aug 08 08:00:26 PM PDT 24
Peak memory 576768 kb
Host smart-1e73c1a5-0f36-4108-86da-b003029f0e11
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417476902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_
device_slow_rsp.1417476902
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.778450672
Short name T2740
Test name
Test status
Simulation time 144415260 ps
CPU time 15.31 seconds
Started Aug 08 07:52:50 PM PDT 24
Finished Aug 08 07:53:06 PM PDT 24
Peak memory 575860 kb
Host smart-57fdb5fa-18dc-4843-9c26-0ea908e0d69c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778450672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr
.778450672
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_error_random.3725945265
Short name T2266
Test name
Test status
Simulation time 1178562142 ps
CPU time 39.71 seconds
Started Aug 08 07:52:54 PM PDT 24
Finished Aug 08 07:53:34 PM PDT 24
Peak memory 575712 kb
Host smart-398c91d0-795d-4ebd-a173-25d96b4c9046
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725945265 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3725945265
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random.3837482758
Short name T1987
Test name
Test status
Simulation time 507452557 ps
CPU time 39.46 seconds
Started Aug 08 07:52:52 PM PDT 24
Finished Aug 08 07:53:32 PM PDT 24
Peak memory 575776 kb
Host smart-138ad152-41c2-4c21-b71c-fb8130756eab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837482758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.3837482758
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2212453461
Short name T531
Test name
Test status
Simulation time 75531418442 ps
CPU time 834.31 seconds
Started Aug 08 07:52:51 PM PDT 24
Finished Aug 08 08:06:45 PM PDT 24
Peak memory 575964 kb
Host smart-9ae22513-ffb6-43f9-ab2a-a6b91b34d43f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212453461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2212453461
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.2991656150
Short name T1552
Test name
Test status
Simulation time 21768900213 ps
CPU time 354.77 seconds
Started Aug 08 07:52:50 PM PDT 24
Finished Aug 08 07:58:46 PM PDT 24
Peak memory 576016 kb
Host smart-678d656a-a10c-45f0-bc29-f80404beac25
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991656150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2991656150
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.2286152918
Short name T2479
Test name
Test status
Simulation time 366006998 ps
CPU time 35.68 seconds
Started Aug 08 07:52:51 PM PDT 24
Finished Aug 08 07:53:27 PM PDT 24
Peak memory 575684 kb
Host smart-1bf9b344-33a1-4cb7-a080-3b26eb4d00c6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286152918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del
ays.2286152918
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_same_source.3198346519
Short name T2450
Test name
Test status
Simulation time 878245323 ps
CPU time 26.32 seconds
Started Aug 08 07:52:49 PM PDT 24
Finished Aug 08 07:53:16 PM PDT 24
Peak memory 575816 kb
Host smart-588f7715-c6f3-409a-adde-ca57cca4a27e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198346519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3198346519
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke.1748771072
Short name T2590
Test name
Test status
Simulation time 200784562 ps
CPU time 8.37 seconds
Started Aug 08 07:52:52 PM PDT 24
Finished Aug 08 07:53:00 PM PDT 24
Peak memory 573736 kb
Host smart-ec4f1ce4-9396-4dd4-a4a2-d59d58b6a389
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748771072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1748771072
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.3605300758
Short name T1501
Test name
Test status
Simulation time 7192643006 ps
CPU time 73.45 seconds
Started Aug 08 07:52:51 PM PDT 24
Finished Aug 08 07:54:05 PM PDT 24
Peak memory 574608 kb
Host smart-a293c2b7-0be2-48da-8433-b77a5f5b07e6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605300758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3605300758
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1966468878
Short name T2682
Test name
Test status
Simulation time 5387410924 ps
CPU time 97.3 seconds
Started Aug 08 07:52:50 PM PDT 24
Finished Aug 08 07:54:28 PM PDT 24
Peak memory 573948 kb
Host smart-7252aefe-19c2-432a-92f6-8d7bd0c5214c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966468878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1966468878
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2183510784
Short name T2064
Test name
Test status
Simulation time 47768888 ps
CPU time 5.94 seconds
Started Aug 08 07:52:52 PM PDT 24
Finished Aug 08 07:52:58 PM PDT 24
Peak memory 574492 kb
Host smart-dff84f0d-a12f-4765-b950-95804710fb30
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183510784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay
s.2183510784
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all.422505688
Short name T432
Test name
Test status
Simulation time 4810592246 ps
CPU time 174.04 seconds
Started Aug 08 07:52:53 PM PDT 24
Finished Aug 08 07:55:47 PM PDT 24
Peak memory 576252 kb
Host smart-34098db6-9e0b-41ba-b69a-34e005d9da43
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422505688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.422505688
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.4087410166
Short name T1389
Test name
Test status
Simulation time 6812026107 ps
CPU time 249.54 seconds
Started Aug 08 07:52:59 PM PDT 24
Finished Aug 08 07:57:09 PM PDT 24
Peak memory 576116 kb
Host smart-37d58c56-ba24-4142-8922-f95d150c9bb1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087410166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.4087410166
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.904452978
Short name T1943
Test name
Test status
Simulation time 47365008 ps
CPU time 30.03 seconds
Started Aug 08 07:52:59 PM PDT 24
Finished Aug 08 07:53:29 PM PDT 24
Peak memory 575860 kb
Host smart-246a1cd6-66ba-4061-b58f-ed75c9005b6e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904452978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_
with_rand_reset.904452978
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.482727608
Short name T2581
Test name
Test status
Simulation time 628801075 ps
CPU time 187.92 seconds
Started Aug 08 07:53:02 PM PDT 24
Finished Aug 08 07:56:10 PM PDT 24
Peak memory 576700 kb
Host smart-78fd84a3-e820-473d-8476-331af252a9ff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482727608 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all
_with_reset_error.482727608
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.3292404173
Short name T1384
Test name
Test status
Simulation time 167855441 ps
CPU time 9.83 seconds
Started Aug 08 07:52:52 PM PDT 24
Finished Aug 08 07:53:02 PM PDT 24
Peak memory 573924 kb
Host smart-0aa7118b-8c08-48cd-be7f-54e925728978
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292404173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3292404173
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.1088276936
Short name T2335
Test name
Test status
Simulation time 7831958830 ps
CPU time 756.73 seconds
Started Aug 08 07:53:19 PM PDT 24
Finished Aug 08 08:05:56 PM PDT 24
Peak memory 646304 kb
Host smart-c9c9a459-ff64-4ce6-a28d-87dadc23a134
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088276936 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.1088276936
Directory /workspace/17.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.chip_csr_rw.2645173134
Short name T1680
Test name
Test status
Simulation time 3886931762 ps
CPU time 235.97 seconds
Started Aug 08 07:53:10 PM PDT 24
Finished Aug 08 07:57:06 PM PDT 24
Peak memory 599312 kb
Host smart-8abcd5c1-637f-4b24-9b1a-c37036391316
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645173134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.2645173134
Directory /workspace/17.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_access_same_device.2024044097
Short name T2334
Test name
Test status
Simulation time 2451180744 ps
CPU time 91.78 seconds
Started Aug 08 07:53:10 PM PDT 24
Finished Aug 08 07:54:42 PM PDT 24
Peak memory 575836 kb
Host smart-686785cc-d312-4bb0-801b-a71714fa06bc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024044097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device
.2024044097
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1350985920
Short name T2821
Test name
Test status
Simulation time 30852143878 ps
CPU time 552.41 seconds
Started Aug 08 07:53:10 PM PDT 24
Finished Aug 08 08:02:22 PM PDT 24
Peak memory 576748 kb
Host smart-ae474ab5-7921-4c2c-80f8-ca2e981a004a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350985920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_
device_slow_rsp.1350985920
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3848608784
Short name T1918
Test name
Test status
Simulation time 1206830628 ps
CPU time 54.96 seconds
Started Aug 08 07:53:09 PM PDT 24
Finished Aug 08 07:54:04 PM PDT 24
Peak memory 575976 kb
Host smart-310bbbf2-bd7d-43a7-9e61-a3524259f19d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848608784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add
r.3848608784
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_error_random.237626614
Short name T1576
Test name
Test status
Simulation time 1983245808 ps
CPU time 64.49 seconds
Started Aug 08 07:53:09 PM PDT 24
Finished Aug 08 07:54:14 PM PDT 24
Peak memory 575900 kb
Host smart-cf487ab2-1c39-4eb9-a186-e2d9b8c20a74
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237626614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.237626614
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random.3065369046
Short name T1916
Test name
Test status
Simulation time 476910007 ps
CPU time 38.14 seconds
Started Aug 08 07:53:00 PM PDT 24
Finished Aug 08 07:53:38 PM PDT 24
Peak memory 575940 kb
Host smart-87fe2830-99c4-4385-ae18-c1d23f86410b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065369046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.3065369046
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.3717570762
Short name T576
Test name
Test status
Simulation time 81842617508 ps
CPU time 917.18 seconds
Started Aug 08 07:53:10 PM PDT 24
Finished Aug 08 08:08:27 PM PDT 24
Peak memory 575884 kb
Host smart-f2335e74-e36b-4e19-9a3c-85ce7793d045
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717570762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3717570762
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.505126689
Short name T2724
Test name
Test status
Simulation time 22587690702 ps
CPU time 393.34 seconds
Started Aug 08 07:53:10 PM PDT 24
Finished Aug 08 07:59:44 PM PDT 24
Peak memory 575908 kb
Host smart-79fb1491-0251-4347-8368-1cfade92e232
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505126689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.505126689
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.653985414
Short name T2451
Test name
Test status
Simulation time 40998937 ps
CPU time 6.45 seconds
Started Aug 08 07:53:10 PM PDT 24
Finished Aug 08 07:53:17 PM PDT 24
Peak memory 573756 kb
Host smart-67e70698-b61a-4f4f-b0a4-fa38680b80e3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653985414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_dela
ys.653985414
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_same_source.2347002294
Short name T2116
Test name
Test status
Simulation time 1709180985 ps
CPU time 54.08 seconds
Started Aug 08 07:53:10 PM PDT 24
Finished Aug 08 07:54:04 PM PDT 24
Peak memory 575696 kb
Host smart-70db6d49-4e09-4aaf-8c27-44e3e04cb52a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347002294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2347002294
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke.1342562081
Short name T2500
Test name
Test status
Simulation time 184853603 ps
CPU time 9.13 seconds
Started Aug 08 07:53:02 PM PDT 24
Finished Aug 08 07:53:11 PM PDT 24
Peak memory 574380 kb
Host smart-84267f57-28c9-4711-a549-52a11be4a1f0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342562081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1342562081
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.3817752977
Short name T1350
Test name
Test status
Simulation time 7219737525 ps
CPU time 75.08 seconds
Started Aug 08 07:53:04 PM PDT 24
Finished Aug 08 07:54:19 PM PDT 24
Peak memory 573916 kb
Host smart-45454b9d-0e2b-4c27-8824-ce92c06c1231
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817752977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3817752977
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.203758786
Short name T2767
Test name
Test status
Simulation time 4771872698 ps
CPU time 81.24 seconds
Started Aug 08 07:53:01 PM PDT 24
Finished Aug 08 07:54:23 PM PDT 24
Peak memory 574584 kb
Host smart-3d199d7a-c8a8-4c14-83a2-065b4471b47a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203758786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.203758786
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.2227460990
Short name T1533
Test name
Test status
Simulation time 48629284 ps
CPU time 6.25 seconds
Started Aug 08 07:53:00 PM PDT 24
Finished Aug 08 07:53:06 PM PDT 24
Peak memory 574432 kb
Host smart-e9b765e8-d047-4818-b2eb-2ee5bbadb4c3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227460990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay
s.2227460990
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all.3591472865
Short name T2635
Test name
Test status
Simulation time 14745301649 ps
CPU time 589.13 seconds
Started Aug 08 07:53:10 PM PDT 24
Finished Aug 08 08:02:59 PM PDT 24
Peak memory 576824 kb
Host smart-44124cd3-b73d-4e0e-83fa-89797cc60f88
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591472865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3591472865
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.2912364225
Short name T1573
Test name
Test status
Simulation time 9424298573 ps
CPU time 332.56 seconds
Started Aug 08 07:53:10 PM PDT 24
Finished Aug 08 07:58:43 PM PDT 24
Peak memory 576732 kb
Host smart-80d4e4d1-2368-45d7-899c-3182fa1f9f26
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912364225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2912364225
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.3317924425
Short name T2659
Test name
Test status
Simulation time 2443685554 ps
CPU time 179.86 seconds
Started Aug 08 07:53:12 PM PDT 24
Finished Aug 08 07:56:12 PM PDT 24
Peak memory 576784 kb
Host smart-48cf5a0f-eb4f-4246-ac11-0fe63d74afe9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317924425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all
_with_rand_reset.3317924425
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.1709650818
Short name T1774
Test name
Test status
Simulation time 185267405 ps
CPU time 53.9 seconds
Started Aug 08 07:53:10 PM PDT 24
Finished Aug 08 07:54:04 PM PDT 24
Peak memory 575880 kb
Host smart-bb89b3d9-1fa6-400e-b81c-1c8148e5a88f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709650818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al
l_with_reset_error.1709650818
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.3074668593
Short name T546
Test name
Test status
Simulation time 270072631 ps
CPU time 31.34 seconds
Started Aug 08 07:53:10 PM PDT 24
Finished Aug 08 07:53:41 PM PDT 24
Peak memory 575936 kb
Host smart-027e673d-1f77-41d6-a3fc-257fcc798a1b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074668593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3074668593
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.1418167555
Short name T1619
Test name
Test status
Simulation time 6108760765 ps
CPU time 464.9 seconds
Started Aug 08 07:53:37 PM PDT 24
Finished Aug 08 08:01:22 PM PDT 24
Peak memory 638556 kb
Host smart-8fa3966e-ac0c-46ea-b568-c51df8d26e7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418167555 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.1418167555
Directory /workspace/18.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.chip_csr_rw.4011239159
Short name T1666
Test name
Test status
Simulation time 5747439863 ps
CPU time 473.13 seconds
Started Aug 08 07:53:32 PM PDT 24
Finished Aug 08 08:01:25 PM PDT 24
Peak memory 599088 kb
Host smart-97da942a-308c-40ca-9996-4977c5792480
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011239159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.4011239159
Directory /workspace/18.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1127534512
Short name T368
Test name
Test status
Simulation time 15697761948 ps
CPU time 1938.84 seconds
Started Aug 08 07:53:19 PM PDT 24
Finished Aug 08 08:25:38 PM PDT 24
Peak memory 593216 kb
Host smart-7f5aa36f-e9ac-4fea-909a-e38f7815abea
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127534512 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.1127534512
Directory /workspace/18.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.chip_tl_errors.1813322764
Short name T563
Test name
Test status
Simulation time 2894930056 ps
CPU time 158.59 seconds
Started Aug 08 07:53:22 PM PDT 24
Finished Aug 08 07:56:01 PM PDT 24
Peak memory 598612 kb
Host smart-df81796b-2a21-4d98-9966-5d77487c3798
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813322764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.1813322764
Directory /workspace/18.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_access_same_device.1931286075
Short name T2798
Test name
Test status
Simulation time 1049747359 ps
CPU time 71.42 seconds
Started Aug 08 07:53:21 PM PDT 24
Finished Aug 08 07:54:33 PM PDT 24
Peak memory 575792 kb
Host smart-35d4749b-49e5-4bc6-9758-3425c17344d9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931286075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device
.1931286075
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2578536249
Short name T2506
Test name
Test status
Simulation time 50869487221 ps
CPU time 924.85 seconds
Started Aug 08 07:53:20 PM PDT 24
Finished Aug 08 08:08:45 PM PDT 24
Peak memory 575928 kb
Host smart-a1e378ce-580c-493f-93ed-0d674cf08b4e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578536249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_
device_slow_rsp.2578536249
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.3035665396
Short name T1466
Test name
Test status
Simulation time 31686803 ps
CPU time 6.4 seconds
Started Aug 08 07:53:28 PM PDT 24
Finished Aug 08 07:53:35 PM PDT 24
Peak memory 574452 kb
Host smart-82d9307e-f633-4ce0-8782-4ce839c507a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035665396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add
r.3035665396
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_error_random.1073785315
Short name T2373
Test name
Test status
Simulation time 245224601 ps
CPU time 11.73 seconds
Started Aug 08 07:53:20 PM PDT 24
Finished Aug 08 07:53:32 PM PDT 24
Peak memory 575688 kb
Host smart-45f3137a-d73d-4d3a-8282-8ec070d613cc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073785315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1073785315
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random.3395265558
Short name T2103
Test name
Test status
Simulation time 254337523 ps
CPU time 12.75 seconds
Started Aug 08 07:53:22 PM PDT 24
Finished Aug 08 07:53:35 PM PDT 24
Peak memory 575916 kb
Host smart-0ba5c0bc-21f5-4abb-8f5e-41d147506f80
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395265558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.3395265558
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.3220789084
Short name T2272
Test name
Test status
Simulation time 101753722142 ps
CPU time 1139.24 seconds
Started Aug 08 07:53:20 PM PDT 24
Finished Aug 08 08:12:19 PM PDT 24
Peak memory 575988 kb
Host smart-c00b4ebc-72f2-4968-b818-b417fb394a80
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220789084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.3220789084
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.3414261035
Short name T1523
Test name
Test status
Simulation time 21746779955 ps
CPU time 343.51 seconds
Started Aug 08 07:53:20 PM PDT 24
Finished Aug 08 07:59:04 PM PDT 24
Peak memory 575936 kb
Host smart-6326cc5f-48c4-4ec4-b32c-90d325d16888
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414261035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3414261035
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.615167358
Short name T1791
Test name
Test status
Simulation time 69847675 ps
CPU time 8.88 seconds
Started Aug 08 07:53:20 PM PDT 24
Finished Aug 08 07:53:29 PM PDT 24
Peak memory 575784 kb
Host smart-39418bc2-d2e6-436f-b11c-645543daeb9c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615167358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_dela
ys.615167358
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_same_source.1605235965
Short name T1674
Test name
Test status
Simulation time 520291685 ps
CPU time 35.15 seconds
Started Aug 08 07:53:22 PM PDT 24
Finished Aug 08 07:53:58 PM PDT 24
Peak memory 575772 kb
Host smart-37e3e6e2-3605-4f92-b09a-89ba4abe4a75
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605235965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1605235965
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke.1410610428
Short name T2630
Test name
Test status
Simulation time 219037511 ps
CPU time 9.44 seconds
Started Aug 08 07:53:20 PM PDT 24
Finished Aug 08 07:53:29 PM PDT 24
Peak memory 574472 kb
Host smart-c461a49b-ee6c-4e19-bf94-dc072279a8d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410610428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1410610428
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.3449465740
Short name T1900
Test name
Test status
Simulation time 8505097665 ps
CPU time 85.42 seconds
Started Aug 08 07:53:21 PM PDT 24
Finished Aug 08 07:54:47 PM PDT 24
Peak memory 573912 kb
Host smart-32b9e7bb-da50-4b60-a03b-87cd36c9a461
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449465740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3449465740
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.2299452026
Short name T2325
Test name
Test status
Simulation time 4436433692 ps
CPU time 73.3 seconds
Started Aug 08 07:53:21 PM PDT 24
Finished Aug 08 07:54:35 PM PDT 24
Peak memory 573896 kb
Host smart-84a8170b-023f-4efa-8b1c-c858e96e1d9a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299452026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2299452026
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.2803058736
Short name T1513
Test name
Test status
Simulation time 53685439 ps
CPU time 6.1 seconds
Started Aug 08 07:53:20 PM PDT 24
Finished Aug 08 07:53:27 PM PDT 24
Peak memory 574404 kb
Host smart-d07aee12-333a-4c7c-b87a-006c4c1cfada
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803058736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay
s.2803058736
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all.440334136
Short name T2491
Test name
Test status
Simulation time 13613133528 ps
CPU time 481.95 seconds
Started Aug 08 07:53:30 PM PDT 24
Finished Aug 08 08:01:32 PM PDT 24
Peak memory 575900 kb
Host smart-70eaeb70-5325-4f7b-b680-e1b643dfb4a7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440334136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.440334136
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.1795624511
Short name T2919
Test name
Test status
Simulation time 2276548976 ps
CPU time 78.05 seconds
Started Aug 08 07:53:30 PM PDT 24
Finished Aug 08 07:54:48 PM PDT 24
Peak memory 575920 kb
Host smart-ca162de2-cce9-482e-8d2b-ba1f2ba52442
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795624511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1795624511
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.2718662865
Short name T430
Test name
Test status
Simulation time 14675380295 ps
CPU time 633.16 seconds
Started Aug 08 07:53:37 PM PDT 24
Finished Aug 08 08:04:10 PM PDT 24
Peak memory 576768 kb
Host smart-7b43d9ab-fe1c-4ee0-b51f-1788051437d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718662865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all
_with_rand_reset.2718662865
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.370269886
Short name T2059
Test name
Test status
Simulation time 28745923 ps
CPU time 15.04 seconds
Started Aug 08 07:53:30 PM PDT 24
Finished Aug 08 07:53:45 PM PDT 24
Peak memory 576024 kb
Host smart-0583dbe0-1d1c-432f-abb4-1dc73673832c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370269886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all
_with_reset_error.370269886
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.2566683457
Short name T2702
Test name
Test status
Simulation time 674001279 ps
CPU time 31.47 seconds
Started Aug 08 07:53:20 PM PDT 24
Finished Aug 08 07:53:52 PM PDT 24
Peak memory 575784 kb
Host smart-f7fc3605-5381-4119-8f27-60567bfaabcb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566683457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2566683457
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.3965291588
Short name T372
Test name
Test status
Simulation time 6387435156 ps
CPU time 449.93 seconds
Started Aug 08 07:53:54 PM PDT 24
Finished Aug 08 08:01:24 PM PDT 24
Peak memory 637688 kb
Host smart-20fadcc0-6e24-46b2-ac0c-b409d1badd44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965291588 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.3965291588
Directory /workspace/19.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.chip_csr_rw.1008396336
Short name T427
Test name
Test status
Simulation time 5746124312 ps
CPU time 481.01 seconds
Started Aug 08 07:53:52 PM PDT 24
Finished Aug 08 08:01:53 PM PDT 24
Peak memory 597820 kb
Host smart-b4e57951-6591-4210-9918-6e6fd5318868
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008396336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.1008396336
Directory /workspace/19.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.3395693797
Short name T1658
Test name
Test status
Simulation time 14896918314 ps
CPU time 2141.61 seconds
Started Aug 08 07:53:29 PM PDT 24
Finished Aug 08 08:29:11 PM PDT 24
Peak memory 593248 kb
Host smart-f9de60eb-197c-4e92-a7b3-54660a6b3da6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395693797 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.3395693797
Directory /workspace/19.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.chip_tl_errors.696460301
Short name T2811
Test name
Test status
Simulation time 3571177948 ps
CPU time 213.07 seconds
Started Aug 08 07:53:31 PM PDT 24
Finished Aug 08 07:57:04 PM PDT 24
Peak memory 603764 kb
Host smart-617130e1-ab9b-4d8c-98fa-88a73300d07d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696460301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.696460301
Directory /workspace/19.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_access_same_device.1454269453
Short name T2344
Test name
Test status
Simulation time 891712885 ps
CPU time 64.24 seconds
Started Aug 08 07:53:38 PM PDT 24
Finished Aug 08 07:54:42 PM PDT 24
Peak memory 575704 kb
Host smart-82df4909-d35b-4d00-9142-32c5de23830a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454269453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device
.1454269453
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.4070765135
Short name T2604
Test name
Test status
Simulation time 153289133478 ps
CPU time 2750.79 seconds
Started Aug 08 07:53:38 PM PDT 24
Finished Aug 08 08:39:29 PM PDT 24
Peak memory 575912 kb
Host smart-fd5c0980-fdbc-41c0-babd-2b1a6fea86f7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070765135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_
device_slow_rsp.4070765135
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.2264596338
Short name T2494
Test name
Test status
Simulation time 1333946534 ps
CPU time 51.73 seconds
Started Aug 08 07:53:39 PM PDT 24
Finished Aug 08 07:54:30 PM PDT 24
Peak memory 575880 kb
Host smart-3fc6217b-fd81-42a7-bf80-db31be79b6cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264596338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add
r.2264596338
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_error_random.650954226
Short name T1808
Test name
Test status
Simulation time 838153664 ps
CPU time 26.2 seconds
Started Aug 08 07:53:37 PM PDT 24
Finished Aug 08 07:54:03 PM PDT 24
Peak memory 575672 kb
Host smart-0e24447b-eb86-4c12-8ac1-b90d7ccc4dd2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650954226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.650954226
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random.4131876448
Short name T501
Test name
Test status
Simulation time 378219287 ps
CPU time 31.59 seconds
Started Aug 08 07:53:38 PM PDT 24
Finished Aug 08 07:54:09 PM PDT 24
Peak memory 575872 kb
Host smart-18851c0e-bed5-459d-b758-70c5586e97c6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131876448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.4131876448
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.2454001252
Short name T467
Test name
Test status
Simulation time 79531976606 ps
CPU time 773.77 seconds
Started Aug 08 07:53:39 PM PDT 24
Finished Aug 08 08:06:33 PM PDT 24
Peak memory 575996 kb
Host smart-0674604b-163a-4866-9232-59511140fee0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454001252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2454001252
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.1625995291
Short name T2620
Test name
Test status
Simulation time 26829096172 ps
CPU time 478.54 seconds
Started Aug 08 07:53:38 PM PDT 24
Finished Aug 08 08:01:37 PM PDT 24
Peak memory 575952 kb
Host smart-ab508bdd-bce4-4adf-86e4-04db4eea464a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625995291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1625995291
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.4098345964
Short name T1755
Test name
Test status
Simulation time 32539165 ps
CPU time 5.69 seconds
Started Aug 08 07:53:43 PM PDT 24
Finished Aug 08 07:53:48 PM PDT 24
Peak memory 573760 kb
Host smart-6a4cd54e-87ad-42a6-bfed-41bb4f1f9bf9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098345964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del
ays.4098345964
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_same_source.582640605
Short name T2075
Test name
Test status
Simulation time 1147314632 ps
CPU time 36.84 seconds
Started Aug 08 07:53:39 PM PDT 24
Finished Aug 08 07:54:16 PM PDT 24
Peak memory 575748 kb
Host smart-293b7b84-7cbf-4c4f-ace2-cb3c880cc57a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582640605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.582640605
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke.1183060311
Short name T2916
Test name
Test status
Simulation time 169529335 ps
CPU time 7.73 seconds
Started Aug 08 07:53:37 PM PDT 24
Finished Aug 08 07:53:45 PM PDT 24
Peak memory 574476 kb
Host smart-65b0114e-d6ac-4116-931a-ad31eb911d8e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183060311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1183060311
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.2101977014
Short name T2400
Test name
Test status
Simulation time 9523087507 ps
CPU time 101.4 seconds
Started Aug 08 07:53:31 PM PDT 24
Finished Aug 08 07:55:13 PM PDT 24
Peak memory 573908 kb
Host smart-88669f14-8cc2-4c52-b20b-1381493ff8d2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101977014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2101977014
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.1235928113
Short name T2069
Test name
Test status
Simulation time 5197906439 ps
CPU time 81.56 seconds
Started Aug 08 07:53:28 PM PDT 24
Finished Aug 08 07:54:50 PM PDT 24
Peak memory 574584 kb
Host smart-71f8c02a-8988-42db-b693-a06c09b28f3f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235928113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1235928113
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.394006761
Short name T2225
Test name
Test status
Simulation time 49756764 ps
CPU time 6.09 seconds
Started Aug 08 07:53:37 PM PDT 24
Finished Aug 08 07:53:43 PM PDT 24
Peak memory 574520 kb
Host smart-b44cdefe-02f2-47f2-b868-8f0f7ce3c842
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394006761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays
.394006761
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all.2160023317
Short name T2367
Test name
Test status
Simulation time 4215589783 ps
CPU time 327.98 seconds
Started Aug 08 07:53:38 PM PDT 24
Finished Aug 08 07:59:06 PM PDT 24
Peak memory 576788 kb
Host smart-1597ce11-c276-4660-b1ac-11014e8b5ad7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160023317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2160023317
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.2413357441
Short name T2082
Test name
Test status
Simulation time 3077104833 ps
CPU time 118.08 seconds
Started Aug 08 07:53:48 PM PDT 24
Finished Aug 08 07:55:46 PM PDT 24
Peak memory 576020 kb
Host smart-97966991-16f2-4018-92ed-38c38ef4b05d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413357441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2413357441
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.1305292876
Short name T2917
Test name
Test status
Simulation time 4213135423 ps
CPU time 558.98 seconds
Started Aug 08 07:53:41 PM PDT 24
Finished Aug 08 08:03:00 PM PDT 24
Peak memory 576788 kb
Host smart-a46c7eda-9a6f-4fac-b618-3a64ebf386ff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305292876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all
_with_rand_reset.1305292876
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.179411518
Short name T2905
Test name
Test status
Simulation time 1249225773 ps
CPU time 158.73 seconds
Started Aug 08 07:53:47 PM PDT 24
Finished Aug 08 07:56:26 PM PDT 24
Peak memory 575904 kb
Host smart-f75b9303-576e-4240-942a-8b495bbdb79e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179411518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all
_with_reset_error.179411518
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.591383111
Short name T1477
Test name
Test status
Simulation time 821919203 ps
CPU time 33.69 seconds
Started Aug 08 07:53:38 PM PDT 24
Finished Aug 08 07:54:12 PM PDT 24
Peak memory 575904 kb
Host smart-6a479b89-c470-4906-8d8e-8265200e6e6f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591383111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.591383111
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.2700470979
Short name T360
Test name
Test status
Simulation time 30840889556 ps
CPU time 6697.38 seconds
Started Aug 08 07:50:11 PM PDT 24
Finished Aug 08 09:41:49 PM PDT 24
Peak memory 594120 kb
Host smart-e1d0e0a5-2914-4a49-b6b9-2896b53332cd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700470979 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.chip_csr_aliasing.2700470979
Directory /workspace/2.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.4250805306
Short name T1550
Test name
Test status
Simulation time 42457459396 ps
CPU time 4419.63 seconds
Started Aug 08 07:50:07 PM PDT 24
Finished Aug 08 09:03:47 PM PDT 24
Peak memory 593076 kb
Host smart-2d643aba-4058-4530-a876-fbd257129014
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250805306 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.4250805306
Directory /workspace/2.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.227198481
Short name T2371
Test name
Test status
Simulation time 7284007266 ps
CPU time 467.14 seconds
Started Aug 08 07:50:12 PM PDT 24
Finished Aug 08 07:58:00 PM PDT 24
Peak memory 640656 kb
Host smart-8e5c4e3e-dc5d-4d2c-9a6b-3ce64a457207
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227198481 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.227198481
Directory /workspace/2.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_rw.1081315973
Short name T2497
Test name
Test status
Simulation time 5866516974 ps
CPU time 703.81 seconds
Started Aug 08 07:50:11 PM PDT 24
Finished Aug 08 08:01:55 PM PDT 24
Peak memory 599028 kb
Host smart-1d693a03-f7a7-4bc4-983f-934feb981613
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081315973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.1081315973
Directory /workspace/2.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.1303311719
Short name T1551
Test name
Test status
Simulation time 3953182760 ps
CPU time 133.13 seconds
Started Aug 08 07:50:08 PM PDT 24
Finished Aug 08 07:52:21 PM PDT 24
Peak memory 591496 kb
Host smart-8f6b48bb-1b8f-49dc-8c9c-1489b2f75ab7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303311719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.chip_prim_tl_access.1303311719
Directory /workspace/2.chip_prim_tl_access/latest

Test location /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1619106388
Short name T2925
Test name
Test status
Simulation time 11673156049 ps
CPU time 400.51 seconds
Started Aug 08 07:50:10 PM PDT 24
Finished Aug 08 07:56:50 PM PDT 24
Peak memory 589140 kb
Host smart-3ec9f793-7d85-49e6-a562-16a2f1504c93
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619106388 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.chip_rv_dm_lc_disabled.1619106388
Directory /workspace/2.chip_rv_dm_lc_disabled/latest

Test location /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.3100627737
Short name T2546
Test name
Test status
Simulation time 15813810413 ps
CPU time 1911.78 seconds
Started Aug 08 07:50:10 PM PDT 24
Finished Aug 08 08:22:02 PM PDT 24
Peak memory 592368 kb
Host smart-0c44dd3d-0af6-4758-808a-be71c8195b66
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100627737 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.3100627737
Directory /workspace/2.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.chip_tl_errors.2189236664
Short name T2129
Test name
Test status
Simulation time 3117362568 ps
CPU time 229.82 seconds
Started Aug 08 07:50:11 PM PDT 24
Finished Aug 08 07:54:01 PM PDT 24
Peak memory 592408 kb
Host smart-1e2e70c4-ddf7-45ed-beee-dbcf4b9cc0e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189236664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.2189236664
Directory /workspace/2.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_access_same_device.1688756446
Short name T490
Test name
Test status
Simulation time 853356208 ps
CPU time 56.3 seconds
Started Aug 08 07:50:04 PM PDT 24
Finished Aug 08 07:51:01 PM PDT 24
Peak memory 575992 kb
Host smart-3803ca76-2968-4f24-aa59-b5162e96edc6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688756446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.
1688756446
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.923044331
Short name T2797
Test name
Test status
Simulation time 2637658397 ps
CPU time 46.28 seconds
Started Aug 08 07:50:11 PM PDT 24
Finished Aug 08 07:50:57 PM PDT 24
Peak memory 573824 kb
Host smart-6f31c9f2-1e8b-4de5-a24d-c802a3edf562
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923044331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_de
vice_slow_rsp.923044331
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.2571749418
Short name T1402
Test name
Test status
Simulation time 54502473 ps
CPU time 7.68 seconds
Started Aug 08 07:50:10 PM PDT 24
Finished Aug 08 07:50:17 PM PDT 24
Peak memory 574792 kb
Host smart-23e9bbdb-a8ba-4fbc-b487-c38319f7b439
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571749418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr
.2571749418
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_error_random.1070946757
Short name T1401
Test name
Test status
Simulation time 550539471 ps
CPU time 45.76 seconds
Started Aug 08 07:50:10 PM PDT 24
Finished Aug 08 07:50:56 PM PDT 24
Peak memory 575688 kb
Host smart-6986eacf-341e-4069-9fbc-3865421fbed7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070946757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1070946757
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random.3465852028
Short name T549
Test name
Test status
Simulation time 573070112 ps
CPU time 48.19 seconds
Started Aug 08 07:50:07 PM PDT 24
Finished Aug 08 07:50:55 PM PDT 24
Peak memory 575896 kb
Host smart-0b8e136c-8239-4d8a-b6e1-e3c4a0138ce9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465852028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.3465852028
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.3881815704
Short name T2885
Test name
Test status
Simulation time 60832955579 ps
CPU time 623.15 seconds
Started Aug 08 07:50:12 PM PDT 24
Finished Aug 08 08:00:35 PM PDT 24
Peak memory 575984 kb
Host smart-a68322d8-a367-4846-ab9e-aad8383e433f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881815704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3881815704
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.2471218563
Short name T1562
Test name
Test status
Simulation time 4309636302 ps
CPU time 72.84 seconds
Started Aug 08 07:50:07 PM PDT 24
Finished Aug 08 07:51:20 PM PDT 24
Peak memory 573824 kb
Host smart-e95ded3b-af3f-4e2d-a7a4-ec974470ec39
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471218563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2471218563
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.4242757204
Short name T2789
Test name
Test status
Simulation time 574907392 ps
CPU time 52.61 seconds
Started Aug 08 07:50:11 PM PDT 24
Finished Aug 08 07:51:04 PM PDT 24
Peak memory 575800 kb
Host smart-b883cc6a-1190-48fb-b013-fd70c1a1867f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242757204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela
ys.4242757204
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_same_source.774420845
Short name T2566
Test name
Test status
Simulation time 2681590426 ps
CPU time 77.03 seconds
Started Aug 08 07:50:11 PM PDT 24
Finished Aug 08 07:51:28 PM PDT 24
Peak memory 575904 kb
Host smart-2af51a34-7c7f-4c67-8791-a703ba110dd4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774420845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.774420845
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke.3767272197
Short name T2306
Test name
Test status
Simulation time 237720487 ps
CPU time 9.22 seconds
Started Aug 08 07:50:05 PM PDT 24
Finished Aug 08 07:50:15 PM PDT 24
Peak memory 573728 kb
Host smart-aa2e5122-14ba-4c6a-b979-a57b82c2c960
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767272197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3767272197
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.1074475114
Short name T2140
Test name
Test status
Simulation time 9372597647 ps
CPU time 95.68 seconds
Started Aug 08 07:50:06 PM PDT 24
Finished Aug 08 07:51:42 PM PDT 24
Peak memory 574548 kb
Host smart-712918ad-c329-4866-81df-f19ce9e1ccdc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074475114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1074475114
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.2187623220
Short name T2640
Test name
Test status
Simulation time 6250287826 ps
CPU time 102.62 seconds
Started Aug 08 07:50:07 PM PDT 24
Finished Aug 08 07:51:50 PM PDT 24
Peak memory 573920 kb
Host smart-19baf902-f9f4-46b1-a3f6-276b80aa7c55
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187623220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2187623220
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.1196481171
Short name T602
Test name
Test status
Simulation time 62060328 ps
CPU time 6.45 seconds
Started Aug 08 07:50:07 PM PDT 24
Finished Aug 08 07:50:13 PM PDT 24
Peak memory 573792 kb
Host smart-291d7902-1d00-4781-809a-bf2dd311583f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196481171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays
.1196481171
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all.3733743658
Short name T2876
Test name
Test status
Simulation time 19008310817 ps
CPU time 721.09 seconds
Started Aug 08 07:50:07 PM PDT 24
Finished Aug 08 08:02:09 PM PDT 24
Peak memory 576792 kb
Host smart-e2788ab9-f4f9-4c5f-946d-e9e600c723b5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733743658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3733743658
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.1067719385
Short name T1621
Test name
Test status
Simulation time 4362701416 ps
CPU time 132.45 seconds
Started Aug 08 07:50:07 PM PDT 24
Finished Aug 08 07:52:20 PM PDT 24
Peak memory 576088 kb
Host smart-8677cdb8-0c3c-462c-81ad-753dae2277b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067719385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1067719385
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.4218700221
Short name T464
Test name
Test status
Simulation time 12087918131 ps
CPU time 701.67 seconds
Started Aug 08 07:50:06 PM PDT 24
Finished Aug 08 08:01:48 PM PDT 24
Peak memory 576008 kb
Host smart-70921f83-03b3-4710-aac1-b661eb8c183a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218700221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_
with_rand_reset.4218700221
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.3444095292
Short name T830
Test name
Test status
Simulation time 2201112418 ps
CPU time 298.11 seconds
Started Aug 08 07:50:07 PM PDT 24
Finished Aug 08 07:55:06 PM PDT 24
Peak memory 576132 kb
Host smart-cb1d6f3b-3d93-4d10-b59b-edf14b1ee339
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444095292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all
_with_reset_error.3444095292
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.752212571
Short name T2071
Test name
Test status
Simulation time 234239615 ps
CPU time 27 seconds
Started Aug 08 07:50:09 PM PDT 24
Finished Aug 08 07:50:36 PM PDT 24
Peak memory 575928 kb
Host smart-429cdcb3-f92f-45b1-98bf-b412edf8ccb1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752212571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.752212571
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/20.chip_tl_errors.699242399
Short name T2158
Test name
Test status
Simulation time 3737571454 ps
CPU time 251.89 seconds
Started Aug 08 07:53:48 PM PDT 24
Finished Aug 08 07:58:00 PM PDT 24
Peak memory 603916 kb
Host smart-707c54bc-730c-49a8-8a61-e6391b355028
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699242399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.699242399
Directory /workspace/20.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_access_same_device.3140632436
Short name T2933
Test name
Test status
Simulation time 1546310142 ps
CPU time 66.03 seconds
Started Aug 08 07:53:50 PM PDT 24
Finished Aug 08 07:54:56 PM PDT 24
Peak memory 575792 kb
Host smart-6494d83e-a2ce-4a90-b8af-02b4965edc7d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140632436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device
.3140632436
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.881607451
Short name T438
Test name
Test status
Simulation time 36482528465 ps
CPU time 652.62 seconds
Started Aug 08 07:53:54 PM PDT 24
Finished Aug 08 08:04:47 PM PDT 24
Peak memory 576756 kb
Host smart-1cd7c431-6c52-4a9f-95d3-bfd7fe88c32c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881607451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_d
evice_slow_rsp.881607451
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.2617784246
Short name T2332
Test name
Test status
Simulation time 244296633 ps
CPU time 28.15 seconds
Started Aug 08 07:53:59 PM PDT 24
Finished Aug 08 07:54:27 PM PDT 24
Peak memory 575900 kb
Host smart-0a6fece9-6906-4d81-a9d5-d0c8dcdcb813
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617784246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add
r.2617784246
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_error_random.1840978596
Short name T2467
Test name
Test status
Simulation time 1146520584 ps
CPU time 39.74 seconds
Started Aug 08 07:53:48 PM PDT 24
Finished Aug 08 07:54:28 PM PDT 24
Peak memory 575648 kb
Host smart-b09a42ef-c61d-4180-af6a-5313ac39f814
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840978596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1840978596
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random.4194054079
Short name T581
Test name
Test status
Simulation time 1373119175 ps
CPU time 44.57 seconds
Started Aug 08 07:53:49 PM PDT 24
Finished Aug 08 07:54:34 PM PDT 24
Peak memory 575936 kb
Host smart-b63d4c3e-31b5-496c-a011-e8b4cd78e8cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194054079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.4194054079
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.3491180350
Short name T590
Test name
Test status
Simulation time 93846349798 ps
CPU time 953.94 seconds
Started Aug 08 07:53:49 PM PDT 24
Finished Aug 08 08:09:43 PM PDT 24
Peak memory 575944 kb
Host smart-87d90981-74e3-434b-899a-dec11d53abe0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491180350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3491180350
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.2852791329
Short name T2142
Test name
Test status
Simulation time 3654090772 ps
CPU time 64.33 seconds
Started Aug 08 07:53:48 PM PDT 24
Finished Aug 08 07:54:53 PM PDT 24
Peak memory 573840 kb
Host smart-c9d321aa-f1dc-4195-876e-0a41b91e5f2d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852791329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.2852791329
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.3965433963
Short name T2733
Test name
Test status
Simulation time 412289119 ps
CPU time 34.75 seconds
Started Aug 08 07:53:48 PM PDT 24
Finished Aug 08 07:54:22 PM PDT 24
Peak memory 575824 kb
Host smart-4ff73e8a-8b2e-41c5-9669-22b519d53b3a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965433963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del
ays.3965433963
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_same_source.1252385982
Short name T2937
Test name
Test status
Simulation time 1229497444 ps
CPU time 37.42 seconds
Started Aug 08 07:53:49 PM PDT 24
Finished Aug 08 07:54:26 PM PDT 24
Peak memory 575756 kb
Host smart-318563d7-1f1c-4058-b22e-28ef0fd34876
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252385982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1252385982
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke.2328167851
Short name T2900
Test name
Test status
Simulation time 49619754 ps
CPU time 7.32 seconds
Started Aug 08 07:53:47 PM PDT 24
Finished Aug 08 07:53:55 PM PDT 24
Peak memory 574456 kb
Host smart-ac8edc6e-eb0c-4266-aff3-6a0b2bd27a56
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328167851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2328167851
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.274618174
Short name T596
Test name
Test status
Simulation time 8267332432 ps
CPU time 84.79 seconds
Started Aug 08 07:53:57 PM PDT 24
Finished Aug 08 07:55:22 PM PDT 24
Peak memory 573876 kb
Host smart-0fffc330-4b2f-447e-8bce-8dc0cf5616e3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274618174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.274618174
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.988482072
Short name T2826
Test name
Test status
Simulation time 5403372254 ps
CPU time 94.02 seconds
Started Aug 08 07:53:47 PM PDT 24
Finished Aug 08 07:55:21 PM PDT 24
Peak memory 574620 kb
Host smart-beaac246-1400-4c3a-931f-4a27345d5a6b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988482072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.988482072
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.2427860951
Short name T1446
Test name
Test status
Simulation time 42728113 ps
CPU time 6.34 seconds
Started Aug 08 07:53:48 PM PDT 24
Finished Aug 08 07:53:55 PM PDT 24
Peak memory 573788 kb
Host smart-c5c30bfa-8db9-4241-ad45-a5b553813227
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427860951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay
s.2427860951
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all.2919418397
Short name T2455
Test name
Test status
Simulation time 193664823 ps
CPU time 8.55 seconds
Started Aug 08 07:54:02 PM PDT 24
Finished Aug 08 07:54:10 PM PDT 24
Peak memory 573784 kb
Host smart-b4960c0f-fb4e-4b9d-8e52-48757709f221
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919418397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2919418397
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.1753452186
Short name T2823
Test name
Test status
Simulation time 4036423210 ps
CPU time 151.93 seconds
Started Aug 08 07:54:03 PM PDT 24
Finished Aug 08 07:56:35 PM PDT 24
Peak memory 576116 kb
Host smart-c0280d75-174d-4675-93e4-2cf8b192c240
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753452186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1753452186
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.961686616
Short name T2214
Test name
Test status
Simulation time 578356409 ps
CPU time 268.24 seconds
Started Aug 08 07:54:00 PM PDT 24
Finished Aug 08 07:58:28 PM PDT 24
Peak memory 575864 kb
Host smart-6fa2fe31-0052-4884-ad22-ea2d8ec7a418
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961686616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_
with_rand_reset.961686616
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.1537649086
Short name T1926
Test name
Test status
Simulation time 6758324256 ps
CPU time 307.31 seconds
Started Aug 08 07:54:00 PM PDT 24
Finished Aug 08 07:59:07 PM PDT 24
Peak memory 575948 kb
Host smart-5fb264b5-cd2e-41d4-b351-85f4f4829c6c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537649086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al
l_with_reset_error.1537649086
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.1069729360
Short name T2793
Test name
Test status
Simulation time 168100364 ps
CPU time 20.51 seconds
Started Aug 08 07:53:50 PM PDT 24
Finished Aug 08 07:54:10 PM PDT 24
Peak memory 575920 kb
Host smart-870812d5-169f-4199-a6b7-3b60ab94a8cc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069729360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1069729360
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/21.chip_tl_errors.2646166991
Short name T617
Test name
Test status
Simulation time 3027470529 ps
CPU time 160.84 seconds
Started Aug 08 07:53:59 PM PDT 24
Finished Aug 08 07:56:40 PM PDT 24
Peak memory 603712 kb
Host smart-f02c45cc-1426-4089-aee2-61e17a09c567
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646166991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.2646166991
Directory /workspace/21.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_access_same_device.715668602
Short name T1747
Test name
Test status
Simulation time 121452216 ps
CPU time 16.33 seconds
Started Aug 08 07:53:58 PM PDT 24
Finished Aug 08 07:54:15 PM PDT 24
Peak memory 575868 kb
Host smart-c97c8df8-b68e-449a-b752-0d72648b06ac
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715668602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.
715668602
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.54695583
Short name T2159
Test name
Test status
Simulation time 149768484626 ps
CPU time 2718.27 seconds
Started Aug 08 07:54:10 PM PDT 24
Finished Aug 08 08:39:29 PM PDT 24
Peak memory 576708 kb
Host smart-8ebe1cbe-505e-49d7-8cc4-78ab9ee86227
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54695583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_de
vice_slow_rsp.54695583
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.272854697
Short name T1699
Test name
Test status
Simulation time 280558459 ps
CPU time 29.68 seconds
Started Aug 08 07:54:10 PM PDT 24
Finished Aug 08 07:54:40 PM PDT 24
Peak memory 575888 kb
Host smart-b11ee196-17b7-4354-93ef-52db1d6e7ea7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272854697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr
.272854697
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_error_random.2513165829
Short name T1798
Test name
Test status
Simulation time 1255764275 ps
CPU time 39.61 seconds
Started Aug 08 07:54:11 PM PDT 24
Finished Aug 08 07:54:51 PM PDT 24
Peak memory 575672 kb
Host smart-718f4122-7067-4a5a-ab49-648273516ad5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513165829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2513165829
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random.1152312098
Short name T2787
Test name
Test status
Simulation time 246181683 ps
CPU time 22.2 seconds
Started Aug 08 07:53:58 PM PDT 24
Finished Aug 08 07:54:20 PM PDT 24
Peak memory 575904 kb
Host smart-b58ac554-10dd-412d-a0bc-9d05ebeb9712
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152312098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.1152312098
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.817720165
Short name T2061
Test name
Test status
Simulation time 12832912798 ps
CPU time 136.28 seconds
Started Aug 08 07:53:58 PM PDT 24
Finished Aug 08 07:56:15 PM PDT 24
Peak memory 576000 kb
Host smart-b40d5081-7719-47ab-a4dd-8fbeaeded1e9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817720165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.817720165
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.160814117
Short name T2540
Test name
Test status
Simulation time 58539991296 ps
CPU time 1086.63 seconds
Started Aug 08 07:54:03 PM PDT 24
Finished Aug 08 08:12:10 PM PDT 24
Peak memory 575844 kb
Host smart-3b48d035-a1f5-4be1-8899-ed2f41246962
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160814117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.160814117
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.150791930
Short name T2115
Test name
Test status
Simulation time 567632890 ps
CPU time 58.93 seconds
Started Aug 08 07:54:02 PM PDT 24
Finished Aug 08 07:55:01 PM PDT 24
Peak memory 575800 kb
Host smart-79fb3abb-c0d0-427c-b80a-d6a734312949
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150791930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_dela
ys.150791930
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_same_source.3737334243
Short name T2463
Test name
Test status
Simulation time 2092264592 ps
CPU time 59.41 seconds
Started Aug 08 07:54:11 PM PDT 24
Finished Aug 08 07:55:10 PM PDT 24
Peak memory 575820 kb
Host smart-41a7ba7e-0525-426b-9371-efe3526b676f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737334243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3737334243
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke.2283021898
Short name T2707
Test name
Test status
Simulation time 52809386 ps
CPU time 6.74 seconds
Started Aug 08 07:54:01 PM PDT 24
Finished Aug 08 07:54:08 PM PDT 24
Peak memory 573856 kb
Host smart-86486677-ba96-4fa8-b73f-5b83ff3a6264
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283021898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2283021898
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.992252281
Short name T1363
Test name
Test status
Simulation time 9461070530 ps
CPU time 91.78 seconds
Started Aug 08 07:53:58 PM PDT 24
Finished Aug 08 07:55:30 PM PDT 24
Peak memory 574552 kb
Host smart-4acd8f78-d918-400e-819b-665c24b311c4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992252281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.992252281
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.3191023106
Short name T1954
Test name
Test status
Simulation time 5884230318 ps
CPU time 99.27 seconds
Started Aug 08 07:53:59 PM PDT 24
Finished Aug 08 07:55:38 PM PDT 24
Peak memory 573844 kb
Host smart-19dfbcbe-c111-4dd0-bddd-4b8d117325d5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191023106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3191023106
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.2408486494
Short name T1463
Test name
Test status
Simulation time 48163261 ps
CPU time 6.43 seconds
Started Aug 08 07:54:01 PM PDT 24
Finished Aug 08 07:54:08 PM PDT 24
Peak memory 573824 kb
Host smart-ad93d8d4-1c24-4939-892f-b63bf858d5ea
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408486494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay
s.2408486494
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all.1465732284
Short name T1605
Test name
Test status
Simulation time 872366156 ps
CPU time 60.31 seconds
Started Aug 08 07:54:11 PM PDT 24
Finished Aug 08 07:55:11 PM PDT 24
Peak memory 575904 kb
Host smart-f7f4b329-de2a-4f56-a56d-baa19265aa47
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465732284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1465732284
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.873258774
Short name T1388
Test name
Test status
Simulation time 7171340334 ps
CPU time 242.76 seconds
Started Aug 08 07:54:11 PM PDT 24
Finished Aug 08 07:58:14 PM PDT 24
Peak memory 575880 kb
Host smart-efe12de8-81ac-4a7f-b759-64d618946dbb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873258774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.873258774
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.997119466
Short name T2068
Test name
Test status
Simulation time 301133323 ps
CPU time 116.43 seconds
Started Aug 08 07:54:11 PM PDT 24
Finished Aug 08 07:56:07 PM PDT 24
Peak memory 576688 kb
Host smart-619d1c3e-694f-4e79-a9ea-9fd283e3a932
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997119466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_
with_rand_reset.997119466
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.1119019017
Short name T489
Test name
Test status
Simulation time 957296513 ps
CPU time 39.44 seconds
Started Aug 08 07:54:10 PM PDT 24
Finished Aug 08 07:54:50 PM PDT 24
Peak memory 576000 kb
Host smart-1d2da17c-8db2-4548-9022-3081605da526
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119019017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1119019017
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/22.chip_tl_errors.1553847535
Short name T543
Test name
Test status
Simulation time 4162846520 ps
CPU time 332.47 seconds
Started Aug 08 07:54:21 PM PDT 24
Finished Aug 08 07:59:54 PM PDT 24
Peak memory 598676 kb
Host smart-1933705d-5324-4e95-9339-7e9528ee5c68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553847535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.1553847535
Directory /workspace/22.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_access_same_device.1927239272
Short name T2508
Test name
Test status
Simulation time 120630969 ps
CPU time 11.13 seconds
Started Aug 08 07:54:22 PM PDT 24
Finished Aug 08 07:54:33 PM PDT 24
Peak memory 575804 kb
Host smart-0c23fba6-3c78-42aa-9e08-d92577f6344e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927239272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device
.1927239272
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1650752486
Short name T2244
Test name
Test status
Simulation time 243002132 ps
CPU time 26.64 seconds
Started Aug 08 07:54:22 PM PDT 24
Finished Aug 08 07:54:49 PM PDT 24
Peak memory 575688 kb
Host smart-74474368-0aa1-4cd0-9d04-c44b09789118
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650752486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add
r.1650752486
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_error_random.3031237689
Short name T1423
Test name
Test status
Simulation time 533505935 ps
CPU time 38.27 seconds
Started Aug 08 07:54:21 PM PDT 24
Finished Aug 08 07:54:59 PM PDT 24
Peak memory 575900 kb
Host smart-9d772640-f7c4-4f4a-a06a-2018ae6bbb6e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031237689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3031237689
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random.1987443128
Short name T2161
Test name
Test status
Simulation time 2304348693 ps
CPU time 81.88 seconds
Started Aug 08 07:54:22 PM PDT 24
Finished Aug 08 07:55:44 PM PDT 24
Peak memory 575912 kb
Host smart-4e4613ee-0154-42ab-a65c-8b00fc421a90
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987443128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.1987443128
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.194609619
Short name T1981
Test name
Test status
Simulation time 63075336499 ps
CPU time 618.32 seconds
Started Aug 08 07:54:22 PM PDT 24
Finished Aug 08 08:04:40 PM PDT 24
Peak memory 575936 kb
Host smart-b92c1643-cfd3-4db5-b392-ea072c04f552
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194609619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.194609619
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.2916606899
Short name T1744
Test name
Test status
Simulation time 38918161490 ps
CPU time 632.62 seconds
Started Aug 08 07:54:23 PM PDT 24
Finished Aug 08 08:04:56 PM PDT 24
Peak memory 575948 kb
Host smart-7f097c1d-5dd8-493a-a457-181d8eb37cd0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916606899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2916606899
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.2661441620
Short name T2028
Test name
Test status
Simulation time 376023636 ps
CPU time 30.85 seconds
Started Aug 08 07:54:21 PM PDT 24
Finished Aug 08 07:54:52 PM PDT 24
Peak memory 575872 kb
Host smart-b482561a-5a70-42ca-8853-b3c214e08004
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661441620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del
ays.2661441620
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_same_source.2258868345
Short name T1975
Test name
Test status
Simulation time 2205632142 ps
CPU time 72.25 seconds
Started Aug 08 07:54:27 PM PDT 24
Finished Aug 08 07:55:39 PM PDT 24
Peak memory 575952 kb
Host smart-f495a6e2-4ef4-491a-bca0-6222a255a85b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258868345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2258868345
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke.1273178008
Short name T2198
Test name
Test status
Simulation time 181328578 ps
CPU time 9.17 seconds
Started Aug 08 07:54:27 PM PDT 24
Finished Aug 08 07:54:36 PM PDT 24
Peak memory 573840 kb
Host smart-f18cd92b-d070-459c-bbe0-8d39d6d88c26
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273178008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1273178008
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.2375125433
Short name T2290
Test name
Test status
Simulation time 4989456595 ps
CPU time 56.37 seconds
Started Aug 08 07:54:22 PM PDT 24
Finished Aug 08 07:55:19 PM PDT 24
Peak memory 573920 kb
Host smart-40077a5c-121b-4816-81fe-34c851112d90
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375125433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2375125433
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.3663795403
Short name T1377
Test name
Test status
Simulation time 5289022990 ps
CPU time 83.39 seconds
Started Aug 08 07:54:22 PM PDT 24
Finished Aug 08 07:55:46 PM PDT 24
Peak memory 574644 kb
Host smart-563c084f-572c-476e-8c74-10d9a8627487
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663795403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3663795403
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.768159313
Short name T2286
Test name
Test status
Simulation time 50256154 ps
CPU time 6.61 seconds
Started Aug 08 07:54:22 PM PDT 24
Finished Aug 08 07:54:29 PM PDT 24
Peak memory 573756 kb
Host smart-ffe77df2-a554-49c2-9626-04cee8412bd8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768159313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays
.768159313
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all.2478029673
Short name T2197
Test name
Test status
Simulation time 1235894053 ps
CPU time 114.21 seconds
Started Aug 08 07:54:39 PM PDT 24
Finished Aug 08 07:56:33 PM PDT 24
Peak memory 576596 kb
Host smart-3f1b5c17-986e-4956-869d-c7e868bcaf91
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478029673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2478029673
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.3246325767
Short name T781
Test name
Test status
Simulation time 2005485424 ps
CPU time 150.43 seconds
Started Aug 08 07:54:40 PM PDT 24
Finished Aug 08 07:57:10 PM PDT 24
Peak memory 575948 kb
Host smart-d72fceb7-a576-47f8-8d59-f44990b62378
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246325767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3246325767
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.2663964963
Short name T2461
Test name
Test status
Simulation time 3181192362 ps
CPU time 261.92 seconds
Started Aug 08 07:54:39 PM PDT 24
Finished Aug 08 07:59:01 PM PDT 24
Peak memory 575948 kb
Host smart-cc18eaa8-3901-424d-beff-b5ed390026ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663964963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all
_with_rand_reset.2663964963
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3152725901
Short name T2408
Test name
Test status
Simulation time 52953138 ps
CPU time 13.96 seconds
Started Aug 08 07:54:40 PM PDT 24
Finished Aug 08 07:54:54 PM PDT 24
Peak memory 574572 kb
Host smart-3e6ca880-c533-4d6e-82a8-6eb614c2ef92
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152725901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al
l_with_reset_error.3152725901
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.2800040214
Short name T1575
Test name
Test status
Simulation time 80730252 ps
CPU time 5.96 seconds
Started Aug 08 07:54:23 PM PDT 24
Finished Aug 08 07:54:29 PM PDT 24
Peak memory 573820 kb
Host smart-6961e9bb-99a2-439a-98f7-f775c11f6008
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800040214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2800040214
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_access_same_device.387127698
Short name T2532
Test name
Test status
Simulation time 1382532770 ps
CPU time 56.34 seconds
Started Aug 08 07:54:40 PM PDT 24
Finished Aug 08 07:55:36 PM PDT 24
Peak memory 575904 kb
Host smart-9f46816e-5a0c-4e75-b627-d95997a414fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387127698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.
387127698
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.223894560
Short name T800
Test name
Test status
Simulation time 70035112247 ps
CPU time 1234.52 seconds
Started Aug 08 07:54:41 PM PDT 24
Finished Aug 08 08:15:15 PM PDT 24
Peak memory 575976 kb
Host smart-2d3b7784-cdf3-4542-b56e-d5c7de2a1634
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223894560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_d
evice_slow_rsp.223894560
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.2120052731
Short name T2877
Test name
Test status
Simulation time 307021506 ps
CPU time 32.44 seconds
Started Aug 08 07:54:50 PM PDT 24
Finished Aug 08 07:55:23 PM PDT 24
Peak memory 575696 kb
Host smart-ebcb51f9-5935-4e0c-bf57-da15f5b0ab19
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120052731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add
r.2120052731
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_error_random.3633857629
Short name T1427
Test name
Test status
Simulation time 252677029 ps
CPU time 10.05 seconds
Started Aug 08 07:54:39 PM PDT 24
Finished Aug 08 07:54:49 PM PDT 24
Peak memory 575804 kb
Host smart-b32be640-decd-48ae-a5b0-a65fae28da53
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633857629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3633857629
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random.2455704415
Short name T2878
Test name
Test status
Simulation time 2600721443 ps
CPU time 89.07 seconds
Started Aug 08 07:54:39 PM PDT 24
Finished Aug 08 07:56:08 PM PDT 24
Peak memory 575848 kb
Host smart-2cde9852-2cd6-43d7-8915-9851aff16f1e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455704415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.2455704415
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.3045321813
Short name T2556
Test name
Test status
Simulation time 98846810397 ps
CPU time 1123.24 seconds
Started Aug 08 07:54:42 PM PDT 24
Finished Aug 08 08:13:26 PM PDT 24
Peak memory 576052 kb
Host smart-2afe2d0c-bd3c-4871-8251-93b914a9e0a6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045321813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3045321813
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.2865074863
Short name T2424
Test name
Test status
Simulation time 15372407605 ps
CPU time 261.87 seconds
Started Aug 08 07:54:39 PM PDT 24
Finished Aug 08 07:59:01 PM PDT 24
Peak memory 575968 kb
Host smart-2827c3a9-763a-45fc-8475-4dbd3b9e751b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865074863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2865074863
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.804501452
Short name T571
Test name
Test status
Simulation time 651418558 ps
CPU time 49.8 seconds
Started Aug 08 07:54:38 PM PDT 24
Finished Aug 08 07:55:28 PM PDT 24
Peak memory 575804 kb
Host smart-6c33dbb8-d544-4921-8fe4-65196a331b85
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804501452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_dela
ys.804501452
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_same_source.1701742602
Short name T1739
Test name
Test status
Simulation time 63914060 ps
CPU time 8.2 seconds
Started Aug 08 07:54:38 PM PDT 24
Finished Aug 08 07:54:46 PM PDT 24
Peak memory 573832 kb
Host smart-791beda9-a843-4ab3-9013-087ed9a220e0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701742602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1701742602
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke.303098722
Short name T2302
Test name
Test status
Simulation time 207847377 ps
CPU time 9.24 seconds
Started Aug 08 07:54:41 PM PDT 24
Finished Aug 08 07:54:50 PM PDT 24
Peak memory 574432 kb
Host smart-4d0eb3b1-a7bf-41fe-a64c-06df5346f3a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303098722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.303098722
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.545086888
Short name T2741
Test name
Test status
Simulation time 6006362461 ps
CPU time 64.67 seconds
Started Aug 08 07:54:39 PM PDT 24
Finished Aug 08 07:55:43 PM PDT 24
Peak memory 573800 kb
Host smart-07b856b0-a1a1-4e9e-8f5a-4a86aa1bf42d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545086888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.545086888
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.478805918
Short name T2350
Test name
Test status
Simulation time 4853215415 ps
CPU time 85.52 seconds
Started Aug 08 07:54:39 PM PDT 24
Finished Aug 08 07:56:04 PM PDT 24
Peak memory 574524 kb
Host smart-5004f55a-2c80-434d-8651-d62d39cd9d14
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478805918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.478805918
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.348337077
Short name T2097
Test name
Test status
Simulation time 47721676 ps
CPU time 6.7 seconds
Started Aug 08 07:54:38 PM PDT 24
Finished Aug 08 07:54:45 PM PDT 24
Peak memory 573772 kb
Host smart-e357b399-b39a-4a58-8f7c-5a7ef3f5534e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348337077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays
.348337077
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.1030242427
Short name T1799
Test name
Test status
Simulation time 5623681353 ps
CPU time 358.53 seconds
Started Aug 08 07:54:56 PM PDT 24
Finished Aug 08 08:00:55 PM PDT 24
Peak memory 576760 kb
Host smart-d7820757-6fa7-47d6-93d0-5e0ba76c9e14
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030242427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1030242427
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.2355513038
Short name T2730
Test name
Test status
Simulation time 313040177 ps
CPU time 164.06 seconds
Started Aug 08 07:54:57 PM PDT 24
Finished Aug 08 07:57:41 PM PDT 24
Peak memory 576652 kb
Host smart-65a5f62c-83e4-413c-a5b5-7774e777fa16
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355513038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all
_with_rand_reset.2355513038
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.3720397871
Short name T1682
Test name
Test status
Simulation time 179984695 ps
CPU time 43.34 seconds
Started Aug 08 07:54:54 PM PDT 24
Finished Aug 08 07:55:37 PM PDT 24
Peak memory 576056 kb
Host smart-36c27954-d0f3-4832-87ff-161652ad66ee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720397871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al
l_with_reset_error.3720397871
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.1399354090
Short name T2806
Test name
Test status
Simulation time 289613197 ps
CPU time 15.81 seconds
Started Aug 08 07:54:53 PM PDT 24
Finished Aug 08 07:55:09 PM PDT 24
Peak memory 575940 kb
Host smart-bd212dbb-4738-42d3-a150-a08149f92c72
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399354090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1399354090
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/24.chip_tl_errors.165216097
Short name T575
Test name
Test status
Simulation time 4471312878 ps
CPU time 330.62 seconds
Started Aug 08 07:54:56 PM PDT 24
Finished Aug 08 08:00:27 PM PDT 24
Peak memory 598588 kb
Host smart-b69a0c76-4820-46f2-984d-1010b64ace59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165216097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.165216097
Directory /workspace/24.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_access_same_device.2296275612
Short name T1514
Test name
Test status
Simulation time 258944067 ps
CPU time 12.25 seconds
Started Aug 08 07:54:56 PM PDT 24
Finished Aug 08 07:55:08 PM PDT 24
Peak memory 573808 kb
Host smart-4fbf7a4f-8822-49b8-8ca7-7198c4eebb68
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296275612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device
.2296275612
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.4106793050
Short name T2744
Test name
Test status
Simulation time 132786483625 ps
CPU time 2337.48 seconds
Started Aug 08 07:54:54 PM PDT 24
Finished Aug 08 08:33:52 PM PDT 24
Peak memory 576784 kb
Host smart-c672adf6-7f10-4b64-bdcd-ac64d2cc9766
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106793050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_
device_slow_rsp.4106793050
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.1143756777
Short name T1476
Test name
Test status
Simulation time 479047763 ps
CPU time 20.48 seconds
Started Aug 08 07:54:54 PM PDT 24
Finished Aug 08 07:55:15 PM PDT 24
Peak memory 575904 kb
Host smart-676d2c6e-6cc3-4b8f-b8a2-c48830c9f662
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143756777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add
r.1143756777
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_error_random.588968011
Short name T2063
Test name
Test status
Simulation time 333567529 ps
CPU time 14.4 seconds
Started Aug 08 07:54:57 PM PDT 24
Finished Aug 08 07:55:12 PM PDT 24
Peak memory 575628 kb
Host smart-1ac68db6-6f5b-4950-9bac-d574410f23a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588968011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.588968011
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random.1466648790
Short name T2274
Test name
Test status
Simulation time 2206214599 ps
CPU time 82.07 seconds
Started Aug 08 07:54:55 PM PDT 24
Finished Aug 08 07:56:17 PM PDT 24
Peak memory 575844 kb
Host smart-b644aebd-adbe-41b7-87b6-fdbea6401e7c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466648790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.1466648790
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.1424863236
Short name T1702
Test name
Test status
Simulation time 6131458891 ps
CPU time 65.46 seconds
Started Aug 08 07:54:55 PM PDT 24
Finished Aug 08 07:56:00 PM PDT 24
Peak memory 574528 kb
Host smart-d05f0023-6eb1-49d8-86d1-91afc0ba3878
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424863236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1424863236
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.501969812
Short name T2586
Test name
Test status
Simulation time 36725401920 ps
CPU time 576.55 seconds
Started Aug 08 07:54:59 PM PDT 24
Finished Aug 08 08:04:37 PM PDT 24
Peak memory 575972 kb
Host smart-f6b2933d-dc61-4574-88e2-5c1a8e1ef9d2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501969812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.501969812
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.3355842156
Short name T2772
Test name
Test status
Simulation time 116176438 ps
CPU time 11.28 seconds
Started Aug 08 07:54:56 PM PDT 24
Finished Aug 08 07:55:07 PM PDT 24
Peak memory 575864 kb
Host smart-87080aff-9eae-4551-a11e-47a97e41331f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355842156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del
ays.3355842156
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_same_source.3118142876
Short name T2672
Test name
Test status
Simulation time 434112463 ps
CPU time 34.96 seconds
Started Aug 08 07:54:56 PM PDT 24
Finished Aug 08 07:55:31 PM PDT 24
Peak memory 575804 kb
Host smart-41b410a9-53ae-4a1f-960c-74b3832195d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118142876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3118142876
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke.3054281279
Short name T1984
Test name
Test status
Simulation time 232654771 ps
CPU time 9.33 seconds
Started Aug 08 07:54:54 PM PDT 24
Finished Aug 08 07:55:03 PM PDT 24
Peak memory 573852 kb
Host smart-0079247e-af3c-4c67-a2bc-423fdf26d15d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054281279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3054281279
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.4135367151
Short name T1528
Test name
Test status
Simulation time 8980740683 ps
CPU time 91.71 seconds
Started Aug 08 07:54:55 PM PDT 24
Finished Aug 08 07:56:27 PM PDT 24
Peak memory 574572 kb
Host smart-b65c8bab-eda6-4ef5-b29c-6c2680437f5b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135367151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.4135367151
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.1045224702
Short name T1632
Test name
Test status
Simulation time 5413253013 ps
CPU time 99.04 seconds
Started Aug 08 07:54:55 PM PDT 24
Finished Aug 08 07:56:34 PM PDT 24
Peak memory 574544 kb
Host smart-bbc7d94a-d6db-4ec1-912c-8c1a0d2f7698
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045224702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1045224702
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.310858128
Short name T2457
Test name
Test status
Simulation time 41732103 ps
CPU time 6.14 seconds
Started Aug 08 07:54:54 PM PDT 24
Finished Aug 08 07:55:01 PM PDT 24
Peak memory 573708 kb
Host smart-fa5865d8-8039-4e31-8619-e6587cfed9f9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310858128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays
.310858128
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all.1110872314
Short name T2499
Test name
Test status
Simulation time 3605104129 ps
CPU time 294.6 seconds
Started Aug 08 07:54:55 PM PDT 24
Finished Aug 08 07:59:49 PM PDT 24
Peak memory 576800 kb
Host smart-643674cf-83d6-4d0b-b707-c24efa809f0f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110872314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1110872314
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.4107503708
Short name T1649
Test name
Test status
Simulation time 2452187163 ps
CPU time 185.75 seconds
Started Aug 08 07:54:59 PM PDT 24
Finished Aug 08 07:58:05 PM PDT 24
Peak memory 576776 kb
Host smart-da17513a-0d85-4f40-b144-e40504184737
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107503708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.4107503708
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.3784544545
Short name T2923
Test name
Test status
Simulation time 14230035461 ps
CPU time 642.28 seconds
Started Aug 08 07:54:58 PM PDT 24
Finished Aug 08 08:05:41 PM PDT 24
Peak memory 576800 kb
Host smart-b839cbc1-a426-496b-a18b-47f2026f6929
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784544545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al
l_with_reset_error.3784544545
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.1370675856
Short name T1663
Test name
Test status
Simulation time 305198423 ps
CPU time 12.89 seconds
Started Aug 08 07:54:55 PM PDT 24
Finished Aug 08 07:55:08 PM PDT 24
Peak memory 575872 kb
Host smart-fa19d45f-ddf2-421f-931c-9e1125e4703a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370675856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1370675856
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/25.chip_tl_errors.4159106009
Short name T648
Test name
Test status
Simulation time 3620525870 ps
CPU time 226.17 seconds
Started Aug 08 07:54:55 PM PDT 24
Finished Aug 08 07:58:41 PM PDT 24
Peak memory 603716 kb
Host smart-d4fc1a63-1bf2-4378-a51c-6d03d56d27cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159106009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.4159106009
Directory /workspace/25.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_access_same_device.1858249072
Short name T1536
Test name
Test status
Simulation time 149381001 ps
CPU time 12.99 seconds
Started Aug 08 07:55:06 PM PDT 24
Finished Aug 08 07:55:20 PM PDT 24
Peak memory 575712 kb
Host smart-602adb79-5eef-4232-a7e5-564bb58ee281
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858249072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device
.1858249072
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.3960677173
Short name T1945
Test name
Test status
Simulation time 2729177969 ps
CPU time 49.58 seconds
Started Aug 08 07:55:14 PM PDT 24
Finished Aug 08 07:56:04 PM PDT 24
Peak memory 574520 kb
Host smart-cf543cd4-6352-497e-9c2c-d1da57915adb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960677173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_
device_slow_rsp.3960677173
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.197921280
Short name T1352
Test name
Test status
Simulation time 777925227 ps
CPU time 30.39 seconds
Started Aug 08 07:55:08 PM PDT 24
Finished Aug 08 07:55:38 PM PDT 24
Peak memory 575876 kb
Host smart-e13de18c-cbee-439f-9a1d-2f2307ea14ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197921280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr
.197921280
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_error_random.2655417732
Short name T2233
Test name
Test status
Simulation time 473299321 ps
CPU time 40.44 seconds
Started Aug 08 07:55:06 PM PDT 24
Finished Aug 08 07:55:47 PM PDT 24
Peak memory 575848 kb
Host smart-1d01efc0-99c3-4da2-8b00-2c80187e58e7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655417732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2655417732
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random.4154379860
Short name T1734
Test name
Test status
Simulation time 1378741510 ps
CPU time 52.86 seconds
Started Aug 08 07:54:57 PM PDT 24
Finished Aug 08 07:55:50 PM PDT 24
Peak memory 575972 kb
Host smart-fe65a1f6-0707-447d-99f7-28eae45c4731
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154379860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.4154379860
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.3057807608
Short name T2288
Test name
Test status
Simulation time 108550888995 ps
CPU time 1145.65 seconds
Started Aug 08 07:54:54 PM PDT 24
Finished Aug 08 08:14:00 PM PDT 24
Peak memory 576032 kb
Host smart-91c6d707-91f4-488c-b4bd-564b3acdcc06
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057807608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3057807608
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.3839749458
Short name T503
Test name
Test status
Simulation time 37677411657 ps
CPU time 610.47 seconds
Started Aug 08 07:55:14 PM PDT 24
Finished Aug 08 08:05:29 PM PDT 24
Peak memory 575988 kb
Host smart-63824f90-9e05-4f49-ae5c-bbceaac631bb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839749458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3839749458
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.352097714
Short name T1882
Test name
Test status
Simulation time 399451259 ps
CPU time 37.74 seconds
Started Aug 08 07:54:57 PM PDT 24
Finished Aug 08 07:55:35 PM PDT 24
Peak memory 575884 kb
Host smart-5a9654b8-3ba5-4554-b6d8-be3885155641
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352097714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_dela
ys.352097714
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_same_source.4207193500
Short name T2018
Test name
Test status
Simulation time 196062826 ps
CPU time 15 seconds
Started Aug 08 07:55:09 PM PDT 24
Finished Aug 08 07:55:24 PM PDT 24
Peak memory 575828 kb
Host smart-8f7b3ee9-76e0-464e-a957-739323e58320
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207193500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.4207193500
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke.4247624778
Short name T2626
Test name
Test status
Simulation time 208184218 ps
CPU time 8.27 seconds
Started Aug 08 07:54:56 PM PDT 24
Finished Aug 08 07:55:05 PM PDT 24
Peak memory 574436 kb
Host smart-02baa01c-14e5-414b-a52f-35ecb081120f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247624778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.4247624778
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.3616084708
Short name T1726
Test name
Test status
Simulation time 8231218137 ps
CPU time 79.18 seconds
Started Aug 08 07:54:55 PM PDT 24
Finished Aug 08 07:56:14 PM PDT 24
Peak memory 574508 kb
Host smart-d5fc4eff-09fd-4ad3-b34b-6c94c6950681
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616084708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3616084708
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.2509830851
Short name T1353
Test name
Test status
Simulation time 4809171291 ps
CPU time 82.56 seconds
Started Aug 08 07:54:57 PM PDT 24
Finished Aug 08 07:56:19 PM PDT 24
Peak memory 574596 kb
Host smart-b180642a-8592-4afe-b6c0-a92d1a2d787a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509830851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2509830851
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.1374089677
Short name T1361
Test name
Test status
Simulation time 57491107 ps
CPU time 6.35 seconds
Started Aug 08 07:54:54 PM PDT 24
Finished Aug 08 07:55:00 PM PDT 24
Peak memory 573736 kb
Host smart-a1e9d9a8-e89c-4a57-97e6-7340f784d562
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374089677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay
s.1374089677
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all.3339608301
Short name T439
Test name
Test status
Simulation time 11678419048 ps
CPU time 418.42 seconds
Started Aug 08 07:55:14 PM PDT 24
Finished Aug 08 08:02:13 PM PDT 24
Peak memory 576748 kb
Host smart-6f39fd89-a91d-4e52-988c-4be4bee98d87
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339608301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3339608301
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.3604429003
Short name T816
Test name
Test status
Simulation time 4469532643 ps
CPU time 161.6 seconds
Started Aug 08 07:55:07 PM PDT 24
Finished Aug 08 07:57:49 PM PDT 24
Peak memory 575988 kb
Host smart-3827c128-d000-4711-a353-8b40c88b6723
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604429003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3604429003
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.3743032809
Short name T1908
Test name
Test status
Simulation time 7272436 ps
CPU time 9.81 seconds
Started Aug 08 07:55:09 PM PDT 24
Finished Aug 08 07:55:19 PM PDT 24
Peak memory 574448 kb
Host smart-a98f5b82-c31f-4e28-9f3e-6c4565a4c50a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743032809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al
l_with_reset_error.3743032809
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.4120197412
Short name T2705
Test name
Test status
Simulation time 649974151 ps
CPU time 28.48 seconds
Started Aug 08 07:55:09 PM PDT 24
Finished Aug 08 07:55:38 PM PDT 24
Peak memory 575812 kb
Host smart-2f6ef00f-6419-42d7-b149-609b42d23bfb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120197412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.4120197412
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/26.chip_tl_errors.106999217
Short name T540
Test name
Test status
Simulation time 2807147499 ps
CPU time 151.31 seconds
Started Aug 08 07:55:06 PM PDT 24
Finished Aug 08 07:57:37 PM PDT 24
Peak memory 603788 kb
Host smart-a0d1a1d1-9529-4564-be07-fe49d2277e96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106999217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.106999217
Directory /workspace/26.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_access_same_device.2590612468
Short name T2769
Test name
Test status
Simulation time 158072973 ps
CPU time 17.78 seconds
Started Aug 08 07:55:09 PM PDT 24
Finished Aug 08 07:55:27 PM PDT 24
Peak memory 575820 kb
Host smart-0891acb0-5b64-4e09-838a-da1de6f85a4a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590612468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device
.2590612468
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2297958063
Short name T2870
Test name
Test status
Simulation time 139560455253 ps
CPU time 2289.21 seconds
Started Aug 08 07:55:18 PM PDT 24
Finished Aug 08 08:33:28 PM PDT 24
Peak memory 575940 kb
Host smart-e9dc1b99-14f5-400a-8e97-f844637b021e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297958063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_
device_slow_rsp.2297958063
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.1917811699
Short name T669
Test name
Test status
Simulation time 768958586 ps
CPU time 32.88 seconds
Started Aug 08 07:55:19 PM PDT 24
Finished Aug 08 07:55:52 PM PDT 24
Peak memory 575744 kb
Host smart-329c609a-627e-4b9c-82de-945f39eb9a3a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917811699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add
r.1917811699
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_error_random.2269584803
Short name T1607
Test name
Test status
Simulation time 247481827 ps
CPU time 11.29 seconds
Started Aug 08 07:55:19 PM PDT 24
Finished Aug 08 07:55:30 PM PDT 24
Peak memory 575856 kb
Host smart-0454e315-4c81-4245-aea2-fef37686b8ae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269584803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2269584803
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random.1907366232
Short name T2023
Test name
Test status
Simulation time 704778047 ps
CPU time 25.75 seconds
Started Aug 08 07:55:06 PM PDT 24
Finished Aug 08 07:55:32 PM PDT 24
Peak memory 575792 kb
Host smart-c7b16013-6db1-4007-9922-32c805675f3b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907366232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.1907366232
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.3749497520
Short name T2441
Test name
Test status
Simulation time 48924640942 ps
CPU time 535 seconds
Started Aug 08 07:55:09 PM PDT 24
Finished Aug 08 08:04:04 PM PDT 24
Peak memory 575984 kb
Host smart-13218e7e-39b8-4fc7-b7ac-60ff6e35cc9d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749497520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3749497520
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.3476992328
Short name T2548
Test name
Test status
Simulation time 38609958563 ps
CPU time 635.8 seconds
Started Aug 08 07:55:09 PM PDT 24
Finished Aug 08 08:05:45 PM PDT 24
Peak memory 576012 kb
Host smart-496cdd43-8e34-4471-a13d-ebee97bcfad5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476992328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3476992328
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.699794039
Short name T2613
Test name
Test status
Simulation time 321805717 ps
CPU time 31.45 seconds
Started Aug 08 07:55:06 PM PDT 24
Finished Aug 08 07:55:37 PM PDT 24
Peak memory 575880 kb
Host smart-37a1c76c-0b75-4efa-b5c9-9527fdda34e6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699794039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_dela
ys.699794039
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_same_source.4129485621
Short name T2761
Test name
Test status
Simulation time 604996215 ps
CPU time 20.31 seconds
Started Aug 08 07:55:19 PM PDT 24
Finished Aug 08 07:55:40 PM PDT 24
Peak memory 575864 kb
Host smart-b66a07f4-89ba-42aa-bd52-e654ba4e0184
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129485621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.4129485621
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke.1626319287
Short name T2739
Test name
Test status
Simulation time 200288952 ps
CPU time 8.93 seconds
Started Aug 08 07:55:06 PM PDT 24
Finished Aug 08 07:55:15 PM PDT 24
Peak memory 574472 kb
Host smart-464e08e4-e99f-42c5-be3c-a79e31b8d51e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626319287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1626319287
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.3732867043
Short name T1673
Test name
Test status
Simulation time 5491821379 ps
CPU time 61.06 seconds
Started Aug 08 07:55:07 PM PDT 24
Finished Aug 08 07:56:08 PM PDT 24
Peak memory 573884 kb
Host smart-a55ed751-7465-47ad-9402-82d06b1a82f6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732867043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3732867043
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.2186514803
Short name T2525
Test name
Test status
Simulation time 4438324726 ps
CPU time 65.99 seconds
Started Aug 08 07:55:06 PM PDT 24
Finished Aug 08 07:56:12 PM PDT 24
Peak memory 573840 kb
Host smart-62292c48-6a5a-46c9-b025-ce24a862eb14
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186514803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.2186514803
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.728329997
Short name T1766
Test name
Test status
Simulation time 42070392 ps
CPU time 6.17 seconds
Started Aug 08 07:55:08 PM PDT 24
Finished Aug 08 07:55:14 PM PDT 24
Peak memory 573788 kb
Host smart-0ca8bcc3-238d-4f36-af6a-4137f71b6c3f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728329997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays
.728329997
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all.3936840817
Short name T2915
Test name
Test status
Simulation time 2088509088 ps
CPU time 188.15 seconds
Started Aug 08 07:55:18 PM PDT 24
Finished Aug 08 07:58:26 PM PDT 24
Peak memory 575904 kb
Host smart-5e88ef83-1800-421a-9e57-40151e4a3ed7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936840817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3936840817
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.3098706518
Short name T1692
Test name
Test status
Simulation time 2322630724 ps
CPU time 69.13 seconds
Started Aug 08 07:55:19 PM PDT 24
Finished Aug 08 07:56:28 PM PDT 24
Peak memory 575964 kb
Host smart-ab96bceb-5cc8-4231-92a3-f47829ae98f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098706518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3098706518
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.3222824938
Short name T844
Test name
Test status
Simulation time 392434518 ps
CPU time 125.68 seconds
Started Aug 08 07:55:28 PM PDT 24
Finished Aug 08 07:57:34 PM PDT 24
Peak memory 576576 kb
Host smart-8c6a8db2-5f0e-4725-a767-d2bf82c5295e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222824938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all
_with_rand_reset.3222824938
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2165138398
Short name T2684
Test name
Test status
Simulation time 774599981 ps
CPU time 172.04 seconds
Started Aug 08 07:55:19 PM PDT 24
Finished Aug 08 07:58:11 PM PDT 24
Peak memory 576712 kb
Host smart-e0053313-9083-442d-a345-ae3e1ed6366f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165138398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al
l_with_reset_error.2165138398
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.1997420021
Short name T2666
Test name
Test status
Simulation time 93232615 ps
CPU time 6.93 seconds
Started Aug 08 07:55:18 PM PDT 24
Finished Aug 08 07:55:25 PM PDT 24
Peak memory 574484 kb
Host smart-b65a50fd-5294-40c8-a311-1b504c33956d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997420021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1997420021
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_access_same_device.1832900166
Short name T2270
Test name
Test status
Simulation time 975566068 ps
CPU time 80.06 seconds
Started Aug 08 07:55:21 PM PDT 24
Finished Aug 08 07:56:41 PM PDT 24
Peak memory 575892 kb
Host smart-3470dbea-813f-40d8-91f4-86b3c7c5245a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832900166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device
.1832900166
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.3873896544
Short name T807
Test name
Test status
Simulation time 31595318057 ps
CPU time 491.72 seconds
Started Aug 08 07:55:28 PM PDT 24
Finished Aug 08 08:03:40 PM PDT 24
Peak memory 575896 kb
Host smart-d06c5475-eca4-47da-9adf-46447e4d5b4e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873896544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_
device_slow_rsp.3873896544
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.3782835141
Short name T1609
Test name
Test status
Simulation time 199455482 ps
CPU time 24.07 seconds
Started Aug 08 07:55:30 PM PDT 24
Finished Aug 08 07:55:54 PM PDT 24
Peak memory 575680 kb
Host smart-5017d38d-8cd2-4595-8c10-b9d81248785a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782835141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add
r.3782835141
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_error_random.2699021556
Short name T1802
Test name
Test status
Simulation time 460284517 ps
CPU time 36.16 seconds
Started Aug 08 07:55:34 PM PDT 24
Finished Aug 08 07:56:10 PM PDT 24
Peak memory 575620 kb
Host smart-bdd1a4c8-d960-485b-ab14-338031a2c91a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699021556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2699021556
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random.3557714469
Short name T473
Test name
Test status
Simulation time 1778196470 ps
CPU time 62.24 seconds
Started Aug 08 07:55:19 PM PDT 24
Finished Aug 08 07:56:21 PM PDT 24
Peak memory 575860 kb
Host smart-7f31a2ba-3738-4d4b-b49d-923a018fb354
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557714469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.3557714469
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.254521648
Short name T1594
Test name
Test status
Simulation time 95514279022 ps
CPU time 1043.65 seconds
Started Aug 08 07:55:19 PM PDT 24
Finished Aug 08 08:12:43 PM PDT 24
Peak memory 575900 kb
Host smart-04ac7adb-762d-4874-aa76-091332ee5620
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254521648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.254521648
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.546663045
Short name T1950
Test name
Test status
Simulation time 4275526873 ps
CPU time 73.78 seconds
Started Aug 08 07:55:28 PM PDT 24
Finished Aug 08 07:56:42 PM PDT 24
Peak memory 574456 kb
Host smart-3b9fbd8b-486c-4179-8bec-728f09058659
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546663045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.546663045
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.2117593243
Short name T1683
Test name
Test status
Simulation time 76860788 ps
CPU time 8.86 seconds
Started Aug 08 07:55:20 PM PDT 24
Finished Aug 08 07:55:29 PM PDT 24
Peak memory 575792 kb
Host smart-073cdac5-56a6-4873-bfbc-4bff2741b59e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117593243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del
ays.2117593243
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_same_source.4024576573
Short name T2398
Test name
Test status
Simulation time 933167720 ps
CPU time 29.64 seconds
Started Aug 08 07:55:30 PM PDT 24
Finished Aug 08 07:56:00 PM PDT 24
Peak memory 575756 kb
Host smart-bbeb564a-c5b9-4f4e-945b-b5a83a9501ba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024576573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.4024576573
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke.1332721179
Short name T1754
Test name
Test status
Simulation time 176274078 ps
CPU time 8.89 seconds
Started Aug 08 07:55:19 PM PDT 24
Finished Aug 08 07:55:28 PM PDT 24
Peak memory 573728 kb
Host smart-609b7f2c-695f-4aaf-96a8-ae9dc4ea255c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332721179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1332721179
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.1044860115
Short name T1878
Test name
Test status
Simulation time 10390680832 ps
CPU time 111.21 seconds
Started Aug 08 07:55:28 PM PDT 24
Finished Aug 08 07:57:19 PM PDT 24
Peak memory 574540 kb
Host smart-298455a5-0b25-4c85-89f1-3e33c55c0ae4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044860115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1044860115
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.3566522219
Short name T2134
Test name
Test status
Simulation time 4431322407 ps
CPU time 76.37 seconds
Started Aug 08 07:55:19 PM PDT 24
Finished Aug 08 07:56:35 PM PDT 24
Peak memory 574588 kb
Host smart-21456a92-8cdc-43fa-93aa-87f29faf1776
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566522219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3566522219
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.2531166220
Short name T1647
Test name
Test status
Simulation time 49522731 ps
CPU time 6.08 seconds
Started Aug 08 07:55:19 PM PDT 24
Finished Aug 08 07:55:25 PM PDT 24
Peak memory 573768 kb
Host smart-9efd03d7-49f0-410a-9cdc-97849237ec2e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531166220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay
s.2531166220
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all.1514541528
Short name T565
Test name
Test status
Simulation time 4800899212 ps
CPU time 166.66 seconds
Started Aug 08 07:55:30 PM PDT 24
Finished Aug 08 07:58:17 PM PDT 24
Peak memory 576012 kb
Host smart-914db8f0-a284-49ec-b7e2-dde624748a8e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514541528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1514541528
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.3372232708
Short name T2466
Test name
Test status
Simulation time 4331306007 ps
CPU time 131.14 seconds
Started Aug 08 07:55:30 PM PDT 24
Finished Aug 08 07:57:42 PM PDT 24
Peak memory 575852 kb
Host smart-edacb28a-865a-4d81-822b-528df5422cef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372232708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3372232708
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.2560448775
Short name T584
Test name
Test status
Simulation time 1187868099 ps
CPU time 239.67 seconds
Started Aug 08 07:55:36 PM PDT 24
Finished Aug 08 07:59:36 PM PDT 24
Peak memory 575972 kb
Host smart-2d62182c-6159-48bf-9909-8d0652e7b3a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560448775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all
_with_rand_reset.2560448775
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3777464364
Short name T1610
Test name
Test status
Simulation time 608388990 ps
CPU time 153.45 seconds
Started Aug 08 07:55:31 PM PDT 24
Finished Aug 08 07:58:05 PM PDT 24
Peak memory 576720 kb
Host smart-ec6d8a61-9355-48aa-93c8-64402411732f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777464364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al
l_with_reset_error.3777464364
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.270555895
Short name T1396
Test name
Test status
Simulation time 841899913 ps
CPU time 33.02 seconds
Started Aug 08 07:55:32 PM PDT 24
Finished Aug 08 07:56:05 PM PDT 24
Peak memory 575792 kb
Host smart-ffb8ffb6-dfa0-4ca6-9f84-54793247bb33
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270555895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.270555895
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/28.chip_tl_errors.2490786943
Short name T2920
Test name
Test status
Simulation time 2996321565 ps
CPU time 203.6 seconds
Started Aug 08 07:55:36 PM PDT 24
Finished Aug 08 07:58:59 PM PDT 24
Peak memory 598928 kb
Host smart-60379189-1316-492a-bd36-4ff681ddd1fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490786943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.2490786943
Directory /workspace/28.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_access_same_device.288635541
Short name T2030
Test name
Test status
Simulation time 3327784637 ps
CPU time 124 seconds
Started Aug 08 07:55:43 PM PDT 24
Finished Aug 08 07:57:47 PM PDT 24
Peak memory 575912 kb
Host smart-2f9b272e-31a7-42b9-bd85-612f4054707e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288635541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.
288635541
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.3796306347
Short name T2622
Test name
Test status
Simulation time 46784687275 ps
CPU time 814.41 seconds
Started Aug 08 07:55:42 PM PDT 24
Finished Aug 08 08:09:17 PM PDT 24
Peak memory 576716 kb
Host smart-a9549b20-b042-4ded-918b-68ac5eaf2348
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796306347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_
device_slow_rsp.3796306347
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.2514797792
Short name T2010
Test name
Test status
Simulation time 1383035994 ps
CPU time 56.16 seconds
Started Aug 08 07:55:42 PM PDT 24
Finished Aug 08 07:56:39 PM PDT 24
Peak memory 575900 kb
Host smart-5571f7c2-ba07-4297-9606-8b0c301ec5d9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514797792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add
r.2514797792
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random.605344188
Short name T559
Test name
Test status
Simulation time 629407670 ps
CPU time 25.77 seconds
Started Aug 08 07:55:37 PM PDT 24
Finished Aug 08 07:56:03 PM PDT 24
Peak memory 575748 kb
Host smart-ef727098-788d-48d0-9043-cc7f5990efff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605344188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.605344188
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.11744903
Short name T442
Test name
Test status
Simulation time 96628436378 ps
CPU time 1026.35 seconds
Started Aug 08 07:55:50 PM PDT 24
Finished Aug 08 08:12:57 PM PDT 24
Peak memory 575876 kb
Host smart-4bff982d-0039-4cff-b7f3-8b614876e0c0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11744903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.11744903
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.3433301316
Short name T2034
Test name
Test status
Simulation time 33404928555 ps
CPU time 551.49 seconds
Started Aug 08 07:55:54 PM PDT 24
Finished Aug 08 08:05:06 PM PDT 24
Peak memory 576764 kb
Host smart-dc95975c-6645-4972-a28b-2e7b0e606ceb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433301316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3433301316
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.2656956233
Short name T485
Test name
Test status
Simulation time 556746183 ps
CPU time 43.9 seconds
Started Aug 08 07:55:54 PM PDT 24
Finished Aug 08 07:56:38 PM PDT 24
Peak memory 575712 kb
Host smart-510b47de-d297-4bfa-a315-f744c70a42da
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656956233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del
ays.2656956233
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_same_source.1009046296
Short name T1668
Test name
Test status
Simulation time 493660472 ps
CPU time 16.58 seconds
Started Aug 08 07:55:54 PM PDT 24
Finished Aug 08 07:56:11 PM PDT 24
Peak memory 575768 kb
Host smart-f1a35507-8893-4dae-bdd3-219aa0daf120
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009046296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1009046296
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke.2492827101
Short name T1925
Test name
Test status
Simulation time 46052009 ps
CPU time 6.18 seconds
Started Aug 08 07:55:32 PM PDT 24
Finished Aug 08 07:55:39 PM PDT 24
Peak memory 573856 kb
Host smart-0ddc3a2c-508b-44f6-959f-6fc45eca9c03
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492827101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2492827101
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.919397917
Short name T1644
Test name
Test status
Simulation time 8549333698 ps
CPU time 91.26 seconds
Started Aug 08 07:55:33 PM PDT 24
Finished Aug 08 07:57:04 PM PDT 24
Peak memory 574596 kb
Host smart-772cdc7f-ff77-4615-bc45-06b77ee225cd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919397917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.919397917
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.2414419190
Short name T541
Test name
Test status
Simulation time 4312479285 ps
CPU time 74.5 seconds
Started Aug 08 07:55:35 PM PDT 24
Finished Aug 08 07:56:50 PM PDT 24
Peak memory 573904 kb
Host smart-d49e0a35-c419-41d4-9933-0786bdb9d3e7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414419190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2414419190
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.3119389986
Short name T2032
Test name
Test status
Simulation time 43738792 ps
CPU time 6.15 seconds
Started Aug 08 07:55:30 PM PDT 24
Finished Aug 08 07:55:37 PM PDT 24
Peak memory 573700 kb
Host smart-70aeefe2-803d-435e-9ad4-70e881249022
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119389986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay
s.3119389986
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all.3273930974
Short name T1672
Test name
Test status
Simulation time 9821832017 ps
CPU time 306.45 seconds
Started Aug 08 07:55:46 PM PDT 24
Finished Aug 08 08:00:52 PM PDT 24
Peak memory 575888 kb
Host smart-fdff382b-b089-4641-83ba-78a872792c37
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273930974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3273930974
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.680993696
Short name T1653
Test name
Test status
Simulation time 2333743321 ps
CPU time 188.92 seconds
Started Aug 08 07:55:43 PM PDT 24
Finished Aug 08 07:58:52 PM PDT 24
Peak memory 575952 kb
Host smart-82f44b5a-97aa-4044-978a-f1e98371aec7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680993696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.680993696
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1038765618
Short name T1805
Test name
Test status
Simulation time 7023687828 ps
CPU time 643.24 seconds
Started Aug 08 07:55:53 PM PDT 24
Finished Aug 08 08:06:37 PM PDT 24
Peak memory 575920 kb
Host smart-3c8f2ebb-c2be-4aeb-bbb6-f4022fb95f1f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038765618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al
l_with_reset_error.1038765618
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.1869572219
Short name T2035
Test name
Test status
Simulation time 286977786 ps
CPU time 14.27 seconds
Started Aug 08 07:55:51 PM PDT 24
Finished Aug 08 07:56:05 PM PDT 24
Peak memory 575848 kb
Host smart-a7dccfd8-4f2a-4fc0-9684-784aa1504bf0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869572219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1869572219
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/29.chip_tl_errors.2710389770
Short name T2751
Test name
Test status
Simulation time 3863410394 ps
CPU time 166.84 seconds
Started Aug 08 07:55:58 PM PDT 24
Finished Aug 08 07:58:45 PM PDT 24
Peak memory 603628 kb
Host smart-fb65b1be-d147-4a60-87a7-67c5c1dd3d28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710389770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.2710389770
Directory /workspace/29.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_access_same_device.328824436
Short name T804
Test name
Test status
Simulation time 2915907842 ps
CPU time 106.64 seconds
Started Aug 08 07:56:01 PM PDT 24
Finished Aug 08 07:57:47 PM PDT 24
Peak memory 575960 kb
Host smart-e4e66b42-ce06-4a31-9352-0104d91d08dd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328824436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.
328824436
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.1360952789
Short name T1879
Test name
Test status
Simulation time 33582376838 ps
CPU time 598.02 seconds
Started Aug 08 07:55:57 PM PDT 24
Finished Aug 08 08:05:55 PM PDT 24
Peak memory 575960 kb
Host smart-d41c48b5-08a8-4e40-b39c-1fd15c180de9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360952789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_
device_slow_rsp.1360952789
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2021312248
Short name T2208
Test name
Test status
Simulation time 553966397 ps
CPU time 20.74 seconds
Started Aug 08 07:55:58 PM PDT 24
Finished Aug 08 07:56:19 PM PDT 24
Peak memory 575748 kb
Host smart-1570a787-7239-48f8-9f24-9f142b6bf521
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021312248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add
r.2021312248
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_error_random.2298594067
Short name T2356
Test name
Test status
Simulation time 2136300434 ps
CPU time 71.91 seconds
Started Aug 08 07:55:54 PM PDT 24
Finished Aug 08 07:57:06 PM PDT 24
Peak memory 575776 kb
Host smart-52cd10b3-4907-4788-a472-fd1ea81333ee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298594067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2298594067
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random.1172603843
Short name T2421
Test name
Test status
Simulation time 1641577343 ps
CPU time 58.02 seconds
Started Aug 08 07:55:45 PM PDT 24
Finished Aug 08 07:56:43 PM PDT 24
Peak memory 575820 kb
Host smart-02069ad3-a6ab-41a4-adf2-5aa298975c31
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172603843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.1172603843
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.2499775702
Short name T2523
Test name
Test status
Simulation time 16439863040 ps
CPU time 165.24 seconds
Started Aug 08 07:55:52 PM PDT 24
Finished Aug 08 07:58:37 PM PDT 24
Peak memory 576688 kb
Host smart-5e9b8edc-d7f5-40e9-8d6a-6e33548908f7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499775702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2499775702
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.3905465718
Short name T2698
Test name
Test status
Simulation time 10245182894 ps
CPU time 163.02 seconds
Started Aug 08 07:55:54 PM PDT 24
Finished Aug 08 07:58:37 PM PDT 24
Peak memory 575932 kb
Host smart-268a5a33-3fcf-4ea2-bf74-759c010cbb7c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905465718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3905465718
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.3068463419
Short name T1570
Test name
Test status
Simulation time 69328339 ps
CPU time 9.77 seconds
Started Aug 08 07:55:54 PM PDT 24
Finished Aug 08 07:56:03 PM PDT 24
Peak memory 575884 kb
Host smart-5ff69a27-e286-479d-8eea-9b34bd5709f2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068463419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del
ays.3068463419
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_same_source.3672621690
Short name T2352
Test name
Test status
Simulation time 522193100 ps
CPU time 34.95 seconds
Started Aug 08 07:56:00 PM PDT 24
Finished Aug 08 07:56:35 PM PDT 24
Peak memory 575760 kb
Host smart-f7b52d4b-7e09-430d-94fa-ccdbebcd81fa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672621690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3672621690
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke.1310294966
Short name T1484
Test name
Test status
Simulation time 223542406 ps
CPU time 9.35 seconds
Started Aug 08 07:55:42 PM PDT 24
Finished Aug 08 07:55:51 PM PDT 24
Peak memory 574472 kb
Host smart-45a5b002-2869-4f01-acbe-8d5d6203a92d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310294966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.1310294966
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.691708448
Short name T2409
Test name
Test status
Simulation time 5497822411 ps
CPU time 58.31 seconds
Started Aug 08 07:55:42 PM PDT 24
Finished Aug 08 07:56:41 PM PDT 24
Peak memory 574628 kb
Host smart-f69fa4a4-6313-4622-bb0c-cc875d26cf16
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691708448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.691708448
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.1394483995
Short name T1863
Test name
Test status
Simulation time 4359230885 ps
CPU time 76.2 seconds
Started Aug 08 07:55:45 PM PDT 24
Finished Aug 08 07:57:02 PM PDT 24
Peak memory 574512 kb
Host smart-931e4247-65cc-4e01-80da-34e01925fa64
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394483995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1394483995
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.593701236
Short name T1898
Test name
Test status
Simulation time 37940961 ps
CPU time 5.87 seconds
Started Aug 08 07:55:43 PM PDT 24
Finished Aug 08 07:55:49 PM PDT 24
Peak memory 573804 kb
Host smart-2228c396-2f23-4058-bf73-4dbadba5f659
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593701236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays
.593701236
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all.313471174
Short name T2187
Test name
Test status
Simulation time 1634269544 ps
CPU time 129.4 seconds
Started Aug 08 07:55:59 PM PDT 24
Finished Aug 08 07:58:09 PM PDT 24
Peak memory 576572 kb
Host smart-6f67560d-e01f-4365-942b-9161c52859b1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313471174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.313471174
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.3287407899
Short name T2654
Test name
Test status
Simulation time 1562087394 ps
CPU time 127.34 seconds
Started Aug 08 07:56:01 PM PDT 24
Finished Aug 08 07:58:08 PM PDT 24
Peak memory 575976 kb
Host smart-e0abb621-45fa-4228-8a22-cfca0dd03496
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287407899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3287407899
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2144631641
Short name T835
Test name
Test status
Simulation time 579914183 ps
CPU time 273.99 seconds
Started Aug 08 07:56:07 PM PDT 24
Finished Aug 08 08:00:41 PM PDT 24
Peak memory 575840 kb
Host smart-32fbde61-aac3-4211-8cfc-3712be5066b5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144631641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all
_with_rand_reset.2144631641
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.4075126626
Short name T852
Test name
Test status
Simulation time 18380087629 ps
CPU time 780.59 seconds
Started Aug 08 07:55:58 PM PDT 24
Finished Aug 08 08:08:59 PM PDT 24
Peak memory 576760 kb
Host smart-cc409dc0-74ed-410e-b700-c97e44afc157
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075126626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al
l_with_reset_error.4075126626
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.705783684
Short name T1393
Test name
Test status
Simulation time 88432811 ps
CPU time 13.41 seconds
Started Aug 08 07:55:53 PM PDT 24
Finished Aug 08 07:56:07 PM PDT 24
Peak memory 575988 kb
Host smart-c6cd54f9-170e-4abf-ab7e-ea800b8c92c4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705783684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.705783684
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.3444006933
Short name T1733
Test name
Test status
Simulation time 56606013572 ps
CPU time 10595.3 seconds
Started Aug 08 07:50:06 PM PDT 24
Finished Aug 08 10:46:42 PM PDT 24
Peak memory 643496 kb
Host smart-53841a35-21b2-43ea-99b0-c89287f630e0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444006933 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.chip_csr_aliasing.3444006933
Directory /workspace/3.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.2370535481
Short name T621
Test name
Test status
Simulation time 6824709059 ps
CPU time 714.63 seconds
Started Aug 08 07:50:07 PM PDT 24
Finished Aug 08 08:02:02 PM PDT 24
Peak memory 592560 kb
Host smart-6bbf938d-9f0d-485e-8cc2-bef4e57d964e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370535481 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.2370535481
Directory /workspace/3.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.1209916320
Short name T362
Test name
Test status
Simulation time 5426986618 ps
CPU time 239.09 seconds
Started Aug 08 07:50:18 PM PDT 24
Finished Aug 08 07:54:17 PM PDT 24
Peak memory 659240 kb
Host smart-cd6c7880-af8e-4da4-99bf-7bc500af952c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209916320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r
eset.1209916320
Directory /workspace/3.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.612577033
Short name T2237
Test name
Test status
Simulation time 11220370548 ps
CPU time 855.94 seconds
Started Aug 08 07:50:17 PM PDT 24
Finished Aug 08 08:04:33 PM PDT 24
Peak memory 645712 kb
Host smart-01506da7-1c26-4955-9ebd-05534c54c74a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612577033 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.612577033
Directory /workspace/3.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_rw.3370614881
Short name T388
Test name
Test status
Simulation time 4241431300 ps
CPU time 284.37 seconds
Started Aug 08 07:50:15 PM PDT 24
Finished Aug 08 07:54:59 PM PDT 24
Peak memory 598816 kb
Host smart-a1903ae1-f36c-407a-bd8e-d6f4405510dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370614881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.3370614881
Directory /workspace/3.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.199679984
Short name T1909
Test name
Test status
Simulation time 17023911539 ps
CPU time 2311.63 seconds
Started Aug 08 07:50:06 PM PDT 24
Finished Aug 08 08:28:38 PM PDT 24
Peak memory 593312 kb
Host smart-293eb947-e16e-4dc9-a856-16196e17b5e4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199679984 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.chip_same_csr_outstanding.199679984
Directory /workspace/3.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.chip_tl_errors.3975353301
Short name T616
Test name
Test status
Simulation time 3099689645 ps
CPU time 209.3 seconds
Started Aug 08 07:50:11 PM PDT 24
Finished Aug 08 07:53:40 PM PDT 24
Peak memory 598560 kb
Host smart-358805b7-f3a8-4fab-8c53-e464703dd530
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975353301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.3975353301
Directory /workspace/3.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_access_same_device.2825880878
Short name T2295
Test name
Test status
Simulation time 2257277316 ps
CPU time 77.28 seconds
Started Aug 08 07:50:14 PM PDT 24
Finished Aug 08 07:51:31 PM PDT 24
Peak memory 575820 kb
Host smart-563be066-5804-4eec-8dd9-410adc619a65
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825880878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.
2825880878
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.466793521
Short name T1788
Test name
Test status
Simulation time 102396851789 ps
CPU time 1780.51 seconds
Started Aug 08 07:50:18 PM PDT 24
Finished Aug 08 08:20:00 PM PDT 24
Peak memory 575924 kb
Host smart-2b509aec-b37e-4c17-8d55-495cd7c4f5fb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466793521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_de
vice_slow_rsp.466793521
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.99703574
Short name T1657
Test name
Test status
Simulation time 846063654 ps
CPU time 30.8 seconds
Started Aug 08 07:50:21 PM PDT 24
Finished Aug 08 07:50:52 PM PDT 24
Peak memory 575924 kb
Host smart-7713e8a0-f242-476a-b7de-a5ff7a2a92ba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99703574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.99703574
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_error_random.2793704161
Short name T1889
Test name
Test status
Simulation time 295997386 ps
CPU time 24.24 seconds
Started Aug 08 07:50:23 PM PDT 24
Finished Aug 08 07:50:47 PM PDT 24
Peak memory 575860 kb
Host smart-39b3b1dd-5114-44c9-8e2a-7336cff1f315
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793704161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2793704161
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random.304003083
Short name T1566
Test name
Test status
Simulation time 466854059 ps
CPU time 20.53 seconds
Started Aug 08 07:50:22 PM PDT 24
Finished Aug 08 07:50:43 PM PDT 24
Peak memory 575880 kb
Host smart-72d1492e-c80d-42e9-a019-a8a3b2de9b81
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304003083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.304003083
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.1908920876
Short name T1966
Test name
Test status
Simulation time 38191677544 ps
CPU time 429.85 seconds
Started Aug 08 07:50:18 PM PDT 24
Finished Aug 08 07:57:28 PM PDT 24
Peak memory 576000 kb
Host smart-180a3e62-4353-4828-8afb-0adcd2a7d208
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908920876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1908920876
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.688858189
Short name T2031
Test name
Test status
Simulation time 29106783018 ps
CPU time 459.34 seconds
Started Aug 08 07:50:23 PM PDT 24
Finished Aug 08 07:58:03 PM PDT 24
Peak memory 575988 kb
Host smart-b2e793cd-e92b-44d5-819c-adf8baa28c53
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688858189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.688858189
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.2036834357
Short name T2056
Test name
Test status
Simulation time 238194690 ps
CPU time 22.63 seconds
Started Aug 08 07:50:24 PM PDT 24
Finished Aug 08 07:50:46 PM PDT 24
Peak memory 575864 kb
Host smart-725f23cc-d353-4354-97ae-da5fbabf8fe2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036834357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela
ys.2036834357
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_same_source.524225771
Short name T572
Test name
Test status
Simulation time 451957347 ps
CPU time 34.84 seconds
Started Aug 08 07:50:24 PM PDT 24
Finished Aug 08 07:50:59 PM PDT 24
Peak memory 576068 kb
Host smart-45c6fbf3-d105-448f-bf34-38b139749ad2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524225771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.524225771
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke.2991622999
Short name T1348
Test name
Test status
Simulation time 208918712 ps
CPU time 8.41 seconds
Started Aug 08 07:50:06 PM PDT 24
Finished Aug 08 07:50:14 PM PDT 24
Peak memory 574500 kb
Host smart-f1917ae4-947c-49da-957c-dfb5756935d7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991622999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2991622999
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.1266774069
Short name T2126
Test name
Test status
Simulation time 8288176618 ps
CPU time 82.93 seconds
Started Aug 08 07:50:18 PM PDT 24
Finished Aug 08 07:51:41 PM PDT 24
Peak memory 573912 kb
Host smart-8c5c2ff5-1775-420f-8fe5-a9529fb7462f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266774069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1266774069
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.1132247083
Short name T2617
Test name
Test status
Simulation time 3464995794 ps
CPU time 58.49 seconds
Started Aug 08 07:50:16 PM PDT 24
Finished Aug 08 07:51:15 PM PDT 24
Peak memory 574576 kb
Host smart-8dd84e71-44c5-44c1-9128-3cfd7e88961e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132247083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1132247083
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.2331464107
Short name T1354
Test name
Test status
Simulation time 48570377 ps
CPU time 6.21 seconds
Started Aug 08 07:50:07 PM PDT 24
Finished Aug 08 07:50:13 PM PDT 24
Peak memory 574516 kb
Host smart-2a6c51be-fe9b-46ba-994e-d2817295275a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331464107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays
.2331464107
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all.23628840
Short name T2049
Test name
Test status
Simulation time 3153620887 ps
CPU time 118.4 seconds
Started Aug 08 07:50:16 PM PDT 24
Finished Aug 08 07:52:15 PM PDT 24
Peak memory 576076 kb
Host smart-87a1f7f3-5953-46a5-99d6-6b518ab977b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23628840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.23628840
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.3569169599
Short name T2567
Test name
Test status
Simulation time 555024649 ps
CPU time 36.22 seconds
Started Aug 08 07:50:18 PM PDT 24
Finished Aug 08 07:50:54 PM PDT 24
Peak memory 575988 kb
Host smart-d3063554-50f8-4f1d-ba85-43b08f03eb81
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569169599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3569169599
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.2278716555
Short name T1661
Test name
Test status
Simulation time 600556598 ps
CPU time 144.86 seconds
Started Aug 08 07:50:15 PM PDT 24
Finished Aug 08 07:52:40 PM PDT 24
Peak memory 575900 kb
Host smart-e2b03392-e024-4bbe-8371-9774b626427e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278716555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_
with_rand_reset.2278716555
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1746682479
Short name T2165
Test name
Test status
Simulation time 695771966 ps
CPU time 238.32 seconds
Started Aug 08 07:50:14 PM PDT 24
Finished Aug 08 07:54:12 PM PDT 24
Peak memory 576732 kb
Host smart-1b9b7cbe-bf06-460b-a667-0ed0bfbdead4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746682479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all
_with_reset_error.1746682479
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.2816941294
Short name T2449
Test name
Test status
Simulation time 250926394 ps
CPU time 13.35 seconds
Started Aug 08 07:50:20 PM PDT 24
Finished Aug 08 07:50:34 PM PDT 24
Peak memory 575784 kb
Host smart-0546f5b3-19d5-45ad-9ddf-0313d300a1e3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816941294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2816941294
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_access_same_device.2530793238
Short name T2673
Test name
Test status
Simulation time 244335453 ps
CPU time 12.56 seconds
Started Aug 08 07:56:07 PM PDT 24
Finished Aug 08 07:56:20 PM PDT 24
Peak memory 573816 kb
Host smart-c86674e6-1642-4b03-b0d9-2dd935486e0a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530793238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device
.2530793238
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.3268536858
Short name T1973
Test name
Test status
Simulation time 86900057192 ps
CPU time 1522.9 seconds
Started Aug 08 07:56:06 PM PDT 24
Finished Aug 08 08:21:29 PM PDT 24
Peak memory 575968 kb
Host smart-14320d67-c498-46b8-a2ab-9cf8fc3d3cb6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268536858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_
device_slow_rsp.3268536858
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.364997813
Short name T1438
Test name
Test status
Simulation time 175015913 ps
CPU time 16.9 seconds
Started Aug 08 07:56:12 PM PDT 24
Finished Aug 08 07:56:29 PM PDT 24
Peak memory 575764 kb
Host smart-01d965a5-a180-458f-9e43-6083c07a71a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364997813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr
.364997813
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_error_random.82947978
Short name T1585
Test name
Test status
Simulation time 397086278 ps
CPU time 31.2 seconds
Started Aug 08 07:56:13 PM PDT 24
Finished Aug 08 07:56:44 PM PDT 24
Peak memory 575804 kb
Host smart-530c58f6-0f34-4086-a50b-d650a2cbcec9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82947978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.82947978
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random.3733464936
Short name T1910
Test name
Test status
Simulation time 2396101240 ps
CPU time 93.31 seconds
Started Aug 08 07:55:54 PM PDT 24
Finished Aug 08 07:57:28 PM PDT 24
Peak memory 575924 kb
Host smart-e273fe2c-5258-4671-96ed-0e90f7ab764f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733464936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.3733464936
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.1240985798
Short name T1962
Test name
Test status
Simulation time 5915353488 ps
CPU time 60.03 seconds
Started Aug 08 07:56:13 PM PDT 24
Finished Aug 08 07:57:13 PM PDT 24
Peak memory 573956 kb
Host smart-54169c4b-958f-43db-a2fa-bad5c1f682b3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240985798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1240985798
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.3061082992
Short name T1404
Test name
Test status
Simulation time 22222358160 ps
CPU time 372.75 seconds
Started Aug 08 07:56:12 PM PDT 24
Finished Aug 08 08:02:25 PM PDT 24
Peak memory 575996 kb
Host smart-419c92a2-f605-4f20-b4b5-a5c04a052f1f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061082992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3061082992
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.4035859930
Short name T2264
Test name
Test status
Simulation time 331226901 ps
CPU time 28.33 seconds
Started Aug 08 07:55:53 PM PDT 24
Finished Aug 08 07:56:21 PM PDT 24
Peak memory 575860 kb
Host smart-428b7489-5f0a-4f95-a7a9-f9634a9c9754
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035859930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del
ays.4035859930
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_same_source.2105549122
Short name T2275
Test name
Test status
Simulation time 578537217 ps
CPU time 40.63 seconds
Started Aug 08 07:56:05 PM PDT 24
Finished Aug 08 07:56:46 PM PDT 24
Peak memory 575888 kb
Host smart-60bf9ee0-9362-43cd-a1e1-cb6461f32159
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105549122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2105549122
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke.4090334375
Short name T1819
Test name
Test status
Simulation time 220742452 ps
CPU time 9.14 seconds
Started Aug 08 07:56:00 PM PDT 24
Finished Aug 08 07:56:09 PM PDT 24
Peak memory 573844 kb
Host smart-e0ccc0a8-9185-4062-bfc5-884beaae8b62
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090334375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.4090334375
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.2272507416
Short name T1804
Test name
Test status
Simulation time 9922105084 ps
CPU time 103.09 seconds
Started Aug 08 07:55:56 PM PDT 24
Finished Aug 08 07:57:39 PM PDT 24
Peak memory 574504 kb
Host smart-f9eae02f-07db-4c7d-914b-84f831574d56
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272507416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2272507416
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.1815600500
Short name T1556
Test name
Test status
Simulation time 5225858753 ps
CPU time 88.02 seconds
Started Aug 08 07:55:55 PM PDT 24
Finished Aug 08 07:57:23 PM PDT 24
Peak memory 574636 kb
Host smart-8bb313ac-af25-4a39-bcef-4244c0cc5f5c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815600500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1815600500
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.879439304
Short name T2512
Test name
Test status
Simulation time 47446668 ps
CPU time 6.29 seconds
Started Aug 08 07:56:00 PM PDT 24
Finished Aug 08 07:56:07 PM PDT 24
Peak memory 573712 kb
Host smart-3749082e-1ef9-411c-abad-11b7f7e117c1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879439304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays
.879439304
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.2756701263
Short name T2612
Test name
Test status
Simulation time 10925376257 ps
CPU time 368.25 seconds
Started Aug 08 07:56:07 PM PDT 24
Finished Aug 08 08:02:16 PM PDT 24
Peak memory 575888 kb
Host smart-31a8f5c3-a2d9-4cc5-9db0-62550b3f60ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756701263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2756701263
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.2100702162
Short name T1548
Test name
Test status
Simulation time 4187319318 ps
CPU time 262.15 seconds
Started Aug 08 07:56:08 PM PDT 24
Finished Aug 08 08:00:30 PM PDT 24
Peak memory 575980 kb
Host smart-94731324-50c0-4144-9da6-241862ac5126
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100702162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all
_with_rand_reset.2100702162
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.4198885332
Short name T1505
Test name
Test status
Simulation time 172317309 ps
CPU time 21.72 seconds
Started Aug 08 07:56:13 PM PDT 24
Finished Aug 08 07:56:35 PM PDT 24
Peak memory 575864 kb
Host smart-09d92501-f7c8-4634-a8e8-927b95022458
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198885332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.4198885332
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_access_same_device.588408924
Short name T2940
Test name
Test status
Simulation time 2086708694 ps
CPU time 92.02 seconds
Started Aug 08 07:56:17 PM PDT 24
Finished Aug 08 07:57:49 PM PDT 24
Peak memory 575936 kb
Host smart-b7355b4b-5ba1-4604-87ff-43726094a609
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588408924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.
588408924
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.4124153414
Short name T1572
Test name
Test status
Simulation time 3210614149 ps
CPU time 56.05 seconds
Started Aug 08 07:56:15 PM PDT 24
Finished Aug 08 07:57:11 PM PDT 24
Peak memory 573912 kb
Host smart-187fa93e-1b4f-463c-979d-cf7b8e7877d8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124153414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_
device_slow_rsp.4124153414
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.2906266450
Short name T2425
Test name
Test status
Simulation time 132020933 ps
CPU time 8.44 seconds
Started Aug 08 07:56:15 PM PDT 24
Finished Aug 08 07:56:24 PM PDT 24
Peak memory 573856 kb
Host smart-fb1735f0-a9be-45cb-b7bb-25d6e214841b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906266450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add
r.2906266450
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_error_random.2270234836
Short name T2830
Test name
Test status
Simulation time 1718991806 ps
CPU time 65.95 seconds
Started Aug 08 07:56:16 PM PDT 24
Finished Aug 08 07:57:22 PM PDT 24
Peak memory 575644 kb
Host smart-9eb7acd5-63b9-4d56-8f5b-d4372129c1fb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270234836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2270234836
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random.1931601787
Short name T2921
Test name
Test status
Simulation time 135444052 ps
CPU time 7.85 seconds
Started Aug 08 07:56:05 PM PDT 24
Finished Aug 08 07:56:13 PM PDT 24
Peak memory 574496 kb
Host smart-8e3b4ff0-4359-48a7-baa1-cdd863907cce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931601787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.1931601787
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.3658796724
Short name T1701
Test name
Test status
Simulation time 45380593663 ps
CPU time 493.66 seconds
Started Aug 08 07:56:08 PM PDT 24
Finished Aug 08 08:04:21 PM PDT 24
Peak memory 576760 kb
Host smart-ea0d7802-73c4-47f9-bb0b-a8b355c875da
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658796724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3658796724
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.3609853021
Short name T2172
Test name
Test status
Simulation time 7924388554 ps
CPU time 131.82 seconds
Started Aug 08 07:56:15 PM PDT 24
Finished Aug 08 07:58:27 PM PDT 24
Peak memory 576756 kb
Host smart-68d040b8-6d1f-46ca-a936-9955068a2772
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609853021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3609853021
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.1465411495
Short name T2011
Test name
Test status
Simulation time 263685144 ps
CPU time 25.98 seconds
Started Aug 08 07:56:08 PM PDT 24
Finished Aug 08 07:56:34 PM PDT 24
Peak memory 575856 kb
Host smart-22d9c2e1-3ff8-4c53-acb2-dd29e8dc3786
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465411495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del
ays.1465411495
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_same_source.582824917
Short name T569
Test name
Test status
Simulation time 1292027919 ps
CPU time 40.9 seconds
Started Aug 08 07:56:15 PM PDT 24
Finished Aug 08 07:56:56 PM PDT 24
Peak memory 575752 kb
Host smart-75ec5fc5-0164-4884-becc-7a71a9a79264
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582824917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.582824917
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke.4091263448
Short name T2644
Test name
Test status
Simulation time 45372939 ps
CPU time 6.13 seconds
Started Aug 08 07:56:14 PM PDT 24
Finished Aug 08 07:56:20 PM PDT 24
Peak memory 574436 kb
Host smart-bceed1fc-3abc-4011-97a3-447f36bb6300
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091263448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.4091263448
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.83746616
Short name T2574
Test name
Test status
Simulation time 6013259122 ps
CPU time 61.02 seconds
Started Aug 08 07:56:05 PM PDT 24
Finished Aug 08 07:57:06 PM PDT 24
Peak memory 574584 kb
Host smart-fdd74a54-1637-47f1-afcd-1a76ca8af27e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83746616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.83746616
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.1501892449
Short name T1457
Test name
Test status
Simulation time 4617040443 ps
CPU time 75.36 seconds
Started Aug 08 07:56:06 PM PDT 24
Finished Aug 08 07:57:21 PM PDT 24
Peak memory 573928 kb
Host smart-252a2252-a3aa-4cb7-9147-0708d442a49a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501892449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1501892449
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.2893238927
Short name T2699
Test name
Test status
Simulation time 43400723 ps
CPU time 6.46 seconds
Started Aug 08 07:56:06 PM PDT 24
Finished Aug 08 07:56:13 PM PDT 24
Peak memory 573768 kb
Host smart-ac3968b7-b127-486f-be21-68356a42a6b4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893238927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay
s.2893238927
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all.2764370218
Short name T2343
Test name
Test status
Simulation time 11563330813 ps
CPU time 354.69 seconds
Started Aug 08 07:56:15 PM PDT 24
Finished Aug 08 08:02:10 PM PDT 24
Peak memory 576752 kb
Host smart-0f81dc27-d40f-4e59-9660-a25798e83e79
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764370218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2764370218
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.737946164
Short name T1695
Test name
Test status
Simulation time 5518367 ps
CPU time 3.81 seconds
Started Aug 08 07:56:14 PM PDT 24
Finished Aug 08 07:56:18 PM PDT 24
Peak memory 565584 kb
Host smart-962b7afa-2b4a-42e2-b0cb-ddc18c910962
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737946164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.737946164
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.3054544460
Short name T1714
Test name
Test status
Simulation time 1060002123 ps
CPU time 213.65 seconds
Started Aug 08 07:56:17 PM PDT 24
Finished Aug 08 07:59:50 PM PDT 24
Peak memory 576692 kb
Host smart-8cbd3e4f-bbae-42cc-865f-7178db82f87a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054544460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all
_with_rand_reset.3054544460
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2740388485
Short name T837
Test name
Test status
Simulation time 3226041013 ps
CPU time 228.22 seconds
Started Aug 08 07:56:16 PM PDT 24
Finished Aug 08 08:00:04 PM PDT 24
Peak memory 575920 kb
Host smart-fabda4b3-6d6a-4b0a-bf43-60c8112cb6a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740388485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al
l_with_reset_error.2740388485
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.41267912
Short name T1370
Test name
Test status
Simulation time 122996442 ps
CPU time 17.82 seconds
Started Aug 08 07:56:17 PM PDT 24
Finished Aug 08 07:56:35 PM PDT 24
Peak memory 575880 kb
Host smart-0dd4c5f1-d2dc-477b-97a4-b67bdaaf043c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41267912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.41267912
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_access_same_device.2915159493
Short name T805
Test name
Test status
Simulation time 1686843244 ps
CPU time 59.63 seconds
Started Aug 08 07:56:24 PM PDT 24
Finished Aug 08 07:57:24 PM PDT 24
Peak memory 575908 kb
Host smart-e199cf0b-b742-4250-ae49-ff22a2390862
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915159493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device
.2915159493
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.2469116446
Short name T793
Test name
Test status
Simulation time 70227206040 ps
CPU time 1161.12 seconds
Started Aug 08 07:56:24 PM PDT 24
Finished Aug 08 08:15:45 PM PDT 24
Peak memory 576000 kb
Host smart-65b91a0d-510b-4e78-a07f-3c9aeb266b94
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469116446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_
device_slow_rsp.2469116446
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.874148293
Short name T2557
Test name
Test status
Simulation time 128765321 ps
CPU time 15.05 seconds
Started Aug 08 07:56:25 PM PDT 24
Finished Aug 08 07:56:40 PM PDT 24
Peak memory 575712 kb
Host smart-2663d55f-93ce-4b3a-9090-bf02cc40398c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874148293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr
.874148293
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_error_random.2387481820
Short name T2310
Test name
Test status
Simulation time 99797474 ps
CPU time 9.93 seconds
Started Aug 08 07:56:26 PM PDT 24
Finished Aug 08 07:56:36 PM PDT 24
Peak memory 575672 kb
Host smart-e8603e7d-fe94-4477-b87b-2efce6fd8379
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387481820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2387481820
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random.703964404
Short name T1545
Test name
Test status
Simulation time 362200390 ps
CPU time 31.36 seconds
Started Aug 08 07:56:25 PM PDT 24
Finished Aug 08 07:56:57 PM PDT 24
Peak memory 575992 kb
Host smart-58e1a90f-3105-48b0-9889-6272b5fa1d09
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703964404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.703964404
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.1240568069
Short name T2509
Test name
Test status
Simulation time 68857844982 ps
CPU time 789.79 seconds
Started Aug 08 07:56:24 PM PDT 24
Finished Aug 08 08:09:34 PM PDT 24
Peak memory 575964 kb
Host smart-abdb513f-4bd6-4048-bca0-cb30b3a54ecb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240568069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1240568069
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.2246992143
Short name T2670
Test name
Test status
Simulation time 3265652719 ps
CPU time 56.14 seconds
Started Aug 08 07:56:28 PM PDT 24
Finished Aug 08 07:57:24 PM PDT 24
Peak memory 574512 kb
Host smart-b84f228a-d93c-4089-8285-38564e7615eb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246992143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2246992143
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.3588216387
Short name T2236
Test name
Test status
Simulation time 540405725 ps
CPU time 41.22 seconds
Started Aug 08 07:56:27 PM PDT 24
Finished Aug 08 07:57:08 PM PDT 24
Peak memory 575720 kb
Host smart-dbf3f5d5-3b00-4c5a-bac1-1b8500454586
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588216387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del
ays.3588216387
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_same_source.2532566784
Short name T491
Test name
Test status
Simulation time 1184667624 ps
CPU time 33.42 seconds
Started Aug 08 07:56:26 PM PDT 24
Finished Aug 08 07:56:59 PM PDT 24
Peak memory 575736 kb
Host smart-fcf86599-1132-4e44-a6ec-73ccf256fffb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532566784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2532566784
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke.2835050894
Short name T2855
Test name
Test status
Simulation time 44765478 ps
CPU time 6.76 seconds
Started Aug 08 07:56:15 PM PDT 24
Finished Aug 08 07:56:22 PM PDT 24
Peak memory 573720 kb
Host smart-0ab09700-7414-4d10-82b8-6e630f585314
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835050894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2835050894
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.2741724623
Short name T2663
Test name
Test status
Simulation time 6837082392 ps
CPU time 70.99 seconds
Started Aug 08 07:56:18 PM PDT 24
Finished Aug 08 07:57:29 PM PDT 24
Peak memory 573900 kb
Host smart-cbe20a04-5d80-4807-afd4-30be99f626b1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741724623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2741724623
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.3366090228
Short name T2339
Test name
Test status
Simulation time 4261610741 ps
CPU time 76.47 seconds
Started Aug 08 07:56:25 PM PDT 24
Finished Aug 08 07:57:41 PM PDT 24
Peak memory 573852 kb
Host smart-d41ad84e-b121-4a23-ab88-5bbdeab36369
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366090228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3366090228
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.2063107007
Short name T2847
Test name
Test status
Simulation time 45088609 ps
CPU time 6.28 seconds
Started Aug 08 07:56:14 PM PDT 24
Finished Aug 08 07:56:21 PM PDT 24
Peak memory 573916 kb
Host smart-ff021ee3-2ea8-47f4-8c89-ad5c460556bd
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063107007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay
s.2063107007
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all.2746784770
Short name T2088
Test name
Test status
Simulation time 4739553014 ps
CPU time 189.28 seconds
Started Aug 08 07:56:25 PM PDT 24
Finished Aug 08 07:59:34 PM PDT 24
Peak memory 576000 kb
Host smart-55142d56-35b7-4157-abe6-370e091d5895
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746784770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2746784770
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.3750892706
Short name T1469
Test name
Test status
Simulation time 5821204 ps
CPU time 3.78 seconds
Started Aug 08 07:56:35 PM PDT 24
Finished Aug 08 07:56:39 PM PDT 24
Peak memory 565528 kb
Host smart-b83640f1-be98-465b-bd8b-ea2e82501212
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750892706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3750892706
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.3899903627
Short name T834
Test name
Test status
Simulation time 465803419 ps
CPU time 105.39 seconds
Started Aug 08 07:56:25 PM PDT 24
Finished Aug 08 07:58:10 PM PDT 24
Peak memory 576664 kb
Host smart-6423d0e4-0f4f-4fdd-9d03-e03dd70a69a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899903627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all
_with_rand_reset.3899903627
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.4218581668
Short name T2592
Test name
Test status
Simulation time 116153443 ps
CPU time 29.24 seconds
Started Aug 08 07:56:38 PM PDT 24
Finished Aug 08 07:57:07 PM PDT 24
Peak memory 575940 kb
Host smart-632cb9ea-e023-4d28-a527-dead71ada44e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218581668 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al
l_with_reset_error.4218581668
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.664889017
Short name T1979
Test name
Test status
Simulation time 128884011 ps
CPU time 18.13 seconds
Started Aug 08 07:56:27 PM PDT 24
Finished Aug 08 07:56:45 PM PDT 24
Peak memory 575904 kb
Host smart-bbe5eb2b-008f-45ef-a5e4-e62c6b24d7ef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664889017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.664889017
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_access_same_device.367934450
Short name T2169
Test name
Test status
Simulation time 788795610 ps
CPU time 29.99 seconds
Started Aug 08 07:56:35 PM PDT 24
Finished Aug 08 07:57:05 PM PDT 24
Peak memory 575760 kb
Host smart-347dc57e-b328-4914-88ca-ed9ab46b64ea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367934450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.
367934450
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1818455686
Short name T2027
Test name
Test status
Simulation time 38960644016 ps
CPU time 700.21 seconds
Started Aug 08 07:56:36 PM PDT 24
Finished Aug 08 08:08:16 PM PDT 24
Peak memory 576776 kb
Host smart-9f794b55-8d1e-466d-af21-1885256fcd1c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818455686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_
device_slow_rsp.1818455686
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.2549944620
Short name T2474
Test name
Test status
Simulation time 466499140 ps
CPU time 20.71 seconds
Started Aug 08 07:56:39 PM PDT 24
Finished Aug 08 07:56:59 PM PDT 24
Peak memory 575860 kb
Host smart-6ec099fc-2bfb-4206-8fd2-e31e8b8bf862
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549944620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add
r.2549944620
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_error_random.54749045
Short name T1604
Test name
Test status
Simulation time 436711775 ps
CPU time 30.33 seconds
Started Aug 08 07:56:35 PM PDT 24
Finished Aug 08 07:57:05 PM PDT 24
Peak memory 575728 kb
Host smart-3fafd065-aa00-42a7-adc2-a8d506c57b71
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54749045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.54749045
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random.3338388444
Short name T1406
Test name
Test status
Simulation time 328179429 ps
CPU time 23.81 seconds
Started Aug 08 07:56:35 PM PDT 24
Finished Aug 08 07:56:59 PM PDT 24
Peak memory 575936 kb
Host smart-7c6e2958-3ea0-4113-ad79-f7d757419585
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338388444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.3338388444
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.833865702
Short name T2792
Test name
Test status
Simulation time 104009796215 ps
CPU time 1113.88 seconds
Started Aug 08 07:56:35 PM PDT 24
Finished Aug 08 08:15:09 PM PDT 24
Peak memory 575972 kb
Host smart-c7fa8c51-fe48-4075-84f8-56909d08cda6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833865702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.833865702
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.1865861902
Short name T1931
Test name
Test status
Simulation time 35772099953 ps
CPU time 622.31 seconds
Started Aug 08 07:56:34 PM PDT 24
Finished Aug 08 08:06:56 PM PDT 24
Peak memory 576020 kb
Host smart-33d6b108-2e60-40e5-b654-14601feaeeb7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865861902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1865861902
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.959296125
Short name T1854
Test name
Test status
Simulation time 438762652 ps
CPU time 45.45 seconds
Started Aug 08 07:56:34 PM PDT 24
Finished Aug 08 07:57:20 PM PDT 24
Peak memory 575732 kb
Host smart-2dd8fbcb-a3f8-4df2-a4a4-aa172797af82
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959296125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_dela
ys.959296125
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_same_source.1593109297
Short name T2163
Test name
Test status
Simulation time 340088405 ps
CPU time 24.29 seconds
Started Aug 08 07:56:35 PM PDT 24
Finished Aug 08 07:57:00 PM PDT 24
Peak memory 575912 kb
Host smart-7a19a64c-c935-4a8b-be55-c3b05d961852
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593109297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1593109297
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke.1386644530
Short name T1920
Test name
Test status
Simulation time 55948181 ps
CPU time 6.66 seconds
Started Aug 08 07:56:35 PM PDT 24
Finished Aug 08 07:56:42 PM PDT 24
Peak memory 573800 kb
Host smart-4363c600-6c92-4c6c-a1ab-26027218b5ac
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386644530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1386644530
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.2414186050
Short name T2038
Test name
Test status
Simulation time 9867594622 ps
CPU time 107.92 seconds
Started Aug 08 07:56:37 PM PDT 24
Finished Aug 08 07:58:25 PM PDT 24
Peak memory 573916 kb
Host smart-9ed85e3c-ce80-4c9b-b9f3-59dd93f53aea
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414186050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2414186050
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.1955202785
Short name T2854
Test name
Test status
Simulation time 3712977544 ps
CPU time 60.06 seconds
Started Aug 08 07:56:34 PM PDT 24
Finished Aug 08 07:57:34 PM PDT 24
Peak memory 573836 kb
Host smart-8199ad6f-447d-4563-8021-c0635f4d6aa6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955202785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1955202785
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.1695919952
Short name T1498
Test name
Test status
Simulation time 44641254 ps
CPU time 6.11 seconds
Started Aug 08 07:56:35 PM PDT 24
Finished Aug 08 07:56:41 PM PDT 24
Peak memory 574432 kb
Host smart-37b6b8a7-10a1-4587-8933-702d1d5f44a4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695919952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay
s.1695919952
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all.2548347279
Short name T1521
Test name
Test status
Simulation time 1326554986 ps
CPU time 56.06 seconds
Started Aug 08 07:56:34 PM PDT 24
Finished Aug 08 07:57:30 PM PDT 24
Peak memory 575808 kb
Host smart-9a9a7652-9418-4692-bb34-835e3c938521
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548347279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2548347279
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.1586614219
Short name T2359
Test name
Test status
Simulation time 4498070364 ps
CPU time 180.68 seconds
Started Aug 08 07:56:37 PM PDT 24
Finished Aug 08 07:59:38 PM PDT 24
Peak memory 575856 kb
Host smart-6240941c-42d3-4401-9b5e-425877be4961
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586614219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1586614219
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3671363508
Short name T2927
Test name
Test status
Simulation time 211103238 ps
CPU time 137.79 seconds
Started Aug 08 07:56:35 PM PDT 24
Finished Aug 08 07:58:53 PM PDT 24
Peak memory 576612 kb
Host smart-fdedf368-1ef7-4d14-8e93-ec36d177fde2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671363508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all
_with_rand_reset.3671363508
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2102488734
Short name T849
Test name
Test status
Simulation time 3155551492 ps
CPU time 404.53 seconds
Started Aug 08 07:56:39 PM PDT 24
Finished Aug 08 08:03:23 PM PDT 24
Peak memory 576780 kb
Host smart-d6ba9651-8915-4582-bb9c-bfd91e5382bf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102488734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al
l_with_reset_error.2102488734
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.637565305
Short name T2297
Test name
Test status
Simulation time 995728339 ps
CPU time 43.33 seconds
Started Aug 08 07:56:35 PM PDT 24
Finished Aug 08 07:57:19 PM PDT 24
Peak memory 575972 kb
Host smart-fdfee632-3e55-4187-89c4-174f46bcd403
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637565305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.637565305
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_access_same_device.2948483901
Short name T2151
Test name
Test status
Simulation time 1766781328 ps
CPU time 78.05 seconds
Started Aug 08 07:57:00 PM PDT 24
Finished Aug 08 07:58:18 PM PDT 24
Peak memory 575944 kb
Host smart-a7aa21f1-36f9-40a0-ba29-2e3718200e0f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948483901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device
.2948483901
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.3707000800
Short name T2892
Test name
Test status
Simulation time 9186409818 ps
CPU time 160.68 seconds
Started Aug 08 07:56:44 PM PDT 24
Finished Aug 08 07:59:25 PM PDT 24
Peak memory 573940 kb
Host smart-b176270d-1328-4fa7-88cb-0a2ec762defe
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707000800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_
device_slow_rsp.3707000800
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.1089495251
Short name T2736
Test name
Test status
Simulation time 920560967 ps
CPU time 34.9 seconds
Started Aug 08 07:56:44 PM PDT 24
Finished Aug 08 07:57:19 PM PDT 24
Peak memory 575868 kb
Host smart-18b8c843-3c2e-4691-925e-249ffe2711b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089495251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add
r.1089495251
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_error_random.970776016
Short name T2235
Test name
Test status
Simulation time 1326758370 ps
CPU time 45.2 seconds
Started Aug 08 07:56:44 PM PDT 24
Finished Aug 08 07:57:30 PM PDT 24
Peak memory 575924 kb
Host smart-bcc061b5-44a9-40dd-ace2-7eb453f17aaa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970776016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.970776016
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random.2392215447
Short name T2112
Test name
Test status
Simulation time 157501142 ps
CPU time 14.54 seconds
Started Aug 08 07:56:43 PM PDT 24
Finished Aug 08 07:56:58 PM PDT 24
Peak memory 575836 kb
Host smart-18178eff-b864-49f1-8087-5088e44e59ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392215447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.2392215447
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.1029111174
Short name T2593
Test name
Test status
Simulation time 16255557994 ps
CPU time 169.69 seconds
Started Aug 08 07:56:44 PM PDT 24
Finished Aug 08 07:59:34 PM PDT 24
Peak memory 575980 kb
Host smart-406c358d-78bc-47ba-86f4-bbac6e668819
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029111174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1029111174
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.237960437
Short name T1811
Test name
Test status
Simulation time 34608638303 ps
CPU time 536.89 seconds
Started Aug 08 07:56:43 PM PDT 24
Finished Aug 08 08:05:40 PM PDT 24
Peak memory 575980 kb
Host smart-f83065a4-ed22-4c57-93d7-397d88f07ad5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237960437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.237960437
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.1716984136
Short name T568
Test name
Test status
Simulation time 429899620 ps
CPU time 34.56 seconds
Started Aug 08 07:57:00 PM PDT 24
Finished Aug 08 07:57:34 PM PDT 24
Peak memory 575868 kb
Host smart-cdb92354-93df-49bf-9c64-d62bc742a4d4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716984136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del
ays.1716984136
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_same_source.3057539673
Short name T1640
Test name
Test status
Simulation time 716460765 ps
CPU time 22.88 seconds
Started Aug 08 07:57:00 PM PDT 24
Finished Aug 08 07:57:23 PM PDT 24
Peak memory 575760 kb
Host smart-9219df90-7b77-415a-bca6-498ab9fcb446
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057539673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3057539673
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke.1103041380
Short name T2820
Test name
Test status
Simulation time 236448001 ps
CPU time 9.52 seconds
Started Aug 08 07:56:34 PM PDT 24
Finished Aug 08 07:56:44 PM PDT 24
Peak memory 574468 kb
Host smart-c106f145-8c6c-4ed3-9122-d741b400ba6d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103041380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1103041380
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.1124751195
Short name T2162
Test name
Test status
Simulation time 8962037080 ps
CPU time 101.89 seconds
Started Aug 08 07:56:44 PM PDT 24
Finished Aug 08 07:58:26 PM PDT 24
Peak memory 573912 kb
Host smart-9c1f5a66-ff23-49f6-9f98-3b5b054991de
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124751195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1124751195
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.832960018
Short name T2488
Test name
Test status
Simulation time 5637858972 ps
CPU time 96.96 seconds
Started Aug 08 07:56:59 PM PDT 24
Finished Aug 08 07:58:36 PM PDT 24
Peak memory 573864 kb
Host smart-dc6e1bce-636f-43c5-abac-294f09342a5c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832960018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.832960018
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.25765975
Short name T2731
Test name
Test status
Simulation time 50110193 ps
CPU time 6.6 seconds
Started Aug 08 07:56:42 PM PDT 24
Finished Aug 08 07:56:49 PM PDT 24
Peak memory 574416 kb
Host smart-dd6d5b0e-65c7-4afe-b63f-572476acdfff
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25765975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.25765975
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all.3031685200
Short name T484
Test name
Test status
Simulation time 2016109197 ps
CPU time 151.68 seconds
Started Aug 08 07:57:00 PM PDT 24
Finished Aug 08 07:59:32 PM PDT 24
Peak memory 575912 kb
Host smart-68ed6600-b0a8-4c0d-8b8b-7d8c07fb95c6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031685200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3031685200
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.1986260575
Short name T1956
Test name
Test status
Simulation time 3589252782 ps
CPU time 119.59 seconds
Started Aug 08 07:56:44 PM PDT 24
Finished Aug 08 07:58:43 PM PDT 24
Peak memory 576048 kb
Host smart-9d699298-7e98-46ce-b3cc-f6a401019354
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986260575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1986260575
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.845152016
Short name T2443
Test name
Test status
Simulation time 77776010 ps
CPU time 61.49 seconds
Started Aug 08 07:56:46 PM PDT 24
Finished Aug 08 07:57:47 PM PDT 24
Peak memory 576600 kb
Host smart-c125e7b8-46be-4011-aee9-af6f06b9c947
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845152016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all
_with_reset_error.845152016
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.2539302747
Short name T2535
Test name
Test status
Simulation time 150334037 ps
CPU time 18.6 seconds
Started Aug 08 07:56:45 PM PDT 24
Finished Aug 08 07:57:03 PM PDT 24
Peak memory 575936 kb
Host smart-7f70ad41-62e6-48db-a279-7ebfd6e1a91d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539302747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2539302747
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_access_same_device.3609546135
Short name T2111
Test name
Test status
Simulation time 265559029 ps
CPU time 27.07 seconds
Started Aug 08 07:56:55 PM PDT 24
Finished Aug 08 07:57:22 PM PDT 24
Peak memory 575840 kb
Host smart-9cd22e21-77bb-41c5-a1c0-c3882730c3e4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609546135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device
.3609546135
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.137675456
Short name T1949
Test name
Test status
Simulation time 60243633939 ps
CPU time 1117.87 seconds
Started Aug 08 07:56:57 PM PDT 24
Finished Aug 08 08:15:35 PM PDT 24
Peak memory 576008 kb
Host smart-32cc233d-e4f2-4c41-a703-fffc11b18541
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137675456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_d
evice_slow_rsp.137675456
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.1046446879
Short name T1465
Test name
Test status
Simulation time 624682927 ps
CPU time 25.04 seconds
Started Aug 08 07:56:54 PM PDT 24
Finished Aug 08 07:57:19 PM PDT 24
Peak memory 575964 kb
Host smart-1a4ee7c1-efa2-42a3-851c-e93d82875cbb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046446879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add
r.1046446879
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_error_random.3971254783
Short name T1633
Test name
Test status
Simulation time 2552881145 ps
CPU time 91.67 seconds
Started Aug 08 07:56:54 PM PDT 24
Finished Aug 08 07:58:25 PM PDT 24
Peak memory 575860 kb
Host smart-191bd4cc-eab4-4f82-bab9-ed4a05ba981f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971254783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3971254783
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random.2731838450
Short name T1843
Test name
Test status
Simulation time 429325203 ps
CPU time 16.67 seconds
Started Aug 08 07:56:54 PM PDT 24
Finished Aug 08 07:57:11 PM PDT 24
Peak memory 575768 kb
Host smart-1cff7d18-0f4c-4b28-86fb-9a46ae7a0e14
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731838450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.2731838450
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.2576921785
Short name T2665
Test name
Test status
Simulation time 34623270133 ps
CPU time 375.7 seconds
Started Aug 08 07:56:55 PM PDT 24
Finished Aug 08 08:03:11 PM PDT 24
Peak memory 576700 kb
Host smart-df7d7fb4-53a8-496e-b9c3-79a0af4e5614
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576921785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2576921785
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.2064457242
Short name T2182
Test name
Test status
Simulation time 68263444019 ps
CPU time 1236.42 seconds
Started Aug 08 07:56:54 PM PDT 24
Finished Aug 08 08:17:31 PM PDT 24
Peak memory 575996 kb
Host smart-c7416244-e3d9-409b-a095-20dae9f58647
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064457242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2064457242
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.2903395222
Short name T2321
Test name
Test status
Simulation time 235738812 ps
CPU time 23.31 seconds
Started Aug 08 07:56:54 PM PDT 24
Finished Aug 08 07:57:17 PM PDT 24
Peak memory 575896 kb
Host smart-200f3e90-3598-4368-a624-c57697347672
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903395222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del
ays.2903395222
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_same_source.1437797732
Short name T595
Test name
Test status
Simulation time 870011824 ps
CPU time 30.43 seconds
Started Aug 08 07:56:55 PM PDT 24
Finished Aug 08 07:57:25 PM PDT 24
Peak memory 575840 kb
Host smart-fa5404dd-b08e-42e2-b596-2104d0e9e969
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437797732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1437797732
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke.3031500834
Short name T89
Test name
Test status
Simulation time 199925196 ps
CPU time 8.86 seconds
Started Aug 08 07:56:44 PM PDT 24
Finished Aug 08 07:56:53 PM PDT 24
Peak memory 574540 kb
Host smart-1bdf4358-4b36-4757-9722-c5cae67c403c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031500834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3031500834
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.3307218778
Short name T1391
Test name
Test status
Simulation time 6855364249 ps
CPU time 74.3 seconds
Started Aug 08 07:56:55 PM PDT 24
Finished Aug 08 07:58:09 PM PDT 24
Peak memory 573852 kb
Host smart-ad70ea00-73d7-425e-9b9f-4f4c59190bdb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307218778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3307218778
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.578812419
Short name T2152
Test name
Test status
Simulation time 3843136922 ps
CPU time 65.18 seconds
Started Aug 08 07:56:55 PM PDT 24
Finished Aug 08 07:58:01 PM PDT 24
Peak memory 574600 kb
Host smart-ac28fdd5-987f-4f9b-9750-b682989fd9aa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578812419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.578812419
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.924267709
Short name T1783
Test name
Test status
Simulation time 58394849 ps
CPU time 6.95 seconds
Started Aug 08 07:57:00 PM PDT 24
Finished Aug 08 07:57:07 PM PDT 24
Peak memory 573768 kb
Host smart-41590f5a-03f4-44ba-8f36-75fdd1ce37cb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924267709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays
.924267709
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all.406548929
Short name T2611
Test name
Test status
Simulation time 5363218403 ps
CPU time 208.77 seconds
Started Aug 08 07:57:14 PM PDT 24
Finished Aug 08 08:00:43 PM PDT 24
Peak memory 575972 kb
Host smart-83e16e68-e933-4ed4-abd4-ada18de3305c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406548929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.406548929
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.2593526463
Short name T790
Test name
Test status
Simulation time 5493128034 ps
CPU time 204.85 seconds
Started Aug 08 07:57:14 PM PDT 24
Finished Aug 08 08:00:39 PM PDT 24
Peak memory 576068 kb
Host smart-a25bdd4f-be1b-4c3a-94e8-6806522a5214
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593526463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2593526463
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1300598206
Short name T2385
Test name
Test status
Simulation time 4439558256 ps
CPU time 549.92 seconds
Started Aug 08 07:57:08 PM PDT 24
Finished Aug 08 08:06:18 PM PDT 24
Peak memory 576176 kb
Host smart-fbe7f1f2-6016-4b4c-8966-f9559458fa58
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300598206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all
_with_rand_reset.1300598206
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1811893905
Short name T848
Test name
Test status
Simulation time 2008654288 ps
CPU time 298.69 seconds
Started Aug 08 07:57:06 PM PDT 24
Finished Aug 08 08:02:05 PM PDT 24
Peak memory 576720 kb
Host smart-25fdb671-de85-4056-9296-902152876481
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811893905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al
l_with_reset_error.1811893905
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.2211734718
Short name T2338
Test name
Test status
Simulation time 179689406 ps
CPU time 20.17 seconds
Started Aug 08 07:56:54 PM PDT 24
Finished Aug 08 07:57:15 PM PDT 24
Peak memory 575936 kb
Host smart-e555cc2f-bf54-45bf-977c-91a1920cc64c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211734718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2211734718
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_access_same_device.1124580089
Short name T2777
Test name
Test status
Simulation time 1757036181 ps
CPU time 66.74 seconds
Started Aug 08 07:57:18 PM PDT 24
Finished Aug 08 07:58:25 PM PDT 24
Peak memory 575772 kb
Host smart-ff7b3288-3a61-4035-84b0-ccaced0f78bc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124580089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device
.1124580089
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.3246611335
Short name T2625
Test name
Test status
Simulation time 103313675352 ps
CPU time 1822.34 seconds
Started Aug 08 07:57:17 PM PDT 24
Finished Aug 08 08:27:39 PM PDT 24
Peak memory 576056 kb
Host smart-af8b9c95-b79b-46d0-b9fe-63a0e4e1b1f5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246611335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_
device_slow_rsp.3246611335
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3891947224
Short name T2678
Test name
Test status
Simulation time 1059105832 ps
CPU time 44.81 seconds
Started Aug 08 07:57:18 PM PDT 24
Finished Aug 08 07:58:03 PM PDT 24
Peak memory 575968 kb
Host smart-b2d46e06-deb1-46b4-aaf8-8111f26655d5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891947224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add
r.3891947224
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_error_random.1490491774
Short name T1635
Test name
Test status
Simulation time 279233501 ps
CPU time 12.92 seconds
Started Aug 08 07:57:18 PM PDT 24
Finished Aug 08 07:57:31 PM PDT 24
Peak memory 575620 kb
Host smart-8c1120fd-bb32-4e6d-8c55-2fb30acd7c14
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490491774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1490491774
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random.3546516570
Short name T2358
Test name
Test status
Simulation time 854249930 ps
CPU time 32.74 seconds
Started Aug 08 07:57:06 PM PDT 24
Finished Aug 08 07:57:39 PM PDT 24
Peak memory 575744 kb
Host smart-54eb7d8f-fcd8-4bb3-8153-4156a6f09f4a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546516570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.3546516570
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.1924380425
Short name T2858
Test name
Test status
Simulation time 55763492430 ps
CPU time 630.46 seconds
Started Aug 08 07:57:05 PM PDT 24
Finished Aug 08 08:07:36 PM PDT 24
Peak memory 575828 kb
Host smart-58a6c3ca-527c-425e-b33b-6b097803e650
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924380425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1924380425
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.3360738067
Short name T2415
Test name
Test status
Simulation time 37486645194 ps
CPU time 619.62 seconds
Started Aug 08 07:57:09 PM PDT 24
Finished Aug 08 08:07:28 PM PDT 24
Peak memory 575944 kb
Host smart-20ccce83-1b40-4526-a833-e5411c30ecb7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360738067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3360738067
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.2156230645
Short name T2485
Test name
Test status
Simulation time 370035841 ps
CPU time 32.5 seconds
Started Aug 08 07:57:09 PM PDT 24
Finished Aug 08 07:57:41 PM PDT 24
Peak memory 575812 kb
Host smart-6102bd1e-f13f-4a03-a0d1-06ad16a06111
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156230645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del
ays.2156230645
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_same_source.24397449
Short name T2271
Test name
Test status
Simulation time 1857576370 ps
CPU time 56.67 seconds
Started Aug 08 07:57:20 PM PDT 24
Finished Aug 08 07:58:17 PM PDT 24
Peak memory 575888 kb
Host smart-ab5f0c17-87d8-4b50-a381-7cd396ff6458
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24397449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.24397449
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke.3867148915
Short name T1416
Test name
Test status
Simulation time 203374185 ps
CPU time 8.95 seconds
Started Aug 08 07:57:05 PM PDT 24
Finished Aug 08 07:57:14 PM PDT 24
Peak memory 573824 kb
Host smart-11e70af7-2c7f-4a76-a656-125a0d316162
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867148915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3867148915
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.2441535741
Short name T2015
Test name
Test status
Simulation time 9388335321 ps
CPU time 92.94 seconds
Started Aug 08 07:57:08 PM PDT 24
Finished Aug 08 07:58:41 PM PDT 24
Peak memory 574596 kb
Host smart-28acec54-9c36-4000-b396-aecde31f5fa1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441535741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2441535741
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.3031498088
Short name T2191
Test name
Test status
Simulation time 4720107170 ps
CPU time 80.37 seconds
Started Aug 08 07:57:06 PM PDT 24
Finished Aug 08 07:58:26 PM PDT 24
Peak memory 573908 kb
Host smart-606d97df-d0eb-4bf0-9461-3efacf9f4bf2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031498088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3031498088
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.1679400268
Short name T1884
Test name
Test status
Simulation time 46582647 ps
CPU time 6.45 seconds
Started Aug 08 07:57:06 PM PDT 24
Finished Aug 08 07:57:13 PM PDT 24
Peak memory 573692 kb
Host smart-71ced820-bad8-41cc-9167-90a3714362dd
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679400268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay
s.1679400268
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all.1316001079
Short name T1420
Test name
Test status
Simulation time 1340966026 ps
CPU time 49.9 seconds
Started Aug 08 07:57:17 PM PDT 24
Finished Aug 08 07:58:07 PM PDT 24
Peak memory 575892 kb
Host smart-09017971-f93c-4c05-b6c2-70f43291dbf9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316001079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1316001079
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.3044123500
Short name T2874
Test name
Test status
Simulation time 1219345891 ps
CPU time 93.77 seconds
Started Aug 08 07:57:20 PM PDT 24
Finished Aug 08 07:58:54 PM PDT 24
Peak memory 576064 kb
Host smart-8ce8afdd-e339-47d4-abef-7695e7b97bc2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044123500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3044123500
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.3459046775
Short name T2801
Test name
Test status
Simulation time 1864100019 ps
CPU time 232.44 seconds
Started Aug 08 07:57:16 PM PDT 24
Finished Aug 08 08:01:09 PM PDT 24
Peak memory 576668 kb
Host smart-46b2bc9a-85a7-47f3-9c4c-a745123d1e46
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459046775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all
_with_rand_reset.3459046775
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.3178900869
Short name T2354
Test name
Test status
Simulation time 346823946 ps
CPU time 120.39 seconds
Started Aug 08 07:57:18 PM PDT 24
Finished Aug 08 07:59:18 PM PDT 24
Peak memory 576760 kb
Host smart-d039019c-391a-409c-ba75-20da7d144b60
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178900869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al
l_with_reset_error.3178900869
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.358277544
Short name T2638
Test name
Test status
Simulation time 247209477 ps
CPU time 28.81 seconds
Started Aug 08 07:57:21 PM PDT 24
Finished Aug 08 07:57:49 PM PDT 24
Peak memory 575920 kb
Host smart-999c658b-d5b2-4f59-8d9d-29ef41dd3433
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358277544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.358277544
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_access_same_device.2852716733
Short name T2576
Test name
Test status
Simulation time 805346699 ps
CPU time 75.69 seconds
Started Aug 08 07:57:19 PM PDT 24
Finished Aug 08 07:58:35 PM PDT 24
Peak memory 575736 kb
Host smart-04f7afb3-d6d2-4f75-960e-c827f0aabd76
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852716733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device
.2852716733
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.3770776313
Short name T812
Test name
Test status
Simulation time 23215427370 ps
CPU time 386.74 seconds
Started Aug 08 07:57:20 PM PDT 24
Finished Aug 08 08:03:47 PM PDT 24
Peak memory 575932 kb
Host smart-75784993-6d4a-429b-a218-14e850d9386c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770776313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_
device_slow_rsp.3770776313
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.991282748
Short name T2647
Test name
Test status
Simulation time 303403571 ps
CPU time 31.28 seconds
Started Aug 08 07:57:17 PM PDT 24
Finished Aug 08 07:57:49 PM PDT 24
Peak memory 575944 kb
Host smart-60d426bf-5983-493a-8444-6df2965d7b51
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991282748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr
.991282748
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_error_random.1361062373
Short name T2648
Test name
Test status
Simulation time 262670500 ps
CPU time 18.03 seconds
Started Aug 08 07:57:18 PM PDT 24
Finished Aug 08 07:57:36 PM PDT 24
Peak memory 575832 kb
Host smart-6e33883f-603c-4fef-a052-6a6238b31eeb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361062373 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1361062373
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random.1437794593
Short name T1902
Test name
Test status
Simulation time 2330379203 ps
CPU time 85.65 seconds
Started Aug 08 07:57:20 PM PDT 24
Finished Aug 08 07:58:46 PM PDT 24
Peak memory 575764 kb
Host smart-238b819e-de65-4df7-9d66-ab3e979b1181
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437794593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.1437794593
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.955148395
Short name T2284
Test name
Test status
Simulation time 17725623963 ps
CPU time 193.45 seconds
Started Aug 08 07:57:18 PM PDT 24
Finished Aug 08 08:00:31 PM PDT 24
Peak memory 576720 kb
Host smart-a1a53219-3c85-435f-bc00-bfa86012db2e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955148395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.955148395
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.3473014691
Short name T2222
Test name
Test status
Simulation time 43510183856 ps
CPU time 771.01 seconds
Started Aug 08 07:57:17 PM PDT 24
Finished Aug 08 08:10:08 PM PDT 24
Peak memory 575972 kb
Host smart-cefd74da-9d39-4d84-a66b-08030ff0656e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473014691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3473014691
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.3126462310
Short name T2657
Test name
Test status
Simulation time 42235125 ps
CPU time 6.21 seconds
Started Aug 08 07:57:20 PM PDT 24
Finished Aug 08 07:57:26 PM PDT 24
Peak memory 573704 kb
Host smart-a06b0932-dd79-4606-a802-1dfd947da3fd
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126462310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del
ays.3126462310
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_same_source.4279440713
Short name T488
Test name
Test status
Simulation time 222349665 ps
CPU time 18.71 seconds
Started Aug 08 07:57:18 PM PDT 24
Finished Aug 08 07:57:37 PM PDT 24
Peak memory 575896 kb
Host smart-6608eb85-fd93-49e4-a224-8c093faf1f95
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279440713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.4279440713
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke.2349507628
Short name T2495
Test name
Test status
Simulation time 227066894 ps
CPU time 9.18 seconds
Started Aug 08 07:57:19 PM PDT 24
Finished Aug 08 07:57:28 PM PDT 24
Peak memory 574472 kb
Host smart-8e665921-5f5e-4a8b-8546-b42210a49783
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349507628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2349507628
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.1622502396
Short name T2456
Test name
Test status
Simulation time 6962747586 ps
CPU time 71.91 seconds
Started Aug 08 07:57:19 PM PDT 24
Finished Aug 08 07:58:31 PM PDT 24
Peak memory 574544 kb
Host smart-638fc4b5-6ad5-4cb6-a4fb-74b4f7561fa5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622502396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1622502396
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.1270296671
Short name T2193
Test name
Test status
Simulation time 4361927116 ps
CPU time 73.85 seconds
Started Aug 08 07:57:19 PM PDT 24
Finished Aug 08 07:58:33 PM PDT 24
Peak memory 573880 kb
Host smart-5b3cf9d5-1262-477d-b54a-f5c1299cdbba
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270296671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1270296671
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.2249260225
Short name T1397
Test name
Test status
Simulation time 46958717 ps
CPU time 6.92 seconds
Started Aug 08 07:57:18 PM PDT 24
Finished Aug 08 07:57:25 PM PDT 24
Peak memory 573788 kb
Host smart-27713c88-d170-43df-beb1-3e8bc9e902bf
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249260225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay
s.2249260225
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all.41288371
Short name T2117
Test name
Test status
Simulation time 2134684472 ps
CPU time 167.57 seconds
Started Aug 08 07:57:36 PM PDT 24
Finished Aug 08 08:00:24 PM PDT 24
Peak memory 576392 kb
Host smart-d474cf46-95f5-4376-be8d-c7588e169146
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41288371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.41288371
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.1330901119
Short name T2703
Test name
Test status
Simulation time 11902111813 ps
CPU time 363.48 seconds
Started Aug 08 07:57:30 PM PDT 24
Finished Aug 08 08:03:34 PM PDT 24
Peak memory 575956 kb
Host smart-d8527da8-5905-4d02-8975-ff279d3831b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330901119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1330901119
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.3812539799
Short name T824
Test name
Test status
Simulation time 12769476817 ps
CPU time 551.76 seconds
Started Aug 08 07:57:36 PM PDT 24
Finished Aug 08 08:06:48 PM PDT 24
Peak memory 576832 kb
Host smart-3726e3dd-6f94-4bdd-9eb6-8ec557a2fe8a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812539799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al
l_with_reset_error.3812539799
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.2049523659
Short name T433
Test name
Test status
Simulation time 388801374 ps
CPU time 16.75 seconds
Started Aug 08 07:57:20 PM PDT 24
Finished Aug 08 07:57:37 PM PDT 24
Peak memory 575696 kb
Host smart-1a05a9e9-f975-4f64-831c-e7b0df537355
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049523659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2049523659
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_access_same_device.884562644
Short name T2405
Test name
Test status
Simulation time 556619406 ps
CPU time 51.37 seconds
Started Aug 08 07:57:31 PM PDT 24
Finished Aug 08 07:58:22 PM PDT 24
Peak memory 575912 kb
Host smart-d9d48cec-4c32-42c8-b74b-64cddad39cdc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884562644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.
884562644
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2362091586
Short name T1444
Test name
Test status
Simulation time 10212742254 ps
CPU time 172.71 seconds
Started Aug 08 07:57:28 PM PDT 24
Finished Aug 08 08:00:21 PM PDT 24
Peak memory 573844 kb
Host smart-6d9eaaff-b543-4263-b5cf-182a0974e0bc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362091586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_
device_slow_rsp.2362091586
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.1346764005
Short name T1628
Test name
Test status
Simulation time 332095692 ps
CPU time 14.78 seconds
Started Aug 08 07:57:49 PM PDT 24
Finished Aug 08 07:58:04 PM PDT 24
Peak memory 575916 kb
Host smart-02f5c262-90c0-4802-a0bf-ae543d8fb7a6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346764005 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add
r.1346764005
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_error_random.565040248
Short name T1608
Test name
Test status
Simulation time 120425728 ps
CPU time 12.49 seconds
Started Aug 08 07:57:31 PM PDT 24
Finished Aug 08 07:57:44 PM PDT 24
Peak memory 575912 kb
Host smart-4ed560fa-f50e-45fb-b76a-7a71062d093c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565040248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.565040248
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random.2749306380
Short name T2403
Test name
Test status
Simulation time 215166903 ps
CPU time 10.3 seconds
Started Aug 08 07:57:29 PM PDT 24
Finished Aug 08 07:57:39 PM PDT 24
Peak memory 573752 kb
Host smart-24244af0-d1ec-44c6-9c83-9d65ea79ab61
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749306380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.2749306380
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.2899715638
Short name T2368
Test name
Test status
Simulation time 46776829698 ps
CPU time 500.25 seconds
Started Aug 08 07:57:29 PM PDT 24
Finished Aug 08 08:05:49 PM PDT 24
Peak memory 576028 kb
Host smart-d8f43ff6-0016-4e81-893e-d64d9601253d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899715638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2899715638
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.1444794527
Short name T2903
Test name
Test status
Simulation time 23065737413 ps
CPU time 373.54 seconds
Started Aug 08 07:57:29 PM PDT 24
Finished Aug 08 08:03:42 PM PDT 24
Peak memory 575816 kb
Host smart-c70e7a9d-0ae2-4265-97b6-1f7c21cf1cc9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444794527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1444794527
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.1935845519
Short name T2401
Test name
Test status
Simulation time 511606612 ps
CPU time 39.92 seconds
Started Aug 08 07:57:28 PM PDT 24
Finished Aug 08 07:58:08 PM PDT 24
Peak memory 575712 kb
Host smart-98fc788d-3de5-48f8-ad45-08049a3e0df3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935845519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del
ays.1935845519
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_same_source.735527068
Short name T2357
Test name
Test status
Simulation time 2651184269 ps
CPU time 76.89 seconds
Started Aug 08 07:57:30 PM PDT 24
Finished Aug 08 07:58:47 PM PDT 24
Peak memory 576032 kb
Host smart-2c3cfc3a-c17d-4e08-a7df-46d1a7a8e17a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735527068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.735527068
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke.3467875243
Short name T2437
Test name
Test status
Simulation time 44936538 ps
CPU time 6.71 seconds
Started Aug 08 07:57:28 PM PDT 24
Finished Aug 08 07:57:34 PM PDT 24
Peak memory 574480 kb
Host smart-f776a1ec-3907-4791-8ced-785ee6ed8cf1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467875243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3467875243
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.1679289417
Short name T1952
Test name
Test status
Simulation time 7766825991 ps
CPU time 79.65 seconds
Started Aug 08 07:57:30 PM PDT 24
Finished Aug 08 07:58:50 PM PDT 24
Peak memory 573920 kb
Host smart-d9236cb1-2ee4-46fd-930f-dff506107bf5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679289417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1679289417
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.976316442
Short name T1486
Test name
Test status
Simulation time 4443054780 ps
CPU time 72.36 seconds
Started Aug 08 07:57:30 PM PDT 24
Finished Aug 08 07:58:43 PM PDT 24
Peak memory 573860 kb
Host smart-83f7e96e-01ea-4db0-8599-d7a7dd60d246
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976316442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.976316442
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.2345047179
Short name T2931
Test name
Test status
Simulation time 44917557 ps
CPU time 5.67 seconds
Started Aug 08 07:57:28 PM PDT 24
Finished Aug 08 07:57:34 PM PDT 24
Peak memory 573752 kb
Host smart-34ff31ae-513f-4c3e-869d-4cfc2c36a068
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345047179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay
s.2345047179
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all.1776840804
Short name T508
Test name
Test status
Simulation time 2844875510 ps
CPU time 256.88 seconds
Started Aug 08 07:57:50 PM PDT 24
Finished Aug 08 08:02:07 PM PDT 24
Peak memory 575884 kb
Host smart-5f509501-91a7-49dc-8049-05fccf6899b7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776840804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1776840804
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.661747531
Short name T798
Test name
Test status
Simulation time 1536725281 ps
CPU time 53.5 seconds
Started Aug 08 07:57:49 PM PDT 24
Finished Aug 08 07:58:42 PM PDT 24
Peak memory 575936 kb
Host smart-906b03ea-8c42-4547-bd09-d47e5655d556
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661747531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.661747531
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.333189952
Short name T2223
Test name
Test status
Simulation time 381888143 ps
CPU time 17.77 seconds
Started Aug 08 07:57:48 PM PDT 24
Finished Aug 08 07:58:06 PM PDT 24
Peak memory 575960 kb
Host smart-d2cf98d4-1a5b-4a15-a6b5-463af6c97426
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333189952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.333189952
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_access_same_device.3717347689
Short name T818
Test name
Test status
Simulation time 585756023 ps
CPU time 23.08 seconds
Started Aug 08 07:58:03 PM PDT 24
Finished Aug 08 07:58:26 PM PDT 24
Peak memory 575864 kb
Host smart-f4ef8d2f-01b6-4231-b7e4-bcc579c927fb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717347689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device
.3717347689
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.959475035
Short name T2624
Test name
Test status
Simulation time 49252807119 ps
CPU time 886.85 seconds
Started Aug 08 07:58:04 PM PDT 24
Finished Aug 08 08:12:51 PM PDT 24
Peak memory 576052 kb
Host smart-f0273e19-0aca-4b05-bcd4-c0b5982a2e0c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959475035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_d
evice_slow_rsp.959475035
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.3819774197
Short name T1435
Test name
Test status
Simulation time 161106196 ps
CPU time 17.93 seconds
Started Aug 08 07:58:07 PM PDT 24
Finished Aug 08 07:58:25 PM PDT 24
Peak memory 575688 kb
Host smart-8ed4cae3-12ac-43b6-b247-4b160f534671
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819774197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add
r.3819774197
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_error_random.3415429544
Short name T2776
Test name
Test status
Simulation time 1216154338 ps
CPU time 35.41 seconds
Started Aug 08 07:58:04 PM PDT 24
Finished Aug 08 07:58:39 PM PDT 24
Peak memory 575908 kb
Host smart-25153d6f-bbaa-4437-abaa-3f7b2b8823df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415429544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3415429544
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random.2299707589
Short name T1630
Test name
Test status
Simulation time 371856868 ps
CPU time 36.62 seconds
Started Aug 08 07:57:50 PM PDT 24
Finished Aug 08 07:58:26 PM PDT 24
Peak memory 575932 kb
Host smart-586bad38-aaf7-4667-a1f7-81a5b94051c4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299707589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.2299707589
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.3733969732
Short name T604
Test name
Test status
Simulation time 29545304208 ps
CPU time 311.04 seconds
Started Aug 08 07:57:48 PM PDT 24
Finished Aug 08 08:02:59 PM PDT 24
Peak memory 575916 kb
Host smart-adba3d6f-6174-4395-bf59-d953ccd2a369
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733969732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3733969732
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.415722733
Short name T594
Test name
Test status
Simulation time 38705227100 ps
CPU time 666.46 seconds
Started Aug 08 07:58:04 PM PDT 24
Finished Aug 08 08:09:10 PM PDT 24
Peak memory 575944 kb
Host smart-a869d88e-6321-4ecc-8cf8-78df574fb067
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415722733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.415722733
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.3715861193
Short name T567
Test name
Test status
Simulation time 564018100 ps
CPU time 52.1 seconds
Started Aug 08 07:57:48 PM PDT 24
Finished Aug 08 07:58:40 PM PDT 24
Peak memory 575744 kb
Host smart-a63f6967-e7f0-4c63-aa74-0e9da2f8d4eb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715861193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del
ays.3715861193
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_same_source.80231742
Short name T1904
Test name
Test status
Simulation time 1150595985 ps
CPU time 37.19 seconds
Started Aug 08 07:58:07 PM PDT 24
Finished Aug 08 07:58:44 PM PDT 24
Peak memory 575872 kb
Host smart-2b569941-3973-46ec-bebc-950ebad407b0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80231742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.80231742
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke.147989195
Short name T2774
Test name
Test status
Simulation time 218197197 ps
CPU time 9.2 seconds
Started Aug 08 07:57:50 PM PDT 24
Finished Aug 08 07:57:59 PM PDT 24
Peak memory 573824 kb
Host smart-e0d10f6a-623a-45b5-928b-23ff55dad10e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147989195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.147989195
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.986570993
Short name T1970
Test name
Test status
Simulation time 5657246550 ps
CPU time 55.92 seconds
Started Aug 08 07:57:51 PM PDT 24
Finished Aug 08 07:58:47 PM PDT 24
Peak memory 573876 kb
Host smart-498ed9c7-edec-41d9-bfd5-c0ab139bb90a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986570993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.986570993
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.4281934352
Short name T1493
Test name
Test status
Simulation time 4750743261 ps
CPU time 80.28 seconds
Started Aug 08 07:57:49 PM PDT 24
Finished Aug 08 07:59:09 PM PDT 24
Peak memory 574588 kb
Host smart-6323d025-2223-499b-a0bc-81f1051face0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281934352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.4281934352
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.558633715
Short name T1645
Test name
Test status
Simulation time 52695777 ps
CPU time 6.65 seconds
Started Aug 08 07:57:50 PM PDT 24
Finished Aug 08 07:57:57 PM PDT 24
Peak memory 574528 kb
Host smart-ca5ac678-a749-4b1c-a526-44d6a4470cee
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558633715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays
.558633715
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all.3661169585
Short name T557
Test name
Test status
Simulation time 2765620940 ps
CPU time 235.17 seconds
Started Aug 08 07:58:03 PM PDT 24
Finished Aug 08 08:01:59 PM PDT 24
Peak memory 576012 kb
Host smart-de2bfdfa-232b-45be-8897-de3278969cf6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661169585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3661169585
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.3224993089
Short name T2164
Test name
Test status
Simulation time 2037112664 ps
CPU time 61.09 seconds
Started Aug 08 07:58:03 PM PDT 24
Finished Aug 08 07:59:04 PM PDT 24
Peak memory 576040 kb
Host smart-09832a5c-1087-4ee7-a662-aa6f70d1fe1e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224993089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3224993089
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.3416744943
Short name T832
Test name
Test status
Simulation time 1407359853 ps
CPU time 270.97 seconds
Started Aug 08 07:58:06 PM PDT 24
Finished Aug 08 08:02:37 PM PDT 24
Peak memory 575860 kb
Host smart-b64d7308-e341-48fd-b380-ef3555ebde17
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416744943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all
_with_rand_reset.3416744943
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.919547389
Short name T2554
Test name
Test status
Simulation time 282559825 ps
CPU time 70.87 seconds
Started Aug 08 07:58:04 PM PDT 24
Finished Aug 08 07:59:15 PM PDT 24
Peak memory 576652 kb
Host smart-a860d389-47be-47e9-8a5c-4703ba602d09
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919547389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all
_with_reset_error.919547389
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.391365924
Short name T1410
Test name
Test status
Simulation time 472755433 ps
CPU time 21.26 seconds
Started Aug 08 07:58:04 PM PDT 24
Finished Aug 08 07:58:26 PM PDT 24
Peak memory 575924 kb
Host smart-7ba0a9de-bde6-4559-9b96-6edbd8848724
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391365924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.391365924
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.2840288237
Short name T2605
Test name
Test status
Simulation time 29335621997 ps
CPU time 5256 seconds
Started Aug 08 07:50:16 PM PDT 24
Finished Aug 08 09:17:53 PM PDT 24
Peak memory 593820 kb
Host smart-86c4ebf7-21b6-4955-8695-eae6d8d8b9cf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840288237 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.chip_csr_aliasing.2840288237
Directory /workspace/4.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.1799302389
Short name T2555
Test name
Test status
Simulation time 46158363167 ps
CPU time 5298.81 seconds
Started Aug 08 07:50:16 PM PDT 24
Finished Aug 08 09:18:35 PM PDT 24
Peak memory 592880 kb
Host smart-3df767bd-2e9a-4b28-b875-48ed488106c8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799302389 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.1799302389
Directory /workspace/4.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.652539207
Short name T426
Test name
Test status
Simulation time 6931322321 ps
CPU time 446.26 seconds
Started Aug 08 07:50:27 PM PDT 24
Finished Aug 08 07:57:53 PM PDT 24
Peak memory 638560 kb
Host smart-71ba1f55-5a55-4845-b11f-722c4f748a2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652539207 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.652539207
Directory /workspace/4.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_rw.1187103739
Short name T2383
Test name
Test status
Simulation time 3500987820 ps
CPU time 254.93 seconds
Started Aug 08 07:50:27 PM PDT 24
Finished Aug 08 07:54:42 PM PDT 24
Peak memory 597368 kb
Host smart-78221fa9-4d73-47f8-a931-de2273c31346
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187103739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.1187103739
Directory /workspace/4.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.230313276
Short name T428
Test name
Test status
Simulation time 28303664744 ps
CPU time 3424.44 seconds
Started Aug 08 07:50:18 PM PDT 24
Finished Aug 08 08:47:23 PM PDT 24
Peak memory 593400 kb
Host smart-9d38de66-bff8-479b-92e0-2998f86dbf1f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230313276 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.chip_same_csr_outstanding.230313276
Directory /workspace/4.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.chip_tl_errors.2175148410
Short name T527
Test name
Test status
Simulation time 3835550620 ps
CPU time 191.21 seconds
Started Aug 08 07:50:14 PM PDT 24
Finished Aug 08 07:53:26 PM PDT 24
Peak memory 598732 kb
Host smart-38673357-73bb-422d-854c-62dc6ab976fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175148410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.2175148410
Directory /workspace/4.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_access_same_device.1136913644
Short name T1853
Test name
Test status
Simulation time 1900073270 ps
CPU time 77.11 seconds
Started Aug 08 07:50:16 PM PDT 24
Finished Aug 08 07:51:33 PM PDT 24
Peak memory 575908 kb
Host smart-34ab10df-5e86-428d-b491-f157a513e642
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136913644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.
1136913644
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.42605068
Short name T2899
Test name
Test status
Simulation time 104138615142 ps
CPU time 1787.2 seconds
Started Aug 08 07:50:27 PM PDT 24
Finished Aug 08 08:20:14 PM PDT 24
Peak memory 576040 kb
Host smart-387a24c7-0d56-4969-af6d-6b6472412c1e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42605068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_dev
ice_slow_rsp.42605068
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.1379223606
Short name T2914
Test name
Test status
Simulation time 770155491 ps
CPU time 30.67 seconds
Started Aug 08 07:50:26 PM PDT 24
Finished Aug 08 07:50:56 PM PDT 24
Peak memory 575856 kb
Host smart-71821aea-54a8-4159-a041-e9eeff1a7674
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379223606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr
.1379223606
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_error_random.2218116023
Short name T2378
Test name
Test status
Simulation time 2176569379 ps
CPU time 74.29 seconds
Started Aug 08 07:50:28 PM PDT 24
Finished Aug 08 07:51:43 PM PDT 24
Peak memory 575740 kb
Host smart-1f6defcc-34a4-4439-b433-6673c456e478
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218116023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2218116023
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random.1156122925
Short name T463
Test name
Test status
Simulation time 2067762360 ps
CPU time 68.65 seconds
Started Aug 08 07:50:19 PM PDT 24
Finished Aug 08 07:51:27 PM PDT 24
Peak memory 575828 kb
Host smart-20e34441-1e82-4e21-a70c-bc8a420ddc29
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156122925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.1156122925
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.3900120394
Short name T1953
Test name
Test status
Simulation time 62881603612 ps
CPU time 668.21 seconds
Started Aug 08 07:50:23 PM PDT 24
Finished Aug 08 08:01:31 PM PDT 24
Peak memory 575960 kb
Host smart-8901cd36-0803-4988-867c-7297e1ec79bb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900120394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3900120394
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.1634441230
Short name T2577
Test name
Test status
Simulation time 54593167410 ps
CPU time 944.91 seconds
Started Aug 08 07:50:16 PM PDT 24
Finished Aug 08 08:06:01 PM PDT 24
Peak memory 576676 kb
Host smart-4661aec7-a72d-406e-8903-9324f49ab838
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634441230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1634441230
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.2823622897
Short name T2313
Test name
Test status
Simulation time 521915316 ps
CPU time 42.82 seconds
Started Aug 08 07:50:15 PM PDT 24
Finished Aug 08 07:50:58 PM PDT 24
Peak memory 575792 kb
Host smart-4854af74-f051-4673-8463-11f626ef8bf7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823622897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela
ys.2823622897
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_same_source.3946278680
Short name T2850
Test name
Test status
Simulation time 1808601238 ps
CPU time 49.05 seconds
Started Aug 08 07:50:23 PM PDT 24
Finished Aug 08 07:51:12 PM PDT 24
Peak memory 575700 kb
Host smart-f995d75e-3c05-4432-8dcf-a4b43ea1644f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946278680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3946278680
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke.837871936
Short name T608
Test name
Test status
Simulation time 143755124 ps
CPU time 7.81 seconds
Started Aug 08 07:50:19 PM PDT 24
Finished Aug 08 07:50:26 PM PDT 24
Peak memory 573784 kb
Host smart-037134f0-a19c-47d9-a86b-beafa8b21c65
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837871936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.837871936
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.2832747559
Short name T2472
Test name
Test status
Simulation time 8690295511 ps
CPU time 94.15 seconds
Started Aug 08 07:50:13 PM PDT 24
Finished Aug 08 07:51:48 PM PDT 24
Peak memory 573472 kb
Host smart-90873a6c-b568-42ac-ac71-145a74bc5068
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832747559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2832747559
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.861792088
Short name T2454
Test name
Test status
Simulation time 4187294069 ps
CPU time 69.83 seconds
Started Aug 08 07:50:16 PM PDT 24
Finished Aug 08 07:51:26 PM PDT 24
Peak memory 574516 kb
Host smart-01a2efc6-3951-4a26-a30d-d6cb11733662
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861792088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.861792088
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.2296856941
Short name T2922
Test name
Test status
Simulation time 35072007 ps
CPU time 5.54 seconds
Started Aug 08 07:50:16 PM PDT 24
Finished Aug 08 07:50:22 PM PDT 24
Peak memory 574456 kb
Host smart-b57cc2d5-f488-449b-9d92-2a4d7267e72f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296856941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays
.2296856941
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all.3763264733
Short name T456
Test name
Test status
Simulation time 2565429012 ps
CPU time 192.4 seconds
Started Aug 08 07:50:24 PM PDT 24
Finished Aug 08 07:53:37 PM PDT 24
Peak memory 575920 kb
Host smart-0bf146eb-c785-4c97-af4b-d82ecf463ce0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763264733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3763264733
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.2668382616
Short name T803
Test name
Test status
Simulation time 3408329183 ps
CPU time 129.77 seconds
Started Aug 08 07:50:23 PM PDT 24
Finished Aug 08 07:52:33 PM PDT 24
Peak memory 575948 kb
Host smart-9cebceff-105a-44ee-a596-897c7775c917
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668382616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2668382616
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.3993741266
Short name T850
Test name
Test status
Simulation time 2045393326 ps
CPU time 267.33 seconds
Started Aug 08 07:50:26 PM PDT 24
Finished Aug 08 07:54:54 PM PDT 24
Peak memory 576748 kb
Host smart-09079388-8581-42bc-a7a4-e7b9acb108c6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993741266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_
with_rand_reset.3993741266
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.139544147
Short name T847
Test name
Test status
Simulation time 196486757 ps
CPU time 97.64 seconds
Started Aug 08 07:50:23 PM PDT 24
Finished Aug 08 07:52:00 PM PDT 24
Peak memory 576664 kb
Host smart-6ae46f66-27f6-4ac3-a962-ecde863e97e9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139544147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_
with_reset_error.139544147
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.3030526526
Short name T2758
Test name
Test status
Simulation time 337785046 ps
CPU time 14.27 seconds
Started Aug 08 07:50:24 PM PDT 24
Finished Aug 08 07:50:38 PM PDT 24
Peak memory 575944 kb
Host smart-825406fd-24d6-4024-beb6-6332d039670d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030526526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3030526526
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_access_same_device.1784347315
Short name T811
Test name
Test status
Simulation time 629600754 ps
CPU time 28.41 seconds
Started Aug 08 07:58:04 PM PDT 24
Finished Aug 08 07:58:32 PM PDT 24
Peak memory 575820 kb
Host smart-bfd0a201-cae4-406e-aace-9348a535eb1f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784347315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device
.1784347315
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.4223985377
Short name T2609
Test name
Test status
Simulation time 119084044659 ps
CPU time 2225.74 seconds
Started Aug 08 07:58:03 PM PDT 24
Finished Aug 08 08:35:10 PM PDT 24
Peak memory 576016 kb
Host smart-ab5788c0-6166-462e-aff3-c0f8eaf73cfd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223985377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_
device_slow_rsp.4223985377
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.2984986240
Short name T2829
Test name
Test status
Simulation time 305833460 ps
CPU time 13.61 seconds
Started Aug 08 07:58:03 PM PDT 24
Finished Aug 08 07:58:17 PM PDT 24
Peak memory 575864 kb
Host smart-4be948ab-b4fa-42f1-93e5-a0a4542798bf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984986240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add
r.2984986240
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_error_random.3793740583
Short name T1886
Test name
Test status
Simulation time 152432428 ps
CPU time 8.23 seconds
Started Aug 08 07:58:05 PM PDT 24
Finished Aug 08 07:58:14 PM PDT 24
Peak memory 573864 kb
Host smart-c4c10d65-b660-4e1d-a30c-cbd75f559987
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793740583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3793740583
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random.3620885866
Short name T529
Test name
Test status
Simulation time 868940045 ps
CPU time 31.81 seconds
Started Aug 08 07:58:03 PM PDT 24
Finished Aug 08 07:58:35 PM PDT 24
Peak memory 575764 kb
Host smart-84a16101-abec-4222-8ec1-56babbff5a79
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620885866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.3620885866
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.297405624
Short name T1809
Test name
Test status
Simulation time 70464960489 ps
CPU time 751.16 seconds
Started Aug 08 07:58:05 PM PDT 24
Finished Aug 08 08:10:37 PM PDT 24
Peak memory 576748 kb
Host smart-6be058b6-af3a-4ac3-abd6-ef50122313a5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297405624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.297405624
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.307904469
Short name T1823
Test name
Test status
Simulation time 4132521590 ps
CPU time 67.67 seconds
Started Aug 08 07:58:03 PM PDT 24
Finished Aug 08 07:59:11 PM PDT 24
Peak memory 574616 kb
Host smart-986b616f-bb58-4a84-90b7-f2c057b9414b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307904469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.307904469
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.2037784398
Short name T548
Test name
Test status
Simulation time 330513049 ps
CPU time 38.09 seconds
Started Aug 08 07:58:02 PM PDT 24
Finished Aug 08 07:58:40 PM PDT 24
Peak memory 575804 kb
Host smart-e660c3b6-7e46-4a32-97a4-49a0aa772b65
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037784398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del
ays.2037784398
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_same_source.1513004586
Short name T1510
Test name
Test status
Simulation time 307734695 ps
CPU time 11.05 seconds
Started Aug 08 07:58:06 PM PDT 24
Finished Aug 08 07:58:17 PM PDT 24
Peak memory 575708 kb
Host smart-f4b0a6d0-d9a9-4c39-bae1-c651afbd94ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513004586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1513004586
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke.2510877725
Short name T1759
Test name
Test status
Simulation time 252282710 ps
CPU time 10.7 seconds
Started Aug 08 07:58:07 PM PDT 24
Finished Aug 08 07:58:18 PM PDT 24
Peak memory 573792 kb
Host smart-76476ab9-4351-41d7-b43e-93ea666f656e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510877725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2510877725
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.446331212
Short name T420
Test name
Test status
Simulation time 7253406160 ps
CPU time 76.96 seconds
Started Aug 08 07:58:05 PM PDT 24
Finished Aug 08 07:59:22 PM PDT 24
Peak memory 574632 kb
Host smart-dae48277-d63d-4b1b-bd39-ac32cdcafaa1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446331212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.446331212
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.1299916832
Short name T2166
Test name
Test status
Simulation time 2831645963 ps
CPU time 48.4 seconds
Started Aug 08 07:58:04 PM PDT 24
Finished Aug 08 07:58:52 PM PDT 24
Peak memory 574564 kb
Host smart-ede2b7c6-527d-4024-8a60-cf089a97cda1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299916832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1299916832
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.5500353
Short name T2729
Test name
Test status
Simulation time 51830558 ps
CPU time 6.74 seconds
Started Aug 08 07:58:04 PM PDT 24
Finished Aug 08 07:58:11 PM PDT 24
Peak memory 574416 kb
Host smart-8f1cdc8e-20b9-47d9-936c-0f78b4cff81d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5500353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.5500353
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.1656174208
Short name T670
Test name
Test status
Simulation time 2207333723 ps
CPU time 67.56 seconds
Started Aug 08 07:58:05 PM PDT 24
Finished Aug 08 07:59:13 PM PDT 24
Peak memory 575760 kb
Host smart-0a8b58da-b06d-449d-919b-6c9e7f8c472a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656174208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1656174208
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.148167704
Short name T1715
Test name
Test status
Simulation time 70407695 ps
CPU time 53.38 seconds
Started Aug 08 07:58:07 PM PDT 24
Finished Aug 08 07:59:00 PM PDT 24
Peak memory 576640 kb
Host smart-85746cf7-cb64-47a7-afd8-3bb6cb045151
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148167704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_
with_rand_reset.148167704
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.2632601816
Short name T2108
Test name
Test status
Simulation time 2467036411 ps
CPU time 103.08 seconds
Started Aug 08 07:58:23 PM PDT 24
Finished Aug 08 08:00:06 PM PDT 24
Peak memory 575964 kb
Host smart-1f73aa30-d92d-48c3-9d63-760ddfaa0d31
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632601816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al
l_with_reset_error.2632601816
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.2445269584
Short name T1558
Test name
Test status
Simulation time 320446932 ps
CPU time 33.7 seconds
Started Aug 08 07:58:04 PM PDT 24
Finished Aug 08 07:58:38 PM PDT 24
Peak memory 575948 kb
Host smart-b7db7187-a4ef-48c1-b2d0-2eb15b0c3177
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445269584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2445269584
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_access_same_device.4262576282
Short name T2790
Test name
Test status
Simulation time 1122250924 ps
CPU time 70.01 seconds
Started Aug 08 07:58:17 PM PDT 24
Finished Aug 08 07:59:27 PM PDT 24
Peak memory 575984 kb
Host smart-0912bfb4-9241-4b46-b3c6-74292cfc7736
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262576282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device
.4262576282
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.3382774164
Short name T2262
Test name
Test status
Simulation time 32329631093 ps
CPU time 539.09 seconds
Started Aug 08 07:58:18 PM PDT 24
Finished Aug 08 08:07:17 PM PDT 24
Peak memory 575868 kb
Host smart-dbc4e071-3747-471b-b585-83a19d380c07
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382774164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_
device_slow_rsp.3382774164
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.1123307644
Short name T1965
Test name
Test status
Simulation time 392071460 ps
CPU time 17.01 seconds
Started Aug 08 07:58:17 PM PDT 24
Finished Aug 08 07:58:34 PM PDT 24
Peak memory 575968 kb
Host smart-ef9cff7d-17c8-4b34-acf4-2d234930d3de
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123307644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add
r.1123307644
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_error_random.213567390
Short name T2386
Test name
Test status
Simulation time 393145082 ps
CPU time 35.54 seconds
Started Aug 08 07:58:20 PM PDT 24
Finished Aug 08 07:58:55 PM PDT 24
Peak memory 575844 kb
Host smart-52a3f49e-856b-43aa-9377-5978390c7c8d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213567390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.213567390
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random.1179113567
Short name T2278
Test name
Test status
Simulation time 269264257 ps
CPU time 12.06 seconds
Started Aug 08 07:58:16 PM PDT 24
Finished Aug 08 07:58:28 PM PDT 24
Peak memory 575828 kb
Host smart-1d668b53-b58b-4c78-9721-9499b45feab7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179113567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.1179113567
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.241302707
Short name T1919
Test name
Test status
Simulation time 32293056732 ps
CPU time 324.89 seconds
Started Aug 08 07:58:18 PM PDT 24
Finished Aug 08 08:03:43 PM PDT 24
Peak memory 575988 kb
Host smart-50b6135d-34bb-4967-9d1e-d1df8be26fec
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241302707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.241302707
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.441953099
Short name T1812
Test name
Test status
Simulation time 50889915684 ps
CPU time 869.54 seconds
Started Aug 08 07:58:20 PM PDT 24
Finished Aug 08 08:12:50 PM PDT 24
Peak memory 575888 kb
Host smart-09ec661d-20f7-4362-bd51-d0335d88ef58
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441953099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.441953099
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.471020824
Short name T523
Test name
Test status
Simulation time 491471365 ps
CPU time 42.77 seconds
Started Aug 08 07:58:23 PM PDT 24
Finished Aug 08 07:59:06 PM PDT 24
Peak memory 575868 kb
Host smart-c3af50b3-7fae-4559-81cd-185574f3d771
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471020824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_dela
ys.471020824
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_same_source.128950740
Short name T1376
Test name
Test status
Simulation time 858004936 ps
CPU time 24.65 seconds
Started Aug 08 07:58:17 PM PDT 24
Finished Aug 08 07:58:42 PM PDT 24
Peak memory 575820 kb
Host smart-76972706-d9b5-4c18-8ae3-be68f326c7f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128950740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.128950740
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke.3172327862
Short name T1662
Test name
Test status
Simulation time 214514865 ps
CPU time 8.87 seconds
Started Aug 08 07:58:16 PM PDT 24
Finished Aug 08 07:58:25 PM PDT 24
Peak memory 573836 kb
Host smart-f0aa47cb-e565-4aaf-bfa6-cd515fe6908b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172327862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3172327862
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.646555248
Short name T1822
Test name
Test status
Simulation time 8817279274 ps
CPU time 90.25 seconds
Started Aug 08 07:58:18 PM PDT 24
Finished Aug 08 07:59:48 PM PDT 24
Peak memory 573944 kb
Host smart-4aa2c1ce-852d-4db7-ae7d-3ac775d5b5d0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646555248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.646555248
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.2989783613
Short name T1826
Test name
Test status
Simulation time 6406864756 ps
CPU time 94.7 seconds
Started Aug 08 07:58:18 PM PDT 24
Finished Aug 08 07:59:53 PM PDT 24
Peak memory 574576 kb
Host smart-f0c1bbc6-91cb-42c3-887b-87da559d3fb1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989783613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2989783613
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.1062562968
Short name T2141
Test name
Test status
Simulation time 51498864 ps
CPU time 6.32 seconds
Started Aug 08 07:58:22 PM PDT 24
Finished Aug 08 07:58:29 PM PDT 24
Peak memory 574504 kb
Host smart-a21592b7-cebb-4fba-89f0-e34e2f191ffe
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062562968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay
s.1062562968
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all.2511668495
Short name T2653
Test name
Test status
Simulation time 1924743899 ps
CPU time 136.38 seconds
Started Aug 08 07:58:23 PM PDT 24
Finished Aug 08 08:00:39 PM PDT 24
Peak memory 575896 kb
Host smart-bf2ee795-855b-4b6a-bc77-811ac5d8014d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511668495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2511668495
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.1896886101
Short name T2207
Test name
Test status
Simulation time 2162744556 ps
CPU time 64.51 seconds
Started Aug 08 07:58:19 PM PDT 24
Finished Aug 08 07:59:24 PM PDT 24
Peak memory 575936 kb
Host smart-6f78bb9e-6a23-4b14-8564-3b80f964d30b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896886101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1896886101
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.32920711
Short name T2817
Test name
Test status
Simulation time 104759464 ps
CPU time 53.26 seconds
Started Aug 08 07:58:17 PM PDT 24
Finished Aug 08 07:59:10 PM PDT 24
Peak memory 575880 kb
Host smart-cf5cd009-c82a-4664-a7c1-97f457ee5090
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32920711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_w
ith_rand_reset.32920711
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.2338306149
Short name T1639
Test name
Test status
Simulation time 726328137 ps
CPU time 249.72 seconds
Started Aug 08 07:58:18 PM PDT 24
Finished Aug 08 08:02:28 PM PDT 24
Peak memory 576696 kb
Host smart-54a14b58-5a0b-408e-acdc-ebdedcebd7e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338306149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al
l_with_reset_error.2338306149
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.2545846891
Short name T2370
Test name
Test status
Simulation time 23171964 ps
CPU time 5.56 seconds
Started Aug 08 07:58:22 PM PDT 24
Finished Aug 08 07:58:28 PM PDT 24
Peak memory 573784 kb
Host smart-29cb0dd4-6d91-4c85-8e45-7ea72ccca5aa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545846891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2545846891
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_access_same_device.607828971
Short name T1600
Test name
Test status
Simulation time 1117526425 ps
CPU time 56.39 seconds
Started Aug 08 07:58:17 PM PDT 24
Finished Aug 08 07:59:14 PM PDT 24
Peak memory 575736 kb
Host smart-3de6692f-c140-4c2f-892b-2a9cc09b729e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607828971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.
607828971
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.444817695
Short name T2582
Test name
Test status
Simulation time 22579279128 ps
CPU time 428.1 seconds
Started Aug 08 07:58:30 PM PDT 24
Finished Aug 08 08:05:38 PM PDT 24
Peak memory 576032 kb
Host smart-5c89a2c6-a919-4b2c-a57d-a1a6df1c794b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444817695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_d
evice_slow_rsp.444817695
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.3893850202
Short name T2677
Test name
Test status
Simulation time 94126258 ps
CPU time 13.42 seconds
Started Aug 08 07:58:30 PM PDT 24
Finished Aug 08 07:58:43 PM PDT 24
Peak memory 575968 kb
Host smart-7831c546-5823-4295-8b03-c4bc1205564d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893850202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add
r.3893850202
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_error_random.2252315825
Short name T1793
Test name
Test status
Simulation time 2085789537 ps
CPU time 65.63 seconds
Started Aug 08 07:58:29 PM PDT 24
Finished Aug 08 07:59:35 PM PDT 24
Peak memory 575768 kb
Host smart-ca78dcd2-cb8a-45e6-9ab1-78e5fdcfb395
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252315825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2252315825
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random.2276409272
Short name T1541
Test name
Test status
Simulation time 161749297 ps
CPU time 17.79 seconds
Started Aug 08 07:58:20 PM PDT 24
Finished Aug 08 07:58:38 PM PDT 24
Peak memory 575828 kb
Host smart-eed7330d-d3c1-483e-90dc-2a72ddd1c5d9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276409272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.2276409272
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.2569146540
Short name T2287
Test name
Test status
Simulation time 59308079458 ps
CPU time 609.91 seconds
Started Aug 08 07:58:18 PM PDT 24
Finished Aug 08 08:08:28 PM PDT 24
Peak memory 575984 kb
Host smart-6b2cf87e-b3c0-433a-98f5-463f5d376867
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569146540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2569146540
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.1210011906
Short name T2589
Test name
Test status
Simulation time 28757965926 ps
CPU time 530.43 seconds
Started Aug 08 07:58:18 PM PDT 24
Finished Aug 08 08:07:08 PM PDT 24
Peak memory 576720 kb
Host smart-060c32fa-f3da-469a-9f9d-962b8ce6f1a3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210011906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1210011906
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.2337795746
Short name T2718
Test name
Test status
Simulation time 373860604 ps
CPU time 30.11 seconds
Started Aug 08 07:58:16 PM PDT 24
Finished Aug 08 07:58:46 PM PDT 24
Peak memory 575948 kb
Host smart-4ccc4f6e-3b5f-4dc5-9c41-d4efc13458bb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337795746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del
ays.2337795746
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_same_source.2730719504
Short name T2247
Test name
Test status
Simulation time 254359919 ps
CPU time 10.05 seconds
Started Aug 08 07:58:29 PM PDT 24
Finished Aug 08 07:58:39 PM PDT 24
Peak memory 575884 kb
Host smart-dea81bbc-e36b-4005-965b-8a3bb64c09ed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730719504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2730719504
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke.3814551574
Short name T2519
Test name
Test status
Simulation time 195825501 ps
CPU time 8.86 seconds
Started Aug 08 07:58:17 PM PDT 24
Finished Aug 08 07:58:26 PM PDT 24
Peak memory 573804 kb
Host smart-f7d5e60e-6a5c-4638-9da5-fc7c3d4e9e66
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814551574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3814551574
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.93043713
Short name T2524
Test name
Test status
Simulation time 8085409611 ps
CPU time 81.04 seconds
Started Aug 08 07:58:22 PM PDT 24
Finished Aug 08 07:59:43 PM PDT 24
Peak memory 573868 kb
Host smart-350e5ded-a6f2-4efc-a389-165bc1b30f91
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93043713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.93043713
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.1187673148
Short name T1488
Test name
Test status
Simulation time 4081627924 ps
CPU time 71.82 seconds
Started Aug 08 07:58:18 PM PDT 24
Finished Aug 08 07:59:30 PM PDT 24
Peak memory 573840 kb
Host smart-bd3bc779-71f6-4765-80f9-336005cea40c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187673148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1187673148
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.3679953231
Short name T2176
Test name
Test status
Simulation time 38667010 ps
CPU time 6.03 seconds
Started Aug 08 07:58:18 PM PDT 24
Finished Aug 08 07:58:24 PM PDT 24
Peak memory 573748 kb
Host smart-30c108e1-e80c-47e5-9fdc-113e87e4df76
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679953231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay
s.3679953231
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all.4269503786
Short name T2212
Test name
Test status
Simulation time 7399136857 ps
CPU time 218.06 seconds
Started Aug 08 07:58:39 PM PDT 24
Finished Aug 08 08:02:17 PM PDT 24
Peak memory 576588 kb
Host smart-a3e70da4-36eb-4dc8-9fb3-0232fed9a964
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269503786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.4269503786
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.1681787848
Short name T1495
Test name
Test status
Simulation time 2472143791 ps
CPU time 188.04 seconds
Started Aug 08 07:58:30 PM PDT 24
Finished Aug 08 08:01:38 PM PDT 24
Peak memory 576156 kb
Host smart-30dbf862-dbbb-4c5a-bf75-ce299223689f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681787848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1681787848
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.1032099992
Short name T2704
Test name
Test status
Simulation time 14111601855 ps
CPU time 628.94 seconds
Started Aug 08 07:58:30 PM PDT 24
Finished Aug 08 08:08:59 PM PDT 24
Peak memory 575932 kb
Host smart-a23e55a7-4f40-4eee-88f4-fde0ea2c9adf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032099992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all
_with_rand_reset.1032099992
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1385622965
Short name T1629
Test name
Test status
Simulation time 3908913055 ps
CPU time 329.65 seconds
Started Aug 08 07:58:31 PM PDT 24
Finished Aug 08 08:04:00 PM PDT 24
Peak memory 576808 kb
Host smart-102fe01d-9393-44b0-a6d0-74de3d42da8c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385622965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al
l_with_reset_error.1385622965
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.785211167
Short name T2697
Test name
Test status
Simulation time 852842212 ps
CPU time 30.89 seconds
Started Aug 08 07:58:38 PM PDT 24
Finished Aug 08 07:59:09 PM PDT 24
Peak memory 575892 kb
Host smart-19e52a27-6120-4b9b-9fd5-a172ec8b5c16
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785211167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.785211167
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_access_same_device.1740671789
Short name T2285
Test name
Test status
Simulation time 1470202411 ps
CPU time 65.73 seconds
Started Aug 08 07:58:30 PM PDT 24
Finished Aug 08 07:59:36 PM PDT 24
Peak memory 575796 kb
Host smart-3b950565-a1e3-41e3-99b6-4b63a866ccac
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740671789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device
.1740671789
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.2861914642
Short name T821
Test name
Test status
Simulation time 37260014776 ps
CPU time 616.48 seconds
Started Aug 08 07:58:39 PM PDT 24
Finished Aug 08 08:08:55 PM PDT 24
Peak memory 575916 kb
Host smart-75548676-c69a-42dc-806f-11e3db8df2a0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861914642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_
device_slow_rsp.2861914642
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.1685216208
Short name T1727
Test name
Test status
Simulation time 936212198 ps
CPU time 35.74 seconds
Started Aug 08 07:58:42 PM PDT 24
Finished Aug 08 07:59:17 PM PDT 24
Peak memory 575720 kb
Host smart-fb36e921-2658-4663-9057-bbf26e8a4502
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685216208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add
r.1685216208
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_error_random.3629488379
Short name T668
Test name
Test status
Simulation time 542974144 ps
CPU time 42.29 seconds
Started Aug 08 07:58:30 PM PDT 24
Finished Aug 08 07:59:12 PM PDT 24
Peak memory 575820 kb
Host smart-2bb5e42f-d654-4659-b150-991646f02a01
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629488379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3629488379
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random.1721683046
Short name T591
Test name
Test status
Simulation time 384851245 ps
CPU time 14.11 seconds
Started Aug 08 07:58:39 PM PDT 24
Finished Aug 08 07:58:53 PM PDT 24
Peak memory 575724 kb
Host smart-d84814b6-7bb9-4365-81ef-8b41a529fe2c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721683046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.1721683046
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.3331307462
Short name T2558
Test name
Test status
Simulation time 38826528810 ps
CPU time 389.39 seconds
Started Aug 08 07:58:30 PM PDT 24
Finished Aug 08 08:04:59 PM PDT 24
Peak memory 576744 kb
Host smart-ac1c926d-e44f-4c58-9b55-9d9224e71a6b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331307462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3331307462
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.125533158
Short name T1817
Test name
Test status
Simulation time 3711816722 ps
CPU time 61.08 seconds
Started Aug 08 07:58:29 PM PDT 24
Finished Aug 08 07:59:31 PM PDT 24
Peak memory 573896 kb
Host smart-77381035-e9a1-4de4-8a5f-ae27e9c613bc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125533158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.125533158
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.754749188
Short name T2006
Test name
Test status
Simulation time 246223945 ps
CPU time 23.59 seconds
Started Aug 08 07:58:32 PM PDT 24
Finished Aug 08 07:58:56 PM PDT 24
Peak memory 575728 kb
Host smart-6e5bafe9-5965-41f9-abad-a18105e3c131
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754749188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_dela
ys.754749188
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_same_source.4159429769
Short name T2460
Test name
Test status
Simulation time 85689412 ps
CPU time 9.05 seconds
Started Aug 08 07:58:30 PM PDT 24
Finished Aug 08 07:58:39 PM PDT 24
Peak memory 575828 kb
Host smart-0fd5cceb-a51a-48d4-b144-169508f3fe07
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159429769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.4159429769
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke.1319062959
Short name T2872
Test name
Test status
Simulation time 50024115 ps
CPU time 6.95 seconds
Started Aug 08 07:58:29 PM PDT 24
Finished Aug 08 07:58:36 PM PDT 24
Peak memory 573796 kb
Host smart-8d6dfb31-fd17-42d2-8e4b-772d081b1e25
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319062959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1319062959
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.391517712
Short name T2177
Test name
Test status
Simulation time 7997723723 ps
CPU time 87.22 seconds
Started Aug 08 07:58:32 PM PDT 24
Finished Aug 08 08:00:00 PM PDT 24
Peak memory 574528 kb
Host smart-da1b337d-f84c-4545-b737-0cbd528ad02e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391517712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.391517712
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.1535669427
Short name T1553
Test name
Test status
Simulation time 3785262398 ps
CPU time 63.95 seconds
Started Aug 08 07:58:28 PM PDT 24
Finished Aug 08 07:59:32 PM PDT 24
Peak memory 573888 kb
Host smart-a403e092-ca7d-420b-9d70-8636efa85494
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535669427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1535669427
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2902660358
Short name T2676
Test name
Test status
Simulation time 39979170 ps
CPU time 6.42 seconds
Started Aug 08 07:58:30 PM PDT 24
Finished Aug 08 07:58:37 PM PDT 24
Peak memory 573772 kb
Host smart-8bf7ee5d-2fad-48a1-8ba4-04c4bf1309d5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902660358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay
s.2902660358
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all.2039414467
Short name T2391
Test name
Test status
Simulation time 3108730962 ps
CPU time 242.3 seconds
Started Aug 08 07:58:41 PM PDT 24
Finished Aug 08 08:02:44 PM PDT 24
Peak memory 575908 kb
Host smart-25e14574-2bee-45d0-b207-71cff16b473f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039414467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2039414467
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.2831963776
Short name T823
Test name
Test status
Simulation time 10954804029 ps
CPU time 395.47 seconds
Started Aug 08 07:58:42 PM PDT 24
Finished Aug 08 08:05:18 PM PDT 24
Peak memory 576808 kb
Host smart-f7a64178-2a19-428c-b3c8-ac9c7e6e12a7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831963776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2831963776
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.2678075000
Short name T1836
Test name
Test status
Simulation time 460305675 ps
CPU time 164.87 seconds
Started Aug 08 07:58:41 PM PDT 24
Finished Aug 08 08:01:26 PM PDT 24
Peak memory 575912 kb
Host smart-f1d0ca75-fa82-4a2d-bdb2-9ee8b75ca20e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678075000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all
_with_rand_reset.2678075000
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.846306830
Short name T2242
Test name
Test status
Simulation time 463501581 ps
CPU time 82.21 seconds
Started Aug 08 07:58:43 PM PDT 24
Finished Aug 08 08:00:06 PM PDT 24
Peak memory 575888 kb
Host smart-f93f0742-5235-4950-9b44-63190c99e7d4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846306830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all
_with_reset_error.846306830
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.1065278210
Short name T1778
Test name
Test status
Simulation time 1366057885 ps
CPU time 51.04 seconds
Started Aug 08 07:58:39 PM PDT 24
Finished Aug 08 07:59:30 PM PDT 24
Peak memory 575872 kb
Host smart-079d1d45-3274-48bd-a8d4-81cc347aa804
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065278210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1065278210
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_access_same_device.2749071427
Short name T775
Test name
Test status
Simulation time 2142086973 ps
CPU time 89.62 seconds
Started Aug 08 07:58:43 PM PDT 24
Finished Aug 08 08:00:12 PM PDT 24
Peak memory 575856 kb
Host smart-25bca1ff-d1f0-4c5c-af0d-6d6295ff2e3c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749071427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device
.2749071427
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.3880786864
Short name T2201
Test name
Test status
Simulation time 10579567462 ps
CPU time 175.8 seconds
Started Aug 08 07:58:46 PM PDT 24
Finished Aug 08 08:01:42 PM PDT 24
Peak memory 574532 kb
Host smart-3feb2141-1e99-414c-8871-422ac3af8578
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880786864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_
device_slow_rsp.3880786864
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1580814116
Short name T2559
Test name
Test status
Simulation time 134161589 ps
CPU time 18.07 seconds
Started Aug 08 07:58:45 PM PDT 24
Finished Aug 08 07:59:03 PM PDT 24
Peak memory 575848 kb
Host smart-ca86ef05-1d31-4e08-a158-60c572261187
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580814116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add
r.1580814116
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_error_random.1720950449
Short name T1844
Test name
Test status
Simulation time 1254763224 ps
CPU time 41.52 seconds
Started Aug 08 07:58:46 PM PDT 24
Finished Aug 08 07:59:28 PM PDT 24
Peak memory 575708 kb
Host smart-2507595c-5877-453a-8c58-e4ecd3452f6a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720950449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1720950449
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random.2492956946
Short name T2579
Test name
Test status
Simulation time 87960827 ps
CPU time 9.5 seconds
Started Aug 08 07:58:45 PM PDT 24
Finished Aug 08 07:58:55 PM PDT 24
Peak memory 575808 kb
Host smart-b5418635-f692-4de1-9451-a04e6a800eeb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492956946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.2492956946
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.1035853975
Short name T2621
Test name
Test status
Simulation time 77971426517 ps
CPU time 804.98 seconds
Started Aug 08 07:58:44 PM PDT 24
Finished Aug 08 08:12:10 PM PDT 24
Peak memory 575856 kb
Host smart-20ba705a-37db-408e-aa1f-dbf5415b0121
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035853975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1035853975
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.2514084044
Short name T1496
Test name
Test status
Simulation time 4448372494 ps
CPU time 78.04 seconds
Started Aug 08 07:58:47 PM PDT 24
Finished Aug 08 08:00:05 PM PDT 24
Peak memory 574552 kb
Host smart-fe68ca05-0441-483a-86a3-871a5ebfcf81
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514084044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2514084044
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.154024720
Short name T1671
Test name
Test status
Simulation time 512360599 ps
CPU time 40.1 seconds
Started Aug 08 07:58:41 PM PDT 24
Finished Aug 08 07:59:21 PM PDT 24
Peak memory 575688 kb
Host smart-48b4537c-1eea-4544-bfe2-add5419e2f36
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154024720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_dela
ys.154024720
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_same_source.3700296924
Short name T1944
Test name
Test status
Simulation time 1369371537 ps
CPU time 43.57 seconds
Started Aug 08 07:58:43 PM PDT 24
Finished Aug 08 07:59:27 PM PDT 24
Peak memory 575768 kb
Host smart-e49d2370-34b1-4032-aaeb-e39d4b2a3dd6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700296924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3700296924
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke.2757999914
Short name T1846
Test name
Test status
Simulation time 50160543 ps
CPU time 6.69 seconds
Started Aug 08 07:58:42 PM PDT 24
Finished Aug 08 07:58:48 PM PDT 24
Peak memory 573788 kb
Host smart-b008d562-2941-4462-8267-ba68bdd0b459
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757999914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2757999914
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.3585422624
Short name T1366
Test name
Test status
Simulation time 8138798246 ps
CPU time 86.09 seconds
Started Aug 08 07:58:41 PM PDT 24
Finished Aug 08 08:00:07 PM PDT 24
Peak memory 573868 kb
Host smart-bb39ea20-5264-4274-837d-d9830e0db97e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585422624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3585422624
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.279758343
Short name T2528
Test name
Test status
Simulation time 5577675009 ps
CPU time 95.52 seconds
Started Aug 08 07:58:41 PM PDT 24
Finished Aug 08 08:00:16 PM PDT 24
Peak memory 574592 kb
Host smart-e947d0f2-af59-482b-842f-d6973851a5ad
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279758343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.279758343
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.4273762616
Short name T1938
Test name
Test status
Simulation time 53485626 ps
CPU time 7.1 seconds
Started Aug 08 07:58:43 PM PDT 24
Finished Aug 08 07:58:50 PM PDT 24
Peak memory 573808 kb
Host smart-85ac4d39-924b-4da7-b9a6-afe7e02cd5d8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273762616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay
s.4273762616
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all.1920622154
Short name T2184
Test name
Test status
Simulation time 7908088687 ps
CPU time 291.46 seconds
Started Aug 08 07:58:46 PM PDT 24
Finished Aug 08 08:03:37 PM PDT 24
Peak memory 575900 kb
Host smart-21c799e9-4e37-454f-9b3d-292f62babd74
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920622154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1920622154
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.667728750
Short name T482
Test name
Test status
Simulation time 12118381492 ps
CPU time 771.62 seconds
Started Aug 08 07:58:47 PM PDT 24
Finished Aug 08 08:11:38 PM PDT 24
Peak memory 575976 kb
Host smart-b6935a31-33de-4577-8fb1-37d0bf350864
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667728750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_
with_rand_reset.667728750
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.177005351
Short name T2445
Test name
Test status
Simulation time 14984930 ps
CPU time 18.98 seconds
Started Aug 08 07:58:57 PM PDT 24
Finished Aug 08 07:59:16 PM PDT 24
Peak memory 574572 kb
Host smart-824868f8-85af-4a5c-a199-45ac5b346a39
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177005351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all
_with_reset_error.177005351
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.1945282110
Short name T2763
Test name
Test status
Simulation time 1405040728 ps
CPU time 62.76 seconds
Started Aug 08 07:58:40 PM PDT 24
Finished Aug 08 07:59:43 PM PDT 24
Peak memory 575808 kb
Host smart-05cae12f-474e-4d76-878c-1d68ebd65f65
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945282110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1945282110
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_access_same_device.717092736
Short name T2669
Test name
Test status
Simulation time 900233252 ps
CPU time 41.6 seconds
Started Aug 08 07:58:56 PM PDT 24
Finished Aug 08 07:59:38 PM PDT 24
Peak memory 575920 kb
Host smart-e3c363ae-f776-4ab8-9745-91f8ec8e26bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717092736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.
717092736
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.3824775893
Short name T2084
Test name
Test status
Simulation time 46560560574 ps
CPU time 847.82 seconds
Started Aug 08 07:59:00 PM PDT 24
Finished Aug 08 08:13:08 PM PDT 24
Peak memory 575880 kb
Host smart-b30de2e7-e211-42f0-a240-4ff1e17f2161
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824775893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_
device_slow_rsp.3824775893
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2733900781
Short name T1815
Test name
Test status
Simulation time 54378505 ps
CPU time 8.93 seconds
Started Aug 08 07:58:54 PM PDT 24
Finished Aug 08 07:59:03 PM PDT 24
Peak memory 575876 kb
Host smart-f036af0c-35dd-4279-afbe-f84516829aa1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733900781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add
r.2733900781
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_error_random.1206607668
Short name T2717
Test name
Test status
Simulation time 33425649 ps
CPU time 6.15 seconds
Started Aug 08 07:59:00 PM PDT 24
Finished Aug 08 07:59:06 PM PDT 24
Peak memory 573840 kb
Host smart-63d4e801-cfe1-4d2f-8cd7-fee4ae019589
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206607668 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1206607668
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random.4159279642
Short name T2848
Test name
Test status
Simulation time 853080991 ps
CPU time 28.46 seconds
Started Aug 08 07:58:54 PM PDT 24
Finished Aug 08 07:59:22 PM PDT 24
Peak memory 575848 kb
Host smart-a3030791-72a9-488d-b318-e08b9f70d7aa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159279642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.4159279642
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.4153803134
Short name T2871
Test name
Test status
Simulation time 72765787599 ps
CPU time 785.65 seconds
Started Aug 08 07:58:54 PM PDT 24
Finished Aug 08 08:12:00 PM PDT 24
Peak memory 575892 kb
Host smart-96ac881e-9008-4a4b-bf38-eca09f417545
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153803134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.4153803134
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.831295538
Short name T2360
Test name
Test status
Simulation time 25200159250 ps
CPU time 431.04 seconds
Started Aug 08 07:58:57 PM PDT 24
Finished Aug 08 08:06:08 PM PDT 24
Peak memory 575820 kb
Host smart-93998326-bc34-4568-9fc7-de71c63ac4df
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831295538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.831295538
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.3781567539
Short name T566
Test name
Test status
Simulation time 448559611 ps
CPU time 44.53 seconds
Started Aug 08 07:58:56 PM PDT 24
Finished Aug 08 07:59:41 PM PDT 24
Peak memory 575904 kb
Host smart-f25254cb-a93c-4fd6-9557-15719a5428ba
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781567539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del
ays.3781567539
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_same_source.590097123
Short name T2226
Test name
Test status
Simulation time 2555312900 ps
CPU time 74.49 seconds
Started Aug 08 07:58:55 PM PDT 24
Finished Aug 08 08:00:09 PM PDT 24
Peak memory 575764 kb
Host smart-3f7868a7-2dea-421b-8440-306fdd31b6ae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590097123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.590097123
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke.3124271552
Short name T2631
Test name
Test status
Simulation time 222522398 ps
CPU time 9.64 seconds
Started Aug 08 07:58:57 PM PDT 24
Finished Aug 08 07:59:07 PM PDT 24
Peak memory 574440 kb
Host smart-971a272f-cfb9-4054-b1e7-5f2f48d5ca96
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124271552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3124271552
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.501050065
Short name T1532
Test name
Test status
Simulation time 6341012630 ps
CPU time 68.32 seconds
Started Aug 08 07:59:00 PM PDT 24
Finished Aug 08 08:00:09 PM PDT 24
Peak memory 574572 kb
Host smart-1508421a-584e-4a51-b841-c6a4a0f3f74d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501050065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.501050065
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.3557047368
Short name T2258
Test name
Test status
Simulation time 4076629815 ps
CPU time 67.77 seconds
Started Aug 08 07:58:57 PM PDT 24
Finished Aug 08 08:00:04 PM PDT 24
Peak memory 573888 kb
Host smart-7d1261a6-d3ee-4aa1-9f69-16d7b6e1051e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557047368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3557047368
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.1939610284
Short name T1591
Test name
Test status
Simulation time 44331338 ps
CPU time 5.95 seconds
Started Aug 08 07:58:56 PM PDT 24
Finished Aug 08 07:59:02 PM PDT 24
Peak memory 573788 kb
Host smart-98ca463e-648e-4682-a5cf-89a5c12bc5ce
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939610284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay
s.1939610284
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all.2433147897
Short name T2807
Test name
Test status
Simulation time 803671530 ps
CPU time 72.94 seconds
Started Aug 08 07:58:55 PM PDT 24
Finished Aug 08 08:00:08 PM PDT 24
Peak memory 576100 kb
Host smart-5263e11e-a819-4183-9412-4fdd5599522e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433147897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.2433147897
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.181938994
Short name T1847
Test name
Test status
Simulation time 8066425440 ps
CPU time 250.54 seconds
Started Aug 08 07:58:55 PM PDT 24
Finished Aug 08 08:03:05 PM PDT 24
Peak memory 575920 kb
Host smart-82e2682c-0490-4226-921c-157729d71032
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181938994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.181938994
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.532852423
Short name T1893
Test name
Test status
Simulation time 62215188 ps
CPU time 24.92 seconds
Started Aug 08 07:58:57 PM PDT 24
Finished Aug 08 07:59:22 PM PDT 24
Peak memory 575840 kb
Host smart-2c57a8f7-7b2f-4f23-beab-c45c107a2250
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532852423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all
_with_reset_error.532852423
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.803822708
Short name T2157
Test name
Test status
Simulation time 998885187 ps
CPU time 41.42 seconds
Started Aug 08 07:58:56 PM PDT 24
Finished Aug 08 07:59:37 PM PDT 24
Peak memory 575872 kb
Host smart-617b5a0b-f4ef-478a-ab64-b86a7ef8f866
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803822708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.803822708
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_access_same_device.2264626664
Short name T2094
Test name
Test status
Simulation time 2672612000 ps
CPU time 106.33 seconds
Started Aug 08 07:59:22 PM PDT 24
Finished Aug 08 08:01:08 PM PDT 24
Peak memory 575984 kb
Host smart-c3ee0ec5-f043-47f5-8971-a0a12b18f5df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264626664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device
.2264626664
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.1971744018
Short name T2427
Test name
Test status
Simulation time 11423741737 ps
CPU time 191 seconds
Started Aug 08 07:59:22 PM PDT 24
Finished Aug 08 08:02:33 PM PDT 24
Peak memory 573912 kb
Host smart-20a7d371-a4bd-48fd-9607-50dfe0e7c665
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971744018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_
device_slow_rsp.1971744018
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.2151334488
Short name T2804
Test name
Test status
Simulation time 65747399 ps
CPU time 10.16 seconds
Started Aug 08 07:59:57 PM PDT 24
Finished Aug 08 08:00:07 PM PDT 24
Peak memory 575828 kb
Host smart-0e94b353-da1e-445c-8934-46be7649e68c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151334488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add
r.2151334488
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_error_random.3893620043
Short name T2692
Test name
Test status
Simulation time 881081283 ps
CPU time 31.95 seconds
Started Aug 08 08:00:01 PM PDT 24
Finished Aug 08 08:00:33 PM PDT 24
Peak memory 575464 kb
Host smart-f233fbee-7914-4e1d-b692-c633e76b131c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893620043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3893620043
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random.1761883317
Short name T2685
Test name
Test status
Simulation time 1991265655 ps
CPU time 74.11 seconds
Started Aug 08 07:59:22 PM PDT 24
Finished Aug 08 08:00:36 PM PDT 24
Peak memory 575924 kb
Host smart-09194e31-7dab-413d-8fe4-8f5dfcc6311d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761883317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.1761883317
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.1508107931
Short name T2664
Test name
Test status
Simulation time 35015032948 ps
CPU time 358.13 seconds
Started Aug 08 07:59:21 PM PDT 24
Finished Aug 08 08:05:19 PM PDT 24
Peak memory 575828 kb
Host smart-1f01283e-9df4-4aa9-804b-4f9a5725a280
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508107931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1508107931
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.433273255
Short name T2407
Test name
Test status
Simulation time 42591221078 ps
CPU time 735.62 seconds
Started Aug 08 07:59:22 PM PDT 24
Finished Aug 08 08:11:38 PM PDT 24
Peak memory 575984 kb
Host smart-fc8a5823-4d45-4331-bed8-75483e1218b6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433273255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.433273255
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.1294661135
Short name T2434
Test name
Test status
Simulation time 291447422 ps
CPU time 25.86 seconds
Started Aug 08 07:59:23 PM PDT 24
Finished Aug 08 07:59:48 PM PDT 24
Peak memory 575804 kb
Host smart-10da4685-f1a0-498b-bdf1-e68b66121020
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294661135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del
ays.1294661135
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_same_source.2581998177
Short name T1415
Test name
Test status
Simulation time 657364017 ps
CPU time 22.65 seconds
Started Aug 08 07:59:59 PM PDT 24
Finished Aug 08 08:00:22 PM PDT 24
Peak memory 575896 kb
Host smart-08b4ab6e-85f3-4095-8498-8bc3bb1769d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581998177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2581998177
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke.2382991056
Short name T2652
Test name
Test status
Simulation time 175760805 ps
CPU time 8.35 seconds
Started Aug 08 07:59:22 PM PDT 24
Finished Aug 08 07:59:31 PM PDT 24
Peak memory 574452 kb
Host smart-352de06a-8037-4dfa-80c4-5269fa065f70
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382991056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2382991056
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.2113121605
Short name T1518
Test name
Test status
Simulation time 9313489145 ps
CPU time 94.43 seconds
Started Aug 08 07:59:23 PM PDT 24
Finished Aug 08 08:00:57 PM PDT 24
Peak memory 574604 kb
Host smart-27a86f68-224d-4b8e-bfb9-1216f7e265ea
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113121605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2113121605
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.783556916
Short name T1400
Test name
Test status
Simulation time 4681503249 ps
CPU time 80.12 seconds
Started Aug 08 07:59:22 PM PDT 24
Finished Aug 08 08:00:42 PM PDT 24
Peak memory 573872 kb
Host smart-2d680ce9-b010-461e-97d3-3bf7e3823505
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783556916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.783556916
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.3490443091
Short name T1921
Test name
Test status
Simulation time 47752120 ps
CPU time 6.54 seconds
Started Aug 08 07:59:23 PM PDT 24
Finished Aug 08 07:59:30 PM PDT 24
Peak memory 574492 kb
Host smart-3fef55c9-31f1-43b6-be2d-a0e6ead95139
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490443091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay
s.3490443091
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all.3743691776
Short name T1947
Test name
Test status
Simulation time 5544936580 ps
CPU time 187.08 seconds
Started Aug 08 08:00:00 PM PDT 24
Finished Aug 08 08:03:07 PM PDT 24
Peak memory 575964 kb
Host smart-ed279fb6-39af-4aa6-8d9b-a805bf3c2e59
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743691776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3743691776
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.2673522188
Short name T2755
Test name
Test status
Simulation time 2135000484 ps
CPU time 85.82 seconds
Started Aug 08 07:59:58 PM PDT 24
Finished Aug 08 08:01:24 PM PDT 24
Peak memory 576008 kb
Host smart-997e7dbb-8640-4753-84d6-488422fbdc15
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673522188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2673522188
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.2658479665
Short name T1871
Test name
Test status
Simulation time 10482828703 ps
CPU time 459.6 seconds
Started Aug 08 08:00:00 PM PDT 24
Finished Aug 08 08:07:40 PM PDT 24
Peak memory 576804 kb
Host smart-1174cfaf-ea9a-421e-bb7e-db5970d3dd3a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658479665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all
_with_rand_reset.2658479665
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.2515068175
Short name T2728
Test name
Test status
Simulation time 2573551282 ps
CPU time 149.31 seconds
Started Aug 08 07:59:57 PM PDT 24
Finished Aug 08 08:02:27 PM PDT 24
Peak memory 576720 kb
Host smart-666bb72a-9609-480c-9986-3ddbfb54d6fc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515068175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al
l_with_reset_error.2515068175
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.3190539662
Short name T460
Test name
Test status
Simulation time 230487821 ps
CPU time 29.77 seconds
Started Aug 08 08:00:00 PM PDT 24
Finished Aug 08 08:00:29 PM PDT 24
Peak memory 575912 kb
Host smart-3b9a38fb-3d0f-4d81-b523-b71ea5d4764e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190539662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3190539662
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_access_same_device.3288597826
Short name T1515
Test name
Test status
Simulation time 358378691 ps
CPU time 29 seconds
Started Aug 08 07:59:59 PM PDT 24
Finished Aug 08 08:00:28 PM PDT 24
Peak memory 575904 kb
Host smart-a67b5166-f535-48dd-bbe9-746c6decfd9b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288597826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device
.3288597826
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.3409929282
Short name T1914
Test name
Test status
Simulation time 29587791958 ps
CPU time 495.32 seconds
Started Aug 08 08:00:00 PM PDT 24
Finished Aug 08 08:08:15 PM PDT 24
Peak memory 575880 kb
Host smart-77487971-9017-42d6-ac04-11f3afbe8834
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409929282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_
device_slow_rsp.3409929282
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.1122362151
Short name T2561
Test name
Test status
Simulation time 267639623 ps
CPU time 31.87 seconds
Started Aug 08 08:00:01 PM PDT 24
Finished Aug 08 08:00:33 PM PDT 24
Peak memory 575660 kb
Host smart-87637c82-7d6e-48c8-a15e-2e4f6ae494c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122362151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add
r.1122362151
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_error_random.2165680808
Short name T1392
Test name
Test status
Simulation time 1111862714 ps
CPU time 40.59 seconds
Started Aug 08 07:59:58 PM PDT 24
Finished Aug 08 08:00:38 PM PDT 24
Peak memory 575852 kb
Host smart-e9a6b778-d4d5-47bd-aaac-cbcb54c38639
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165680808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2165680808
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random.1020811612
Short name T1560
Test name
Test status
Simulation time 134744776 ps
CPU time 13.83 seconds
Started Aug 08 07:59:58 PM PDT 24
Finished Aug 08 08:00:12 PM PDT 24
Peak memory 575880 kb
Host smart-d294efc0-64a9-4daf-8623-a90a3573d949
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020811612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.1020811612
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.1583957475
Short name T2492
Test name
Test status
Simulation time 31969723605 ps
CPU time 330.67 seconds
Started Aug 08 08:00:02 PM PDT 24
Finished Aug 08 08:05:37 PM PDT 24
Peak memory 575948 kb
Host smart-28e6c4c1-7800-4430-8909-e9cc1e4f1b4b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583957475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1583957475
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.3885511192
Short name T547
Test name
Test status
Simulation time 61380590996 ps
CPU time 1047.64 seconds
Started Aug 08 07:59:59 PM PDT 24
Finished Aug 08 08:17:27 PM PDT 24
Peak memory 576036 kb
Host smart-c20656aa-aa04-4202-ba2a-1403e3745822
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885511192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3885511192
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.1390551241
Short name T2526
Test name
Test status
Simulation time 181153715 ps
CPU time 16.55 seconds
Started Aug 08 07:59:59 PM PDT 24
Finished Aug 08 08:00:16 PM PDT 24
Peak memory 575864 kb
Host smart-0e98e73c-a1ed-4df2-9849-acdccc0630f1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390551241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del
ays.1390551241
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_same_source.2280234877
Short name T1686
Test name
Test status
Simulation time 128890762 ps
CPU time 12.24 seconds
Started Aug 08 07:59:56 PM PDT 24
Finished Aug 08 08:00:09 PM PDT 24
Peak memory 575872 kb
Host smart-2f8d290e-84d2-4fc4-bd5a-e9174149f761
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280234877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2280234877
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke.386078392
Short name T1685
Test name
Test status
Simulation time 46393084 ps
CPU time 6.39 seconds
Started Aug 08 08:00:00 PM PDT 24
Finished Aug 08 08:00:07 PM PDT 24
Peak memory 574452 kb
Host smart-6a75c4f5-c449-46a3-991c-c19b74c95519
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386078392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.386078392
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.3575629135
Short name T1426
Test name
Test status
Simulation time 9123717790 ps
CPU time 100.56 seconds
Started Aug 08 08:00:02 PM PDT 24
Finished Aug 08 08:01:47 PM PDT 24
Peak memory 573884 kb
Host smart-2dc698af-5c5f-458f-a3e6-9966f49479c2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575629135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3575629135
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1599513905
Short name T2846
Test name
Test status
Simulation time 4127903021 ps
CPU time 74.06 seconds
Started Aug 08 07:59:57 PM PDT 24
Finished Aug 08 08:01:11 PM PDT 24
Peak memory 573840 kb
Host smart-317995c0-9de7-481d-ae04-d2f90dcd43de
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599513905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1599513905
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.294331786
Short name T2661
Test name
Test status
Simulation time 56875488 ps
CPU time 7.34 seconds
Started Aug 08 07:59:59 PM PDT 24
Finished Aug 08 08:00:07 PM PDT 24
Peak memory 574484 kb
Host smart-5388b8dd-341f-4e72-8da1-0d30c714ff87
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294331786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays
.294331786
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all.3109256045
Short name T448
Test name
Test status
Simulation time 9141178976 ps
CPU time 368.39 seconds
Started Aug 08 08:00:00 PM PDT 24
Finished Aug 08 08:06:09 PM PDT 24
Peak memory 575912 kb
Host smart-30af55df-afcf-4b51-895e-953c64e5296c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109256045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3109256045
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2503887862
Short name T1440
Test name
Test status
Simulation time 91122422 ps
CPU time 19.68 seconds
Started Aug 08 08:00:01 PM PDT 24
Finished Aug 08 08:00:21 PM PDT 24
Peak memory 576020 kb
Host smart-74a051b0-8156-46c9-97e6-2d3af7afadbf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503887862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all
_with_rand_reset.2503887862
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3990580894
Short name T782
Test name
Test status
Simulation time 3903897055 ps
CPU time 408.46 seconds
Started Aug 08 08:00:02 PM PDT 24
Finished Aug 08 08:06:55 PM PDT 24
Peak memory 576780 kb
Host smart-14cec83b-d2ab-4587-ba1c-c83d32906306
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990580894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al
l_with_reset_error.3990580894
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.2907370883
Short name T2573
Test name
Test status
Simulation time 195968806 ps
CPU time 11.88 seconds
Started Aug 08 08:00:02 PM PDT 24
Finished Aug 08 08:00:18 PM PDT 24
Peak memory 575888 kb
Host smart-312cf6d8-2e21-4b07-a41d-3277dfd264a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907370883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2907370883
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_access_same_device.2945449224
Short name T2785
Test name
Test status
Simulation time 2213646077 ps
CPU time 87.19 seconds
Started Aug 08 07:59:59 PM PDT 24
Finished Aug 08 08:01:26 PM PDT 24
Peak memory 575992 kb
Host smart-b86ba5e4-b6a7-44a9-8750-e2429c21132a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945449224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device
.2945449224
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.2661148945
Short name T2727
Test name
Test status
Simulation time 59225754521 ps
CPU time 1066.21 seconds
Started Aug 08 07:59:58 PM PDT 24
Finished Aug 08 08:17:45 PM PDT 24
Peak memory 575960 kb
Host smart-2384a9db-e2b6-468f-b134-8f1772129407
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661148945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_
device_slow_rsp.2661148945
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.3345919812
Short name T1448
Test name
Test status
Simulation time 1139041131 ps
CPU time 44.32 seconds
Started Aug 08 08:00:00 PM PDT 24
Finished Aug 08 08:00:44 PM PDT 24
Peak memory 575740 kb
Host smart-ce73202d-5d79-4b08-abca-72b8af2b183f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345919812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add
r.3345919812
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_error_random.861371780
Short name T2802
Test name
Test status
Simulation time 1922954670 ps
CPU time 62.03 seconds
Started Aug 08 08:00:00 PM PDT 24
Finished Aug 08 08:01:02 PM PDT 24
Peak memory 575720 kb
Host smart-6fd5bec0-69ff-4f2f-9520-7193b9dfd51d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861371780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.861371780
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random.2858452403
Short name T1409
Test name
Test status
Simulation time 401624241 ps
CPU time 35.08 seconds
Started Aug 08 08:00:00 PM PDT 24
Finished Aug 08 08:00:35 PM PDT 24
Peak memory 575892 kb
Host smart-042b4343-bf6a-4085-90a0-399454c37802
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858452403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.2858452403
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.892880060
Short name T1723
Test name
Test status
Simulation time 77901425021 ps
CPU time 847.7 seconds
Started Aug 08 08:00:00 PM PDT 24
Finished Aug 08 08:14:08 PM PDT 24
Peak memory 576008 kb
Host smart-2910ce1d-8f37-4148-9385-b533483665d8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892880060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.892880060
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.1217994487
Short name T2568
Test name
Test status
Simulation time 33215253479 ps
CPU time 546.42 seconds
Started Aug 08 08:00:02 PM PDT 24
Finished Aug 08 08:09:13 PM PDT 24
Peak memory 575848 kb
Host smart-b4eca1f4-a655-49c1-a35c-a8b429714826
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217994487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.1217994487
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.2432486888
Short name T555
Test name
Test status
Simulation time 190895565 ps
CPU time 17.41 seconds
Started Aug 08 07:59:58 PM PDT 24
Finished Aug 08 08:00:16 PM PDT 24
Peak memory 575728 kb
Host smart-4b68ea99-1381-4149-a394-d413ea6e3346
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432486888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del
ays.2432486888
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_same_source.678598109
Short name T1824
Test name
Test status
Simulation time 1120247624 ps
CPU time 35.25 seconds
Started Aug 08 07:59:57 PM PDT 24
Finished Aug 08 08:00:33 PM PDT 24
Peak memory 575796 kb
Host smart-1274879f-8ea2-4e87-919e-f02b3b75dcf9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678598109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.678598109
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke.3029602952
Short name T2123
Test name
Test status
Simulation time 54616339 ps
CPU time 7.03 seconds
Started Aug 08 07:59:59 PM PDT 24
Finished Aug 08 08:00:07 PM PDT 24
Peak memory 573768 kb
Host smart-2a5de26e-8f7c-4055-a4c8-e2685ae63510
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029602952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3029602952
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.2038309155
Short name T2073
Test name
Test status
Simulation time 5901710414 ps
CPU time 60.83 seconds
Started Aug 08 07:59:59 PM PDT 24
Finished Aug 08 08:00:59 PM PDT 24
Peak memory 573900 kb
Host smart-81eb5ed3-c498-4eaa-9cae-55290ff90675
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038309155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2038309155
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1616410558
Short name T1360
Test name
Test status
Simulation time 3229979094 ps
CPU time 54.98 seconds
Started Aug 08 07:59:57 PM PDT 24
Finished Aug 08 08:00:52 PM PDT 24
Peak memory 574540 kb
Host smart-fb95256e-f40f-4ffc-ac76-3f382fd9adaf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616410558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1616410558
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.2514250316
Short name T1982
Test name
Test status
Simulation time 46794241 ps
CPU time 5.91 seconds
Started Aug 08 07:59:59 PM PDT 24
Finished Aug 08 08:00:05 PM PDT 24
Peak memory 574480 kb
Host smart-4762b24f-7fe7-4201-8e94-8b8434436c41
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514250316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay
s.2514250316
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all.3710428131
Short name T2544
Test name
Test status
Simulation time 6125385724 ps
CPU time 220.36 seconds
Started Aug 08 08:00:00 PM PDT 24
Finished Aug 08 08:03:40 PM PDT 24
Peak memory 575952 kb
Host smart-657ec472-a484-4a26-baa9-e91bd22dedcf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710428131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3710428131
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.1866882360
Short name T2174
Test name
Test status
Simulation time 1633076612 ps
CPU time 43.2 seconds
Started Aug 08 07:59:58 PM PDT 24
Finished Aug 08 08:00:42 PM PDT 24
Peak memory 576008 kb
Host smart-cac5db58-caa1-42c2-844f-c506186fc1df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866882360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1866882360
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.720078440
Short name T1883
Test name
Test status
Simulation time 647999724 ps
CPU time 209.05 seconds
Started Aug 08 08:00:00 PM PDT 24
Finished Aug 08 08:03:29 PM PDT 24
Peak memory 575840 kb
Host smart-dbf7c12e-0028-43af-9045-c253b4d8cf20
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720078440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_
with_rand_reset.720078440
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.492491517
Short name T1583
Test name
Test status
Simulation time 51360061 ps
CPU time 90.05 seconds
Started Aug 08 07:59:59 PM PDT 24
Finished Aug 08 08:01:29 PM PDT 24
Peak memory 576668 kb
Host smart-e07fbaa8-2e3d-4001-a750-8f07c8ecba9a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492491517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all
_with_reset_error.492491517
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.3078888425
Short name T1928
Test name
Test status
Simulation time 47659617 ps
CPU time 7.25 seconds
Started Aug 08 07:59:59 PM PDT 24
Finished Aug 08 08:00:06 PM PDT 24
Peak memory 573848 kb
Host smart-4af30481-cb5a-4170-bfe0-fa6dbeab0ed6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078888425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3078888425
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_access_same_device.322846380
Short name T1768
Test name
Test status
Simulation time 1677241610 ps
CPU time 63.74 seconds
Started Aug 08 07:59:59 PM PDT 24
Finished Aug 08 08:01:03 PM PDT 24
Peak memory 575708 kb
Host smart-accd6396-c93d-439d-8bdd-a5a069a51acc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322846380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.
322846380
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.2651847461
Short name T2314
Test name
Test status
Simulation time 107793913244 ps
CPU time 1703.29 seconds
Started Aug 08 08:00:12 PM PDT 24
Finished Aug 08 08:28:35 PM PDT 24
Peak memory 575860 kb
Host smart-e32be29d-cef3-4a72-8a62-b9abba86da16
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651847461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_
device_slow_rsp.2651847461
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.2212532850
Short name T1775
Test name
Test status
Simulation time 1407605121 ps
CPU time 57.3 seconds
Started Aug 08 08:00:13 PM PDT 24
Finished Aug 08 08:01:10 PM PDT 24
Peak memory 575936 kb
Host smart-f40af6b8-4280-4ffb-9fbd-9d7a2e745432
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212532850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add
r.2212532850
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_error_random.1502923694
Short name T2133
Test name
Test status
Simulation time 266143392 ps
CPU time 23.12 seconds
Started Aug 08 08:00:15 PM PDT 24
Finished Aug 08 08:00:38 PM PDT 24
Peak memory 575968 kb
Host smart-3a16d25f-ae41-461e-8c26-7d36ed702e63
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502923694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.1502923694
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random.20551810
Short name T2100
Test name
Test status
Simulation time 2218088313 ps
CPU time 76.8 seconds
Started Aug 08 07:59:58 PM PDT 24
Finished Aug 08 08:01:15 PM PDT 24
Peak memory 575884 kb
Host smart-88a564e1-648d-4562-80ae-aec6e4b3e2f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20551810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.20551810
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.138675336
Short name T507
Test name
Test status
Simulation time 95839873547 ps
CPU time 1011.18 seconds
Started Aug 08 08:00:00 PM PDT 24
Finished Aug 08 08:16:51 PM PDT 24
Peak memory 575976 kb
Host smart-6c314a5c-59b0-468d-89df-d8afa04a0db2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138675336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.138675336
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.2452505269
Short name T1749
Test name
Test status
Simulation time 9262530181 ps
CPU time 155.97 seconds
Started Aug 08 08:00:00 PM PDT 24
Finished Aug 08 08:02:36 PM PDT 24
Peak memory 576036 kb
Host smart-420be913-f4fd-4c5b-abbf-081464d066d2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452505269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2452505269
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.3155497165
Short name T2376
Test name
Test status
Simulation time 318109942 ps
CPU time 29.35 seconds
Started Aug 08 07:59:59 PM PDT 24
Finished Aug 08 08:00:28 PM PDT 24
Peak memory 575884 kb
Host smart-b5a58a5f-906b-4d61-8c0f-3060a30ca055
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155497165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del
ays.3155497165
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_same_source.223257800
Short name T2273
Test name
Test status
Simulation time 1872832586 ps
CPU time 56.5 seconds
Started Aug 08 08:00:18 PM PDT 24
Finished Aug 08 08:01:15 PM PDT 24
Peak memory 575884 kb
Host smart-06e605f4-3db6-4014-92c5-85ea0fccf3c5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223257800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.223257800
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke.2891054277
Short name T1795
Test name
Test status
Simulation time 41603415 ps
CPU time 6.42 seconds
Started Aug 08 07:59:57 PM PDT 24
Finished Aug 08 08:00:04 PM PDT 24
Peak memory 573816 kb
Host smart-ceba00b1-5369-4680-bdb3-4ae1895bacfb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891054277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2891054277
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.3421409778
Short name T1408
Test name
Test status
Simulation time 9264928924 ps
CPU time 102.35 seconds
Started Aug 08 07:59:59 PM PDT 24
Finished Aug 08 08:01:42 PM PDT 24
Peak memory 574584 kb
Host smart-7ea08b91-fa35-4023-b425-f333f1294705
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421409778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3421409778
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.3692503384
Short name T2603
Test name
Test status
Simulation time 6838359832 ps
CPU time 118.26 seconds
Started Aug 08 08:00:00 PM PDT 24
Finished Aug 08 08:01:58 PM PDT 24
Peak memory 573812 kb
Host smart-13681899-64a7-4eef-b8e4-1e4324e14670
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692503384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3692503384
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.1999181367
Short name T2283
Test name
Test status
Simulation time 47322634 ps
CPU time 6.52 seconds
Started Aug 08 08:00:00 PM PDT 24
Finished Aug 08 08:00:06 PM PDT 24
Peak memory 574504 kb
Host smart-5b859356-35f8-4e31-aa6f-f479fe50e506
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999181367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay
s.1999181367
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all.1639991560
Short name T1806
Test name
Test status
Simulation time 7187257324 ps
CPU time 212.32 seconds
Started Aug 08 08:00:19 PM PDT 24
Finished Aug 08 08:03:51 PM PDT 24
Peak memory 575960 kb
Host smart-9e28b88d-6fd9-4a58-b248-ffbe33d99013
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639991560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1639991560
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.3835566858
Short name T1708
Test name
Test status
Simulation time 4608777444 ps
CPU time 334.01 seconds
Started Aug 08 08:00:20 PM PDT 24
Finished Aug 08 08:05:54 PM PDT 24
Peak memory 576732 kb
Host smart-bc823000-77cc-4c66-bc7b-e2822edfc8d9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835566858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3835566858
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.1038487858
Short name T2679
Test name
Test status
Simulation time 3813038209 ps
CPU time 430.02 seconds
Started Aug 08 08:00:13 PM PDT 24
Finished Aug 08 08:07:23 PM PDT 24
Peak memory 576724 kb
Host smart-2dd7dafe-ad31-4caf-8711-696043ce79e9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038487858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all
_with_rand_reset.1038487858
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.4024861323
Short name T2778
Test name
Test status
Simulation time 5822774619 ps
CPU time 364.66 seconds
Started Aug 08 08:00:17 PM PDT 24
Finished Aug 08 08:06:21 PM PDT 24
Peak memory 576776 kb
Host smart-ad2b76d4-148a-4da7-90c7-e5ad457c1a11
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024861323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al
l_with_reset_error.4024861323
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.3621043043
Short name T1422
Test name
Test status
Simulation time 28397913 ps
CPU time 6.27 seconds
Started Aug 08 08:00:13 PM PDT 24
Finished Aug 08 08:00:20 PM PDT 24
Peak memory 574528 kb
Host smart-4d8c91bc-4203-4182-abf4-f78a98319f64
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621043043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3621043043
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.2138309022
Short name T2906
Test name
Test status
Simulation time 9664564389 ps
CPU time 1053.94 seconds
Started Aug 08 07:50:31 PM PDT 24
Finished Aug 08 08:08:05 PM PDT 24
Peak memory 646576 kb
Host smart-8a3ae707-46ea-4d9c-a4c5-83cf669f4da6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138309022 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.2138309022
Directory /workspace/5.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.chip_csr_rw.2311073918
Short name T1960
Test name
Test status
Simulation time 4607589758 ps
CPU time 258.45 seconds
Started Aug 08 07:50:33 PM PDT 24
Finished Aug 08 07:54:51 PM PDT 24
Peak memory 598260 kb
Host smart-d0bc6116-bc15-48df-96a6-fc1e93ca24d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311073918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.2311073918
Directory /workspace/5.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.1555541732
Short name T413
Test name
Test status
Simulation time 15993070091 ps
CPU time 1929.96 seconds
Started Aug 08 07:50:22 PM PDT 24
Finished Aug 08 08:22:33 PM PDT 24
Peak memory 593316 kb
Host smart-573c6c74-bb81-405b-b47f-925d1b7b0c28
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555541732 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.1555541732
Directory /workspace/5.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.chip_tl_errors.1946432662
Short name T530
Test name
Test status
Simulation time 4457358429 ps
CPU time 392.16 seconds
Started Aug 08 07:50:25 PM PDT 24
Finished Aug 08 07:56:57 PM PDT 24
Peak memory 598668 kb
Host smart-04b63625-ac57-4f6f-9085-7c4f4e46c52a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946432662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.1946432662
Directory /workspace/5.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_access_same_device.299293359
Short name T2414
Test name
Test status
Simulation time 2281115210 ps
CPU time 92.8 seconds
Started Aug 08 07:50:26 PM PDT 24
Finished Aug 08 07:51:59 PM PDT 24
Peak memory 575908 kb
Host smart-2ed5fdc0-cac0-4ef8-964f-81ff5e8eedb3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299293359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.299293359
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.902196725
Short name T2843
Test name
Test status
Simulation time 131738491913 ps
CPU time 2387.08 seconds
Started Aug 08 07:50:27 PM PDT 24
Finished Aug 08 08:30:15 PM PDT 24
Peak memory 575908 kb
Host smart-b24b0f6e-952c-492c-80d0-9ed5ab82d015
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902196725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_de
vice_slow_rsp.902196725
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1756789150
Short name T2842
Test name
Test status
Simulation time 277063959 ps
CPU time 30.8 seconds
Started Aug 08 07:50:32 PM PDT 24
Finished Aug 08 07:51:03 PM PDT 24
Peak memory 575960 kb
Host smart-112ca937-3693-477a-b455-455932410d0d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756789150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr
.1756789150
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_error_random.3425292103
Short name T1460
Test name
Test status
Simulation time 952307558 ps
CPU time 36.27 seconds
Started Aug 08 07:50:26 PM PDT 24
Finished Aug 08 07:51:02 PM PDT 24
Peak memory 575840 kb
Host smart-8d6cd8cc-b2f1-4202-8c17-4abd357511dc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425292103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3425292103
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random.2306359303
Short name T1693
Test name
Test status
Simulation time 421485140 ps
CPU time 38.31 seconds
Started Aug 08 07:50:29 PM PDT 24
Finished Aug 08 07:51:07 PM PDT 24
Peak memory 575816 kb
Host smart-dff9dca4-f0b5-4ae5-a9b1-1b3a1afcb650
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306359303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.2306359303
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.72932528
Short name T2481
Test name
Test status
Simulation time 36377216617 ps
CPU time 396.98 seconds
Started Aug 08 07:50:24 PM PDT 24
Finished Aug 08 07:57:01 PM PDT 24
Peak memory 575792 kb
Host smart-b3c45899-8868-4a18-966c-1438c7c4369c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72932528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.72932528
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.1347052699
Short name T2432
Test name
Test status
Simulation time 35719132132 ps
CPU time 529.94 seconds
Started Aug 08 07:50:29 PM PDT 24
Finished Aug 08 07:59:19 PM PDT 24
Peak memory 576728 kb
Host smart-62e4de01-1257-464c-a3bf-106362e6cdf9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347052699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1347052699
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.2998827682
Short name T2775
Test name
Test status
Simulation time 396737444 ps
CPU time 37.06 seconds
Started Aug 08 07:50:27 PM PDT 24
Finished Aug 08 07:51:04 PM PDT 24
Peak memory 575696 kb
Host smart-fd34b8dd-cb40-4671-83f3-16f5b3167950
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998827682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela
ys.2998827682
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_same_source.3048855458
Short name T2145
Test name
Test status
Simulation time 499831597 ps
CPU time 36.16 seconds
Started Aug 08 07:50:23 PM PDT 24
Finished Aug 08 07:50:59 PM PDT 24
Peak memory 575860 kb
Host smart-0ff2b9c4-684a-4179-b84d-66a0cea80876
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048855458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3048855458
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke.2021442443
Short name T1868
Test name
Test status
Simulation time 57184762 ps
CPU time 7.02 seconds
Started Aug 08 07:50:26 PM PDT 24
Finished Aug 08 07:50:33 PM PDT 24
Peak memory 574444 kb
Host smart-dfc22b98-370f-42a9-a1b5-38adf40818d9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021442443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2021442443
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.3721895250
Short name T2146
Test name
Test status
Simulation time 10118770972 ps
CPU time 109.61 seconds
Started Aug 08 07:50:25 PM PDT 24
Finished Aug 08 07:52:15 PM PDT 24
Peak memory 573888 kb
Host smart-a1536ee0-275a-471e-8e77-ae8462eb827e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721895250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3721895250
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1618534918
Short name T1800
Test name
Test status
Simulation time 5359017239 ps
CPU time 88.9 seconds
Started Aug 08 07:50:24 PM PDT 24
Finished Aug 08 07:51:53 PM PDT 24
Peak memory 574620 kb
Host smart-2c3510ab-7a56-4651-a949-74b0336e27f8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618534918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1618534918
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.2337425162
Short name T1357
Test name
Test status
Simulation time 46121581 ps
CPU time 5.84 seconds
Started Aug 08 07:50:25 PM PDT 24
Finished Aug 08 07:50:31 PM PDT 24
Peak memory 574440 kb
Host smart-b1a95f9d-7329-4c0b-ade5-203e89954009
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337425162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays
.2337425162
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all.3674594444
Short name T2190
Test name
Test status
Simulation time 1541500430 ps
CPU time 42.05 seconds
Started Aug 08 07:50:33 PM PDT 24
Finished Aug 08 07:51:15 PM PDT 24
Peak memory 575900 kb
Host smart-11d61750-a7ca-4835-89d2-44d4de52d0d7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674594444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3674594444
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.1537667280
Short name T2529
Test name
Test status
Simulation time 7042162032 ps
CPU time 282.46 seconds
Started Aug 08 07:50:31 PM PDT 24
Finished Aug 08 07:55:14 PM PDT 24
Peak memory 576148 kb
Host smart-0f619276-1299-4436-b909-0ea7f2da9a79
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537667280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1537667280
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.4198278764
Short name T2708
Test name
Test status
Simulation time 1077971329 ps
CPU time 142.27 seconds
Started Aug 08 07:50:33 PM PDT 24
Finished Aug 08 07:52:55 PM PDT 24
Peak memory 576680 kb
Host smart-40fb7ab6-d983-4b70-bf27-824ba9bd0b06
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198278764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_
with_rand_reset.4198278764
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.417546236
Short name T2323
Test name
Test status
Simulation time 823851384 ps
CPU time 105.53 seconds
Started Aug 08 07:50:34 PM PDT 24
Finished Aug 08 07:52:20 PM PDT 24
Peak memory 576696 kb
Host smart-e457f839-2e1b-48d6-86bb-87d62cde58ac
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417546236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_
with_reset_error.417546236
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.456945418
Short name T1713
Test name
Test status
Simulation time 92173803 ps
CPU time 11.27 seconds
Started Aug 08 07:50:22 PM PDT 24
Finished Aug 08 07:50:33 PM PDT 24
Peak memory 575972 kb
Host smart-8bf0a4f2-524c-4dfa-b508-fdeaaa56d9f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456945418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.456945418
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_access_same_device.1262789157
Short name T1756
Test name
Test status
Simulation time 3128425278 ps
CPU time 136.34 seconds
Started Aug 08 08:00:14 PM PDT 24
Finished Aug 08 08:02:31 PM PDT 24
Peak memory 575944 kb
Host smart-fe8beb67-b044-4738-b0aa-f17e25e61a4f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262789157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device
.1262789157
Directory /workspace/50.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1384777408
Short name T2317
Test name
Test status
Simulation time 26911102996 ps
CPU time 468.47 seconds
Started Aug 08 08:00:18 PM PDT 24
Finished Aug 08 08:08:07 PM PDT 24
Peak memory 576652 kb
Host smart-ff055328-f460-41f6-b60f-768f2a46b63c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384777408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_
device_slow_rsp.1384777408
Directory /workspace/50.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.1485505718
Short name T1940
Test name
Test status
Simulation time 280720020 ps
CPU time 30.4 seconds
Started Aug 08 08:00:16 PM PDT 24
Finished Aug 08 08:00:47 PM PDT 24
Peak memory 575956 kb
Host smart-ef1a084f-17f3-43ff-b295-e6b36ed05e82
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485505718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add
r.1485505718
Directory /workspace/50.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_error_random.3447150221
Short name T2001
Test name
Test status
Simulation time 2026460261 ps
CPU time 70.16 seconds
Started Aug 08 08:00:21 PM PDT 24
Finished Aug 08 08:01:31 PM PDT 24
Peak memory 575804 kb
Host smart-5be85320-c637-4fbd-adb3-ff32b1d260bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447150221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.3447150221
Directory /workspace/50.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random.105463804
Short name T2137
Test name
Test status
Simulation time 593828405 ps
CPU time 51.11 seconds
Started Aug 08 08:00:18 PM PDT 24
Finished Aug 08 08:01:10 PM PDT 24
Peak memory 575836 kb
Host smart-fa7ac849-e109-40d5-85ed-94e5deb3e102
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105463804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.105463804
Directory /workspace/50.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.1202034360
Short name T2096
Test name
Test status
Simulation time 46234014902 ps
CPU time 506.66 seconds
Started Aug 08 08:00:20 PM PDT 24
Finished Aug 08 08:08:47 PM PDT 24
Peak memory 576672 kb
Host smart-bb08a77d-6248-455e-badf-95e9a2f91388
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202034360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.1202034360
Directory /workspace/50.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.40858238
Short name T2859
Test name
Test status
Simulation time 20505348779 ps
CPU time 352.36 seconds
Started Aug 08 08:00:19 PM PDT 24
Finished Aug 08 08:06:11 PM PDT 24
Peak memory 576000 kb
Host smart-684a1ccf-735c-4a8b-9db0-b61ee5b58318
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40858238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.40858238
Directory /workspace/50.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.129292457
Short name T1737
Test name
Test status
Simulation time 373079032 ps
CPU time 35.3 seconds
Started Aug 08 08:00:15 PM PDT 24
Finished Aug 08 08:00:51 PM PDT 24
Peak memory 575872 kb
Host smart-cd4370a0-15ee-469b-8e1a-d2e94973e957
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129292457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_dela
ys.129292457
Directory /workspace/50.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_same_source.2308777726
Short name T2293
Test name
Test status
Simulation time 449899664 ps
CPU time 28.99 seconds
Started Aug 08 08:00:14 PM PDT 24
Finished Aug 08 08:00:43 PM PDT 24
Peak memory 575808 kb
Host smart-4a5bbd94-92d1-49a5-bdb9-f7609480b13f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308777726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.2308777726
Directory /workspace/50.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke.2693613466
Short name T2719
Test name
Test status
Simulation time 182456784 ps
CPU time 8.39 seconds
Started Aug 08 08:00:19 PM PDT 24
Finished Aug 08 08:00:27 PM PDT 24
Peak memory 573824 kb
Host smart-c59993bc-1db0-40c3-91aa-aef226c77e53
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693613466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.2693613466
Directory /workspace/50.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.750282848
Short name T2563
Test name
Test status
Simulation time 7806273883 ps
CPU time 81.63 seconds
Started Aug 08 08:00:17 PM PDT 24
Finished Aug 08 08:01:39 PM PDT 24
Peak memory 573924 kb
Host smart-d5daa499-4d08-4a72-aa48-0de36b966a25
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750282848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.750282848
Directory /workspace/50.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.2327336530
Short name T2748
Test name
Test status
Simulation time 5030718495 ps
CPU time 80.7 seconds
Started Aug 08 08:00:20 PM PDT 24
Finished Aug 08 08:01:41 PM PDT 24
Peak memory 574540 kb
Host smart-e4afb1db-bb3c-400b-a0b6-412e3bdd5ae7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327336530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.2327336530
Directory /workspace/50.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.3593523693
Short name T636
Test name
Test status
Simulation time 50781784 ps
CPU time 6.66 seconds
Started Aug 08 08:00:21 PM PDT 24
Finished Aug 08 08:00:27 PM PDT 24
Peak memory 573972 kb
Host smart-0311bb08-ea0d-47e6-b807-7afc3faec508
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593523693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay
s.3593523693
Directory /workspace/50.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all.124125558
Short name T2752
Test name
Test status
Simulation time 5578197622 ps
CPU time 186.09 seconds
Started Aug 08 08:00:20 PM PDT 24
Finished Aug 08 08:03:27 PM PDT 24
Peak memory 576224 kb
Host smart-bb69347e-4523-4190-9326-52c519fab47f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124125558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.124125558
Directory /workspace/50.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.322310685
Short name T2507
Test name
Test status
Simulation time 14433985868 ps
CPU time 547.32 seconds
Started Aug 08 08:00:21 PM PDT 24
Finished Aug 08 08:09:29 PM PDT 24
Peak memory 576960 kb
Host smart-8c848fdf-236b-4846-abb4-17a6da9b90e7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322310685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.322310685
Directory /workspace/50.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3341569694
Short name T845
Test name
Test status
Simulation time 14889898033 ps
CPU time 728.5 seconds
Started Aug 08 08:00:17 PM PDT 24
Finished Aug 08 08:12:26 PM PDT 24
Peak memory 576016 kb
Host smart-eabc176c-df80-46af-a72d-624679ae1e2a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341569694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all
_with_rand_reset.3341569694
Directory /workspace/50.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.4043435799
Short name T1825
Test name
Test status
Simulation time 1439861439 ps
CPU time 199.4 seconds
Started Aug 08 08:00:18 PM PDT 24
Finished Aug 08 08:03:38 PM PDT 24
Peak memory 575888 kb
Host smart-4ce20880-c9e6-44fd-9d91-ab0424a9e1dc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043435799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al
l_with_reset_error.4043435799
Directory /workspace/50.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.280789949
Short name T1507
Test name
Test status
Simulation time 35921902 ps
CPU time 6.84 seconds
Started Aug 08 08:00:19 PM PDT 24
Finished Aug 08 08:00:26 PM PDT 24
Peak memory 573932 kb
Host smart-16c16f1d-6380-4abe-97c2-3de6a28344e0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280789949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.280789949
Directory /workspace/50.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_access_same_device.3919680183
Short name T500
Test name
Test status
Simulation time 2924347150 ps
CPU time 110.04 seconds
Started Aug 08 08:00:20 PM PDT 24
Finished Aug 08 08:02:10 PM PDT 24
Peak memory 575772 kb
Host smart-77f5d0a1-4cd2-417f-9b26-8ab4bc540589
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919680183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device
.3919680183
Directory /workspace/51.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2026212551
Short name T2583
Test name
Test status
Simulation time 106519299945 ps
CPU time 1911.37 seconds
Started Aug 08 08:00:19 PM PDT 24
Finished Aug 08 08:32:10 PM PDT 24
Peak memory 576048 kb
Host smart-eeffe13f-c43e-4207-bcb2-d7886a2e2105
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026212551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_
device_slow_rsp.2026212551
Directory /workspace/51.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.1899111568
Short name T2388
Test name
Test status
Simulation time 1024568208 ps
CPU time 40.22 seconds
Started Aug 08 08:00:17 PM PDT 24
Finished Aug 08 08:00:58 PM PDT 24
Peak memory 575780 kb
Host smart-89d02598-5966-4f0e-b749-2a5452730564
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899111568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add
r.1899111568
Directory /workspace/51.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_error_random.2117963600
Short name T2005
Test name
Test status
Simulation time 1389550265 ps
CPU time 49.26 seconds
Started Aug 08 08:00:17 PM PDT 24
Finished Aug 08 08:01:06 PM PDT 24
Peak memory 575872 kb
Host smart-6c325584-6367-48f1-8d4b-c8bd96b0cf12
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117963600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.2117963600
Directory /workspace/51.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random.1460630953
Short name T2206
Test name
Test status
Simulation time 1784332570 ps
CPU time 65.39 seconds
Started Aug 08 08:00:12 PM PDT 24
Finished Aug 08 08:01:18 PM PDT 24
Peak memory 575920 kb
Host smart-f5a4b81e-8b2c-46d2-94a8-ff305dd31acd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460630953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.1460630953
Directory /workspace/51.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.2644615664
Short name T1905
Test name
Test status
Simulation time 50324114983 ps
CPU time 534 seconds
Started Aug 08 08:00:17 PM PDT 24
Finished Aug 08 08:09:11 PM PDT 24
Peak memory 576728 kb
Host smart-2287a8f1-3e4c-40fb-be87-ae64acc13655
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644615664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.2644615664
Directory /workspace/51.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.1228617906
Short name T2440
Test name
Test status
Simulation time 28609787801 ps
CPU time 459.48 seconds
Started Aug 08 08:00:12 PM PDT 24
Finished Aug 08 08:07:51 PM PDT 24
Peak memory 575908 kb
Host smart-f2fb0ac4-1d43-4ef0-a7aa-be042ba6ba7f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228617906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.1228617906
Directory /workspace/51.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.3251269414
Short name T1861
Test name
Test status
Simulation time 433631634 ps
CPU time 41.41 seconds
Started Aug 08 08:00:13 PM PDT 24
Finished Aug 08 08:00:54 PM PDT 24
Peak memory 575836 kb
Host smart-13f3dd15-d84b-4c5d-9562-6d4d6c7e6fec
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251269414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del
ays.3251269414
Directory /workspace/51.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_same_source.4011121744
Short name T2691
Test name
Test status
Simulation time 1105218097 ps
CPU time 35.43 seconds
Started Aug 08 08:00:18 PM PDT 24
Finished Aug 08 08:00:54 PM PDT 24
Peak memory 575784 kb
Host smart-6fa9da17-3d9c-47d7-939b-7b6cb55f23fc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011121744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.4011121744
Directory /workspace/51.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke.106779659
Short name T1431
Test name
Test status
Simulation time 210972058 ps
CPU time 9.02 seconds
Started Aug 08 08:00:12 PM PDT 24
Finished Aug 08 08:00:21 PM PDT 24
Peak memory 574500 kb
Host smart-36f8187d-645c-4128-898a-aec914ae2c4b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106779659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.106779659
Directory /workspace/51.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.3990003793
Short name T2017
Test name
Test status
Simulation time 5049415928 ps
CPU time 50.7 seconds
Started Aug 08 08:00:11 PM PDT 24
Finished Aug 08 08:01:02 PM PDT 24
Peak memory 573864 kb
Host smart-2fa4ca67-2dc1-440c-a286-0447e78150d4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990003793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.3990003793
Directory /workspace/51.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.2659421194
Short name T1801
Test name
Test status
Simulation time 4483005893 ps
CPU time 73.94 seconds
Started Aug 08 08:00:12 PM PDT 24
Finished Aug 08 08:01:26 PM PDT 24
Peak memory 573900 kb
Host smart-a801112d-1a89-4525-8d54-8aa4362a3735
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659421194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.2659421194
Directory /workspace/51.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.3138734955
Short name T2522
Test name
Test status
Simulation time 53814608 ps
CPU time 5.86 seconds
Started Aug 08 08:00:19 PM PDT 24
Finished Aug 08 08:00:24 PM PDT 24
Peak memory 573744 kb
Host smart-bb49456a-5156-4a30-9ddf-c2a0a2ea0dce
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138734955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay
s.3138734955
Directory /workspace/51.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all.1802596774
Short name T445
Test name
Test status
Simulation time 9118790028 ps
CPU time 348.12 seconds
Started Aug 08 08:00:13 PM PDT 24
Finished Aug 08 08:06:01 PM PDT 24
Peak memory 576160 kb
Host smart-03d08ed1-05b2-4247-8c48-69f2ad1605b9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802596774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.1802596774
Directory /workspace/51.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.339936988
Short name T2121
Test name
Test status
Simulation time 5741350664 ps
CPU time 195.55 seconds
Started Aug 08 08:00:12 PM PDT 24
Finished Aug 08 08:03:28 PM PDT 24
Peak memory 576108 kb
Host smart-86ce6dfa-36ee-4941-aa0d-c93325c4b6e3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339936988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.339936988
Directory /workspace/51.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.827706411
Short name T2039
Test name
Test status
Simulation time 1945295631 ps
CPU time 335.92 seconds
Started Aug 08 08:00:17 PM PDT 24
Finished Aug 08 08:05:53 PM PDT 24
Peak memory 575900 kb
Host smart-1b9e80a6-9815-4302-abc7-1484e6f5120b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827706411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_
with_rand_reset.827706411
Directory /workspace/51.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.623297285
Short name T833
Test name
Test status
Simulation time 2013045806 ps
CPU time 263.38 seconds
Started Aug 08 08:00:19 PM PDT 24
Finished Aug 08 08:04:42 PM PDT 24
Peak memory 575872 kb
Host smart-39b674a4-ad45-4e20-ba32-f68b9c86bee9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623297285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all
_with_reset_error.623297285
Directory /workspace/51.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.255991747
Short name T1786
Test name
Test status
Simulation time 1247246485 ps
CPU time 49.11 seconds
Started Aug 08 08:00:17 PM PDT 24
Finished Aug 08 08:01:06 PM PDT 24
Peak memory 575964 kb
Host smart-5f6b40dc-0a24-4399-9ab1-e589ae181f63
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255991747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.255991747
Directory /workspace/51.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_access_same_device.3468086803
Short name T819
Test name
Test status
Simulation time 60800052 ps
CPU time 6.79 seconds
Started Aug 08 08:00:13 PM PDT 24
Finished Aug 08 08:00:19 PM PDT 24
Peak memory 573808 kb
Host smart-7ea94721-e017-428f-8704-ad94a2c30b5c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468086803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device
.3468086803
Directory /workspace/52.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.731969491
Short name T550
Test name
Test status
Simulation time 54944981657 ps
CPU time 967.57 seconds
Started Aug 08 08:00:22 PM PDT 24
Finished Aug 08 08:16:30 PM PDT 24
Peak memory 575916 kb
Host smart-8094f8c4-54ad-4bf2-9549-95a26a87c64b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731969491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_d
evice_slow_rsp.731969491
Directory /workspace/52.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.2853880243
Short name T1796
Test name
Test status
Simulation time 1158449012 ps
CPU time 40.5 seconds
Started Aug 08 08:00:18 PM PDT 24
Finished Aug 08 08:00:58 PM PDT 24
Peak memory 575876 kb
Host smart-e56d14dc-a603-4c0c-a25b-24808ab086e9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853880243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add
r.2853880243
Directory /workspace/52.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_error_random.2542436409
Short name T1665
Test name
Test status
Simulation time 1964570173 ps
CPU time 68.21 seconds
Started Aug 08 08:00:12 PM PDT 24
Finished Aug 08 08:01:21 PM PDT 24
Peak memory 575836 kb
Host smart-9da859a0-ca92-4fe7-9f42-3d404382b907
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542436409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.2542436409
Directory /workspace/52.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random.1894311160
Short name T2361
Test name
Test status
Simulation time 167814594 ps
CPU time 9.25 seconds
Started Aug 08 08:00:13 PM PDT 24
Finished Aug 08 08:00:22 PM PDT 24
Peak memory 573860 kb
Host smart-25bbf126-35e7-4c5c-b5b1-1041c71d9f76
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894311160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.1894311160
Directory /workspace/52.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.3064283305
Short name T2077
Test name
Test status
Simulation time 82459228614 ps
CPU time 861.1 seconds
Started Aug 08 08:00:18 PM PDT 24
Finished Aug 08 08:14:40 PM PDT 24
Peak memory 576720 kb
Host smart-7dbf2a2e-6f83-4b35-ae5c-1b2084be03c3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064283305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.3064283305
Directory /workspace/52.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.1237890749
Short name T449
Test name
Test status
Simulation time 49884709015 ps
CPU time 858.13 seconds
Started Aug 08 08:00:13 PM PDT 24
Finished Aug 08 08:14:31 PM PDT 24
Peak memory 576700 kb
Host smart-6dd7921a-7785-490f-a236-b7690d764109
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237890749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.1237890749
Directory /workspace/52.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.2878435383
Short name T2289
Test name
Test status
Simulation time 144475270 ps
CPU time 15.47 seconds
Started Aug 08 08:00:17 PM PDT 24
Finished Aug 08 08:00:32 PM PDT 24
Peak memory 575748 kb
Host smart-454a9634-9a72-4a20-82c0-7033499ecc2d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878435383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del
ays.2878435383
Directory /workspace/52.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_same_source.2451012353
Short name T1500
Test name
Test status
Simulation time 2217431874 ps
CPU time 68.41 seconds
Started Aug 08 08:00:19 PM PDT 24
Finished Aug 08 08:01:28 PM PDT 24
Peak memory 575940 kb
Host smart-f2e7bfea-fa7c-4f67-b724-738ce6bc9fd9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451012353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.2451012353
Directory /workspace/52.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke.698128753
Short name T1358
Test name
Test status
Simulation time 166540204 ps
CPU time 8.49 seconds
Started Aug 08 08:00:13 PM PDT 24
Finished Aug 08 08:00:22 PM PDT 24
Peak memory 573756 kb
Host smart-8759989a-2fcb-4fc7-ac6b-50767b832798
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698128753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.698128753
Directory /workspace/52.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.2257738364
Short name T2783
Test name
Test status
Simulation time 6731125043 ps
CPU time 70.55 seconds
Started Aug 08 08:00:18 PM PDT 24
Finished Aug 08 08:01:29 PM PDT 24
Peak memory 573920 kb
Host smart-296b9692-45e6-4376-9a7a-300838184d35
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257738364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.2257738364
Directory /workspace/52.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.129454634
Short name T2135
Test name
Test status
Simulation time 6149371644 ps
CPU time 104.38 seconds
Started Aug 08 08:00:15 PM PDT 24
Finished Aug 08 08:02:00 PM PDT 24
Peak memory 573860 kb
Host smart-9bb1a7f9-1c54-4d77-a5be-db680fbdad01
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129454634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.129454634
Directory /workspace/52.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.1338017366
Short name T1689
Test name
Test status
Simulation time 41524234 ps
CPU time 6.3 seconds
Started Aug 08 08:00:18 PM PDT 24
Finished Aug 08 08:00:24 PM PDT 24
Peak memory 574468 kb
Host smart-3daa367a-4d61-4ff5-a908-7379f7820c8c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338017366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay
s.1338017366
Directory /workspace/52.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all.4011348978
Short name T2435
Test name
Test status
Simulation time 2122365177 ps
CPU time 88.99 seconds
Started Aug 08 08:00:21 PM PDT 24
Finished Aug 08 08:01:50 PM PDT 24
Peak memory 576032 kb
Host smart-aa3ee536-55d4-4704-87d0-61e14006d2b9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011348978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.4011348978
Directory /workspace/52.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.771304890
Short name T820
Test name
Test status
Simulation time 2149073360 ps
CPU time 186.41 seconds
Started Aug 08 08:00:28 PM PDT 24
Finished Aug 08 08:03:34 PM PDT 24
Peak memory 576112 kb
Host smart-aa473811-50ec-425d-b457-38233e0f7f8a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771304890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.771304890
Directory /workspace/52.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.3563870862
Short name T435
Test name
Test status
Simulation time 1640965252 ps
CPU time 176.87 seconds
Started Aug 08 08:00:21 PM PDT 24
Finished Aug 08 08:03:18 PM PDT 24
Peak memory 575788 kb
Host smart-c057bfe3-26df-4e6d-860d-de53c85b2258
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563870862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all
_with_rand_reset.3563870862
Directory /workspace/52.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.662906615
Short name T2514
Test name
Test status
Simulation time 8150950383 ps
CPU time 375.85 seconds
Started Aug 08 08:00:28 PM PDT 24
Finished Aug 08 08:06:44 PM PDT 24
Peak memory 575960 kb
Host smart-d3067fdc-4791-40f1-813a-59bb57af2fc7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662906615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all
_with_reset_error.662906615
Directory /workspace/52.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.1163362548
Short name T2571
Test name
Test status
Simulation time 593672685 ps
CPU time 23.33 seconds
Started Aug 08 08:00:17 PM PDT 24
Finished Aug 08 08:00:40 PM PDT 24
Peak memory 575896 kb
Host smart-188e9164-4df2-4014-804c-326a4263e8a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163362548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.1163362548
Directory /workspace/52.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_access_same_device.683632283
Short name T1866
Test name
Test status
Simulation time 474286194 ps
CPU time 18.94 seconds
Started Aug 08 08:00:31 PM PDT 24
Finished Aug 08 08:00:50 PM PDT 24
Peak memory 575848 kb
Host smart-86c422e8-32e2-4faa-ba77-fe11a2155226
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683632283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device.
683632283
Directory /workspace/53.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2627135928
Short name T1797
Test name
Test status
Simulation time 716367489 ps
CPU time 27.73 seconds
Started Aug 08 08:00:28 PM PDT 24
Finished Aug 08 08:00:56 PM PDT 24
Peak memory 575836 kb
Host smart-a69b6ec7-faf9-487b-920b-4a0a6dd35843
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627135928 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add
r.2627135928
Directory /workspace/53.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_error_random.3695464994
Short name T2328
Test name
Test status
Simulation time 239573347 ps
CPU time 21.31 seconds
Started Aug 08 08:00:29 PM PDT 24
Finished Aug 08 08:00:51 PM PDT 24
Peak memory 575884 kb
Host smart-fd03d70c-e6e7-45f0-8b78-c2d895ea1604
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695464994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.3695464994
Directory /workspace/53.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random.1522700688
Short name T1875
Test name
Test status
Simulation time 1087890988 ps
CPU time 36.48 seconds
Started Aug 08 08:00:30 PM PDT 24
Finished Aug 08 08:01:06 PM PDT 24
Peak memory 575868 kb
Host smart-b890bc67-07de-4cd1-9d0d-37863c87a630
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522700688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.1522700688
Directory /workspace/53.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.3481241297
Short name T1752
Test name
Test status
Simulation time 56448080312 ps
CPU time 640.12 seconds
Started Aug 08 08:00:29 PM PDT 24
Finished Aug 08 08:11:09 PM PDT 24
Peak memory 575904 kb
Host smart-57e33efe-d7c2-4e73-ada5-981b522e720f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481241297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.3481241297
Directory /workspace/53.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.3306470250
Short name T2482
Test name
Test status
Simulation time 32931784769 ps
CPU time 488.09 seconds
Started Aug 08 08:00:28 PM PDT 24
Finished Aug 08 08:08:36 PM PDT 24
Peak memory 575964 kb
Host smart-43d5ff52-6bed-4f10-ab40-6d4d18876073
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306470250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.3306470250
Directory /workspace/53.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.3236065903
Short name T2219
Test name
Test status
Simulation time 32666771 ps
CPU time 5.75 seconds
Started Aug 08 08:00:26 PM PDT 24
Finished Aug 08 08:00:32 PM PDT 24
Peak memory 574516 kb
Host smart-de4ef028-5baf-4d74-b586-08ae96c23b2d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236065903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del
ays.3236065903
Directory /workspace/53.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_same_source.2676681371
Short name T583
Test name
Test status
Simulation time 510413628 ps
CPU time 36.55 seconds
Started Aug 08 08:00:29 PM PDT 24
Finished Aug 08 08:01:06 PM PDT 24
Peak memory 575772 kb
Host smart-6adc95cc-c28c-4a55-b021-4d05fee02be6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676681371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.2676681371
Directory /workspace/53.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke.1409018761
Short name T1569
Test name
Test status
Simulation time 37482417 ps
CPU time 5.65 seconds
Started Aug 08 08:00:27 PM PDT 24
Finished Aug 08 08:00:33 PM PDT 24
Peak memory 573788 kb
Host smart-d8706edd-5d55-4322-add8-b0ecc5b3a3eb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409018761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.1409018761
Directory /workspace/53.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.944353000
Short name T2722
Test name
Test status
Simulation time 6121982439 ps
CPU time 63.23 seconds
Started Aug 08 08:00:27 PM PDT 24
Finished Aug 08 08:01:30 PM PDT 24
Peak memory 573860 kb
Host smart-877fe73f-c080-49d7-b5de-6dddb3056588
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944353000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.944353000
Directory /workspace/53.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1096733143
Short name T2656
Test name
Test status
Simulation time 3063747233 ps
CPU time 51.26 seconds
Started Aug 08 08:00:27 PM PDT 24
Finished Aug 08 08:01:18 PM PDT 24
Peak memory 574540 kb
Host smart-5775c1db-0c6b-4bb1-ab65-6d85273df306
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096733143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.1096733143
Directory /workspace/53.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.228566468
Short name T2304
Test name
Test status
Simulation time 40998718 ps
CPU time 6.08 seconds
Started Aug 08 08:00:28 PM PDT 24
Finished Aug 08 08:00:34 PM PDT 24
Peak memory 574428 kb
Host smart-3325a1d1-3cde-49fc-9999-b638d00b1753
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228566468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delays
.228566468
Directory /workspace/53.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all.763921059
Short name T2539
Test name
Test status
Simulation time 10605061915 ps
CPU time 370.1 seconds
Started Aug 08 08:00:28 PM PDT 24
Finished Aug 08 08:06:38 PM PDT 24
Peak memory 576784 kb
Host smart-911471e7-94a5-4f07-9f19-2764822dda15
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763921059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.763921059
Directory /workspace/53.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.1875923854
Short name T2132
Test name
Test status
Simulation time 10097466919 ps
CPU time 314.7 seconds
Started Aug 08 08:00:39 PM PDT 24
Finished Aug 08 08:05:54 PM PDT 24
Peak memory 575944 kb
Host smart-db5f289f-4b40-4ac3-8710-8a9dbe87dc20
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875923854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.1875923854
Directory /workspace/53.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.3665403853
Short name T2462
Test name
Test status
Simulation time 74323371 ps
CPU time 27.49 seconds
Started Aug 08 08:00:29 PM PDT 24
Finished Aug 08 08:00:56 PM PDT 24
Peak memory 575980 kb
Host smart-fe72bc85-5df9-43ec-9226-204f625e92fc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665403853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all
_with_rand_reset.3665403853
Directory /workspace/53.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.4067283963
Short name T841
Test name
Test status
Simulation time 713458176 ps
CPU time 207.07 seconds
Started Aug 08 08:00:32 PM PDT 24
Finished Aug 08 08:04:00 PM PDT 24
Peak memory 575836 kb
Host smart-95dd5cd6-2665-4125-826d-979a0702ac9c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067283963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al
l_with_reset_error.4067283963
Directory /workspace/53.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.2164506020
Short name T2695
Test name
Test status
Simulation time 1196336907 ps
CPU time 48.47 seconds
Started Aug 08 08:00:39 PM PDT 24
Finished Aug 08 08:01:27 PM PDT 24
Peak memory 575912 kb
Host smart-2b53b970-0610-4a91-8d12-5e818de5ddb3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164506020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.2164506020
Directory /workspace/53.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_access_same_device.586951987
Short name T1991
Test name
Test status
Simulation time 566294467 ps
CPU time 24.16 seconds
Started Aug 08 08:00:38 PM PDT 24
Finished Aug 08 08:01:03 PM PDT 24
Peak memory 575812 kb
Host smart-2c2168b7-7c1f-477d-9993-6258f9474bd2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586951987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device.
586951987
Directory /workspace/54.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.3329108107
Short name T2865
Test name
Test status
Simulation time 122269935503 ps
CPU time 2129.76 seconds
Started Aug 08 08:00:39 PM PDT 24
Finished Aug 08 08:36:09 PM PDT 24
Peak memory 575920 kb
Host smart-9c734493-df54-4132-a0ab-04b6e8b3922e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329108107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_
device_slow_rsp.3329108107
Directory /workspace/54.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.1139050302
Short name T1362
Test name
Test status
Simulation time 601237609 ps
CPU time 20.12 seconds
Started Aug 08 08:00:42 PM PDT 24
Finished Aug 08 08:01:02 PM PDT 24
Peak memory 575928 kb
Host smart-778436cf-2425-4783-afe6-07d771ea2d9a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139050302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add
r.1139050302
Directory /workspace/54.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_error_random.2750906732
Short name T1771
Test name
Test status
Simulation time 1569731186 ps
CPU time 51.39 seconds
Started Aug 08 08:00:40 PM PDT 24
Finished Aug 08 08:01:32 PM PDT 24
Peak memory 575836 kb
Host smart-2ca8edbf-b248-4f55-b336-dbbfcb97a437
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750906732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.2750906732
Directory /workspace/54.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random.2148346527
Short name T1772
Test name
Test status
Simulation time 2057724963 ps
CPU time 74.3 seconds
Started Aug 08 08:00:28 PM PDT 24
Finished Aug 08 08:01:43 PM PDT 24
Peak memory 575888 kb
Host smart-c1d728e0-2d89-4fd6-8f12-7935576b76f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148346527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.2148346527
Directory /workspace/54.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.2661553737
Short name T2671
Test name
Test status
Simulation time 59868884926 ps
CPU time 620.06 seconds
Started Aug 08 08:00:29 PM PDT 24
Finished Aug 08 08:10:49 PM PDT 24
Peak memory 576684 kb
Host smart-d27a20ac-7dda-4c21-b81d-475ba21ad90b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661553737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.2661553737
Directory /workspace/54.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.3185300440
Short name T2473
Test name
Test status
Simulation time 29704816177 ps
CPU time 462.47 seconds
Started Aug 08 08:00:40 PM PDT 24
Finished Aug 08 08:08:22 PM PDT 24
Peak memory 575836 kb
Host smart-8074e587-3968-4bab-a979-78eda22673e5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185300440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.3185300440
Directory /workspace/54.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.2026224889
Short name T2153
Test name
Test status
Simulation time 427996116 ps
CPU time 35.36 seconds
Started Aug 08 08:00:39 PM PDT 24
Finished Aug 08 08:01:15 PM PDT 24
Peak memory 575728 kb
Host smart-eb000186-bc31-4910-9099-fc32b1c52e83
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026224889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del
ays.2026224889
Directory /workspace/54.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_same_source.4014245144
Short name T592
Test name
Test status
Simulation time 294659783 ps
CPU time 10.46 seconds
Started Aug 08 08:00:38 PM PDT 24
Finished Aug 08 08:00:49 PM PDT 24
Peak memory 575656 kb
Host smart-f1bdf9ef-3204-44b7-b5e6-927be7fd5fcd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014245144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.4014245144
Directory /workspace/54.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke.3429375972
Short name T2464
Test name
Test status
Simulation time 145631875 ps
CPU time 7.36 seconds
Started Aug 08 08:00:39 PM PDT 24
Finished Aug 08 08:00:47 PM PDT 24
Peak memory 574476 kb
Host smart-dceb16e6-6be9-4d1b-9557-ed87e928044f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429375972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.3429375972
Directory /workspace/54.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.2013322344
Short name T1725
Test name
Test status
Simulation time 7085680860 ps
CPU time 71.07 seconds
Started Aug 08 08:00:32 PM PDT 24
Finished Aug 08 08:01:44 PM PDT 24
Peak memory 574580 kb
Host smart-9148ef8f-08d5-4204-980c-8add293e8c85
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013322344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.2013322344
Directory /workspace/54.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.130134580
Short name T1453
Test name
Test status
Simulation time 4875336173 ps
CPU time 82.92 seconds
Started Aug 08 08:00:33 PM PDT 24
Finished Aug 08 08:01:56 PM PDT 24
Peak memory 573916 kb
Host smart-7d994bcc-be45-4488-8cfa-2f254f470d2e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130134580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.130134580
Directory /workspace/54.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.2388550519
Short name T1489
Test name
Test status
Simulation time 40959885 ps
CPU time 6.12 seconds
Started Aug 08 08:00:33 PM PDT 24
Finished Aug 08 08:00:40 PM PDT 24
Peak memory 574540 kb
Host smart-5084e4b6-f7f0-4c30-91d8-7cc6d4e2a207
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388550519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay
s.2388550519
Directory /workspace/54.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all.2949785293
Short name T481
Test name
Test status
Simulation time 1384505017 ps
CPU time 115.59 seconds
Started Aug 08 08:00:40 PM PDT 24
Finished Aug 08 08:02:36 PM PDT 24
Peak memory 575996 kb
Host smart-962bb642-e858-4f96-bfc7-0d00f5ad9cd3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949785293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.2949785293
Directory /workspace/54.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.3955193410
Short name T1779
Test name
Test status
Simulation time 9707458428 ps
CPU time 340.35 seconds
Started Aug 08 08:00:40 PM PDT 24
Finished Aug 08 08:06:21 PM PDT 24
Peak memory 576140 kb
Host smart-f842c9e7-2a1f-446d-adad-eb998c322f64
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955193410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.3955193410
Directory /workspace/54.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.1888370913
Short name T1750
Test name
Test status
Simulation time 2160560870 ps
CPU time 286.55 seconds
Started Aug 08 08:00:39 PM PDT 24
Finished Aug 08 08:05:26 PM PDT 24
Peak memory 576024 kb
Host smart-26653538-e418-4298-a477-15c8a0fa134d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888370913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all
_with_rand_reset.1888370913
Directory /workspace/54.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.1755577165
Short name T2081
Test name
Test status
Simulation time 6379581040 ps
CPU time 329.43 seconds
Started Aug 08 08:00:39 PM PDT 24
Finished Aug 08 08:06:08 PM PDT 24
Peak memory 575960 kb
Host smart-61adecbb-cb69-447b-b7cf-29c187718182
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755577165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al
l_with_reset_error.1755577165
Directory /workspace/54.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.2844532319
Short name T2181
Test name
Test status
Simulation time 227591360 ps
CPU time 29.05 seconds
Started Aug 08 08:00:41 PM PDT 24
Finished Aug 08 08:01:10 PM PDT 24
Peak memory 575948 kb
Host smart-d862a995-fcd6-4bf3-8b0f-2e30c7b4dbeb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844532319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.2844532319
Directory /workspace/54.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_access_same_device.1755305587
Short name T493
Test name
Test status
Simulation time 767233975 ps
CPU time 61.08 seconds
Started Aug 08 08:00:40 PM PDT 24
Finished Aug 08 08:01:41 PM PDT 24
Peak memory 575960 kb
Host smart-bba96e81-b5fc-483a-ad06-13b8c2b5083d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755305587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device
.1755305587
Directory /workspace/55.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.2794046493
Short name T1624
Test name
Test status
Simulation time 418298669 ps
CPU time 17.72 seconds
Started Aug 08 08:00:53 PM PDT 24
Finished Aug 08 08:01:11 PM PDT 24
Peak memory 575732 kb
Host smart-2809a88e-9dfd-49dc-8bb2-a25fb2707b74
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794046493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add
r.2794046493
Directory /workspace/55.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_error_random.177566102
Short name T1554
Test name
Test status
Simulation time 2214076709 ps
CPU time 60.6 seconds
Started Aug 08 08:00:40 PM PDT 24
Finished Aug 08 08:01:41 PM PDT 24
Peak memory 575980 kb
Host smart-ba447e99-d151-4fbc-84ee-90bd264ab2b6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177566102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.177566102
Directory /workspace/55.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random.3633714909
Short name T2318
Test name
Test status
Simulation time 465693523 ps
CPU time 39.49 seconds
Started Aug 08 08:00:45 PM PDT 24
Finished Aug 08 08:01:25 PM PDT 24
Peak memory 575860 kb
Host smart-a87b9da4-47d6-469f-b367-9813c5a4a9f0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633714909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.3633714909
Directory /workspace/55.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.4143539025
Short name T2086
Test name
Test status
Simulation time 87129616267 ps
CPU time 1013.08 seconds
Started Aug 08 08:00:41 PM PDT 24
Finished Aug 08 08:17:34 PM PDT 24
Peak memory 575984 kb
Host smart-77d05985-1e69-42f4-8263-1baf764e61b6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143539025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.4143539025
Directory /workspace/55.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.4068202826
Short name T1703
Test name
Test status
Simulation time 15186219890 ps
CPU time 265.77 seconds
Started Aug 08 08:00:41 PM PDT 24
Finished Aug 08 08:05:07 PM PDT 24
Peak memory 575848 kb
Host smart-9ff73c59-5f82-4f43-b887-450b933a9817
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068202826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.4068202826
Directory /workspace/55.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.135052463
Short name T2276
Test name
Test status
Simulation time 467854346 ps
CPU time 35.66 seconds
Started Aug 08 08:00:48 PM PDT 24
Finished Aug 08 08:01:23 PM PDT 24
Peak memory 575868 kb
Host smart-b31571a8-93c5-4067-b866-2fc8683abbc6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135052463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_dela
ys.135052463
Directory /workspace/55.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_same_source.4107351535
Short name T1626
Test name
Test status
Simulation time 564387426 ps
CPU time 39.31 seconds
Started Aug 08 08:00:46 PM PDT 24
Finished Aug 08 08:01:26 PM PDT 24
Peak memory 575724 kb
Host smart-75fd9c59-9545-415e-b5b9-55e29275ca78
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107351535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.4107351535
Directory /workspace/55.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke.1236561976
Short name T2831
Test name
Test status
Simulation time 214720206 ps
CPU time 8.91 seconds
Started Aug 08 08:00:40 PM PDT 24
Finished Aug 08 08:00:49 PM PDT 24
Peak memory 574532 kb
Host smart-7a34d678-1f9c-4803-bb47-b6685cabb629
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236561976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.1236561976
Directory /workspace/55.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.2308563843
Short name T2256
Test name
Test status
Simulation time 8939788621 ps
CPU time 93.25 seconds
Started Aug 08 08:00:39 PM PDT 24
Finished Aug 08 08:02:12 PM PDT 24
Peak memory 574572 kb
Host smart-d158bead-c462-47f3-aa8c-6c216a918b59
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308563843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.2308563843
Directory /workspace/55.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.744748415
Short name T1458
Test name
Test status
Simulation time 3878426638 ps
CPU time 58.14 seconds
Started Aug 08 08:00:40 PM PDT 24
Finished Aug 08 08:01:38 PM PDT 24
Peak memory 573836 kb
Host smart-bcd6a4f5-5a88-4013-8f9f-42d857bc63b4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744748415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.744748415
Directory /workspace/55.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.541208374
Short name T2929
Test name
Test status
Simulation time 55102865 ps
CPU time 6.61 seconds
Started Aug 08 08:00:39 PM PDT 24
Finished Aug 08 08:00:46 PM PDT 24
Peak memory 573808 kb
Host smart-08c5b834-16b1-4472-ace8-5a71980b612c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541208374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delays
.541208374
Directory /workspace/55.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all.972746414
Short name T1980
Test name
Test status
Simulation time 4333778090 ps
CPU time 347.52 seconds
Started Aug 08 08:00:54 PM PDT 24
Finished Aug 08 08:06:41 PM PDT 24
Peak memory 576280 kb
Host smart-d24cb28d-f904-4324-8826-baa4cbe5266c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972746414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.972746414
Directory /workspace/55.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.1077853267
Short name T1996
Test name
Test status
Simulation time 916006754 ps
CPU time 75.52 seconds
Started Aug 08 08:00:53 PM PDT 24
Finished Aug 08 08:02:08 PM PDT 24
Peak memory 575984 kb
Host smart-78b785ec-ab70-4465-ae16-a83ce71f7493
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077853267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.1077853267
Directory /workspace/55.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.4169527704
Short name T2868
Test name
Test status
Simulation time 610112012 ps
CPU time 223.88 seconds
Started Aug 08 08:00:55 PM PDT 24
Finished Aug 08 08:04:39 PM PDT 24
Peak memory 576688 kb
Host smart-84b456a3-d8fc-4e88-bfad-5c471d4bd9b4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169527704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all
_with_rand_reset.4169527704
Directory /workspace/55.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.2598722414
Short name T2375
Test name
Test status
Simulation time 230955116 ps
CPU time 47.63 seconds
Started Aug 08 08:00:52 PM PDT 24
Finished Aug 08 08:01:40 PM PDT 24
Peak memory 575924 kb
Host smart-cc491db1-5a1a-4a92-9bb0-64d1a5ff0579
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598722414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al
l_with_reset_error.2598722414
Directory /workspace/55.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.943977264
Short name T552
Test name
Test status
Simulation time 1381960617 ps
CPU time 52.26 seconds
Started Aug 08 08:00:40 PM PDT 24
Finished Aug 08 08:01:32 PM PDT 24
Peak memory 575908 kb
Host smart-85265872-9452-4327-90ac-0acb83b80c44
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943977264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.943977264
Directory /workspace/55.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_access_same_device.2680023075
Short name T2410
Test name
Test status
Simulation time 2774310952 ps
CPU time 114.87 seconds
Started Aug 08 08:00:53 PM PDT 24
Finished Aug 08 08:02:48 PM PDT 24
Peak memory 575988 kb
Host smart-55da88cf-b809-4307-85eb-8087f12d59c0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680023075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device
.2680023075
Directory /workspace/56.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.3577024553
Short name T458
Test name
Test status
Simulation time 55246277535 ps
CPU time 822.98 seconds
Started Aug 08 08:01:00 PM PDT 24
Finished Aug 08 08:14:44 PM PDT 24
Peak memory 576008 kb
Host smart-e7cb6990-7b9c-443b-bd6d-bbb03cf841c3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577024553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_
device_slow_rsp.3577024553
Directory /workspace/56.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.3780366019
Short name T1935
Test name
Test status
Simulation time 912165988 ps
CPU time 35.74 seconds
Started Aug 08 08:01:07 PM PDT 24
Finished Aug 08 08:01:43 PM PDT 24
Peak memory 575964 kb
Host smart-1fdf5758-3b96-4934-95df-086dd19b57f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780366019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add
r.3780366019
Directory /workspace/56.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_error_random.4009807421
Short name T1616
Test name
Test status
Simulation time 426345754 ps
CPU time 17.47 seconds
Started Aug 08 08:01:16 PM PDT 24
Finished Aug 08 08:01:34 PM PDT 24
Peak memory 575652 kb
Host smart-7ba38e88-eb9b-4196-9030-039643d92214
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009807421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.4009807421
Directory /workspace/56.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random.2223096882
Short name T1497
Test name
Test status
Simulation time 262901021 ps
CPU time 27.16 seconds
Started Aug 08 08:00:56 PM PDT 24
Finished Aug 08 08:01:23 PM PDT 24
Peak memory 575864 kb
Host smart-dfdced62-bb94-4699-9a58-9ad2818de0e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223096882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.2223096882
Directory /workspace/56.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.3849344528
Short name T2513
Test name
Test status
Simulation time 86705005987 ps
CPU time 941.38 seconds
Started Aug 08 08:00:54 PM PDT 24
Finished Aug 08 08:16:35 PM PDT 24
Peak memory 575908 kb
Host smart-618780eb-1fd4-4b4b-bf28-ab87338f756f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849344528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.3849344528
Directory /workspace/56.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.3459368503
Short name T1842
Test name
Test status
Simulation time 28314962898 ps
CPU time 479.11 seconds
Started Aug 08 08:00:54 PM PDT 24
Finished Aug 08 08:08:53 PM PDT 24
Peak memory 576036 kb
Host smart-d68e6498-bdc5-40d4-9a97-01a6c40a6de1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459368503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.3459368503
Directory /workspace/56.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.3286743453
Short name T471
Test name
Test status
Simulation time 347226697 ps
CPU time 31.13 seconds
Started Aug 08 08:00:54 PM PDT 24
Finished Aug 08 08:01:25 PM PDT 24
Peak memory 575740 kb
Host smart-c3f2f381-ca14-4d9e-ad5c-b084983eaa3f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286743453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del
ays.3286743453
Directory /workspace/56.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_same_source.1153821649
Short name T1593
Test name
Test status
Simulation time 1446354579 ps
CPU time 40.58 seconds
Started Aug 08 08:01:05 PM PDT 24
Finished Aug 08 08:01:45 PM PDT 24
Peak memory 575884 kb
Host smart-7f15e896-a569-46bd-8789-0fb6cc736214
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153821649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.1153821649
Directory /workspace/56.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke.2123752731
Short name T2260
Test name
Test status
Simulation time 57568474 ps
CPU time 6.97 seconds
Started Aug 08 08:00:53 PM PDT 24
Finished Aug 08 08:01:00 PM PDT 24
Peak memory 573860 kb
Host smart-8fe5c397-fc9c-4189-8f16-32734da65ab4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123752731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.2123752731
Directory /workspace/56.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.3958855291
Short name T2265
Test name
Test status
Simulation time 9635539257 ps
CPU time 102.65 seconds
Started Aug 08 08:00:55 PM PDT 24
Finished Aug 08 08:02:37 PM PDT 24
Peak memory 573904 kb
Host smart-a50d90c1-0228-4e5b-9639-993868413a9a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958855291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.3958855291
Directory /workspace/56.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.4069078145
Short name T1421
Test name
Test status
Simulation time 4872741434 ps
CPU time 90.06 seconds
Started Aug 08 08:00:54 PM PDT 24
Finished Aug 08 08:02:24 PM PDT 24
Peak memory 573896 kb
Host smart-44e424fc-308d-4458-872c-1ce1cee8f28e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069078145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.4069078145
Directory /workspace/56.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.608245868
Short name T1993
Test name
Test status
Simulation time 45949863 ps
CPU time 6.19 seconds
Started Aug 08 08:00:56 PM PDT 24
Finished Aug 08 08:01:02 PM PDT 24
Peak memory 573708 kb
Host smart-bd18eb46-3ded-4d4e-bcd2-45826691791b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608245868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delays
.608245868
Directory /workspace/56.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all.1324620021
Short name T499
Test name
Test status
Simulation time 6535044607 ps
CPU time 230.22 seconds
Started Aug 08 08:01:17 PM PDT 24
Finished Aug 08 08:05:07 PM PDT 24
Peak memory 575964 kb
Host smart-81becf09-d307-43a3-b5f2-402e2bc7e59a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324620021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.1324620021
Directory /workspace/56.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.3226904327
Short name T1890
Test name
Test status
Simulation time 10003065918 ps
CPU time 342.41 seconds
Started Aug 08 08:01:12 PM PDT 24
Finished Aug 08 08:06:55 PM PDT 24
Peak memory 576712 kb
Host smart-4a0bb854-a68b-4df3-afaf-e97f146dc49e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226904327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.3226904327
Directory /workspace/56.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.1664083864
Short name T1913
Test name
Test status
Simulation time 17797687 ps
CPU time 28.09 seconds
Started Aug 08 08:01:07 PM PDT 24
Finished Aug 08 08:01:35 PM PDT 24
Peak memory 574608 kb
Host smart-6e3a5f52-82e7-418d-8425-1dbc5b3ece96
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664083864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al
l_with_reset_error.1664083864
Directory /workspace/56.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.1704185211
Short name T1810
Test name
Test status
Simulation time 808529064 ps
CPU time 37.4 seconds
Started Aug 08 08:01:07 PM PDT 24
Finished Aug 08 08:01:44 PM PDT 24
Peak memory 575708 kb
Host smart-413a0457-9da2-4153-8259-912fbd6590a4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704185211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.1704185211
Directory /workspace/56.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_access_same_device.3488594193
Short name T2585
Test name
Test status
Simulation time 1839063015 ps
CPU time 77.58 seconds
Started Aug 08 08:01:16 PM PDT 24
Finished Aug 08 08:02:33 PM PDT 24
Peak memory 575984 kb
Host smart-fde1ce05-9fed-4abc-b023-d7ebc8f9d758
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488594193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device
.3488594193
Directory /workspace/57.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.803602813
Short name T1717
Test name
Test status
Simulation time 64655078428 ps
CPU time 1058.15 seconds
Started Aug 08 08:01:17 PM PDT 24
Finished Aug 08 08:18:56 PM PDT 24
Peak memory 575852 kb
Host smart-9bd1366c-8aa1-4f95-9f87-bc1859db384a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803602813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_d
evice_slow_rsp.803602813
Directory /workspace/57.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.3287200198
Short name T2596
Test name
Test status
Simulation time 1165662954 ps
CPU time 45.73 seconds
Started Aug 08 08:01:18 PM PDT 24
Finished Aug 08 08:02:04 PM PDT 24
Peak memory 575944 kb
Host smart-dcd7490c-8f7d-419e-b58d-5d6b843eadfc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287200198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add
r.3287200198
Directory /workspace/57.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_error_random.922528481
Short name T1760
Test name
Test status
Simulation time 535083870 ps
CPU time 41.55 seconds
Started Aug 08 08:01:21 PM PDT 24
Finished Aug 08 08:02:02 PM PDT 24
Peak memory 575956 kb
Host smart-8f9dad64-d0e1-4c2f-bb0c-938e53ed7912
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922528481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.922528481
Directory /workspace/57.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random.1095241636
Short name T2040
Test name
Test status
Simulation time 614087968 ps
CPU time 23.84 seconds
Started Aug 08 08:01:17 PM PDT 24
Finished Aug 08 08:01:41 PM PDT 24
Peak memory 575880 kb
Host smart-661a7094-9ace-4117-9023-a3306758e8cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095241636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.1095241636
Directory /workspace/57.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.192623854
Short name T1527
Test name
Test status
Simulation time 60775624306 ps
CPU time 633.49 seconds
Started Aug 08 08:01:17 PM PDT 24
Finished Aug 08 08:11:51 PM PDT 24
Peak memory 576000 kb
Host smart-0e161750-281b-44ba-a241-b9f52a5e5b6c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192623854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.192623854
Directory /workspace/57.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.2731379605
Short name T483
Test name
Test status
Simulation time 25339008713 ps
CPU time 425.54 seconds
Started Aug 08 08:01:18 PM PDT 24
Finished Aug 08 08:08:24 PM PDT 24
Peak memory 575824 kb
Host smart-f40898bd-a1de-470d-a9a1-a67bf310adf9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731379605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.2731379605
Directory /workspace/57.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.3153665614
Short name T453
Test name
Test status
Simulation time 453877245 ps
CPU time 39.64 seconds
Started Aug 08 08:01:12 PM PDT 24
Finished Aug 08 08:01:52 PM PDT 24
Peak memory 575828 kb
Host smart-2965ab9f-cb31-42cf-9567-8790d40d2179
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153665614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del
ays.3153665614
Directory /workspace/57.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_same_source.1032708421
Short name T2837
Test name
Test status
Simulation time 2060395903 ps
CPU time 59.81 seconds
Started Aug 08 08:01:18 PM PDT 24
Finished Aug 08 08:02:18 PM PDT 24
Peak memory 575720 kb
Host smart-1a1c73af-aa0e-4377-a02d-b858982161b9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032708421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.1032708421
Directory /workspace/57.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke.40723786
Short name T2913
Test name
Test status
Simulation time 253366859 ps
CPU time 10.64 seconds
Started Aug 08 08:01:12 PM PDT 24
Finished Aug 08 08:01:23 PM PDT 24
Peak memory 574440 kb
Host smart-035780ac-c544-4caa-8c04-eded3f6996dc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40723786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.40723786
Directory /workspace/57.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.772614997
Short name T2478
Test name
Test status
Simulation time 5006324775 ps
CPU time 50.35 seconds
Started Aug 08 08:01:07 PM PDT 24
Finished Aug 08 08:01:58 PM PDT 24
Peak memory 573804 kb
Host smart-20c8db1f-3ba3-4d7f-92ac-8a4404eb1318
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772614997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.772614997
Directory /workspace/57.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.423473840
Short name T2210
Test name
Test status
Simulation time 4160828561 ps
CPU time 69.27 seconds
Started Aug 08 08:01:16 PM PDT 24
Finished Aug 08 08:02:25 PM PDT 24
Peak memory 573860 kb
Host smart-7c8043b2-5a62-49d4-85da-5e37784f3165
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423473840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.423473840
Directory /workspace/57.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.1293079281
Short name T1467
Test name
Test status
Simulation time 47180549 ps
CPU time 6.24 seconds
Started Aug 08 08:01:16 PM PDT 24
Finished Aug 08 08:01:23 PM PDT 24
Peak memory 574496 kb
Host smart-eeda5587-fb92-4d9a-bb9a-f6f7e8a7dad5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293079281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay
s.1293079281
Directory /workspace/57.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all.3587392192
Short name T492
Test name
Test status
Simulation time 8799811660 ps
CPU time 290.65 seconds
Started Aug 08 08:01:16 PM PDT 24
Finished Aug 08 08:06:07 PM PDT 24
Peak memory 576716 kb
Host smart-263c1d66-ee4d-4e64-9fba-7dc852abe6ca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587392192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.3587392192
Directory /workspace/57.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.3765100721
Short name T2147
Test name
Test status
Simulation time 1592015117 ps
CPU time 123.48 seconds
Started Aug 08 08:01:20 PM PDT 24
Finished Aug 08 08:03:23 PM PDT 24
Peak memory 576112 kb
Host smart-80cc09d0-d337-4691-b498-57c579218fd6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765100721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.3765100721
Directory /workspace/57.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.843880332
Short name T840
Test name
Test status
Simulation time 1156242659 ps
CPU time 219.56 seconds
Started Aug 08 08:01:16 PM PDT 24
Finished Aug 08 08:04:56 PM PDT 24
Peak memory 576728 kb
Host smart-89fde834-0abe-4aa7-bd6d-ead1789ac159
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843880332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all
_with_reset_error.843880332
Directory /workspace/57.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.3262231478
Short name T1941
Test name
Test status
Simulation time 140601307 ps
CPU time 18.6 seconds
Started Aug 08 08:01:20 PM PDT 24
Finished Aug 08 08:01:39 PM PDT 24
Peak memory 575960 kb
Host smart-68afa611-5d46-4173-9d35-51fa019434bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262231478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.3262231478
Directory /workspace/57.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_access_same_device.3387750921
Short name T1482
Test name
Test status
Simulation time 79646199 ps
CPU time 7.97 seconds
Started Aug 08 08:01:16 PM PDT 24
Finished Aug 08 08:01:24 PM PDT 24
Peak memory 573788 kb
Host smart-1eb9a48b-6ad2-417b-a617-b32c9bbe4cb9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387750921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device
.3387750921
Directory /workspace/58.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.1398598676
Short name T2205
Test name
Test status
Simulation time 74749610353 ps
CPU time 1328.14 seconds
Started Aug 08 08:01:17 PM PDT 24
Finished Aug 08 08:23:25 PM PDT 24
Peak memory 576756 kb
Host smart-1a57a34d-0e6b-4b87-b625-3c724a8d8394
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398598676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_
device_slow_rsp.1398598676
Directory /workspace/58.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3238777501
Short name T1839
Test name
Test status
Simulation time 22893586 ps
CPU time 5.21 seconds
Started Aug 08 08:01:34 PM PDT 24
Finished Aug 08 08:01:39 PM PDT 24
Peak memory 573772 kb
Host smart-05774a42-197d-46eb-bfe6-4fcc3a6a905d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238777501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add
r.3238777501
Directory /workspace/58.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_error_random.2275144597
Short name T2257
Test name
Test status
Simulation time 762984367 ps
CPU time 26.45 seconds
Started Aug 08 08:01:33 PM PDT 24
Finished Aug 08 08:02:00 PM PDT 24
Peak memory 575940 kb
Host smart-d72db052-5644-4b48-9f3b-bc638474a2c1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275144597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.2275144597
Directory /workspace/58.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random.4287401373
Short name T1958
Test name
Test status
Simulation time 1234823323 ps
CPU time 44.06 seconds
Started Aug 08 08:01:20 PM PDT 24
Finished Aug 08 08:02:04 PM PDT 24
Peak memory 575728 kb
Host smart-7ae452cb-fde1-44c9-b3cb-ccb7be61c7c8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287401373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.4287401373
Directory /workspace/58.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.571916129
Short name T2562
Test name
Test status
Simulation time 97912414765 ps
CPU time 1037.43 seconds
Started Aug 08 08:01:19 PM PDT 24
Finished Aug 08 08:18:37 PM PDT 24
Peak memory 576768 kb
Host smart-15da15e9-f92e-48c6-90ac-ee93dc8bff78
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571916129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.571916129
Directory /workspace/58.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.759825146
Short name T1462
Test name
Test status
Simulation time 55972078258 ps
CPU time 994.7 seconds
Started Aug 08 08:01:18 PM PDT 24
Finished Aug 08 08:17:52 PM PDT 24
Peak memory 575944 kb
Host smart-fcd03a51-8bc5-4c7b-b20b-389db3280495
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759825146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.759825146
Directory /workspace/58.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.389762334
Short name T1974
Test name
Test status
Simulation time 370360719 ps
CPU time 31.06 seconds
Started Aug 08 08:01:18 PM PDT 24
Finished Aug 08 08:01:49 PM PDT 24
Peak memory 575764 kb
Host smart-ca2e311d-7c3b-48f9-8980-42ce01369df6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389762334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_dela
ys.389762334
Directory /workspace/58.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_same_source.1553232997
Short name T457
Test name
Test status
Simulation time 419996667 ps
CPU time 28.52 seconds
Started Aug 08 08:01:17 PM PDT 24
Finished Aug 08 08:01:45 PM PDT 24
Peak memory 575832 kb
Host smart-455e31bc-a5bf-4611-83b4-ce5cf97afbde
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553232997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.1553232997
Directory /workspace/58.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke.1423946617
Short name T2229
Test name
Test status
Simulation time 184986837 ps
CPU time 9.01 seconds
Started Aug 08 08:01:17 PM PDT 24
Finished Aug 08 08:01:26 PM PDT 24
Peak memory 573748 kb
Host smart-b044431e-9916-44c1-a869-4f43c0dbc604
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423946617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.1423946617
Directory /workspace/58.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.4275269537
Short name T2808
Test name
Test status
Simulation time 7665419850 ps
CPU time 77.84 seconds
Started Aug 08 08:01:17 PM PDT 24
Finished Aug 08 08:02:34 PM PDT 24
Peak memory 574640 kb
Host smart-284b38c8-5ee8-48e2-925b-96ce56ae35fa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275269537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.4275269537
Directory /workspace/58.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.3706675166
Short name T1840
Test name
Test status
Simulation time 4605698914 ps
CPU time 76.5 seconds
Started Aug 08 08:01:18 PM PDT 24
Finished Aug 08 08:02:35 PM PDT 24
Peak memory 574572 kb
Host smart-d9839c5b-37e4-47e4-9332-8510999bbcbc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706675166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.3706675166
Directory /workspace/58.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2539608683
Short name T1601
Test name
Test status
Simulation time 41734561 ps
CPU time 6.1 seconds
Started Aug 08 08:01:17 PM PDT 24
Finished Aug 08 08:01:23 PM PDT 24
Peak memory 573776 kb
Host smart-a78c3827-8ea6-4991-88b3-ecbf4bf398f1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539608683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay
s.2539608683
Directory /workspace/58.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all.1519401479
Short name T2065
Test name
Test status
Simulation time 5560711587 ps
CPU time 188.29 seconds
Started Aug 08 08:01:31 PM PDT 24
Finished Aug 08 08:04:40 PM PDT 24
Peak memory 575884 kb
Host smart-ae3bbf01-a9df-47ea-a551-7a6fadf16ab1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519401479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.1519401479
Directory /workspace/58.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.883473010
Short name T2547
Test name
Test status
Simulation time 7785036 ps
CPU time 7.1 seconds
Started Aug 08 08:01:34 PM PDT 24
Finished Aug 08 08:01:41 PM PDT 24
Peak memory 574548 kb
Host smart-c05a5eb2-87b4-4b4a-aee0-2c9e27cd435f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883473010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_
with_rand_reset.883473010
Directory /workspace/58.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.904242452
Short name T606
Test name
Test status
Simulation time 4830735029 ps
CPU time 402.15 seconds
Started Aug 08 08:01:32 PM PDT 24
Finished Aug 08 08:08:14 PM PDT 24
Peak memory 576776 kb
Host smart-47e47b30-1396-4abb-9b7e-55bf9dededa5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904242452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all
_with_reset_error.904242452
Directory /workspace/58.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.1923186065
Short name T2062
Test name
Test status
Simulation time 590156924 ps
CPU time 23.77 seconds
Started Aug 08 08:01:30 PM PDT 24
Finished Aug 08 08:01:54 PM PDT 24
Peak memory 576008 kb
Host smart-a55e9086-178a-4dab-a48d-9201d47c3b75
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923186065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.1923186065
Directory /workspace/58.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_access_same_device.3350343482
Short name T815
Test name
Test status
Simulation time 1268154801 ps
CPU time 44.54 seconds
Started Aug 08 08:01:31 PM PDT 24
Finished Aug 08 08:02:15 PM PDT 24
Peak memory 575892 kb
Host smart-4e245e6e-023a-44cd-b3f3-e8596ef13f7a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350343482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device
.3350343482
Directory /workspace/59.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.275909241
Short name T799
Test name
Test status
Simulation time 146223943458 ps
CPU time 2639.47 seconds
Started Aug 08 08:01:47 PM PDT 24
Finished Aug 08 08:45:47 PM PDT 24
Peak memory 575912 kb
Host smart-a414f8d9-9404-4442-83eb-7f75bbd9f5fc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275909241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_d
evice_slow_rsp.275909241
Directory /workspace/59.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.2904242073
Short name T1381
Test name
Test status
Simulation time 157405677 ps
CPU time 8.77 seconds
Started Aug 08 08:01:47 PM PDT 24
Finished Aug 08 08:01:56 PM PDT 24
Peak memory 573900 kb
Host smart-a2102925-59ae-4d0b-bd27-07221dee6ee1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904242073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add
r.2904242073
Directory /workspace/59.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_error_random.1052321553
Short name T1542
Test name
Test status
Simulation time 436638389 ps
CPU time 37.04 seconds
Started Aug 08 08:01:46 PM PDT 24
Finished Aug 08 08:02:23 PM PDT 24
Peak memory 575892 kb
Host smart-e9ba9afa-aeb2-42fc-aa4a-92a955d0a566
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052321553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.1052321553
Directory /workspace/59.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random.2201082556
Short name T2110
Test name
Test status
Simulation time 481895603 ps
CPU time 37.8 seconds
Started Aug 08 08:01:33 PM PDT 24
Finished Aug 08 08:02:11 PM PDT 24
Peak memory 575976 kb
Host smart-dfcad052-6cec-41f1-adad-2849d3bb4917
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201082556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.2201082556
Directory /workspace/59.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.3303882263
Short name T2168
Test name
Test status
Simulation time 67216194046 ps
CPU time 705.9 seconds
Started Aug 08 08:01:34 PM PDT 24
Finished Aug 08 08:13:21 PM PDT 24
Peak memory 575908 kb
Host smart-66c13d1f-24c3-478c-b637-50230b489ca7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303882263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.3303882263
Directory /workspace/59.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.3864643908
Short name T1531
Test name
Test status
Simulation time 41540995439 ps
CPU time 729.46 seconds
Started Aug 08 08:01:32 PM PDT 24
Finished Aug 08 08:13:42 PM PDT 24
Peak memory 576228 kb
Host smart-7f0a51e2-0b5c-4ffa-9568-c53ac1fcdb2c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864643908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.3864643908
Directory /workspace/59.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.449964663
Short name T1710
Test name
Test status
Simulation time 323344791 ps
CPU time 29.83 seconds
Started Aug 08 08:01:32 PM PDT 24
Finished Aug 08 08:02:01 PM PDT 24
Peak memory 575896 kb
Host smart-3a673e81-cefe-42b1-874f-04174c1e8e09
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449964663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_dela
ys.449964663
Directory /workspace/59.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_same_source.2537467483
Short name T2851
Test name
Test status
Simulation time 58543890 ps
CPU time 7.27 seconds
Started Aug 08 08:01:47 PM PDT 24
Finished Aug 08 08:01:55 PM PDT 24
Peak memory 574548 kb
Host smart-7d39d081-41cf-4f61-8e68-45c4648c1df3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537467483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.2537467483
Directory /workspace/59.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke.1874043877
Short name T1870
Test name
Test status
Simulation time 241501917 ps
CPU time 9.69 seconds
Started Aug 08 08:01:31 PM PDT 24
Finished Aug 08 08:01:41 PM PDT 24
Peak memory 574460 kb
Host smart-eda2091a-d8e4-4773-a1b9-920c755c338f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874043877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.1874043877
Directory /workspace/59.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.1615362121
Short name T1656
Test name
Test status
Simulation time 9682405357 ps
CPU time 101.63 seconds
Started Aug 08 08:01:34 PM PDT 24
Finished Aug 08 08:03:16 PM PDT 24
Peak memory 574584 kb
Host smart-33bfd5b6-8ba2-4e64-9abf-ad4b747e6f86
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615362121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.1615362121
Directory /workspace/59.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.1450185879
Short name T1385
Test name
Test status
Simulation time 2965854692 ps
CPU time 51.87 seconds
Started Aug 08 08:01:31 PM PDT 24
Finished Aug 08 08:02:23 PM PDT 24
Peak memory 573832 kb
Host smart-5049e8bc-6dab-4ef5-924f-cb4c9f7a1b58
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450185879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.1450185879
Directory /workspace/59.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.2593752961
Short name T2712
Test name
Test status
Simulation time 43253844 ps
CPU time 6.3 seconds
Started Aug 08 08:01:34 PM PDT 24
Finished Aug 08 08:01:41 PM PDT 24
Peak memory 573784 kb
Host smart-8ecebfd4-811d-4580-9813-0f18ff4436aa
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593752961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay
s.2593752961
Directory /workspace/59.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all.1328250177
Short name T2591
Test name
Test status
Simulation time 736029165 ps
CPU time 53.61 seconds
Started Aug 08 08:01:47 PM PDT 24
Finished Aug 08 08:02:40 PM PDT 24
Peak memory 575836 kb
Host smart-0fec163b-b5e6-49f7-9610-a39ab247fc42
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328250177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.1328250177
Directory /workspace/59.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.1041412208
Short name T1468
Test name
Test status
Simulation time 2628581924 ps
CPU time 193.15 seconds
Started Aug 08 08:01:47 PM PDT 24
Finished Aug 08 08:05:00 PM PDT 24
Peak memory 576148 kb
Host smart-7cef5500-62c6-45ea-9133-ed2374f7fceb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041412208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.1041412208
Directory /workspace/59.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3704502828
Short name T1700
Test name
Test status
Simulation time 11339117032 ps
CPU time 620.85 seconds
Started Aug 08 08:01:46 PM PDT 24
Finished Aug 08 08:12:08 PM PDT 24
Peak memory 575900 kb
Host smart-b88bc5f5-3f0f-4396-8b21-33a66385208d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704502828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all
_with_rand_reset.3704502828
Directory /workspace/59.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.3517949007
Short name T2429
Test name
Test status
Simulation time 8286195394 ps
CPU time 439.82 seconds
Started Aug 08 08:01:47 PM PDT 24
Finished Aug 08 08:09:07 PM PDT 24
Peak memory 576716 kb
Host smart-4ca78c9d-1493-4dc7-8665-57a9e935fbef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517949007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al
l_with_reset_error.3517949007
Directory /workspace/59.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.1354693952
Short name T1380
Test name
Test status
Simulation time 87885905 ps
CPU time 6.58 seconds
Started Aug 08 08:01:46 PM PDT 24
Finished Aug 08 08:01:52 PM PDT 24
Peak memory 573864 kb
Host smart-585441e6-f2cf-423f-b7d3-ddcccc5f85fa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354693952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.1354693952
Directory /workspace/59.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.183733154
Short name T2924
Test name
Test status
Simulation time 6600585478 ps
CPU time 483.31 seconds
Started Aug 08 07:50:35 PM PDT 24
Finished Aug 08 07:58:39 PM PDT 24
Peak memory 637784 kb
Host smart-d1a2d03f-8d8b-445d-b7b5-c7dfa77184ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183733154 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.183733154
Directory /workspace/6.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.chip_csr_rw.3477330488
Short name T2938
Test name
Test status
Simulation time 4017365400 ps
CPU time 299.67 seconds
Started Aug 08 07:50:35 PM PDT 24
Finished Aug 08 07:55:35 PM PDT 24
Peak memory 599012 kb
Host smart-709c95f5-a334-4b1a-ab4a-7c4a38cc75d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477330488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.3477330488
Directory /workspace/6.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.2764145776
Short name T1634
Test name
Test status
Simulation time 30315551488 ps
CPU time 4845.78 seconds
Started Aug 08 07:50:34 PM PDT 24
Finished Aug 08 09:11:20 PM PDT 24
Peak memory 593024 kb
Host smart-dd671e4a-5d93-4e72-ab38-ec9cade9ce23
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764145776 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.2764145776
Directory /workspace/6.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.chip_tl_errors.984783223
Short name T649
Test name
Test status
Simulation time 4230297379 ps
CPU time 386.15 seconds
Started Aug 08 07:50:31 PM PDT 24
Finished Aug 08 07:56:58 PM PDT 24
Peak memory 598664 kb
Host smart-892c9d5c-a727-40e7-bf39-52f90f21b979
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984783223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.984783223
Directory /workspace/6.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_access_same_device.3189776296
Short name T2234
Test name
Test status
Simulation time 205428235 ps
CPU time 13.96 seconds
Started Aug 08 07:50:31 PM PDT 24
Finished Aug 08 07:50:45 PM PDT 24
Peak memory 575916 kb
Host smart-41ff531c-c827-4372-aeea-aa86e6919d69
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189776296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.
3189776296
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.3984487526
Short name T808
Test name
Test status
Simulation time 45588649934 ps
CPU time 725.69 seconds
Started Aug 08 07:50:35 PM PDT 24
Finished Aug 08 08:02:40 PM PDT 24
Peak memory 575864 kb
Host smart-9160e08f-6382-4437-8570-bcbe4b78414a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984487526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d
evice_slow_rsp.3984487526
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.2545743409
Short name T2784
Test name
Test status
Simulation time 301301848 ps
CPU time 30.68 seconds
Started Aug 08 07:50:35 PM PDT 24
Finished Aug 08 07:51:06 PM PDT 24
Peak memory 575884 kb
Host smart-c710d4b0-a05a-402f-8394-8f2f17ab4298
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545743409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr
.2545743409
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_error_random.4062099077
Short name T1765
Test name
Test status
Simulation time 71200611 ps
CPU time 7.53 seconds
Started Aug 08 07:50:33 PM PDT 24
Finished Aug 08 07:50:41 PM PDT 24
Peak memory 575780 kb
Host smart-27f473ab-e92a-42aa-9620-e11691b6ce5e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062099077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.4062099077
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random.593179999
Short name T1588
Test name
Test status
Simulation time 97641674 ps
CPU time 10.69 seconds
Started Aug 08 07:50:35 PM PDT 24
Finished Aug 08 07:50:45 PM PDT 24
Peak memory 575792 kb
Host smart-1f6afc45-16cb-4d25-a2f3-e1e4fda91e59
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593179999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.593179999
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.445196385
Short name T2587
Test name
Test status
Simulation time 65528838317 ps
CPU time 660.65 seconds
Started Aug 08 07:50:32 PM PDT 24
Finished Aug 08 08:01:33 PM PDT 24
Peak memory 576036 kb
Host smart-e18e732f-22f9-4574-904d-37905ad6f966
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445196385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.445196385
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.1216513398
Short name T2009
Test name
Test status
Simulation time 11818512566 ps
CPU time 196.64 seconds
Started Aug 08 07:50:44 PM PDT 24
Finished Aug 08 07:54:01 PM PDT 24
Peak memory 575848 kb
Host smart-283371ce-26ea-418d-941e-376292c1bab0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216513398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1216513398
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.2337743825
Short name T1487
Test name
Test status
Simulation time 249822277 ps
CPU time 19.76 seconds
Started Aug 08 07:50:43 PM PDT 24
Finished Aug 08 07:51:03 PM PDT 24
Peak memory 575800 kb
Host smart-c3ae8ded-156b-4eff-b1e5-bbaba68b1c3d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337743825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela
ys.2337743825
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_same_source.3800040179
Short name T2533
Test name
Test status
Simulation time 42400577 ps
CPU time 6.39 seconds
Started Aug 08 07:50:32 PM PDT 24
Finished Aug 08 07:50:39 PM PDT 24
Peak memory 574472 kb
Host smart-582c4157-d3b6-4e1b-a0e2-eec49e5e14c1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800040179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3800040179
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke.561699993
Short name T1586
Test name
Test status
Simulation time 226350052 ps
CPU time 9.34 seconds
Started Aug 08 07:50:42 PM PDT 24
Finished Aug 08 07:50:52 PM PDT 24
Peak memory 573796 kb
Host smart-37f05897-3c1b-426e-88e6-531a5423eae7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561699993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.561699993
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.2880028677
Short name T2615
Test name
Test status
Simulation time 10282968213 ps
CPU time 112.01 seconds
Started Aug 08 07:50:44 PM PDT 24
Finished Aug 08 07:52:36 PM PDT 24
Peak memory 573856 kb
Host smart-1d1eea97-0bbb-4411-bddb-dfb47ae815ac
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880028677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2880028677
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.3562859403
Short name T1461
Test name
Test status
Simulation time 5847026240 ps
CPU time 98.68 seconds
Started Aug 08 07:50:31 PM PDT 24
Finished Aug 08 07:52:09 PM PDT 24
Peak memory 573872 kb
Host smart-754c8db7-60de-4bbc-9019-3ef9d008aa51
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562859403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3562859403
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.2405193662
Short name T2004
Test name
Test status
Simulation time 42473020 ps
CPU time 5.93 seconds
Started Aug 08 07:50:44 PM PDT 24
Finished Aug 08 07:50:50 PM PDT 24
Peak memory 574464 kb
Host smart-ef4cf5e0-a204-492d-b941-898910a15030
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405193662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays
.2405193662
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all.228078476
Short name T558
Test name
Test status
Simulation time 16435615438 ps
CPU time 640.88 seconds
Started Aug 08 07:50:31 PM PDT 24
Finished Aug 08 08:01:12 PM PDT 24
Peak memory 575960 kb
Host smart-a70630bd-9127-4d6c-b187-099dbd2d62e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228078476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.228078476
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.1334466154
Short name T2694
Test name
Test status
Simulation time 6634625795 ps
CPU time 240.74 seconds
Started Aug 08 07:50:34 PM PDT 24
Finished Aug 08 07:54:35 PM PDT 24
Peak memory 576140 kb
Host smart-499b11e6-4185-491b-9817-e15a0ab69f6d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334466154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1334466154
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.1540066278
Short name T1865
Test name
Test status
Simulation time 2024431625 ps
CPU time 230.6 seconds
Started Aug 08 07:50:35 PM PDT 24
Finished Aug 08 07:54:26 PM PDT 24
Peak memory 576688 kb
Host smart-d738929a-141f-45b8-8b55-abcb787bf9ee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540066278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_
with_rand_reset.1540066278
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.4077388426
Short name T2816
Test name
Test status
Simulation time 7120339112 ps
CPU time 334.38 seconds
Started Aug 08 07:50:43 PM PDT 24
Finished Aug 08 07:56:18 PM PDT 24
Peak memory 576768 kb
Host smart-8c4c9c20-e996-4c4c-9763-6b6df73fb2d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077388426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all
_with_reset_error.4077388426
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.74466885
Short name T2600
Test name
Test status
Simulation time 299492173 ps
CPU time 34.45 seconds
Started Aug 08 07:50:31 PM PDT 24
Finished Aug 08 07:51:06 PM PDT 24
Peak memory 575884 kb
Host smart-b56cfa95-4d22-49a1-95e2-e0a6e6cd5a9b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74466885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.74466885
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_access_same_device.2579455681
Short name T520
Test name
Test status
Simulation time 1473807208 ps
CPU time 61.23 seconds
Started Aug 08 08:01:49 PM PDT 24
Finished Aug 08 08:02:51 PM PDT 24
Peak memory 575900 kb
Host smart-3ea693f7-2488-455d-8402-cb9fb5b0f07b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579455681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device
.2579455681
Directory /workspace/60.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.185471071
Short name T2700
Test name
Test status
Simulation time 76964856903 ps
CPU time 1473.53 seconds
Started Aug 08 08:01:49 PM PDT 24
Finished Aug 08 08:26:23 PM PDT 24
Peak memory 576020 kb
Host smart-a85a0967-f42d-4a70-905e-0e257191d96d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185471071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_d
evice_slow_rsp.185471071
Directory /workspace/60.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.695756679
Short name T2114
Test name
Test status
Simulation time 255774696 ps
CPU time 12.65 seconds
Started Aug 08 08:01:48 PM PDT 24
Finished Aug 08 08:02:01 PM PDT 24
Peak memory 575936 kb
Host smart-e6b2e957-7b4c-4afe-bb6c-007e427339fb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695756679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_addr
.695756679
Directory /workspace/60.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_error_random.195121104
Short name T2079
Test name
Test status
Simulation time 617017376 ps
CPU time 49.11 seconds
Started Aug 08 08:01:48 PM PDT 24
Finished Aug 08 08:02:37 PM PDT 24
Peak memory 575884 kb
Host smart-76f66b63-a27d-4f23-9b40-96b97e3f4a03
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195121104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.195121104
Directory /workspace/60.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random.3158531077
Short name T1998
Test name
Test status
Simulation time 1589726633 ps
CPU time 52.4 seconds
Started Aug 08 08:01:48 PM PDT 24
Finished Aug 08 08:02:41 PM PDT 24
Peak memory 575932 kb
Host smart-9baf97d4-e379-4f29-a1c2-9ddacf31391c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158531077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.3158531077
Directory /workspace/60.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.2770069884
Short name T2845
Test name
Test status
Simulation time 19454556397 ps
CPU time 192.79 seconds
Started Aug 08 08:01:48 PM PDT 24
Finished Aug 08 08:05:01 PM PDT 24
Peak memory 575860 kb
Host smart-d3642ac2-94ed-4b00-8113-858fbee2b6d9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770069884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.2770069884
Directory /workspace/60.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.2203263412
Short name T599
Test name
Test status
Simulation time 18451124394 ps
CPU time 305.76 seconds
Started Aug 08 08:01:48 PM PDT 24
Finished Aug 08 08:06:54 PM PDT 24
Peak memory 576004 kb
Host smart-46a3f6a8-d92d-4107-b21d-a25569bb18d1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203263412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.2203263412
Directory /workspace/60.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.1938057723
Short name T1803
Test name
Test status
Simulation time 461297524 ps
CPU time 35.47 seconds
Started Aug 08 08:01:48 PM PDT 24
Finished Aug 08 08:02:23 PM PDT 24
Peak memory 575840 kb
Host smart-df5545b5-a3a0-4743-b49e-aa76fac62b2c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938057723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del
ays.1938057723
Directory /workspace/60.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_same_source.2885013397
Short name T2374
Test name
Test status
Simulation time 642880166 ps
CPU time 20.72 seconds
Started Aug 08 08:01:48 PM PDT 24
Finished Aug 08 08:02:09 PM PDT 24
Peak memory 575756 kb
Host smart-74f93cd9-e359-4bb7-8e08-acb0c7ffda9b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885013397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.2885013397
Directory /workspace/60.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke.3901014142
Short name T2446
Test name
Test status
Simulation time 51624640 ps
CPU time 6.76 seconds
Started Aug 08 08:01:49 PM PDT 24
Finished Aug 08 08:01:55 PM PDT 24
Peak memory 574472 kb
Host smart-6ffe1432-0b61-47c5-9cc3-1b769efc907c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901014142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.3901014142
Directory /workspace/60.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.2667365972
Short name T2709
Test name
Test status
Simulation time 9807562743 ps
CPU time 100.5 seconds
Started Aug 08 08:01:48 PM PDT 24
Finished Aug 08 08:03:29 PM PDT 24
Peak memory 574600 kb
Host smart-3eaddc44-7a2c-4dbf-a7da-9ea1479c5a6f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667365972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.2667365972
Directory /workspace/60.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.434361988
Short name T422
Test name
Test status
Simulation time 4584132816 ps
CPU time 74.13 seconds
Started Aug 08 08:01:48 PM PDT 24
Finished Aug 08 08:03:02 PM PDT 24
Peak memory 573932 kb
Host smart-7b274c5d-b614-4c80-9dcf-11d60f9a188a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434361988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.434361988
Directory /workspace/60.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.1006801354
Short name T2578
Test name
Test status
Simulation time 48133124 ps
CPU time 6.1 seconds
Started Aug 08 08:01:47 PM PDT 24
Finished Aug 08 08:01:54 PM PDT 24
Peak memory 573764 kb
Host smart-bb671f9c-8b7d-4bbb-9891-40efdcbd360a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006801354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay
s.1006801354
Directory /workspace/60.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all.249774350
Short name T506
Test name
Test status
Simulation time 4611093221 ps
CPU time 140.64 seconds
Started Aug 08 08:01:50 PM PDT 24
Finished Aug 08 08:04:10 PM PDT 24
Peak memory 576060 kb
Host smart-caa89f60-fce2-48d1-9402-e20ca8f0bbc1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249774350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.249774350
Directory /workspace/60.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.2355205552
Short name T2217
Test name
Test status
Simulation time 8941818143 ps
CPU time 344.82 seconds
Started Aug 08 08:01:48 PM PDT 24
Finished Aug 08 08:07:33 PM PDT 24
Peak memory 576024 kb
Host smart-7347d0fe-612d-4156-a865-ba8868d18f46
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355205552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.2355205552
Directory /workspace/60.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.1586436347
Short name T2085
Test name
Test status
Simulation time 100366527 ps
CPU time 43.54 seconds
Started Aug 08 08:01:50 PM PDT 24
Finished Aug 08 08:02:34 PM PDT 24
Peak memory 576512 kb
Host smart-3bdd1b0c-741e-4144-ade4-e6f340c7b494
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586436347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all
_with_rand_reset.1586436347
Directory /workspace/60.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.788683660
Short name T1650
Test name
Test status
Simulation time 337341551 ps
CPU time 123.66 seconds
Started Aug 08 08:01:50 PM PDT 24
Finished Aug 08 08:03:54 PM PDT 24
Peak memory 575868 kb
Host smart-883ea1d6-f27a-4574-a41f-180d6e2e683b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788683660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all
_with_reset_error.788683660
Directory /workspace/60.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.3602359847
Short name T2024
Test name
Test status
Simulation time 527588938 ps
CPU time 25.71 seconds
Started Aug 08 08:01:50 PM PDT 24
Finished Aug 08 08:02:16 PM PDT 24
Peak memory 575876 kb
Host smart-720a28d2-16ea-4f1b-8cd4-0f7b3b64969c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602359847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.3602359847
Directory /workspace/60.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_access_same_device.1947751262
Short name T2496
Test name
Test status
Simulation time 569348511 ps
CPU time 46.55 seconds
Started Aug 08 08:01:59 PM PDT 24
Finished Aug 08 08:02:46 PM PDT 24
Peak memory 575800 kb
Host smart-c10d0099-6918-4498-83ed-7430304bd681
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947751262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device
.1947751262
Directory /workspace/61.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.585503450
Short name T2238
Test name
Test status
Simulation time 84560595829 ps
CPU time 1579.03 seconds
Started Aug 08 08:02:01 PM PDT 24
Finished Aug 08 08:28:20 PM PDT 24
Peak memory 576688 kb
Host smart-d4a33b49-c176-4c5d-8d20-eff7fb198518
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585503450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_d
evice_slow_rsp.585503450
Directory /workspace/61.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.2111435737
Short name T2167
Test name
Test status
Simulation time 457711172 ps
CPU time 20.43 seconds
Started Aug 08 08:01:58 PM PDT 24
Finished Aug 08 08:02:18 PM PDT 24
Peak memory 575688 kb
Host smart-291e6551-498f-4134-bf13-48ee755693f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111435737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add
r.2111435737
Directory /workspace/61.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_error_random.1759662201
Short name T2458
Test name
Test status
Simulation time 1928942857 ps
CPU time 63.11 seconds
Started Aug 08 08:01:58 PM PDT 24
Finished Aug 08 08:03:01 PM PDT 24
Peak memory 575884 kb
Host smart-b3245476-9dea-48b5-bdcf-275333dffe7c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759662201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.1759662201
Directory /workspace/61.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random.2499320643
Short name T2390
Test name
Test status
Simulation time 1861295132 ps
CPU time 60.8 seconds
Started Aug 08 08:02:02 PM PDT 24
Finished Aug 08 08:03:02 PM PDT 24
Peak memory 575844 kb
Host smart-a6b97d85-023f-4071-aee1-2daf5f61d4ab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499320643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.2499320643
Directory /workspace/61.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.2068896091
Short name T440
Test name
Test status
Simulation time 69033816136 ps
CPU time 656.33 seconds
Started Aug 08 08:01:59 PM PDT 24
Finished Aug 08 08:12:55 PM PDT 24
Peak memory 575980 kb
Host smart-ae5be070-5005-43b0-bc58-6a089dca8429
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068896091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.2068896091
Directory /workspace/61.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.3467757408
Short name T2470
Test name
Test status
Simulation time 18269071310 ps
CPU time 308.94 seconds
Started Aug 08 08:01:58 PM PDT 24
Finished Aug 08 08:07:07 PM PDT 24
Peak memory 576716 kb
Host smart-6ae1cd56-7fec-459e-b1f0-7341871dd5ff
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467757408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.3467757408
Directory /workspace/61.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.2007391743
Short name T2013
Test name
Test status
Simulation time 553767803 ps
CPU time 47.38 seconds
Started Aug 08 08:01:57 PM PDT 24
Finished Aug 08 08:02:44 PM PDT 24
Peak memory 575792 kb
Host smart-fa093a6f-1cde-4651-95c7-de765291743d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007391743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del
ays.2007391743
Directory /workspace/61.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_same_source.1934519365
Short name T2307
Test name
Test status
Simulation time 175549034 ps
CPU time 14.66 seconds
Started Aug 08 08:02:01 PM PDT 24
Finished Aug 08 08:02:16 PM PDT 24
Peak memory 575752 kb
Host smart-27e83fe1-22e4-4ec4-b333-56f9d88616ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934519365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.1934519365
Directory /workspace/61.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke.1044197105
Short name T2211
Test name
Test status
Simulation time 43468841 ps
CPU time 6.07 seconds
Started Aug 08 08:01:52 PM PDT 24
Finished Aug 08 08:01:58 PM PDT 24
Peak memory 573800 kb
Host smart-e30e4443-d426-4740-b0f2-6789cf6472d3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044197105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.1044197105
Directory /workspace/61.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.1492561488
Short name T2484
Test name
Test status
Simulation time 8484369316 ps
CPU time 81.44 seconds
Started Aug 08 08:02:02 PM PDT 24
Finished Aug 08 08:03:23 PM PDT 24
Peak memory 573884 kb
Host smart-b384dd7a-0aeb-4313-88ac-b3156113c6d6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492561488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.1492561488
Directory /workspace/61.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.3258295528
Short name T2486
Test name
Test status
Simulation time 4616781614 ps
CPU time 80.36 seconds
Started Aug 08 08:01:58 PM PDT 24
Finished Aug 08 08:03:19 PM PDT 24
Peak memory 573948 kb
Host smart-8520f023-e8de-4ea4-85d5-71aca7787885
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258295528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.3258295528
Directory /workspace/61.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2709865136
Short name T2643
Test name
Test status
Simulation time 43335014 ps
CPU time 5.94 seconds
Started Aug 08 08:01:52 PM PDT 24
Finished Aug 08 08:01:58 PM PDT 24
Peak memory 573768 kb
Host smart-50ca5151-5f56-4117-9c30-39ea7fac8fcf
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709865136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay
s.2709865136
Directory /workspace/61.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all.3849929764
Short name T1873
Test name
Test status
Simulation time 10043483558 ps
CPU time 394.75 seconds
Started Aug 08 08:01:59 PM PDT 24
Finished Aug 08 08:08:34 PM PDT 24
Peak memory 576740 kb
Host smart-53fc8898-d6c7-41c2-ab14-d9ae060ec7ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849929764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.3849929764
Directory /workspace/61.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.3080492439
Short name T1763
Test name
Test status
Simulation time 7762057018 ps
CPU time 265.2 seconds
Started Aug 08 08:01:58 PM PDT 24
Finished Aug 08 08:06:23 PM PDT 24
Peak memory 576580 kb
Host smart-e5bde3f4-99e8-4239-a8d0-7218c82210c6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080492439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.3080492439
Directory /workspace/61.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.1859926225
Short name T1511
Test name
Test status
Simulation time 2636748173 ps
CPU time 254.53 seconds
Started Aug 08 08:01:59 PM PDT 24
Finished Aug 08 08:06:13 PM PDT 24
Peak memory 576800 kb
Host smart-866beae9-9730-4c31-8fa9-16b1829491f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859926225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al
l_with_reset_error.1859926225
Directory /workspace/61.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.3839069501
Short name T2760
Test name
Test status
Simulation time 544671312 ps
CPU time 21.96 seconds
Started Aug 08 08:01:59 PM PDT 24
Finished Aug 08 08:02:21 PM PDT 24
Peak memory 575748 kb
Host smart-3cf5aa61-26a0-4e3c-9e97-545d89e2f133
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839069501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.3839069501
Directory /workspace/61.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_access_same_device.3887767580
Short name T2045
Test name
Test status
Simulation time 250635193 ps
CPU time 14.23 seconds
Started Aug 08 08:02:12 PM PDT 24
Finished Aug 08 08:02:26 PM PDT 24
Peak memory 575732 kb
Host smart-55fac4cf-1bbd-44b1-9102-60f0c3eaf366
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887767580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device
.3887767580
Directory /workspace/62.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.642614629
Short name T2891
Test name
Test status
Simulation time 84632249357 ps
CPU time 1618.72 seconds
Started Aug 08 08:02:11 PM PDT 24
Finished Aug 08 08:29:11 PM PDT 24
Peak memory 576024 kb
Host smart-b516958b-892f-46ac-a81e-0feaaa035d02
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642614629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_d
evice_slow_rsp.642614629
Directory /workspace/62.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.1650320023
Short name T1425
Test name
Test status
Simulation time 74158392 ps
CPU time 10.82 seconds
Started Aug 08 08:02:19 PM PDT 24
Finished Aug 08 08:02:30 PM PDT 24
Peak memory 575892 kb
Host smart-408762ef-5c39-4029-b6bf-7ebed2f4dfae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650320023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add
r.1650320023
Directory /workspace/62.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_error_random.1926251832
Short name T82
Test name
Test status
Simulation time 43112957 ps
CPU time 6.62 seconds
Started Aug 08 08:02:11 PM PDT 24
Finished Aug 08 08:02:18 PM PDT 24
Peak memory 573868 kb
Host smart-88fcc663-f0df-416c-8ad0-608ff69e9622
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926251832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.1926251832
Directory /workspace/62.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random.769917530
Short name T1976
Test name
Test status
Simulation time 1751162760 ps
CPU time 61.35 seconds
Started Aug 08 08:02:01 PM PDT 24
Finished Aug 08 08:03:02 PM PDT 24
Peak memory 575804 kb
Host smart-abc9c2ce-7b20-4888-a842-0605cf2181df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769917530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.769917530
Directory /workspace/62.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.2045127775
Short name T1365
Test name
Test status
Simulation time 35695180822 ps
CPU time 360.9 seconds
Started Aug 08 08:01:59 PM PDT 24
Finished Aug 08 08:08:00 PM PDT 24
Peak memory 575800 kb
Host smart-790d84a3-60eb-41d6-a152-4183fdcb9dad
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045127775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.2045127775
Directory /workspace/62.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.2208398335
Short name T1491
Test name
Test status
Simulation time 31959206081 ps
CPU time 544.55 seconds
Started Aug 08 08:01:58 PM PDT 24
Finished Aug 08 08:11:03 PM PDT 24
Peak memory 575836 kb
Host smart-8f26fb83-4c16-44bd-a296-b1049c5ecd8b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208398335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.2208398335
Directory /workspace/62.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.3406037921
Short name T1443
Test name
Test status
Simulation time 37122235 ps
CPU time 6.68 seconds
Started Aug 08 08:02:00 PM PDT 24
Finished Aug 08 08:02:07 PM PDT 24
Peak memory 574480 kb
Host smart-4f5e8e97-08d6-4ec0-8d7d-701f9bc6570a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406037921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del
ays.3406037921
Directory /workspace/62.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_same_source.3881160014
Short name T1534
Test name
Test status
Simulation time 1724199558 ps
CPU time 49.02 seconds
Started Aug 08 08:02:11 PM PDT 24
Finished Aug 08 08:03:01 PM PDT 24
Peak memory 575860 kb
Host smart-b71b1cb7-df79-490b-8036-e0920f6574f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881160014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.3881160014
Directory /workspace/62.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke.3447782885
Short name T1434
Test name
Test status
Simulation time 240166348 ps
CPU time 9.26 seconds
Started Aug 08 08:01:58 PM PDT 24
Finished Aug 08 08:02:08 PM PDT 24
Peak memory 574472 kb
Host smart-2c6f199d-b8a7-4501-a16d-c7af848a3efc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447782885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.3447782885
Directory /workspace/62.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.275236762
Short name T2311
Test name
Test status
Simulation time 6814737367 ps
CPU time 72.74 seconds
Started Aug 08 08:02:00 PM PDT 24
Finished Aug 08 08:03:13 PM PDT 24
Peak memory 574576 kb
Host smart-ea036142-cfb8-4dc7-b798-b064decf3cfb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275236762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.275236762
Directory /workspace/62.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.460754029
Short name T1785
Test name
Test status
Simulation time 4897587188 ps
CPU time 79.58 seconds
Started Aug 08 08:01:58 PM PDT 24
Finished Aug 08 08:03:18 PM PDT 24
Peak memory 574576 kb
Host smart-2f6543e4-7709-4213-8673-afe710beddf9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460754029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.460754029
Directory /workspace/62.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.1880195564
Short name T1428
Test name
Test status
Simulation time 49333764 ps
CPU time 6.17 seconds
Started Aug 08 08:01:58 PM PDT 24
Finished Aug 08 08:02:04 PM PDT 24
Peak memory 573800 kb
Host smart-328143d1-3434-487b-9d2a-d1423f07fb67
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880195564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay
s.1880195564
Directory /workspace/62.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all.1467133857
Short name T2873
Test name
Test status
Simulation time 2845058475 ps
CPU time 266.14 seconds
Started Aug 08 08:02:11 PM PDT 24
Finished Aug 08 08:06:37 PM PDT 24
Peak memory 576788 kb
Host smart-66698344-3038-419b-a607-393839eebbb4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467133857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.1467133857
Directory /workspace/62.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.2717674787
Short name T1782
Test name
Test status
Simulation time 10994419499 ps
CPU time 362.72 seconds
Started Aug 08 08:02:11 PM PDT 24
Finished Aug 08 08:08:14 PM PDT 24
Peak memory 575944 kb
Host smart-f5302802-d053-4cf6-ae15-7e2dbd47ee97
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717674787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.2717674787
Directory /workspace/62.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.4174548000
Short name T578
Test name
Test status
Simulation time 812943902 ps
CPU time 303.84 seconds
Started Aug 08 08:02:12 PM PDT 24
Finished Aug 08 08:07:16 PM PDT 24
Peak memory 575904 kb
Host smart-c36a1ed7-995f-421d-b683-d8f79813b21e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174548000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all
_with_rand_reset.4174548000
Directory /workspace/62.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.910250905
Short name T2381
Test name
Test status
Simulation time 107105886 ps
CPU time 83.34 seconds
Started Aug 08 08:02:12 PM PDT 24
Finished Aug 08 08:03:35 PM PDT 24
Peak memory 575888 kb
Host smart-4ebdfdcb-0373-4b3d-aa1f-fd9087efb364
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910250905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all
_with_reset_error.910250905
Directory /workspace/62.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.1524704466
Short name T2889
Test name
Test status
Simulation time 853957501 ps
CPU time 31.42 seconds
Started Aug 08 08:02:11 PM PDT 24
Finished Aug 08 08:02:43 PM PDT 24
Peak memory 575768 kb
Host smart-1933ef45-9e65-44a2-8d4a-0c5851fde84e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524704466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.1524704466
Directory /workspace/62.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_access_same_device.2512732389
Short name T2588
Test name
Test status
Simulation time 1985715865 ps
CPU time 75.24 seconds
Started Aug 08 08:02:24 PM PDT 24
Finished Aug 08 08:03:39 PM PDT 24
Peak memory 575972 kb
Host smart-b59bf2d1-d6f8-4b04-95f3-1bdcb4f10dfc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512732389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device
.2512732389
Directory /workspace/63.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.109517256
Short name T2689
Test name
Test status
Simulation time 288472423 ps
CPU time 14 seconds
Started Aug 08 08:02:26 PM PDT 24
Finished Aug 08 08:02:40 PM PDT 24
Peak memory 575732 kb
Host smart-3f0c3ac4-f561-44cd-b0a3-33350185589d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109517256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_addr
.109517256
Directory /workspace/63.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_error_random.4241673269
Short name T1526
Test name
Test status
Simulation time 197460397 ps
CPU time 19.36 seconds
Started Aug 08 08:02:22 PM PDT 24
Finished Aug 08 08:02:41 PM PDT 24
Peak memory 575716 kb
Host smart-732cb107-aa35-4f4f-ae13-f7fba86db883
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241673269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.4241673269
Directory /workspace/63.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random.1328763236
Short name T2231
Test name
Test status
Simulation time 612808870 ps
CPU time 46.32 seconds
Started Aug 08 08:02:12 PM PDT 24
Finished Aug 08 08:02:58 PM PDT 24
Peak memory 575900 kb
Host smart-6bdd75bd-db52-4765-b125-5557d570c33f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328763236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.1328763236
Directory /workspace/63.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.1302013685
Short name T2770
Test name
Test status
Simulation time 80420979204 ps
CPU time 844.07 seconds
Started Aug 08 08:02:12 PM PDT 24
Finished Aug 08 08:16:16 PM PDT 24
Peak memory 576692 kb
Host smart-47b91252-334d-4886-97bd-530e3bc518ec
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302013685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.1302013685
Directory /workspace/63.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.2780941312
Short name T2202
Test name
Test status
Simulation time 54029871408 ps
CPU time 926.9 seconds
Started Aug 08 08:02:12 PM PDT 24
Finished Aug 08 08:17:39 PM PDT 24
Peak memory 576044 kb
Host smart-b4bf10f2-6cc5-4d95-b164-d296d16adc36
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780941312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.2780941312
Directory /workspace/63.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.1074109144
Short name T454
Test name
Test status
Simulation time 601956829 ps
CPU time 47.53 seconds
Started Aug 08 08:02:12 PM PDT 24
Finished Aug 08 08:02:59 PM PDT 24
Peak memory 575788 kb
Host smart-61fd4392-f799-4d2f-8a05-95f29e941aa2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074109144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del
ays.1074109144
Directory /workspace/63.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_same_source.3928217462
Short name T556
Test name
Test status
Simulation time 2564386327 ps
CPU time 70.01 seconds
Started Aug 08 08:02:22 PM PDT 24
Finished Aug 08 08:03:32 PM PDT 24
Peak memory 575872 kb
Host smart-0687ef27-1a9e-49d7-8fb8-b0f0f5dda9b4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928217462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.3928217462
Directory /workspace/63.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke.1787685615
Short name T586
Test name
Test status
Simulation time 45573674 ps
CPU time 6.28 seconds
Started Aug 08 08:02:12 PM PDT 24
Finished Aug 08 08:02:19 PM PDT 24
Peak memory 573772 kb
Host smart-229c6766-f727-4828-a534-fcc1e611e9cd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787685615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.1787685615
Directory /workspace/63.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.1322158501
Short name T2531
Test name
Test status
Simulation time 7428642530 ps
CPU time 77.77 seconds
Started Aug 08 08:02:12 PM PDT 24
Finished Aug 08 08:03:30 PM PDT 24
Peak memory 573900 kb
Host smart-ebb4aef3-d5c7-43df-b4c5-7abb7e5c5381
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322158501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.1322158501
Directory /workspace/63.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.1928570233
Short name T1923
Test name
Test status
Simulation time 4721011394 ps
CPU time 81.17 seconds
Started Aug 08 08:02:12 PM PDT 24
Finished Aug 08 08:03:33 PM PDT 24
Peak memory 574596 kb
Host smart-ce004a8c-a57b-47d2-a85a-9bbe6ebacd6d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928570233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.1928570233
Directory /workspace/63.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.3086634499
Short name T2686
Test name
Test status
Simulation time 45178360 ps
CPU time 6.27 seconds
Started Aug 08 08:02:11 PM PDT 24
Finished Aug 08 08:02:18 PM PDT 24
Peak memory 574448 kb
Host smart-07015e04-7abc-4dd7-bd92-7df62977e03f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086634499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay
s.3086634499
Directory /workspace/63.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all.625794734
Short name T2029
Test name
Test status
Simulation time 2175140857 ps
CPU time 191.2 seconds
Started Aug 08 08:02:30 PM PDT 24
Finished Aug 08 08:05:41 PM PDT 24
Peak memory 576016 kb
Host smart-3bb300b0-37f0-43a9-aaac-7e59a6b374db
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625794734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.625794734
Directory /workspace/63.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.3221500200
Short name T1522
Test name
Test status
Simulation time 7011560942 ps
CPU time 247.27 seconds
Started Aug 08 08:02:23 PM PDT 24
Finished Aug 08 08:06:30 PM PDT 24
Peak memory 575948 kb
Host smart-ad319ee5-7968-485b-a067-53878b3f80eb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221500200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.3221500200
Directory /workspace/63.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.1981959140
Short name T2601
Test name
Test status
Simulation time 4669666210 ps
CPU time 254.53 seconds
Started Aug 08 08:02:25 PM PDT 24
Finished Aug 08 08:06:39 PM PDT 24
Peak memory 576764 kb
Host smart-3279226b-8955-4d7b-9b1d-93201454f6ed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981959140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all
_with_rand_reset.1981959140
Directory /workspace/63.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.1996848828
Short name T2294
Test name
Test status
Simulation time 219293048 ps
CPU time 46.3 seconds
Started Aug 08 08:02:33 PM PDT 24
Finished Aug 08 08:03:19 PM PDT 24
Peak memory 576528 kb
Host smart-b91ef986-5fed-4580-9af7-250c65194009
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996848828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al
l_with_reset_error.1996848828
Directory /workspace/63.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.2009020041
Short name T1509
Test name
Test status
Simulation time 50501043 ps
CPU time 8.92 seconds
Started Aug 08 08:02:22 PM PDT 24
Finished Aug 08 08:02:31 PM PDT 24
Peak memory 575980 kb
Host smart-6722d429-d659-4685-9169-45209301f2b5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009020041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.2009020041
Directory /workspace/63.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_access_same_device.3941508149
Short name T2517
Test name
Test status
Simulation time 1285562936 ps
CPU time 52.48 seconds
Started Aug 08 08:02:29 PM PDT 24
Finished Aug 08 08:03:22 PM PDT 24
Peak memory 575896 kb
Host smart-77c5f091-b647-4fa3-b155-aa4236b49fe4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941508149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device
.3941508149
Directory /workspace/64.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.973684788
Short name T2897
Test name
Test status
Simulation time 239720675 ps
CPU time 25.04 seconds
Started Aug 08 08:02:39 PM PDT 24
Finished Aug 08 08:03:04 PM PDT 24
Peak memory 575944 kb
Host smart-ee07942b-b6cb-44ac-a8f6-e7f24e1dfcd2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973684788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_addr
.973684788
Directory /workspace/64.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_error_random.1900357300
Short name T2003
Test name
Test status
Simulation time 335708325 ps
CPU time 28.16 seconds
Started Aug 08 08:02:30 PM PDT 24
Finished Aug 08 08:02:58 PM PDT 24
Peak memory 575740 kb
Host smart-762e554b-c104-4b4e-8ed2-5b36598da805
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900357300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.1900357300
Directory /workspace/64.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random.3739777631
Short name T475
Test name
Test status
Simulation time 383620054 ps
CPU time 33.74 seconds
Started Aug 08 08:02:29 PM PDT 24
Finished Aug 08 08:03:03 PM PDT 24
Peak memory 575912 kb
Host smart-6cc4cada-31cb-4010-8a0a-c0782088df37
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739777631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.3739777631
Directory /workspace/64.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.1582731488
Short name T1598
Test name
Test status
Simulation time 66809792697 ps
CPU time 633.88 seconds
Started Aug 08 08:02:26 PM PDT 24
Finished Aug 08 08:13:00 PM PDT 24
Peak memory 575828 kb
Host smart-06f3c755-6c48-4593-8163-1af1edc6efb1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582731488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.1582731488
Directory /workspace/64.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.720122565
Short name T2935
Test name
Test status
Simulation time 67359923167 ps
CPU time 1194.04 seconds
Started Aug 08 08:02:23 PM PDT 24
Finished Aug 08 08:22:17 PM PDT 24
Peak memory 575976 kb
Host smart-e8a62cce-7a65-4ad9-a588-a36ea360fb92
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720122565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.720122565
Directory /workspace/64.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.4164025383
Short name T1614
Test name
Test status
Simulation time 539902694 ps
CPU time 45.23 seconds
Started Aug 08 08:02:30 PM PDT 24
Finished Aug 08 08:03:16 PM PDT 24
Peak memory 575908 kb
Host smart-f9925076-eded-4388-b511-3e0b8ae72bb6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164025383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del
ays.4164025383
Directory /workspace/64.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_same_source.1061471306
Short name T2716
Test name
Test status
Simulation time 813565306 ps
CPU time 24.42 seconds
Started Aug 08 08:02:34 PM PDT 24
Finished Aug 08 08:02:59 PM PDT 24
Peak memory 575836 kb
Host smart-a1ffb0ae-3e57-45aa-a9db-9dbfb32aff94
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061471306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.1061471306
Directory /workspace/64.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke.516301092
Short name T1922
Test name
Test status
Simulation time 47325467 ps
CPU time 6.35 seconds
Started Aug 08 08:02:24 PM PDT 24
Finished Aug 08 08:02:30 PM PDT 24
Peak memory 573804 kb
Host smart-08c5240b-8ce6-4659-b7a9-7683d49390c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516301092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.516301092
Directory /workspace/64.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.259475452
Short name T2714
Test name
Test status
Simulation time 6204562690 ps
CPU time 64.67 seconds
Started Aug 08 08:02:26 PM PDT 24
Finished Aug 08 08:03:31 PM PDT 24
Peak memory 574548 kb
Host smart-e936739e-37ab-4d78-a728-d93a39744c21
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259475452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.259475452
Directory /workspace/64.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.735779986
Short name T2856
Test name
Test status
Simulation time 5327863809 ps
CPU time 91.93 seconds
Started Aug 08 08:02:28 PM PDT 24
Finished Aug 08 08:04:00 PM PDT 24
Peak memory 573868 kb
Host smart-e2b18b5f-8c18-4304-a5a7-a822649b30c0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735779986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.735779986
Directory /workspace/64.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.55666711
Short name T1895
Test name
Test status
Simulation time 52593476 ps
CPU time 6.8 seconds
Started Aug 08 08:02:27 PM PDT 24
Finished Aug 08 08:02:34 PM PDT 24
Peak memory 574524 kb
Host smart-10e167b1-92d8-47d0-8166-4ac523956146
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55666711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delays.55666711
Directory /workspace/64.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all.1197072392
Short name T2118
Test name
Test status
Simulation time 3269422156 ps
CPU time 278.37 seconds
Started Aug 08 08:02:35 PM PDT 24
Finished Aug 08 08:07:13 PM PDT 24
Peak memory 576000 kb
Host smart-3ac03836-3661-47e1-a37a-0993b139ab2c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197072392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.1197072392
Directory /workspace/64.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.992593447
Short name T2477
Test name
Test status
Simulation time 706448667 ps
CPU time 55.58 seconds
Started Aug 08 08:02:39 PM PDT 24
Finished Aug 08 08:03:34 PM PDT 24
Peak memory 575980 kb
Host smart-0f2c8fe2-83cc-418c-8cbb-0fe82287847b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992593447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.992593447
Directory /workspace/64.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.4290183714
Short name T1748
Test name
Test status
Simulation time 99696470 ps
CPU time 13.23 seconds
Started Aug 08 08:02:35 PM PDT 24
Finished Aug 08 08:02:48 PM PDT 24
Peak memory 574652 kb
Host smart-b17388b1-2410-4875-815c-fd6b097a52cd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290183714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all
_with_rand_reset.4290183714
Directory /workspace/64.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3142346195
Short name T1851
Test name
Test status
Simulation time 3590109598 ps
CPU time 139.24 seconds
Started Aug 08 08:02:34 PM PDT 24
Finished Aug 08 08:04:54 PM PDT 24
Peak memory 576156 kb
Host smart-db4d5a71-84ac-4a1a-9040-bc9663fa914f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142346195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al
l_with_reset_error.3142346195
Directory /workspace/64.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.150866138
Short name T2908
Test name
Test status
Simulation time 837560990 ps
CPU time 37.75 seconds
Started Aug 08 08:02:22 PM PDT 24
Finished Aug 08 08:03:00 PM PDT 24
Peak memory 575912 kb
Host smart-f4f50206-a007-49d9-a5bf-8782e7bd4816
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150866138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.150866138
Directory /workspace/64.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_access_same_device.2447153072
Short name T1694
Test name
Test status
Simulation time 156603630 ps
CPU time 13.02 seconds
Started Aug 08 08:02:36 PM PDT 24
Finished Aug 08 08:02:49 PM PDT 24
Peak memory 575840 kb
Host smart-2b2136f3-d2b9-455e-967f-0c1aa5f2e932
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447153072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device
.2447153072
Directory /workspace/65.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.2998983399
Short name T2680
Test name
Test status
Simulation time 46103362441 ps
CPU time 811.02 seconds
Started Aug 08 08:02:35 PM PDT 24
Finished Aug 08 08:16:07 PM PDT 24
Peak memory 576044 kb
Host smart-9ab3c907-f921-45b0-abef-1da4f358fc2d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998983399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_
device_slow_rsp.2998983399
Directory /workspace/65.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.2461912745
Short name T2051
Test name
Test status
Simulation time 34489167 ps
CPU time 6.47 seconds
Started Aug 08 08:02:35 PM PDT 24
Finished Aug 08 08:02:42 PM PDT 24
Peak memory 574488 kb
Host smart-23e4f19d-d737-4903-bc9f-ffb869f00482
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461912745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add
r.2461912745
Directory /workspace/65.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_error_random.263170344
Short name T1450
Test name
Test status
Simulation time 199557125 ps
CPU time 18.62 seconds
Started Aug 08 08:02:37 PM PDT 24
Finished Aug 08 08:02:55 PM PDT 24
Peak memory 575828 kb
Host smart-0ab6b2bc-23f5-4604-9b21-80a739ba0bd9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263170344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.263170344
Directory /workspace/65.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random.2299308122
Short name T2602
Test name
Test status
Simulation time 117363419 ps
CPU time 13.53 seconds
Started Aug 08 08:02:36 PM PDT 24
Finished Aug 08 08:02:49 PM PDT 24
Peak memory 575928 kb
Host smart-0956a22a-816b-4ebf-9909-5451c393b344
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299308122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.2299308122
Directory /workspace/65.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.4148116462
Short name T1567
Test name
Test status
Simulation time 5230447361 ps
CPU time 55.01 seconds
Started Aug 08 08:02:35 PM PDT 24
Finished Aug 08 08:03:31 PM PDT 24
Peak memory 573836 kb
Host smart-3ba6ac52-e1e6-45a2-9ec8-9537e8490bcb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148116462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.4148116462
Directory /workspace/65.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.160248794
Short name T560
Test name
Test status
Simulation time 56514087807 ps
CPU time 1018.41 seconds
Started Aug 08 08:02:35 PM PDT 24
Finished Aug 08 08:19:34 PM PDT 24
Peak memory 575960 kb
Host smart-0907879e-8a64-4b32-85fe-43988e6005b5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160248794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.160248794
Directory /workspace/65.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.745297672
Short name T2397
Test name
Test status
Simulation time 282864648 ps
CPU time 25.73 seconds
Started Aug 08 08:02:35 PM PDT 24
Finished Aug 08 08:03:01 PM PDT 24
Peak memory 575856 kb
Host smart-7a64641c-a35e-4ea0-8d80-5cca34a2d1b3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745297672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_dela
ys.745297672
Directory /workspace/65.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_same_source.2597350565
Short name T1597
Test name
Test status
Simulation time 235466141 ps
CPU time 9.49 seconds
Started Aug 08 08:02:35 PM PDT 24
Finished Aug 08 08:02:44 PM PDT 24
Peak memory 573848 kb
Host smart-dbdbcfa7-be9f-498f-8b9a-1b44e4af05e8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597350565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.2597350565
Directory /workspace/65.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke.798249601
Short name T539
Test name
Test status
Simulation time 223573420 ps
CPU time 9.41 seconds
Started Aug 08 08:02:36 PM PDT 24
Finished Aug 08 08:02:45 PM PDT 24
Peak memory 573780 kb
Host smart-6706c298-0a67-492b-8c1f-f829fcf4f306
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798249601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.798249601
Directory /workspace/65.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.2044799209
Short name T1508
Test name
Test status
Simulation time 6330434135 ps
CPU time 64.79 seconds
Started Aug 08 08:02:34 PM PDT 24
Finished Aug 08 08:03:39 PM PDT 24
Peak memory 573916 kb
Host smart-d3f889b5-1e38-443d-8935-b4c5fadd8fb8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044799209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.2044799209
Directory /workspace/65.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.1499109036
Short name T1371
Test name
Test status
Simulation time 5500817107 ps
CPU time 91.09 seconds
Started Aug 08 08:02:36 PM PDT 24
Finished Aug 08 08:04:07 PM PDT 24
Peak memory 573880 kb
Host smart-969166dd-801f-40a0-91e5-3f6623520e32
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499109036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.1499109036
Directory /workspace/65.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.1281499814
Short name T1382
Test name
Test status
Simulation time 50148310 ps
CPU time 6.76 seconds
Started Aug 08 08:02:37 PM PDT 24
Finished Aug 08 08:02:43 PM PDT 24
Peak memory 573824 kb
Host smart-3350b34f-b920-4480-9d21-d0821cbba40b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281499814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay
s.1281499814
Directory /workspace/65.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all.2104220875
Short name T1742
Test name
Test status
Simulation time 387895197 ps
CPU time 33.68 seconds
Started Aug 08 08:02:35 PM PDT 24
Finished Aug 08 08:03:09 PM PDT 24
Peak memory 575792 kb
Host smart-85dee43b-c326-412f-b3ef-cfe051f3ab78
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104220875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.2104220875
Directory /workspace/65.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.2846227379
Short name T2130
Test name
Test status
Simulation time 9326764264 ps
CPU time 292.18 seconds
Started Aug 08 08:02:36 PM PDT 24
Finished Aug 08 08:07:28 PM PDT 24
Peak memory 576296 kb
Host smart-e0ab86a9-400a-4593-9e19-485ae4792b57
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846227379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.2846227379
Directory /workspace/65.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.3734219173
Short name T2688
Test name
Test status
Simulation time 113790114 ps
CPU time 50.02 seconds
Started Aug 08 08:02:36 PM PDT 24
Finished Aug 08 08:03:26 PM PDT 24
Peak memory 575908 kb
Host smart-82c31c06-736a-4143-98d0-25f1c8db34d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734219173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all
_with_rand_reset.3734219173
Directory /workspace/65.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.329725103
Short name T827
Test name
Test status
Simulation time 4046291144 ps
CPU time 437.56 seconds
Started Aug 08 08:02:37 PM PDT 24
Finished Aug 08 08:09:55 PM PDT 24
Peak memory 576692 kb
Host smart-a9c1026e-ed6a-4cfb-99d2-69559af514b9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329725103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all
_with_reset_error.329725103
Directory /workspace/65.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.1256517867
Short name T2300
Test name
Test status
Simulation time 92599024 ps
CPU time 11.45 seconds
Started Aug 08 08:02:39 PM PDT 24
Finished Aug 08 08:02:50 PM PDT 24
Peak memory 575920 kb
Host smart-bfafb72c-7b6b-44d2-8a15-41fc65c39f50
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256517867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.1256517867
Directory /workspace/65.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_access_same_device.565739750
Short name T797
Test name
Test status
Simulation time 921335254 ps
CPU time 58.62 seconds
Started Aug 08 08:02:54 PM PDT 24
Finished Aug 08 08:03:52 PM PDT 24
Peak memory 575992 kb
Host smart-cea3d2c8-d3b3-4fcf-a5e3-2ec8763827d4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565739750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device.
565739750
Directory /workspace/66.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.265613610
Short name T2658
Test name
Test status
Simulation time 89398823835 ps
CPU time 1532.3 seconds
Started Aug 08 08:02:53 PM PDT 24
Finished Aug 08 08:28:26 PM PDT 24
Peak memory 576012 kb
Host smart-22211b90-6315-447d-97de-00a9b572fdf5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265613610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_d
evice_slow_rsp.265613610
Directory /workspace/66.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.3073142952
Short name T2113
Test name
Test status
Simulation time 537170793 ps
CPU time 21.47 seconds
Started Aug 08 08:02:51 PM PDT 24
Finished Aug 08 08:03:13 PM PDT 24
Peak memory 575860 kb
Host smart-0e6c9958-deca-4073-b769-59f76c8c0f4a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073142952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add
r.3073142952
Directory /workspace/66.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_error_random.503312960
Short name T2786
Test name
Test status
Simulation time 905207161 ps
CPU time 27.91 seconds
Started Aug 08 08:02:48 PM PDT 24
Finished Aug 08 08:03:16 PM PDT 24
Peak memory 575932 kb
Host smart-bbf17a62-d1e1-47d1-9cf2-6d570b23c555
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503312960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.503312960
Directory /workspace/66.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random.1676462569
Short name T1529
Test name
Test status
Simulation time 1655472608 ps
CPU time 57.45 seconds
Started Aug 08 08:02:51 PM PDT 24
Finished Aug 08 08:03:49 PM PDT 24
Peak memory 575840 kb
Host smart-15fdb89e-7b75-4f35-923a-ec986909474a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676462569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.1676462569
Directory /workspace/66.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.3839543661
Short name T2022
Test name
Test status
Simulation time 39259149282 ps
CPU time 420.31 seconds
Started Aug 08 08:02:48 PM PDT 24
Finished Aug 08 08:09:48 PM PDT 24
Peak memory 575836 kb
Host smart-6b2b9262-dfad-422b-9d3e-e7e934e5fdbf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839543661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.3839543661
Directory /workspace/66.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.619365444
Short name T2228
Test name
Test status
Simulation time 3839111070 ps
CPU time 61.28 seconds
Started Aug 08 08:02:49 PM PDT 24
Finished Aug 08 08:03:50 PM PDT 24
Peak memory 573916 kb
Host smart-10d62bd0-6261-4add-88a3-0849b9ab4ad6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619365444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.619365444
Directory /workspace/66.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.3410300199
Short name T2918
Test name
Test status
Simulation time 500746562 ps
CPU time 47.49 seconds
Started Aug 08 08:02:48 PM PDT 24
Finished Aug 08 08:03:36 PM PDT 24
Peak memory 575804 kb
Host smart-108dcf1f-ede7-42e4-a324-08b938328a15
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410300199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del
ays.3410300199
Directory /workspace/66.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_same_source.2989536007
Short name T87
Test name
Test status
Simulation time 338760926 ps
CPU time 13.28 seconds
Started Aug 08 08:02:52 PM PDT 24
Finished Aug 08 08:03:05 PM PDT 24
Peak memory 575820 kb
Host smart-eea96526-874d-4cf5-9873-0bf0237b68f4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989536007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.2989536007
Directory /workspace/66.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke.2858639678
Short name T2419
Test name
Test status
Simulation time 38873974 ps
CPU time 5.87 seconds
Started Aug 08 08:02:37 PM PDT 24
Finished Aug 08 08:02:42 PM PDT 24
Peak memory 574536 kb
Host smart-d3218cee-06a6-4a26-9aa6-c457d8cc2650
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858639678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.2858639678
Directory /workspace/66.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.4262066376
Short name T2606
Test name
Test status
Simulation time 9514752366 ps
CPU time 104.26 seconds
Started Aug 08 08:02:53 PM PDT 24
Finished Aug 08 08:04:37 PM PDT 24
Peak memory 573932 kb
Host smart-4c6ce481-0a2c-4028-b777-322e0e15c4c3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262066376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.4262066376
Directory /workspace/66.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.3289647621
Short name T580
Test name
Test status
Simulation time 5815507189 ps
CPU time 105.52 seconds
Started Aug 08 08:02:53 PM PDT 24
Finished Aug 08 08:04:39 PM PDT 24
Peak memory 573944 kb
Host smart-98946583-1fb4-4998-9772-051cc21f7fcc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289647621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.3289647621
Directory /workspace/66.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.1870584431
Short name T1395
Test name
Test status
Simulation time 43214072 ps
CPU time 5.61 seconds
Started Aug 08 08:02:37 PM PDT 24
Finished Aug 08 08:02:42 PM PDT 24
Peak memory 573764 kb
Host smart-71ee21b2-240d-4cba-bb08-5d199d6666be
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870584431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay
s.1870584431
Directory /workspace/66.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all.2074525083
Short name T1934
Test name
Test status
Simulation time 2283324134 ps
CPU time 148.43 seconds
Started Aug 08 08:02:53 PM PDT 24
Finished Aug 08 08:05:21 PM PDT 24
Peak memory 576040 kb
Host smart-f47de39d-d0b3-4692-8a45-c96149ab5071
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074525083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.2074525083
Directory /workspace/66.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.2235608299
Short name T1787
Test name
Test status
Simulation time 5667024822 ps
CPU time 178.82 seconds
Started Aug 08 08:02:48 PM PDT 24
Finished Aug 08 08:05:47 PM PDT 24
Peak memory 576072 kb
Host smart-5a75b567-e668-4e3a-aa39-f82b06daf4bb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235608299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.2235608299
Directory /workspace/66.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.1312489588
Short name T1850
Test name
Test status
Simulation time 3089246369 ps
CPU time 237.34 seconds
Started Aug 08 08:02:51 PM PDT 24
Finished Aug 08 08:06:49 PM PDT 24
Peak memory 576788 kb
Host smart-5f5916e9-2c38-4f74-9e0e-4e801f1695bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312489588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all
_with_rand_reset.1312489588
Directory /workspace/66.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3473060816
Short name T642
Test name
Test status
Simulation time 9618305436 ps
CPU time 416.22 seconds
Started Aug 08 08:02:50 PM PDT 24
Finished Aug 08 08:09:46 PM PDT 24
Peak memory 576740 kb
Host smart-02cdaa17-01c2-41d1-bfaf-48db437065de
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473060816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al
l_with_reset_error.3473060816
Directory /workspace/66.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.1985117801
Short name T2809
Test name
Test status
Simulation time 1013882020 ps
CPU time 41.5 seconds
Started Aug 08 08:02:48 PM PDT 24
Finished Aug 08 08:03:30 PM PDT 24
Peak memory 575900 kb
Host smart-5a91ebee-71e5-4c01-ba33-ca646398e0bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985117801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.1985117801
Directory /workspace/66.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_access_same_device.3977788907
Short name T526
Test name
Test status
Simulation time 3097802061 ps
CPU time 117.97 seconds
Started Aug 08 08:02:47 PM PDT 24
Finished Aug 08 08:04:45 PM PDT 24
Peak memory 575892 kb
Host smart-fedf4741-e70e-45df-b3de-02a605c1dfed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977788907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device
.3977788907
Directory /workspace/67.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.2974780226
Short name T810
Test name
Test status
Simulation time 43506013238 ps
CPU time 698.28 seconds
Started Aug 08 08:02:52 PM PDT 24
Finished Aug 08 08:14:31 PM PDT 24
Peak memory 575980 kb
Host smart-aefa4279-2de0-4d1b-8959-016a218c3a2b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974780226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_
device_slow_rsp.2974780226
Directory /workspace/67.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.3316915447
Short name T1684
Test name
Test status
Simulation time 250226569 ps
CPU time 27.88 seconds
Started Aug 08 08:03:00 PM PDT 24
Finished Aug 08 08:03:28 PM PDT 24
Peak memory 575944 kb
Host smart-d2f5e9ce-9996-4c00-bdc0-4fbe3a226f9e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316915447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add
r.3316915447
Directory /workspace/67.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_error_random.2919982589
Short name T2296
Test name
Test status
Simulation time 2020330075 ps
CPU time 68.94 seconds
Started Aug 08 08:02:48 PM PDT 24
Finished Aug 08 08:03:57 PM PDT 24
Peak memory 575936 kb
Host smart-fe885031-14cc-479c-9ee2-016e66de399b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919982589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.2919982589
Directory /workspace/67.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random.2847702555
Short name T2503
Test name
Test status
Simulation time 364525096 ps
CPU time 34.4 seconds
Started Aug 08 08:02:51 PM PDT 24
Finished Aug 08 08:03:25 PM PDT 24
Peak memory 575952 kb
Host smart-1f8245c9-232e-4626-8b26-613d08a3a45e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847702555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.2847702555
Directory /workspace/67.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.766729685
Short name T2569
Test name
Test status
Simulation time 6057979573 ps
CPU time 58.24 seconds
Started Aug 08 08:02:49 PM PDT 24
Finished Aug 08 08:03:47 PM PDT 24
Peak memory 574568 kb
Host smart-4dc7a650-d094-46f1-ba06-3217f4f60e50
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766729685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.766729685
Directory /workspace/67.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.2650752919
Short name T2101
Test name
Test status
Simulation time 25672207222 ps
CPU time 434.42 seconds
Started Aug 08 08:02:54 PM PDT 24
Finished Aug 08 08:10:09 PM PDT 24
Peak memory 575880 kb
Host smart-fa8b6ef1-69f7-4c6d-81f5-790f4e1c9785
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650752919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.2650752919
Directory /workspace/67.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.3172894723
Short name T2436
Test name
Test status
Simulation time 560305672 ps
CPU time 49.9 seconds
Started Aug 08 08:02:48 PM PDT 24
Finished Aug 08 08:03:37 PM PDT 24
Peak memory 575900 kb
Host smart-dcaf15f5-05c6-4c68-8139-55220244e85d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172894723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del
ays.3172894723
Directory /workspace/67.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_same_source.1299906715
Short name T1579
Test name
Test status
Simulation time 384096859 ps
CPU time 30.74 seconds
Started Aug 08 08:02:48 PM PDT 24
Finished Aug 08 08:03:18 PM PDT 24
Peak memory 575856 kb
Host smart-2a37853f-9b78-4883-b81b-3346685a4095
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299906715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.1299906715
Directory /workspace/67.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke.856224391
Short name T2881
Test name
Test status
Simulation time 181839069 ps
CPU time 7.68 seconds
Started Aug 08 08:02:53 PM PDT 24
Finished Aug 08 08:03:01 PM PDT 24
Peak memory 573800 kb
Host smart-9aa1d042-0b00-46df-94e0-06f68b6134e5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856224391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.856224391
Directory /workspace/67.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.3239539779
Short name T1612
Test name
Test status
Simulation time 6770982873 ps
CPU time 70.27 seconds
Started Aug 08 08:02:52 PM PDT 24
Finished Aug 08 08:04:02 PM PDT 24
Peak memory 573856 kb
Host smart-d8d01409-c14e-4683-9c5e-f9377abd2ff7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239539779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.3239539779
Directory /workspace/67.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.1264382631
Short name T1972
Test name
Test status
Simulation time 5749007824 ps
CPU time 96.33 seconds
Started Aug 08 08:02:47 PM PDT 24
Finished Aug 08 08:04:23 PM PDT 24
Peak memory 573808 kb
Host smart-051bdc47-39ba-4e82-ab90-eb1094661fbc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264382631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.1264382631
Directory /workspace/67.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.1048839711
Short name T2597
Test name
Test status
Simulation time 42823015 ps
CPU time 6.64 seconds
Started Aug 08 08:02:53 PM PDT 24
Finished Aug 08 08:03:00 PM PDT 24
Peak memory 574436 kb
Host smart-7a9c7c5a-5d7c-4779-8ba3-b8b49882e79d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048839711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay
s.1048839711
Directory /workspace/67.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all.2935051347
Short name T2377
Test name
Test status
Simulation time 1825796832 ps
CPU time 141.82 seconds
Started Aug 08 08:02:58 PM PDT 24
Finished Aug 08 08:05:20 PM PDT 24
Peak memory 575848 kb
Host smart-07a2250a-131e-4e2b-99ab-753db2655865
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935051347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.2935051347
Directory /workspace/67.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.390834735
Short name T1969
Test name
Test status
Simulation time 958625364 ps
CPU time 32.86 seconds
Started Aug 08 08:02:59 PM PDT 24
Finished Aug 08 08:03:32 PM PDT 24
Peak memory 575988 kb
Host smart-9d770dd3-b36c-4be6-bc3c-a1ce2afe4295
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390834735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.390834735
Directory /workspace/67.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2398419081
Short name T495
Test name
Test status
Simulation time 1114300291 ps
CPU time 261.51 seconds
Started Aug 08 08:03:07 PM PDT 24
Finished Aug 08 08:07:29 PM PDT 24
Peak memory 575912 kb
Host smart-90d59477-f339-448b-a75f-73abd1458d94
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398419081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all
_with_rand_reset.2398419081
Directory /workspace/67.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.712594101
Short name T1829
Test name
Test status
Simulation time 484756182 ps
CPU time 54.88 seconds
Started Aug 08 08:03:00 PM PDT 24
Finished Aug 08 08:03:55 PM PDT 24
Peak memory 575892 kb
Host smart-2d0c990d-cc30-4de0-af5b-fb4dbbaa9a89
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712594101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all
_with_reset_error.712594101
Directory /workspace/67.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.1103024330
Short name T1364
Test name
Test status
Simulation time 294602793 ps
CPU time 15.83 seconds
Started Aug 08 08:03:01 PM PDT 24
Finished Aug 08 08:03:17 PM PDT 24
Peak memory 575776 kb
Host smart-4b5277f7-b910-4418-8bd4-cc0ec9276ede
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103024330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.1103024330
Directory /workspace/67.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_access_same_device.2900158854
Short name T2224
Test name
Test status
Simulation time 322142204 ps
CPU time 24.83 seconds
Started Aug 08 08:03:08 PM PDT 24
Finished Aug 08 08:03:33 PM PDT 24
Peak memory 575880 kb
Host smart-f6bd75db-61f4-4648-80b4-74bba88e15b1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900158854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device
.2900158854
Directory /workspace/68.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3367186834
Short name T2127
Test name
Test status
Simulation time 56552452793 ps
CPU time 1008.78 seconds
Started Aug 08 08:02:58 PM PDT 24
Finished Aug 08 08:19:47 PM PDT 24
Peak memory 575972 kb
Host smart-4851d00f-6fe5-4f4d-843b-9522aa4b972d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367186834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_
device_slow_rsp.3367186834
Directory /workspace/68.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.2273195473
Short name T2764
Test name
Test status
Simulation time 1325558092 ps
CPU time 53.13 seconds
Started Aug 08 08:03:14 PM PDT 24
Finished Aug 08 08:04:08 PM PDT 24
Peak memory 575932 kb
Host smart-b7123787-cb7d-42f8-b10b-0c80deba9888
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273195473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add
r.2273195473
Directory /workspace/68.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_error_random.554807254
Short name T1929
Test name
Test status
Simulation time 1696458542 ps
CPU time 59.43 seconds
Started Aug 08 08:02:58 PM PDT 24
Finished Aug 08 08:03:57 PM PDT 24
Peak memory 575940 kb
Host smart-9778ff38-0b77-4630-a278-34885d961b81
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554807254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.554807254
Directory /workspace/68.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random.2225460016
Short name T1543
Test name
Test status
Simulation time 524300942 ps
CPU time 42.2 seconds
Started Aug 08 08:02:59 PM PDT 24
Finished Aug 08 08:03:41 PM PDT 24
Peak memory 575764 kb
Host smart-74221610-b3c5-4013-9d3b-41eb7e4723b5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225460016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.2225460016
Directory /workspace/68.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.3856834687
Short name T1589
Test name
Test status
Simulation time 81831169000 ps
CPU time 883.27 seconds
Started Aug 08 08:03:00 PM PDT 24
Finished Aug 08 08:17:44 PM PDT 24
Peak memory 575848 kb
Host smart-f6469bc1-49ce-407c-9c5e-34ca3b3b57bc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856834687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.3856834687
Directory /workspace/68.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.3560828193
Short name T2025
Test name
Test status
Simulation time 57593660773 ps
CPU time 1034.43 seconds
Started Aug 08 08:03:00 PM PDT 24
Finished Aug 08 08:20:14 PM PDT 24
Peak memory 576068 kb
Host smart-62d5a82e-a210-4ef8-a372-8d45c1e54e21
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560828193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.3560828193
Directory /workspace/68.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.3794284021
Short name T2091
Test name
Test status
Simulation time 450603738 ps
CPU time 37.17 seconds
Started Aug 08 08:03:00 PM PDT 24
Finished Aug 08 08:03:37 PM PDT 24
Peak memory 576020 kb
Host smart-12ba51f1-7199-4916-b811-10359053a0e3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794284021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del
ays.3794284021
Directory /workspace/68.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_same_source.3243427072
Short name T1439
Test name
Test status
Simulation time 461661376 ps
CPU time 33.45 seconds
Started Aug 08 08:02:59 PM PDT 24
Finished Aug 08 08:03:32 PM PDT 24
Peak memory 575724 kb
Host smart-425949cd-6dd3-4822-aab3-83cd3fd396ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243427072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.3243427072
Directory /workspace/68.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke.447359559
Short name T2875
Test name
Test status
Simulation time 172561651 ps
CPU time 8.11 seconds
Started Aug 08 08:03:07 PM PDT 24
Finished Aug 08 08:03:15 PM PDT 24
Peak memory 573792 kb
Host smart-c8ce4e09-860f-45a4-8da6-7eb3a725a67e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447359559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.447359559
Directory /workspace/68.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.1032143158
Short name T2150
Test name
Test status
Simulation time 7189244529 ps
CPU time 75.52 seconds
Started Aug 08 08:02:58 PM PDT 24
Finished Aug 08 08:04:13 PM PDT 24
Peak memory 574556 kb
Host smart-c5cdcd95-3869-4a88-b343-98fd5501a2a5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032143158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.1032143158
Directory /workspace/68.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.3478618371
Short name T2549
Test name
Test status
Simulation time 5927376772 ps
CPU time 104.47 seconds
Started Aug 08 08:02:58 PM PDT 24
Finished Aug 08 08:04:43 PM PDT 24
Peak memory 574640 kb
Host smart-c9e5d301-1b3c-4d06-98c7-340937f4e40d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478618371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.3478618371
Directory /workspace/68.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.3284337792
Short name T2498
Test name
Test status
Simulation time 44810611 ps
CPU time 5.73 seconds
Started Aug 08 08:02:59 PM PDT 24
Finished Aug 08 08:03:05 PM PDT 24
Peak memory 573696 kb
Host smart-1501e419-6c74-409d-ac55-c7cebaac0f56
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284337792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay
s.3284337792
Directory /workspace/68.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all.2350826690
Short name T534
Test name
Test status
Simulation time 13976611405 ps
CPU time 510.81 seconds
Started Aug 08 08:03:11 PM PDT 24
Finished Aug 08 08:11:42 PM PDT 24
Peak memory 575892 kb
Host smart-43c41abf-8b28-48c8-80de-0cd5daa45c5b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350826690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.2350826690
Directory /workspace/68.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.2439922927
Short name T2907
Test name
Test status
Simulation time 1063655731 ps
CPU time 79.59 seconds
Started Aug 08 08:03:09 PM PDT 24
Finished Aug 08 08:04:29 PM PDT 24
Peak memory 575996 kb
Host smart-0b213067-5693-4c43-bf09-63809111c3ae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439922927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.2439922927
Directory /workspace/68.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3746419765
Short name T2827
Test name
Test status
Simulation time 89274387 ps
CPU time 75.45 seconds
Started Aug 08 08:03:10 PM PDT 24
Finished Aug 08 08:04:26 PM PDT 24
Peak memory 575836 kb
Host smart-994ec6f1-7ebe-41d4-950e-744133e78385
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746419765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all
_with_rand_reset.3746419765
Directory /workspace/68.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.267570148
Short name T2331
Test name
Test status
Simulation time 3130132918 ps
CPU time 298.15 seconds
Started Aug 08 08:03:12 PM PDT 24
Finished Aug 08 08:08:11 PM PDT 24
Peak memory 576800 kb
Host smart-6e0f9fbe-cc44-42b6-964e-30687150c1d3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267570148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all
_with_reset_error.267570148
Directory /workspace/68.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.2998134812
Short name T1631
Test name
Test status
Simulation time 1181757416 ps
CPU time 47.4 seconds
Started Aug 08 08:03:07 PM PDT 24
Finished Aug 08 08:03:54 PM PDT 24
Peak memory 575792 kb
Host smart-e1129135-c10d-4b0e-9b3c-f44fbf28e8cd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998134812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.2998134812
Directory /workspace/68.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_access_same_device.685462304
Short name T1547
Test name
Test status
Simulation time 210358336 ps
CPU time 19.17 seconds
Started Aug 08 08:03:12 PM PDT 24
Finished Aug 08 08:03:32 PM PDT 24
Peak memory 575856 kb
Host smart-841a1dae-7e5f-4981-83f9-af1632b518e0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685462304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device.
685462304
Directory /workspace/69.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.2004681490
Short name T2822
Test name
Test status
Simulation time 115843245353 ps
CPU time 2048.19 seconds
Started Aug 08 08:03:12 PM PDT 24
Finished Aug 08 08:37:21 PM PDT 24
Peak memory 576024 kb
Host smart-306d37a0-293f-4ba9-bbcb-c1a09e4c6068
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004681490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_
device_slow_rsp.2004681490
Directory /workspace/69.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.2977917268
Short name T1455
Test name
Test status
Simulation time 1034389916 ps
CPU time 39.56 seconds
Started Aug 08 08:03:12 PM PDT 24
Finished Aug 08 08:03:52 PM PDT 24
Peak memory 575988 kb
Host smart-c236d1dd-8187-4e28-8fe0-413f43f4312f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977917268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add
r.2977917268
Directory /workspace/69.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_error_random.879764078
Short name T2735
Test name
Test status
Simulation time 114962973 ps
CPU time 7.1 seconds
Started Aug 08 08:03:09 PM PDT 24
Finished Aug 08 08:03:16 PM PDT 24
Peak memory 574372 kb
Host smart-664fcf17-61cb-4333-9863-ab8b6aa6a119
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879764078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.879764078
Directory /workspace/69.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random.1786571778
Short name T2058
Test name
Test status
Simulation time 1303008700 ps
CPU time 48.09 seconds
Started Aug 08 08:03:14 PM PDT 24
Finished Aug 08 08:04:02 PM PDT 24
Peak memory 575752 kb
Host smart-60a6226c-dee3-4d1b-b9a5-23e0c87eb712
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786571778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.1786571778
Directory /workspace/69.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.1376685504
Short name T1475
Test name
Test status
Simulation time 2757378062 ps
CPU time 28.84 seconds
Started Aug 08 08:03:09 PM PDT 24
Finished Aug 08 08:03:38 PM PDT 24
Peak memory 573800 kb
Host smart-c0fa8fd6-d2af-41e3-a407-d54760437cd5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376685504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.1376685504
Directory /workspace/69.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.4221610411
Short name T2413
Test name
Test status
Simulation time 8029427395 ps
CPU time 133.27 seconds
Started Aug 08 08:03:12 PM PDT 24
Finished Aug 08 08:05:25 PM PDT 24
Peak memory 575956 kb
Host smart-d3f828a1-b20f-4d01-9001-f2b4bd01761e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221610411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.4221610411
Directory /workspace/69.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.2482417083
Short name T2768
Test name
Test status
Simulation time 537812028 ps
CPU time 45.44 seconds
Started Aug 08 08:03:09 PM PDT 24
Finished Aug 08 08:03:54 PM PDT 24
Peak memory 575760 kb
Host smart-8e9046d0-a158-445c-9508-2193a91d2e08
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482417083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del
ays.2482417083
Directory /workspace/69.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_same_source.3272885672
Short name T1473
Test name
Test status
Simulation time 1602111089 ps
CPU time 48.13 seconds
Started Aug 08 08:03:14 PM PDT 24
Finished Aug 08 08:04:02 PM PDT 24
Peak memory 575804 kb
Host smart-483879c8-abeb-4cfc-8b3c-1097b7bf21a7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272885672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.3272885672
Directory /workspace/69.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke.798112225
Short name T1651
Test name
Test status
Simulation time 209107617 ps
CPU time 8.25 seconds
Started Aug 08 08:03:10 PM PDT 24
Finished Aug 08 08:03:18 PM PDT 24
Peak memory 574492 kb
Host smart-8744a4ef-6536-40bc-b968-a73f7a6c0fc8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798112225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.798112225
Directory /workspace/69.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.1185748150
Short name T519
Test name
Test status
Simulation time 8636942809 ps
CPU time 90.04 seconds
Started Aug 08 08:03:12 PM PDT 24
Finished Aug 08 08:04:42 PM PDT 24
Peak memory 573920 kb
Host smart-10d774c5-f423-49bd-b1d3-c02495e1d710
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185748150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.1185748150
Directory /workspace/69.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.2764598543
Short name T1711
Test name
Test status
Simulation time 4633793820 ps
CPU time 77.36 seconds
Started Aug 08 08:03:08 PM PDT 24
Finished Aug 08 08:04:25 PM PDT 24
Peak memory 573892 kb
Host smart-0c1f16fa-f64b-412d-bf83-ae3e5a2c1d52
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764598543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.2764598543
Directory /workspace/69.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.2929611203
Short name T2139
Test name
Test status
Simulation time 45427334 ps
CPU time 5.83 seconds
Started Aug 08 08:03:12 PM PDT 24
Finished Aug 08 08:03:18 PM PDT 24
Peak memory 573756 kb
Host smart-cd1a728f-9876-4fab-9cb7-b97d46017bae
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929611203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay
s.2929611203
Directory /workspace/69.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all.230825551
Short name T1891
Test name
Test status
Simulation time 543224702 ps
CPU time 38.15 seconds
Started Aug 08 08:03:10 PM PDT 24
Finished Aug 08 08:03:48 PM PDT 24
Peak memory 575852 kb
Host smart-f7526d03-d710-45fa-85b6-c0d6415231a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230825551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.230825551
Directory /workspace/69.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.3229773806
Short name T671
Test name
Test status
Simulation time 846118030 ps
CPU time 63.41 seconds
Started Aug 08 08:03:10 PM PDT 24
Finished Aug 08 08:04:14 PM PDT 24
Peak memory 575980 kb
Host smart-976eb9c9-74eb-403b-a5c3-1bc84dfa57c4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229773806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.3229773806
Directory /workspace/69.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.672595397
Short name T1398
Test name
Test status
Simulation time 125753691 ps
CPU time 85.53 seconds
Started Aug 08 08:03:09 PM PDT 24
Finished Aug 08 08:04:35 PM PDT 24
Peak memory 576696 kb
Host smart-89dfe654-2975-498d-9e48-dbd5bc7e8f3d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672595397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_
with_rand_reset.672595397
Directory /workspace/69.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.3329365593
Short name T2887
Test name
Test status
Simulation time 4491776200 ps
CPU time 164.3 seconds
Started Aug 08 08:03:12 PM PDT 24
Finished Aug 08 08:05:56 PM PDT 24
Peak memory 576076 kb
Host smart-a66c3f90-8653-43dc-b1a8-b0ec215baa6f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329365593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al
l_with_reset_error.3329365593
Directory /workspace/69.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.1470517809
Short name T2911
Test name
Test status
Simulation time 917619192 ps
CPU time 36.81 seconds
Started Aug 08 08:03:09 PM PDT 24
Finished Aug 08 08:03:46 PM PDT 24
Peak memory 575952 kb
Host smart-aa7f97df-8fb7-4b86-94b7-77c35d147df2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470517809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.1470517809
Directory /workspace/69.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.2849387867
Short name T2674
Test name
Test status
Simulation time 7552517800 ps
CPU time 534.8 seconds
Started Aug 08 07:50:59 PM PDT 24
Finished Aug 08 07:59:54 PM PDT 24
Peak memory 638512 kb
Host smart-95bf617c-1f5a-4bae-9518-0da3bdc3c329
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849387867 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.2849387867
Directory /workspace/7.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.chip_csr_rw.3563317891
Short name T424
Test name
Test status
Simulation time 5914982413 ps
CPU time 480.55 seconds
Started Aug 08 07:50:59 PM PDT 24
Finished Aug 08 07:59:00 PM PDT 24
Peak memory 598532 kb
Host smart-e991f086-6cde-4df7-8aed-df15a98a85be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563317891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.3563317891
Directory /workspace/7.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.1917699640
Short name T1790
Test name
Test status
Simulation time 30025795538 ps
CPU time 4084.09 seconds
Started Aug 08 07:50:43 PM PDT 24
Finished Aug 08 08:58:48 PM PDT 24
Peak memory 593732 kb
Host smart-d1cb9f93-88c7-4a61-ad72-160b18e3c630
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917699640 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.1917699640
Directory /workspace/7.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.chip_tl_errors.3863309447
Short name T2143
Test name
Test status
Simulation time 3851579522 ps
CPU time 280.59 seconds
Started Aug 08 07:50:42 PM PDT 24
Finished Aug 08 07:55:23 PM PDT 24
Peak memory 598568 kb
Host smart-c5b3874b-b70e-4542-8aef-3cae6572da09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863309447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.3863309447
Directory /workspace/7.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_access_same_device.4115241098
Short name T2803
Test name
Test status
Simulation time 1768127201 ps
CPU time 79.89 seconds
Started Aug 08 07:50:46 PM PDT 24
Finished Aug 08 07:52:06 PM PDT 24
Peak memory 575912 kb
Host smart-8115cfb1-f27b-4b74-bf76-4d29d95b9f12
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115241098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.
4115241098
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.3246456272
Short name T772
Test name
Test status
Simulation time 62760355645 ps
CPU time 1087.59 seconds
Started Aug 08 07:50:47 PM PDT 24
Finished Aug 08 08:08:55 PM PDT 24
Peak memory 575920 kb
Host smart-73fa7525-eff4-4024-8b5f-55cc5196218b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246456272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d
evice_slow_rsp.3246456272
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.613079493
Short name T1379
Test name
Test status
Simulation time 275555083 ps
CPU time 31.13 seconds
Started Aug 08 07:50:40 PM PDT 24
Finished Aug 08 07:51:12 PM PDT 24
Peak memory 575924 kb
Host smart-d1ed06ca-48f9-4ba7-b152-ef903179f4a8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613079493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.
613079493
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_error_random.3751563443
Short name T2771
Test name
Test status
Simulation time 2497892960 ps
CPU time 73.39 seconds
Started Aug 08 07:50:47 PM PDT 24
Finished Aug 08 07:52:00 PM PDT 24
Peak memory 575748 kb
Host smart-0a064e7d-659f-4f69-8815-df229e960647
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751563443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3751563443
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random.3201576189
Short name T2279
Test name
Test status
Simulation time 1908748249 ps
CPU time 71.19 seconds
Started Aug 08 07:50:59 PM PDT 24
Finished Aug 08 07:52:10 PM PDT 24
Peak memory 575648 kb
Host smart-ca095434-d85a-49e0-af4b-b991ead2facc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201576189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.3201576189
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.701543296
Short name T1698
Test name
Test status
Simulation time 29763375865 ps
CPU time 313.29 seconds
Started Aug 08 07:51:00 PM PDT 24
Finished Aug 08 07:56:13 PM PDT 24
Peak memory 575732 kb
Host smart-e7e24da5-ed8c-45f6-9be6-15958d95c32f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701543296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.701543296
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.2144367234
Short name T2033
Test name
Test status
Simulation time 44633591791 ps
CPU time 723.09 seconds
Started Aug 08 07:50:40 PM PDT 24
Finished Aug 08 08:02:44 PM PDT 24
Peak memory 575924 kb
Host smart-ba77d681-e74d-4202-9794-d9b9063afabc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144367234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2144367234
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.3107737845
Short name T2749
Test name
Test status
Simulation time 256873577 ps
CPU time 23.51 seconds
Started Aug 08 07:50:39 PM PDT 24
Finished Aug 08 07:51:03 PM PDT 24
Peak memory 575876 kb
Host smart-57049d8e-d9dc-443b-9034-f645ba3c3c30
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107737845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela
ys.3107737845
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_same_source.2440908015
Short name T2218
Test name
Test status
Simulation time 52761298 ps
CPU time 6.52 seconds
Started Aug 08 07:50:55 PM PDT 24
Finished Aug 08 07:51:01 PM PDT 24
Peak memory 573688 kb
Host smart-14edb68d-3943-49c2-ab06-20ebfeae0c80
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440908015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2440908015
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke.109011664
Short name T2928
Test name
Test status
Simulation time 244129768 ps
CPU time 10.7 seconds
Started Aug 08 07:50:31 PM PDT 24
Finished Aug 08 07:50:42 PM PDT 24
Peak memory 573760 kb
Host smart-97aa916f-0190-43a0-9948-4ac22e18ac17
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109011664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.109011664
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.3239748661
Short name T1503
Test name
Test status
Simulation time 7842231081 ps
CPU time 78.51 seconds
Started Aug 08 07:50:34 PM PDT 24
Finished Aug 08 07:51:53 PM PDT 24
Peak memory 573864 kb
Host smart-7c873994-c218-40a5-8a0c-26178fd8937e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239748661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3239748661
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.1500450702
Short name T2379
Test name
Test status
Simulation time 4561582528 ps
CPU time 78.03 seconds
Started Aug 08 07:50:39 PM PDT 24
Finished Aug 08 07:51:57 PM PDT 24
Peak memory 573812 kb
Host smart-6d99f3dd-a734-42b5-a8d0-7b676fc7f67c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500450702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1500450702
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.4232194781
Short name T1864
Test name
Test status
Simulation time 51457579 ps
CPU time 6.76 seconds
Started Aug 08 07:50:35 PM PDT 24
Finished Aug 08 07:50:42 PM PDT 24
Peak memory 574460 kb
Host smart-d1f49ade-3336-42ed-b7a1-40616896bb47
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232194781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays
.4232194781
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all.3794564338
Short name T2746
Test name
Test status
Simulation time 8253393163 ps
CPU time 274.81 seconds
Started Aug 08 07:50:39 PM PDT 24
Finished Aug 08 07:55:14 PM PDT 24
Peak memory 576024 kb
Host smart-00aaf0a9-6baa-4dad-8efe-f021f48e316b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794564338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3794564338
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.901610220
Short name T2614
Test name
Test status
Simulation time 11891861629 ps
CPU time 419.91 seconds
Started Aug 08 07:50:40 PM PDT 24
Finished Aug 08 07:57:40 PM PDT 24
Peak memory 576124 kb
Host smart-ccaa56de-61cd-4c34-bbc6-2e05a70d9303
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901610220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.901610220
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.149930754
Short name T2683
Test name
Test status
Simulation time 826966623 ps
CPU time 254.61 seconds
Started Aug 08 07:50:40 PM PDT 24
Finished Aug 08 07:54:55 PM PDT 24
Peak memory 575888 kb
Host smart-18c10df6-4e7d-46ad-8240-a768293ba2a6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149930754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_w
ith_rand_reset.149930754
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.414104256
Short name T2148
Test name
Test status
Simulation time 819549853 ps
CPU time 119.06 seconds
Started Aug 08 07:50:39 PM PDT 24
Finished Aug 08 07:52:38 PM PDT 24
Peak memory 575832 kb
Host smart-197ccc89-fc88-4a4d-a109-e428cf82bc89
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414104256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_
with_reset_error.414104256
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.2447693369
Short name T2309
Test name
Test status
Simulation time 135159321 ps
CPU time 7.89 seconds
Started Aug 08 07:50:45 PM PDT 24
Finished Aug 08 07:50:53 PM PDT 24
Peak memory 573856 kb
Host smart-7f5d4ad3-e6d7-4c0a-a157-3df3f4d9d9c4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447693369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2447693369
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_access_same_device.3415181202
Short name T1924
Test name
Test status
Simulation time 2169157925 ps
CPU time 86 seconds
Started Aug 08 08:03:34 PM PDT 24
Finished Aug 08 08:05:00 PM PDT 24
Peak memory 575924 kb
Host smart-ee4606c3-5c74-4d0a-aeb7-eb306eb9a286
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415181202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device
.3415181202
Directory /workspace/70.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.524408485
Short name T787
Test name
Test status
Simulation time 47370619222 ps
CPU time 791.81 seconds
Started Aug 08 08:03:20 PM PDT 24
Finished Aug 08 08:16:32 PM PDT 24
Peak memory 576028 kb
Host smart-e0951556-5709-4d6a-9110-0aae7cd9da37
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524408485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_d
evice_slow_rsp.524408485
Directory /workspace/70.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.1044705633
Short name T1571
Test name
Test status
Simulation time 1114401385 ps
CPU time 41.06 seconds
Started Aug 08 08:03:34 PM PDT 24
Finished Aug 08 08:04:15 PM PDT 24
Peak memory 575940 kb
Host smart-06472034-e30d-40a2-ba4c-ba6ce1890d39
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044705633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add
r.1044705633
Directory /workspace/70.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_error_random.3007434377
Short name T2738
Test name
Test status
Simulation time 1708558395 ps
CPU time 52.78 seconds
Started Aug 08 08:03:22 PM PDT 24
Finished Aug 08 08:04:14 PM PDT 24
Peak memory 575816 kb
Host smart-435ad56b-84f3-4965-bf6e-570c97017dc5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007434377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.3007434377
Directory /workspace/70.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random.1353237091
Short name T538
Test name
Test status
Simulation time 254715599 ps
CPU time 11.13 seconds
Started Aug 08 08:03:34 PM PDT 24
Finished Aug 08 08:03:45 PM PDT 24
Peak memory 575772 kb
Host smart-e247d30d-db18-4268-94ee-2bf10694fbf6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353237091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.1353237091
Directory /workspace/70.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.3785571022
Short name T2835
Test name
Test status
Simulation time 86416510416 ps
CPU time 970.4 seconds
Started Aug 08 08:03:34 PM PDT 24
Finished Aug 08 08:19:45 PM PDT 24
Peak memory 576736 kb
Host smart-4dd6d67d-da44-4b66-8cfb-2217bce11f99
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785571022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.3785571022
Directory /workspace/70.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.3842162588
Short name T461
Test name
Test status
Simulation time 3997675558 ps
CPU time 64.5 seconds
Started Aug 08 08:03:21 PM PDT 24
Finished Aug 08 08:04:25 PM PDT 24
Peak memory 574600 kb
Host smart-54317bf8-11b9-4051-842e-000d8319bf18
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842162588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.3842162588
Directory /workspace/70.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.481731855
Short name T2241
Test name
Test status
Simulation time 469601357 ps
CPU time 35.07 seconds
Started Aug 08 08:03:21 PM PDT 24
Finished Aug 08 08:03:56 PM PDT 24
Peak memory 575836 kb
Host smart-c3e934e1-a8c1-495b-89a6-f30f74efc1eb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481731855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_dela
ys.481731855
Directory /workspace/70.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_same_source.3874902129
Short name T1595
Test name
Test status
Simulation time 181830192 ps
CPU time 15.03 seconds
Started Aug 08 08:03:28 PM PDT 24
Finished Aug 08 08:03:43 PM PDT 24
Peak memory 575728 kb
Host smart-1a81fd2f-7f82-4144-bb2d-40f875030554
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874902129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.3874902129
Directory /workspace/70.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke.4065786222
Short name T1688
Test name
Test status
Simulation time 215736385 ps
CPU time 8.61 seconds
Started Aug 08 08:03:20 PM PDT 24
Finished Aug 08 08:03:29 PM PDT 24
Peak memory 573816 kb
Host smart-1033efeb-ba6c-4316-bee2-3e6fb5f81f3c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065786222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.4065786222
Directory /workspace/70.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.3617457030
Short name T1390
Test name
Test status
Simulation time 8335650307 ps
CPU time 84.24 seconds
Started Aug 08 08:03:22 PM PDT 24
Finished Aug 08 08:04:46 PM PDT 24
Peak memory 574556 kb
Host smart-35a6e4b5-4c16-469b-83fb-573f82afe2d8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617457030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.3617457030
Directory /workspace/70.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.2524455723
Short name T2412
Test name
Test status
Simulation time 4590922295 ps
CPU time 70.95 seconds
Started Aug 08 08:03:28 PM PDT 24
Finished Aug 08 08:04:39 PM PDT 24
Peak memory 573872 kb
Host smart-1d683d6f-3be8-47a4-8c26-ebdc20645044
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524455723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.2524455723
Directory /workspace/70.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.2775739236
Short name T2067
Test name
Test status
Simulation time 54905854 ps
CPU time 7.17 seconds
Started Aug 08 08:03:21 PM PDT 24
Finished Aug 08 08:03:28 PM PDT 24
Peak memory 574556 kb
Host smart-e8af11aa-0c7d-4e38-be5c-f9742d7aeea0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775739236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay
s.2775739236
Directory /workspace/70.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all.277148684
Short name T2844
Test name
Test status
Simulation time 3197653267 ps
CPU time 266.69 seconds
Started Aug 08 08:03:21 PM PDT 24
Finished Aug 08 08:07:48 PM PDT 24
Peak memory 575928 kb
Host smart-85c05067-6806-428b-81ec-5630224657a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277148684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.277148684
Directory /workspace/70.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.2989452423
Short name T2372
Test name
Test status
Simulation time 5323874350 ps
CPU time 171.54 seconds
Started Aug 08 08:03:20 PM PDT 24
Finished Aug 08 08:06:12 PM PDT 24
Peak memory 576180 kb
Host smart-92a990d2-171a-40ac-a8b5-05d5afd3b1e6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989452423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.2989452423
Directory /workspace/70.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.1837546278
Short name T1927
Test name
Test status
Simulation time 312328562 ps
CPU time 93.88 seconds
Started Aug 08 08:03:34 PM PDT 24
Finished Aug 08 08:05:08 PM PDT 24
Peak memory 576616 kb
Host smart-db391656-0b23-4371-9f15-5ec23fdc9df3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837546278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all
_with_rand_reset.1837546278
Directory /workspace/70.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.667786190
Short name T843
Test name
Test status
Simulation time 185191252 ps
CPU time 56.71 seconds
Started Aug 08 08:03:28 PM PDT 24
Finished Aug 08 08:04:25 PM PDT 24
Peak memory 575852 kb
Host smart-5452c166-543d-4bef-ae5e-a2e5ecfbd049
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667786190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all
_with_reset_error.667786190
Directory /workspace/70.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.2557986261
Short name T2341
Test name
Test status
Simulation time 73911173 ps
CPU time 6.08 seconds
Started Aug 08 08:03:21 PM PDT 24
Finished Aug 08 08:03:27 PM PDT 24
Peak memory 574504 kb
Host smart-61a29629-0d87-4f97-9d31-a0dd96d4f7bf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557986261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.2557986261
Directory /workspace/70.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_access_same_device.1825784323
Short name T822
Test name
Test status
Simulation time 133876506 ps
CPU time 17.11 seconds
Started Aug 08 08:03:40 PM PDT 24
Finished Aug 08 08:03:57 PM PDT 24
Peak memory 575772 kb
Host smart-262f3a96-afd6-4f54-83c1-e44a9e2044a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825784323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device
.1825784323
Directory /workspace/71.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2925611549
Short name T1490
Test name
Test status
Simulation time 170757168 ps
CPU time 19.77 seconds
Started Aug 08 08:03:41 PM PDT 24
Finished Aug 08 08:04:01 PM PDT 24
Peak memory 575940 kb
Host smart-75d23451-3e7d-4a1f-889e-07a3505af169
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925611549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add
r.2925611549
Directory /workspace/71.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_error_random.892451334
Short name T2861
Test name
Test status
Simulation time 285873069 ps
CPU time 25.02 seconds
Started Aug 08 08:03:42 PM PDT 24
Finished Aug 08 08:04:07 PM PDT 24
Peak memory 575828 kb
Host smart-4ba6e0d8-8f40-4f33-ae7c-5edbc52ecf9b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892451334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.892451334
Directory /workspace/71.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random.571772679
Short name T1814
Test name
Test status
Simulation time 830396434 ps
CPU time 28.09 seconds
Started Aug 08 08:03:40 PM PDT 24
Finished Aug 08 08:04:08 PM PDT 24
Peak memory 575832 kb
Host smart-a625af1a-f7f8-4ec5-aeea-0b9334284c6b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571772679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.571772679
Directory /workspace/71.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.150674358
Short name T2243
Test name
Test status
Simulation time 43416143319 ps
CPU time 454.63 seconds
Started Aug 08 08:03:41 PM PDT 24
Finished Aug 08 08:11:16 PM PDT 24
Peak memory 575932 kb
Host smart-f330fa91-005e-43c4-8cbd-50275c3e01a0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150674358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.150674358
Directory /workspace/71.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.1454183876
Short name T2093
Test name
Test status
Simulation time 65015257953 ps
CPU time 1173.82 seconds
Started Aug 08 08:03:41 PM PDT 24
Finished Aug 08 08:23:15 PM PDT 24
Peak memory 575876 kb
Host smart-e720b538-60fb-4644-b097-03d040d649a4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454183876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.1454183876
Directory /workspace/71.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.2494700526
Short name T2087
Test name
Test status
Simulation time 494708265 ps
CPU time 42.61 seconds
Started Aug 08 08:03:41 PM PDT 24
Finished Aug 08 08:04:23 PM PDT 24
Peak memory 575908 kb
Host smart-3af440c2-cd1d-4dbb-aac8-a2a27bbc2163
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494700526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del
ays.2494700526
Directory /workspace/71.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_same_source.538274944
Short name T2687
Test name
Test status
Simulation time 225545246 ps
CPU time 16.51 seconds
Started Aug 08 08:03:40 PM PDT 24
Finished Aug 08 08:03:56 PM PDT 24
Peak memory 575856 kb
Host smart-4c6fb36b-b8f3-4624-b558-25fd650e5ded
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538274944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.538274944
Directory /workspace/71.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke.49442424
Short name T2841
Test name
Test status
Simulation time 53015455 ps
CPU time 6.91 seconds
Started Aug 08 08:03:39 PM PDT 24
Finished Aug 08 08:03:46 PM PDT 24
Peak memory 573780 kb
Host smart-1aee3a1f-a13f-498f-bfc7-232163f779bf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49442424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.49442424
Directory /workspace/71.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.910624039
Short name T2765
Test name
Test status
Simulation time 7114124441 ps
CPU time 71.36 seconds
Started Aug 08 08:03:41 PM PDT 24
Finished Aug 08 08:04:53 PM PDT 24
Peak memory 574540 kb
Host smart-00fa8a58-7952-4a19-acf0-e11e77e21aa7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910624039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.910624039
Directory /workspace/71.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.3930622296
Short name T1512
Test name
Test status
Simulation time 5394901012 ps
CPU time 92.6 seconds
Started Aug 08 08:03:43 PM PDT 24
Finished Aug 08 08:05:15 PM PDT 24
Peak memory 573896 kb
Host smart-786551b2-2391-4128-8b3d-c8f06fe9017a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930622296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.3930622296
Directory /workspace/71.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.1448539243
Short name T1368
Test name
Test status
Simulation time 40742662 ps
CPU time 5.84 seconds
Started Aug 08 08:03:42 PM PDT 24
Finished Aug 08 08:03:48 PM PDT 24
Peak memory 573808 kb
Host smart-80ecc217-0969-459b-a85f-243020d1891e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448539243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay
s.1448539243
Directory /workspace/71.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all.25401748
Short name T2521
Test name
Test status
Simulation time 1612809371 ps
CPU time 117.15 seconds
Started Aug 08 08:03:40 PM PDT 24
Finished Aug 08 08:05:37 PM PDT 24
Peak memory 575856 kb
Host smart-b171774a-acc4-4067-b44e-663263f1b99d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25401748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.25401748
Directory /workspace/71.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.1822493622
Short name T618
Test name
Test status
Simulation time 4536824230 ps
CPU time 151.38 seconds
Started Aug 08 08:03:40 PM PDT 24
Finished Aug 08 08:06:11 PM PDT 24
Peak memory 576084 kb
Host smart-f6e962e8-47a3-469d-8089-7a3e4145e840
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822493622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.1822493622
Directory /workspace/71.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2955298733
Short name T452
Test name
Test status
Simulation time 1983279110 ps
CPU time 438.33 seconds
Started Aug 08 08:03:40 PM PDT 24
Finished Aug 08 08:10:58 PM PDT 24
Peak memory 576712 kb
Host smart-f04762c2-5008-44c7-a880-fa721c1f2b68
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955298733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all
_with_rand_reset.2955298733
Directory /workspace/71.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.4044090466
Short name T1436
Test name
Test status
Simulation time 151904931 ps
CPU time 31.55 seconds
Started Aug 08 08:03:41 PM PDT 24
Finished Aug 08 08:04:12 PM PDT 24
Peak memory 575856 kb
Host smart-87111194-7a4c-4260-8048-6cc2b7ec1627
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044090466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al
l_with_reset_error.4044090466
Directory /workspace/71.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.305628191
Short name T1852
Test name
Test status
Simulation time 327653132 ps
CPU time 16.15 seconds
Started Aug 08 08:03:40 PM PDT 24
Finished Aug 08 08:03:56 PM PDT 24
Peak memory 575972 kb
Host smart-d812625d-2514-4e55-b3a3-f6201777e32b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305628191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.305628191
Directory /workspace/71.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_access_same_device.2997675392
Short name T1722
Test name
Test status
Simulation time 279078150 ps
CPU time 17.72 seconds
Started Aug 08 08:04:03 PM PDT 24
Finished Aug 08 08:04:20 PM PDT 24
Peak memory 575864 kb
Host smart-07790aed-3eeb-4f91-8852-2f139dddc8ae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997675392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device
.2997675392
Directory /workspace/72.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.2178831996
Short name T2836
Test name
Test status
Simulation time 9544624568 ps
CPU time 165.3 seconds
Started Aug 08 08:04:01 PM PDT 24
Finished Aug 08 08:06:46 PM PDT 24
Peak memory 574580 kb
Host smart-1e8d73fa-22a6-4851-8d29-3294ef8699a6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178831996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_
device_slow_rsp.2178831996
Directory /workspace/72.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.136519581
Short name T1838
Test name
Test status
Simulation time 24457670 ps
CPU time 5.78 seconds
Started Aug 08 08:04:02 PM PDT 24
Finished Aug 08 08:04:08 PM PDT 24
Peak memory 573864 kb
Host smart-a0aadbe4-f433-4cf5-93bf-8da8ae6d7f1a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136519581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_addr
.136519581
Directory /workspace/72.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_error_random.1250824441
Short name T1456
Test name
Test status
Simulation time 337950414 ps
CPU time 24.7 seconds
Started Aug 08 08:03:58 PM PDT 24
Finished Aug 08 08:04:23 PM PDT 24
Peak memory 575856 kb
Host smart-cfd98663-bf77-4d87-9964-f87248db8905
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250824441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.1250824441
Directory /workspace/72.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random.1898577222
Short name T2490
Test name
Test status
Simulation time 169912195 ps
CPU time 18.34 seconds
Started Aug 08 08:04:00 PM PDT 24
Finished Aug 08 08:04:18 PM PDT 24
Peak memory 575720 kb
Host smart-9c08c7d6-1ebb-4ecd-8843-b5b400e304ab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898577222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.1898577222
Directory /workspace/72.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.4055526603
Short name T1437
Test name
Test status
Simulation time 50212446553 ps
CPU time 531.88 seconds
Started Aug 08 08:04:00 PM PDT 24
Finished Aug 08 08:12:52 PM PDT 24
Peak memory 576708 kb
Host smart-9919e4df-ed9c-4a16-9524-b8bf62cc6ece
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055526603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.4055526603
Directory /workspace/72.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.1716516454
Short name T1712
Test name
Test status
Simulation time 45494102969 ps
CPU time 803.08 seconds
Started Aug 08 08:04:00 PM PDT 24
Finished Aug 08 08:17:23 PM PDT 24
Peak memory 575896 kb
Host smart-f1fd5988-7752-4764-a639-5deecec1abe7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716516454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.1716516454
Directory /workspace/72.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.3301038856
Short name T2203
Test name
Test status
Simulation time 303543839 ps
CPU time 25.73 seconds
Started Aug 08 08:04:03 PM PDT 24
Finished Aug 08 08:04:29 PM PDT 24
Peak memory 575772 kb
Host smart-8fe11f48-5f71-4a5a-a228-958b5adce3df
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301038856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del
ays.3301038856
Directory /workspace/72.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_same_source.1199592540
Short name T2773
Test name
Test status
Simulation time 111670142 ps
CPU time 11.18 seconds
Started Aug 08 08:03:59 PM PDT 24
Finished Aug 08 08:04:11 PM PDT 24
Peak memory 575796 kb
Host smart-baebe8d0-3905-4d59-806d-5f22e3eaf418
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199592540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.1199592540
Directory /workspace/72.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke.934287876
Short name T2633
Test name
Test status
Simulation time 39790111 ps
CPU time 6.04 seconds
Started Aug 08 08:03:41 PM PDT 24
Finished Aug 08 08:03:47 PM PDT 24
Peak memory 574444 kb
Host smart-3bfa9bfa-7882-4db9-b40f-de2ceb1bdec4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934287876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.934287876
Directory /workspace/72.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.1465465043
Short name T1648
Test name
Test status
Simulation time 7034402831 ps
CPU time 75.59 seconds
Started Aug 08 08:03:42 PM PDT 24
Finished Aug 08 08:04:58 PM PDT 24
Peak memory 573932 kb
Host smart-78fded56-03a6-4b21-ae01-72228b0ca046
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465465043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.1465465043
Directory /workspace/72.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.2265720106
Short name T1584
Test name
Test status
Simulation time 4651482085 ps
CPU time 75.24 seconds
Started Aug 08 08:03:42 PM PDT 24
Finished Aug 08 08:04:57 PM PDT 24
Peak memory 573884 kb
Host smart-28fa81ab-c364-4701-9487-5d815a73b214
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265720106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.2265720106
Directory /workspace/72.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.2451157888
Short name T1472
Test name
Test status
Simulation time 40106587 ps
CPU time 6.03 seconds
Started Aug 08 08:03:42 PM PDT 24
Finished Aug 08 08:03:48 PM PDT 24
Peak memory 573816 kb
Host smart-2e69d226-91be-4035-8aeb-51aaafc00eeb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451157888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay
s.2451157888
Directory /workspace/72.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all.790824286
Short name T1670
Test name
Test status
Simulation time 1167851869 ps
CPU time 89.92 seconds
Started Aug 08 08:04:02 PM PDT 24
Finished Aug 08 08:05:32 PM PDT 24
Peak memory 575824 kb
Host smart-556d1bd9-d533-40a1-ac06-1ffe4fa6f5cd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790824286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.790824286
Directory /workspace/72.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.1266913216
Short name T2720
Test name
Test status
Simulation time 1823345591 ps
CPU time 64.63 seconds
Started Aug 08 08:04:01 PM PDT 24
Finished Aug 08 08:05:06 PM PDT 24
Peak memory 576072 kb
Host smart-efc56427-7223-4514-8d35-bf142bf552c3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266913216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.1266913216
Directory /workspace/72.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.3214393860
Short name T1999
Test name
Test status
Simulation time 109081349 ps
CPU time 45.11 seconds
Started Aug 08 08:04:00 PM PDT 24
Finished Aug 08 08:04:45 PM PDT 24
Peak memory 575912 kb
Host smart-81f92b4e-6736-4afe-b628-6cbd315ba850
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214393860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all
_with_rand_reset.3214393860
Directory /workspace/72.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.2380748976
Short name T574
Test name
Test status
Simulation time 2985828649 ps
CPU time 396.82 seconds
Started Aug 08 08:04:04 PM PDT 24
Finished Aug 08 08:10:41 PM PDT 24
Peak memory 576796 kb
Host smart-0d75865b-cade-435a-8ee3-93778fee0602
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380748976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al
l_with_reset_error.2380748976
Directory /workspace/72.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.2184035054
Short name T1546
Test name
Test status
Simulation time 866173451 ps
CPU time 38.51 seconds
Started Aug 08 08:04:00 PM PDT 24
Finished Aug 08 08:04:39 PM PDT 24
Peak memory 575828 kb
Host smart-0c11c100-88f2-47be-91f0-352fcddc2678
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184035054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.2184035054
Directory /workspace/72.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_access_same_device.2659393007
Short name T1620
Test name
Test status
Simulation time 390539564 ps
CPU time 39.63 seconds
Started Aug 08 08:04:01 PM PDT 24
Finished Aug 08 08:04:41 PM PDT 24
Peak memory 575960 kb
Host smart-7653688b-3a70-4aca-827b-2411becbdee1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659393007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device
.2659393007
Directory /workspace/73.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.1103148498
Short name T1654
Test name
Test status
Simulation time 37238747378 ps
CPU time 675.97 seconds
Started Aug 08 08:03:59 PM PDT 24
Finished Aug 08 08:15:15 PM PDT 24
Peak memory 575776 kb
Host smart-0b6a1b09-40bb-4bd0-87c2-d177939a7416
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103148498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_
device_slow_rsp.1103148498
Directory /workspace/73.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.3404193652
Short name T1933
Test name
Test status
Simulation time 976646744 ps
CPU time 35.51 seconds
Started Aug 08 08:04:02 PM PDT 24
Finished Aug 08 08:04:37 PM PDT 24
Peak memory 575868 kb
Host smart-abb6b0a9-d521-4508-9bb8-8c1ac7a8f11e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404193652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add
r.3404193652
Directory /workspace/73.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_error_random.2823378529
Short name T2008
Test name
Test status
Simulation time 798388065 ps
CPU time 29.07 seconds
Started Aug 08 08:03:59 PM PDT 24
Finished Aug 08 08:04:28 PM PDT 24
Peak memory 575680 kb
Host smart-f7690b6f-5281-4d3a-b153-aa487de4543e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823378529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.2823378529
Directory /workspace/73.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random.3335594987
Short name T2799
Test name
Test status
Simulation time 1536071925 ps
CPU time 53.56 seconds
Started Aug 08 08:04:00 PM PDT 24
Finished Aug 08 08:04:53 PM PDT 24
Peak memory 575904 kb
Host smart-71441b04-067d-4496-8d33-b72c9873a85a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335594987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.3335594987
Directory /workspace/73.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.1077939934
Short name T2192
Test name
Test status
Simulation time 64232325729 ps
CPU time 672.75 seconds
Started Aug 08 08:04:03 PM PDT 24
Finished Aug 08 08:15:16 PM PDT 24
Peak memory 575980 kb
Host smart-b1a9cbdf-1b58-48dc-95d4-54f6b01852fc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077939934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.1077939934
Directory /workspace/73.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.2729270574
Short name T2195
Test name
Test status
Simulation time 22249760748 ps
CPU time 381.77 seconds
Started Aug 08 08:03:59 PM PDT 24
Finished Aug 08 08:10:22 PM PDT 24
Peak memory 575856 kb
Host smart-dde904d6-1986-42c0-9e5d-a7a066349e71
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729270574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.2729270574
Directory /workspace/73.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.3946004783
Short name T2737
Test name
Test status
Simulation time 380343251 ps
CPU time 29.42 seconds
Started Aug 08 08:04:01 PM PDT 24
Finished Aug 08 08:04:31 PM PDT 24
Peak memory 575720 kb
Host smart-967a6b0f-37c0-4663-ba34-5cf8fdf1f5c4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946004783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del
ays.3946004783
Directory /workspace/73.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_same_source.1044333065
Short name T2261
Test name
Test status
Simulation time 517131471 ps
CPU time 34.45 seconds
Started Aug 08 08:04:00 PM PDT 24
Finished Aug 08 08:04:34 PM PDT 24
Peak memory 575888 kb
Host smart-13a55749-c4f9-4741-918b-a8c0f99a1b99
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044333065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.1044333065
Directory /workspace/73.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke.2635055503
Short name T1762
Test name
Test status
Simulation time 45879062 ps
CPU time 6.3 seconds
Started Aug 08 08:04:00 PM PDT 24
Finished Aug 08 08:04:06 PM PDT 24
Peak memory 573780 kb
Host smart-c0a897e4-7b34-42b0-8f31-c0679648f6ed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635055503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.2635055503
Directory /workspace/73.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.3346670673
Short name T2012
Test name
Test status
Simulation time 9000762029 ps
CPU time 93.09 seconds
Started Aug 08 08:04:02 PM PDT 24
Finished Aug 08 08:05:35 PM PDT 24
Peak memory 574608 kb
Host smart-c9d25829-8100-48d4-9f81-b3058df14117
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346670673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.3346670673
Directory /workspace/73.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1792489972
Short name T2791
Test name
Test status
Simulation time 3348740725 ps
CPU time 57.4 seconds
Started Aug 08 08:03:59 PM PDT 24
Finished Aug 08 08:04:57 PM PDT 24
Peak memory 573888 kb
Host smart-8235dd17-89c6-43c6-9541-4dff44745c82
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792489972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.1792489972
Directory /workspace/73.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.3553458386
Short name T1867
Test name
Test status
Simulation time 43765197 ps
CPU time 6.52 seconds
Started Aug 08 08:03:59 PM PDT 24
Finished Aug 08 08:04:06 PM PDT 24
Peak memory 573804 kb
Host smart-0aaeb5d0-69f2-4543-818a-10179c7a0d1a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553458386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay
s.3553458386
Directory /workspace/73.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all.3761042902
Short name T778
Test name
Test status
Simulation time 15341636518 ps
CPU time 686.2 seconds
Started Aug 08 08:03:59 PM PDT 24
Finished Aug 08 08:15:26 PM PDT 24
Peak memory 576352 kb
Host smart-01a3b10f-4dab-46f0-949f-3d62f5e13aa9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761042902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.3761042902
Directory /workspace/73.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.3844852615
Short name T1740
Test name
Test status
Simulation time 5558389139 ps
CPU time 186.44 seconds
Started Aug 08 08:04:01 PM PDT 24
Finished Aug 08 08:07:08 PM PDT 24
Peak memory 576076 kb
Host smart-2680c23f-df3c-47d2-8612-b2064eae6a9d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844852615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.3844852615
Directory /workspace/73.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.2406491280
Short name T2632
Test name
Test status
Simulation time 1060378864 ps
CPU time 253.27 seconds
Started Aug 08 08:03:59 PM PDT 24
Finished Aug 08 08:08:12 PM PDT 24
Peak memory 576680 kb
Host smart-c72c93d9-82f0-4e01-89c2-5b7477d0d47e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406491280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al
l_with_reset_error.2406491280
Directory /workspace/73.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.2598184509
Short name T2389
Test name
Test status
Simulation time 346404530 ps
CPU time 16.68 seconds
Started Aug 08 08:04:00 PM PDT 24
Finished Aug 08 08:04:16 PM PDT 24
Peak memory 575816 kb
Host smart-b946031a-693e-4ced-9e39-7e8524bbd5b7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598184509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.2598184509
Directory /workspace/73.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_access_same_device.2101602552
Short name T2886
Test name
Test status
Simulation time 853314788 ps
CPU time 33.43 seconds
Started Aug 08 08:04:13 PM PDT 24
Finished Aug 08 08:04:47 PM PDT 24
Peak memory 575952 kb
Host smart-129bac20-d479-4fe6-ba96-5b2f72d139ee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101602552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device
.2101602552
Directory /workspace/74.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.861749779
Short name T786
Test name
Test status
Simulation time 26296803463 ps
CPU time 471.67 seconds
Started Aug 08 08:04:12 PM PDT 24
Finished Aug 08 08:12:04 PM PDT 24
Peak memory 575940 kb
Host smart-cd7df402-c6af-4afd-be68-b185cad054fa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861749779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_d
evice_slow_rsp.861749779
Directory /workspace/74.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.2695617631
Short name T1403
Test name
Test status
Simulation time 235732695 ps
CPU time 22.17 seconds
Started Aug 08 08:04:16 PM PDT 24
Finished Aug 08 08:04:38 PM PDT 24
Peak memory 575712 kb
Host smart-8e26b12f-c76e-4219-8d33-3719bfd92eff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695617631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add
r.2695617631
Directory /workspace/74.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_error_random.135204439
Short name T1828
Test name
Test status
Simulation time 631288181 ps
CPU time 22.62 seconds
Started Aug 08 08:04:12 PM PDT 24
Finished Aug 08 08:04:35 PM PDT 24
Peak memory 575896 kb
Host smart-2c4ac5d3-0e77-4e58-a253-0aacd55b080c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135204439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.135204439
Directory /workspace/74.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random.2414019854
Short name T1412
Test name
Test status
Simulation time 379999335 ps
CPU time 16.65 seconds
Started Aug 08 08:04:13 PM PDT 24
Finished Aug 08 08:04:30 PM PDT 24
Peak memory 575920 kb
Host smart-f1c119bc-ea76-461b-aa10-101f8f38c509
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414019854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.2414019854
Directory /workspace/74.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.1002238856
Short name T2066
Test name
Test status
Simulation time 40612128843 ps
CPU time 462.2 seconds
Started Aug 08 08:04:14 PM PDT 24
Finished Aug 08 08:11:56 PM PDT 24
Peak memory 576044 kb
Host smart-af09600e-5401-431d-90de-95d6ab58a026
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002238856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.1002238856
Directory /workspace/74.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.2011115154
Short name T1821
Test name
Test status
Simulation time 3251732285 ps
CPU time 54.89 seconds
Started Aug 08 08:04:13 PM PDT 24
Finished Aug 08 08:05:08 PM PDT 24
Peak memory 574548 kb
Host smart-d7bc7515-212e-4161-98e1-df43f0eb8535
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011115154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.2011115154
Directory /workspace/74.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.412624172
Short name T2646
Test name
Test status
Simulation time 391336927 ps
CPU time 37.74 seconds
Started Aug 08 08:04:13 PM PDT 24
Finished Aug 08 08:04:51 PM PDT 24
Peak memory 575880 kb
Host smart-993555f8-e63f-41bc-bde8-eeeeab4a451e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412624172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_dela
ys.412624172
Directory /workspace/74.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_same_source.1973179365
Short name T466
Test name
Test status
Simulation time 489864635 ps
CPU time 37.9 seconds
Started Aug 08 08:04:13 PM PDT 24
Finished Aug 08 08:04:51 PM PDT 24
Peak memory 575820 kb
Host smart-874b8aba-93f0-4727-95ab-21c62d6d7da7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973179365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.1973179365
Directory /workspace/74.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke.3311146207
Short name T2824
Test name
Test status
Simulation time 51276171 ps
CPU time 6.62 seconds
Started Aug 08 08:04:00 PM PDT 24
Finished Aug 08 08:04:06 PM PDT 24
Peak memory 574500 kb
Host smart-00699136-1f65-4362-99ab-f01af3c8fa0a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311146207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.3311146207
Directory /workspace/74.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.2755623191
Short name T2160
Test name
Test status
Simulation time 9422475092 ps
CPU time 95.45 seconds
Started Aug 08 08:04:16 PM PDT 24
Finished Aug 08 08:05:52 PM PDT 24
Peak memory 574564 kb
Host smart-80d1e81f-bbb6-44bb-a6ee-77adc9009d93
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755623191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.2755623191
Directory /workspace/74.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.3761959247
Short name T2319
Test name
Test status
Simulation time 5462813392 ps
CPU time 98.58 seconds
Started Aug 08 08:04:13 PM PDT 24
Finished Aug 08 08:05:52 PM PDT 24
Peak memory 574508 kb
Host smart-cffe31c7-1042-4b43-80a3-e964e2974e5d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761959247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.3761959247
Directory /workspace/74.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.1642417039
Short name T2594
Test name
Test status
Simulation time 44205896 ps
CPU time 6.13 seconds
Started Aug 08 08:04:02 PM PDT 24
Finished Aug 08 08:04:08 PM PDT 24
Peak memory 573744 kb
Host smart-31f82e92-8659-4edf-91e6-51e93df5e74f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642417039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay
s.1642417039
Directory /workspace/74.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all.2316749296
Short name T472
Test name
Test status
Simulation time 10670997094 ps
CPU time 419.59 seconds
Started Aug 08 08:04:16 PM PDT 24
Finished Aug 08 08:11:16 PM PDT 24
Peak memory 575984 kb
Host smart-c0864b87-0208-4b3e-b260-78f5537ed882
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316749296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.2316749296
Directory /workspace/74.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.327318793
Short name T791
Test name
Test status
Simulation time 15735854550 ps
CPU time 480.7 seconds
Started Aug 08 08:04:14 PM PDT 24
Finished Aug 08 08:12:15 PM PDT 24
Peak memory 575932 kb
Host smart-ed6ed619-419e-41a2-a82f-457dacdbcfc1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327318793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.327318793
Directory /workspace/74.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.4116213878
Short name T2277
Test name
Test status
Simulation time 415287745 ps
CPU time 105.8 seconds
Started Aug 08 08:04:18 PM PDT 24
Finished Aug 08 08:06:04 PM PDT 24
Peak memory 575972 kb
Host smart-8a5a3721-9666-4f9c-b991-9588a4f433ed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116213878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all
_with_rand_reset.4116213878
Directory /workspace/74.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.1590468382
Short name T518
Test name
Test status
Simulation time 2476717320 ps
CPU time 219.92 seconds
Started Aug 08 08:04:17 PM PDT 24
Finished Aug 08 08:07:57 PM PDT 24
Peak memory 576716 kb
Host smart-54bbadee-4cd4-44a4-9bc0-a9ac21dc2dd5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590468382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al
l_with_reset_error.1590468382
Directory /workspace/74.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.3916715867
Short name T1414
Test name
Test status
Simulation time 258421281 ps
CPU time 29.18 seconds
Started Aug 08 08:04:14 PM PDT 24
Finished Aug 08 08:04:43 PM PDT 24
Peak memory 575796 kb
Host smart-86600343-e090-4fcc-aade-e211d431ae33
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916715867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.3916715867
Directory /workspace/74.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_access_same_device.401675811
Short name T1997
Test name
Test status
Simulation time 2714189291 ps
CPU time 116.8 seconds
Started Aug 08 08:04:15 PM PDT 24
Finished Aug 08 08:06:12 PM PDT 24
Peak memory 576032 kb
Host smart-3f35139b-2751-4990-adf4-57558070192b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401675811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device.
401675811
Directory /workspace/75.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1469440076
Short name T2825
Test name
Test status
Simulation time 152786439767 ps
CPU time 2629.12 seconds
Started Aug 08 08:04:23 PM PDT 24
Finished Aug 08 08:48:13 PM PDT 24
Peak memory 575956 kb
Host smart-0e54882c-626b-4821-b9e5-1e53f5271cfb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469440076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_
device_slow_rsp.1469440076
Directory /workspace/75.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.1194366048
Short name T1675
Test name
Test status
Simulation time 614074644 ps
CPU time 25.87 seconds
Started Aug 08 08:04:28 PM PDT 24
Finished Aug 08 08:04:54 PM PDT 24
Peak memory 575912 kb
Host smart-3cf508d0-e990-4425-a4cb-be8412b5108f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194366048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add
r.1194366048
Directory /workspace/75.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_error_random.1010515424
Short name T1978
Test name
Test status
Simulation time 1402458182 ps
CPU time 46.53 seconds
Started Aug 08 08:04:32 PM PDT 24
Finished Aug 08 08:05:18 PM PDT 24
Peak memory 575884 kb
Host smart-9f4399ae-2a01-44cd-a2b9-4b2825937fea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010515424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.1010515424
Directory /workspace/75.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random.3344200743
Short name T2070
Test name
Test status
Simulation time 156417918 ps
CPU time 16.71 seconds
Started Aug 08 08:04:14 PM PDT 24
Finished Aug 08 08:04:31 PM PDT 24
Peak memory 575916 kb
Host smart-d86ca938-6d64-4b58-9e53-fe154c9ef9a8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344200743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.3344200743
Directory /workspace/75.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.3220334589
Short name T1590
Test name
Test status
Simulation time 62673413223 ps
CPU time 677.46 seconds
Started Aug 08 08:04:23 PM PDT 24
Finished Aug 08 08:15:40 PM PDT 24
Peak memory 576040 kb
Host smart-88d00770-a363-4b8d-9c58-26f8350b51c9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220334589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.3220334589
Directory /workspace/75.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.3347778714
Short name T2810
Test name
Test status
Simulation time 16102232202 ps
CPU time 284.04 seconds
Started Aug 08 08:04:15 PM PDT 24
Finished Aug 08 08:08:59 PM PDT 24
Peak memory 575980 kb
Host smart-b356ea4e-567e-4a9e-a707-dd98cc8e07d8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347778714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.3347778714
Directory /workspace/75.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.1961244332
Short name T1770
Test name
Test status
Simulation time 63922627 ps
CPU time 8.34 seconds
Started Aug 08 08:04:17 PM PDT 24
Finished Aug 08 08:04:25 PM PDT 24
Peak memory 575888 kb
Host smart-f3b5ed7b-5b72-4e36-9702-a3514c1236e6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961244332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del
ays.1961244332
Directory /workspace/75.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_same_source.3557766521
Short name T1660
Test name
Test status
Simulation time 524878153 ps
CPU time 35.5 seconds
Started Aug 08 08:04:13 PM PDT 24
Finished Aug 08 08:04:49 PM PDT 24
Peak memory 575900 kb
Host smart-430824bc-7067-43e0-a3cd-cfdbca32d3a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557766521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.3557766521
Directory /workspace/75.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke.3071563480
Short name T1856
Test name
Test status
Simulation time 180321709 ps
CPU time 8.72 seconds
Started Aug 08 08:04:23 PM PDT 24
Finished Aug 08 08:04:32 PM PDT 24
Peak memory 573848 kb
Host smart-e5f07d51-2bd9-4452-ba86-4a23c57578c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071563480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.3071563480
Directory /workspace/75.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.2547671222
Short name T2220
Test name
Test status
Simulation time 5898351910 ps
CPU time 58.92 seconds
Started Aug 08 08:04:18 PM PDT 24
Finished Aug 08 08:05:17 PM PDT 24
Peak memory 573940 kb
Host smart-b77c6674-3084-4ab2-a681-4b1ae42796ee
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547671222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.2547671222
Directory /workspace/75.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.1206482935
Short name T1485
Test name
Test status
Simulation time 5697264967 ps
CPU time 93.32 seconds
Started Aug 08 08:04:14 PM PDT 24
Finished Aug 08 08:05:48 PM PDT 24
Peak memory 573824 kb
Host smart-ea26db19-94fb-4289-8cdd-dcc614fe178b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206482935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.1206482935
Directory /workspace/75.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.3166620897
Short name T1730
Test name
Test status
Simulation time 41588276 ps
CPU time 5.94 seconds
Started Aug 08 08:04:18 PM PDT 24
Finished Aug 08 08:04:24 PM PDT 24
Peak memory 573836 kb
Host smart-95b5d140-fd48-477d-a1b1-903e17f5f625
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166620897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay
s.3166620897
Directory /workspace/75.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all.942835822
Short name T496
Test name
Test status
Simulation time 11703919692 ps
CPU time 376.37 seconds
Started Aug 08 08:04:28 PM PDT 24
Finished Aug 08 08:10:44 PM PDT 24
Peak memory 576724 kb
Host smart-873a3a61-5397-4569-9878-185bec43dc4f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942835822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.942835822
Directory /workspace/75.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.2183928452
Short name T1655
Test name
Test status
Simulation time 12483461985 ps
CPU time 482.84 seconds
Started Aug 08 08:04:28 PM PDT 24
Finished Aug 08 08:12:32 PM PDT 24
Peak memory 576736 kb
Host smart-f292335c-94d8-4c78-809e-94a241cd8368
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183928452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.2183928452
Directory /workspace/75.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.2788658983
Short name T839
Test name
Test status
Simulation time 8982980951 ps
CPU time 411.07 seconds
Started Aug 08 08:04:28 PM PDT 24
Finished Aug 08 08:11:19 PM PDT 24
Peak memory 575968 kb
Host smart-36d6e798-a199-41e3-a0b0-f1180e994648
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788658983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all
_with_rand_reset.2788658983
Directory /workspace/75.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.4044131171
Short name T2411
Test name
Test status
Simulation time 2037950719 ps
CPU time 160.39 seconds
Started Aug 08 08:04:28 PM PDT 24
Finished Aug 08 08:07:08 PM PDT 24
Peak memory 575784 kb
Host smart-586404f7-f22a-4060-85fa-2c1be8881175
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044131171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al
l_with_reset_error.4044131171
Directory /workspace/75.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.3985244098
Short name T2402
Test name
Test status
Simulation time 101604677 ps
CPU time 14.53 seconds
Started Aug 08 08:04:27 PM PDT 24
Finished Aug 08 08:04:42 PM PDT 24
Peak memory 575868 kb
Host smart-e5914a04-8e76-43ba-8526-79c07fd3274c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985244098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.3985244098
Directory /workspace/75.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_access_same_device.1102483680
Short name T1638
Test name
Test status
Simulation time 341846757 ps
CPU time 35.3 seconds
Started Aug 08 08:04:38 PM PDT 24
Finished Aug 08 08:05:13 PM PDT 24
Peak memory 575928 kb
Host smart-592125dc-74d9-44b8-a45a-ef91104bb0c3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102483680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device
.1102483680
Directory /workspace/76.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.2588985817
Short name T2042
Test name
Test status
Simulation time 111233089194 ps
CPU time 2074.58 seconds
Started Aug 08 08:04:27 PM PDT 24
Finished Aug 08 08:39:02 PM PDT 24
Peak memory 574708 kb
Host smart-2b59ddc3-e307-4d82-a33b-54e709bdc5f4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588985817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_
device_slow_rsp.2588985817
Directory /workspace/76.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.1346830598
Short name T2465
Test name
Test status
Simulation time 917962130 ps
CPU time 34.41 seconds
Started Aug 08 08:04:30 PM PDT 24
Finished Aug 08 08:05:04 PM PDT 24
Peak memory 575852 kb
Host smart-beb431d0-f5e0-495b-81aa-6d9c05d2e131
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346830598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add
r.1346830598
Directory /workspace/76.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_error_random.2690041464
Short name T1736
Test name
Test status
Simulation time 242630070 ps
CPU time 22.23 seconds
Started Aug 08 08:04:27 PM PDT 24
Finished Aug 08 08:04:49 PM PDT 24
Peak memory 575896 kb
Host smart-f0b1d6aa-1473-4707-b1f5-670c864a4810
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690041464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.2690041464
Directory /workspace/76.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random.4267922365
Short name T2796
Test name
Test status
Simulation time 247490161 ps
CPU time 25.41 seconds
Started Aug 08 08:04:28 PM PDT 24
Finished Aug 08 08:04:54 PM PDT 24
Peak memory 575756 kb
Host smart-d328d925-5143-4e55-882c-2d824d07d808
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267922365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.4267922365
Directory /workspace/76.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.1406513008
Short name T1617
Test name
Test status
Simulation time 55471614340 ps
CPU time 559.93 seconds
Started Aug 08 08:04:27 PM PDT 24
Finished Aug 08 08:13:47 PM PDT 24
Peak memory 576044 kb
Host smart-d032a3a0-9939-4e0a-95a9-112f5f1a2dcc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406513008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.1406513008
Directory /workspace/76.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.1276586298
Short name T2599
Test name
Test status
Simulation time 64055445826 ps
CPU time 1207.77 seconds
Started Aug 08 08:04:31 PM PDT 24
Finished Aug 08 08:24:39 PM PDT 24
Peak memory 576048 kb
Host smart-f76abc13-21e2-4608-81e3-ac2e8ee1066b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276586298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.1276586298
Directory /workspace/76.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.3597347255
Short name T1464
Test name
Test status
Simulation time 111809817 ps
CPU time 12.35 seconds
Started Aug 08 08:04:29 PM PDT 24
Finished Aug 08 08:04:42 PM PDT 24
Peak memory 575828 kb
Host smart-b7ee56e6-a292-4445-8444-5cc4e3a0b84f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597347255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del
ays.3597347255
Directory /workspace/76.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_same_source.3775838391
Short name T561
Test name
Test status
Simulation time 1116212785 ps
CPU time 35.83 seconds
Started Aug 08 08:04:38 PM PDT 24
Finished Aug 08 08:05:14 PM PDT 24
Peak memory 575748 kb
Host smart-a01ef79c-73b3-491f-aed5-47e06c191a73
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775838391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.3775838391
Directory /workspace/76.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke.308469564
Short name T1581
Test name
Test status
Simulation time 204567257 ps
CPU time 9.04 seconds
Started Aug 08 08:04:28 PM PDT 24
Finished Aug 08 08:04:38 PM PDT 24
Peak memory 573824 kb
Host smart-afa2183b-2a99-48fe-9264-ad8c8941b7ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308469564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.308469564
Directory /workspace/76.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.1100291327
Short name T2046
Test name
Test status
Simulation time 9865659510 ps
CPU time 99.92 seconds
Started Aug 08 08:04:27 PM PDT 24
Finished Aug 08 08:06:08 PM PDT 24
Peak memory 573936 kb
Host smart-a9d4a356-bcbc-4fd8-894b-23f416221024
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100291327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.1100291327
Directory /workspace/76.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.3356020238
Short name T1876
Test name
Test status
Simulation time 6123758356 ps
CPU time 105.53 seconds
Started Aug 08 08:04:38 PM PDT 24
Finished Aug 08 08:06:23 PM PDT 24
Peak memory 573880 kb
Host smart-6eafd883-89df-474e-bf85-a9fe132a57e2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356020238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.3356020238
Directory /workspace/76.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.307546178
Short name T1592
Test name
Test status
Simulation time 59270729 ps
CPU time 6.72 seconds
Started Aug 08 08:04:32 PM PDT 24
Finished Aug 08 08:04:39 PM PDT 24
Peak memory 574492 kb
Host smart-dac38807-8a3c-4d8e-8216-4fa84cf4f6bf
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307546178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays
.307546178
Directory /workspace/76.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all.3312810932
Short name T1780
Test name
Test status
Simulation time 6033908754 ps
CPU time 207.14 seconds
Started Aug 08 08:04:28 PM PDT 24
Finished Aug 08 08:07:55 PM PDT 24
Peak memory 575976 kb
Host smart-918ba62e-34d8-4c3a-a6b8-a1a2b13d1c7b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312810932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.3312810932
Directory /workspace/76.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.2609673354
Short name T2215
Test name
Test status
Simulation time 3024083725 ps
CPU time 268.04 seconds
Started Aug 08 08:04:28 PM PDT 24
Finished Aug 08 08:08:57 PM PDT 24
Peak memory 576112 kb
Host smart-47bfde57-c997-461d-a4ab-ca8da4b7c4fc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609673354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.2609673354
Directory /workspace/76.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.807765871
Short name T2565
Test name
Test status
Simulation time 2637986568 ps
CPU time 326.92 seconds
Started Aug 08 08:04:38 PM PDT 24
Finished Aug 08 08:10:05 PM PDT 24
Peak memory 576764 kb
Host smart-8e1fded3-5ef1-49b5-bf87-2af6965cde6f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807765871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_
with_rand_reset.807765871
Directory /workspace/76.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.726293812
Short name T2696
Test name
Test status
Simulation time 10655577804 ps
CPU time 460.18 seconds
Started Aug 08 08:04:41 PM PDT 24
Finished Aug 08 08:12:21 PM PDT 24
Peak memory 576804 kb
Host smart-aad3a8dd-14de-440b-80a4-97e25318bcfb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726293812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all
_with_reset_error.726293812
Directory /workspace/76.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.1674411841
Short name T2909
Test name
Test status
Simulation time 179104276 ps
CPU time 22.48 seconds
Started Aug 08 08:04:27 PM PDT 24
Finished Aug 08 08:04:50 PM PDT 24
Peak memory 575940 kb
Host smart-528a75bb-4191-4a3b-afad-3fbdcf2f0330
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674411841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.1674411841
Directory /workspace/76.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_access_same_device.4129654904
Short name T2634
Test name
Test status
Simulation time 1330798337 ps
CPU time 54.79 seconds
Started Aug 08 08:04:41 PM PDT 24
Finished Aug 08 08:05:36 PM PDT 24
Peak memory 575732 kb
Host smart-d984bdb2-72b9-42a1-95ec-bbb7cfb3bec6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129654904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device
.4129654904
Directory /workspace/77.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.981146039
Short name T2721
Test name
Test status
Simulation time 139245250501 ps
CPU time 2450.36 seconds
Started Aug 08 08:04:40 PM PDT 24
Finished Aug 08 08:45:31 PM PDT 24
Peak memory 576036 kb
Host smart-b5d72873-d08b-4db7-85ae-d8adab611af9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981146039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_d
evice_slow_rsp.981146039
Directory /workspace/77.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3257239699
Short name T2204
Test name
Test status
Simulation time 31791825 ps
CPU time 6.24 seconds
Started Aug 08 08:04:39 PM PDT 24
Finished Aug 08 08:04:46 PM PDT 24
Peak memory 573876 kb
Host smart-e536e02d-cd27-4ee8-83e8-439235f7541c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257239699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add
r.3257239699
Directory /workspace/77.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_error_random.797451264
Short name T2399
Test name
Test status
Simulation time 457631973 ps
CPU time 17.89 seconds
Started Aug 08 08:04:39 PM PDT 24
Finished Aug 08 08:04:57 PM PDT 24
Peak memory 575916 kb
Host smart-3ac18647-62b2-4422-8682-fe4b92a90a84
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797451264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.797451264
Directory /workspace/77.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random.1904130194
Short name T1611
Test name
Test status
Simulation time 165226724 ps
CPU time 17.17 seconds
Started Aug 08 08:04:40 PM PDT 24
Finished Aug 08 08:04:58 PM PDT 24
Peak memory 575856 kb
Host smart-2c84bb43-cd2d-4197-93ce-2b869c84ccea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904130194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.1904130194
Directory /workspace/77.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.183087259
Short name T2433
Test name
Test status
Simulation time 90172334783 ps
CPU time 996.1 seconds
Started Aug 08 08:04:38 PM PDT 24
Finished Aug 08 08:21:15 PM PDT 24
Peak memory 575856 kb
Host smart-92e31876-4c63-4306-b88a-c23c97727127
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183087259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.183087259
Directory /workspace/77.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.525368995
Short name T2693
Test name
Test status
Simulation time 35335877697 ps
CPU time 559.47 seconds
Started Aug 08 08:04:38 PM PDT 24
Finished Aug 08 08:13:58 PM PDT 24
Peak memory 575936 kb
Host smart-95c05c65-8de8-45e7-bee0-c2c77c07785d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525368995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.525368995
Directory /workspace/77.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.1246711848
Short name T2832
Test name
Test status
Simulation time 363713788 ps
CPU time 28.76 seconds
Started Aug 08 08:04:43 PM PDT 24
Finished Aug 08 08:05:12 PM PDT 24
Peak memory 575848 kb
Host smart-d778e23b-df2a-47ba-b8f4-f04eae604ad0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246711848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del
ays.1246711848
Directory /workspace/77.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_same_source.3057704423
Short name T1636
Test name
Test status
Simulation time 216342603 ps
CPU time 8.95 seconds
Started Aug 08 08:04:43 PM PDT 24
Finished Aug 08 08:04:52 PM PDT 24
Peak memory 574492 kb
Host smart-01ccb72b-18e0-4ef5-9a6f-ab58ef06eae0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057704423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.3057704423
Directory /workspace/77.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke.539740815
Short name T2572
Test name
Test status
Simulation time 249227663 ps
CPU time 9.97 seconds
Started Aug 08 08:04:39 PM PDT 24
Finished Aug 08 08:04:49 PM PDT 24
Peak memory 573808 kb
Host smart-8f4646f8-5315-44a0-a2c3-08deecb28e72
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539740815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.539740815
Directory /workspace/77.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.2227675179
Short name T2641
Test name
Test status
Simulation time 10341813452 ps
CPU time 109.24 seconds
Started Aug 08 08:04:40 PM PDT 24
Finished Aug 08 08:06:29 PM PDT 24
Peak memory 573872 kb
Host smart-fc4abb3e-d4a2-4d32-b6d4-06dfdf97cf02
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227675179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.2227675179
Directory /workspace/77.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1293031569
Short name T1405
Test name
Test status
Simulation time 4517269727 ps
CPU time 78.54 seconds
Started Aug 08 08:04:42 PM PDT 24
Finished Aug 08 08:06:01 PM PDT 24
Peak memory 573892 kb
Host smart-acc836dc-f510-4021-80c5-427db64a000c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293031569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.1293031569
Directory /workspace/77.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.2095460979
Short name T2534
Test name
Test status
Simulation time 60316021 ps
CPU time 6.63 seconds
Started Aug 08 08:04:40 PM PDT 24
Finished Aug 08 08:04:46 PM PDT 24
Peak memory 573780 kb
Host smart-7796888c-a7a4-4304-bd52-045f295926d2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095460979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay
s.2095460979
Directory /workspace/77.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all.2830836029
Short name T477
Test name
Test status
Simulation time 1528688358 ps
CPU time 112.28 seconds
Started Aug 08 08:04:40 PM PDT 24
Finished Aug 08 08:06:33 PM PDT 24
Peak memory 576704 kb
Host smart-db251bb4-6db3-41e2-89a4-a9578059a4f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830836029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.2830836029
Directory /workspace/77.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.2827031215
Short name T2912
Test name
Test status
Simulation time 1701697845 ps
CPU time 129.44 seconds
Started Aug 08 08:04:42 PM PDT 24
Finished Aug 08 08:06:52 PM PDT 24
Peak memory 576240 kb
Host smart-69f67532-a273-498e-9675-5fd97f7aceb7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827031215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.2827031215
Directory /workspace/77.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.3722289936
Short name T1899
Test name
Test status
Simulation time 420085342 ps
CPU time 188.68 seconds
Started Aug 08 08:04:39 PM PDT 24
Finished Aug 08 08:07:47 PM PDT 24
Peak memory 575924 kb
Host smart-48d735a3-7650-41fe-a987-f3ef6dedf65b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722289936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all
_with_rand_reset.3722289936
Directory /workspace/77.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.2919348297
Short name T788
Test name
Test status
Simulation time 12043398231 ps
CPU time 734.65 seconds
Started Aug 08 08:04:42 PM PDT 24
Finished Aug 08 08:16:57 PM PDT 24
Peak memory 579068 kb
Host smart-82a7eb84-7ff2-439d-b88c-68bff34d0e54
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919348297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al
l_with_reset_error.2919348297
Directory /workspace/77.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.1533210351
Short name T2515
Test name
Test status
Simulation time 585854286 ps
CPU time 27.07 seconds
Started Aug 08 08:04:40 PM PDT 24
Finished Aug 08 08:05:07 PM PDT 24
Peak memory 575984 kb
Host smart-73e8e53b-309d-4937-86fd-e1fc2c47668c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533210351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.1533210351
Directory /workspace/77.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_access_same_device.2079255592
Short name T2346
Test name
Test status
Simulation time 717286019 ps
CPU time 55.22 seconds
Started Aug 08 08:04:40 PM PDT 24
Finished Aug 08 08:05:35 PM PDT 24
Peak memory 575856 kb
Host smart-a6e8a3de-3f8f-45e3-958a-b823674442eb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079255592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device
.2079255592
Directory /workspace/78.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2171209078
Short name T1691
Test name
Test status
Simulation time 22773413475 ps
CPU time 395.32 seconds
Started Aug 08 08:04:40 PM PDT 24
Finished Aug 08 08:11:15 PM PDT 24
Peak memory 576692 kb
Host smart-14aec191-99c2-4e1e-ac51-8e7b29d81c64
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171209078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_
device_slow_rsp.2171209078
Directory /workspace/78.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.2548770093
Short name T2747
Test name
Test status
Simulation time 591879075 ps
CPU time 23.54 seconds
Started Aug 08 08:05:05 PM PDT 24
Finished Aug 08 08:05:29 PM PDT 24
Peak memory 575880 kb
Host smart-2409d8e8-54f0-491f-b11d-9f884d200d6b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548770093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add
r.2548770093
Directory /workspace/78.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_error_random.2810450951
Short name T2186
Test name
Test status
Simulation time 1059139714 ps
CPU time 36.36 seconds
Started Aug 08 08:05:08 PM PDT 24
Finished Aug 08 08:05:45 PM PDT 24
Peak memory 575808 kb
Host smart-22665610-2092-43e9-b82a-383ce8d347a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810450951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.2810450951
Directory /workspace/78.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random.197872030
Short name T2299
Test name
Test status
Simulation time 1029388349 ps
CPU time 33.8 seconds
Started Aug 08 08:04:39 PM PDT 24
Finished Aug 08 08:05:13 PM PDT 24
Peak memory 575920 kb
Host smart-ef343d92-69da-4a52-840c-3a7fece0e533
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197872030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.197872030
Directory /workspace/78.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.889447479
Short name T1764
Test name
Test status
Simulation time 22516902336 ps
CPU time 246.53 seconds
Started Aug 08 08:04:39 PM PDT 24
Finished Aug 08 08:08:46 PM PDT 24
Peak memory 575860 kb
Host smart-c61b1af7-39bd-472f-9592-0d6a34a9c1a2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889447479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.889447479
Directory /workspace/78.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.788015612
Short name T2428
Test name
Test status
Simulation time 35585726462 ps
CPU time 528.36 seconds
Started Aug 08 08:04:42 PM PDT 24
Finished Aug 08 08:13:31 PM PDT 24
Peak memory 576028 kb
Host smart-602fae7f-42bd-4429-8169-27f8399a8241
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788015612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.788015612
Directory /workspace/78.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.1577933256
Short name T1378
Test name
Test status
Simulation time 243095735 ps
CPU time 22.32 seconds
Started Aug 08 08:04:39 PM PDT 24
Finished Aug 08 08:05:02 PM PDT 24
Peak memory 575844 kb
Host smart-b45e51c3-eb7b-4076-97f1-b3980c99c19a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577933256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del
ays.1577933256
Directory /workspace/78.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_same_source.2831974599
Short name T2560
Test name
Test status
Simulation time 2264196837 ps
CPU time 67.4 seconds
Started Aug 08 08:04:40 PM PDT 24
Finished Aug 08 08:05:48 PM PDT 24
Peak memory 575948 kb
Host smart-d52a34fd-db7b-493d-bff3-31cf928b6370
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831974599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.2831974599
Directory /workspace/78.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke.2428114233
Short name T1939
Test name
Test status
Simulation time 50698642 ps
CPU time 6.54 seconds
Started Aug 08 08:04:40 PM PDT 24
Finished Aug 08 08:04:46 PM PDT 24
Peak memory 573808 kb
Host smart-0563d4da-1a93-4f95-a446-06daab2bf2f1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428114233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.2428114233
Directory /workspace/78.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.1592798488
Short name T1580
Test name
Test status
Simulation time 6861466930 ps
CPU time 74.37 seconds
Started Aug 08 08:04:40 PM PDT 24
Finished Aug 08 08:05:54 PM PDT 24
Peak memory 573880 kb
Host smart-9f203749-5608-446a-9b25-89486ebf99ed
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592798488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.1592798488
Directory /workspace/78.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.1249871877
Short name T1745
Test name
Test status
Simulation time 5129694532 ps
CPU time 77.55 seconds
Started Aug 08 08:04:39 PM PDT 24
Finished Aug 08 08:05:57 PM PDT 24
Peak memory 574572 kb
Host smart-9278cd7a-2556-415f-a8b2-aa05d39aa1f8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249871877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.1249871877
Directory /workspace/78.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.1970648151
Short name T1441
Test name
Test status
Simulation time 45106483 ps
CPU time 6.47 seconds
Started Aug 08 08:04:41 PM PDT 24
Finished Aug 08 08:04:47 PM PDT 24
Peak memory 574428 kb
Host smart-c30ff6c6-73e5-4f4d-8dc9-c0bd9dff0545
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970648151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay
s.1970648151
Directory /workspace/78.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all.2913149233
Short name T2179
Test name
Test status
Simulation time 3539218864 ps
CPU time 117.67 seconds
Started Aug 08 08:05:09 PM PDT 24
Finished Aug 08 08:07:06 PM PDT 24
Peak memory 575888 kb
Host smart-d236b5ae-ea18-43fe-b9c8-474e7d0fc683
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913149233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.2913149233
Directory /workspace/78.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.224682248
Short name T1911
Test name
Test status
Simulation time 9182036324 ps
CPU time 329.14 seconds
Started Aug 08 08:05:04 PM PDT 24
Finished Aug 08 08:10:34 PM PDT 24
Peak memory 576116 kb
Host smart-4244de79-627a-499d-86e4-c0fee9c2c2b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224682248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.224682248
Directory /workspace/78.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.81344672
Short name T2330
Test name
Test status
Simulation time 10679337960 ps
CPU time 649.1 seconds
Started Aug 08 08:05:04 PM PDT 24
Finished Aug 08 08:15:54 PM PDT 24
Peak memory 576796 kb
Host smart-c84f84bd-98e4-4f89-849e-b857f2b64686
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81344672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_w
ith_rand_reset.81344672
Directory /workspace/78.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1020856538
Short name T1687
Test name
Test status
Simulation time 5986238114 ps
CPU time 344.85 seconds
Started Aug 08 08:05:05 PM PDT 24
Finished Aug 08 08:10:50 PM PDT 24
Peak memory 575908 kb
Host smart-228871f5-13fd-4afd-90dc-fcb77d261f99
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020856538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al
l_with_reset_error.1020856538
Directory /workspace/78.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.2400084970
Short name T658
Test name
Test status
Simulation time 289272193 ps
CPU time 14.58 seconds
Started Aug 08 08:05:06 PM PDT 24
Finished Aug 08 08:05:21 PM PDT 24
Peak memory 575812 kb
Host smart-ba772049-d0eb-4798-b10b-01ab720d17ac
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400084970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.2400084970
Directory /workspace/78.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_access_same_device.2201032777
Short name T1888
Test name
Test status
Simulation time 251640620 ps
CPU time 12.55 seconds
Started Aug 08 08:05:04 PM PDT 24
Finished Aug 08 08:05:17 PM PDT 24
Peak memory 574476 kb
Host smart-10bf826c-001e-44b3-86ab-9ae47bf8e6a4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201032777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device
.2201032777
Directory /workspace/79.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.480896575
Short name T795
Test name
Test status
Simulation time 80100830364 ps
CPU time 1540.55 seconds
Started Aug 08 08:05:06 PM PDT 24
Finished Aug 08 08:30:47 PM PDT 24
Peak memory 575996 kb
Host smart-38c39632-cee4-49f1-94f5-bc66917ba555
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480896575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_d
evice_slow_rsp.480896575
Directory /workspace/79.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.723178419
Short name T2637
Test name
Test status
Simulation time 76881502 ps
CPU time 10.3 seconds
Started Aug 08 08:05:05 PM PDT 24
Finished Aug 08 08:05:15 PM PDT 24
Peak memory 575740 kb
Host smart-3e78bc3d-de51-4bb2-8cdc-10d81bc9e631
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723178419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_addr
.723178419
Directory /workspace/79.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_error_random.175729360
Short name T2510
Test name
Test status
Simulation time 2159763944 ps
CPU time 83.51 seconds
Started Aug 08 08:05:07 PM PDT 24
Finished Aug 08 08:06:31 PM PDT 24
Peak memory 575968 kb
Host smart-da6dcf76-2feb-4f8f-a066-03e2fe14de48
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175729360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.175729360
Directory /workspace/79.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random.655989492
Short name T2406
Test name
Test status
Simulation time 2131730601 ps
CPU time 76.33 seconds
Started Aug 08 08:05:05 PM PDT 24
Finished Aug 08 08:06:22 PM PDT 24
Peak memory 575752 kb
Host smart-42ce929a-def1-4680-87ab-ac1c89080c4d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655989492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.655989492
Directory /workspace/79.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.2686140414
Short name T2898
Test name
Test status
Simulation time 104432992924 ps
CPU time 1121.75 seconds
Started Aug 08 08:05:05 PM PDT 24
Finished Aug 08 08:23:47 PM PDT 24
Peak memory 575876 kb
Host smart-f8cb2c3a-d794-4cc3-94ee-9a28c99e4d39
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686140414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.2686140414
Directory /workspace/79.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.2424774342
Short name T474
Test name
Test status
Simulation time 41172019010 ps
CPU time 737.09 seconds
Started Aug 08 08:05:06 PM PDT 24
Finished Aug 08 08:17:24 PM PDT 24
Peak memory 575840 kb
Host smart-cb712170-df46-4c79-8d5f-3c5423fdd814
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424774342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.2424774342
Directory /workspace/79.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.584571813
Short name T1994
Test name
Test status
Simulation time 306635279 ps
CPU time 29.22 seconds
Started Aug 08 08:05:06 PM PDT 24
Finished Aug 08 08:05:35 PM PDT 24
Peak memory 575892 kb
Host smart-22b047b5-e8fe-4a6d-8965-424e9e30db77
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584571813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_dela
ys.584571813
Directory /workspace/79.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_same_source.3047293848
Short name T2336
Test name
Test status
Simulation time 580481722 ps
CPU time 41.81 seconds
Started Aug 08 08:05:04 PM PDT 24
Finished Aug 08 08:05:46 PM PDT 24
Peak memory 575840 kb
Host smart-1aebcfbf-8d1b-4b6f-b61c-7598c96e39af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047293848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.3047293848
Directory /workspace/79.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke.3505776817
Short name T2092
Test name
Test status
Simulation time 233850433 ps
CPU time 10.05 seconds
Started Aug 08 08:05:04 PM PDT 24
Finished Aug 08 08:05:14 PM PDT 24
Peak memory 574460 kb
Host smart-14b71038-62c3-41ea-bfd4-5740ea34cabe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505776817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.3505776817
Directory /workspace/79.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.246968461
Short name T2932
Test name
Test status
Simulation time 7525765976 ps
CPU time 77.56 seconds
Started Aug 08 08:05:05 PM PDT 24
Finished Aug 08 08:06:23 PM PDT 24
Peak memory 574596 kb
Host smart-241ca033-7bf7-4d57-a78f-4da8639e358d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246968461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.246968461
Directory /workspace/79.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.1667524324
Short name T1669
Test name
Test status
Simulation time 5170654113 ps
CPU time 90.41 seconds
Started Aug 08 08:05:05 PM PDT 24
Finished Aug 08 08:06:35 PM PDT 24
Peak memory 573908 kb
Host smart-ee6ee1ab-4baa-4775-b8f8-f715ccf4e744
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667524324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.1667524324
Directory /workspace/79.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.2002956093
Short name T1906
Test name
Test status
Simulation time 41069389 ps
CPU time 6.41 seconds
Started Aug 08 08:05:05 PM PDT 24
Finished Aug 08 08:05:12 PM PDT 24
Peak memory 573760 kb
Host smart-937bd10e-4714-4ced-96c6-50700fa8179c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002956093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay
s.2002956093
Directory /workspace/79.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all.1834046342
Short name T2106
Test name
Test status
Simulation time 8436115639 ps
CPU time 344.7 seconds
Started Aug 08 08:05:05 PM PDT 24
Finished Aug 08 08:10:50 PM PDT 24
Peak memory 575916 kb
Host smart-2cd65af9-4fa3-482c-ac5a-4118e77b2e82
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834046342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.1834046342
Directory /workspace/79.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.2936067886
Short name T1789
Test name
Test status
Simulation time 2677014802 ps
CPU time 197.13 seconds
Started Aug 08 08:05:06 PM PDT 24
Finished Aug 08 08:08:23 PM PDT 24
Peak memory 575960 kb
Host smart-f41fa32d-df9d-45e8-be26-b30ce1007577
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936067886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.2936067886
Directory /workspace/79.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.2138327845
Short name T2107
Test name
Test status
Simulation time 7621962884 ps
CPU time 316.45 seconds
Started Aug 08 08:05:05 PM PDT 24
Finished Aug 08 08:10:22 PM PDT 24
Peak memory 575964 kb
Host smart-ac1e03ea-0097-4d24-a778-a05e436cd14d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138327845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all
_with_rand_reset.2138327845
Directory /workspace/79.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.2181262543
Short name T2545
Test name
Test status
Simulation time 639345908 ps
CPU time 204.7 seconds
Started Aug 08 08:05:07 PM PDT 24
Finished Aug 08 08:08:31 PM PDT 24
Peak memory 576724 kb
Host smart-cf3136b4-5736-4ddf-a0d9-9bc16c4968dd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181262543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al
l_with_reset_error.2181262543
Directory /workspace/79.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.3108423325
Short name T1885
Test name
Test status
Simulation time 227237231 ps
CPU time 26.52 seconds
Started Aug 08 08:05:05 PM PDT 24
Finished Aug 08 08:05:31 PM PDT 24
Peak memory 575984 kb
Host smart-f0c78c42-fcde-4a6f-9d5f-9a83b7b956c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108423325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.3108423325
Directory /workspace/79.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.3173836532
Short name T690
Test name
Test status
Simulation time 6770856840 ps
CPU time 508.55 seconds
Started Aug 08 07:51:06 PM PDT 24
Finished Aug 08 07:59:35 PM PDT 24
Peak memory 644544 kb
Host smart-4633d617-afa8-4b94-934a-38dea164ba04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173836532 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.3173836532
Directory /workspace/8.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.chip_csr_rw.3253490818
Short name T1637
Test name
Test status
Simulation time 4235726120 ps
CPU time 297.13 seconds
Started Aug 08 07:51:06 PM PDT 24
Finished Aug 08 07:56:03 PM PDT 24
Peak memory 597564 kb
Host smart-6e9fbc1c-081a-44e4-999f-05c8aed16a1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253490818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.3253490818
Directory /workspace/8.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.4153827860
Short name T1942
Test name
Test status
Simulation time 13715943870 ps
CPU time 1714.27 seconds
Started Aug 08 07:50:47 PM PDT 24
Finished Aug 08 08:19:22 PM PDT 24
Peak memory 592944 kb
Host smart-cda011cd-25b2-4ebc-86dd-b53086904e3b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153827860 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.4153827860
Directory /workspace/8.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_access_same_device.2778994088
Short name T2893
Test name
Test status
Simulation time 2004150980 ps
CPU time 73.24 seconds
Started Aug 08 07:50:50 PM PDT 24
Finished Aug 08 07:52:03 PM PDT 24
Peak memory 576024 kb
Host smart-85044130-9427-471a-9b88-8979af33ada2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778994088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.
2778994088
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.347463962
Short name T1753
Test name
Test status
Simulation time 51905584962 ps
CPU time 830.43 seconds
Started Aug 08 07:50:48 PM PDT 24
Finished Aug 08 08:04:38 PM PDT 24
Peak memory 576048 kb
Host smart-a2b6ed80-dc4f-46a4-88d1-4a705b2b1865
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347463962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_de
vice_slow_rsp.347463962
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.3286041735
Short name T2250
Test name
Test status
Simulation time 584652308 ps
CPU time 24.33 seconds
Started Aug 08 07:51:02 PM PDT 24
Finished Aug 08 07:51:26 PM PDT 24
Peak memory 575844 kb
Host smart-4496b787-1f1b-4c2a-9108-8821f075a422
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286041735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr
.3286041735
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_error_random.54577009
Short name T1915
Test name
Test status
Simulation time 477590504 ps
CPU time 38.38 seconds
Started Aug 08 07:51:01 PM PDT 24
Finished Aug 08 07:51:39 PM PDT 24
Peak memory 575804 kb
Host smart-a5a1a2ad-86b2-433c-a604-57c85a0a8c55
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54577009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.54577009
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random.29417837
Short name T564
Test name
Test status
Simulation time 1224604669 ps
CPU time 43.4 seconds
Started Aug 08 07:51:00 PM PDT 24
Finished Aug 08 07:51:43 PM PDT 24
Peak memory 575724 kb
Host smart-338226f2-f998-4c6e-a131-25a4fd2c30ae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29417837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.29417837
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.1641139723
Short name T1971
Test name
Test status
Simulation time 15484327301 ps
CPU time 172.39 seconds
Started Aug 08 07:50:48 PM PDT 24
Finished Aug 08 07:53:40 PM PDT 24
Peak memory 575904 kb
Host smart-50097966-8b47-4980-ad43-9aa7810ff7e6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641139723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1641139723
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.1385585901
Short name T446
Test name
Test status
Simulation time 30189456081 ps
CPU time 509.12 seconds
Started Aug 08 07:50:49 PM PDT 24
Finished Aug 08 07:59:18 PM PDT 24
Peak memory 575944 kb
Host smart-9d0388f0-aadf-41aa-9512-e255f17defcd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385585901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1385585901
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.4173982557
Short name T2754
Test name
Test status
Simulation time 204640425 ps
CPU time 20.57 seconds
Started Aug 08 07:50:51 PM PDT 24
Finished Aug 08 07:51:12 PM PDT 24
Peak memory 575868 kb
Host smart-b542cd8c-0565-4dab-8700-62cbd864db98
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173982557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela
ys.4173982557
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_same_source.2121235332
Short name T2762
Test name
Test status
Simulation time 333304899 ps
CPU time 26.55 seconds
Started Aug 08 07:51:00 PM PDT 24
Finished Aug 08 07:51:26 PM PDT 24
Peak memory 575808 kb
Host smart-f0f138fc-0a88-487b-a47e-551480b23a2a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121235332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2121235332
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke.965940448
Short name T1519
Test name
Test status
Simulation time 137920744 ps
CPU time 7.33 seconds
Started Aug 08 07:51:00 PM PDT 24
Finished Aug 08 07:51:07 PM PDT 24
Peak memory 573700 kb
Host smart-2bcb465c-ef46-4166-b9a0-0fee5a6fc3d7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965940448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.965940448
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.4097140084
Short name T551
Test name
Test status
Simulation time 9428061476 ps
CPU time 101.13 seconds
Started Aug 08 07:50:52 PM PDT 24
Finished Aug 08 07:52:33 PM PDT 24
Peak memory 574532 kb
Host smart-a8070efa-d551-4b3b-a6a9-54074c81c3d3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097140084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.4097140084
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.4073269761
Short name T2099
Test name
Test status
Simulation time 5319026644 ps
CPU time 88.09 seconds
Started Aug 08 07:50:51 PM PDT 24
Finished Aug 08 07:52:20 PM PDT 24
Peak memory 574528 kb
Host smart-2c29ef03-5d7c-4d62-ae7f-dbd306495fd5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073269761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.4073269761
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.1702668758
Short name T2511
Test name
Test status
Simulation time 55168585 ps
CPU time 6.53 seconds
Started Aug 08 07:50:52 PM PDT 24
Finished Aug 08 07:50:58 PM PDT 24
Peak memory 573796 kb
Host smart-f9416b9c-7605-4ee8-b886-8c81198586ca
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702668758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays
.1702668758
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all.3097601803
Short name T2706
Test name
Test status
Simulation time 10295752132 ps
CPU time 406.23 seconds
Started Aug 08 07:51:00 PM PDT 24
Finished Aug 08 07:57:47 PM PDT 24
Peak memory 576732 kb
Host smart-c321b29e-7b54-40fd-a4ac-89d0c22d3e9c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097601803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.3097601803
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.2172190311
Short name T1618
Test name
Test status
Simulation time 6274539138 ps
CPU time 392.66 seconds
Started Aug 08 07:50:56 PM PDT 24
Finished Aug 08 07:57:29 PM PDT 24
Peak memory 575956 kb
Host smart-3d1881dc-9940-4168-82b1-4083843fd874
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172190311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_
with_rand_reset.2172190311
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.1987389790
Short name T2355
Test name
Test status
Simulation time 95164802 ps
CPU time 32.02 seconds
Started Aug 08 07:51:06 PM PDT 24
Finished Aug 08 07:51:38 PM PDT 24
Peak memory 576192 kb
Host smart-452a6097-f3c4-46cb-b9fa-5c461f89508e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987389790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all
_with_reset_error.1987389790
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.2676228534
Short name T603
Test name
Test status
Simulation time 542225810 ps
CPU time 25.35 seconds
Started Aug 08 07:50:56 PM PDT 24
Finished Aug 08 07:51:22 PM PDT 24
Peak memory 575860 kb
Host smart-f3bd0f2b-db3d-4955-a70a-6e2ba75c5f83
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676228534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2676228534
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_access_same_device.4139690238
Short name T2327
Test name
Test status
Simulation time 946061013 ps
CPU time 74.99 seconds
Started Aug 08 08:05:21 PM PDT 24
Finished Aug 08 08:06:36 PM PDT 24
Peak memory 575980 kb
Host smart-e83c1c2b-4efa-4b4c-b4dc-398a7d09804f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139690238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device
.4139690238
Directory /workspace/80.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.2080608720
Short name T2910
Test name
Test status
Simulation time 80287245506 ps
CPU time 1473.99 seconds
Started Aug 08 08:05:20 PM PDT 24
Finished Aug 08 08:29:54 PM PDT 24
Peak memory 576024 kb
Host smart-c991bfc5-dcd5-4e12-b968-4dc6e7e926fb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080608720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_
device_slow_rsp.2080608720
Directory /workspace/80.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2501751302
Short name T1369
Test name
Test status
Simulation time 371315307 ps
CPU time 16.97 seconds
Started Aug 08 08:05:24 PM PDT 24
Finished Aug 08 08:05:41 PM PDT 24
Peak memory 575952 kb
Host smart-71d209ba-a1d1-4c29-9656-a7eb5e5ce845
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501751302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add
r.2501751302
Directory /workspace/80.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_error_random.1635770997
Short name T1386
Test name
Test status
Simulation time 1844289800 ps
CPU time 57.65 seconds
Started Aug 08 08:05:18 PM PDT 24
Finished Aug 08 08:06:15 PM PDT 24
Peak memory 575824 kb
Host smart-c4ea9171-37b9-4f2f-96df-b55c0ef5d4fa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635770997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.1635770997
Directory /workspace/80.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random.3232259632
Short name T2710
Test name
Test status
Simulation time 820788819 ps
CPU time 26.38 seconds
Started Aug 08 08:05:23 PM PDT 24
Finished Aug 08 08:05:50 PM PDT 24
Peak memory 575776 kb
Host smart-b77e304e-ec22-43aa-9f42-f49ff534858d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232259632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.3232259632
Directory /workspace/80.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.3576779269
Short name T1606
Test name
Test status
Simulation time 103546755178 ps
CPU time 997.37 seconds
Started Aug 08 08:05:23 PM PDT 24
Finished Aug 08 08:22:00 PM PDT 24
Peak memory 574872 kb
Host smart-dc9bd707-2664-4f06-8fbe-07e3df03a053
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576779269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.3576779269
Directory /workspace/80.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.3253090218
Short name T2629
Test name
Test status
Simulation time 18152950219 ps
CPU time 299.08 seconds
Started Aug 08 08:05:19 PM PDT 24
Finished Aug 08 08:10:18 PM PDT 24
Peak memory 575944 kb
Host smart-940baacd-9b82-4048-b112-35a14786bf6d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253090218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.3253090218
Directory /workspace/80.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.99059153
Short name T2095
Test name
Test status
Simulation time 509713156 ps
CPU time 50.73 seconds
Started Aug 08 08:05:18 PM PDT 24
Finished Aug 08 08:06:09 PM PDT 24
Peak memory 575828 kb
Host smart-7bfb47b5-5690-4425-a25d-7c802a607bdb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99059153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_delay
s.99059153
Directory /workspace/80.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_same_source.3857080806
Short name T582
Test name
Test status
Simulation time 2674770749 ps
CPU time 74.19 seconds
Started Aug 08 08:05:23 PM PDT 24
Finished Aug 08 08:06:37 PM PDT 24
Peak memory 575888 kb
Host smart-adc80007-4526-46bf-af77-9b7732fc3320
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857080806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.3857080806
Directory /workspace/80.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke.882107507
Short name T2213
Test name
Test status
Simulation time 199743493 ps
CPU time 8.66 seconds
Started Aug 08 08:05:07 PM PDT 24
Finished Aug 08 08:05:16 PM PDT 24
Peak memory 574444 kb
Host smart-12962fb5-5cd9-40b5-bf59-538b53f760ea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882107507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.882107507
Directory /workspace/80.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.1701877760
Short name T1559
Test name
Test status
Simulation time 5706239681 ps
CPU time 59.97 seconds
Started Aug 08 08:05:07 PM PDT 24
Finished Aug 08 08:06:07 PM PDT 24
Peak memory 573904 kb
Host smart-b0ca2c07-db9e-4b29-be33-da4c555471d2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701877760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.1701877760
Directory /workspace/80.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.605706008
Short name T1855
Test name
Test status
Simulation time 6138232195 ps
CPU time 108.45 seconds
Started Aug 08 08:05:19 PM PDT 24
Finished Aug 08 08:07:07 PM PDT 24
Peak memory 573928 kb
Host smart-e4e86a8c-156b-4347-8325-9e4cff680332
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605706008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.605706008
Directory /workspace/80.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.1383636419
Short name T2109
Test name
Test status
Simulation time 39011174 ps
CPU time 5.88 seconds
Started Aug 08 08:05:07 PM PDT 24
Finished Aug 08 08:05:13 PM PDT 24
Peak memory 574432 kb
Host smart-91c650f5-6fb3-4991-9f5e-df0ed057bb17
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383636419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay
s.1383636419
Directory /workspace/80.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all.990396434
Short name T1917
Test name
Test status
Simulation time 10536135702 ps
CPU time 374.09 seconds
Started Aug 08 08:05:20 PM PDT 24
Finished Aug 08 08:11:35 PM PDT 24
Peak memory 576752 kb
Host smart-ee9becba-b7bf-47c4-9187-508bb547e16a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990396434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.990396434
Directory /workspace/80.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.1849918287
Short name T1807
Test name
Test status
Simulation time 1577905331 ps
CPU time 126.13 seconds
Started Aug 08 08:05:19 PM PDT 24
Finished Aug 08 08:07:25 PM PDT 24
Peak memory 575792 kb
Host smart-7c771719-bd85-4071-871b-d24b0a9ad2e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849918287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.1849918287
Directory /workspace/80.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.1535772083
Short name T2303
Test name
Test status
Simulation time 6408991706 ps
CPU time 314.39 seconds
Started Aug 08 08:05:41 PM PDT 24
Finished Aug 08 08:10:56 PM PDT 24
Peak memory 576712 kb
Host smart-18d763ab-038e-42f7-8886-09f0ba106f70
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535772083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all
_with_rand_reset.1535772083
Directory /workspace/80.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.1022553268
Short name T846
Test name
Test status
Simulation time 3662492268 ps
CPU time 353.25 seconds
Started Aug 08 08:05:18 PM PDT 24
Finished Aug 08 08:11:12 PM PDT 24
Peak memory 576800 kb
Host smart-d13779e1-9676-40ee-8259-4d8ae18b6746
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022553268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al
l_with_reset_error.1022553268
Directory /workspace/80.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.4152845992
Short name T1794
Test name
Test status
Simulation time 138416372 ps
CPU time 9.83 seconds
Started Aug 08 08:05:18 PM PDT 24
Finished Aug 08 08:05:28 PM PDT 24
Peak memory 574680 kb
Host smart-f95cc682-39d0-43dd-90cb-aa7ee73637ba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152845992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.4152845992
Directory /workspace/80.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_access_same_device.4057026718
Short name T784
Test name
Test status
Simulation time 825025968 ps
CPU time 62.07 seconds
Started Aug 08 08:05:41 PM PDT 24
Finished Aug 08 08:06:44 PM PDT 24
Peak memory 575888 kb
Host smart-a0626863-b23e-4106-a5ea-34a31bf79bde
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057026718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device
.4057026718
Directory /workspace/81.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.2823209407
Short name T2291
Test name
Test status
Simulation time 110505542393 ps
CPU time 2038.74 seconds
Started Aug 08 08:05:20 PM PDT 24
Finished Aug 08 08:39:19 PM PDT 24
Peak memory 576032 kb
Host smart-5145a1f5-8f16-4fff-a2fd-d38da293f6da
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823209407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_
device_slow_rsp.2823209407
Directory /workspace/81.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.3845232000
Short name T1697
Test name
Test status
Simulation time 86700414 ps
CPU time 10.47 seconds
Started Aug 08 08:05:23 PM PDT 24
Finished Aug 08 08:05:33 PM PDT 24
Peak memory 574768 kb
Host smart-6a9de666-af94-4018-a9a9-65d2637a181b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845232000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add
r.3845232000
Directory /workspace/81.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_error_random.2961998551
Short name T2369
Test name
Test status
Simulation time 137165715 ps
CPU time 7.42 seconds
Started Aug 08 08:05:23 PM PDT 24
Finished Aug 08 08:05:31 PM PDT 24
Peak memory 573876 kb
Host smart-f0c2ae40-6356-4237-a4d0-6ae366bf3432
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961998551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.2961998551
Directory /workspace/81.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random.4159775254
Short name T562
Test name
Test status
Simulation time 294266663 ps
CPU time 26.86 seconds
Started Aug 08 08:05:25 PM PDT 24
Finished Aug 08 08:05:52 PM PDT 24
Peak memory 575796 kb
Host smart-68055988-5a0a-4a25-bdd5-45103091d652
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159775254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.4159775254
Directory /workspace/81.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.2404722224
Short name T2530
Test name
Test status
Simulation time 58604192460 ps
CPU time 585.34 seconds
Started Aug 08 08:05:18 PM PDT 24
Finished Aug 08 08:15:04 PM PDT 24
Peak memory 575832 kb
Host smart-549836d5-025e-4c73-96be-98d55ccd7d47
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404722224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.2404722224
Directory /workspace/81.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.2268015467
Short name T1577
Test name
Test status
Simulation time 48274298388 ps
CPU time 815.96 seconds
Started Aug 08 08:05:21 PM PDT 24
Finished Aug 08 08:18:57 PM PDT 24
Peak memory 575960 kb
Host smart-e5cd173b-b5e6-43d3-8616-a2655b82aebd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268015467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.2268015467
Directory /workspace/81.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.2043927386
Short name T2939
Test name
Test status
Simulation time 623740964 ps
CPU time 55.59 seconds
Started Aug 08 08:05:21 PM PDT 24
Finished Aug 08 08:06:17 PM PDT 24
Peak memory 575808 kb
Host smart-9e43e95f-8e5f-4282-8523-a98591103f0c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043927386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del
ays.2043927386
Directory /workspace/81.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_same_source.2859746901
Short name T573
Test name
Test status
Simulation time 1828110373 ps
CPU time 52.08 seconds
Started Aug 08 08:05:18 PM PDT 24
Finished Aug 08 08:06:10 PM PDT 24
Peak memory 575800 kb
Host smart-8e72d906-ad3d-4fce-b4b7-32213d2ab846
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859746901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.2859746901
Directory /workspace/81.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke.4253077456
Short name T1537
Test name
Test status
Simulation time 198122936 ps
CPU time 8.13 seconds
Started Aug 08 08:05:23 PM PDT 24
Finished Aug 08 08:05:31 PM PDT 24
Peak memory 573836 kb
Host smart-9f5a36c8-ea63-49a3-a4e6-48bb878d8b62
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253077456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.4253077456
Directory /workspace/81.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.3624572215
Short name T1729
Test name
Test status
Simulation time 9601199241 ps
CPU time 105.73 seconds
Started Aug 08 08:05:19 PM PDT 24
Finished Aug 08 08:07:05 PM PDT 24
Peak memory 574608 kb
Host smart-b165fe84-6b81-4f52-983e-b11811224cb9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624572215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.3624572215
Directory /workspace/81.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.626616517
Short name T1849
Test name
Test status
Simulation time 5320499106 ps
CPU time 92.6 seconds
Started Aug 08 08:05:21 PM PDT 24
Finished Aug 08 08:06:53 PM PDT 24
Peak memory 574604 kb
Host smart-2afe483f-4606-4797-877f-e5709dce7be9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626616517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.626616517
Directory /workspace/81.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.3133972980
Short name T2348
Test name
Test status
Simulation time 46834522 ps
CPU time 6.36 seconds
Started Aug 08 08:05:19 PM PDT 24
Finished Aug 08 08:05:26 PM PDT 24
Peak memory 574464 kb
Host smart-cc0a76f0-c39a-41c9-9b8b-a619b00f4474
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133972980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay
s.3133972980
Directory /workspace/81.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all.433152392
Short name T1776
Test name
Test status
Simulation time 2684218578 ps
CPU time 184.11 seconds
Started Aug 08 08:05:41 PM PDT 24
Finished Aug 08 08:08:46 PM PDT 24
Peak memory 576000 kb
Host smart-17df7c5a-90ac-417a-9390-78ad499e1e31
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433152392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.433152392
Directory /workspace/81.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.4016002766
Short name T2619
Test name
Test status
Simulation time 18739781632 ps
CPU time 677.21 seconds
Started Aug 08 08:05:41 PM PDT 24
Finished Aug 08 08:16:58 PM PDT 24
Peak memory 576704 kb
Host smart-bc193b96-2b9d-4f64-9857-2600e04ce6f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016002766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.4016002766
Directory /workspace/81.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.457457418
Short name T2322
Test name
Test status
Simulation time 3866507333 ps
CPU time 506.35 seconds
Started Aug 08 08:05:19 PM PDT 24
Finished Aug 08 08:13:46 PM PDT 24
Peak memory 575960 kb
Host smart-44ada566-956b-4470-8ca0-a1d0f023e234
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457457418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_
with_rand_reset.457457418
Directory /workspace/81.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.1618375402
Short name T2883
Test name
Test status
Simulation time 1530739205 ps
CPU time 111.59 seconds
Started Aug 08 08:05:23 PM PDT 24
Finished Aug 08 08:07:15 PM PDT 24
Peak memory 575524 kb
Host smart-b475a764-4b79-44ef-adc8-5d41834c1887
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618375402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al
l_with_reset_error.1618375402
Directory /workspace/81.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.3762841373
Short name T2185
Test name
Test status
Simulation time 148406320 ps
CPU time 18.58 seconds
Started Aug 08 08:05:41 PM PDT 24
Finished Aug 08 08:06:00 PM PDT 24
Peak memory 575936 kb
Host smart-e70d9f61-6792-43fc-a17c-1aa9dfd39d85
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762841373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.3762841373
Directory /workspace/81.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_access_same_device.758225693
Short name T2667
Test name
Test status
Simulation time 1926297227 ps
CPU time 71.55 seconds
Started Aug 08 08:05:33 PM PDT 24
Finished Aug 08 08:06:45 PM PDT 24
Peak memory 575840 kb
Host smart-875f2a4f-0839-44dc-93d3-191a2feb0796
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758225693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device.
758225693
Directory /workspace/82.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.3653562165
Short name T2105
Test name
Test status
Simulation time 111368073252 ps
CPU time 2113.58 seconds
Started Aug 08 08:05:29 PM PDT 24
Finished Aug 08 08:40:43 PM PDT 24
Peak memory 575900 kb
Host smart-c4388d15-d725-4d78-874f-d38c3cade156
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653562165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_
device_slow_rsp.3653562165
Directory /workspace/82.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.2715639930
Short name T1459
Test name
Test status
Simulation time 1378279338 ps
CPU time 49.11 seconds
Started Aug 08 08:05:34 PM PDT 24
Finished Aug 08 08:06:23 PM PDT 24
Peak memory 575892 kb
Host smart-0db82f48-530d-4dd2-8d4c-2b2c1d67b4b4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715639930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add
r.2715639930
Directory /workspace/82.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_error_random.1384792122
Short name T1349
Test name
Test status
Simulation time 653548998 ps
CPU time 21.35 seconds
Started Aug 08 08:05:34 PM PDT 24
Finished Aug 08 08:05:55 PM PDT 24
Peak memory 575664 kb
Host smart-1e9e4cdd-6892-4bab-8f32-c4e9f6d2348c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384792122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.1384792122
Directory /workspace/82.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random.676680688
Short name T2651
Test name
Test status
Simulation time 395832028 ps
CPU time 16.87 seconds
Started Aug 08 08:05:25 PM PDT 24
Finished Aug 08 08:05:42 PM PDT 24
Peak memory 575776 kb
Host smart-4d6e040e-b29a-4447-8fbb-fe9cbb10f2c4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676680688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.676680688
Directory /workspace/82.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.3379391685
Short name T2781
Test name
Test status
Simulation time 29037379726 ps
CPU time 304.45 seconds
Started Aug 08 08:05:42 PM PDT 24
Finished Aug 08 08:10:46 PM PDT 24
Peak memory 575960 kb
Host smart-4e9eda43-a74b-4609-a192-3d15f9e80a45
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379391685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.3379391685
Directory /workspace/82.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.2905582249
Short name T2007
Test name
Test status
Simulation time 32586076677 ps
CPU time 499.51 seconds
Started Aug 08 08:05:28 PM PDT 24
Finished Aug 08 08:13:47 PM PDT 24
Peak memory 575896 kb
Host smart-3df4a206-02a1-421e-b3bc-a9d925a71d1c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905582249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.2905582249
Directory /workspace/82.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.1514851094
Short name T1758
Test name
Test status
Simulation time 302905493 ps
CPU time 25.52 seconds
Started Aug 08 08:05:40 PM PDT 24
Finished Aug 08 08:06:06 PM PDT 24
Peak memory 575860 kb
Host smart-719c7eac-e94c-4d80-8a83-9517e7da4d77
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514851094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del
ays.1514851094
Directory /workspace/82.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_same_source.32138416
Short name T2867
Test name
Test status
Simulation time 1120504120 ps
CPU time 31.64 seconds
Started Aug 08 08:05:29 PM PDT 24
Finished Aug 08 08:06:01 PM PDT 24
Peak memory 575764 kb
Host smart-ae5715f0-db58-429f-acdf-8e22e6e7c59f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32138416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.32138416
Directory /workspace/82.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke.2188297331
Short name T1869
Test name
Test status
Simulation time 40363492 ps
CPU time 5.59 seconds
Started Aug 08 08:05:40 PM PDT 24
Finished Aug 08 08:05:46 PM PDT 24
Peak memory 573768 kb
Host smart-707ccf92-f4bc-46ef-af64-767c410fe5a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188297331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.2188297331
Directory /workspace/82.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.1614898715
Short name T1442
Test name
Test status
Simulation time 8757044084 ps
CPU time 88.6 seconds
Started Aug 08 08:05:40 PM PDT 24
Finished Aug 08 08:07:09 PM PDT 24
Peak memory 574536 kb
Host smart-bedce182-3392-40e0-b322-7aa4418a5336
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614898715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.1614898715
Directory /workspace/82.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.1004307886
Short name T1387
Test name
Test status
Simulation time 3998228175 ps
CPU time 70.15 seconds
Started Aug 08 08:05:24 PM PDT 24
Finished Aug 08 08:06:34 PM PDT 24
Peak memory 573772 kb
Host smart-0bb1b8d6-8b30-434d-9305-dee0fa7e24ef
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004307886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.1004307886
Directory /workspace/82.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.4054980477
Short name T1520
Test name
Test status
Simulation time 49747618 ps
CPU time 6.58 seconds
Started Aug 08 08:05:23 PM PDT 24
Finished Aug 08 08:05:30 PM PDT 24
Peak memory 573704 kb
Host smart-2f7337d7-33e0-4106-b590-ac1916e45b1c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054980477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay
s.4054980477
Directory /workspace/82.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all.1328473133
Short name T2320
Test name
Test status
Simulation time 2745824797 ps
CPU time 201.35 seconds
Started Aug 08 08:05:37 PM PDT 24
Finished Aug 08 08:08:58 PM PDT 24
Peak memory 576472 kb
Host smart-f800e636-7ef4-4a40-bea8-b641c68a7bb2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328473133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.1328473133
Directory /workspace/82.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.703592137
Short name T2248
Test name
Test status
Simulation time 2340905490 ps
CPU time 75.75 seconds
Started Aug 08 08:05:31 PM PDT 24
Finished Aug 08 08:06:47 PM PDT 24
Peak memory 576040 kb
Host smart-f61b4eaa-e9a9-41c8-86f7-4f23f71439db
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703592137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.703592137
Directory /workspace/82.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.2123877062
Short name T2732
Test name
Test status
Simulation time 7183847 ps
CPU time 23.23 seconds
Started Aug 08 08:05:34 PM PDT 24
Finished Aug 08 08:05:58 PM PDT 24
Peak memory 574560 kb
Host smart-30adfea2-d955-45cf-8913-758d50b46395
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123877062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all
_with_rand_reset.2123877062
Directory /workspace/82.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.2189071652
Short name T2788
Test name
Test status
Simulation time 6141374736 ps
CPU time 391.41 seconds
Started Aug 08 08:05:31 PM PDT 24
Finished Aug 08 08:12:03 PM PDT 24
Peak memory 576820 kb
Host smart-0e227b19-1e93-43e9-a922-74fc00c33891
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189071652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al
l_with_reset_error.2189071652
Directory /workspace/82.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.519081765
Short name T1479
Test name
Test status
Simulation time 229726725 ps
CPU time 14.24 seconds
Started Aug 08 08:05:31 PM PDT 24
Finished Aug 08 08:05:46 PM PDT 24
Peak memory 575992 kb
Host smart-76b69ca6-9728-4c0e-a87e-2028e46a0356
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519081765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.519081765
Directory /workspace/82.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_access_same_device.1405247393
Short name T1948
Test name
Test status
Simulation time 848779933 ps
CPU time 54.76 seconds
Started Aug 08 08:05:42 PM PDT 24
Finished Aug 08 08:06:37 PM PDT 24
Peak memory 575848 kb
Host smart-ed7d8c29-c584-44ab-9082-23f93d5c81e6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405247393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device
.1405247393
Directory /workspace/83.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.3902044249
Short name T2444
Test name
Test status
Simulation time 23389934578 ps
CPU time 381.94 seconds
Started Aug 08 08:05:39 PM PDT 24
Finished Aug 08 08:12:01 PM PDT 24
Peak memory 575848 kb
Host smart-c54698dd-4966-4ef1-abdf-986a5cb2d9c9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902044249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_
device_slow_rsp.3902044249
Directory /workspace/83.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.824645213
Short name T2675
Test name
Test status
Simulation time 57156364 ps
CPU time 6.37 seconds
Started Aug 08 08:05:37 PM PDT 24
Finished Aug 08 08:05:44 PM PDT 24
Peak memory 573796 kb
Host smart-0196f3ea-3e78-49fa-96b6-0d994ed396be
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824645213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_addr
.824645213
Directory /workspace/83.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_error_random.1779607943
Short name T1964
Test name
Test status
Simulation time 580836896 ps
CPU time 22.7 seconds
Started Aug 08 08:05:42 PM PDT 24
Finished Aug 08 08:06:05 PM PDT 24
Peak memory 575868 kb
Host smart-cce28197-5a41-4c69-86cc-3a6537d4b8f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779607943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.1779607943
Directory /workspace/83.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random.4077648867
Short name T2812
Test name
Test status
Simulation time 2389043516 ps
CPU time 87.13 seconds
Started Aug 08 08:05:38 PM PDT 24
Finished Aug 08 08:07:06 PM PDT 24
Peak memory 575964 kb
Host smart-7e1dfb37-ab70-4c91-beda-9ce95cc0590a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077648867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.4077648867
Directory /workspace/83.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.2695757600
Short name T2442
Test name
Test status
Simulation time 108115544439 ps
CPU time 1150.02 seconds
Started Aug 08 08:05:36 PM PDT 24
Finished Aug 08 08:24:46 PM PDT 24
Peak memory 575904 kb
Host smart-dfa1cc74-5871-4905-b477-39719654bdf6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695757600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.2695757600
Directory /workspace/83.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.2568267870
Short name T2766
Test name
Test status
Simulation time 2914122492 ps
CPU time 49.95 seconds
Started Aug 08 08:05:37 PM PDT 24
Finished Aug 08 08:06:27 PM PDT 24
Peak memory 574528 kb
Host smart-0d0f227b-4d07-491e-8e9a-bf35f2bb204a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568267870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.2568267870
Directory /workspace/83.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.638404296
Short name T2418
Test name
Test status
Simulation time 391306284 ps
CPU time 31.77 seconds
Started Aug 08 08:05:37 PM PDT 24
Finished Aug 08 08:06:09 PM PDT 24
Peak memory 575748 kb
Host smart-ee37565d-1cb3-40f8-9e1e-a884be47d822
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638404296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_dela
ys.638404296
Directory /workspace/83.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_same_source.2897833592
Short name T2753
Test name
Test status
Simulation time 278996261 ps
CPU time 19.49 seconds
Started Aug 08 08:05:40 PM PDT 24
Finished Aug 08 08:05:59 PM PDT 24
Peak memory 575852 kb
Host smart-9ec6a422-56ce-4225-8cfc-607189cc4d61
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897833592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.2897833592
Directory /workspace/83.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke.2128367467
Short name T1499
Test name
Test status
Simulation time 47810778 ps
CPU time 6.3 seconds
Started Aug 08 08:05:30 PM PDT 24
Finished Aug 08 08:05:36 PM PDT 24
Peak memory 573728 kb
Host smart-2a450b1f-cfb1-4aef-9866-a50fdc29493c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128367467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.2128367467
Directory /workspace/83.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.1894053793
Short name T2552
Test name
Test status
Simulation time 9100488106 ps
CPU time 96.39 seconds
Started Aug 08 08:05:31 PM PDT 24
Finished Aug 08 08:07:07 PM PDT 24
Peak memory 574568 kb
Host smart-0c9e3e48-b7fa-42b9-9edf-3bdb08106489
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894053793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.1894053793
Directory /workspace/83.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3396783575
Short name T1820
Test name
Test status
Simulation time 4856359133 ps
CPU time 86.02 seconds
Started Aug 08 08:05:37 PM PDT 24
Finished Aug 08 08:07:03 PM PDT 24
Peak memory 574584 kb
Host smart-67c158a8-0c02-4b2f-b2c7-b8198dc9b1b8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396783575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.3396783575
Directory /workspace/83.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.782216882
Short name T1988
Test name
Test status
Simulation time 55878111 ps
CPU time 6.89 seconds
Started Aug 08 08:05:37 PM PDT 24
Finished Aug 08 08:05:44 PM PDT 24
Peak memory 573748 kb
Host smart-12e94d5b-bdda-439d-a670-162270ba5a6f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782216882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delays
.782216882
Directory /workspace/83.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all.4285122307
Short name T2723
Test name
Test status
Simulation time 2110084221 ps
CPU time 153.94 seconds
Started Aug 08 08:05:45 PM PDT 24
Finished Aug 08 08:08:19 PM PDT 24
Peak memory 576720 kb
Host smart-517bad5b-fbd4-48a5-87eb-970c2e5bf445
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285122307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.4285122307
Directory /workspace/83.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.2657667214
Short name T2052
Test name
Test status
Simulation time 446358090 ps
CPU time 31.82 seconds
Started Aug 08 08:05:42 PM PDT 24
Finished Aug 08 08:06:14 PM PDT 24
Peak memory 575880 kb
Host smart-39f1ce9b-3292-44ee-9692-2085869aa886
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657667214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.2657667214
Directory /workspace/83.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.2546714537
Short name T1746
Test name
Test status
Simulation time 137564731 ps
CPU time 24.67 seconds
Started Aug 08 08:05:45 PM PDT 24
Finished Aug 08 08:06:09 PM PDT 24
Peak memory 576120 kb
Host smart-526e2f64-2e50-4c1a-a2c0-47341d022b0d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546714537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all
_with_rand_reset.2546714537
Directory /workspace/83.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.2957720168
Short name T2267
Test name
Test status
Simulation time 8591639232 ps
CPU time 488.77 seconds
Started Aug 08 08:05:36 PM PDT 24
Finished Aug 08 08:13:45 PM PDT 24
Peak memory 576824 kb
Host smart-741d67cc-6089-4a9a-9724-5d6ce29918b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957720168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al
l_with_reset_error.2957720168
Directory /workspace/83.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.2731474579
Short name T1936
Test name
Test status
Simulation time 981685650 ps
CPU time 40.43 seconds
Started Aug 08 08:05:39 PM PDT 24
Finished Aug 08 08:06:20 PM PDT 24
Peak memory 575980 kb
Host smart-62a2b69f-5591-4f0e-8a84-fe752ee1b14c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731474579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.2731474579
Directory /workspace/83.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_access_same_device.1940351671
Short name T1830
Test name
Test status
Simulation time 265350042 ps
CPU time 26.59 seconds
Started Aug 08 08:05:53 PM PDT 24
Finished Aug 08 08:06:19 PM PDT 24
Peak memory 575924 kb
Host smart-822eadfe-cf19-4158-8d05-0cef4baf7e28
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940351671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device
.1940351671
Directory /workspace/84.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2699093046
Short name T2750
Test name
Test status
Simulation time 47310464764 ps
CPU time 774.9 seconds
Started Aug 08 08:05:53 PM PDT 24
Finished Aug 08 08:18:48 PM PDT 24
Peak memory 576012 kb
Host smart-88219de9-0f90-4529-af6a-a847072d1d24
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699093046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_
device_slow_rsp.2699093046
Directory /workspace/84.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.1402419601
Short name T1741
Test name
Test status
Simulation time 88928639 ps
CPU time 7.34 seconds
Started Aug 08 08:05:50 PM PDT 24
Finished Aug 08 08:05:57 PM PDT 24
Peak memory 574404 kb
Host smart-f919fdf7-5e25-4e9f-ba45-0d11e98807a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402419601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add
r.1402419601
Directory /workspace/84.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_error_random.4067784895
Short name T2438
Test name
Test status
Simulation time 408260800 ps
CPU time 16.06 seconds
Started Aug 08 08:05:47 PM PDT 24
Finished Aug 08 08:06:03 PM PDT 24
Peak memory 575640 kb
Host smart-3d540375-a196-4eaf-b3d1-e3886be1cb64
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067784895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.4067784895
Directory /workspace/84.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random.2023190735
Short name T2701
Test name
Test status
Simulation time 368286596 ps
CPU time 15.56 seconds
Started Aug 08 08:05:47 PM PDT 24
Finished Aug 08 08:06:03 PM PDT 24
Peak memory 575748 kb
Host smart-168e3dfc-11ee-42cf-aa3e-9e14d1e1e9e9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023190735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.2023190735
Directory /workspace/84.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.3216949877
Short name T1445
Test name
Test status
Simulation time 87795262398 ps
CPU time 937.63 seconds
Started Aug 08 08:05:47 PM PDT 24
Finished Aug 08 08:21:25 PM PDT 24
Peak memory 575824 kb
Host smart-8a339459-03b2-4921-ac7f-bf0b99e8a397
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216949877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.3216949877
Directory /workspace/84.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.3081009170
Short name T1470
Test name
Test status
Simulation time 28108231438 ps
CPU time 464.15 seconds
Started Aug 08 08:05:53 PM PDT 24
Finished Aug 08 08:13:37 PM PDT 24
Peak memory 575972 kb
Host smart-b4e9a78d-a99e-466d-a12a-bb1c7e02dff5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081009170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.3081009170
Directory /workspace/84.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.1592669800
Short name T2430
Test name
Test status
Simulation time 124246956 ps
CPU time 12.84 seconds
Started Aug 08 08:05:48 PM PDT 24
Finished Aug 08 08:06:00 PM PDT 24
Peak memory 575892 kb
Host smart-bf41c17b-8cf3-4595-b15d-8240ff360a82
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592669800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del
ays.1592669800
Directory /workspace/84.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_same_source.2354031245
Short name T1407
Test name
Test status
Simulation time 1020441596 ps
CPU time 32.4 seconds
Started Aug 08 08:05:46 PM PDT 24
Finished Aug 08 08:06:19 PM PDT 24
Peak memory 575872 kb
Host smart-29d19840-7609-40e1-8927-a4168991b002
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354031245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.2354031245
Directory /workspace/84.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke.3216549270
Short name T2439
Test name
Test status
Simulation time 215274164 ps
CPU time 9.14 seconds
Started Aug 08 08:05:37 PM PDT 24
Finished Aug 08 08:05:46 PM PDT 24
Peak memory 573788 kb
Host smart-2ca612af-aed5-4481-ac10-5fa06bebc29c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216549270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.3216549270
Directory /workspace/84.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.1359344124
Short name T1367
Test name
Test status
Simulation time 9552955434 ps
CPU time 102.18 seconds
Started Aug 08 08:05:48 PM PDT 24
Finished Aug 08 08:07:30 PM PDT 24
Peak memory 573920 kb
Host smart-8d524906-9f7f-4c1c-89f9-8a5a8f6805c3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359344124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.1359344124
Directory /workspace/84.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.1605593673
Short name T1827
Test name
Test status
Simulation time 6005531569 ps
CPU time 105.04 seconds
Started Aug 08 08:05:47 PM PDT 24
Finished Aug 08 08:07:32 PM PDT 24
Peak memory 573876 kb
Host smart-ebd41709-7552-43de-b7a7-907ebef02013
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605593673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.1605593673
Directory /workspace/84.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1733924334
Short name T2815
Test name
Test status
Simulation time 56330790 ps
CPU time 5.97 seconds
Started Aug 08 08:05:38 PM PDT 24
Finished Aug 08 08:05:44 PM PDT 24
Peak memory 573796 kb
Host smart-3a557d06-2d59-4148-bca8-4f54db1f90e2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733924334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay
s.1733924334
Directory /workspace/84.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all.3023638242
Short name T1596
Test name
Test status
Simulation time 2399403307 ps
CPU time 158.05 seconds
Started Aug 08 08:05:49 PM PDT 24
Finished Aug 08 08:08:27 PM PDT 24
Peak memory 575932 kb
Host smart-56d72cde-7f19-4e3a-9e75-ec70013b0cb3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023638242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.3023638242
Directory /workspace/84.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.3079860645
Short name T2000
Test name
Test status
Simulation time 15052048583 ps
CPU time 571.95 seconds
Started Aug 08 08:05:48 PM PDT 24
Finished Aug 08 08:15:20 PM PDT 24
Peak memory 576048 kb
Host smart-1db56ce6-a862-4bac-a1cb-2caf99e043c6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079860645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.3079860645
Directory /workspace/84.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.3170618114
Short name T2711
Test name
Test status
Simulation time 387378546 ps
CPU time 129.35 seconds
Started Aug 08 08:05:48 PM PDT 24
Finished Aug 08 08:07:58 PM PDT 24
Peak memory 576708 kb
Host smart-7a1e0845-f0a0-457f-925a-83bfebf09d37
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170618114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all
_with_rand_reset.3170618114
Directory /workspace/84.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2523218614
Short name T851
Test name
Test status
Simulation time 351524504 ps
CPU time 155.2 seconds
Started Aug 08 08:05:49 PM PDT 24
Finished Aug 08 08:08:24 PM PDT 24
Peak memory 576716 kb
Host smart-03205a24-e194-4e9a-a6d3-39eea5efda55
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523218614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al
l_with_reset_error.2523218614
Directory /workspace/84.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.1775401916
Short name T2364
Test name
Test status
Simulation time 315822786 ps
CPU time 13.49 seconds
Started Aug 08 08:05:51 PM PDT 24
Finished Aug 08 08:06:04 PM PDT 24
Peak memory 575976 kb
Host smart-1567ea90-1a10-446b-9a20-d33fb6aa2edc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775401916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.1775401916
Directory /workspace/84.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_access_same_device.3592806742
Short name T2124
Test name
Test status
Simulation time 152460556 ps
CPU time 13.28 seconds
Started Aug 08 08:05:47 PM PDT 24
Finished Aug 08 08:06:01 PM PDT 24
Peak memory 575868 kb
Host smart-f0891951-f4d9-4f0c-8e35-2506ca2af269
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592806742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device
.3592806742
Directory /workspace/85.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.695554530
Short name T2047
Test name
Test status
Simulation time 102149896306 ps
CPU time 1620.01 seconds
Started Aug 08 08:05:52 PM PDT 24
Finished Aug 08 08:32:53 PM PDT 24
Peak memory 576024 kb
Host smart-0cce8974-f25f-4bde-aace-604f714baf7a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695554530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_d
evice_slow_rsp.695554530
Directory /workspace/85.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.2064218383
Short name T2800
Test name
Test status
Simulation time 940845141 ps
CPU time 34.55 seconds
Started Aug 08 08:05:57 PM PDT 24
Finished Aug 08 08:06:32 PM PDT 24
Peak memory 575880 kb
Host smart-2b082515-7851-4de0-889a-3d5860642f65
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064218383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add
r.2064218383
Directory /workspace/85.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_error_random.1786001448
Short name T1907
Test name
Test status
Simulation time 236643582 ps
CPU time 10.8 seconds
Started Aug 08 08:06:01 PM PDT 24
Finished Aug 08 08:06:12 PM PDT 24
Peak memory 574456 kb
Host smart-0e58d765-6a74-4d1e-ab3b-373eb8020369
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786001448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.1786001448
Directory /workspace/85.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random.259761792
Short name T1696
Test name
Test status
Simulation time 296913711 ps
CPU time 24.81 seconds
Started Aug 08 08:05:53 PM PDT 24
Finished Aug 08 08:06:17 PM PDT 24
Peak memory 575868 kb
Host smart-56bcdb4c-aca0-44c1-8a4b-5c91311868e4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259761792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.259761792
Directory /workspace/85.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.4275188699
Short name T2564
Test name
Test status
Simulation time 22131592281 ps
CPU time 227.37 seconds
Started Aug 08 08:05:51 PM PDT 24
Finished Aug 08 08:09:39 PM PDT 24
Peak memory 575892 kb
Host smart-85f4e38d-d32c-4f6e-899d-71a894ede8db
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275188699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.4275188699
Directory /workspace/85.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.537755794
Short name T2326
Test name
Test status
Simulation time 3192196160 ps
CPU time 55.42 seconds
Started Aug 08 08:05:50 PM PDT 24
Finished Aug 08 08:06:46 PM PDT 24
Peak memory 573828 kb
Host smart-e96a0488-11f6-4aaf-a6d2-4409eee34b36
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537755794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.537755794
Directory /workspace/85.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.1812037714
Short name T587
Test name
Test status
Simulation time 70865050 ps
CPU time 8.45 seconds
Started Aug 08 08:05:48 PM PDT 24
Finished Aug 08 08:05:57 PM PDT 24
Peak memory 575740 kb
Host smart-3df5129a-e56b-4ed0-bb21-706881dd6d3a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812037714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del
ays.1812037714
Directory /workspace/85.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_same_source.2815750690
Short name T1492
Test name
Test status
Simulation time 373370691 ps
CPU time 27.53 seconds
Started Aug 08 08:05:57 PM PDT 24
Finished Aug 08 08:06:24 PM PDT 24
Peak memory 575812 kb
Host smart-358c751d-c52a-4198-80ad-f2724f66f194
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815750690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.2815750690
Directory /workspace/85.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke.3200455371
Short name T2254
Test name
Test status
Simulation time 233696014 ps
CPU time 10.26 seconds
Started Aug 08 08:05:47 PM PDT 24
Finished Aug 08 08:05:58 PM PDT 24
Peak memory 574484 kb
Host smart-0837e8bf-e56a-48cc-8ed3-ecae7b4d71cc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200455371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.3200455371
Directory /workspace/85.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.3158897165
Short name T2268
Test name
Test status
Simulation time 10215801375 ps
CPU time 105.74 seconds
Started Aug 08 08:05:47 PM PDT 24
Finished Aug 08 08:07:33 PM PDT 24
Peak memory 574500 kb
Host smart-6cf657f0-f12d-45d1-a08e-4fc75f9c7f34
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158897165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.3158897165
Directory /workspace/85.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.2329858544
Short name T2537
Test name
Test status
Simulation time 6137478475 ps
CPU time 98.92 seconds
Started Aug 08 08:05:50 PM PDT 24
Finished Aug 08 08:07:30 PM PDT 24
Peak memory 574552 kb
Host smart-1abae3f3-d20d-4776-896c-81a705f493db
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329858544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.2329858544
Directory /workspace/85.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.2165906912
Short name T1480
Test name
Test status
Simulation time 40860455 ps
CPU time 5.85 seconds
Started Aug 08 08:05:50 PM PDT 24
Finished Aug 08 08:05:56 PM PDT 24
Peak memory 573764 kb
Host smart-3e712ab8-bbd0-4f8e-a823-c08a170de9bc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165906912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay
s.2165906912
Directory /workspace/85.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all.293741828
Short name T468
Test name
Test status
Simulation time 1622178903 ps
CPU time 126.98 seconds
Started Aug 08 08:05:57 PM PDT 24
Finished Aug 08 08:08:04 PM PDT 24
Peak memory 575872 kb
Host smart-622c9430-5461-4caf-9769-915342dfe3d7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293741828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.293741828
Directory /workspace/85.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.1461714976
Short name T1724
Test name
Test status
Simulation time 711317426 ps
CPU time 62.95 seconds
Started Aug 08 08:05:57 PM PDT 24
Finished Aug 08 08:07:00 PM PDT 24
Peak memory 576036 kb
Host smart-c466f31a-c493-4a29-b292-62fd55badab4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461714976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.1461714976
Directory /workspace/85.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.3708667850
Short name T2553
Test name
Test status
Simulation time 4453029299 ps
CPU time 557.14 seconds
Started Aug 08 08:05:58 PM PDT 24
Finished Aug 08 08:15:16 PM PDT 24
Peak memory 576728 kb
Host smart-5ddc03fc-02e3-4dfe-a609-a02c75e24fcd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708667850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all
_with_rand_reset.3708667850
Directory /workspace/85.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.4169241134
Short name T785
Test name
Test status
Simulation time 18357530756 ps
CPU time 723.33 seconds
Started Aug 08 08:05:56 PM PDT 24
Finished Aug 08 08:18:00 PM PDT 24
Peak memory 575952 kb
Host smart-d43284fc-8f46-4b94-91fd-1a52a5bc2bbd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169241134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al
l_with_reset_error.4169241134
Directory /workspace/85.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.3009987756
Short name T2074
Test name
Test status
Simulation time 627168715 ps
CPU time 28.3 seconds
Started Aug 08 08:05:57 PM PDT 24
Finished Aug 08 08:06:25 PM PDT 24
Peak memory 575984 kb
Host smart-443f2800-652d-4ab2-b817-0fa3394fbe53
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009987756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3009987756
Directory /workspace/85.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_access_same_device.3972839970
Short name T2608
Test name
Test status
Simulation time 3672261825 ps
CPU time 135.02 seconds
Started Aug 08 08:05:57 PM PDT 24
Finished Aug 08 08:08:12 PM PDT 24
Peak memory 576000 kb
Host smart-f2133051-fb32-4927-ae46-4a92d549ac05
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972839970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device
.3972839970
Directory /workspace/86.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.2848545486
Short name T2020
Test name
Test status
Simulation time 118997614052 ps
CPU time 1960.6 seconds
Started Aug 08 08:05:57 PM PDT 24
Finished Aug 08 08:38:38 PM PDT 24
Peak memory 576016 kb
Host smart-c434c2ac-28a0-49ee-bce0-2d23a7bfd72b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848545486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_
device_slow_rsp.2848545486
Directory /workspace/86.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.1668270481
Short name T2054
Test name
Test status
Simulation time 38558910 ps
CPU time 6.94 seconds
Started Aug 08 08:05:57 PM PDT 24
Finished Aug 08 08:06:04 PM PDT 24
Peak memory 574456 kb
Host smart-00f9a7a5-eb71-46a5-975a-68b3391b6faf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668270481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add
r.1668270481
Directory /workspace/86.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_error_random.3582526343
Short name T2863
Test name
Test status
Simulation time 289781339 ps
CPU time 11.94 seconds
Started Aug 08 08:05:55 PM PDT 24
Finished Aug 08 08:06:07 PM PDT 24
Peak memory 575908 kb
Host smart-ecb2cf01-183b-4505-b934-af17b79d5ac2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582526343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.3582526343
Directory /workspace/86.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random.3386187195
Short name T2726
Test name
Test status
Simulation time 576750472 ps
CPU time 44.28 seconds
Started Aug 08 08:05:57 PM PDT 24
Finished Aug 08 08:06:41 PM PDT 24
Peak memory 575896 kb
Host smart-de21a7b8-f57b-43b0-ac21-13428ffddc1d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386187195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.3386187195
Directory /workspace/86.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.1803005596
Short name T2041
Test name
Test status
Simulation time 93290094359 ps
CPU time 1047.37 seconds
Started Aug 08 08:05:57 PM PDT 24
Finished Aug 08 08:23:25 PM PDT 24
Peak memory 575920 kb
Host smart-a974f71e-9b8c-4831-bd3b-0d3a5b37e630
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803005596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.1803005596
Directory /workspace/86.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.978152137
Short name T2550
Test name
Test status
Simulation time 18718102941 ps
CPU time 307.88 seconds
Started Aug 08 08:05:57 PM PDT 24
Finished Aug 08 08:11:05 PM PDT 24
Peak memory 576000 kb
Host smart-956763ba-52a3-46a2-9684-3b1ca211af1e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978152137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.978152137
Directory /workspace/86.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.3750075244
Short name T1578
Test name
Test status
Simulation time 301388421 ps
CPU time 25.63 seconds
Started Aug 08 08:05:57 PM PDT 24
Finished Aug 08 08:06:23 PM PDT 24
Peak memory 575696 kb
Host smart-0a4dcfcb-e448-4623-b33d-06731236693c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750075244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del
ays.3750075244
Directory /workspace/86.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_same_source.1178972170
Short name T577
Test name
Test status
Simulation time 333460616 ps
CPU time 23.94 seconds
Started Aug 08 08:06:01 PM PDT 24
Finished Aug 08 08:06:25 PM PDT 24
Peak memory 575920 kb
Host smart-9bf6200e-e8c4-43d9-84b4-6ec0f43d9d07
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178972170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.1178972170
Directory /workspace/86.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke.4005134252
Short name T2380
Test name
Test status
Simulation time 50210580 ps
CPU time 6.71 seconds
Started Aug 08 08:05:57 PM PDT 24
Finished Aug 08 08:06:04 PM PDT 24
Peak memory 573808 kb
Host smart-4ced7857-e7d3-4ae7-90e3-29c45edc8b8a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005134252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.4005134252
Directory /workspace/86.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.1571263135
Short name T2459
Test name
Test status
Simulation time 9809852178 ps
CPU time 106.11 seconds
Started Aug 08 08:05:58 PM PDT 24
Finished Aug 08 08:07:44 PM PDT 24
Peak memory 574552 kb
Host smart-51fbff52-22d5-46cf-aedc-4d8bd772c6e1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571263135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.1571263135
Directory /workspace/86.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.1512757551
Short name T2662
Test name
Test status
Simulation time 4994419500 ps
CPU time 82.96 seconds
Started Aug 08 08:05:58 PM PDT 24
Finished Aug 08 08:07:21 PM PDT 24
Peak memory 574640 kb
Host smart-f4a31659-b151-4821-a203-0fb01f820146
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512757551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.1512757551
Directory /workspace/86.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.268986637
Short name T1557
Test name
Test status
Simulation time 38881544 ps
CPU time 6.27 seconds
Started Aug 08 08:05:57 PM PDT 24
Finished Aug 08 08:06:03 PM PDT 24
Peak memory 574488 kb
Host smart-a8571b2d-2047-4a9a-b266-4d3cea245e57
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268986637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delays
.268986637
Directory /workspace/86.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all.3584580568
Short name T1549
Test name
Test status
Simulation time 2630742478 ps
CPU time 85.71 seconds
Started Aug 08 08:05:59 PM PDT 24
Finished Aug 08 08:07:24 PM PDT 24
Peak memory 576028 kb
Host smart-8de7132f-8aa2-44e1-99f1-91de85125292
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584580568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.3584580568
Directory /workspace/86.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.2926356817
Short name T1664
Test name
Test status
Simulation time 1011845437 ps
CPU time 84.17 seconds
Started Aug 08 08:06:09 PM PDT 24
Finished Aug 08 08:07:33 PM PDT 24
Peak memory 575880 kb
Host smart-96347047-eea3-4a8f-a530-da386386f62f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926356817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.2926356817
Directory /workspace/86.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.558061279
Short name T842
Test name
Test status
Simulation time 5540914705 ps
CPU time 433 seconds
Started Aug 08 08:06:09 PM PDT 24
Finished Aug 08 08:13:22 PM PDT 24
Peak memory 575952 kb
Host smart-b6dc88d5-e38e-44bf-ba74-35fc12f2e7f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558061279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_
with_rand_reset.558061279
Directory /workspace/86.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.592130168
Short name T1383
Test name
Test status
Simulation time 195291677 ps
CPU time 79.35 seconds
Started Aug 08 08:06:09 PM PDT 24
Finished Aug 08 08:07:29 PM PDT 24
Peak memory 576728 kb
Host smart-decd0bfc-b3f4-4583-b2b2-0369bd7fe946
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592130168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all
_with_reset_error.592130168
Directory /workspace/86.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.3257547057
Short name T1355
Test name
Test status
Simulation time 486990160 ps
CPU time 24.3 seconds
Started Aug 08 08:05:56 PM PDT 24
Finished Aug 08 08:06:20 PM PDT 24
Peak memory 575960 kb
Host smart-e14d7131-0189-42f2-aa6a-4919db55287c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257547057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.3257547057
Directory /workspace/86.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_access_same_device.3064874700
Short name T813
Test name
Test status
Simulation time 82783765 ps
CPU time 7.94 seconds
Started Aug 08 08:06:10 PM PDT 24
Finished Aug 08 08:06:18 PM PDT 24
Peak memory 573768 kb
Host smart-02c64827-7c97-46c2-884d-11c6b1087c61
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064874700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device
.3064874700
Directory /workspace/87.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.1335892007
Short name T770
Test name
Test status
Simulation time 31546926404 ps
CPU time 575.41 seconds
Started Aug 08 08:06:10 PM PDT 24
Finished Aug 08 08:15:47 PM PDT 24
Peak memory 576776 kb
Host smart-f43980fb-2c36-4f6d-8cda-00cff57f270c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335892007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_
device_slow_rsp.1335892007
Directory /workspace/87.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.1323147459
Short name T1399
Test name
Test status
Simulation time 1346990102 ps
CPU time 50.12 seconds
Started Aug 08 08:06:22 PM PDT 24
Finished Aug 08 08:07:12 PM PDT 24
Peak memory 575776 kb
Host smart-708ab241-64df-45de-95ea-7135d3cb29a6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323147459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add
r.1323147459
Directory /workspace/87.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_error_random.1924758547
Short name T1732
Test name
Test status
Simulation time 605070136 ps
CPU time 45.26 seconds
Started Aug 08 08:06:21 PM PDT 24
Finished Aug 08 08:07:07 PM PDT 24
Peak memory 575812 kb
Host smart-9d76fbd5-7ac9-49ca-87f0-47d1aa4b5e13
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924758547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.1924758547
Directory /workspace/87.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random.1200071778
Short name T2426
Test name
Test status
Simulation time 458402371 ps
CPU time 45.19 seconds
Started Aug 08 08:06:09 PM PDT 24
Finished Aug 08 08:06:55 PM PDT 24
Peak memory 575884 kb
Host smart-cb1b64c5-0bdd-43f7-8860-c97a698a1b68
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200071778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.1200071778
Directory /workspace/87.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.3827883867
Short name T2178
Test name
Test status
Simulation time 90248839279 ps
CPU time 1080.98 seconds
Started Aug 08 08:06:10 PM PDT 24
Finished Aug 08 08:24:11 PM PDT 24
Peak memory 576756 kb
Host smart-30ce176a-283f-461a-9dae-1c82b006fa0a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827883867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.3827883867
Directory /workspace/87.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.1937901913
Short name T504
Test name
Test status
Simulation time 51935088080 ps
CPU time 882.36 seconds
Started Aug 08 08:06:10 PM PDT 24
Finished Aug 08 08:20:53 PM PDT 24
Peak memory 575988 kb
Host smart-64338753-08e5-4510-8946-3b15f590e548
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937901913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.1937901913
Directory /workspace/87.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.2336451054
Short name T2618
Test name
Test status
Simulation time 534898928 ps
CPU time 45.2 seconds
Started Aug 08 08:06:12 PM PDT 24
Finished Aug 08 08:06:57 PM PDT 24
Peak memory 575744 kb
Host smart-b6701388-4f41-4f10-a3e3-11c4cd5e7683
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336451054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del
ays.2336451054
Directory /workspace/87.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_same_source.1913799165
Short name T536
Test name
Test status
Simulation time 533681868 ps
CPU time 42.46 seconds
Started Aug 08 08:06:08 PM PDT 24
Finished Aug 08 08:06:51 PM PDT 24
Peak memory 575776 kb
Host smart-8c6d1a5e-f1fc-442f-8a04-f8ca0806b63e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913799165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.1913799165
Directory /workspace/87.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke.871090638
Short name T1679
Test name
Test status
Simulation time 45707178 ps
CPU time 6.24 seconds
Started Aug 08 08:06:14 PM PDT 24
Finished Aug 08 08:06:20 PM PDT 24
Peak memory 574524 kb
Host smart-b3fa4182-a9e6-446f-923f-a6cc4306ad0c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871090638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.871090638
Directory /workspace/87.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.3711736339
Short name T1374
Test name
Test status
Simulation time 7300267819 ps
CPU time 77.59 seconds
Started Aug 08 08:06:10 PM PDT 24
Finished Aug 08 08:07:28 PM PDT 24
Peak memory 573932 kb
Host smart-c8267512-4e71-4d2a-86cd-b69286029610
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711736339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.3711736339
Directory /workspace/87.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.4009329064
Short name T2384
Test name
Test status
Simulation time 5384355842 ps
CPU time 93.91 seconds
Started Aug 08 08:06:09 PM PDT 24
Finished Aug 08 08:07:43 PM PDT 24
Peak memory 573900 kb
Host smart-d3f6f895-97f2-4f6f-8964-b7791e661a5b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009329064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.4009329064
Directory /workspace/87.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.2558104123
Short name T1544
Test name
Test status
Simulation time 47666933 ps
CPU time 6.63 seconds
Started Aug 08 08:06:09 PM PDT 24
Finished Aug 08 08:06:16 PM PDT 24
Peak memory 574440 kb
Host smart-4ac24fdf-33c9-4d8b-8c49-aca948495652
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558104123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay
s.2558104123
Directory /workspace/87.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all.149677729
Short name T1932
Test name
Test status
Simulation time 2713078445 ps
CPU time 217.63 seconds
Started Aug 08 08:06:21 PM PDT 24
Finished Aug 08 08:09:59 PM PDT 24
Peak memory 576008 kb
Host smart-4f884349-8f19-4009-b40e-aac1bc7210fb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149677729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.149677729
Directory /workspace/87.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.2429093553
Short name T638
Test name
Test status
Simulation time 1907121487 ps
CPU time 159.76 seconds
Started Aug 08 08:06:21 PM PDT 24
Finished Aug 08 08:09:01 PM PDT 24
Peak memory 576036 kb
Host smart-4d8b8dc0-37de-401c-9f19-e11b5bfb7130
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429093553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.2429093553
Directory /workspace/87.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3447298271
Short name T2527
Test name
Test status
Simulation time 15901687297 ps
CPU time 792.15 seconds
Started Aug 08 08:06:24 PM PDT 24
Finished Aug 08 08:19:36 PM PDT 24
Peak memory 576716 kb
Host smart-6a45a085-2c8b-41f6-b9db-1fd4ab107563
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447298271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all
_with_rand_reset.3447298271
Directory /workspace/87.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.789168281
Short name T826
Test name
Test status
Simulation time 3062444633 ps
CPU time 208.02 seconds
Started Aug 08 08:06:24 PM PDT 24
Finished Aug 08 08:09:52 PM PDT 24
Peak memory 576808 kb
Host smart-047f7c8e-f7c1-410d-a955-f556b6a7ba69
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789168281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all
_with_reset_error.789168281
Directory /workspace/87.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.726727031
Short name T437
Test name
Test status
Simulation time 345628453 ps
CPU time 16.41 seconds
Started Aug 08 08:06:26 PM PDT 24
Finished Aug 08 08:06:42 PM PDT 24
Peak memory 575824 kb
Host smart-6d60c174-48d5-4986-8d68-b8194226594d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726727031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.726727031
Directory /workspace/87.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_access_same_device.3447368079
Short name T1433
Test name
Test status
Simulation time 921703357 ps
CPU time 63.43 seconds
Started Aug 08 08:06:24 PM PDT 24
Finished Aug 08 08:07:28 PM PDT 24
Peak memory 575944 kb
Host smart-97a77773-9e38-4c54-8ef6-f232dd48bcb5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447368079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device
.3447368079
Directory /workspace/88.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.2279522169
Short name T2382
Test name
Test status
Simulation time 73020903119 ps
CPU time 1350.39 seconds
Started Aug 08 08:06:24 PM PDT 24
Finished Aug 08 08:28:55 PM PDT 24
Peak memory 576048 kb
Host smart-c6d20660-84d6-4839-8506-a142350d3cc7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279522169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_
device_slow_rsp.2279522169
Directory /workspace/88.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.1149016414
Short name T1837
Test name
Test status
Simulation time 81797353 ps
CPU time 10.31 seconds
Started Aug 08 08:06:20 PM PDT 24
Finished Aug 08 08:06:31 PM PDT 24
Peak memory 575792 kb
Host smart-5aca97a9-4e6c-415e-ba7c-32b6812bc03e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149016414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add
r.1149016414
Directory /workspace/88.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_error_random.519408584
Short name T2312
Test name
Test status
Simulation time 246926005 ps
CPU time 22.85 seconds
Started Aug 08 08:06:25 PM PDT 24
Finished Aug 08 08:06:47 PM PDT 24
Peak memory 575704 kb
Host smart-85e61f51-caaa-41ee-9a14-ca833d99cfad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519408584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.519408584
Directory /workspace/88.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random.3281468140
Short name T1751
Test name
Test status
Simulation time 1163549693 ps
CPU time 39.91 seconds
Started Aug 08 08:06:24 PM PDT 24
Finished Aug 08 08:07:04 PM PDT 24
Peak memory 575856 kb
Host smart-235873ae-0709-41d4-ab24-d60b4460be7e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281468140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.3281468140
Directory /workspace/88.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.2790840991
Short name T2131
Test name
Test status
Simulation time 33049546969 ps
CPU time 321.31 seconds
Started Aug 08 08:06:21 PM PDT 24
Finished Aug 08 08:11:42 PM PDT 24
Peak memory 576772 kb
Host smart-9ddc8ea0-4272-4ef2-9b39-9383182e8163
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790840991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.2790840991
Directory /workspace/88.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.3137894053
Short name T1704
Test name
Test status
Simulation time 45949441897 ps
CPU time 798.93 seconds
Started Aug 08 08:06:21 PM PDT 24
Finished Aug 08 08:19:40 PM PDT 24
Peak memory 575836 kb
Host smart-ff8767ef-bcf3-4def-9fc4-493573c75011
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137894053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.3137894053
Directory /workspace/88.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.1801681400
Short name T1781
Test name
Test status
Simulation time 178025755 ps
CPU time 17.55 seconds
Started Aug 08 08:06:22 PM PDT 24
Finished Aug 08 08:06:39 PM PDT 24
Peak memory 575812 kb
Host smart-cab407e4-e02a-49ec-a0c7-f155bb24552a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801681400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del
ays.1801681400
Directory /workspace/88.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_same_source.4026142291
Short name T1504
Test name
Test status
Simulation time 791108477 ps
CPU time 24.63 seconds
Started Aug 08 08:06:24 PM PDT 24
Finished Aug 08 08:06:49 PM PDT 24
Peak memory 575908 kb
Host smart-fd676f27-541b-41a0-8194-a1d70f794bf5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026142291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.4026142291
Directory /workspace/88.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke.3937935097
Short name T2828
Test name
Test status
Simulation time 248805625 ps
CPU time 10.18 seconds
Started Aug 08 08:06:21 PM PDT 24
Finished Aug 08 08:06:31 PM PDT 24
Peak memory 573792 kb
Host smart-dcabcc80-6916-4f74-ab82-44a66496d709
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937935097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.3937935097
Directory /workspace/88.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.3256415185
Short name T1506
Test name
Test status
Simulation time 5421395808 ps
CPU time 58.81 seconds
Started Aug 08 08:06:20 PM PDT 24
Finished Aug 08 08:07:19 PM PDT 24
Peak memory 573900 kb
Host smart-70cf7a05-201c-4edd-aadb-35293ced53ba
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256415185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.3256415185
Directory /workspace/88.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.4247691251
Short name T801
Test name
Test status
Simulation time 5435815944 ps
CPU time 89.91 seconds
Started Aug 08 08:06:20 PM PDT 24
Finished Aug 08 08:07:50 PM PDT 24
Peak memory 574652 kb
Host smart-8385b096-d0b4-4491-99d8-c271cb240f49
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247691251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.4247691251
Directory /workspace/88.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.2729367871
Short name T1394
Test name
Test status
Simulation time 35893136 ps
CPU time 5.53 seconds
Started Aug 08 08:06:21 PM PDT 24
Finished Aug 08 08:06:27 PM PDT 24
Peak memory 574468 kb
Host smart-61cb768c-2ef4-4295-b2cd-ffc1f1abaf7b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729367871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay
s.2729367871
Directory /workspace/88.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all.132321277
Short name T2742
Test name
Test status
Simulation time 6680607250 ps
CPU time 241.14 seconds
Started Aug 08 08:06:22 PM PDT 24
Finished Aug 08 08:10:24 PM PDT 24
Peak memory 576760 kb
Host smart-da66ccc5-fa21-4828-a8f4-2e96d4c2f23c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132321277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.132321277
Directory /workspace/88.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.617021458
Short name T516
Test name
Test status
Simulation time 728277863 ps
CPU time 66.6 seconds
Started Aug 08 08:06:36 PM PDT 24
Finished Aug 08 08:07:42 PM PDT 24
Peak memory 576060 kb
Host smart-07b96d53-3749-4283-a8af-76a75375049d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617021458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.617021458
Directory /workspace/88.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.406312879
Short name T2175
Test name
Test status
Simulation time 157563974 ps
CPU time 90.46 seconds
Started Aug 08 08:06:20 PM PDT 24
Finished Aug 08 08:07:51 PM PDT 24
Peak memory 576664 kb
Host smart-3e2eff31-12e2-4aa0-bc6e-a05e3a7d1399
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406312879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_
with_rand_reset.406312879
Directory /workspace/88.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.2811831673
Short name T2542
Test name
Test status
Simulation time 713276436 ps
CPU time 218.55 seconds
Started Aug 08 08:06:36 PM PDT 24
Finished Aug 08 08:10:15 PM PDT 24
Peak memory 575904 kb
Host smart-fe7fa90c-e854-46c7-8931-b96f3c9e0bf7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811831673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al
l_with_reset_error.2811831673
Directory /workspace/88.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.985910483
Short name T2194
Test name
Test status
Simulation time 792586299 ps
CPU time 33.27 seconds
Started Aug 08 08:06:24 PM PDT 24
Finished Aug 08 08:06:58 PM PDT 24
Peak memory 576000 kb
Host smart-464cef8d-b8fb-4f4d-a5fd-a897241181a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985910483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.985910483
Directory /workspace/88.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_access_same_device.85935007
Short name T1967
Test name
Test status
Simulation time 1044943312 ps
CPU time 55.29 seconds
Started Aug 08 08:06:33 PM PDT 24
Finished Aug 08 08:07:29 PM PDT 24
Peak memory 575728 kb
Host smart-2660132c-1f85-47c4-8a75-60e65a0579f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85935007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device.85935007
Directory /workspace/89.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.714817089
Short name T2623
Test name
Test status
Simulation time 90316863379 ps
CPU time 1649.98 seconds
Started Aug 08 08:06:35 PM PDT 24
Finished Aug 08 08:34:05 PM PDT 24
Peak memory 575996 kb
Host smart-04ce5942-f3c1-4fe4-b389-bdfbac101e4c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714817089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_d
evice_slow_rsp.714817089
Directory /workspace/89.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.3283030064
Short name T2043
Test name
Test status
Simulation time 145000749 ps
CPU time 9.5 seconds
Started Aug 08 08:06:50 PM PDT 24
Finished Aug 08 08:06:59 PM PDT 24
Peak memory 573888 kb
Host smart-5d7835f5-e3ae-44e4-bef1-6da0f74c1b3d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283030064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add
r.3283030064
Directory /workspace/89.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_error_random.904196913
Short name T1834
Test name
Test status
Simulation time 793197936 ps
CPU time 27.47 seconds
Started Aug 08 08:06:39 PM PDT 24
Finished Aug 08 08:07:06 PM PDT 24
Peak memory 575728 kb
Host smart-59004a65-9b4e-433b-885e-91ef8479f142
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904196913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.904196913
Directory /workspace/89.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random.4118781004
Short name T1862
Test name
Test status
Simulation time 2532987176 ps
CPU time 80.2 seconds
Started Aug 08 08:06:36 PM PDT 24
Finished Aug 08 08:07:57 PM PDT 24
Peak memory 575884 kb
Host smart-c0d47a3e-a14f-491c-83d3-693d185e4251
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118781004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.4118781004
Directory /workspace/89.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.647852803
Short name T1990
Test name
Test status
Simulation time 106097068607 ps
CPU time 1161.52 seconds
Started Aug 08 08:06:36 PM PDT 24
Finished Aug 08 08:25:57 PM PDT 24
Peak memory 575904 kb
Host smart-15095acc-6ac2-4f6b-9dcd-1e6ee44d0655
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647852803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.647852803
Directory /workspace/89.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.4048359130
Short name T1587
Test name
Test status
Simulation time 63217805283 ps
CPU time 1193.99 seconds
Started Aug 08 08:06:35 PM PDT 24
Finished Aug 08 08:26:30 PM PDT 24
Peak memory 575924 kb
Host smart-72da3343-2396-4b00-9905-abef54793ca1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048359130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.4048359130
Directory /workspace/89.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.2461652436
Short name T1574
Test name
Test status
Simulation time 206033128 ps
CPU time 18.01 seconds
Started Aug 08 08:06:38 PM PDT 24
Finished Aug 08 08:06:57 PM PDT 24
Peak memory 575748 kb
Host smart-218ec030-2a0a-4ac1-9677-90e568becd30
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461652436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del
ays.2461652436
Directory /workspace/89.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_same_source.3995236838
Short name T2002
Test name
Test status
Simulation time 2356758663 ps
CPU time 67.48 seconds
Started Aug 08 08:06:34 PM PDT 24
Finished Aug 08 08:07:41 PM PDT 24
Peak memory 575952 kb
Host smart-43f070b5-3197-413c-a45e-02032bd13325
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995236838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.3995236838
Directory /workspace/89.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke.1732795868
Short name T1424
Test name
Test status
Simulation time 160443912 ps
CPU time 8.16 seconds
Started Aug 08 08:06:32 PM PDT 24
Finished Aug 08 08:06:40 PM PDT 24
Peak memory 574444 kb
Host smart-68793cc9-30c3-4fe3-85c2-09229c707d8a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732795868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.1732795868
Directory /workspace/89.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.3772965646
Short name T1359
Test name
Test status
Simulation time 7055980662 ps
CPU time 78.22 seconds
Started Aug 08 08:06:35 PM PDT 24
Finished Aug 08 08:07:53 PM PDT 24
Peak memory 574528 kb
Host smart-0df3bab6-55a7-4527-b1de-c4951e2e1bbc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772965646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.3772965646
Directory /workspace/89.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.367110467
Short name T1417
Test name
Test status
Simulation time 4759387909 ps
CPU time 81.83 seconds
Started Aug 08 08:06:33 PM PDT 24
Finished Aug 08 08:07:55 PM PDT 24
Peak memory 574628 kb
Host smart-d6a7c6ae-ceb6-4174-9ffe-8ddad32a347b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367110467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.367110467
Directory /workspace/89.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.267380198
Short name T1977
Test name
Test status
Simulation time 44824589 ps
CPU time 6.39 seconds
Started Aug 08 08:06:34 PM PDT 24
Finished Aug 08 08:06:40 PM PDT 24
Peak memory 573768 kb
Host smart-b27d7bf1-6e40-4e7d-a9df-98075ed82001
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267380198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delays
.267380198
Directory /workspace/89.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all.980359410
Short name T605
Test name
Test status
Simulation time 6352766367 ps
CPU time 239.86 seconds
Started Aug 08 08:06:46 PM PDT 24
Finished Aug 08 08:10:46 PM PDT 24
Peak memory 576772 kb
Host smart-58a73c02-50a1-4c85-add2-72750f7b0307
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980359410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.980359410
Directory /workspace/89.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.240053440
Short name T2598
Test name
Test status
Simulation time 10156827753 ps
CPU time 387.34 seconds
Started Aug 08 08:06:44 PM PDT 24
Finished Aug 08 08:13:11 PM PDT 24
Peak memory 575952 kb
Host smart-4d73f30c-4f76-4c90-bfe5-c073ae0c0796
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240053440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.240053440
Directory /workspace/89.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.121516796
Short name T1872
Test name
Test status
Simulation time 9172559150 ps
CPU time 476.41 seconds
Started Aug 08 08:06:45 PM PDT 24
Finished Aug 08 08:14:41 PM PDT 24
Peak memory 576768 kb
Host smart-9ee50bab-769f-4e9b-8a17-33d67f55850c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121516796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all
_with_reset_error.121516796
Directory /workspace/89.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.2566794878
Short name T2021
Test name
Test status
Simulation time 764014224 ps
CPU time 31.46 seconds
Started Aug 08 08:06:46 PM PDT 24
Finished Aug 08 08:07:18 PM PDT 24
Peak memory 576000 kb
Host smart-2e872fa9-d0f3-4776-9f75-aeb72a3cefab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566794878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.2566794878
Directory /workspace/89.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.3915999451
Short name T2125
Test name
Test status
Simulation time 6008114820 ps
CPU time 373.38 seconds
Started Aug 08 07:51:31 PM PDT 24
Finished Aug 08 07:57:45 PM PDT 24
Peak memory 638624 kb
Host smart-2c75f544-2309-465f-ada4-6fd3fbd3df2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915999451 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.3915999451
Directory /workspace/9.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.chip_csr_rw.1693427806
Short name T2475
Test name
Test status
Simulation time 6241369866 ps
CPU time 522.84 seconds
Started Aug 08 07:51:27 PM PDT 24
Finished Aug 08 08:00:10 PM PDT 24
Peak memory 599284 kb
Host smart-d5a717a2-7b04-411d-8eb1-7ac538518ba0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693427806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.1693427806
Directory /workspace/9.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.3258227441
Short name T149
Test name
Test status
Simulation time 15945364698 ps
CPU time 1795.89 seconds
Started Aug 08 07:51:05 PM PDT 24
Finished Aug 08 08:21:01 PM PDT 24
Peak memory 592904 kb
Host smart-04fc0bd8-a4d6-4299-8017-a9a6abe6b2ef
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258227441 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.3258227441
Directory /workspace/9.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.chip_tl_errors.3422368313
Short name T2890
Test name
Test status
Simulation time 4415634585 ps
CPU time 270.76 seconds
Started Aug 08 07:51:06 PM PDT 24
Finished Aug 08 07:55:37 PM PDT 24
Peak memory 603744 kb
Host smart-d0c87593-8a98-4279-b5e5-2d0399810bda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422368313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.3422368313
Directory /workspace/9.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_access_same_device.906455868
Short name T2795
Test name
Test status
Simulation time 709762545 ps
CPU time 32.02 seconds
Started Aug 08 07:51:18 PM PDT 24
Finished Aug 08 07:51:50 PM PDT 24
Peak memory 575904 kb
Host smart-fb0048af-013b-471c-bff7-e3be689113af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906455868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.906455868
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.542033612
Short name T2813
Test name
Test status
Simulation time 64193001560 ps
CPU time 1115.09 seconds
Started Aug 08 07:51:17 PM PDT 24
Finished Aug 08 08:09:52 PM PDT 24
Peak memory 576056 kb
Host smart-8de680f2-9035-41e9-98b8-3f8bb3cbffc7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542033612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_de
vice_slow_rsp.542033612
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.88609298
Short name T2170
Test name
Test status
Simulation time 223203845 ps
CPU time 23.88 seconds
Started Aug 08 07:51:16 PM PDT 24
Finished Aug 08 07:51:40 PM PDT 24
Peak memory 575696 kb
Host smart-d389f329-3884-4f0a-bd4e-9b72e807c346
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88609298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.88609298
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_error_random.3835029466
Short name T2351
Test name
Test status
Simulation time 587124727 ps
CPU time 43.95 seconds
Started Aug 08 07:51:17 PM PDT 24
Finished Aug 08 07:52:02 PM PDT 24
Peak memory 575664 kb
Host smart-d6041300-8f1e-40f8-8e42-669f80b9f879
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835029466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3835029466
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random.3811033349
Short name T2759
Test name
Test status
Simulation time 912644798 ps
CPU time 30.74 seconds
Started Aug 08 07:51:06 PM PDT 24
Finished Aug 08 07:51:37 PM PDT 24
Peak memory 575740 kb
Host smart-83de3c02-1e49-4804-a6f4-914a44f8c34e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811033349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.3811033349
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.415781553
Short name T579
Test name
Test status
Simulation time 79429480831 ps
CPU time 803.65 seconds
Started Aug 08 07:51:17 PM PDT 24
Finished Aug 08 08:04:40 PM PDT 24
Peak memory 575860 kb
Host smart-7c17d396-e5ae-43c8-b80a-eb258f985ae0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415781553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.415781553
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.2538098752
Short name T2681
Test name
Test status
Simulation time 7313720322 ps
CPU time 121.53 seconds
Started Aug 08 07:51:19 PM PDT 24
Finished Aug 08 07:53:20 PM PDT 24
Peak memory 575916 kb
Host smart-3fe2cbeb-0411-4fbf-a5cd-604c9950c06f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538098752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2538098752
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.2136689707
Short name T1874
Test name
Test status
Simulation time 429208351 ps
CPU time 35.46 seconds
Started Aug 08 07:51:17 PM PDT 24
Finished Aug 08 07:51:53 PM PDT 24
Peak memory 575872 kb
Host smart-0cb6dff0-f7e3-4f51-aaf9-9075585493f7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136689707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela
ys.2136689707
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_same_source.824547454
Short name T2838
Test name
Test status
Simulation time 1446497705 ps
CPU time 43.13 seconds
Started Aug 08 07:51:21 PM PDT 24
Finished Aug 08 07:52:04 PM PDT 24
Peak memory 575868 kb
Host smart-a4256f6f-f028-4e9f-870f-54f4848956e4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824547454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.824547454
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke.2649051970
Short name T2253
Test name
Test status
Simulation time 224029483 ps
CPU time 9.27 seconds
Started Aug 08 07:51:07 PM PDT 24
Finished Aug 08 07:51:16 PM PDT 24
Peak memory 574468 kb
Host smart-461c21f6-51ea-41c4-8436-c641a7ed023d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649051970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2649051970
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.3100905387
Short name T2292
Test name
Test status
Simulation time 9807997418 ps
CPU time 103.45 seconds
Started Aug 08 07:51:06 PM PDT 24
Finished Aug 08 07:52:50 PM PDT 24
Peak memory 574600 kb
Host smart-d1f0cde2-d4c4-48cd-9c80-ba2cc3035971
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100905387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3100905387
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.1071399432
Short name T1706
Test name
Test status
Simulation time 5525730501 ps
CPU time 95.67 seconds
Started Aug 08 07:51:07 PM PDT 24
Finished Aug 08 07:52:43 PM PDT 24
Peak memory 573896 kb
Host smart-3aa3a2ee-4837-464c-b1c4-0ba395f31be2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071399432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1071399432
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.1540795099
Short name T1449
Test name
Test status
Simulation time 46231809 ps
CPU time 6.13 seconds
Started Aug 08 07:51:06 PM PDT 24
Finished Aug 08 07:51:12 PM PDT 24
Peak memory 573712 kb
Host smart-94d9b4dc-2ed1-4e25-80a1-f0e631d7908e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540795099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays
.1540795099
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all.4198566871
Short name T487
Test name
Test status
Simulation time 1577784296 ps
CPU time 126.57 seconds
Started Aug 08 07:51:17 PM PDT 24
Finished Aug 08 07:53:24 PM PDT 24
Peak memory 576292 kb
Host smart-17c4fc56-ed19-40eb-b95c-9d7df310604e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198566871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.4198566871
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.692742769
Short name T806
Test name
Test status
Simulation time 12115052009 ps
CPU time 479.25 seconds
Started Aug 08 07:51:16 PM PDT 24
Finished Aug 08 07:59:16 PM PDT 24
Peak memory 576776 kb
Host smart-30f5f532-c192-40fb-b1c2-070e4c37d18a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692742769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.692742769
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.1675600376
Short name T2642
Test name
Test status
Simulation time 521248885 ps
CPU time 84.13 seconds
Started Aug 08 07:51:17 PM PDT 24
Finished Aug 08 07:52:41 PM PDT 24
Peak memory 576700 kb
Host smart-707ef6e4-2bad-4898-92df-79a80b77e168
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675600376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_
with_rand_reset.1675600376
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.869657276
Short name T1447
Test name
Test status
Simulation time 158661185 ps
CPU time 9.36 seconds
Started Aug 08 07:51:16 PM PDT 24
Finished Aug 08 07:51:26 PM PDT 24
Peak memory 573924 kb
Host smart-f1d654d3-5192-4f4f-bb42-1f897490013f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869657276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.869657276
Directory /workspace/9.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_access_same_device.1932182194
Short name T2894
Test name
Test status
Simulation time 252599320 ps
CPU time 12.83 seconds
Started Aug 08 08:06:46 PM PDT 24
Finished Aug 08 08:06:59 PM PDT 24
Peak memory 574556 kb
Host smart-b7a18fb5-9d50-4508-81f5-9767879bd52f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932182194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device
.1932182194
Directory /workspace/90.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.1503071219
Short name T2189
Test name
Test status
Simulation time 106303909086 ps
CPU time 1993.54 seconds
Started Aug 08 08:06:47 PM PDT 24
Finished Aug 08 08:40:01 PM PDT 24
Peak memory 576048 kb
Host smart-dd5f257f-83a4-4583-90e8-a3dd02dc51fb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503071219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_
device_slow_rsp.1503071219
Directory /workspace/90.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.2391859053
Short name T1709
Test name
Test status
Simulation time 53662873 ps
CPU time 7.56 seconds
Started Aug 08 08:06:46 PM PDT 24
Finished Aug 08 08:06:53 PM PDT 24
Peak memory 575696 kb
Host smart-db229b82-e8eb-41c4-a760-1d491ddfb1fd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391859053 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add
r.2391859053
Directory /workspace/90.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_error_random.3576189592
Short name T2896
Test name
Test status
Simulation time 2206220589 ps
CPU time 75.65 seconds
Started Aug 08 08:06:50 PM PDT 24
Finished Aug 08 08:08:06 PM PDT 24
Peak memory 575752 kb
Host smart-fde0c372-3505-445e-99ce-b2889fd631bb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576189592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.3576189592
Directory /workspace/90.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random.3676313942
Short name T2098
Test name
Test status
Simulation time 303949899 ps
CPU time 26.95 seconds
Started Aug 08 08:06:50 PM PDT 24
Finished Aug 08 08:07:18 PM PDT 24
Peak memory 575764 kb
Host smart-6b5e8728-f616-4c45-8b22-4013001f3ffa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676313942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.3676313942
Directory /workspace/90.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.1207493699
Short name T2584
Test name
Test status
Simulation time 29473362625 ps
CPU time 301.54 seconds
Started Aug 08 08:06:45 PM PDT 24
Finished Aug 08 08:11:46 PM PDT 24
Peak memory 575796 kb
Host smart-28461ac3-ff36-4c3c-8116-e5aaad04c0e6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207493699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.1207493699
Directory /workspace/90.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.1977576496
Short name T2188
Test name
Test status
Simulation time 58873794283 ps
CPU time 976.28 seconds
Started Aug 08 08:06:51 PM PDT 24
Finished Aug 08 08:23:07 PM PDT 24
Peak memory 575956 kb
Host smart-19b281bb-1750-4f9f-96d1-776dbdd1b786
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977576496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.1977576496
Directory /workspace/90.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.4199293073
Short name T532
Test name
Test status
Simulation time 353003238 ps
CPU time 29.59 seconds
Started Aug 08 08:06:48 PM PDT 24
Finished Aug 08 08:07:18 PM PDT 24
Peak memory 575828 kb
Host smart-4bad8a46-8ba9-4f8a-98c0-8dc27233a73a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199293073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del
ays.4199293073
Directory /workspace/90.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_same_source.2935542199
Short name T2353
Test name
Test status
Simulation time 400320365 ps
CPU time 28.66 seconds
Started Aug 08 08:06:49 PM PDT 24
Finished Aug 08 08:07:18 PM PDT 24
Peak memory 575840 kb
Host smart-d79e0171-d552-401e-9606-26864c16031b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935542199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.2935542199
Directory /workspace/90.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke.3009163760
Short name T2468
Test name
Test status
Simulation time 52074192 ps
CPU time 6.54 seconds
Started Aug 08 08:06:46 PM PDT 24
Finished Aug 08 08:06:53 PM PDT 24
Peak memory 573828 kb
Host smart-93050a17-1e7f-4e4d-8471-21022d90228f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009163760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.3009163760
Directory /workspace/90.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.4252700369
Short name T1818
Test name
Test status
Simulation time 4786033638 ps
CPU time 47.21 seconds
Started Aug 08 08:06:46 PM PDT 24
Finished Aug 08 08:07:33 PM PDT 24
Peak memory 573912 kb
Host smart-651bba33-84cb-4321-bab6-9be7e473ef50
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252700369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.4252700369
Directory /workspace/90.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.2220582376
Short name T2083
Test name
Test status
Simulation time 4866573297 ps
CPU time 79.46 seconds
Started Aug 08 08:06:44 PM PDT 24
Finished Aug 08 08:08:04 PM PDT 24
Peak memory 573828 kb
Host smart-868d6818-c190-4561-bfc5-009c1ce74748
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220582376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.2220582376
Directory /workspace/90.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.1797157456
Short name T2805
Test name
Test status
Simulation time 42493992 ps
CPU time 6.05 seconds
Started Aug 08 08:06:45 PM PDT 24
Finished Aug 08 08:06:51 PM PDT 24
Peak memory 573800 kb
Host smart-e3ec120d-7a88-48ab-9eff-f6eeed74f91a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797157456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay
s.1797157456
Directory /workspace/90.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all.2366926531
Short name T2362
Test name
Test status
Simulation time 6447102581 ps
CPU time 248.86 seconds
Started Aug 08 08:06:56 PM PDT 24
Finished Aug 08 08:11:05 PM PDT 24
Peak memory 575896 kb
Host smart-5795a45a-f684-475e-a525-3cd902f2b3b7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366926531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.2366926531
Directory /workspace/90.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.939347274
Short name T2337
Test name
Test status
Simulation time 16147483258 ps
CPU time 637.78 seconds
Started Aug 08 08:07:00 PM PDT 24
Finished Aug 08 08:17:39 PM PDT 24
Peak memory 576048 kb
Host smart-991664cc-2577-4b37-b362-14c45fd51aa2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939347274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.939347274
Directory /workspace/90.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.2702194931
Short name T2316
Test name
Test status
Simulation time 3791934562 ps
CPU time 603.4 seconds
Started Aug 08 08:06:56 PM PDT 24
Finished Aug 08 08:16:59 PM PDT 24
Peak memory 576684 kb
Host smart-93d6e8bc-1f62-4dfa-ba3e-1bd84e76ad9b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702194931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all
_with_rand_reset.2702194931
Directory /workspace/90.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.1343567981
Short name T1419
Test name
Test status
Simulation time 2003787430 ps
CPU time 256.25 seconds
Started Aug 08 08:06:55 PM PDT 24
Finished Aug 08 08:11:12 PM PDT 24
Peak memory 576680 kb
Host smart-74c393a7-4983-43f6-80ca-9a83379ca00d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343567981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al
l_with_reset_error.1343567981
Directory /workspace/90.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.3149573911
Short name T2639
Test name
Test status
Simulation time 71365921 ps
CPU time 9.84 seconds
Started Aug 08 08:06:51 PM PDT 24
Finished Aug 08 08:07:01 PM PDT 24
Peak memory 575888 kb
Host smart-1b8d8953-4fad-4ca2-be41-165ab8413ea3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149573911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.3149573911
Directory /workspace/90.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_access_same_device.4065939301
Short name T1451
Test name
Test status
Simulation time 165802660 ps
CPU time 10.06 seconds
Started Aug 08 08:06:56 PM PDT 24
Finished Aug 08 08:07:07 PM PDT 24
Peak memory 574484 kb
Host smart-e5e9446a-beb0-422f-ae70-0eb41b37c243
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065939301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device
.4065939301
Directory /workspace/91.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.2973030851
Short name T2794
Test name
Test status
Simulation time 118064696514 ps
CPU time 2081.52 seconds
Started Aug 08 08:06:56 PM PDT 24
Finished Aug 08 08:41:38 PM PDT 24
Peak memory 576052 kb
Host smart-1e445ac4-43cc-49f2-b89d-4447254d1f67
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973030851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_
device_slow_rsp.2973030851
Directory /workspace/91.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.1016966796
Short name T2342
Test name
Test status
Simulation time 59824778 ps
CPU time 6.5 seconds
Started Aug 08 08:06:55 PM PDT 24
Finished Aug 08 08:07:01 PM PDT 24
Peak memory 573772 kb
Host smart-2f7f8f43-e542-4a55-98cb-8dc2edcd9a0e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016966796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add
r.1016966796
Directory /workspace/91.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_error_random.3725508515
Short name T2447
Test name
Test status
Simulation time 2400444480 ps
CPU time 91.29 seconds
Started Aug 08 08:06:58 PM PDT 24
Finished Aug 08 08:08:29 PM PDT 24
Peak memory 575976 kb
Host smart-72ee10c8-5b68-4ae4-a6cf-d6fe9a8120cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725508515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.3725508515
Directory /workspace/91.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random.2512197773
Short name T2645
Test name
Test status
Simulation time 266538237 ps
CPU time 23.8 seconds
Started Aug 08 08:06:56 PM PDT 24
Finished Aug 08 08:07:20 PM PDT 24
Peak memory 575948 kb
Host smart-d7973160-ec4a-44c6-9c52-e233856ef287
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512197773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.2512197773
Directory /workspace/91.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.1643517153
Short name T2743
Test name
Test status
Simulation time 94792871504 ps
CPU time 1063.02 seconds
Started Aug 08 08:06:56 PM PDT 24
Finished Aug 08 08:24:39 PM PDT 24
Peak memory 575812 kb
Host smart-f7887c9f-04a1-4c0c-98c3-016912e45395
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643517153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.1643517153
Directory /workspace/91.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.3385608755
Short name T1858
Test name
Test status
Simulation time 20871714904 ps
CPU time 354.63 seconds
Started Aug 08 08:06:56 PM PDT 24
Finished Aug 08 08:12:51 PM PDT 24
Peak memory 575832 kb
Host smart-b5e442da-8f03-4d0b-9ea4-3efbc340f3e4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385608755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.3385608755
Directory /workspace/91.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.388005006
Short name T589
Test name
Test status
Simulation time 415348757 ps
CPU time 39.31 seconds
Started Aug 08 08:06:55 PM PDT 24
Finished Aug 08 08:07:34 PM PDT 24
Peak memory 575876 kb
Host smart-01dd165b-666c-49fd-a98e-10eedc411419
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388005006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_dela
ys.388005006
Directory /workspace/91.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_same_source.3177201128
Short name T533
Test name
Test status
Simulation time 365711784 ps
CPU time 27.22 seconds
Started Aug 08 08:07:00 PM PDT 24
Finished Aug 08 08:07:27 PM PDT 24
Peak memory 575852 kb
Host smart-bfb5efdc-01d0-4078-935d-45b968124d77
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177201128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.3177201128
Directory /workspace/91.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke.2277524133
Short name T1707
Test name
Test status
Simulation time 229172692 ps
CPU time 8.7 seconds
Started Aug 08 08:06:58 PM PDT 24
Finished Aug 08 08:07:07 PM PDT 24
Peak memory 573776 kb
Host smart-6302f712-7d41-45e4-b3a0-e4db0a6d78b1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277524133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.2277524133
Directory /workspace/91.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.2074589225
Short name T1615
Test name
Test status
Simulation time 6846879177 ps
CPU time 70.33 seconds
Started Aug 08 08:06:58 PM PDT 24
Finished Aug 08 08:08:08 PM PDT 24
Peak memory 574636 kb
Host smart-97123eb7-33f5-486c-aaeb-1b9b2a091d5a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074589225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.2074589225
Directory /workspace/91.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.3636531272
Short name T2173
Test name
Test status
Simulation time 7403525972 ps
CPU time 128.43 seconds
Started Aug 08 08:06:56 PM PDT 24
Finished Aug 08 08:09:04 PM PDT 24
Peak memory 573852 kb
Host smart-8836cdff-f41a-4785-a135-920936659333
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636531272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.3636531272
Directory /workspace/91.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.1297760386
Short name T1897
Test name
Test status
Simulation time 41122954 ps
CPU time 6.02 seconds
Started Aug 08 08:06:56 PM PDT 24
Finished Aug 08 08:07:02 PM PDT 24
Peak memory 573800 kb
Host smart-c48204de-a757-4919-a425-5637e2517aaf
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297760386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay
s.1297760386
Directory /workspace/91.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all.2281063620
Short name T444
Test name
Test status
Simulation time 2108124171 ps
CPU time 195.96 seconds
Started Aug 08 08:06:58 PM PDT 24
Finished Aug 08 08:10:14 PM PDT 24
Peak memory 576700 kb
Host smart-6ec80cae-b326-4cf1-8b51-2d56a0a9744c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281063620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.2281063620
Directory /workspace/91.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.1933106221
Short name T2259
Test name
Test status
Simulation time 4101295452 ps
CPU time 552.52 seconds
Started Aug 08 08:06:56 PM PDT 24
Finished Aug 08 08:16:09 PM PDT 24
Peak memory 575980 kb
Host smart-5c5e24d7-0961-4bd5-93ca-735897209dc7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933106221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all
_with_rand_reset.1933106221
Directory /workspace/91.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.3912384347
Short name T2904
Test name
Test status
Simulation time 6095367948 ps
CPU time 569.4 seconds
Started Aug 08 08:06:56 PM PDT 24
Finished Aug 08 08:16:26 PM PDT 24
Peak memory 576636 kb
Host smart-88af1aa5-f2c2-4a51-a51f-86fb4d0f8b7c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912384347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al
l_with_reset_error.3912384347
Directory /workspace/91.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.136204861
Short name T600
Test name
Test status
Simulation time 746434809 ps
CPU time 26.25 seconds
Started Aug 08 08:06:59 PM PDT 24
Finished Aug 08 08:07:26 PM PDT 24
Peak memory 575844 kb
Host smart-0971af42-1642-496f-b995-776fc4beb2e3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136204861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.136204861
Directory /workspace/91.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_access_same_device.3236498145
Short name T2431
Test name
Test status
Simulation time 900649573 ps
CPU time 61.44 seconds
Started Aug 08 08:07:06 PM PDT 24
Finished Aug 08 08:08:07 PM PDT 24
Peak memory 575956 kb
Host smart-35304bb1-0011-4928-89c6-b34992fc46c7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236498145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device
.3236498145
Directory /workspace/92.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.1676779116
Short name T789
Test name
Test status
Simulation time 30203445593 ps
CPU time 573.15 seconds
Started Aug 08 08:07:07 PM PDT 24
Finished Aug 08 08:16:40 PM PDT 24
Peak memory 575848 kb
Host smart-3db369e9-00e9-4cc7-966c-752ae13ea8c8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676779116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_
device_slow_rsp.1676779116
Directory /workspace/92.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.2960565420
Short name T2866
Test name
Test status
Simulation time 359856163 ps
CPU time 18.96 seconds
Started Aug 08 08:07:06 PM PDT 24
Finished Aug 08 08:07:25 PM PDT 24
Peak memory 575960 kb
Host smart-f12a1e1c-995e-4179-955c-8150ee2dfe28
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960565420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add
r.2960565420
Directory /workspace/92.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_error_random.976402254
Short name T1676
Test name
Test status
Simulation time 655151476 ps
CPU time 22.22 seconds
Started Aug 08 08:07:09 PM PDT 24
Finished Aug 08 08:07:32 PM PDT 24
Peak memory 575924 kb
Host smart-fc0a9c9e-04b6-4e42-8c9f-3bc50a1f6e0a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976402254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.976402254
Directory /workspace/92.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random.2178363827
Short name T1813
Test name
Test status
Simulation time 267094856 ps
CPU time 20.8 seconds
Started Aug 08 08:07:08 PM PDT 24
Finished Aug 08 08:07:29 PM PDT 24
Peak memory 575868 kb
Host smart-2af920a8-26bf-4ed0-b58d-f2cfd7768765
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178363827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.2178363827
Directory /workspace/92.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.89703300
Short name T2668
Test name
Test status
Simulation time 13263652288 ps
CPU time 144.16 seconds
Started Aug 08 08:07:10 PM PDT 24
Finished Aug 08 08:09:34 PM PDT 24
Peak memory 575800 kb
Host smart-22cae94d-37a4-4565-9295-04c2123aefc8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89703300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.89703300
Directory /workspace/92.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.1651170616
Short name T1690
Test name
Test status
Simulation time 63261444208 ps
CPU time 1140.44 seconds
Started Aug 08 08:07:07 PM PDT 24
Finished Aug 08 08:26:07 PM PDT 24
Peak memory 576008 kb
Host smart-bf28231b-5a72-4a32-a64c-e8c78e7b83c7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651170616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.1651170616
Directory /workspace/92.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.2591370986
Short name T1767
Test name
Test status
Simulation time 314451855 ps
CPU time 31.45 seconds
Started Aug 08 08:07:05 PM PDT 24
Finished Aug 08 08:07:37 PM PDT 24
Peak memory 575720 kb
Host smart-b7906966-43c7-44aa-b2d8-64637f892fff
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591370986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del
ays.2591370986
Directory /workspace/92.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_same_source.4100358037
Short name T1901
Test name
Test status
Simulation time 354347652 ps
CPU time 25.06 seconds
Started Aug 08 08:07:08 PM PDT 24
Finished Aug 08 08:07:34 PM PDT 24
Peak memory 575776 kb
Host smart-87cd5ea6-c102-4a97-bf8c-4549098b68fd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100358037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.4100358037
Directory /workspace/92.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke.3552739086
Short name T1418
Test name
Test status
Simulation time 240568940 ps
CPU time 9.44 seconds
Started Aug 08 08:06:56 PM PDT 24
Finished Aug 08 08:07:06 PM PDT 24
Peak memory 574444 kb
Host smart-a7332912-b647-4e5e-a0ed-63f30c5933a4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552739086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.3552739086
Directory /workspace/92.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.3854388176
Short name T2080
Test name
Test status
Simulation time 7957533116 ps
CPU time 81.87 seconds
Started Aug 08 08:07:08 PM PDT 24
Finished Aug 08 08:08:30 PM PDT 24
Peak memory 573844 kb
Host smart-fce12ed2-91ca-42f1-8920-2f42a0f430b5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854388176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.3854388176
Directory /workspace/92.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.2246105658
Short name T1848
Test name
Test status
Simulation time 3028063057 ps
CPU time 48.85 seconds
Started Aug 08 08:07:08 PM PDT 24
Finished Aug 08 08:07:57 PM PDT 24
Peak memory 574540 kb
Host smart-f13295c6-98a9-4776-ae99-5b42ef70d69f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246105658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.2246105658
Directory /workspace/92.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.1118292899
Short name T1432
Test name
Test status
Simulation time 39982159 ps
CPU time 5.61 seconds
Started Aug 08 08:07:08 PM PDT 24
Finished Aug 08 08:07:14 PM PDT 24
Peak memory 573784 kb
Host smart-66e3fb8e-1e98-4f2e-a58e-bb182e422ed5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118292899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay
s.1118292899
Directory /workspace/92.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all.1496617751
Short name T2239
Test name
Test status
Simulation time 1219319748 ps
CPU time 86.34 seconds
Started Aug 08 08:07:06 PM PDT 24
Finished Aug 08 08:08:32 PM PDT 24
Peak memory 575992 kb
Host smart-56407146-ca67-4603-bb77-2d949a176fbe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496617751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.1496617751
Directory /workspace/92.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.708835234
Short name T2782
Test name
Test status
Simulation time 268919355 ps
CPU time 96.39 seconds
Started Aug 08 08:07:06 PM PDT 24
Finished Aug 08 08:08:43 PM PDT 24
Peak memory 575920 kb
Host smart-cc8cece8-14c6-4137-bed0-e75699baf1f8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708835234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_
with_rand_reset.708835234
Directory /workspace/92.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.2413990478
Short name T2713
Test name
Test status
Simulation time 3375358475 ps
CPU time 450.2 seconds
Started Aug 08 08:07:08 PM PDT 24
Finished Aug 08 08:14:38 PM PDT 24
Peak memory 575928 kb
Host smart-4720a8d5-8f80-44e5-a0f2-4746a0e0f87a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413990478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al
l_with_reset_error.2413990478
Directory /workspace/92.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.1590503094
Short name T1832
Test name
Test status
Simulation time 85434602 ps
CPU time 12.48 seconds
Started Aug 08 08:07:06 PM PDT 24
Finished Aug 08 08:07:19 PM PDT 24
Peak memory 575912 kb
Host smart-1a9661af-e503-4791-b979-eda97227539b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590503094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.1590503094
Directory /workspace/92.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_access_same_device.734356351
Short name T2347
Test name
Test status
Simulation time 2996678573 ps
CPU time 128.29 seconds
Started Aug 08 08:07:07 PM PDT 24
Finished Aug 08 08:09:15 PM PDT 24
Peak memory 575768 kb
Host smart-c5963a31-48b9-4646-8154-a39c74c77b41
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734356351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device.
734356351
Directory /workspace/93.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3850828980
Short name T2221
Test name
Test status
Simulation time 74908822111 ps
CPU time 1355.81 seconds
Started Aug 08 08:07:18 PM PDT 24
Finished Aug 08 08:29:54 PM PDT 24
Peak memory 576012 kb
Host smart-12e7c930-9795-4997-ab8e-ffef770425f5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850828980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_
device_slow_rsp.3850828980
Directory /workspace/93.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.634053304
Short name T1375
Test name
Test status
Simulation time 188417467 ps
CPU time 19.38 seconds
Started Aug 08 08:07:18 PM PDT 24
Finished Aug 08 08:07:37 PM PDT 24
Peak memory 575800 kb
Host smart-fd281aed-f438-4d58-a37b-46fc5d7b1977
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634053304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_addr
.634053304
Directory /workspace/93.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_error_random.3826574659
Short name T2610
Test name
Test status
Simulation time 580470431 ps
CPU time 23.11 seconds
Started Aug 08 08:07:16 PM PDT 24
Finished Aug 08 08:07:39 PM PDT 24
Peak memory 575880 kb
Host smart-250a975e-bc1b-475b-9aa6-8d067ab76b7d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826574659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.3826574659
Directory /workspace/93.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random.1026632987
Short name T2422
Test name
Test status
Simulation time 502417341 ps
CPU time 43.46 seconds
Started Aug 08 08:07:06 PM PDT 24
Finished Aug 08 08:07:50 PM PDT 24
Peak memory 575932 kb
Host smart-43ab81f2-7e93-42c2-add9-9a832c2456f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026632987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.1026632987
Directory /workspace/93.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.3288182373
Short name T1894
Test name
Test status
Simulation time 27496251565 ps
CPU time 273.16 seconds
Started Aug 08 08:07:06 PM PDT 24
Finished Aug 08 08:11:40 PM PDT 24
Peak memory 575844 kb
Host smart-3076853d-9946-4173-b8bf-f025e1248122
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288182373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.3288182373
Directory /workspace/93.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.3172651995
Short name T1841
Test name
Test status
Simulation time 35020818574 ps
CPU time 637.29 seconds
Started Aug 08 08:07:12 PM PDT 24
Finished Aug 08 08:17:50 PM PDT 24
Peak memory 576080 kb
Host smart-9afcced9-ba5c-4346-8ebd-8337154c9a15
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172651995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.3172651995
Directory /workspace/93.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.49069669
Short name T2423
Test name
Test status
Simulation time 218123388 ps
CPU time 21.71 seconds
Started Aug 08 08:07:11 PM PDT 24
Finished Aug 08 08:07:33 PM PDT 24
Peak memory 575752 kb
Host smart-7e9a30e4-694d-43c4-90ce-44f5dc2aa8e9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49069669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_delay
s.49069669
Directory /workspace/93.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_same_source.1964381172
Short name T2232
Test name
Test status
Simulation time 580011359 ps
CPU time 40.54 seconds
Started Aug 08 08:07:17 PM PDT 24
Finished Aug 08 08:07:57 PM PDT 24
Peak memory 575808 kb
Host smart-c80c6431-b02a-44f3-8566-0e31cb19c698
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964381172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.1964381172
Directory /workspace/93.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke.1796227919
Short name T1538
Test name
Test status
Simulation time 212048131 ps
CPU time 8.52 seconds
Started Aug 08 08:07:07 PM PDT 24
Finished Aug 08 08:07:15 PM PDT 24
Peak memory 573744 kb
Host smart-6863de72-7ad7-47b6-957d-cd873c0a19f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796227919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.1796227919
Directory /workspace/93.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.3992623679
Short name T1716
Test name
Test status
Simulation time 8299455506 ps
CPU time 91.63 seconds
Started Aug 08 08:07:09 PM PDT 24
Finished Aug 08 08:08:40 PM PDT 24
Peak memory 573876 kb
Host smart-501dd283-6867-4405-a099-e7c57639707a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992623679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.3992623679
Directory /workspace/93.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.730542053
Short name T2305
Test name
Test status
Simulation time 6164932579 ps
CPU time 103.32 seconds
Started Aug 08 08:07:12 PM PDT 24
Finished Aug 08 08:08:55 PM PDT 24
Peak memory 573940 kb
Host smart-36e2aecb-bd2b-4e60-b2a1-07afef97fe2d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730542053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.730542053
Directory /workspace/93.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2121750802
Short name T1535
Test name
Test status
Simulation time 40152075 ps
CPU time 5.82 seconds
Started Aug 08 08:07:08 PM PDT 24
Finished Aug 08 08:07:14 PM PDT 24
Peak memory 574456 kb
Host smart-42a810d1-64d4-4db5-90af-39bcc1d5b8f1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121750802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay
s.2121750802
Directory /workspace/93.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all.3437456753
Short name T1719
Test name
Test status
Simulation time 5617597577 ps
CPU time 206.34 seconds
Started Aug 08 08:07:18 PM PDT 24
Finished Aug 08 08:10:45 PM PDT 24
Peak memory 576056 kb
Host smart-9c63379d-8b7f-4210-a1d9-e09106d1a61a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437456753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.3437456753
Directory /workspace/93.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.3054363464
Short name T2252
Test name
Test status
Simulation time 1362509370 ps
CPU time 104.08 seconds
Started Aug 08 08:07:22 PM PDT 24
Finished Aug 08 08:09:06 PM PDT 24
Peak memory 575896 kb
Host smart-e5874a49-0038-4e05-ab06-76439b8a3852
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054363464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.3054363464
Directory /workspace/93.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1853577135
Short name T2053
Test name
Test status
Simulation time 2559807114 ps
CPU time 178.43 seconds
Started Aug 08 08:07:18 PM PDT 24
Finished Aug 08 08:10:16 PM PDT 24
Peak memory 576780 kb
Host smart-8f6e1a2f-9a4c-46ab-b348-72c457e1d835
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853577135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all
_with_rand_reset.1853577135
Directory /workspace/93.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.4162167133
Short name T515
Test name
Test status
Simulation time 12977032461 ps
CPU time 549.22 seconds
Started Aug 08 08:07:16 PM PDT 24
Finished Aug 08 08:16:25 PM PDT 24
Peak memory 576816 kb
Host smart-2d12ae1a-2293-4e4c-b4b0-7c476e685805
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162167133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al
l_with_reset_error.4162167133
Directory /workspace/93.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.2669038946
Short name T2518
Test name
Test status
Simulation time 269874277 ps
CPU time 31.51 seconds
Started Aug 08 08:07:22 PM PDT 24
Finished Aug 08 08:07:54 PM PDT 24
Peak memory 575868 kb
Host smart-b55061b1-80be-4636-8404-0610ae117aa4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669038946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.2669038946
Directory /workspace/93.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_access_same_device.2729981791
Short name T1720
Test name
Test status
Simulation time 1036129096 ps
CPU time 66.74 seconds
Started Aug 08 08:07:23 PM PDT 24
Finished Aug 08 08:08:30 PM PDT 24
Peak memory 575948 kb
Host smart-e6703dd7-5694-4f43-b887-cd2c4802c4fa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729981791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device
.2729981791
Directory /workspace/94.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.3057378870
Short name T2048
Test name
Test status
Simulation time 49763899165 ps
CPU time 882.82 seconds
Started Aug 08 08:07:21 PM PDT 24
Finished Aug 08 08:22:04 PM PDT 24
Peak memory 575876 kb
Host smart-237c9c2c-7637-40e6-b1f2-035eb9b6dbde
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057378870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_
device_slow_rsp.3057378870
Directory /workspace/94.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.3974711065
Short name T2037
Test name
Test status
Simulation time 36448380 ps
CPU time 6.52 seconds
Started Aug 08 08:07:18 PM PDT 24
Finished Aug 08 08:07:25 PM PDT 24
Peak memory 573796 kb
Host smart-737b39ea-67a8-41ae-bd7d-81f0ad820496
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974711065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add
r.3974711065
Directory /workspace/94.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_error_random.2164643034
Short name T1659
Test name
Test status
Simulation time 213456288 ps
CPU time 19.91 seconds
Started Aug 08 08:07:16 PM PDT 24
Finished Aug 08 08:07:36 PM PDT 24
Peak memory 575860 kb
Host smart-05920c3e-9565-497a-a787-7991469c60b0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164643034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.2164643034
Directory /workspace/94.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random.776054002
Short name T2839
Test name
Test status
Simulation time 208722640 ps
CPU time 21.16 seconds
Started Aug 08 08:07:18 PM PDT 24
Finished Aug 08 08:07:40 PM PDT 24
Peak memory 575924 kb
Host smart-f25d36a6-9515-41a2-8ca1-5b8e7ce6e01c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776054002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.776054002
Directory /workspace/94.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.856315036
Short name T2483
Test name
Test status
Simulation time 10964303494 ps
CPU time 120.29 seconds
Started Aug 08 08:07:22 PM PDT 24
Finished Aug 08 08:09:23 PM PDT 24
Peak memory 574704 kb
Host smart-88cabab6-a41b-4d0e-aa4a-9294ca6f2b67
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856315036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.856315036
Directory /workspace/94.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.4212814005
Short name T2715
Test name
Test status
Simulation time 5740527170 ps
CPU time 89.1 seconds
Started Aug 08 08:07:22 PM PDT 24
Finished Aug 08 08:08:51 PM PDT 24
Peak memory 574640 kb
Host smart-bb71cab3-7d00-480a-8c46-16ffe32705d9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212814005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.4212814005
Directory /workspace/94.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.4197277307
Short name T2078
Test name
Test status
Simulation time 285768897 ps
CPU time 24.51 seconds
Started Aug 08 08:07:16 PM PDT 24
Finished Aug 08 08:07:41 PM PDT 24
Peak memory 575816 kb
Host smart-b3e69d8f-2f06-4890-af1c-743acfdb71a6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197277307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del
ays.4197277307
Directory /workspace/94.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_same_source.1844826265
Short name T2019
Test name
Test status
Simulation time 259801281 ps
CPU time 20.38 seconds
Started Aug 08 08:07:22 PM PDT 24
Finished Aug 08 08:07:42 PM PDT 24
Peak memory 575744 kb
Host smart-21508e59-6f80-41cd-b2c8-6f40f272387f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844826265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.1844826265
Directory /workspace/94.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke.1791152369
Short name T2888
Test name
Test status
Simulation time 45869881 ps
CPU time 6.39 seconds
Started Aug 08 08:07:18 PM PDT 24
Finished Aug 08 08:07:24 PM PDT 24
Peak memory 573844 kb
Host smart-e3df9f7f-2a0b-41ad-9505-a0af16c0f302
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791152369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.1791152369
Directory /workspace/94.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.2499414467
Short name T1517
Test name
Test status
Simulation time 11043748448 ps
CPU time 120.16 seconds
Started Aug 08 08:07:16 PM PDT 24
Finished Aug 08 08:09:16 PM PDT 24
Peak memory 573940 kb
Host smart-86f63297-5b4b-4ced-b40b-e2cf9066cb89
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499414467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.2499414467
Directory /workspace/94.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.2645682945
Short name T1930
Test name
Test status
Simulation time 5855284204 ps
CPU time 96.88 seconds
Started Aug 08 08:07:22 PM PDT 24
Finished Aug 08 08:08:59 PM PDT 24
Peak memory 574600 kb
Host smart-6c85f62e-4c42-4800-ad37-5d4e8192bd2a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645682945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.2645682945
Directory /workspace/94.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.3322277587
Short name T2340
Test name
Test status
Simulation time 44208522 ps
CPU time 6.33 seconds
Started Aug 08 08:07:20 PM PDT 24
Finished Aug 08 08:07:27 PM PDT 24
Peak memory 574448 kb
Host smart-55f6d778-2270-4561-b119-e7529d756fd4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322277587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay
s.3322277587
Directory /workspace/94.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all.975774955
Short name T2725
Test name
Test status
Simulation time 453142395 ps
CPU time 16.32 seconds
Started Aug 08 08:07:18 PM PDT 24
Finished Aug 08 08:07:34 PM PDT 24
Peak memory 575716 kb
Host smart-7169922f-57f0-42c6-b4e1-d729c5ea7638
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975774955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.975774955
Directory /workspace/94.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.4259833131
Short name T2895
Test name
Test status
Simulation time 1673878900 ps
CPU time 121.04 seconds
Started Aug 08 08:07:26 PM PDT 24
Finished Aug 08 08:09:27 PM PDT 24
Peak memory 576544 kb
Host smart-ad0e84c2-efe7-4f1b-8b53-55b776a3513a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259833131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.4259833131
Directory /workspace/94.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.2387559342
Short name T2879
Test name
Test status
Simulation time 476289686 ps
CPU time 57.33 seconds
Started Aug 08 08:07:26 PM PDT 24
Finished Aug 08 08:08:24 PM PDT 24
Peak memory 575872 kb
Host smart-ace2685c-f16e-42a9-96a0-d87f062e7919
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387559342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all
_with_rand_reset.2387559342
Directory /workspace/94.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.2163008350
Short name T2575
Test name
Test status
Simulation time 267332604 ps
CPU time 70.34 seconds
Started Aug 08 08:07:28 PM PDT 24
Finished Aug 08 08:08:38 PM PDT 24
Peak memory 576856 kb
Host smart-04e34265-bb43-4768-be4d-113176d7aae9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163008350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al
l_with_reset_error.2163008350
Directory /workspace/94.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.99088476
Short name T1995
Test name
Test status
Simulation time 37609702 ps
CPU time 7.27 seconds
Started Aug 08 08:07:19 PM PDT 24
Finished Aug 08 08:07:27 PM PDT 24
Peak memory 573824 kb
Host smart-9216740b-d63a-47bc-b31f-cc6e620606b3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99088476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.99088476
Directory /workspace/94.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_access_same_device.753282450
Short name T1955
Test name
Test status
Simulation time 823947889 ps
CPU time 34.65 seconds
Started Aug 08 08:07:27 PM PDT 24
Finished Aug 08 08:08:01 PM PDT 24
Peak memory 575944 kb
Host smart-6ce4a611-9ca2-402c-863e-6a199368afde
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753282450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device.
753282450
Directory /workspace/95.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.893673865
Short name T2301
Test name
Test status
Simulation time 828850551 ps
CPU time 35.52 seconds
Started Aug 08 08:07:26 PM PDT 24
Finished Aug 08 08:08:02 PM PDT 24
Peak memory 575920 kb
Host smart-99408ff9-5cf0-4550-8d58-6d99dbf46a49
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893673865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_addr
.893673865
Directory /workspace/95.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_error_random.3422938990
Short name T1641
Test name
Test status
Simulation time 396706664 ps
CPU time 32.17 seconds
Started Aug 08 08:07:32 PM PDT 24
Finished Aug 08 08:08:05 PM PDT 24
Peak memory 575732 kb
Host smart-e938095f-d4f3-431e-92ef-8e686099b3ae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422938990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.3422938990
Directory /workspace/95.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random.1522669724
Short name T1718
Test name
Test status
Simulation time 511484700 ps
CPU time 45.6 seconds
Started Aug 08 08:07:27 PM PDT 24
Finished Aug 08 08:08:12 PM PDT 24
Peak memory 575972 kb
Host smart-b6608147-c7f7-4a0c-a7c0-fb86927a1208
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522669724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.1522669724
Directory /workspace/95.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.1827702130
Short name T2476
Test name
Test status
Simulation time 97172383160 ps
CPU time 1092.63 seconds
Started Aug 08 08:07:32 PM PDT 24
Finished Aug 08 08:25:45 PM PDT 24
Peak memory 575988 kb
Host smart-4e5056dc-17cf-48b5-90b1-2e342d995063
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827702130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.1827702130
Directory /workspace/95.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.2145100115
Short name T1678
Test name
Test status
Simulation time 12488028610 ps
CPU time 202.44 seconds
Started Aug 08 08:07:25 PM PDT 24
Finished Aug 08 08:10:48 PM PDT 24
Peak memory 575864 kb
Host smart-f5fd1cc3-a22c-427b-81fe-1e8a51766cbd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145100115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.2145100115
Directory /workspace/95.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.1192964438
Short name T2543
Test name
Test status
Simulation time 365364772 ps
CPU time 28.17 seconds
Started Aug 08 08:07:27 PM PDT 24
Finished Aug 08 08:07:55 PM PDT 24
Peak memory 575764 kb
Host smart-a374221d-2e04-44a9-83b0-ecd2c46d2b28
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192964438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del
ays.1192964438
Directory /workspace/95.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_same_source.2353067033
Short name T2745
Test name
Test status
Simulation time 192570144 ps
CPU time 15.55 seconds
Started Aug 08 08:07:27 PM PDT 24
Finished Aug 08 08:07:43 PM PDT 24
Peak memory 575796 kb
Host smart-cce9fd9d-9a94-4f1c-a63c-8a12e597168d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353067033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.2353067033
Directory /workspace/95.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke.1284759381
Short name T2057
Test name
Test status
Simulation time 178679924 ps
CPU time 7.88 seconds
Started Aug 08 08:07:25 PM PDT 24
Finished Aug 08 08:07:33 PM PDT 24
Peak memory 573736 kb
Host smart-93e05df2-6307-4b1f-aafa-036f0ace685d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284759381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.1284759381
Directory /workspace/95.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.141107021
Short name T1563
Test name
Test status
Simulation time 6021602435 ps
CPU time 63.98 seconds
Started Aug 08 08:07:32 PM PDT 24
Finished Aug 08 08:08:36 PM PDT 24
Peak memory 573852 kb
Host smart-456f8dc4-c314-4a8e-bfe1-4e895ba6149c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141107021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.141107021
Directory /workspace/95.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.1681720271
Short name T2119
Test name
Test status
Simulation time 3782577680 ps
CPU time 63.19 seconds
Started Aug 08 08:07:29 PM PDT 24
Finished Aug 08 08:08:33 PM PDT 24
Peak memory 574544 kb
Host smart-8e8d9923-526b-4004-8221-42803817bc2a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681720271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.1681720271
Directory /workspace/95.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.236221217
Short name T1896
Test name
Test status
Simulation time 38109557 ps
CPU time 5.58 seconds
Started Aug 08 08:07:27 PM PDT 24
Finished Aug 08 08:07:32 PM PDT 24
Peak memory 573740 kb
Host smart-6a5c7ae9-7d6d-473d-b0a3-a89da4d03087
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236221217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delays
.236221217
Directory /workspace/95.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all.3764125740
Short name T2156
Test name
Test status
Simulation time 2449501980 ps
CPU time 102.74 seconds
Started Aug 08 08:07:26 PM PDT 24
Finished Aug 08 08:09:09 PM PDT 24
Peak memory 575960 kb
Host smart-d0db3b9b-a576-47ba-bb56-d2d9bba04708
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764125740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.3764125740
Directory /workspace/95.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.3055082718
Short name T2180
Test name
Test status
Simulation time 10297914919 ps
CPU time 363.93 seconds
Started Aug 08 08:07:28 PM PDT 24
Finished Aug 08 08:13:32 PM PDT 24
Peak memory 576112 kb
Host smart-0b86e84e-a7c4-4c78-984d-11d572bd40ac
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055082718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.3055082718
Directory /workspace/95.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.3351157630
Short name T494
Test name
Test status
Simulation time 14934571436 ps
CPU time 853.77 seconds
Started Aug 08 08:07:25 PM PDT 24
Finished Aug 08 08:21:39 PM PDT 24
Peak memory 575912 kb
Host smart-f40d6d36-fbc5-4edf-b299-6a7f31b21fd1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351157630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all
_with_rand_reset.3351157630
Directory /workspace/95.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.2695548252
Short name T828
Test name
Test status
Simulation time 227200479 ps
CPU time 83.3 seconds
Started Aug 08 08:07:25 PM PDT 24
Finished Aug 08 08:08:49 PM PDT 24
Peak memory 575892 kb
Host smart-3a0685e9-b69c-490b-92d1-0cb0ca80aa14
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695548252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al
l_with_reset_error.2695548252
Directory /workspace/95.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.1546920782
Short name T1539
Test name
Test status
Simulation time 272540299 ps
CPU time 28.01 seconds
Started Aug 08 08:07:26 PM PDT 24
Finished Aug 08 08:07:54 PM PDT 24
Peak memory 575880 kb
Host smart-684b0dc3-85ea-4835-bcc6-62328ac44fca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546920782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.1546920782
Directory /workspace/95.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_access_same_device.2836288665
Short name T2840
Test name
Test status
Simulation time 694493047 ps
CPU time 53.68 seconds
Started Aug 08 08:07:40 PM PDT 24
Finished Aug 08 08:08:34 PM PDT 24
Peak memory 575844 kb
Host smart-07cb8413-5317-4020-b70e-6b4c792c2d17
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836288665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device
.2836288665
Directory /workspace/96.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.877587539
Short name T1880
Test name
Test status
Simulation time 95778653611 ps
CPU time 1794.31 seconds
Started Aug 08 08:07:35 PM PDT 24
Finished Aug 08 08:37:30 PM PDT 24
Peak memory 576024 kb
Host smart-7d1ddd56-ec2a-41c6-bd26-c4867f2b7943
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877587539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_d
evice_slow_rsp.877587539
Directory /workspace/96.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.279423871
Short name T1961
Test name
Test status
Simulation time 143646885 ps
CPU time 17.88 seconds
Started Aug 08 08:07:48 PM PDT 24
Finished Aug 08 08:08:06 PM PDT 24
Peak memory 575960 kb
Host smart-d5b1eb43-5d48-4f74-ac5c-b853f57fc0e7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279423871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_addr
.279423871
Directory /workspace/96.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_error_random.2952666701
Short name T2541
Test name
Test status
Simulation time 1617196982 ps
CPU time 63.26 seconds
Started Aug 08 08:07:36 PM PDT 24
Finished Aug 08 08:08:40 PM PDT 24
Peak memory 575708 kb
Host smart-d2f53cc9-902a-4a9f-bb59-0be367fd2369
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952666701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.2952666701
Directory /workspace/96.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random.3689778424
Short name T1613
Test name
Test status
Simulation time 2058655952 ps
CPU time 85.21 seconds
Started Aug 08 08:07:36 PM PDT 24
Finished Aug 08 08:09:01 PM PDT 24
Peak memory 575844 kb
Host smart-30490460-f659-4633-b7b5-e31f7a1d0873
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689778424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.3689778424
Directory /workspace/96.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.671073673
Short name T1568
Test name
Test status
Simulation time 60727392093 ps
CPU time 653.53 seconds
Started Aug 08 08:07:38 PM PDT 24
Finished Aug 08 08:18:31 PM PDT 24
Peak memory 575908 kb
Host smart-8cd3dfbf-3e52-4692-82bc-9caf36edea33
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671073673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.671073673
Directory /workspace/96.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.3321726545
Short name T2628
Test name
Test status
Simulation time 32939006899 ps
CPU time 587.12 seconds
Started Aug 08 08:07:35 PM PDT 24
Finished Aug 08 08:17:23 PM PDT 24
Peak memory 575828 kb
Host smart-e3bcee1e-4fad-4f14-812b-923e6ec53d2e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321726545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.3321726545
Directory /workspace/96.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.634199570
Short name T2149
Test name
Test status
Simulation time 619034316 ps
CPU time 50.52 seconds
Started Aug 08 08:07:36 PM PDT 24
Finished Aug 08 08:08:27 PM PDT 24
Peak memory 575944 kb
Host smart-61fb3fe9-4329-4b50-8022-aafc5e73f98b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634199570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_dela
ys.634199570
Directory /workspace/96.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_same_source.111401261
Short name T1738
Test name
Test status
Simulation time 689849927 ps
CPU time 20.93 seconds
Started Aug 08 08:07:40 PM PDT 24
Finished Aug 08 08:08:01 PM PDT 24
Peak memory 575852 kb
Host smart-5bf42738-0059-42c3-ba79-436feb44eb43
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111401261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.111401261
Directory /workspace/96.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke.1159273341
Short name T1373
Test name
Test status
Simulation time 194926461 ps
CPU time 8.74 seconds
Started Aug 08 08:07:37 PM PDT 24
Finished Aug 08 08:07:46 PM PDT 24
Peak memory 574420 kb
Host smart-4dcb1905-c4a7-46ea-bf88-95e7fede4a48
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159273341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.1159273341
Directory /workspace/96.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.1595739304
Short name T2416
Test name
Test status
Simulation time 8176537949 ps
CPU time 83.02 seconds
Started Aug 08 08:07:36 PM PDT 24
Finished Aug 08 08:08:59 PM PDT 24
Peak memory 574528 kb
Host smart-7ff483b4-a8f5-4915-b883-8b1ff48c0853
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595739304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.1595739304
Directory /workspace/96.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.3480668810
Short name T2814
Test name
Test status
Simulation time 4466150816 ps
CPU time 75.78 seconds
Started Aug 08 08:07:39 PM PDT 24
Finished Aug 08 08:08:55 PM PDT 24
Peak memory 573808 kb
Host smart-e4cfbf41-e929-44b3-a992-ce7ed3f5d90a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480668810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.3480668810
Directory /workspace/96.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.3284104928
Short name T2392
Test name
Test status
Simulation time 42850076 ps
CPU time 6.17 seconds
Started Aug 08 08:07:36 PM PDT 24
Finished Aug 08 08:07:42 PM PDT 24
Peak memory 573768 kb
Host smart-95edf1db-f946-402f-b781-961446bd3ae8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284104928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay
s.3284104928
Directory /workspace/96.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all.2484241454
Short name T476
Test name
Test status
Simulation time 1101900859 ps
CPU time 90.47 seconds
Started Aug 08 08:07:45 PM PDT 24
Finished Aug 08 08:09:16 PM PDT 24
Peak memory 575924 kb
Host smart-411f025f-802b-400a-9267-5d580d330ad0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484241454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.2484241454
Directory /workspace/96.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.984600733
Short name T1705
Test name
Test status
Simulation time 349676588 ps
CPU time 28.48 seconds
Started Aug 08 08:07:48 PM PDT 24
Finished Aug 08 08:08:16 PM PDT 24
Peak memory 575864 kb
Host smart-fe7ff7fd-14de-4288-9148-2b2344e7dc20
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984600733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.984600733
Directory /workspace/96.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.1805783524
Short name T2936
Test name
Test status
Simulation time 2289706918 ps
CPU time 126.43 seconds
Started Aug 08 08:07:47 PM PDT 24
Finished Aug 08 08:09:54 PM PDT 24
Peak memory 575972 kb
Host smart-b77cd75f-b39b-4b65-a487-cf98e44eb52c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805783524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all
_with_rand_reset.1805783524
Directory /workspace/96.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.253852917
Short name T1721
Test name
Test status
Simulation time 2192706779 ps
CPU time 116.91 seconds
Started Aug 08 08:07:45 PM PDT 24
Finished Aug 08 08:09:42 PM PDT 24
Peak memory 576804 kb
Host smart-119b3678-d179-4c8f-a047-69f3532e52b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253852917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all
_with_reset_error.253852917
Directory /workspace/96.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.3178560941
Short name T2505
Test name
Test status
Simulation time 333319882 ps
CPU time 39.32 seconds
Started Aug 08 08:07:38 PM PDT 24
Finished Aug 08 08:08:17 PM PDT 24
Peak memory 575960 kb
Host smart-71038ee8-9a58-43e7-bbac-74bacf0348f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178560941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.3178560941
Directory /workspace/96.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_access_same_device.1734163852
Short name T2144
Test name
Test status
Simulation time 2167243692 ps
CPU time 90.71 seconds
Started Aug 08 08:07:46 PM PDT 24
Finished Aug 08 08:09:17 PM PDT 24
Peak memory 575888 kb
Host smart-9b9482e9-b401-4ea9-9eb4-38bfbe27f004
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734163852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device
.1734163852
Directory /workspace/97.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1598414438
Short name T817
Test name
Test status
Simulation time 26729344402 ps
CPU time 473.61 seconds
Started Aug 08 08:07:48 PM PDT 24
Finished Aug 08 08:15:42 PM PDT 24
Peak memory 576016 kb
Host smart-55756e43-8130-4171-aaa2-308a8e0d76be
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598414438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_
device_slow_rsp.1598414438
Directory /workspace/97.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.4127684829
Short name T2779
Test name
Test status
Simulation time 1168945407 ps
CPU time 41.2 seconds
Started Aug 08 08:07:55 PM PDT 24
Finished Aug 08 08:08:37 PM PDT 24
Peak memory 575940 kb
Host smart-e3241047-654c-45dd-98a4-e743fc681cbc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127684829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add
r.4127684829
Directory /workspace/97.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_error_random.1815361109
Short name T1946
Test name
Test status
Simulation time 2235714175 ps
CPU time 75.28 seconds
Started Aug 08 08:07:55 PM PDT 24
Finished Aug 08 08:09:11 PM PDT 24
Peak memory 575900 kb
Host smart-000836dd-7a44-4679-9166-a61693c9d8b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815361109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.1815361109
Directory /workspace/97.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random.884841686
Short name T2060
Test name
Test status
Simulation time 2349461772 ps
CPU time 90.61 seconds
Started Aug 08 08:07:45 PM PDT 24
Finished Aug 08 08:09:16 PM PDT 24
Peak memory 575900 kb
Host smart-a8c56786-690d-442a-9e2b-bfe7822e0741
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884841686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.884841686
Directory /workspace/97.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.933174680
Short name T1478
Test name
Test status
Simulation time 10333641778 ps
CPU time 116.7 seconds
Started Aug 08 08:07:46 PM PDT 24
Finished Aug 08 08:09:42 PM PDT 24
Peak memory 576004 kb
Host smart-887914b4-de78-4e46-bc0a-eba98fe39d6c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933174680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.933174680
Directory /workspace/97.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.359030794
Short name T2551
Test name
Test status
Simulation time 63719168826 ps
CPU time 1151.34 seconds
Started Aug 08 08:07:46 PM PDT 24
Finished Aug 08 08:26:57 PM PDT 24
Peak memory 575844 kb
Host smart-9a6f5db0-0f7c-4b77-92a4-8b5166f1a03f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359030794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.359030794
Directory /workspace/97.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.2290560532
Short name T1599
Test name
Test status
Simulation time 273462820 ps
CPU time 27 seconds
Started Aug 08 08:07:46 PM PDT 24
Finished Aug 08 08:08:13 PM PDT 24
Peak memory 575824 kb
Host smart-c841b243-b66a-4052-9e3a-90841dca079f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290560532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del
ays.2290560532
Directory /workspace/97.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_same_source.3056213907
Short name T1757
Test name
Test status
Simulation time 334839969 ps
CPU time 24.2 seconds
Started Aug 08 08:07:55 PM PDT 24
Finished Aug 08 08:08:19 PM PDT 24
Peak memory 575880 kb
Host smart-e5645e9e-b086-47cd-a69e-a2453686cbf1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056213907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.3056213907
Directory /workspace/97.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke.439490326
Short name T593
Test name
Test status
Simulation time 49871334 ps
CPU time 6.63 seconds
Started Aug 08 08:07:46 PM PDT 24
Finished Aug 08 08:07:53 PM PDT 24
Peak memory 574500 kb
Host smart-6d84c96a-da68-44c6-bef3-9e242ff20cdb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439490326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.439490326
Directory /workspace/97.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.3394495264
Short name T2489
Test name
Test status
Simulation time 8048181223 ps
CPU time 85.41 seconds
Started Aug 08 08:07:45 PM PDT 24
Finished Aug 08 08:09:11 PM PDT 24
Peak memory 573872 kb
Host smart-fb29d644-9f1f-49e2-a105-ee9bf3c54089
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394495264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.3394495264
Directory /workspace/97.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.1055759315
Short name T2882
Test name
Test status
Simulation time 5166549135 ps
CPU time 84.77 seconds
Started Aug 08 08:07:46 PM PDT 24
Finished Aug 08 08:09:10 PM PDT 24
Peak memory 574604 kb
Host smart-b81ce307-6e72-4112-9ce6-1279b128be34
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055759315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.1055759315
Directory /workspace/97.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.1804315754
Short name T2756
Test name
Test status
Simulation time 47407088 ps
CPU time 6.38 seconds
Started Aug 08 08:07:46 PM PDT 24
Finished Aug 08 08:07:53 PM PDT 24
Peak memory 573972 kb
Host smart-81f51b00-07ef-4848-8d9c-9141f199e9b7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804315754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay
s.1804315754
Directory /workspace/97.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all.1557340383
Short name T776
Test name
Test status
Simulation time 3932686373 ps
CPU time 169.16 seconds
Started Aug 08 08:07:57 PM PDT 24
Finished Aug 08 08:10:46 PM PDT 24
Peak memory 575928 kb
Host smart-8f0d12f2-fdf2-4209-9ec7-f257243a7478
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557340383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.1557340383
Directory /workspace/97.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.2649724484
Short name T1643
Test name
Test status
Simulation time 10121257503 ps
CPU time 360.06 seconds
Started Aug 08 08:07:57 PM PDT 24
Finished Aug 08 08:13:57 PM PDT 24
Peak memory 576780 kb
Host smart-c05647cc-c88f-4ec9-8084-33e378ef6480
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649724484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.2649724484
Directory /workspace/97.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.2953274521
Short name T2930
Test name
Test status
Simulation time 5203903802 ps
CPU time 692.19 seconds
Started Aug 08 08:07:56 PM PDT 24
Finished Aug 08 08:19:29 PM PDT 24
Peak memory 575976 kb
Host smart-9c2e6867-3edc-4c58-8130-cfac85ed20ef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953274521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all
_with_rand_reset.2953274521
Directory /workspace/97.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.3381018105
Short name T88
Test name
Test status
Simulation time 3673361223 ps
CPU time 344.33 seconds
Started Aug 08 08:07:58 PM PDT 24
Finished Aug 08 08:13:43 PM PDT 24
Peak memory 576764 kb
Host smart-6222af96-4d12-4f4c-9831-e4d6d0dc2ec8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381018105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al
l_with_reset_error.3381018105
Directory /workspace/97.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.907349220
Short name T2230
Test name
Test status
Simulation time 237511323 ps
CPU time 26.66 seconds
Started Aug 08 08:07:56 PM PDT 24
Finished Aug 08 08:08:23 PM PDT 24
Peak memory 575828 kb
Host smart-09c77dfb-6a2c-47cf-babb-9c4f86c92cd0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907349220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.907349220
Directory /workspace/97.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_access_same_device.3403698191
Short name T1728
Test name
Test status
Simulation time 2743366942 ps
CPU time 122.78 seconds
Started Aug 08 08:07:56 PM PDT 24
Finished Aug 08 08:09:58 PM PDT 24
Peak memory 576008 kb
Host smart-c1d0cc1b-6116-4afc-ab53-f70fdbacf0d4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403698191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device
.3403698191
Directory /workspace/98.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.1555303562
Short name T2901
Test name
Test status
Simulation time 45297826838 ps
CPU time 819.13 seconds
Started Aug 08 08:07:56 PM PDT 24
Finished Aug 08 08:21:35 PM PDT 24
Peak memory 576772 kb
Host smart-f23ce505-5b13-493d-b53c-277d66d47f8b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555303562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_
device_slow_rsp.1555303562
Directory /workspace/98.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.4115654289
Short name T1356
Test name
Test status
Simulation time 187463807 ps
CPU time 19.48 seconds
Started Aug 08 08:08:09 PM PDT 24
Finished Aug 08 08:08:29 PM PDT 24
Peak memory 575956 kb
Host smart-8c6126c8-dc39-47b4-b63b-adc92cf3c813
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115654289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add
r.4115654289
Directory /workspace/98.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_error_random.3422413637
Short name T2089
Test name
Test status
Simulation time 101122798 ps
CPU time 10.81 seconds
Started Aug 08 08:08:06 PM PDT 24
Finished Aug 08 08:08:17 PM PDT 24
Peak memory 575816 kb
Host smart-7c45b167-502f-47fa-b7b8-c7171a8d90e9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422413637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.3422413637
Directory /workspace/98.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random.1664024470
Short name T2263
Test name
Test status
Simulation time 500569957 ps
CPU time 44.52 seconds
Started Aug 08 08:07:58 PM PDT 24
Finished Aug 08 08:08:42 PM PDT 24
Peak memory 575728 kb
Host smart-41b25c65-4dcb-470c-8467-04ebdf4482a6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664024470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.1664024470
Directory /workspace/98.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.1851121976
Short name T554
Test name
Test status
Simulation time 62218967431 ps
CPU time 678.7 seconds
Started Aug 08 08:07:56 PM PDT 24
Finished Aug 08 08:19:15 PM PDT 24
Peak memory 576028 kb
Host smart-942a297b-b11e-4bd4-8a2e-d17915aacb2b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851121976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.1851121976
Directory /workspace/98.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.2733734595
Short name T2448
Test name
Test status
Simulation time 33475446473 ps
CPU time 579.92 seconds
Started Aug 08 08:07:56 PM PDT 24
Finished Aug 08 08:17:36 PM PDT 24
Peak memory 576012 kb
Host smart-66cebdce-3c8d-41af-a96f-e11c74885e77
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733734595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.2733734595
Directory /workspace/98.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.626186572
Short name T1627
Test name
Test status
Simulation time 336356983 ps
CPU time 31.24 seconds
Started Aug 08 08:07:57 PM PDT 24
Finished Aug 08 08:08:28 PM PDT 24
Peak memory 575804 kb
Host smart-826d6402-a66e-4f4c-8104-472796560dd1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626186572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_dela
ys.626186572
Directory /workspace/98.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_same_source.666845424
Short name T2780
Test name
Test status
Simulation time 2037552252 ps
CPU time 59.85 seconds
Started Aug 08 08:08:07 PM PDT 24
Finished Aug 08 08:09:07 PM PDT 24
Peak memory 575884 kb
Host smart-c5f53f5a-42a1-4332-ae0d-ccf0c48516f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666845424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.666845424
Directory /workspace/98.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke.2751961622
Short name T1516
Test name
Test status
Simulation time 169463159 ps
CPU time 8.31 seconds
Started Aug 08 08:07:57 PM PDT 24
Finished Aug 08 08:08:05 PM PDT 24
Peak memory 574460 kb
Host smart-5cdec90e-2880-460c-91db-5dcb7a696d23
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751961622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.2751961622
Directory /workspace/98.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.2717757940
Short name T2734
Test name
Test status
Simulation time 9731428498 ps
CPU time 108.17 seconds
Started Aug 08 08:07:57 PM PDT 24
Finished Aug 08 08:09:46 PM PDT 24
Peak memory 574088 kb
Host smart-af286c8e-cf3c-47a8-9321-d3d9bf5f0766
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717757940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.2717757940
Directory /workspace/98.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.788815972
Short name T2655
Test name
Test status
Simulation time 4999668307 ps
CPU time 88.08 seconds
Started Aug 08 08:07:56 PM PDT 24
Finished Aug 08 08:09:24 PM PDT 24
Peak memory 573880 kb
Host smart-9cf64df1-12bb-427c-8be5-c552fe3bb120
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788815972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.788815972
Directory /workspace/98.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2662112225
Short name T2227
Test name
Test status
Simulation time 55417493 ps
CPU time 6.54 seconds
Started Aug 08 08:07:57 PM PDT 24
Finished Aug 08 08:08:03 PM PDT 24
Peak memory 573812 kb
Host smart-84a93dd3-7f6e-4b03-b618-0f42633ef954
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662112225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay
s.2662112225
Directory /workspace/98.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all.433906660
Short name T502
Test name
Test status
Simulation time 11737058696 ps
CPU time 540.81 seconds
Started Aug 08 08:08:09 PM PDT 24
Finished Aug 08 08:17:11 PM PDT 24
Peak memory 576168 kb
Host smart-60b5e1bb-baca-4e1b-ad52-03920c597195
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433906660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.433906660
Directory /workspace/98.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.1911408385
Short name T2349
Test name
Test status
Simulation time 511631746 ps
CPU time 46.01 seconds
Started Aug 08 08:08:06 PM PDT 24
Finished Aug 08 08:08:52 PM PDT 24
Peak memory 575996 kb
Host smart-fe31c06d-ce8a-48b8-9df4-fe4da3258948
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911408385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.1911408385
Directory /workspace/98.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.4051544562
Short name T470
Test name
Test status
Simulation time 7134786002 ps
CPU time 402.55 seconds
Started Aug 08 08:08:06 PM PDT 24
Finished Aug 08 08:14:49 PM PDT 24
Peak memory 575988 kb
Host smart-960002a8-2cf4-4568-adad-e65b6c21874f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051544562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all
_with_rand_reset.4051544562
Directory /workspace/98.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.3315173739
Short name T1681
Test name
Test status
Simulation time 421843968 ps
CPU time 123.34 seconds
Started Aug 08 08:08:06 PM PDT 24
Finished Aug 08 08:10:09 PM PDT 24
Peak memory 576744 kb
Host smart-304b0386-2699-423c-a5d0-614f54da6798
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315173739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_al
l_with_reset_error.3315173739
Directory /workspace/98.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.3358674953
Short name T462
Test name
Test status
Simulation time 317737819 ps
CPU time 33.94 seconds
Started Aug 08 08:08:10 PM PDT 24
Finished Aug 08 08:08:44 PM PDT 24
Peak memory 576004 kb
Host smart-027dc7bc-732a-48a2-8503-b7e5b6220b4f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358674953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.3358674953
Directory /workspace/98.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_access_same_device.2163528266
Short name T2138
Test name
Test status
Simulation time 1871791479 ps
CPU time 91.13 seconds
Started Aug 08 08:08:16 PM PDT 24
Finished Aug 08 08:09:48 PM PDT 24
Peak memory 575828 kb
Host smart-be2e338e-7f72-4f4b-8f6f-2d7ff1e25bd2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163528266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device
.2163528266
Directory /workspace/99.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.88310689
Short name T1986
Test name
Test status
Simulation time 39967198546 ps
CPU time 705.16 seconds
Started Aug 08 08:08:18 PM PDT 24
Finished Aug 08 08:20:04 PM PDT 24
Peak memory 575972 kb
Host smart-28bee5f9-a383-4be6-921f-4ed58cbcf3b6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88310689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_de
vice_slow_rsp.88310689
Directory /workspace/99.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.2939027359
Short name T2926
Test name
Test status
Simulation time 78293343 ps
CPU time 10.11 seconds
Started Aug 08 08:08:19 PM PDT 24
Finished Aug 08 08:08:29 PM PDT 24
Peak memory 575912 kb
Host smart-377a50c2-bd94-43b2-8e46-3a677640dfdc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939027359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add
r.2939027359
Directory /workspace/99.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_error_random.4266460793
Short name T2245
Test name
Test status
Simulation time 43590855 ps
CPU time 5.94 seconds
Started Aug 08 08:08:15 PM PDT 24
Finished Aug 08 08:08:21 PM PDT 24
Peak memory 573808 kb
Host smart-3f4f1583-bb5f-4728-92eb-812e72c123e3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266460793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.4266460793
Directory /workspace/99.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random.139798897
Short name T2055
Test name
Test status
Simulation time 219323046 ps
CPU time 20.97 seconds
Started Aug 08 08:08:06 PM PDT 24
Finished Aug 08 08:08:27 PM PDT 24
Peak memory 575816 kb
Host smart-930f13a8-a220-4960-9b2a-76f8407fe3af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139798897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.139798897
Directory /workspace/99.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.2609129864
Short name T2251
Test name
Test status
Simulation time 58540069232 ps
CPU time 715.71 seconds
Started Aug 08 08:08:06 PM PDT 24
Finished Aug 08 08:20:03 PM PDT 24
Peak memory 575972 kb
Host smart-15c91ef3-f992-4ca9-922e-6c9983fc1acf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609129864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.2609129864
Directory /workspace/99.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.3080237217
Short name T1959
Test name
Test status
Simulation time 10559573158 ps
CPU time 176.27 seconds
Started Aug 08 08:08:05 PM PDT 24
Finished Aug 08 08:11:01 PM PDT 24
Peak memory 575812 kb
Host smart-6fd64187-be8d-47c4-a6fd-a0972c963cdb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080237217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.3080237217
Directory /workspace/99.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.148087431
Short name T2026
Test name
Test status
Simulation time 452347137 ps
CPU time 40.67 seconds
Started Aug 08 08:08:10 PM PDT 24
Finished Aug 08 08:08:50 PM PDT 24
Peak memory 575752 kb
Host smart-61aa3143-95ad-4ba9-a77f-71a969c3508c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148087431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_dela
ys.148087431
Directory /workspace/99.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_same_source.2865084025
Short name T2269
Test name
Test status
Simulation time 118935118 ps
CPU time 11.18 seconds
Started Aug 08 08:08:21 PM PDT 24
Finished Aug 08 08:08:32 PM PDT 24
Peak memory 575864 kb
Host smart-cf062e21-4a9e-4241-a5e0-ee603b898bf7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865084025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.2865084025
Directory /workspace/99.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke.214610402
Short name T2471
Test name
Test status
Simulation time 169860455 ps
CPU time 8.6 seconds
Started Aug 08 08:08:06 PM PDT 24
Finished Aug 08 08:08:14 PM PDT 24
Peak memory 574552 kb
Host smart-e0cd2adb-0a40-4472-b505-24a68fde7732
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214610402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.214610402
Directory /workspace/99.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.2787724886
Short name T1892
Test name
Test status
Simulation time 5055822864 ps
CPU time 82.98 seconds
Started Aug 08 08:08:07 PM PDT 24
Finished Aug 08 08:09:30 PM PDT 24
Peak memory 573856 kb
Host smart-00dde30d-0344-400e-8f42-c04480fad850
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787724886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.2787724886
Directory /workspace/99.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.1651614658
Short name T1951
Test name
Test status
Simulation time 51931424 ps
CPU time 6.94 seconds
Started Aug 08 08:08:06 PM PDT 24
Finished Aug 08 08:08:13 PM PDT 24
Peak memory 574440 kb
Host smart-884e72a8-681d-40cc-b54f-9e5e15fd1d1e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651614658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay
s.1651614658
Directory /workspace/99.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all.3410367335
Short name T2396
Test name
Test status
Simulation time 5794824658 ps
CPU time 196.76 seconds
Started Aug 08 08:08:16 PM PDT 24
Finished Aug 08 08:11:33 PM PDT 24
Peak memory 575896 kb
Host smart-c48c2a74-1072-48a8-8294-9c591d68db21
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410367335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.3410367335
Directory /workspace/99.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.740102585
Short name T2536
Test name
Test status
Simulation time 9191079308 ps
CPU time 278.74 seconds
Started Aug 08 08:08:16 PM PDT 24
Finished Aug 08 08:12:55 PM PDT 24
Peak memory 576752 kb
Host smart-592810aa-3354-4f76-b35a-3a46918b86fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740102585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.740102585
Directory /workspace/99.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.2540817128
Short name T497
Test name
Test status
Simulation time 4387929294 ps
CPU time 563.34 seconds
Started Aug 08 08:08:21 PM PDT 24
Finished Aug 08 08:17:44 PM PDT 24
Peak memory 576716 kb
Host smart-01b9cec8-8cbf-4cbd-8a22-d68df045a4db
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540817128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all
_with_rand_reset.2540817128
Directory /workspace/99.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.2891818042
Short name T2240
Test name
Test status
Simulation time 3154138859 ps
CPU time 115.28 seconds
Started Aug 08 08:08:17 PM PDT 24
Finished Aug 08 08:10:12 PM PDT 24
Peak memory 576128 kb
Host smart-23737427-7ebe-4b44-b4b0-3297c51c6bb0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891818042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al
l_with_reset_error.2891818042
Directory /workspace/99.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.804065812
Short name T2857
Test name
Test status
Simulation time 1072415815 ps
CPU time 40.13 seconds
Started Aug 08 08:08:18 PM PDT 24
Finished Aug 08 08:08:58 PM PDT 24
Peak memory 575960 kb
Host smart-d4d5095d-8bdd-4ffb-93e5-5483b155bf6c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804065812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.804065812
Directory /workspace/99.xbar_unmapped_addr/latest

Test location /workspace/coverage/default/0.chip_jtag_csr_rw.499411181
Short name T85
Test name
Test status
Simulation time 11069225250 ps
CPU time 1090.55 seconds
Started Aug 08 08:10:33 PM PDT 24
Finished Aug 08 08:28:44 PM PDT 24
Peak memory 608112 kb
Host smart-056b8519-dee0-466e-81a3-c508a4ba6719
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499411181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch
ip_jtag_csr_rw.499411181
Directory /workspace/0.chip_jtag_csr_rw/latest

Test location /workspace/coverage/default/0.chip_jtag_mem_access.906753205
Short name T205
Test name
Test status
Simulation time 13362364110 ps
CPU time 1382.99 seconds
Started Aug 08 08:10:33 PM PDT 24
Finished Aug 08 08:33:36 PM PDT 24
Peak memory 607976 kb
Host smart-e5b93252-2eb6-4e63-9379-57c8fee5eeb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906753205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m
em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.906753205
Directory /workspace/0.chip_jtag_mem_access/latest

Test location /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2552145783
Short name T53
Test name
Test status
Simulation time 5086426424 ps
CPU time 428.93 seconds
Started Aug 08 08:20:59 PM PDT 24
Finished Aug 08 08:28:08 PM PDT 24
Peak memory 620972 kb
Host smart-e11ce42e-cd2f-457d-bddc-12f1986bc438
User root
Command /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2
552145783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.2552145783
Directory /workspace/0.chip_rv_dm_ndm_reset_req/latest

Test location /workspace/coverage/default/0.chip_sival_flash_info_access.2575649127
Short name T1296
Test name
Test status
Simulation time 2646658784 ps
CPU time 266.89 seconds
Started Aug 08 08:15:07 PM PDT 24
Finished Aug 08 08:19:34 PM PDT 24
Peak memory 609952 kb
Host smart-f5ca8a54-3156-4259-9381-3c4285fac2c0
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=2575649127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.2575649127
Directory /workspace/0.chip_sival_flash_info_access/latest

Test location /workspace/coverage/default/0.chip_sw_aes_enc.2760027904
Short name T1012
Test name
Test status
Simulation time 3529000658 ps
CPU time 334.13 seconds
Started Aug 08 08:19:01 PM PDT 24
Finished Aug 08 08:24:36 PM PDT 24
Peak memory 609648 kb
Host smart-ccffabcb-13d5-4617-b5c0-ded44c88427d
User root
Command /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760027904 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.2760027904
Directory /workspace/0.chip_sw_aes_enc/latest

Test location /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3477011919
Short name T1161
Test name
Test status
Simulation time 2613944864 ps
CPU time 234.26 seconds
Started Aug 08 08:17:26 PM PDT 24
Finished Aug 08 08:21:22 PM PDT 24
Peak memory 609672 kb
Host smart-d79950d2-e523-4142-824f-f806aaa49104
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477
011919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.3477011919
Directory /workspace/0.chip_sw_aes_enc_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.244793012
Short name T1238
Test name
Test status
Simulation time 2942825153 ps
CPU time 318.62 seconds
Started Aug 08 08:18:37 PM PDT 24
Finished Aug 08 08:23:56 PM PDT 24
Peak memory 609724 kb
Host smart-c5a2ec9e-3cf8-4e98-9a7e-d25f10e19623
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=244793012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.244793012
Directory /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_aes_entropy.1294818645
Short name T1128
Test name
Test status
Simulation time 2661966520 ps
CPU time 310.4 seconds
Started Aug 08 08:17:13 PM PDT 24
Finished Aug 08 08:22:24 PM PDT 24
Peak memory 609212 kb
Host smart-1cb7a813-2677-467b-8d51-47b8b37ece7f
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294818645 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.1294818645
Directory /workspace/0.chip_sw_aes_entropy/latest

Test location /workspace/coverage/default/0.chip_sw_aes_idle.3492238127
Short name T872
Test name
Test status
Simulation time 3153376044 ps
CPU time 259.52 seconds
Started Aug 08 08:16:19 PM PDT 24
Finished Aug 08 08:20:39 PM PDT 24
Peak memory 609700 kb
Host smart-89274512-8fee-4ecd-8a04-a96b534888d6
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492238127 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.3492238127
Directory /workspace/0.chip_sw_aes_idle/latest

Test location /workspace/coverage/default/0.chip_sw_aes_masking_off.341504034
Short name T717
Test name
Test status
Simulation time 3077414807 ps
CPU time 335.33 seconds
Started Aug 08 08:17:46 PM PDT 24
Finished Aug 08 08:23:21 PM PDT 24
Peak memory 610448 kb
Host smart-b0719265-4cde-4b3e-92a2-3f8a2634cefe
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341504034 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.341504034
Directory /workspace/0.chip_sw_aes_masking_off/latest

Test location /workspace/coverage/default/0.chip_sw_aes_smoketest.999530235
Short name T1248
Test name
Test status
Simulation time 3398698622 ps
CPU time 238.59 seconds
Started Aug 08 08:20:34 PM PDT 24
Finished Aug 08 08:24:32 PM PDT 24
Peak memory 609228 kb
Host smart-145baf6c-45fc-4709-a88b-a7b6a0496dbc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999530235 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_aes_smoketest.999530235
Directory /workspace/0.chip_sw_aes_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1348480392
Short name T615
Test name
Test status
Simulation time 2626510707 ps
CPU time 289.02 seconds
Started Aug 08 08:18:27 PM PDT 24
Finished Aug 08 08:23:16 PM PDT 24
Peak memory 609644 kb
Host smart-9d6263e6-a533-44bd-9d26-44e9ea712eec
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1348480392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.1348480392
Directory /workspace/0.chip_sw_alert_handler_entropy/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_escalation.343762408
Short name T225
Test name
Test status
Simulation time 5899454280 ps
CPU time 484.09 seconds
Started Aug 08 08:15:35 PM PDT 24
Finished Aug 08 08:23:40 PM PDT 24
Peak memory 619660 kb
Host smart-59b3cf80-3cd4-4072-8f27-df894351615d
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=343762408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.343762408
Directory /workspace/0.chip_sw_alert_handler_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2763453479
Short name T1164
Test name
Test status
Simulation time 8804015874 ps
CPU time 2076.74 seconds
Started Aug 08 08:18:39 PM PDT 24
Finished Aug 08 08:53:16 PM PDT 24
Peak memory 610176 kb
Host smart-928e2984-8a6a-4fec-94f9-7e95349981a8
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2763453479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.2763453479
Directory /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3258380093
Short name T1027
Test name
Test status
Simulation time 7683572344 ps
CPU time 1874.68 seconds
Started Aug 08 08:21:13 PM PDT 24
Finished Aug 08 08:52:28 PM PDT 24
Peak memory 610092 kb
Host smart-8012f34d-f3e8-436f-bf73-469c0ce63499
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3258380093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg
le.3258380093
Directory /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2849805985
Short name T159
Test name
Test status
Simulation time 11411245240 ps
CPU time 1259.79 seconds
Started Aug 08 08:19:15 PM PDT 24
Finished Aug 08 08:40:15 PM PDT 24
Peak memory 610988 kb
Host smart-c03691d2-1f10-4259-bfc3-5b83cde996f3
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler
_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849805985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han
dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.chip_sw_alert_handler_lpg_sleep_mode_pings.2849805985
Directory /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2327117014
Short name T672
Test name
Test status
Simulation time 8327784324 ps
CPU time 1358.46 seconds
Started Aug 08 08:20:48 PM PDT 24
Finished Aug 08 08:43:27 PM PDT 24
Peak memory 610056 kb
Host smart-7d4bb7ae-0710-4587-bc31-d023fc865513
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=2327117014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.2327117014
Directory /workspace/0.chip_sw_alert_handler_ping_ok/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3375372665
Short name T1144
Test name
Test status
Simulation time 5926627010 ps
CPU time 532.59 seconds
Started Aug 08 08:18:52 PM PDT 24
Finished Aug 08 08:27:45 PM PDT 24
Peak memory 610156 kb
Host smart-746e5d9a-bf29-4a58-ac5b-90b4d266afed
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3375372665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.3375372665
Directory /workspace/0.chip_sw_alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4006478911
Short name T1259
Test name
Test status
Simulation time 255819832964 ps
CPU time 11831.9 seconds
Started Aug 08 08:17:14 PM PDT 24
Finished Aug 08 11:34:28 PM PDT 24
Peak memory 610840 kb
Host smart-f8ba391a-c3e8-4e9d-bbc2-6362d8af1381
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006478911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4006478911
Directory /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location /workspace/coverage/default/0.chip_sw_alert_test.2192960868
Short name T68
Test name
Test status
Simulation time 2727647688 ps
CPU time 330.09 seconds
Started Aug 08 08:18:09 PM PDT 24
Finished Aug 08 08:23:39 PM PDT 24
Peak memory 609296 kb
Host smart-62d269c4-d74f-4239-9939-d03b810ac2af
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192960868 -assert nopostproc +UVM_TESTNAME=chip_ba
se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.chip_sw_alert_test.2192960868
Directory /workspace/0.chip_sw_alert_test/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_irq.3845261504
Short name T1099
Test name
Test status
Simulation time 4386220636 ps
CPU time 446.63 seconds
Started Aug 08 08:16:39 PM PDT 24
Finished Aug 08 08:24:06 PM PDT 24
Peak memory 609928 kb
Host smart-f7fe39fb-08f0-466c-8ba9-8bb2a02c9a85
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845261504 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.3845261504
Directory /workspace/0.chip_sw_aon_timer_irq/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.891162341
Short name T124
Test name
Test status
Simulation time 7003244604 ps
CPU time 455.26 seconds
Started Aug 08 08:16:48 PM PDT 24
Finished Aug 08 08:24:23 PM PDT 24
Peak memory 609156 kb
Host smart-08080e56-61b1-4893-aee6-c47f3b77d107
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=891162341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.891162341
Directory /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.498616858
Short name T1274
Test name
Test status
Simulation time 2791494196 ps
CPU time 256.87 seconds
Started Aug 08 08:21:43 PM PDT 24
Finished Aug 08 08:26:00 PM PDT 24
Peak memory 609536 kb
Host smart-d79ff784-beeb-4d95-8027-c68d6360a94c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498616858 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_aon_timer_smoketest.498616858
Directory /workspace/0.chip_sw_aon_timer_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1375232102
Short name T927
Test name
Test status
Simulation time 9583180094 ps
CPU time 1239.95 seconds
Started Aug 08 08:16:15 PM PDT 24
Finished Aug 08 08:36:55 PM PDT 24
Peak memory 610520 kb
Host smart-4569fbe8-3df7-4a27-8373-ac9a7ee89628
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1375232102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.1375232102
Directory /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3792697849
Short name T1317
Test name
Test status
Simulation time 5107528408 ps
CPU time 499.95 seconds
Started Aug 08 08:18:20 PM PDT 24
Finished Aug 08 08:26:40 PM PDT 24
Peak memory 610560 kb
Host smart-bf18624f-2f36-45dc-a974-0777c78d573a
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3792697849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.3792697849
Directory /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location /workspace/coverage/default/0.chip_sw_ast_clk_outputs.930403317
Short name T1167
Test name
Test status
Simulation time 7675587530 ps
CPU time 1142.09 seconds
Started Aug 08 08:18:05 PM PDT 24
Finished Aug 08 08:37:07 PM PDT 24
Peak memory 616276 kb
Host smart-18f8e28b-8ada-4d96-b5eb-940db4279360
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930403317 -assert nopos
tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.930403317
Directory /workspace/0.chip_sw_ast_clk_outputs/latest

Test location /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.3005867310
Short name T142
Test name
Test status
Simulation time 21709010150 ps
CPU time 3324.67 seconds
Started Aug 08 08:24:08 PM PDT 24
Finished Aug 08 09:19:33 PM PDT 24
Peak memory 610816 kb
Host smart-d8e4b8d3-0e29-4cc5-9492-822fcbe6d9d4
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005867310
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.3005867310
Directory /workspace/0.chip_sw_ast_clk_rst_inputs/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1657251094
Short name T1002
Test name
Test status
Simulation time 12831067482 ps
CPU time 1134.24 seconds
Started Aug 08 08:16:54 PM PDT 24
Finished Aug 08 08:35:48 PM PDT 24
Peak memory 620500 kb
Host smart-921c9081-d16d-4792-b5e2-7ada5571a316
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=1657251094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.1657251094
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2479198086
Short name T1140
Test name
Test status
Simulation time 3898557780 ps
CPU time 551.56 seconds
Started Aug 08 08:18:50 PM PDT 24
Finished Aug 08 08:28:01 PM PDT 24
Peak memory 612056 kb
Host smart-755cc462-9bad-4cd8-8c41-e021308354b8
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479198086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_dev.2479198086
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1446072891
Short name T898
Test name
Test status
Simulation time 3661435170 ps
CPU time 655.59 seconds
Started Aug 08 08:20:07 PM PDT 24
Finished Aug 08 08:31:02 PM PDT 24
Peak memory 612076 kb
Host smart-9532ea5e-e5e5-45d7-abec-d80087c8a25d
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446072891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_rma.1446072891
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2635140596
Short name T1226
Test name
Test status
Simulation time 4023149994 ps
CPU time 679.35 seconds
Started Aug 08 08:21:27 PM PDT 24
Finished Aug 08 08:32:46 PM PDT 24
Peak memory 612180 kb
Host smart-101ab741-28a7-4b00-8704-fc0cc3922ff5
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635140596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2635140596
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3027865993
Short name T1251
Test name
Test status
Simulation time 3993355640 ps
CPU time 432.72 seconds
Started Aug 08 08:18:43 PM PDT 24
Finished Aug 08 08:25:56 PM PDT 24
Peak memory 612880 kb
Host smart-e2c87545-8557-4ae1-b46a-d7aefb9b3c40
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027865993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_dev.3027865993
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2215917621
Short name T123
Test name
Test status
Simulation time 4826780904 ps
CPU time 567.29 seconds
Started Aug 08 08:19:08 PM PDT 24
Finished Aug 08 08:28:35 PM PDT 24
Peak memory 612152 kb
Host smart-5ff549c5-36f2-41b7-b752-be94b4babe21
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215917621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_rma.2215917621
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1728641371
Short name T892
Test name
Test status
Simulation time 4790622128 ps
CPU time 577.07 seconds
Started Aug 08 08:16:58 PM PDT 24
Finished Aug 08 08:26:35 PM PDT 24
Peak memory 612196 kb
Host smart-45bd222a-2643-4ab5-888c-40d1876061c5
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728641371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1728641371
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1878388410
Short name T1180
Test name
Test status
Simulation time 2611203284 ps
CPU time 176.22 seconds
Started Aug 08 08:17:55 PM PDT 24
Finished Aug 08 08:20:51 PM PDT 24
Peak memory 609708 kb
Host smart-9e3497d1-c927-48a9-bad8-8995d75b0b26
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878388410 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_clkmgr_jitter.1878388410
Directory /workspace/0.chip_sw_clkmgr_jitter/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2074595887
Short name T106
Test name
Test status
Simulation time 4055555380 ps
CPU time 565.36 seconds
Started Aug 08 08:19:31 PM PDT 24
Finished Aug 08 08:28:57 PM PDT 24
Peak memory 609728 kb
Host smart-67352cae-82e2-4425-b3b7-f00adb9b2342
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074595887 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.2074595887
Directory /workspace/0.chip_sw_clkmgr_jitter_frequency/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.790280326
Short name T1304
Test name
Test status
Simulation time 2294888695 ps
CPU time 194.73 seconds
Started Aug 08 08:23:38 PM PDT 24
Finished Aug 08 08:26:54 PM PDT 24
Peak memory 609280 kb
Host smart-87dc5d0f-4537-493b-b864-aa4fbe453b7c
User root
Command /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790280326 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.790280326
Directory /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1824244925
Short name T1051
Test name
Test status
Simulation time 5026841376 ps
CPU time 536.57 seconds
Started Aug 08 08:19:19 PM PDT 24
Finished Aug 08 08:28:16 PM PDT 24
Peak memory 610312 kb
Host smart-477acb94-1898-497f-af37-12456d2887ae
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824244925 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.1824244925
Directory /workspace/0.chip_sw_clkmgr_off_aes_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2721845373
Short name T1152
Test name
Test status
Simulation time 4468193548 ps
CPU time 537.19 seconds
Started Aug 08 08:17:36 PM PDT 24
Finished Aug 08 08:26:34 PM PDT 24
Peak memory 609536 kb
Host smart-54f07182-aed6-4001-89e3-913ee970932c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721845373 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.2721845373
Directory /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3516321217
Short name T1021
Test name
Test status
Simulation time 5358001020 ps
CPU time 354.12 seconds
Started Aug 08 08:19:01 PM PDT 24
Finished Aug 08 08:24:55 PM PDT 24
Peak memory 609500 kb
Host smart-e8464676-641a-4b89-9337-a5916d1229af
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516321217 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.3516321217
Directory /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2868688868
Short name T224
Test name
Test status
Simulation time 4250011698 ps
CPU time 443.35 seconds
Started Aug 08 08:19:46 PM PDT 24
Finished Aug 08 08:27:10 PM PDT 24
Peak memory 610152 kb
Host smart-3e727352-c196-46ca-ad88-eec91d7335fb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868688868 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.2868688868
Directory /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.163358495
Short name T1188
Test name
Test status
Simulation time 12474805780 ps
CPU time 1144.3 seconds
Started Aug 08 08:19:42 PM PDT 24
Finished Aug 08 08:38:47 PM PDT 24
Peak memory 610136 kb
Host smart-1b612db0-9d8e-4318-9539-366780b963ef
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163358495
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.163358495
Directory /workspace/0.chip_sw_clkmgr_off_peri/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2573210532
Short name T626
Test name
Test status
Simulation time 3307812924 ps
CPU time 338.33 seconds
Started Aug 08 08:19:25 PM PDT 24
Finished Aug 08 08:25:04 PM PDT 24
Peak memory 609796 kb
Host smart-6ad2d449-3712-45b5-b12e-8f5c99f44fc6
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573210532 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.2573210532
Directory /workspace/0.chip_sw_clkmgr_reset_frequency/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.562579508
Short name T1041
Test name
Test status
Simulation time 5190537640 ps
CPU time 597.4 seconds
Started Aug 08 08:18:42 PM PDT 24
Finished Aug 08 08:28:39 PM PDT 24
Peak memory 610048 kb
Host smart-3d8927f8-21de-436d-9778-5c9f714b973e
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562579508 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.562579508
Directory /workspace/0.chip_sw_clkmgr_sleep_frequency/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3569557962
Short name T914
Test name
Test status
Simulation time 2609149900 ps
CPU time 186.84 seconds
Started Aug 08 08:22:32 PM PDT 24
Finished Aug 08 08:25:39 PM PDT 24
Peak memory 609500 kb
Host smart-05466582-eeaf-4a62-a305-0e2d9753d0df
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569557962 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.chip_sw_clkmgr_smoketest.3569557962
Directory /workspace/0.chip_sw_clkmgr_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_coremark.3994803217
Short name T389
Test name
Test status
Simulation time 71573437328 ps
CPU time 14743.6 seconds
Started Aug 08 08:20:18 PM PDT 24
Finished Aug 09 12:26:03 AM PDT 24
Peak memory 610064 kb
Host smart-e3d8964a-6727-40c5-a768-3636c09655d5
User root
Command /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3994803217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.3994803217
Directory /workspace/0.chip_sw_coremark/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2156787074
Short name T1095
Test name
Test status
Simulation time 17834492544 ps
CPU time 4395.13 seconds
Started Aug 08 08:19:13 PM PDT 24
Finished Aug 08 09:32:29 PM PDT 24
Peak memory 610148 kb
Host smart-b20ba4b8-ba88-452e-99af-06ed77906889
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156787074 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.2156787074
Directory /workspace/0.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1978323540
Short name T1114
Test name
Test status
Simulation time 42167061390 ps
CPU time 7059.47 seconds
Started Aug 08 08:18:13 PM PDT 24
Finished Aug 08 10:15:53 PM PDT 24
Peak memory 610356 kb
Host smart-5bcadc81-3fbd-4ad0-9ae8-fb03dc6ead12
User root
Command /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_
cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1978323540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.1978323540
Directory /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_kat_test.4188935981
Short name T1182
Test name
Test status
Simulation time 3412600012 ps
CPU time 305.78 seconds
Started Aug 08 08:17:10 PM PDT 24
Finished Aug 08 08:22:16 PM PDT 24
Peak memory 609620 kb
Host smart-2529ae59-d44a-4967-aa0a-0dcb0c3dcb00
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188935981 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.4188935981
Directory /workspace/0.chip_sw_csrng_kat_test/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.4271466260
Short name T1023
Test name
Test status
Simulation time 5914976836 ps
CPU time 830.12 seconds
Started Aug 08 08:17:15 PM PDT 24
Finished Aug 08 08:31:06 PM PDT 24
Peak memory 611332 kb
Host smart-1ae12aa5-4139-47ed-bd43-b80984485eca
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima
ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271466260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_
lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr
ng_lc_hw_debug_en_test.4271466260
Directory /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_smoketest.1073222791
Short name T855
Test name
Test status
Simulation time 2948693868 ps
CPU time 189.39 seconds
Started Aug 08 08:19:14 PM PDT 24
Finished Aug 08 08:22:24 PM PDT 24
Peak memory 609300 kb
Host smart-af7170b4-00b9-43bb-ac86-a99957b0b416
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073222791 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.chip_sw_csrng_smoketest.1073222791
Directory /workspace/0.chip_sw_csrng_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_data_integrity_escalation.2873437502
Short name T103
Test name
Test status
Simulation time 5117521800 ps
CPU time 509.73 seconds
Started Aug 08 08:16:00 PM PDT 24
Finished Aug 08 08:24:31 PM PDT 24
Peak memory 611072 kb
Host smart-29bdbe2b-209a-4681-ab18-9a534b2fbfe1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2873437502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.2873437502
Directory /workspace/0.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_edn_auto_mode.857261789
Short name T875
Test name
Test status
Simulation time 5786326564 ps
CPU time 1414.85 seconds
Started Aug 08 08:18:45 PM PDT 24
Finished Aug 08 08:42:20 PM PDT 24
Peak memory 610292 kb
Host smart-5e903a0f-57d4-4498-992c-2a894188265d
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857261789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_a
uto_mode.857261789
Directory /workspace/0.chip_sw_edn_auto_mode/latest

Test location /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1173252308
Short name T1060
Test name
Test status
Simulation time 6296370760 ps
CPU time 949.89 seconds
Started Aug 08 08:21:06 PM PDT 24
Finished Aug 08 08:36:57 PM PDT 24
Peak memory 610664 kb
Host smart-7fcffbf0-fcb8-4a6c-8be9-13c9c84ed084
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed
n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1173252308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.1173252308
Directory /workspace/0.chip_sw_edn_entropy_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.343790877
Short name T375
Test name
Test status
Simulation time 8013840104 ps
CPU time 1392.03 seconds
Started Aug 08 08:17:11 PM PDT 24
Finished Aug 08 08:40:23 PM PDT 24
Peak memory 609956 kb
Host smart-469ba9af-fdf0-4a28-bd2b-ace8802da739
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e
ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343790877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.343790877
Directory /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest

Test location /workspace/coverage/default/0.chip_sw_edn_kat.1934569700
Short name T886
Test name
Test status
Simulation time 3621012350 ps
CPU time 670.73 seconds
Started Aug 08 08:16:27 PM PDT 24
Finished Aug 08 08:27:38 PM PDT 24
Peak memory 615608 kb
Host smart-28a42e0b-1041-4065-b9ab-46926265c9fe
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3
+accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934569700 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_edn_kat.1934569700
Directory /workspace/0.chip_sw_edn_kat/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3637738490
Short name T960
Test name
Test status
Simulation time 3147224970 ps
CPU time 272.54 seconds
Started Aug 08 08:18:03 PM PDT 24
Finished Aug 08 08:22:35 PM PDT 24
Peak memory 608496 kb
Host smart-6f70c22a-9815-40d9-9b74-d799a174e4c7
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36
37738490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.3637738490
Directory /workspace/0.chip_sw_entropy_src_ast_rng_req/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_csrng.3838978242
Short name T127
Test name
Test status
Simulation time 8124530668 ps
CPU time 2228.77 seconds
Started Aug 08 08:20:35 PM PDT 24
Finished Aug 08 08:57:44 PM PDT 24
Peak memory 609988 kb
Host smart-7f05c2fc-8527-47d2-8202-508cd1aaa8b9
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_
csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3838978242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.3838978242
Directory /workspace/0.chip_sw_entropy_src_csrng/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.4293773555
Short name T961
Test name
Test status
Simulation time 2582224160 ps
CPU time 188.93 seconds
Started Aug 08 08:16:56 PM PDT 24
Finished Aug 08 08:20:06 PM PDT 24
Peak memory 609676 kb
Host smart-6cac6f52-bf79-4598-b13f-329a1c16d070
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293773555
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.4293773555
Directory /workspace/0.chip_sw_entropy_src_kat_test/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.4075182097
Short name T1341
Test name
Test status
Simulation time 3468062900 ps
CPU time 395.05 seconds
Started Aug 08 08:21:37 PM PDT 24
Finished Aug 08 08:28:12 PM PDT 24
Peak memory 609672 kb
Host smart-8f7dec32-7f02-4130-b9ac-2e7a7e9946eb
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4075182097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.4075182097
Directory /workspace/0.chip_sw_entropy_src_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_example_concurrency.774729539
Short name T969
Test name
Test status
Simulation time 2666878112 ps
CPU time 249.98 seconds
Started Aug 08 08:15:57 PM PDT 24
Finished Aug 08 08:20:07 PM PDT 24
Peak memory 609608 kb
Host smart-96455c96-452d-4a9e-9a17-d474a376886b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774729539 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_example_concurrency.774729539
Directory /workspace/0.chip_sw_example_concurrency/latest

Test location /workspace/coverage/default/0.chip_sw_example_flash.3127476542
Short name T1105
Test name
Test status
Simulation time 3079462216 ps
CPU time 235.92 seconds
Started Aug 08 08:14:54 PM PDT 24
Finished Aug 08 08:18:50 PM PDT 24
Peak memory 608244 kb
Host smart-9776850a-f559-48c7-b15c-9ff0149144da
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127476542 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_example_flash.3127476542
Directory /workspace/0.chip_sw_example_flash/latest

Test location /workspace/coverage/default/0.chip_sw_example_manufacturer.3386301692
Short name T1010
Test name
Test status
Simulation time 2043749416 ps
CPU time 213.69 seconds
Started Aug 08 08:17:15 PM PDT 24
Finished Aug 08 08:20:49 PM PDT 24
Peak memory 609300 kb
Host smart-51e24e4e-5118-42d1-99af-354f84b58457
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386301692 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_example_manufacturer.3386301692
Directory /workspace/0.chip_sw_example_manufacturer/latest

Test location /workspace/coverage/default/0.chip_sw_example_rom.1587065655
Short name T1157
Test name
Test status
Simulation time 2402260760 ps
CPU time 129.41 seconds
Started Aug 08 08:15:03 PM PDT 24
Finished Aug 08 08:17:14 PM PDT 24
Peak memory 608876 kb
Host smart-0b542b30-0e11-4a41-bd55-8c3d33f2a7d1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587065655 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_example_rom.1587065655
Directory /workspace/0.chip_sw_example_rom/latest

Test location /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.640894662
Short name T51
Test name
Test status
Simulation time 58781352200 ps
CPU time 10567 seconds
Started Aug 08 08:15:55 PM PDT 24
Finished Aug 08 11:12:03 PM PDT 24
Peak memory 624700 kb
Host smart-d91de0f4-d5e6-4e5d-b1d2-d33b3c143841
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=640894662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.640894662
Directory /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest

Test location /workspace/coverage/default/0.chip_sw_flash_crash_alert.1159843388
Short name T643
Test name
Test status
Simulation time 4616210428 ps
CPU time 554.23 seconds
Started Aug 08 08:22:51 PM PDT 24
Finished Aug 08 08:32:06 PM PDT 24
Peak memory 610920 kb
Host smart-98f9acfe-4edf-4ead-a519-fe5a9e996b3e
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:
new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=1159843388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.1159843388
Directory /workspace/0.chip_sw_flash_crash_alert/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_access.2265154911
Short name T907
Test name
Test status
Simulation time 5760842540 ps
CPU time 1281.77 seconds
Started Aug 08 08:18:32 PM PDT 24
Finished Aug 08 08:39:54 PM PDT 24
Peak memory 609856 kb
Host smart-dd607da4-1bc7-4b1f-b7b8-befe56f5e879
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265154911 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.chip_sw_flash_ctrl_access.2265154911
Directory /workspace/0.chip_sw_flash_ctrl_access/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3734165500
Short name T1062
Test name
Test status
Simulation time 6432141909 ps
CPU time 781.54 seconds
Started Aug 08 08:15:55 PM PDT 24
Finished Aug 08 08:28:56 PM PDT 24
Peak memory 608204 kb
Host smart-69db28da-5b31-477e-a067-4da6c6ff5376
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734165500 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.3734165500
Directory /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1082176144
Short name T1159
Test name
Test status
Simulation time 7710612692 ps
CPU time 1206.01 seconds
Started Aug 08 08:19:52 PM PDT 24
Finished Aug 08 08:39:58 PM PDT 24
Peak memory 608924 kb
Host smart-c7f9fa98-b1ac-4299-9afc-e8cb28b7823b
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082176144 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1082176144
Directory /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2644260800
Short name T1064
Test name
Test status
Simulation time 6075041199 ps
CPU time 1046.33 seconds
Started Aug 08 08:16:52 PM PDT 24
Finished Aug 08 08:34:19 PM PDT 24
Peak memory 610080 kb
Host smart-2fa59d44-f907-4a50-9f33-022f87b1d0c6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644260800 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.2644260800
Directory /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1369218802
Short name T1181
Test name
Test status
Simulation time 3008236200 ps
CPU time 355.38 seconds
Started Aug 08 08:20:37 PM PDT 24
Finished Aug 08 08:26:33 PM PDT 24
Peak memory 609444 kb
Host smart-e70a937b-e542-4496-9676-d1990df61533
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369218802 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.1369218802
Directory /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2899021348
Short name T881
Test name
Test status
Simulation time 6152135524 ps
CPU time 1215.35 seconds
Started Aug 08 08:19:07 PM PDT 24
Finished Aug 08 08:39:23 PM PDT 24
Peak memory 610092 kb
Host smart-025094af-222e-4cd5-a71f-7a4cb4baac6b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899021348 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.2899021348
Directory /workspace/0.chip_sw_flash_ctrl_mem_protection/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.241885720
Short name T1130
Test name
Test status
Simulation time 4980021212 ps
CPU time 743.18 seconds
Started Aug 08 08:18:30 PM PDT 24
Finished Aug 08 08:30:54 PM PDT 24
Peak memory 609832 kb
Host smart-7b0ccbfe-8981-4e9b-9206-0000348f3216
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241885720 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.241885720
Directory /workspace/0.chip_sw_flash_ctrl_ops/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2077048818
Short name T329
Test name
Test status
Simulation time 4207951458 ps
CPU time 550.25 seconds
Started Aug 08 08:18:33 PM PDT 24
Finished Aug 08 08:27:43 PM PDT 24
Peak memory 609732 kb
Host smart-1a4447fb-087f-4bcd-84dd-4e2a60099a4d
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_
rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2077048818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2077048818
Directory /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3335853801
Short name T381
Test name
Test status
Simulation time 3684673606 ps
CPU time 357.81 seconds
Started Aug 08 08:20:51 PM PDT 24
Finished Aug 08 08:26:49 PM PDT 24
Peak memory 609744 kb
Host smart-c314c272-a97c-4d4c-91c2-b18abc1f676f
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335853
801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.3335853801
Directory /workspace/0.chip_sw_flash_ctrl_write_clear/latest

Test location /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1586987856
Short name T1243
Test name
Test status
Simulation time 2496138920 ps
CPU time 174 seconds
Started Aug 08 08:23:15 PM PDT 24
Finished Aug 08 08:26:09 PM PDT 24
Peak memory 609476 kb
Host smart-bd6c3c56-ad9d-4eb8-bd13-358383b4b7c0
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket
est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1586987856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.1586987856
Directory /workspace/0.chip_sw_flash_scrambling_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_gpio_smoketest.166268983
Short name T94
Test name
Test status
Simulation time 2779840137 ps
CPU time 265.34 seconds
Started Aug 08 08:22:20 PM PDT 24
Finished Aug 08 08:26:46 PM PDT 24
Peak memory 609956 kb
Host smart-35a3b0f6-a7f2-43f1-9e9a-574e1df6f1ae
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166268983 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.chip_sw_gpio_smoketest.166268983
Directory /workspace/0.chip_sw_gpio_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc.858944815
Short name T906
Test name
Test status
Simulation time 3174486480 ps
CPU time 217.54 seconds
Started Aug 08 08:17:41 PM PDT 24
Finished Aug 08 08:21:19 PM PDT 24
Peak memory 609748 kb
Host smart-2ddf5193-d164-44a8-96d2-9bd45e83379e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858944815 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_hmac_enc.858944815
Directory /workspace/0.chip_sw_hmac_enc/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc_idle.323625152
Short name T1345
Test name
Test status
Simulation time 3182692908 ps
CPU time 327.99 seconds
Started Aug 08 08:18:23 PM PDT 24
Finished Aug 08 08:23:51 PM PDT 24
Peak memory 609284 kb
Host smart-654d01e1-f621-4a66-b0f8-b2f328de3e13
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323625152 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_hmac_enc_idle.323625152
Directory /workspace/0.chip_sw_hmac_enc_idle/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.857071571
Short name T336
Test name
Test status
Simulation time 2206326654 ps
CPU time 233.05 seconds
Started Aug 08 08:21:36 PM PDT 24
Finished Aug 08 08:25:29 PM PDT 24
Peak memory 609696 kb
Host smart-31d0ee33-03ff-460c-a263-853254aac855
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857071571 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.857071571
Directory /workspace/0.chip_sw_hmac_enc_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2123448738
Short name T119
Test name
Test status
Simulation time 3579633265 ps
CPU time 384.39 seconds
Started Aug 08 08:18:42 PM PDT 24
Finished Aug 08 08:25:06 PM PDT 24
Peak memory 609836 kb
Host smart-8ac09897-4867-4001-a12e-6f0fa4919e0f
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123448738 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.2123448738
Directory /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_multistream.232490792
Short name T893
Test name
Test status
Simulation time 6549155864 ps
CPU time 1834.26 seconds
Started Aug 08 08:17:39 PM PDT 24
Finished Aug 08 08:48:14 PM PDT 24
Peak memory 610164 kb
Host smart-82a1b375-dc59-4865-bd87-8d13fd0c78b9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232490792 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.chip_sw_hmac_multistream.232490792
Directory /workspace/0.chip_sw_hmac_multistream/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_oneshot.346741799
Short name T1222
Test name
Test status
Simulation time 3496256228 ps
CPU time 316.56 seconds
Started Aug 08 08:19:09 PM PDT 24
Finished Aug 08 08:24:26 PM PDT 24
Peak memory 609268 kb
Host smart-d1ff244c-20bb-40a6-b9cf-c9b5e1cfec1a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346741799 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_hmac_oneshot.346741799
Directory /workspace/0.chip_sw_hmac_oneshot/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_smoketest.2612461123
Short name T908
Test name
Test status
Simulation time 3368382432 ps
CPU time 317.32 seconds
Started Aug 08 08:22:29 PM PDT 24
Finished Aug 08 08:27:46 PM PDT 24
Peak memory 609656 kb
Host smart-62bb4ea5-3806-4c6d-a518-def8b2524065
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612461123 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_hmac_smoketest.2612461123
Directory /workspace/0.chip_sw_hmac_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3685761158
Short name T322
Test name
Test status
Simulation time 4377458682 ps
CPU time 519.27 seconds
Started Aug 08 08:18:15 PM PDT 24
Finished Aug 08 08:26:55 PM PDT 24
Peak memory 609548 kb
Host smart-9ef0da01-3858-41b7-b41a-512d3c1d6f83
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685761158 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.3685761158
Directory /workspace/0.chip_sw_i2c_device_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2695922951
Short name T308
Test name
Test status
Simulation time 5244742410 ps
CPU time 909.12 seconds
Started Aug 08 08:16:47 PM PDT 24
Finished Aug 08 08:31:57 PM PDT 24
Peak memory 609368 kb
Host smart-9bf75b44-e15d-4f70-9ecb-a9ec1d39051d
User root
Command /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695922951 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.2695922951
Directory /workspace/0.chip_sw_i2c_host_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1093070190
Short name T1007
Test name
Test status
Simulation time 5597232524 ps
CPU time 860.89 seconds
Started Aug 08 08:16:02 PM PDT 24
Finished Aug 08 08:30:23 PM PDT 24
Peak memory 609476 kb
Host smart-bee5a344-cc38-44be-ad46-0701456a3286
User root
Command /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093070190 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.1093070190
Directory /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3464981339
Short name T337
Test name
Test status
Simulation time 5525514230 ps
CPU time 986.65 seconds
Started Aug 08 08:19:25 PM PDT 24
Finished Aug 08 08:35:53 PM PDT 24
Peak memory 609972 kb
Host smart-a8f24149-d5b9-43fb-9905-711c32c5900e
User root
Command /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464981339 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.3464981339
Directory /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest

Test location /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3042088238
Short name T1156
Test name
Test status
Simulation time 64451500991 ps
CPU time 12235.7 seconds
Started Aug 08 08:17:06 PM PDT 24
Finished Aug 08 11:41:04 PM PDT 24
Peak memory 624684 kb
Host smart-89517189-22ad-4520-8004-22237febe016
User root
Command /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3042088238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.3042088238
Directory /workspace/0.chip_sw_inject_scramble_seed/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1933522299
Short name T1053
Test name
Test status
Simulation time 8875293720 ps
CPU time 2188.68 seconds
Started Aug 08 08:20:54 PM PDT 24
Finished Aug 08 08:57:23 PM PDT 24
Peak memory 616540 kb
Host smart-5cd40006-7388-4cef-8111-ab330c9701ef
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933
522299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.1933522299
Directory /workspace/0.chip_sw_keymgr_key_derivation/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2041314332
Short name T971
Test name
Test status
Simulation time 12452502000 ps
CPU time 2618.58 seconds
Started Aug 08 08:18:47 PM PDT 24
Finished Aug 08 09:02:26 PM PDT 24
Peak memory 618144 kb
Host smart-4043892d-6a0f-4560-96d1-3319802eb87a
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2041314332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.2041314332
Directory /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1310401197
Short name T1029
Test name
Test status
Simulation time 6971949973 ps
CPU time 1003.8 seconds
Started Aug 08 08:20:24 PM PDT 24
Finished Aug 08 08:37:08 PM PDT 24
Peak memory 617804 kb
Host smart-685c8e55-8a1a-4534-838c-22319315e5d9
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1310401197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en
_reduced_freq.1310401197
Directory /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2688149452
Short name T1205
Test name
Test status
Simulation time 10207373150 ps
CPU time 2080 seconds
Started Aug 08 08:17:43 PM PDT 24
Finished Aug 08 08:52:23 PM PDT 24
Peak memory 617836 kb
Host smart-791f7e20-02a3-468a-bc2b-a35579df7e68
User root
Command /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2688149452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.2688149452
Directory /workspace/0.chip_sw_keymgr_key_derivation_prod/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.788290785
Short name T977
Test name
Test status
Simulation time 8793592710 ps
CPU time 1397.8 seconds
Started Aug 08 08:18:29 PM PDT 24
Finished Aug 08 08:41:47 PM PDT 24
Peak memory 611008 kb
Host smart-1c5f4317-d85c-42cd-9725-bbc5dfc13df8
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78829
0785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.788290785
Directory /workspace/0.chip_sw_keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2858031908
Short name T274
Test name
Test status
Simulation time 15220493926 ps
CPU time 4526.07 seconds
Started Aug 08 08:18:53 PM PDT 24
Finished Aug 08 09:34:20 PM PDT 24
Peak memory 609632 kb
Host smart-165952d2-fe5c-4da3-93ae-75da14cde4bc
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28580
31908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2858031908
Directory /workspace/0.chip_sw_keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_app_rom.1146403019
Short name T1292
Test name
Test status
Simulation time 2678206572 ps
CPU time 172.29 seconds
Started Aug 08 08:16:20 PM PDT 24
Finished Aug 08 08:19:12 PM PDT 24
Peak memory 609312 kb
Host smart-e368edb1-1777-4b73-af7a-1afd17f77f4a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146403019 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_kmac_app_rom.1146403019
Directory /workspace/0.chip_sw_kmac_app_rom/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_entropy.3438762844
Short name T1281
Test name
Test status
Simulation time 3064692344 ps
CPU time 301.18 seconds
Started Aug 08 08:16:47 PM PDT 24
Finished Aug 08 08:21:49 PM PDT 24
Peak memory 609500 kb
Host smart-df7c14f9-7fc2-40d4-bd04-b003098e8d2b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438762844 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_kmac_entropy.3438762844
Directory /workspace/0.chip_sw_kmac_entropy/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2900076915
Short name T265
Test name
Test status
Simulation time 2718694328 ps
CPU time 243.15 seconds
Started Aug 08 08:17:15 PM PDT 24
Finished Aug 08 08:21:19 PM PDT 24
Peak memory 609668 kb
Host smart-18a5c4c7-3514-49f7-ac26-e489400ee755
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900076915 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.chip_sw_kmac_mode_cshake.2900076915
Directory /workspace/0.chip_sw_kmac_mode_cshake/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2683680111
Short name T1191
Test name
Test status
Simulation time 3154425400 ps
CPU time 370.26 seconds
Started Aug 08 08:18:35 PM PDT 24
Finished Aug 08 08:24:46 PM PDT 24
Peak memory 609756 kb
Host smart-4597c204-35a2-41b5-9703-14f9b32c9596
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683680111 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.chip_sw_kmac_mode_kmac.2683680111
Directory /workspace/0.chip_sw_kmac_mode_kmac/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.502337046
Short name T390
Test name
Test status
Simulation time 4006704159 ps
CPU time 357.36 seconds
Started Aug 08 08:17:04 PM PDT 24
Finished Aug 08 08:23:02 PM PDT 24
Peak memory 609704 kb
Host smart-d2542d5d-732a-4399-98ca-40b124961f70
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502337046 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.502337046
Directory /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2196991017
Short name T1065
Test name
Test status
Simulation time 3323278049 ps
CPU time 310.22 seconds
Started Aug 08 08:18:27 PM PDT 24
Finished Aug 08 08:23:37 PM PDT 24
Peak memory 608536 kb
Host smart-9ee62f2e-672a-4e37-85d2-11c275328609
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21969910
17 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2196991017
Directory /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_smoketest.3183951014
Short name T1300
Test name
Test status
Simulation time 3363635800 ps
CPU time 364.63 seconds
Started Aug 08 08:22:04 PM PDT 24
Finished Aug 08 08:28:09 PM PDT 24
Peak memory 609628 kb
Host smart-3000cbcc-7b00-44cc-bad4-359df802be90
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183951014 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_kmac_smoketest.3183951014
Directory /workspace/0.chip_sw_kmac_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2983002907
Short name T1149
Test name
Test status
Simulation time 3687405000 ps
CPU time 335.57 seconds
Started Aug 08 08:16:32 PM PDT 24
Finished Aug 08 08:22:08 PM PDT 24
Peak memory 609364 kb
Host smart-7eedafde-dcfa-4a16-b7f7-db6c452be3d6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983002907 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.2983002907
Directory /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.339470459
Short name T246
Test name
Test status
Simulation time 3011013044 ps
CPU time 156.69 seconds
Started Aug 08 08:17:58 PM PDT 24
Finished Aug 08 08:20:36 PM PDT 24
Peak memory 620136 kb
Host smart-9cf279ab-7bd3-4e5a-8af7-85fed890f948
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33947045
9 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.339470459
Directory /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.437719707
Short name T632
Test name
Test status
Simulation time 2786293471 ps
CPU time 145.51 seconds
Started Aug 08 08:16:05 PM PDT 24
Finished Aug 08 08:18:30 PM PDT 24
Peak memory 620692 kb
Host smart-f8c6b45a-6e8e-4bd5-8b94-0acdaac06cc1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules
,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=437719707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.437719707
Directory /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1450418201
Short name T176
Test name
Test status
Simulation time 2754589753 ps
CPU time 246.33 seconds
Started Aug 08 08:15:49 PM PDT 24
Finished Aug 08 08:19:55 PM PDT 24
Peak memory 621756 kb
Host smart-ec35768b-089d-40bb-b5e1-0fbceb51eb58
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules
,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1450418201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.1450418201
Directory /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.68665587
Short name T50
Test name
Test status
Simulation time 3878087215 ps
CPU time 141.15 seconds
Started Aug 08 08:15:48 PM PDT 24
Finished Aug 08 08:18:09 PM PDT 24
Peak memory 620040 kb
Host smart-f8f8df76-063f-4b5d-a04f-177870682d6c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68665587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.68665587
Directory /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.4185279599
Short name T1318
Test name
Test status
Simulation time 13056143110 ps
CPU time 1080 seconds
Started Aug 08 08:16:11 PM PDT 24
Finished Aug 08 08:34:12 PM PDT 24
Peak memory 622468 kb
Host smart-19d991e3-0311-4fd9-a211-7062a92ad07f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185279599 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.4185279599
Directory /workspace/0.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2567299994
Short name T1268
Test name
Test status
Simulation time 2829286492 ps
CPU time 113.22 seconds
Started Aug 08 08:15:14 PM PDT 24
Finished Aug 08 08:17:07 PM PDT 24
Peak memory 617044 kb
Host smart-1faf9abb-ae8b-45ab-8eda-9e12e3617c57
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes
t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2567299994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.2567299994
Directory /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2230706026
Short name T1151
Test name
Test status
Simulation time 3202570573 ps
CPU time 130.47 seconds
Started Aug 08 08:15:53 PM PDT 24
Finished Aug 08 08:18:04 PM PDT 24
Peak memory 617388 kb
Host smart-02969d42-37f6-4bf9-89b6-a89f9a21fd9f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s
im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230706026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2230706026
Directory /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3052495603
Short name T1221
Test name
Test status
Simulation time 51765575975 ps
CPU time 5729.02 seconds
Started Aug 08 08:17:50 PM PDT 24
Finished Aug 08 09:53:20 PM PDT 24
Peak memory 620316 kb
Host smart-0222f133-80b4-4060-aa82-33be69bc6a50
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052495603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip
_sw_lc_walkthrough_dev.3052495603
Directory /workspace/0.chip_sw_lc_walkthrough_dev/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.676693783
Short name T282
Test name
Test status
Simulation time 51727489624 ps
CPU time 5739.36 seconds
Started Aug 08 08:16:56 PM PDT 24
Finished Aug 08 09:52:36 PM PDT 24
Peak memory 620576 kb
Host smart-a3e9cfbf-88c3-444a-84f4-26d4e891c6b6
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d
evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676693783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip
_sw_lc_walkthrough_prod.676693783
Directory /workspace/0.chip_sw_lc_walkthrough_prod/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1685385707
Short name T1063
Test name
Test status
Simulation time 8494134577 ps
CPU time 898.33 seconds
Started Aug 08 08:18:14 PM PDT 24
Finished Aug 08 08:33:14 PM PDT 24
Peak memory 619024 kb
Host smart-7e2f08f8-4010-489e-b2c5-eeda1a8bd6d8
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa
lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685385707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.1685385707
Directory /workspace/0.chip_sw_lc_walkthrough_prodend/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2878601415
Short name T284
Test name
Test status
Simulation time 45452995098 ps
CPU time 5390.2 seconds
Started Aug 08 08:17:11 PM PDT 24
Finished Aug 08 09:47:02 PM PDT 24
Peak memory 620584 kb
Host smart-ff2d2a21-140d-41f4-892a-258ff0ee91be
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878601415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip
_sw_lc_walkthrough_rma.2878601415
Directory /workspace/0.chip_sw_lc_walkthrough_rma/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2856039399
Short name T1309
Test name
Test status
Simulation time 23592755982 ps
CPU time 2194.73 seconds
Started Aug 08 08:17:49 PM PDT 24
Finished Aug 08 08:54:25 PM PDT 24
Peak memory 621092 kb
Host smart-84ce7b49-8e9f-4508-bb28-9f6feb770615
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks
_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2856039399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun
locks.2856039399
Directory /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.4065360456
Short name T153
Test name
Test status
Simulation time 18443596664 ps
CPU time 3934.86 seconds
Started Aug 08 08:18:28 PM PDT 24
Finished Aug 08 09:24:03 PM PDT 24
Peak memory 610264 kb
Host smart-babda81f-8721-4fb1-881d-a92e63229c61
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne
w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4065360456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.4065360456
Directory /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2034348537
Short name T613
Test name
Test status
Simulation time 25002845164 ps
CPU time 4288.6 seconds
Started Aug 08 08:18:54 PM PDT 24
Finished Aug 08 09:30:23 PM PDT 24
Peak memory 610324 kb
Host smart-cf896fb0-57bb-4aea-85a5-d128f86ce1dd
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e
cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034348537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu
ced_freq.2034348537
Directory /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3938888228
Short name T1079
Test name
Test status
Simulation time 2938731702 ps
CPU time 475.54 seconds
Started Aug 08 08:17:56 PM PDT 24
Finished Aug 08 08:25:51 PM PDT 24
Peak memory 609700 kb
Host smart-4cb25649-317d-4e6a-98d6-69b3addd2d70
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn
_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938888228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.3938888228
Directory /workspace/0.chip_sw_otbn_mem_scramble/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_randomness.2391609756
Short name T905
Test name
Test status
Simulation time 6506812960 ps
CPU time 903.54 seconds
Started Aug 08 08:20:39 PM PDT 24
Finished Aug 08 08:35:43 PM PDT 24
Peak memory 610252 kb
Host smart-e2160add-8569-45ed-bb85-33c479954e45
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2391609756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.2391609756
Directory /workspace/0.chip_sw_otbn_randomness/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_smoketest.223380273
Short name T152
Test name
Test status
Simulation time 9079616120 ps
CPU time 2088.7 seconds
Started Aug 08 08:21:18 PM PDT 24
Finished Aug 08 08:56:08 PM PDT 24
Peak memory 609484 kb
Host smart-3fb0357e-f6dc-4ffd-b0f7-124a586dd2a3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223380273 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_otbn_smoketest.223380273
Directory /workspace/0.chip_sw_otbn_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.514374686
Short name T966
Test name
Test status
Simulation time 28337106758 ps
CPU time 4959.13 seconds
Started Aug 08 08:15:23 PM PDT 24
Finished Aug 08 09:38:03 PM PDT 24
Peak memory 610240 kb
Host smart-ed5aeaf0-828c-48b1-882e-d4d7372819a9
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514374
686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.514374686
Directory /workspace/0.chip_sw_otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1109570114
Short name T4
Test name
Test status
Simulation time 3489271008 ps
CPU time 318.66 seconds
Started Aug 08 08:17:44 PM PDT 24
Finished Aug 08 08:23:03 PM PDT 24
Peak memory 609016 kb
Host smart-5e630bbe-9057-4aec-9027-0c842e7e953e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109570114 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.1109570114
Directory /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.411772536
Short name T1042
Test name
Test status
Simulation time 7323235796 ps
CPU time 1385.65 seconds
Started Aug 08 08:17:22 PM PDT 24
Finished Aug 08 08:40:28 PM PDT 24
Peak memory 610616 kb
Host smart-be52f0db-c967-4ae2-8875-397c62abcd78
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=411772536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.411772536
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.218831320
Short name T1194
Test name
Test status
Simulation time 8716021060 ps
CPU time 1477.04 seconds
Started Aug 08 08:19:18 PM PDT 24
Finished Aug 08 08:43:56 PM PDT 24
Peak memory 610680 kb
Host smart-2258bd2f-95ce-4c13-a083-4a38a3a83e8c
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=218831320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.218831320
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.376038329
Short name T1108
Test name
Test status
Simulation time 7186029760 ps
CPU time 1268.14 seconds
Started Aug 08 08:20:08 PM PDT 24
Finished Aug 08 08:41:17 PM PDT 24
Peak memory 610684 kb
Host smart-91b73d33-3248-4dc5-b815-d1513382e8f8
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=376038329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.376038329
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4117150879
Short name T1067
Test name
Test status
Simulation time 4421986922 ps
CPU time 564.71 seconds
Started Aug 08 08:16:24 PM PDT 24
Finished Aug 08 08:25:49 PM PDT 24
Peak memory 610064 kb
Host smart-06e4fd74-1475-4781-bfa2-e0d59f1d533a
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=4117150879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4117150879
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3806131405
Short name T868
Test name
Test status
Simulation time 2074494060 ps
CPU time 178.82 seconds
Started Aug 08 08:22:47 PM PDT 24
Finished Aug 08 08:25:46 PM PDT 24
Peak memory 609600 kb
Host smart-72436454-6657-4c68-a0a1-635a19dc1f1f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806131405 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_otp_ctrl_smoketest.3806131405
Directory /workspace/0.chip_sw_otp_ctrl_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_pattgen_ios.4133145448
Short name T338
Test name
Test status
Simulation time 2939905272 ps
CPU time 216.03 seconds
Started Aug 08 08:14:48 PM PDT 24
Finished Aug 08 08:18:25 PM PDT 24
Peak memory 612380 kb
Host smart-ed4544c1-e651-4fbb-97ad-47c0059a439b
User root
Command /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133145448 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.4133145448
Directory /workspace/0.chip_sw_pattgen_ios/latest

Test location /workspace/coverage/default/0.chip_sw_power_idle_load.2457541674
Short name T967
Test name
Test status
Simulation time 4045018588 ps
CPU time 640.99 seconds
Started Aug 08 08:20:39 PM PDT 24
Finished Aug 08 08:31:21 PM PDT 24
Peak memory 609476 kb
Host smart-c950a50b-28d9-4787-8898-e4333265bd6a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457541674 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.2457541674
Directory /workspace/0.chip_sw_power_idle_load/latest

Test location /workspace/coverage/default/0.chip_sw_power_sleep_load.31301605
Short name T1107
Test name
Test status
Simulation time 11403249234 ps
CPU time 743.67 seconds
Started Aug 08 08:19:01 PM PDT 24
Finished Aug 08 08:31:25 PM PDT 24
Peak memory 609968 kb
Host smart-daa69d7f-af8e-4afd-90cd-b9b4edae6c65
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31301605 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.31301605
Directory /workspace/0.chip_sw_power_sleep_load/latest

Test location /workspace/coverage/default/0.chip_sw_power_virus.3015977932
Short name T202
Test name
Test status
Simulation time 6178428064 ps
CPU time 1643.18 seconds
Started Aug 08 08:24:20 PM PDT 24
Finished Aug 08 08:51:43 PM PDT 24
Peak memory 624996 kb
Host smart-22aa8f47-c373-4889-94c4-d031ba8cda47
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_
power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes
t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3015977932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.3015977932
Directory /workspace/0.chip_sw_power_virus/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.177264067
Short name T169
Test name
Test status
Simulation time 9510088732 ps
CPU time 1678.02 seconds
Started Aug 08 08:17:48 PM PDT 24
Finished Aug 08 08:45:47 PM PDT 24
Peak memory 611480 kb
Host smart-21fd546b-1035-4a43-a363-2abca199adb0
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772
64067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.177264067
Directory /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2338194440
Short name T920
Test name
Test status
Simulation time 26003624432 ps
CPU time 2303.69 seconds
Started Aug 08 08:19:53 PM PDT 24
Finished Aug 08 08:58:17 PM PDT 24
Peak memory 610928 kb
Host smart-0cdc95e3-5e21-4bc5-8462-77bd47052e89
User root
Command /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233
8194440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.2338194440
Directory /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1017486755
Short name T921
Test name
Test status
Simulation time 13140647551 ps
CPU time 1574.04 seconds
Started Aug 08 08:17:45 PM PDT 24
Finished Aug 08 08:43:59 PM PDT 24
Peak memory 611520 kb
Host smart-20e360ff-bf1c-43ce-99a5-70d33b757230
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1017486755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1017486755
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1922534267
Short name T110
Test name
Test status
Simulation time 21876701506 ps
CPU time 2239.78 seconds
Started Aug 08 08:20:36 PM PDT 24
Finished Aug 08 08:57:56 PM PDT 24
Peak memory 610828 kb
Host smart-3ba349e0-5023-4321-b0a4-669ad8643051
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1922534267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1922534267
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.4116219082
Short name T972
Test name
Test status
Simulation time 8470180520 ps
CPU time 902.17 seconds
Started Aug 08 08:18:06 PM PDT 24
Finished Aug 08 08:33:08 PM PDT 24
Peak memory 610760 kb
Host smart-3de87975-98b2-4aea-8e89-282ad0d5fc65
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116219082 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.4116219082
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2620959255
Short name T1206
Test name
Test status
Simulation time 3796896274 ps
CPU time 463.97 seconds
Started Aug 08 08:20:21 PM PDT 24
Finished Aug 08 08:28:06 PM PDT 24
Peak memory 616288 kb
Host smart-c77c1a09-042d-464c-82c2-52bca99cc048
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2620959255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.2620959255
Directory /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2685150362
Short name T975
Test name
Test status
Simulation time 10399172135 ps
CPU time 1340.8 seconds
Started Aug 08 08:18:10 PM PDT 24
Finished Aug 08 08:40:32 PM PDT 24
Peak memory 611420 kb
Host smart-d22800e2-90b4-4371-995d-78d85f1ccfc7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685150362 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2685150362
Directory /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3108801265
Short name T1234
Test name
Test status
Simulation time 7556782296 ps
CPU time 401.39 seconds
Started Aug 08 08:18:09 PM PDT 24
Finished Aug 08 08:24:51 PM PDT 24
Peak memory 610324 kb
Host smart-b066aee6-4232-4afd-8604-f098c42f1907
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108801265 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3108801265
Directory /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1332725706
Short name T1124
Test name
Test status
Simulation time 7110343170 ps
CPU time 583.63 seconds
Started Aug 08 08:16:07 PM PDT 24
Finished Aug 08 08:25:51 PM PDT 24
Peak memory 610824 kb
Host smart-903d7ffe-d317-4b08-b246-4a2e60b71ab3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332725706 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.1332725706
Directory /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1777392700
Short name T901
Test name
Test status
Simulation time 22907958147 ps
CPU time 2464.71 seconds
Started Aug 08 08:16:54 PM PDT 24
Finished Aug 08 08:57:59 PM PDT 24
Peak memory 611536 kb
Host smart-0438b7ec-9f17-448a-9394-dfe32a6a58b9
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1777392700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1777392700
Directory /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1773535819
Short name T401
Test name
Test status
Simulation time 20952446696 ps
CPU time 1735.9 seconds
Started Aug 08 08:19:51 PM PDT 24
Finished Aug 08 08:48:47 PM PDT 24
Peak memory 610972 kb
Host smart-ca45a13b-544c-426d-911f-9a0d11e04f79
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1773535819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1773535819
Directory /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3305987150
Short name T1072
Test name
Test status
Simulation time 43484008209 ps
CPU time 3362.73 seconds
Started Aug 08 08:18:43 PM PDT 24
Finished Aug 08 09:14:46 PM PDT 24
Peak memory 611808 kb
Host smart-668673ac-1f3a-45cb-b6e4-d0a38c57a856
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power
_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305987150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit
ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s
leep_power_glitch_reset.3305987150
Directory /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2372602914
Short name T644
Test name
Test status
Simulation time 3344615396 ps
CPU time 302.08 seconds
Started Aug 08 08:18:52 PM PDT 24
Finished Aug 08 08:23:54 PM PDT 24
Peak memory 609416 kb
Host smart-e74b73bd-e2b3-4e2d-bc72-8eeaf3e66f3e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372602914 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.2372602914
Directory /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.855839545
Short name T34
Test name
Test status
Simulation time 5078215437 ps
CPU time 365.44 seconds
Started Aug 08 08:18:50 PM PDT 24
Finished Aug 08 08:24:56 PM PDT 24
Peak memory 616296 kb
Host smart-23835d74-1406-452e-bb0d-eb68e19827d1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=855839545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.855839545
Directory /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2237859482
Short name T1120
Test name
Test status
Simulation time 5650326860 ps
CPU time 322.25 seconds
Started Aug 08 08:21:02 PM PDT 24
Finished Aug 08 08:26:25 PM PDT 24
Peak memory 610772 kb
Host smart-93d27934-dfc4-42e8-9e9e-3761360bbbc4
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2237859482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.2237859482
Directory /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1320879860
Short name T1343
Test name
Test status
Simulation time 5904280472 ps
CPU time 379.64 seconds
Started Aug 08 08:22:57 PM PDT 24
Finished Aug 08 08:29:16 PM PDT 24
Peak memory 610492 kb
Host smart-bb3f01b4-7bcb-4c91-b9ed-dc43ca89be09
User root
Command /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320879860 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.1320879860
Directory /workspace/0.chip_sw_pwrmgr_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3109241174
Short name T919
Test name
Test status
Simulation time 7798550364 ps
CPU time 957.97 seconds
Started Aug 08 08:15:37 PM PDT 24
Finished Aug 08 08:31:36 PM PDT 24
Peak memory 610876 kb
Host smart-e0cfd6da-2607-40ef-a8ac-d3316dcd4586
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109241174 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.3109241174
Directory /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1112672058
Short name T995
Test name
Test status
Simulation time 5030453040 ps
CPU time 511.41 seconds
Started Aug 08 08:16:26 PM PDT 24
Finished Aug 08 08:24:58 PM PDT 24
Peak memory 610612 kb
Host smart-982e4714-47ec-4914-aec5-aa442b99b9f8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112672058 -assert no
postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1112672058
Directory /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3915016242
Short name T915
Test name
Test status
Simulation time 5932205952 ps
CPU time 350.95 seconds
Started Aug 08 08:21:32 PM PDT 24
Finished Aug 08 08:27:23 PM PDT 24
Peak memory 610376 kb
Host smart-3484f3fe-c7b2-4a22-9466-d5bc06a47fcd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915016242 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.3915016242
Directory /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3021152228
Short name T948
Test name
Test status
Simulation time 5171814460 ps
CPU time 409.74 seconds
Started Aug 08 08:15:46 PM PDT 24
Finished Aug 08 08:22:36 PM PDT 24
Peak memory 610464 kb
Host smart-d4a25c8b-cc8f-4aa9-9c19-3be951a38970
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302
1152228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.3021152228
Directory /workspace/0.chip_sw_pwrmgr_wdog_reset/latest

Test location /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2393842462
Short name T1247
Test name
Test status
Simulation time 8756242170 ps
CPU time 574.29 seconds
Started Aug 08 08:18:45 PM PDT 24
Finished Aug 08 08:28:19 PM PDT 24
Peak memory 623800 kb
Host smart-30348680-fa7b-4f1d-aa37-579f97cd3096
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393842462 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.2393842462
Directory /workspace/0.chip_sw_rom_ctrl_integrity_check/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1448000056
Short name T243
Test name
Test status
Simulation time 6742031752 ps
CPU time 652.8 seconds
Started Aug 08 08:18:48 PM PDT 24
Finished Aug 08 08:29:41 PM PDT 24
Peak memory 610564 kb
Host smart-4343b7ee-3bfd-4556-becd-e2c1989532b6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448000056 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.1448000056
Directory /workspace/0.chip_sw_rstmgr_cpu_info/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.916391677
Short name T1223
Test name
Test status
Simulation time 5063230584 ps
CPU time 708.62 seconds
Started Aug 08 08:15:51 PM PDT 24
Finished Aug 08 08:27:40 PM PDT 24
Peak memory 641440 kb
Host smart-99c87646-6d84-4a0c-93aa-48f542aacb48
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
916391677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.916391677
Directory /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2635383438
Short name T1338
Test name
Test status
Simulation time 2038193656 ps
CPU time 190.1 seconds
Started Aug 08 08:22:09 PM PDT 24
Finished Aug 08 08:25:20 PM PDT 24
Peak memory 609540 kb
Host smart-6e2c96d6-8885-4020-bfb9-96376d869038
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635383438 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.chip_sw_rstmgr_smoketest.2635383438
Directory /workspace/0.chip_sw_rstmgr_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3705270450
Short name T354
Test name
Test status
Simulation time 3684489512 ps
CPU time 424.94 seconds
Started Aug 08 08:15:36 PM PDT 24
Finished Aug 08 08:22:42 PM PDT 24
Peak memory 610128 kb
Host smart-4bd31b7d-0de9-4d2f-ae37-a190c40e1682
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705270450 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_rstmgr_sw_req.3705270450
Directory /workspace/0.chip_sw_rstmgr_sw_req/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.447118617
Short name T1250
Test name
Test status
Simulation time 2584442296 ps
CPU time 228.95 seconds
Started Aug 08 08:15:54 PM PDT 24
Finished Aug 08 08:19:43 PM PDT 24
Peak memory 609588 kb
Host smart-184f2566-1db8-4763-b8c1-bdf59e555b3c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447118617 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.447118617
Directory /workspace/0.chip_sw_rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2015329542
Short name T179
Test name
Test status
Simulation time 2889866947 ps
CPU time 239.89 seconds
Started Aug 08 08:23:03 PM PDT 24
Finished Aug 08 08:27:03 PM PDT 24
Peak memory 608588 kb
Host smart-a7c2c4d2-694a-47ac-9843-bff7563e6f78
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015329542 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.2015329542
Directory /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3624713069
Short name T237
Test name
Test status
Simulation time 5641672026 ps
CPU time 947.89 seconds
Started Aug 08 08:16:32 PM PDT 24
Finished Aug 08 08:32:20 PM PDT 24
Peak memory 609972 kb
Host smart-c95040a3-5542-476e-a70e-5cb6a7d9f99c
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3624713069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.3624713069
Directory /workspace/0.chip_sw_rv_core_ibex_rnd/latest

Test location /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.56367101
Short name T627
Test name
Test status
Simulation time 5362881089 ps
CPU time 665.17 seconds
Started Aug 08 08:20:33 PM PDT 24
Finished Aug 08 08:31:39 PM PDT 24
Peak memory 624360 kb
Host smart-a80da1ea-fd1a-455a-84df-6e0f39b6d8a5
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56367101 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.56367101
Directory /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2577873302
Short name T1199
Test name
Test status
Simulation time 6431834388 ps
CPU time 509.34 seconds
Started Aug 08 08:19:33 PM PDT 24
Finished Aug 08 08:28:02 PM PDT 24
Peak memory 621412 kb
Host smart-3f73ff99-5165-4a4d-8e93-f4bcfc7d534a
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577873302 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.2577873302
Directory /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest

Test location /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2238828062
Short name T298
Test name
Test status
Simulation time 4490775032 ps
CPU time 635.4 seconds
Started Aug 08 08:20:25 PM PDT 24
Finished Aug 08 08:31:01 PM PDT 24
Peak memory 621008 kb
Host smart-5f455a85-a23e-4b28-9051-fca49ecf7577
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223882
8062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2238828062
Directory /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3880900618
Short name T321
Test name
Test status
Simulation time 2921456180 ps
CPU time 223.15 seconds
Started Aug 08 08:21:19 PM PDT 24
Finished Aug 08 08:25:03 PM PDT 24
Peak memory 609756 kb
Host smart-d0604440-9bbe-46e5-b3af-081aedcaa8ce
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880900618 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_rv_plic_smoketest.3880900618
Directory /workspace/0.chip_sw_rv_plic_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_rv_timer_irq.2322258466
Short name T1277
Test name
Test status
Simulation time 3356293184 ps
CPU time 271.29 seconds
Started Aug 08 08:18:22 PM PDT 24
Finished Aug 08 08:22:54 PM PDT 24
Peak memory 609596 kb
Host smart-ed804fc3-b378-4817-b20c-dbb237b0c59c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322258466 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_rv_timer_irq.2322258466
Directory /workspace/0.chip_sw_rv_timer_irq/latest

Test location /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2990744858
Short name T1076
Test name
Test status
Simulation time 2920099546 ps
CPU time 217.39 seconds
Started Aug 08 08:21:12 PM PDT 24
Finished Aug 08 08:24:49 PM PDT 24
Peak memory 609232 kb
Host smart-84bcd890-ba07-45f6-a774-63f6acc2050a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990744858 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_rv_timer_smoketest.2990744858
Directory /workspace/0.chip_sw_rv_timer_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1546750333
Short name T145
Test name
Test status
Simulation time 2689241954 ps
CPU time 347.93 seconds
Started Aug 08 08:17:44 PM PDT 24
Finished Aug 08 08:23:32 PM PDT 24
Peak memory 610480 kb
Host smart-d1203426-360d-4417-87fe-2efaddb8ce85
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546750
333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.1546750333
Directory /workspace/0.chip_sw_sensor_ctrl_status/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2707879428
Short name T65
Test name
Test status
Simulation time 4024867752 ps
CPU time 290.62 seconds
Started Aug 08 08:16:45 PM PDT 24
Finished Aug 08 08:21:36 PM PDT 24
Peak memory 609400 kb
Host smart-83314c70-2227-477d-8ce5-aca11045137a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707879428 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.2707879428
Directory /workspace/0.chip_sw_sleep_pin_retention/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2302843488
Short name T654
Test name
Test status
Simulation time 9203512888 ps
CPU time 1204.88 seconds
Started Aug 08 08:16:43 PM PDT 24
Finished Aug 08 08:36:48 PM PDT 24
Peak memory 610588 kb
Host smart-446476d9-6ea2-47d6-b7f0-8a821ae8aabe
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302843488 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.2302843488
Directory /workspace/0.chip_sw_sleep_pwm_pulses/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1659002845
Short name T514
Test name
Test status
Simulation time 8398478700 ps
CPU time 918.25 seconds
Started Aug 08 08:19:03 PM PDT 24
Finished Aug 08 08:34:22 PM PDT 24
Peak memory 610388 kb
Host smart-2285faf8-fe55-4d5b-8ebf-af740393d324
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659002845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl
eep_sram_ret_contents_no_scramble.1659002845
Directory /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1344985420
Short name T1230
Test name
Test status
Simulation time 8569665308 ps
CPU time 558.7 seconds
Started Aug 08 08:19:07 PM PDT 24
Finished Aug 08 08:28:26 PM PDT 24
Peak memory 610612 kb
Host smart-c62366cf-5379-480b-a626-da0c6a3ddb2d
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344985420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep
_sram_ret_contents_scramble.1344985420
Directory /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_pass_through.1329425319
Short name T200
Test name
Test status
Simulation time 6680746052 ps
CPU time 489.49 seconds
Started Aug 08 08:15:58 PM PDT 24
Finished Aug 08 08:24:07 PM PDT 24
Peak memory 623108 kb
Host smart-eaa3572b-0611-4f1c-8a2e-8ef8db1d72a4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329425319 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.1329425319
Directory /workspace/0.chip_sw_spi_device_pass_through/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_tpm.1370941744
Short name T42
Test name
Test status
Simulation time 3471129014 ps
CPU time 300.25 seconds
Started Aug 08 08:16:26 PM PDT 24
Finished Aug 08 08:21:27 PM PDT 24
Peak memory 618428 kb
Host smart-80c82092-9799-45d2-95a9-f99b75382bc8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370941744 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.1370941744
Directory /workspace/0.chip_sw_spi_device_tpm/latest

Test location /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1964848243
Short name T38
Test name
Test status
Simulation time 3156100894 ps
CPU time 281.99 seconds
Started Aug 08 08:15:36 PM PDT 24
Finished Aug 08 08:20:19 PM PDT 24
Peak memory 610040 kb
Host smart-d0e19421-8faf-46a7-98c8-a801dc2c6364
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964848243 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.1964848243
Directory /workspace/0.chip_sw_spi_host_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.14380084
Short name T178
Test name
Test status
Simulation time 5036676040 ps
CPU time 524.92 seconds
Started Aug 08 08:18:37 PM PDT 24
Finished Aug 08 08:27:22 PM PDT 24
Peak memory 611112 kb
Host smart-cbecc290-e0f8-42a8-acea-ff2f4f094744
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14380084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_
scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_s
ram_ctrl_scrambled_access.14380084
Directory /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1720380719
Short name T355
Test name
Test status
Simulation time 3566780266 ps
CPU time 498.3 seconds
Started Aug 08 08:18:37 PM PDT 24
Finished Aug 08 08:26:56 PM PDT 24
Peak memory 610872 kb
Host smart-67e5dd96-2a36-41aa-8cbe-b563f94414c5
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s
w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720380719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1720380719
Directory /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1453197546
Short name T177
Test name
Test status
Simulation time 4940079525 ps
CPU time 480.65 seconds
Started Aug 08 08:20:35 PM PDT 24
Finished Aug 08 08:28:36 PM PDT 24
Peak memory 610764 kb
Host smart-0f779ab6-2435-4569-9dce-4a6d95dcadbe
User root
Command /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk
_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453197546 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1453197546
Directory /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.4033443070
Short name T1069
Test name
Test status
Simulation time 3251053048 ps
CPU time 186.46 seconds
Started Aug 08 08:23:14 PM PDT 24
Finished Aug 08 08:26:21 PM PDT 24
Peak memory 609392 kb
Host smart-74a562ba-973f-498a-bcd2-755d3417dd14
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033443070 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.4033443070
Directory /workspace/0.chip_sw_sram_ctrl_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3062233071
Short name T1158
Test name
Test status
Simulation time 20380478932 ps
CPU time 3534.98 seconds
Started Aug 08 08:18:37 PM PDT 24
Finished Aug 08 09:17:33 PM PDT 24
Peak memory 609272 kb
Host smart-92674f14-d3af-4b82-8466-fecc207df557
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062233071 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.3062233071
Directory /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.703252541
Short name T211
Test name
Test status
Simulation time 2929668894 ps
CPU time 274.53 seconds
Started Aug 08 08:16:39 PM PDT 24
Finished Aug 08 08:21:14 PM PDT 24
Peak memory 613112 kb
Host smart-fe62e206-a9a2-4009-bd5c-44b77d26d9a5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703252541 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.703252541
Directory /workspace/0.chip_sw_sysrst_ctrl_inputs/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1237601300
Short name T22
Test name
Test status
Simulation time 3611079518 ps
CPU time 386.59 seconds
Started Aug 08 08:15:49 PM PDT 24
Finished Aug 08 08:22:16 PM PDT 24
Peak memory 609292 kb
Host smart-c86f14eb-0674-4f3b-ac3a-5e47d78e7c91
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237601300 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.1237601300
Directory /workspace/0.chip_sw_sysrst_ctrl_outputs/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3836940359
Short name T41
Test name
Test status
Simulation time 5829116208 ps
CPU time 418.09 seconds
Started Aug 08 08:17:52 PM PDT 24
Finished Aug 08 08:24:50 PM PDT 24
Peak memory 609844 kb
Host smart-3f125c89-6537-41eb-9294-64a3ace3edc8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836940359 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3836940359
Directory /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.678700898
Short name T151
Test name
Test status
Simulation time 7812374376 ps
CPU time 1358.11 seconds
Started Aug 08 08:15:47 PM PDT 24
Finished Aug 08 08:38:26 PM PDT 24
Peak memory 624624 kb
Host smart-5002f8f0-fa76-4c63-970e-8e483ca99536
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=678700898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.678700898
Directory /workspace/0.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/0.chip_sw_uart_smoketest.2075702560
Short name T1011
Test name
Test status
Simulation time 2872934184 ps
CPU time 258.69 seconds
Started Aug 08 08:20:39 PM PDT 24
Finished Aug 08 08:24:58 PM PDT 24
Peak memory 614932 kb
Host smart-cacaf2be-6203-41bb-b26c-4fcb6bce064b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075702560 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_sw_uart_smoketest.2075702560
Directory /workspace/0.chip_sw_uart_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3053585962
Short name T1037
Test name
Test status
Simulation time 4673876112 ps
CPU time 605.27 seconds
Started Aug 08 08:16:35 PM PDT 24
Finished Aug 08 08:26:41 PM PDT 24
Peak memory 624132 kb
Host smart-e8912c27-e160-45f0-a95e-fecc82380054
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053585962 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.3053585962
Directory /workspace/0.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3022901034
Short name T1036
Test name
Test status
Simulation time 4496646768 ps
CPU time 644.05 seconds
Started Aug 08 08:15:28 PM PDT 24
Finished Aug 08 08:26:13 PM PDT 24
Peak memory 624164 kb
Host smart-894fd862-58d8-4a85-9f1b-da2f1f3cf047
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022901034 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.3022901034
Directory /workspace/0.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1100283481
Short name T77
Test name
Test status
Simulation time 3004548178 ps
CPU time 266.62 seconds
Started Aug 08 08:22:02 PM PDT 24
Finished Aug 08 08:26:29 PM PDT 24
Peak memory 609852 kb
Host smart-d44bb1c3-3ad7-4c29-bfa7-c80afdfae912
User root
Command /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100283481
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.1100283481
Directory /workspace/0.chip_sw_usb_ast_clk_calib/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_dpi.2611770226
Short name T1166
Test name
Test status
Simulation time 11870187378 ps
CPU time 2771.91 seconds
Started Aug 08 08:15:37 PM PDT 24
Finished Aug 08 09:01:50 PM PDT 24
Peak memory 610172 kb
Host smart-2355167c-a706-4bce-801d-ac019a6a3a40
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2611770226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.2611770226
Directory /workspace/0.chip_sw_usbdev_dpi/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1472080371
Short name T21
Test name
Test status
Simulation time 31361590900 ps
CPU time 7592.1 seconds
Started Aug 08 08:16:08 PM PDT 24
Finished Aug 08 10:22:42 PM PDT 24
Peak memory 610096 kb
Host smart-8b8436e4-1e2d-4c2b-a0d9-2e9613a59241
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=1472080371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.1472080371
Directory /workspace/0.chip_sw_usbdev_pincfg/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_pullup.1520996713
Short name T79
Test name
Test status
Simulation time 3254988584 ps
CPU time 238.23 seconds
Started Aug 08 08:14:33 PM PDT 24
Finished Aug 08 08:18:31 PM PDT 24
Peak memory 609728 kb
Host smart-9a6d0e4a-a7f3-4bff-b6b4-d473e77a1088
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520996713
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.1520996713
Directory /workspace/0.chip_sw_usbdev_pullup/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_setuprx.929787293
Short name T25
Test name
Test status
Simulation time 3951981730 ps
CPU time 523.35 seconds
Started Aug 08 08:17:09 PM PDT 24
Finished Aug 08 08:25:52 PM PDT 24
Peak memory 609728 kb
Host smart-000de7c2-06c5-4f4b-ac8c-b0207b3b4a57
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929787293
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.929787293
Directory /workspace/0.chip_sw_usbdev_setuprx/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_stream.1392267814
Short name T26
Test name
Test status
Simulation time 18360061520 ps
CPU time 4687.07 seconds
Started Aug 08 08:15:32 PM PDT 24
Finished Aug 08 09:33:40 PM PDT 24
Peak memory 610212 kb
Host smart-c58c228a-3972-4d24-a97c-19d518ae28ff
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru
les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1392267814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.1392267814
Directory /workspace/0.chip_sw_usbdev_stream/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_vbus.889238168
Short name T1176
Test name
Test status
Simulation time 2810575440 ps
CPU time 229.38 seconds
Started Aug 08 08:16:44 PM PDT 24
Finished Aug 08 08:20:34 PM PDT 24
Peak memory 609792 kb
Host smart-a1046ca3-8059-4d00-83a3-7032d2e7baba
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889238168 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.889238168
Directory /workspace/0.chip_sw_usbdev_vbus/latest

Test location /workspace/coverage/default/0.chip_tap_straps_dev.2369834311
Short name T1100
Test name
Test status
Simulation time 12257812847 ps
CPU time 1056.77 seconds
Started Aug 08 08:20:00 PM PDT 24
Finished Aug 08 08:37:37 PM PDT 24
Peak memory 620984 kb
Host smart-47cbd0d7-5ffe-4f1c-90f1-2be51b54ee9a
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2369834311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.2369834311
Directory /workspace/0.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/0.chip_tap_straps_prod.104249601
Short name T1196
Test name
Test status
Simulation time 2570937888 ps
CPU time 142.88 seconds
Started Aug 08 08:19:59 PM PDT 24
Finished Aug 08 08:22:22 PM PDT 24
Peak memory 623344 kb
Host smart-8bcc0beb-d490-4f98-b182-049d652cf5e7
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=104249601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.104249601
Directory /workspace/0.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/0.chip_tap_straps_rma.3608681599
Short name T1283
Test name
Test status
Simulation time 3641653023 ps
CPU time 359.87 seconds
Started Aug 08 08:19:11 PM PDT 24
Finished Aug 08 08:25:11 PM PDT 24
Peak memory 631708 kb
Host smart-f0626289-70df-4266-a334-ac47d8503fed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608681599 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.3608681599
Directory /workspace/0.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/0.chip_tap_straps_testunlock0.399033761
Short name T72
Test name
Test status
Simulation time 1809391545 ps
CPU time 133.8 seconds
Started Aug 08 08:19:19 PM PDT 24
Finished Aug 08 08:21:33 PM PDT 24
Peak memory 623764 kb
Host smart-b71ebe83-50f4-48cc-94b1-2f315be68ff2
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399033761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.399033761
Directory /workspace/0.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_dev.2526540413
Short name T1039
Test name
Test status
Simulation time 15898559864 ps
CPU time 4195.31 seconds
Started Aug 08 08:23:57 PM PDT 24
Finished Aug 08 09:33:53 PM PDT 24
Peak memory 610244 kb
Host smart-53b8d433-b445-43d7-8c42-46f39cf0a6a8
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526540413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rom_e2e_asm_init_dev.2526540413
Directory /workspace/0.rom_e2e_asm_init_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_prod.2128108199
Short name T352
Test name
Test status
Simulation time 15369240196 ps
CPU time 5209.71 seconds
Started Aug 08 08:31:24 PM PDT 24
Finished Aug 08 09:58:15 PM PDT 24
Peak memory 610200 kb
Host smart-a7115b87-dff5-4daf-9a80-583a4bd3a5c8
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128108199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_
SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rom_e2e_asm_init_prod.2128108199
Directory /workspace/0.rom_e2e_asm_init_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1954057912
Short name T1327
Test name
Test status
Simulation time 15153981636 ps
CPU time 4856.11 seconds
Started Aug 08 08:23:55 PM PDT 24
Finished Aug 08 09:44:52 PM PDT 24
Peak memory 610216 kb
Host smart-0c2e8e3b-82fc-44f1-a80d-757ed3964629
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954057912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_e2e_asm_init_prod_end.1954057912
Directory /workspace/0.rom_e2e_asm_init_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_rma.2521565887
Short name T888
Test name
Test status
Simulation time 14627510136 ps
CPU time 4112.87 seconds
Started Aug 08 08:24:42 PM PDT 24
Finished Aug 08 09:33:16 PM PDT 24
Peak memory 610020 kb
Host smart-3ed3b8ba-edbe-4c13-92cf-2382b9de7ee0
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521565887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rom_e2e_asm_init_rma.2521565887
Directory /workspace/0.rom_e2e_asm_init_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1119688151
Short name T1070
Test name
Test status
Simulation time 12019561143 ps
CPU time 3139.53 seconds
Started Aug 08 08:24:57 PM PDT 24
Finished Aug 08 09:17:17 PM PDT 24
Peak memory 610540 kb
Host smart-a302d25f-babd-42db-ab62-1dcb6b274fbc
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119688151 -assert nopostproc +UVM_TESTNAME=chip_base_te
st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.rom_e2e_asm_init_test_unlocked0.1119688151
Directory /workspace/0.rom_e2e_asm_init_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1741994080
Short name T1173
Test name
Test status
Simulation time 24031494888 ps
CPU time 7346.91 seconds
Started Aug 08 08:31:35 PM PDT 24
Finished Aug 08 10:34:03 PM PDT 24
Peak memory 610080 kb
Host smart-f5d730a7-6c5b-408b-be63-fd694bee420a
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1741994080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1741994080
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.643753307
Short name T365
Test name
Test status
Simulation time 24467619596 ps
CPU time 6136.7 seconds
Started Aug 08 08:27:06 PM PDT 24
Finished Aug 08 10:09:24 PM PDT 24
Peak memory 609484 kb
Host smart-9f33b678-e60a-4425-8238-f973e1045cc0
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=643753307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.643753307
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1019392340
Short name T1330
Test name
Test status
Simulation time 23718983540 ps
CPU time 6071.03 seconds
Started Aug 08 08:25:10 PM PDT 24
Finished Aug 08 10:06:22 PM PDT 24
Peak memory 610088 kb
Host smart-648d36fe-3607-4620-afee-33f463665f77
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1019392340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1019392340
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3522996701
Short name T363
Test name
Test status
Simulation time 18247363408 ps
CPU time 4906.66 seconds
Started Aug 08 08:25:59 PM PDT 24
Finished Aug 08 09:47:47 PM PDT 24
Peak memory 610028 kb
Host smart-86c5c917-3627-4913-8b05-7359bd0cc6d0
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,
mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3522996701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3522996701
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1307247701
Short name T1054
Test name
Test status
Simulation time 15313864260 ps
CPU time 4391.7 seconds
Started Aug 08 08:30:39 PM PDT 24
Finished Aug 08 09:43:53 PM PDT 24
Peak memory 609996 kb
Host smart-d14c6fc9-834b-4bb1-9512-def4971a9680
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1307247701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1307247701
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2745409112
Short name T1183
Test name
Test status
Simulation time 15068488052 ps
CPU time 5555.27 seconds
Started Aug 08 08:29:35 PM PDT 24
Finished Aug 08 10:02:12 PM PDT 24
Peak memory 609436 kb
Host smart-960641a6-f54a-4937-af83-aec0aa6a2b72
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2745409112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2745409112
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.941926314
Short name T1034
Test name
Test status
Simulation time 15864271930 ps
CPU time 5336.1 seconds
Started Aug 08 08:29:51 PM PDT 24
Finished Aug 08 09:58:48 PM PDT 24
Peak memory 610148 kb
Host smart-902b0bbb-4746-4b65-a88b-31ef258b65e0
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=941926314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.941926314
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.863291425
Short name T1184
Test name
Test status
Simulation time 14855013120 ps
CPU time 4329.54 seconds
Started Aug 08 08:23:45 PM PDT 24
Finished Aug 08 09:35:55 PM PDT 24
Peak memory 609960 kb
Host smart-dced6206-ce1d-46ed-b8fa-ab9c269f996e
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=863291425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.863291425
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2976594770
Short name T1297
Test name
Test status
Simulation time 10837160120 ps
CPU time 3017.7 seconds
Started Aug 08 08:24:28 PM PDT 24
Finished Aug 08 09:14:46 PM PDT 24
Peak memory 610120 kb
Host smart-30f4b9bc-b4e9-4a47-a6d5-4328ba9127c4
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4,
mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2976594770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2976594770
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.478932492
Short name T1218
Test name
Test status
Simulation time 16045414316 ps
CPU time 3970.92 seconds
Started Aug 08 08:25:54 PM PDT 24
Finished Aug 08 09:32:05 PM PDT 24
Peak memory 610252 kb
Host smart-fd1c4a4b-9744-4393-9d2b-a01bd2b6d6ff
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478932492 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.478932492
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3525523589
Short name T1197
Test name
Test status
Simulation time 15290955340 ps
CPU time 3978.31 seconds
Started Aug 08 08:23:06 PM PDT 24
Finished Aug 08 09:29:25 PM PDT 24
Peak memory 610124 kb
Host smart-e9ed3a87-c9fb-43d0-8b30-f711103e3257
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525523589
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3525523589
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3084288732
Short name T396
Test name
Test status
Simulation time 15393104740 ps
CPU time 3656.27 seconds
Started Aug 08 08:23:09 PM PDT 24
Finished Aug 08 09:24:06 PM PDT 24
Peak memory 610208 kb
Host smart-30c6f89a-2491-4b5a-b203-c7f3861b24dc
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308428
8732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3084288732
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1078469596
Short name T1026
Test name
Test status
Simulation time 15082195252 ps
CPU time 3941.18 seconds
Started Aug 08 08:25:04 PM PDT 24
Finished Aug 08 09:30:45 PM PDT 24
Peak memory 610300 kb
Host smart-010c1c65-21ba-43ec-9ed0-b3700e83ae64
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078469596
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1078469596
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3926164650
Short name T963
Test name
Test status
Simulation time 11039718144 ps
CPU time 3095.8 seconds
Started Aug 08 08:25:23 PM PDT 24
Finished Aug 08 09:16:59 PM PDT 24
Peak memory 610248 kb
Host smart-648506ee-3f84-4478-86f4-3db2ab918cc6
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3926164650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3926164650
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.3427659998
Short name T412
Test name
Test status
Simulation time 12083784055 ps
CPU time 1984.29 seconds
Started Aug 08 08:21:00 PM PDT 24
Finished Aug 08 08:54:05 PM PDT 24
Peak memory 624276 kb
Host smart-daed9d75-8c51-4eff-9da6-5d0ec10b5ce4
User root
Command /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34276
59998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.3427659998
Directory /workspace/0.rom_e2e_jtag_debug_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.3387959047
Short name T664
Test name
Test status
Simulation time 10465643495 ps
CPU time 2398.8 seconds
Started Aug 08 08:23:24 PM PDT 24
Finished Aug 08 09:03:24 PM PDT 24
Peak memory 624476 kb
Host smart-bbb0e6dd-a3fd-4930-a0bd-231a4963526c
User root
Command /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33879
59047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.3387959047
Directory /workspace/0.rom_e2e_jtag_debug_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2017536777
Short name T665
Test name
Test status
Simulation time 11070423716 ps
CPU time 2041.97 seconds
Started Aug 08 08:20:58 PM PDT 24
Finished Aug 08 08:55:01 PM PDT 24
Peak memory 624432 kb
Host smart-6846fac5-d6ad-42ce-8d76-02e0b60e3762
User root
Command /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2017536777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.2017536777
Directory /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2371694044
Short name T233
Test name
Test status
Simulation time 24526143116 ps
CPU time 2350.04 seconds
Started Aug 08 08:20:20 PM PDT 24
Finished Aug 08 08:59:31 PM PDT 24
Peak memory 620456 kb
Host smart-14cfc882-dc18-4d47-a294-5731f8f35928
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di
sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2371694044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.2371694044
Directory /workspace/0.rom_e2e_jtag_inject_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.634433723
Short name T234
Test name
Test status
Simulation time 24434198566 ps
CPU time 2716.26 seconds
Started Aug 08 08:21:18 PM PDT 24
Finished Aug 08 09:06:35 PM PDT 24
Peak memory 620416 kb
Host smart-0916cf10-f366-4965-9417-e97a2494219f
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di
sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=634433723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.634433723
Directory /workspace/0.rom_e2e_jtag_inject_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.268087255
Short name T232
Test name
Test status
Simulation time 31050298831 ps
CPU time 2730.21 seconds
Started Aug 08 08:21:09 PM PDT 24
Finished Aug 08 09:06:40 PM PDT 24
Peak memory 620960 kb
Host smart-e59300bc-298b-44fe-a490-a3ff3451c586
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock
ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268087255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_i
nject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_
test_unlocked0.268087255
Directory /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2470503269
Short name T984
Test name
Test status
Simulation time 14742130744 ps
CPU time 4440.96 seconds
Started Aug 08 08:25:25 PM PDT 24
Finished Aug 08 09:39:26 PM PDT 24
Peak memory 610124 kb
Host smart-0e386a04-e439-4ece-902f-d90d423d2600
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid
_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470503269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip
_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in
it_rom_ext_invalid_meas.2470503269
Directory /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.4257331131
Short name T1266
Test name
Test status
Simulation time 15266718840 ps
CPU time 3751.74 seconds
Started Aug 08 08:25:02 PM PDT 24
Finished Aug 08 09:27:34 PM PDT 24
Peak memory 610152 kb
Host smart-7ef266da-9742-45e7-b11f-0bcbe359f73c
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:
new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257331131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.4257331131
Directory /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3653268138
Short name T964
Test name
Test status
Simulation time 14767121070 ps
CPU time 4477.14 seconds
Started Aug 08 08:26:33 PM PDT 24
Finished Aug 08 09:41:11 PM PDT 24
Peak memory 610028 kb
Host smart-d1d7119c-80e5-4466-a4e1-1d207c2a2ec8
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas
:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653268138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext
_no_meas.3653268138
Directory /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location /workspace/coverage/default/0.rom_e2e_self_hash.1025059976
Short name T1145
Test name
Test status
Simulation time 26744477960 ps
CPU time 7279.76 seconds
Started Aug 08 08:26:38 PM PDT 24
Finished Aug 08 10:27:59 PM PDT 24
Peak memory 610036 kb
Host smart-85d4f89c-78c2-4f36-ae0b-336f6382c09a
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r
ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025059976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.1025059976
Directory /workspace/0.rom_e2e_self_hash/latest

Test location /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1483075938
Short name T947
Test name
Test status
Simulation time 15057975808 ps
CPU time 3688.32 seconds
Started Aug 08 08:25:05 PM PDT 24
Finished Aug 08 09:26:34 PM PDT 24
Peak memory 611268 kb
Host smart-2a8bb644-863c-48ce-a90a-eab52dcacf20
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne
w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483075938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu
tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_
shutdown_exception_c.1483075938
Directory /workspace/0.rom_e2e_shutdown_exception_c/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3144249287
Short name T1090
Test name
Test status
Simulation time 22887678880 ps
CPU time 5893.99 seconds
Started Aug 08 08:23:37 PM PDT 24
Finished Aug 08 10:01:51 PM PDT 24
Peak memory 610144 kb
Host smart-0077bc59-943a-4acd-8c3a-705f0798dde8
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev
:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3144249287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b
ad_dev.3144249287
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.421661517
Short name T47
Test name
Test status
Simulation time 23458025880 ps
CPU time 6320.49 seconds
Started Aug 08 08:29:17 PM PDT 24
Finished Aug 08 10:14:38 PM PDT 24
Peak memory 611084 kb
Host smart-5e2d0c5f-4643-449e-b291-92c6e9bc2869
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p
rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=421661517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b
_bad_prod.421661517
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2085206761
Short name T900
Test name
Test status
Simulation time 23718325108 ps
CPU time 5765.39 seconds
Started Aug 08 08:27:34 PM PDT 24
Finished Aug 08 10:03:40 PM PDT 24
Peak memory 610260 kb
Host smart-6eefff9d-4159-4d3b-9c1c-ea5559931dba
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p
rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=2085206761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_
bad_b_bad_prod_end.2085206761
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.908740814
Short name T1340
Test name
Test status
Simulation time 21827178332 ps
CPU time 5724.96 seconds
Started Aug 08 08:26:22 PM PDT 24
Finished Aug 08 10:01:48 PM PDT 24
Peak memory 610188 kb
Host smart-3d2b7fea-402d-4b8d-adb7-d41ed7fcce36
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r
ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=908740814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_
bad_rma.908740814
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.4233697813
Short name T871
Test name
Test status
Simulation time 17946054757 ps
CPU time 5150.85 seconds
Started Aug 08 08:24:57 PM PDT 24
Finished Aug 08 09:50:48 PM PDT 24
Peak memory 610204 kb
Host smart-f9816d7f-7e2e-481a-a89e-20f1dd444bf5
User root
Command /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t
est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4233697813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b
_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw
ays_a_bad_b_bad_test_unlocked0.4233697813
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.499767218
Short name T46
Test name
Test status
Simulation time 14677995049 ps
CPU time 3431.03 seconds
Started Aug 08 08:24:49 PM PDT 24
Finished Aug 08 09:22:00 PM PDT 24
Peak memory 611304 kb
Host smart-fe7e762f-0cfa-4f87-ab97-de3f20bf926b
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499767218 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.499767218
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3039425551
Short name T895
Test name
Test status
Simulation time 14903773525 ps
CPU time 4668.16 seconds
Started Aug 08 08:31:29 PM PDT 24
Finished Aug 08 09:49:17 PM PDT 24
Peak memory 610080 kb
Host smart-f84fbaa9-56f5-4fa9-9c59-67de7a49e4f1
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039425551 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3039425551
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2429378257
Short name T996
Test name
Test status
Simulation time 14493697048 ps
CPU time 3489.62 seconds
Started Aug 08 08:23:18 PM PDT 24
Finished Aug 08 09:21:28 PM PDT 24
Peak memory 610088 kb
Host smart-9019a910-e02b-4de8-8172-896257bce8de
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429378257 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2429378257
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1460544561
Short name T1198
Test name
Test status
Simulation time 14444602678 ps
CPU time 3717.2 seconds
Started Aug 08 08:26:06 PM PDT 24
Finished Aug 08 09:28:05 PM PDT 24
Peak memory 611308 kb
Host smart-1915758f-b7af-43e4-8200-579a000d06e4
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460544561 -assert nopostproc +UVM_TESTNAME=chip_base
_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1460544561
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1471162502
Short name T1087
Test name
Test status
Simulation time 11334437971 ps
CPU time 2958.8 seconds
Started Aug 08 08:31:28 PM PDT 24
Finished Aug 08 09:20:47 PM PDT 24
Peak memory 610632 kb
Host smart-f38eb848-03c5-4467-b654-d75e46ca58bc
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471162502 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1471162502
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.4115665067
Short name T1203
Test name
Test status
Simulation time 15330550262 ps
CPU time 4672.73 seconds
Started Aug 08 08:26:26 PM PDT 24
Finished Aug 08 09:44:19 PM PDT 24
Peak memory 610204 kb
Host smart-2b2921a6-b19b-4e6f-9516-c43e26822b5e
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115665067 -assert nopostproc +UVM_TESTNAME=chip_base_
test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.4115665067
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2122083929
Short name T1077
Test name
Test status
Simulation time 14657455275 ps
CPU time 3570.82 seconds
Started Aug 08 08:27:29 PM PDT 24
Finished Aug 08 09:27:01 PM PDT 24
Peak memory 610300 kb
Host smart-4e2e6379-b0fc-482c-8011-91cb6cc96929
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122083929 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2122083929
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.237112280
Short name T1024
Test name
Test status
Simulation time 14794454055 ps
CPU time 4050.29 seconds
Started Aug 08 08:26:28 PM PDT 24
Finished Aug 08 09:33:59 PM PDT 24
Peak memory 610408 kb
Host smart-51428f3e-6542-4b39-ab7f-2e2f54b449b7
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237112280 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.237112280
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.912153712
Short name T1216
Test name
Test status
Simulation time 13868906972 ps
CPU time 3616.68 seconds
Started Aug 08 08:23:07 PM PDT 24
Finished Aug 08 09:23:25 PM PDT 24
Peak memory 610296 kb
Host smart-6a24e411-4aa1-4931-87e5-eea87fcf446d
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912153712 -assert nopostproc +UVM_TESTNAME=chip_base_
test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.912153712
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.255824194
Short name T913
Test name
Test status
Simulation time 10710791810 ps
CPU time 3176.77 seconds
Started Aug 08 08:27:11 PM PDT 24
Finished Aug 08 09:20:08 PM PDT 24
Peak memory 610408 kb
Host smart-581304ec-5a91-49df-abf0-4645b512ff7f
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255824194 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.255824194
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_smoke.2038392510
Short name T1342
Test name
Test status
Simulation time 15127579304 ps
CPU time 3914.24 seconds
Started Aug 08 08:23:03 PM PDT 24
Finished Aug 08 09:28:18 PM PDT 24
Peak memory 611044 kb
Host smart-fd87a480-da05-4960-86a1-98265a106db0
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img
_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to
p/hw/dv/tools/sim.tcl +ntb_random_seed=2038392510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.2038392510
Directory /workspace/0.rom_e2e_smoke/latest

Test location /workspace/coverage/default/0.rom_e2e_static_critical.3088345421
Short name T998
Test name
Test status
Simulation time 17180502374 ps
CPU time 4967.39 seconds
Started Aug 08 08:26:31 PM PDT 24
Finished Aug 08 09:49:19 PM PDT 24
Peak memory 609940 kb
Host smart-489819e7-396c-46a1-9283-24f22c722bef
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul
es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088345421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.3088345421
Directory /workspace/0.rom_e2e_static_critical/latest

Test location /workspace/coverage/default/0.rom_keymgr_functest.3166448422
Short name T1017
Test name
Test status
Simulation time 4281328180 ps
CPU time 477.82 seconds
Started Aug 08 08:22:37 PM PDT 24
Finished Aug 08 08:30:35 PM PDT 24
Peak memory 610304 kb
Host smart-fffd39d1-3f9d-430b-8093-3e1059c29a09
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166448422 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.3166448422
Directory /workspace/0.rom_keymgr_functest/latest

Test location /workspace/coverage/default/0.rom_raw_unlock.23805743
Short name T660
Test name
Test status
Simulation time 4511099291 ps
CPU time 253.44 seconds
Started Aug 08 08:21:34 PM PDT 24
Finished Aug 08 08:25:48 PM PDT 24
Peak memory 619784 kb
Host smart-be5884d9-4e23-44dd-a491-553a80b3e883
User root
Command /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE
xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=23805743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.23805743
Directory /workspace/0.rom_raw_unlock/latest

Test location /workspace/coverage/default/0.rom_volatile_raw_unlock.1263116185
Short name T1246
Test name
Test status
Simulation time 2230639720 ps
CPU time 100.6 seconds
Started Aug 08 08:19:42 PM PDT 24
Finished Aug 08 08:21:22 PM PDT 24
Peak memory 616988 kb
Host smart-68143fe6-acd1-41a8-8f7e-ca62812dc796
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1
+sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263116185 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.1263116185
Directory /workspace/0.rom_volatile_raw_unlock/latest

Test location /workspace/coverage/default/1.chip_jtag_mem_access.2565621214
Short name T86
Test name
Test status
Simulation time 13546604440 ps
CPU time 1721.23 seconds
Started Aug 08 08:24:21 PM PDT 24
Finished Aug 08 08:53:02 PM PDT 24
Peak memory 607736 kb
Host smart-eb9be0bb-23a1-48fb-8718-f64d792c9f75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565621214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_
mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.2
565621214
Directory /workspace/1.chip_jtag_mem_access/latest

Test location /workspace/coverage/default/1.chip_plic_all_irqs_10.3033024360
Short name T158
Test name
Test status
Simulation time 4207896938 ps
CPU time 815.52 seconds
Started Aug 08 08:31:41 PM PDT 24
Finished Aug 08 08:45:17 PM PDT 24
Peak memory 608464 kb
Host smart-60859cdb-a343-4906-9113-e8ae5b394ded
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033024360 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.chip_plic_all_irqs_10.3033024360
Directory /workspace/1.chip_plic_all_irqs_10/latest

Test location /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2287726889
Short name T54
Test name
Test status
Simulation time 3913852424 ps
CPU time 588.48 seconds
Started Aug 08 08:38:30 PM PDT 24
Finished Aug 08 08:48:19 PM PDT 24
Peak memory 619944 kb
Host smart-28bc1260-aa62-4142-b46f-97b5f8bd5321
User root
Command /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2
287726889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.2287726889
Directory /workspace/1.chip_rv_dm_ndm_reset_req/latest

Test location /workspace/coverage/default/1.chip_sival_flash_info_access.1537074063
Short name T1085
Test name
Test status
Simulation time 2805778360 ps
CPU time 261.47 seconds
Started Aug 08 08:23:44 PM PDT 24
Finished Aug 08 08:28:06 PM PDT 24
Peak memory 609916 kb
Host smart-2ce092d7-d5c5-40ab-a7a7-404bba61c2f2
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=1537074063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.1537074063
Directory /workspace/1.chip_sival_flash_info_access/latest

Test location /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1473281995
Short name T1084
Test name
Test status
Simulation time 17871035936 ps
CPU time 345.19 seconds
Started Aug 08 08:29:09 PM PDT 24
Finished Aug 08 08:34:54 PM PDT 24
Peak memory 619384 kb
Host smart-02ae79d9-90ea-41a8-aa10-aa20ae7c57f6
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1473281995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1473281995
Directory /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_aes_enc.781773100
Short name T1284
Test name
Test status
Simulation time 3069491474 ps
CPU time 282.88 seconds
Started Aug 08 08:27:04 PM PDT 24
Finished Aug 08 08:31:47 PM PDT 24
Peak memory 609628 kb
Host smart-f576c810-10d0-49b0-8e5a-0702c805ce2e
User root
Command /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781773100 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.781773100
Directory /workspace/1.chip_sw_aes_enc/latest

Test location /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.4277625516
Short name T111
Test name
Test status
Simulation time 2618895970 ps
CPU time 255.03 seconds
Started Aug 08 08:27:35 PM PDT 24
Finished Aug 08 08:31:50 PM PDT 24
Peak memory 608392 kb
Host smart-6cb58e42-181b-43e6-a02c-2b2c9e6d9812
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277
625516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.4277625516
Directory /workspace/1.chip_sw_aes_enc_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2759454608
Short name T1003
Test name
Test status
Simulation time 2559443778 ps
CPU time 244.78 seconds
Started Aug 08 08:32:40 PM PDT 24
Finished Aug 08 08:36:45 PM PDT 24
Peak memory 608656 kb
Host smart-f8a84525-5407-403b-952c-9949f4dfe9d3
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2759454608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.2759454608
Directory /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_aes_entropy.2514915825
Short name T107
Test name
Test status
Simulation time 2966966966 ps
CPU time 339.86 seconds
Started Aug 08 08:28:58 PM PDT 24
Finished Aug 08 08:34:38 PM PDT 24
Peak memory 609492 kb
Host smart-560eb509-9fbd-48fe-b0d6-8cd9ca097af7
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514915825 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.2514915825
Directory /workspace/1.chip_sw_aes_entropy/latest

Test location /workspace/coverage/default/1.chip_sw_aes_idle.3908044266
Short name T377
Test name
Test status
Simulation time 2762083422 ps
CPU time 233.62 seconds
Started Aug 08 08:29:31 PM PDT 24
Finished Aug 08 08:33:25 PM PDT 24
Peak memory 609400 kb
Host smart-d6c11614-bb3a-40e6-8e67-9065d80ffa9b
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908044266 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.3908044266
Directory /workspace/1.chip_sw_aes_idle/latest

Test location /workspace/coverage/default/1.chip_sw_aes_masking_off.1831652282
Short name T981
Test name
Test status
Simulation time 3261438095 ps
CPU time 234 seconds
Started Aug 08 08:26:43 PM PDT 24
Finished Aug 08 08:30:37 PM PDT 24
Peak memory 610424 kb
Host smart-a7595425-ead4-4f26-b2b9-63b58a6b271d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831652282 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.1831652282
Directory /workspace/1.chip_sw_aes_masking_off/latest

Test location /workspace/coverage/default/1.chip_sw_aes_smoketest.1163517374
Short name T1025
Test name
Test status
Simulation time 2764653948 ps
CPU time 293.7 seconds
Started Aug 08 08:33:39 PM PDT 24
Finished Aug 08 08:38:33 PM PDT 24
Peak memory 609684 kb
Host smart-937c9200-9d75-432d-ac2f-0a897ceaebf2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163517374 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_aes_smoketest.1163517374
Directory /workspace/1.chip_sw_aes_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_entropy.2330391635
Short name T92
Test name
Test status
Simulation time 3060012397 ps
CPU time 293.95 seconds
Started Aug 08 08:27:43 PM PDT 24
Finished Aug 08 08:32:37 PM PDT 24
Peak memory 609400 kb
Host smart-f3a02739-8c89-485d-b53f-859dcdd240c3
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2330391635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.2330391635
Directory /workspace/1.chip_sw_alert_handler_entropy/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_escalation.4210804207
Short name T1307
Test name
Test status
Simulation time 5131293092 ps
CPU time 533.13 seconds
Started Aug 08 08:27:10 PM PDT 24
Finished Aug 08 08:36:03 PM PDT 24
Peak memory 619684 kb
Host smart-8d508e74-a0ea-411e-9e49-072a9ee2fef8
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=4210804207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.4210804207
Directory /workspace/1.chip_sw_alert_handler_escalation/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.997909472
Short name T414
Test name
Test status
Simulation time 5357480356 ps
CPU time 1188.51 seconds
Started Aug 08 08:28:41 PM PDT 24
Finished Aug 08 08:48:29 PM PDT 24
Peak memory 610212 kb
Host smart-ae2e3fec-a5d2-4c08-bcc4-91ce039ca4f5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=997909472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.997909472
Directory /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2928743763
Short name T1294
Test name
Test status
Simulation time 8207666012 ps
CPU time 1712.22 seconds
Started Aug 08 08:29:21 PM PDT 24
Finished Aug 08 08:57:53 PM PDT 24
Peak memory 610144 kb
Host smart-872163e0-0d09-43af-8d4d-75cf3cb2e2b7
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2928743763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg
le.2928743763
Directory /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1094490004
Short name T904
Test name
Test status
Simulation time 7952885000 ps
CPU time 1561.62 seconds
Started Aug 08 08:30:31 PM PDT 24
Finished Aug 08 08:56:33 PM PDT 24
Peak memory 609448 kb
Host smart-0d21635a-9d32-4cbe-9598-17050ca84eb8
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=1094490004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.1094490004
Directory /workspace/1.chip_sw_alert_handler_ping_ok/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.930028083
Short name T722
Test name
Test status
Simulation time 3719785408 ps
CPU time 320.69 seconds
Started Aug 08 08:29:15 PM PDT 24
Finished Aug 08 08:34:36 PM PDT 24
Peak memory 609748 kb
Host smart-5ed75697-829c-4a81-95ba-83aa9b57abaa
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=930028083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.930028083
Directory /workspace/1.chip_sw_alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.227782087
Short name T160
Test name
Test status
Simulation time 255689649776 ps
CPU time 11747.4 seconds
Started Aug 08 08:29:49 PM PDT 24
Finished Aug 08 11:45:39 PM PDT 24
Peak memory 610552 kb
Host smart-64274974-62a6-4eb9-8d9b-43683ffed2af
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227782087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.227782087
Directory /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3380907675
Short name T890
Test name
Test status
Simulation time 7625541914 ps
CPU time 293.93 seconds
Started Aug 08 08:25:13 PM PDT 24
Finished Aug 08 08:30:07 PM PDT 24
Peak memory 609192 kb
Host smart-2740473a-67a5-48d6-ab2f-1cd5c35197b8
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3380907675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3380907675
Directory /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1651868552
Short name T869
Test name
Test status
Simulation time 2929895512 ps
CPU time 334.37 seconds
Started Aug 08 08:33:37 PM PDT 24
Finished Aug 08 08:39:12 PM PDT 24
Peak memory 609376 kb
Host smart-f970fe23-ee15-4cd9-b3e5-b9d2e2656f69
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651868552 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_aon_timer_smoketest.1651868552
Directory /workspace/1.chip_sw_aon_timer_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3762576768
Short name T1295
Test name
Test status
Simulation time 10005304088 ps
CPU time 907.68 seconds
Started Aug 08 08:26:13 PM PDT 24
Finished Aug 08 08:41:21 PM PDT 24
Peak memory 610524 kb
Host smart-31e14f17-9fe0-401e-ac13-7b34b8ed0eec
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3762576768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.3762576768
Directory /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2080514145
Short name T882
Test name
Test status
Simulation time 4428578600 ps
CPU time 576.67 seconds
Started Aug 08 08:28:04 PM PDT 24
Finished Aug 08 08:37:41 PM PDT 24
Peak memory 610340 kb
Host smart-51f24253-328d-4627-97a8-5f8f51101834
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2080514145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.2080514145
Directory /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location /workspace/coverage/default/1.chip_sw_ast_clk_outputs.3590217771
Short name T929
Test name
Test status
Simulation time 8507827724 ps
CPU time 1007.2 seconds
Started Aug 08 08:38:59 PM PDT 24
Finished Aug 08 08:55:46 PM PDT 24
Peak memory 616292 kb
Host smart-5eb60c6e-8af7-426d-9788-33c598465f2e
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590217771 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.3590217771
Directory /workspace/1.chip_sw_ast_clk_outputs/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.236757057
Short name T1207
Test name
Test status
Simulation time 4230335612 ps
CPU time 904.77 seconds
Started Aug 08 08:31:25 PM PDT 24
Finished Aug 08 08:46:30 PM PDT 24
Peak memory 612076 kb
Host smart-9e024ea7-679c-4f59-ace8-64cc69517469
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236757057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl
kmgr_external_clk_src_for_sw_fast_dev.236757057
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3762937757
Short name T1257
Test name
Test status
Simulation time 3803451590 ps
CPU time 771.33 seconds
Started Aug 08 08:31:57 PM PDT 24
Finished Aug 08 08:44:49 PM PDT 24
Peak memory 612124 kb
Host smart-b3b09a80-372e-4d76-926a-99413b077caa
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762937757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_rma.3762937757
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.534401884
Short name T402
Test name
Test status
Simulation time 4363774886 ps
CPU time 644.76 seconds
Started Aug 08 08:31:19 PM PDT 24
Finished Aug 08 08:42:04 PM PDT 24
Peak memory 612220 kb
Host smart-c53b766f-937b-41c0-a934-49b84ab2c6c1
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534401884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM
_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.534401884
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3646690071
Short name T1177
Test name
Test status
Simulation time 5111912074 ps
CPU time 726.36 seconds
Started Aug 08 08:31:32 PM PDT 24
Finished Aug 08 08:43:39 PM PDT 24
Peak memory 612156 kb
Host smart-658285de-32df-4fbd-ba0e-66c62189dd97
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646690071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_rma.3646690071
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.816737683
Short name T993
Test name
Test status
Simulation time 5364926600 ps
CPU time 625.4 seconds
Started Aug 08 08:30:27 PM PDT 24
Finished Aug 08 08:40:52 PM PDT 24
Peak memory 612204 kb
Host smart-702b8056-6069-4133-ba7a-7f7ee2702c00
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816737683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM
_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.816737683
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3494993203
Short name T1269
Test name
Test status
Simulation time 2245042454 ps
CPU time 279.96 seconds
Started Aug 08 08:31:59 PM PDT 24
Finished Aug 08 08:36:41 PM PDT 24
Peak memory 609680 kb
Host smart-512fef16-2dd2-4f2c-9750-f0cef8d36b05
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494993203 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_clkmgr_jitter.3494993203
Directory /workspace/1.chip_sw_clkmgr_jitter/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1073490214
Short name T409
Test name
Test status
Simulation time 4205136398 ps
CPU time 565.12 seconds
Started Aug 08 08:36:39 PM PDT 24
Finished Aug 08 08:46:04 PM PDT 24
Peak memory 609500 kb
Host smart-6840485a-638a-441b-8ad7-1a3669c0ec68
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073490214 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.1073490214
Directory /workspace/1.chip_sw_clkmgr_jitter_frequency/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3709368033
Short name T1233
Test name
Test status
Simulation time 2605309816 ps
CPU time 184.84 seconds
Started Aug 08 08:33:23 PM PDT 24
Finished Aug 08 08:36:28 PM PDT 24
Peak memory 609636 kb
Host smart-dc330ace-cd37-47e6-984c-51e5e7a5ff08
User root
Command /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709368033 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.3709368033
Directory /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2521895127
Short name T393
Test name
Test status
Simulation time 4560179956 ps
CPU time 504 seconds
Started Aug 08 08:30:23 PM PDT 24
Finished Aug 08 08:38:47 PM PDT 24
Peak memory 609416 kb
Host smart-218b34ea-2170-47a4-86f9-5d28ed032a11
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521895127 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.2521895127
Directory /workspace/1.chip_sw_clkmgr_off_aes_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2386441232
Short name T1290
Test name
Test status
Simulation time 4766934070 ps
CPU time 588.4 seconds
Started Aug 08 08:30:32 PM PDT 24
Finished Aug 08 08:40:21 PM PDT 24
Peak memory 610188 kb
Host smart-88de9ba1-800d-41a6-a1f5-10608b72b3e7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386441232 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.2386441232
Directory /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.343462407
Short name T968
Test name
Test status
Simulation time 5332115816 ps
CPU time 677.55 seconds
Started Aug 08 08:32:13 PM PDT 24
Finished Aug 08 08:43:31 PM PDT 24
Peak memory 610128 kb
Host smart-1365799f-194d-45c8-aee5-feda0560272c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343462407 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.343462407
Directory /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2132726674
Short name T1083
Test name
Test status
Simulation time 5870337832 ps
CPU time 548.88 seconds
Started Aug 08 08:30:47 PM PDT 24
Finished Aug 08 08:39:56 PM PDT 24
Peak memory 610324 kb
Host smart-b0eee814-656e-47aa-878e-e3268cd1eebb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132726674 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.2132726674
Directory /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2074746825
Short name T356
Test name
Test status
Simulation time 10025997296 ps
CPU time 1423.97 seconds
Started Aug 08 08:31:01 PM PDT 24
Finished Aug 08 08:54:46 PM PDT 24
Peak memory 610448 kb
Host smart-03488991-1699-4b55-ad70-baed49945b24
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074746825
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.2074746825
Directory /workspace/1.chip_sw_clkmgr_off_peri/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.446459722
Short name T987
Test name
Test status
Simulation time 3249448026 ps
CPU time 432.64 seconds
Started Aug 08 08:30:39 PM PDT 24
Finished Aug 08 08:37:52 PM PDT 24
Peak memory 609736 kb
Host smart-dda559c7-f6bd-4daf-bcb1-b80ab38755df
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446459722 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.446459722
Directory /workspace/1.chip_sw_clkmgr_reset_frequency/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1713247310
Short name T854
Test name
Test status
Simulation time 4565427766 ps
CPU time 619.12 seconds
Started Aug 08 08:31:00 PM PDT 24
Finished Aug 08 08:41:19 PM PDT 24
Peak memory 610204 kb
Host smart-9bacb73f-c383-44a4-93c3-c19ac606b520
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713247310 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.1713247310
Directory /workspace/1.chip_sw_clkmgr_sleep_frequency/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.792795732
Short name T932
Test name
Test status
Simulation time 3296844356 ps
CPU time 216.1 seconds
Started Aug 08 08:33:07 PM PDT 24
Finished Aug 08 08:36:44 PM PDT 24
Peak memory 609612 kb
Host smart-60ea59f2-431c-457a-aa93-8a7ddd6e1827
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792795732 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.chip_sw_clkmgr_smoketest.792795732
Directory /workspace/1.chip_sw_clkmgr_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2506923117
Short name T937
Test name
Test status
Simulation time 12085990656 ps
CPU time 3414.58 seconds
Started Aug 08 08:29:23 PM PDT 24
Finished Aug 08 09:26:18 PM PDT 24
Peak memory 609620 kb
Host smart-1ff1116b-5230-4d7f-bdd5-78df22fbe1bd
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506923117 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.2506923117
Directory /workspace/1.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2108971447
Short name T185
Test name
Test status
Simulation time 4118758984 ps
CPU time 427.2 seconds
Started Aug 08 08:28:58 PM PDT 24
Finished Aug 08 08:36:06 PM PDT 24
Peak memory 610308 kb
Host smart-fe2fe937-869b-45f9-b521-6f0738c0d67c
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21089
71447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.2108971447
Directory /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_kat_test.619623896
Short name T899
Test name
Test status
Simulation time 3070662068 ps
CPU time 314.22 seconds
Started Aug 08 08:28:18 PM PDT 24
Finished Aug 08 08:33:33 PM PDT 24
Peak memory 609432 kb
Host smart-67fd601d-b1b3-4766-9f59-283c0a34dd73
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619623896 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.619623896
Directory /workspace/1.chip_sw_csrng_kat_test/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1431697692
Short name T1185
Test name
Test status
Simulation time 7735890116 ps
CPU time 840.79 seconds
Started Aug 08 08:27:54 PM PDT 24
Finished Aug 08 08:41:55 PM PDT 24
Peak memory 610728 kb
Host smart-8c2bf6f5-b8c1-4d77-addf-fb40de5948ac
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima
ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431697692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_
lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr
ng_lc_hw_debug_en_test.1431697692
Directory /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_smoketest.680465856
Short name T973
Test name
Test status
Simulation time 2080486296 ps
CPU time 274.14 seconds
Started Aug 08 08:35:09 PM PDT 24
Finished Aug 08 08:39:43 PM PDT 24
Peak memory 609620 kb
Host smart-d530e851-1be9-4d1d-b434-39e03223eaf2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680465856 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_csrng_smoketest.680465856
Directory /workspace/1.chip_sw_csrng_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_data_integrity_escalation.1266997158
Short name T1301
Test name
Test status
Simulation time 4910271120 ps
CPU time 928.74 seconds
Started Aug 08 08:22:00 PM PDT 24
Finished Aug 08 08:37:29 PM PDT 24
Peak memory 611112 kb
Host smart-e3b73add-3a04-4cc0-b924-c4ac0228ec73
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1266997158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.1266997158
Directory /workspace/1.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/1.chip_sw_edn_auto_mode.2325550260
Short name T419
Test name
Test status
Simulation time 4990701040 ps
CPU time 894.5 seconds
Started Aug 08 08:28:46 PM PDT 24
Finished Aug 08 08:43:41 PM PDT 24
Peak memory 610312 kb
Host smart-8150cc33-3a00-4c99-82fe-f0c3ac246317
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325550260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_
auto_mode.2325550260
Directory /workspace/1.chip_sw_edn_auto_mode/latest

Test location /workspace/coverage/default/1.chip_sw_edn_boot_mode.539004357
Short name T361
Test name
Test status
Simulation time 3227573992 ps
CPU time 595.37 seconds
Started Aug 08 08:28:13 PM PDT 24
Finished Aug 08 08:38:09 PM PDT 24
Peak memory 609996 kb
Host smart-a0d90945-c216-4540-958d-7f8e1a8171b3
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539004357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_b
oot_mode.539004357
Directory /workspace/1.chip_sw_edn_boot_mode/latest

Test location /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.753668309
Short name T415
Test name
Test status
Simulation time 6624559896 ps
CPU time 974.11 seconds
Started Aug 08 08:28:58 PM PDT 24
Finished Aug 08 08:45:12 PM PDT 24
Peak memory 609564 kb
Host smart-c9147cdd-5eee-4515-894a-e3e9f8a28093
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed
n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=753668309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.753668309
Directory /workspace/1.chip_sw_edn_entropy_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1459947113
Short name T417
Test name
Test status
Simulation time 6891458984 ps
CPU time 878.47 seconds
Started Aug 08 08:28:49 PM PDT 24
Finished Aug 08 08:43:28 PM PDT 24
Peak memory 609656 kb
Host smart-b731342a-1533-4cdd-b9dd-db65e6066b8b
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e
ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459947113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.1459947113
Directory /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest

Test location /workspace/coverage/default/1.chip_sw_edn_kat.129447233
Short name T1043
Test name
Test status
Simulation time 3246445480 ps
CPU time 646.61 seconds
Started Aug 08 08:28:27 PM PDT 24
Finished Aug 08 08:39:14 PM PDT 24
Peak memory 615248 kb
Host smart-6a9a46e9-2d85-4b7a-a98a-853ef9e3d740
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3
+accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129447233 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_edn_kat.129447233
Directory /workspace/1.chip_sw_edn_kat/latest

Test location /workspace/coverage/default/1.chip_sw_edn_sw_mode.4259044837
Short name T1101
Test name
Test status
Simulation time 11225521840 ps
CPU time 2981.13 seconds
Started Aug 08 08:28:32 PM PDT 24
Finished Aug 08 09:18:14 PM PDT 24
Peak memory 609992 kb
Host smart-5204ed26-bef7-4eb7-9b77-ceb40a55fe4f
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259044837 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.4259044837
Directory /workspace/1.chip_sw_edn_sw_mode/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.4272047602
Short name T260
Test name
Test status
Simulation time 3194178520 ps
CPU time 342.65 seconds
Started Aug 08 08:28:21 PM PDT 24
Finished Aug 08 08:34:04 PM PDT 24
Peak memory 609752 kb
Host smart-437dcd34-03c7-479e-8715-158713ba3b53
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42
72047602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.4272047602
Directory /workspace/1.chip_sw_entropy_src_ast_rng_req/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1207107631
Short name T1147
Test name
Test status
Simulation time 3187160412 ps
CPU time 191.56 seconds
Started Aug 08 08:27:48 PM PDT 24
Finished Aug 08 08:30:59 PM PDT 24
Peak memory 608452 kb
Host smart-e1f78311-ba8e-4d24-9628-6651be6338ca
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207107631
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.1207107631
Directory /workspace/1.chip_sw_entropy_src_kat_test/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1142033088
Short name T1022
Test name
Test status
Simulation time 3785718478 ps
CPU time 457.82 seconds
Started Aug 08 08:34:08 PM PDT 24
Finished Aug 08 08:41:46 PM PDT 24
Peak memory 609728 kb
Host smart-b1b22dfa-b278-45ea-b5f5-c451e6b4e535
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1142033088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.1142033088
Directory /workspace/1.chip_sw_entropy_src_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_example_concurrency.490348698
Short name T1131
Test name
Test status
Simulation time 2183475534 ps
CPU time 225.4 seconds
Started Aug 08 08:22:18 PM PDT 24
Finished Aug 08 08:26:04 PM PDT 24
Peak memory 609392 kb
Host smart-700ecbd4-04e9-4fa7-a255-3715f61cb723
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490348698 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_example_concurrency.490348698
Directory /workspace/1.chip_sw_example_concurrency/latest

Test location /workspace/coverage/default/1.chip_sw_example_flash.410405077
Short name T1057
Test name
Test status
Simulation time 2915634028 ps
CPU time 238.62 seconds
Started Aug 08 08:21:39 PM PDT 24
Finished Aug 08 08:25:37 PM PDT 24
Peak memory 609688 kb
Host smart-fb5b5d2b-f3ab-4e8f-b6dc-836d567a011b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410405077 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_example_flash.410405077
Directory /workspace/1.chip_sw_example_flash/latest

Test location /workspace/coverage/default/1.chip_sw_example_manufacturer.2728753697
Short name T1262
Test name
Test status
Simulation time 2439131708 ps
CPU time 179.97 seconds
Started Aug 08 08:21:28 PM PDT 24
Finished Aug 08 08:24:28 PM PDT 24
Peak memory 609372 kb
Host smart-63c3490c-0c65-4ced-9aa3-995aab2fc0f6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728753697 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_example_manufacturer.2728753697
Directory /workspace/1.chip_sw_example_manufacturer/latest

Test location /workspace/coverage/default/1.chip_sw_example_rom.3260558758
Short name T1110
Test name
Test status
Simulation time 1995291096 ps
CPU time 125.68 seconds
Started Aug 08 08:21:11 PM PDT 24
Finished Aug 08 08:23:17 PM PDT 24
Peak memory 607912 kb
Host smart-cbaeed93-83e1-4eb9-afa8-54e7d4446f6f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260558758 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_example_rom.3260558758
Directory /workspace/1.chip_sw_example_rom/latest

Test location /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2266931097
Short name T207
Test name
Test status
Simulation time 58251159981 ps
CPU time 11258.1 seconds
Started Aug 08 08:21:59 PM PDT 24
Finished Aug 08 11:29:38 PM PDT 24
Peak memory 624752 kb
Host smart-7729ddfc-f7b9-46f5-baae-e8517d166fae
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=2266931097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.2266931097
Directory /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest

Test location /workspace/coverage/default/1.chip_sw_flash_crash_alert.175836029
Short name T1049
Test name
Test status
Simulation time 5173083856 ps
CPU time 604.85 seconds
Started Aug 08 08:32:33 PM PDT 24
Finished Aug 08 08:42:38 PM PDT 24
Peak memory 611200 kb
Host smart-c97b71b1-4f47-40bc-98c8-c62e163aae72
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:
new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=175836029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.175836029
Directory /workspace/1.chip_sw_flash_crash_alert/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_access.1806256610
Short name T1031
Test name
Test status
Simulation time 6045777240 ps
CPU time 1148.98 seconds
Started Aug 08 08:25:07 PM PDT 24
Finished Aug 08 08:44:18 PM PDT 24
Peak memory 610092 kb
Host smart-d1d9cef7-97a7-463e-82dc-08a764171e44
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806256610 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.chip_sw_flash_ctrl_access.1806256610
Directory /workspace/1.chip_sw_flash_ctrl_access/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.613752968
Short name T883
Test name
Test status
Simulation time 6467893973 ps
CPU time 1200.29 seconds
Started Aug 08 08:23:39 PM PDT 24
Finished Aug 08 08:43:39 PM PDT 24
Peak memory 609316 kb
Host smart-2edb59ff-69d3-4d80-9354-056b8b2afbc6
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613752968 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.613752968
Directory /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2151366921
Short name T398
Test name
Test status
Simulation time 7012516888 ps
CPU time 1250.96 seconds
Started Aug 08 08:33:10 PM PDT 24
Finished Aug 08 08:54:02 PM PDT 24
Peak memory 610088 kb
Host smart-3029df44-0b8c-4074-a259-81b8edac5a2c
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151366921 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2151366921
Directory /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1122800867
Short name T1346
Test name
Test status
Simulation time 5668516339 ps
CPU time 1089.98 seconds
Started Aug 08 08:24:17 PM PDT 24
Finished Aug 08 08:42:27 PM PDT 24
Peak memory 609256 kb
Host smart-6a660590-cd75-4457-8d9a-c222eaa086dd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122800867 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.1122800867
Directory /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.720909291
Short name T1040
Test name
Test status
Simulation time 3589961572 ps
CPU time 370.75 seconds
Started Aug 08 08:23:46 PM PDT 24
Finished Aug 08 08:29:57 PM PDT 24
Peak memory 609948 kb
Host smart-5576aa76-b24b-4339-b1ad-33684b62a853
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720909291 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.720909291
Directory /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3438936236
Short name T1242
Test name
Test status
Simulation time 4091308218 ps
CPU time 444.44 seconds
Started Aug 08 08:28:25 PM PDT 24
Finished Aug 08 08:35:51 PM PDT 24
Peak memory 610284 kb
Host smart-5596c83a-2eaa-4f24-adac-6e71c451fe5f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34
38936236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.3438936236
Directory /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3355752285
Short name T979
Test name
Test status
Simulation time 5128861196 ps
CPU time 1287.19 seconds
Started Aug 08 08:34:02 PM PDT 24
Finished Aug 08 08:55:30 PM PDT 24
Peak memory 609440 kb
Host smart-9f4082a0-f2aa-4f6b-bee6-532c3bf28f23
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355752285 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.3355752285
Directory /workspace/1.chip_sw_flash_ctrl_mem_protection/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2357028264
Short name T335
Test name
Test status
Simulation time 3659372308 ps
CPU time 672.06 seconds
Started Aug 08 08:25:16 PM PDT 24
Finished Aug 08 08:36:29 PM PDT 24
Peak memory 609928 kb
Host smart-89ad818d-8416-4f41-b70b-965307753979
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2357028264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.2357028264
Directory /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3335729080
Short name T343
Test name
Test status
Simulation time 4825305345 ps
CPU time 616.83 seconds
Started Aug 08 08:32:17 PM PDT 24
Finished Aug 08 08:42:34 PM PDT 24
Peak memory 609896 kb
Host smart-eb9ee23e-c91f-425a-b3b3-7473a89d53b1
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_
rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3335729080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3335729080
Directory /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.3140791269
Short name T943
Test name
Test status
Simulation time 2737621512 ps
CPU time 407.75 seconds
Started Aug 08 08:32:36 PM PDT 24
Finished Aug 08 08:39:24 PM PDT 24
Peak memory 608576 kb
Host smart-cc3e1eaa-13bb-4abb-86d9-84ee8af73ca3
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140791
269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.3140791269
Directory /workspace/1.chip_sw_flash_ctrl_write_clear/latest

Test location /workspace/coverage/default/1.chip_sw_flash_init.2297310490
Short name T1220
Test name
Test status
Simulation time 19958223062 ps
CPU time 1791.93 seconds
Started Aug 08 08:24:13 PM PDT 24
Finished Aug 08 08:54:06 PM PDT 24
Peak memory 614432 kb
Host smart-8733be32-0496-4e0f-b235-f44b4b16c4de
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297310490 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.2297310490
Directory /workspace/1.chip_sw_flash_init/latest

Test location /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1177718346
Short name T1293
Test name
Test status
Simulation time 17775030657 ps
CPU time 1916.06 seconds
Started Aug 08 08:31:54 PM PDT 24
Finished Aug 08 09:03:50 PM PDT 24
Peak memory 613512 kb
Host smart-1c8425a1-8cdf-40c3-bfce-18bc2c93b5ac
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1177718346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.1177718346
Directory /workspace/1.chip_sw_flash_init_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1960444072
Short name T115
Test name
Test status
Simulation time 2426169358 ps
CPU time 182.98 seconds
Started Aug 08 08:36:26 PM PDT 24
Finished Aug 08 08:39:29 PM PDT 24
Peak memory 609684 kb
Host smart-c18c501b-59bd-4088-bd7d-575ede8df7dc
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket
est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1960444072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.1960444072
Directory /workspace/1.chip_sw_flash_scrambling_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc.3673391328
Short name T856
Test name
Test status
Simulation time 2669260322 ps
CPU time 202.92 seconds
Started Aug 08 08:28:48 PM PDT 24
Finished Aug 08 08:32:11 PM PDT 24
Peak memory 609804 kb
Host smart-9938f481-e35e-4c94-9cdb-09d23c88a1ec
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673391328 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_hmac_enc.3673391328
Directory /workspace/1.chip_sw_hmac_enc/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3373739699
Short name T1097
Test name
Test status
Simulation time 2873461732 ps
CPU time 316.36 seconds
Started Aug 08 08:31:59 PM PDT 24
Finished Aug 08 08:37:16 PM PDT 24
Peak memory 609776 kb
Host smart-891a81a9-fec0-413e-90e7-0a40ab232728
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373739699 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_hmac_enc_idle.3373739699
Directory /workspace/1.chip_sw_hmac_enc_idle/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2268418379
Short name T925
Test name
Test status
Simulation time 2978816539 ps
CPU time 221.89 seconds
Started Aug 08 08:28:18 PM PDT 24
Finished Aug 08 08:32:00 PM PDT 24
Peak memory 609752 kb
Host smart-cf2c8ad5-7576-47f4-8181-f534cb5cd25d
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268418379 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.2268418379
Directory /workspace/1.chip_sw_hmac_enc_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1107596239
Short name T112
Test name
Test status
Simulation time 2731816104 ps
CPU time 283.83 seconds
Started Aug 08 08:33:29 PM PDT 24
Finished Aug 08 08:38:13 PM PDT 24
Peak memory 609800 kb
Host smart-ec2045d0-4591-46e1-b2b2-e32e42eb646c
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107596239 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.1107596239
Directory /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_multistream.3087967677
Short name T1187
Test name
Test status
Simulation time 7480983384 ps
CPU time 1668.84 seconds
Started Aug 08 08:30:40 PM PDT 24
Finished Aug 08 08:58:29 PM PDT 24
Peak memory 608868 kb
Host smart-f6a184b7-d37d-46ae-9b4d-e3e987a5a440
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087967677 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_hmac_multistream.3087967677
Directory /workspace/1.chip_sw_hmac_multistream/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_oneshot.3797158008
Short name T1235
Test name
Test status
Simulation time 3186067148 ps
CPU time 311.3 seconds
Started Aug 08 08:29:15 PM PDT 24
Finished Aug 08 08:34:27 PM PDT 24
Peak memory 609752 kb
Host smart-10a38b8f-b52c-40d6-aee2-9f99fd7809c7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797158008 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_hmac_oneshot.3797158008
Directory /workspace/1.chip_sw_hmac_oneshot/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_smoketest.1278044563
Short name T198
Test name
Test status
Simulation time 3262282440 ps
CPU time 413.44 seconds
Started Aug 08 08:35:07 PM PDT 24
Finished Aug 08 08:42:00 PM PDT 24
Peak memory 609716 kb
Host smart-6474ae3b-bed6-470d-a024-df52fbcfea27
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278044563 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_hmac_smoketest.1278044563
Directory /workspace/1.chip_sw_hmac_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.82740307
Short name T323
Test name
Test status
Simulation time 4057116568 ps
CPU time 599.17 seconds
Started Aug 08 08:23:10 PM PDT 24
Finished Aug 08 08:33:09 PM PDT 24
Peak memory 609744 kb
Host smart-5238f6d0-5c42-4c10-83df-689eba9da40a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82740307 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.82740307
Directory /workspace/1.chip_sw_i2c_device_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3085215165
Short name T317
Test name
Test status
Simulation time 5362684584 ps
CPU time 689.6 seconds
Started Aug 08 08:22:25 PM PDT 24
Finished Aug 08 08:33:55 PM PDT 24
Peak memory 609456 kb
Host smart-44f29506-1503-481e-a916-2c63573810ff
User root
Command /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085215165 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.3085215165
Directory /workspace/1.chip_sw_i2c_host_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3194755222
Short name T217
Test name
Test status
Simulation time 4868080042 ps
CPU time 966.21 seconds
Started Aug 08 08:24:18 PM PDT 24
Finished Aug 08 08:40:25 PM PDT 24
Peak memory 609968 kb
Host smart-0495bf5b-482f-4ab5-8d80-edbdd716df56
User root
Command /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194755222 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.3194755222
Directory /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1812660026
Short name T319
Test name
Test status
Simulation time 5806277632 ps
CPU time 714.92 seconds
Started Aug 08 08:22:16 PM PDT 24
Finished Aug 08 08:34:11 PM PDT 24
Peak memory 609456 kb
Host smart-c5ce3391-5d9d-4a08-a3e6-569ea2692760
User root
Command /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812660026 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.1812660026
Directory /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest

Test location /workspace/coverage/default/1.chip_sw_inject_scramble_seed.164689669
Short name T206
Test name
Test status
Simulation time 65763099559 ps
CPU time 11274 seconds
Started Aug 08 08:23:23 PM PDT 24
Finished Aug 08 11:31:19 PM PDT 24
Peak memory 624864 kb
Host smart-931b6eea-b51d-461e-8e58-14d2b3d0c37e
User root
Command /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=164689669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.164689669
Directory /workspace/1.chip_sw_inject_scramble_seed/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3713969247
Short name T1118
Test name
Test status
Simulation time 9489007990 ps
CPU time 2213.85 seconds
Started Aug 08 08:29:59 PM PDT 24
Finished Aug 08 09:06:53 PM PDT 24
Peak memory 617876 kb
Host smart-3cc4dc0b-856b-4e89-ba62-72eb8cb3f9c7
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713
969247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.3713969247
Directory /workspace/1.chip_sw_keymgr_key_derivation/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2237217980
Short name T1082
Test name
Test status
Simulation time 9668643793 ps
CPU time 1890.18 seconds
Started Aug 08 08:29:18 PM PDT 24
Finished Aug 08 09:00:48 PM PDT 24
Peak memory 617872 kb
Host smart-e024ba1e-8eb5-4919-a777-4951e5f94d5c
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2237217980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.2237217980
Directory /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2547559978
Short name T1068
Test name
Test status
Simulation time 10064468463 ps
CPU time 1996.11 seconds
Started Aug 08 08:33:34 PM PDT 24
Finished Aug 08 09:06:51 PM PDT 24
Peak memory 617608 kb
Host smart-e3ebb849-c369-4fc9-ab13-6459304f6353
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2547559978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en
_reduced_freq.2547559978
Directory /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.4164721185
Short name T269
Test name
Test status
Simulation time 8358335144 ps
CPU time 1578.78 seconds
Started Aug 08 08:30:03 PM PDT 24
Finished Aug 08 08:56:22 PM PDT 24
Peak memory 616844 kb
Host smart-7a390143-c20f-4849-9f20-50e707db0bd9
User root
Command /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4164721185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.4164721185
Directory /workspace/1.chip_sw_keymgr_key_derivation_prod/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2934047279
Short name T268
Test name
Test status
Simulation time 9204028918 ps
CPU time 2423.32 seconds
Started Aug 08 08:29:57 PM PDT 24
Finished Aug 08 09:10:21 PM PDT 24
Peak memory 610848 kb
Host smart-7a61917c-41e8-4afc-9c78-4585ba473df6
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293404
7279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.2934047279
Directory /workspace/1.chip_sw_keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3384913426
Short name T408
Test name
Test status
Simulation time 9274496760 ps
CPU time 1967.28 seconds
Started Aug 08 08:30:07 PM PDT 24
Finished Aug 08 09:02:54 PM PDT 24
Peak memory 611040 kb
Host smart-61ecb491-b0b6-44cc-8f84-93279531c5d7
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33849
13426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.3384913426
Directory /workspace/1.chip_sw_keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3132331367
Short name T273
Test name
Test status
Simulation time 15930213592 ps
CPU time 4846.19 seconds
Started Aug 08 08:29:21 PM PDT 24
Finished Aug 08 09:50:08 PM PDT 24
Peak memory 609952 kb
Host smart-2b6846d0-5c4a-47d8-b5a5-35d782fb2dc2
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31323
31367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.3132331367
Directory /workspace/1.chip_sw_keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_app_rom.1391983448
Short name T383
Test name
Test status
Simulation time 2684380352 ps
CPU time 285.72 seconds
Started Aug 08 08:35:25 PM PDT 24
Finished Aug 08 08:40:11 PM PDT 24
Peak memory 609320 kb
Host smart-8c4c3b67-49b2-4e64-a828-f7fb4c8d550f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391983448 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_kmac_app_rom.1391983448
Directory /workspace/1.chip_sw_kmac_app_rom/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_entropy.2328173274
Short name T392
Test name
Test status
Simulation time 2882425576 ps
CPU time 283.83 seconds
Started Aug 08 08:23:18 PM PDT 24
Finished Aug 08 08:28:02 PM PDT 24
Peak memory 608432 kb
Host smart-a0a8d591-c13e-43c0-bcbb-fcdef1f5944d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328173274 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_kmac_entropy.2328173274
Directory /workspace/1.chip_sw_kmac_entropy/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_idle.2294870525
Short name T1009
Test name
Test status
Simulation time 2701250756 ps
CPU time 219.45 seconds
Started Aug 08 08:35:38 PM PDT 24
Finished Aug 08 08:39:18 PM PDT 24
Peak memory 609316 kb
Host smart-d50ee917-fdcb-4194-bc62-adbecc960c43
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294870525 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_kmac_idle.2294870525
Directory /workspace/1.chip_sw_kmac_idle/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3702060833
Short name T896
Test name
Test status
Simulation time 3067137566 ps
CPU time 269.86 seconds
Started Aug 08 08:35:52 PM PDT 24
Finished Aug 08 08:40:23 PM PDT 24
Peak memory 609324 kb
Host smart-b9fedaaf-b101-44fb-a57e-6c96f5314b0c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702060833 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.chip_sw_kmac_mode_cshake.3702060833
Directory /workspace/1.chip_sw_kmac_mode_cshake/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2565489303
Short name T1192
Test name
Test status
Simulation time 3334837428 ps
CPU time 345.33 seconds
Started Aug 08 08:29:30 PM PDT 24
Finished Aug 08 08:35:15 PM PDT 24
Peak memory 609732 kb
Host smart-d4f4d221-bfe9-4f47-9d09-65efae2ebf75
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565489303 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_kmac_mode_kmac.2565489303
Directory /workspace/1.chip_sw_kmac_mode_kmac/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1102595116
Short name T1033
Test name
Test status
Simulation time 2887494465 ps
CPU time 302.18 seconds
Started Aug 08 08:29:50 PM PDT 24
Finished Aug 08 08:34:53 PM PDT 24
Peak memory 609724 kb
Host smart-0cd4c756-ce83-4de4-ba5c-64b696377ef4
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102595116 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.1102595116
Directory /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.250756636
Short name T865
Test name
Test status
Simulation time 2789785461 ps
CPU time 270.11 seconds
Started Aug 08 08:39:56 PM PDT 24
Finished Aug 08 08:44:27 PM PDT 24
Peak memory 609812 kb
Host smart-aab08634-6c44-49d3-a95b-477c4dbca4a8
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25075663
6 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.250756636
Directory /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_smoketest.2324571943
Short name T1298
Test name
Test status
Simulation time 3101139656 ps
CPU time 338.99 seconds
Started Aug 08 08:34:25 PM PDT 24
Finished Aug 08 08:40:04 PM PDT 24
Peak memory 609280 kb
Host smart-87364930-a4c7-40a4-8feb-97384920e86d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324571943 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_kmac_smoketest.2324571943
Directory /workspace/1.chip_sw_kmac_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1846121967
Short name T951
Test name
Test status
Simulation time 2359277596 ps
CPU time 233.13 seconds
Started Aug 08 08:23:19 PM PDT 24
Finished Aug 08 08:27:12 PM PDT 24
Peak memory 609548 kb
Host smart-1f9f06f8-2f76-4dad-97b1-8990ef33dd11
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846121967 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.1846121967
Directory /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3339596196
Short name T166
Test name
Test status
Simulation time 4899209892 ps
CPU time 445.26 seconds
Started Aug 08 08:31:10 PM PDT 24
Finished Aug 08 08:38:36 PM PDT 24
Peak memory 610876 kb
Host smart-df9c08f1-d9ed-41f4-98a1-18607cbe5ed9
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3339596196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.3339596196
Directory /workspace/1.chip_sw_lc_ctrl_program_error/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3230077558
Short name T245
Test name
Test status
Simulation time 3568414663 ps
CPU time 171.43 seconds
Started Aug 08 08:25:20 PM PDT 24
Finished Aug 08 08:28:12 PM PDT 24
Peak memory 620084 kb
Host smart-ddcaeb6f-a78b-4575-962d-81c00b1e2e24
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32300775
58 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.3230077558
Directory /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.4174354990
Short name T259
Test name
Test status
Simulation time 5346256469 ps
CPU time 460.51 seconds
Started Aug 08 08:26:19 PM PDT 24
Finished Aug 08 08:33:59 PM PDT 24
Peak memory 621152 kb
Host smart-7d29d190-48c3-42e6-8d4c-eee0520ee7b0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174354990 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.4174354990
Directory /workspace/1.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3690855339
Short name T1
Test name
Test status
Simulation time 2231560111 ps
CPU time 100.26 seconds
Started Aug 08 08:25:17 PM PDT 24
Finished Aug 08 08:26:57 PM PDT 24
Peak memory 617964 kb
Host smart-f8c8ac29-a678-4c05-8add-594040d3bb6a
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes
t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3690855339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.3690855339
Directory /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.246706922
Short name T70
Test name
Test status
Simulation time 2249701016 ps
CPU time 105.94 seconds
Started Aug 08 08:24:33 PM PDT 24
Finished Aug 08 08:26:19 PM PDT 24
Peak memory 617064 kb
Host smart-ced70673-a101-4e68-97ae-d634cd8f852f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s
im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246706922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST
_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.246706922
Directory /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.391770855
Short name T279
Test name
Test status
Simulation time 47329416260 ps
CPU time 6056.73 seconds
Started Aug 08 08:24:51 PM PDT 24
Finished Aug 08 10:05:48 PM PDT 24
Peak memory 620512 kb
Host smart-cf63a8bd-1ba7-41b9-9ee7-f9136b1297c0
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391770855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch
ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_
sw_lc_walkthrough_dev.391770855
Directory /workspace/1.chip_sw_lc_walkthrough_dev/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3551992858
Short name T285
Test name
Test status
Simulation time 50729446538 ps
CPU time 5593.69 seconds
Started Aug 08 08:25:43 PM PDT 24
Finished Aug 08 09:58:58 PM PDT 24
Peak memory 620612 kb
Host smart-93936159-8a01-40fb-810f-98896751f021
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d
evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551992858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi
p_sw_lc_walkthrough_prod.3551992858
Directory /workspace/1.chip_sw_lc_walkthrough_prod/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.4031733457
Short name T944
Test name
Test status
Simulation time 8411711960 ps
CPU time 1022.32 seconds
Started Aug 08 08:25:37 PM PDT 24
Finished Aug 08 08:42:40 PM PDT 24
Peak memory 619312 kb
Host smart-2a97fcbb-4899-4639-97df-6a0006b16484
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa
lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031733457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.4031733457
Directory /workspace/1.chip_sw_lc_walkthrough_prodend/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1354714343
Short name T1201
Test name
Test status
Simulation time 48038648245 ps
CPU time 6144.26 seconds
Started Aug 08 08:25:51 PM PDT 24
Finished Aug 08 10:08:16 PM PDT 24
Peak memory 620692 kb
Host smart-fa059f65-282a-4275-a114-60d10637b063
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354714343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip
_sw_lc_walkthrough_rma.1354714343
Directory /workspace/1.chip_sw_lc_walkthrough_rma/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2833242203
Short name T897
Test name
Test status
Simulation time 29871843254 ps
CPU time 2203.06 seconds
Started Aug 08 08:24:17 PM PDT 24
Finished Aug 08 09:01:01 PM PDT 24
Peak memory 621176 kb
Host smart-95d485e7-178d-484b-ae5d-b8eac1e28912
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks
_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2833242203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun
locks.2833242203
Directory /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.4039988760
Short name T1046
Test name
Test status
Simulation time 17656547642 ps
CPU time 4327.77 seconds
Started Aug 08 08:26:14 PM PDT 24
Finished Aug 08 09:38:22 PM PDT 24
Peak memory 610236 kb
Host smart-89c4df56-f4d6-4741-a0f9-1bb9cde84b5d
User root
Command /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_
rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4039988760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.4039988760
Directory /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.832816433
Short name T945
Test name
Test status
Simulation time 19168706156 ps
CPU time 3716.44 seconds
Started Aug 08 08:27:34 PM PDT 24
Finished Aug 08 09:29:31 PM PDT 24
Peak memory 610032 kb
Host smart-40083a19-7653-4ce3-8828-b7e5dadd2347
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne
w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=832816433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.832816433
Directory /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.642355176
Short name T1236
Test name
Test status
Simulation time 25243558935 ps
CPU time 3998.51 seconds
Started Aug 08 08:31:58 PM PDT 24
Finished Aug 08 09:38:37 PM PDT 24
Peak memory 610348 kb
Host smart-38373805-d728-482c-8f48-3efce56085f1
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e
cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642355176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc
ed_freq.642355176
Directory /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2868513011
Short name T248
Test name
Test status
Simulation time 3835098048 ps
CPU time 396.81 seconds
Started Aug 08 08:26:08 PM PDT 24
Finished Aug 08 08:32:46 PM PDT 24
Peak memory 609492 kb
Host smart-6bf9669d-0ed8-4819-823d-2bbd70283652
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn
_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868513011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.2868513011
Directory /workspace/1.chip_sw_otbn_mem_scramble/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_randomness.1427656899
Short name T320
Test name
Test status
Simulation time 5999544120 ps
CPU time 1089.22 seconds
Started Aug 08 08:27:26 PM PDT 24
Finished Aug 08 08:45:35 PM PDT 24
Peak memory 610232 kb
Host smart-bc06d392-c4d3-4fea-af34-5b141f3652f6
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1427656899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.1427656899
Directory /workspace/1.chip_sw_otbn_randomness/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_smoketest.883335621
Short name T1150
Test name
Test status
Simulation time 7443217104 ps
CPU time 1695.37 seconds
Started Aug 08 08:34:09 PM PDT 24
Finished Aug 08 09:02:25 PM PDT 24
Peak memory 610228 kb
Host smart-5669efc7-2aba-45e9-880e-9aa5ad1599a0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883335621 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_otbn_smoketest.883335621
Directory /workspace/1.chip_sw_otbn_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2003225382
Short name T411
Test name
Test status
Simulation time 2759028161 ps
CPU time 286.15 seconds
Started Aug 08 08:24:50 PM PDT 24
Finished Aug 08 08:29:36 PM PDT 24
Peak memory 608736 kb
Host smart-1e4272b0-8c2f-45d3-921f-1c6d6cb638e7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003225382 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.2003225382
Directory /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.264375410
Short name T1015
Test name
Test status
Simulation time 7731699532 ps
CPU time 1440.1 seconds
Started Aug 08 08:27:18 PM PDT 24
Finished Aug 08 08:51:19 PM PDT 24
Peak memory 610436 kb
Host smart-2c3705bd-fa62-4395-945f-78c1600a8707
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=264375410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.264375410
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2433117625
Short name T1299
Test name
Test status
Simulation time 7327543982 ps
CPU time 1639.69 seconds
Started Aug 08 08:25:12 PM PDT 24
Finished Aug 08 08:52:32 PM PDT 24
Peak memory 610784 kb
Host smart-bbedbc6d-9a39-4808-be00-ad6e1d205f06
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2433117625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.2433117625
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2665516156
Short name T155
Test name
Test status
Simulation time 7343089502 ps
CPU time 1112.44 seconds
Started Aug 08 08:24:45 PM PDT 24
Finished Aug 08 08:43:18 PM PDT 24
Peak memory 610760 kb
Host smart-1504d88f-755e-497e-9b38-2cd8a5ee4e76
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2665516156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.2665516156
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2491504816
Short name T1006
Test name
Test status
Simulation time 5299835700 ps
CPU time 810.01 seconds
Started Aug 08 08:24:53 PM PDT 24
Finished Aug 08 08:38:24 PM PDT 24
Peak memory 610120 kb
Host smart-2099d7f9-8889-4149-9a52-06cfd9ab077a
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=2491504816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2491504816
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3647017628
Short name T917
Test name
Test status
Simulation time 3177667642 ps
CPU time 302.95 seconds
Started Aug 08 08:34:16 PM PDT 24
Finished Aug 08 08:39:19 PM PDT 24
Peak memory 609348 kb
Host smart-bec897da-7565-4ec6-b5ef-ae589db4ed8d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647017628 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_otp_ctrl_smoketest.3647017628
Directory /workspace/1.chip_sw_otp_ctrl_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_pattgen_ios.735854810
Short name T331
Test name
Test status
Simulation time 3032230792 ps
CPU time 257.81 seconds
Started Aug 08 08:22:30 PM PDT 24
Finished Aug 08 08:26:48 PM PDT 24
Peak memory 610312 kb
Host smart-6109a43d-7a49-4cbb-a7ab-986592cf5e41
User root
Command /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735854810 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.735854810
Directory /workspace/1.chip_sw_pattgen_ios/latest

Test location /workspace/coverage/default/1.chip_sw_plic_sw_irq.1732457577
Short name T229
Test name
Test status
Simulation time 2841491378 ps
CPU time 236.13 seconds
Started Aug 08 08:30:26 PM PDT 24
Finished Aug 08 08:34:22 PM PDT 24
Peak memory 609744 kb
Host smart-1e2af090-97e3-46a3-9634-864cbf4a3e1a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732457577 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.chip_sw_plic_sw_irq.1732457577
Directory /workspace/1.chip_sw_plic_sw_irq/latest

Test location /workspace/coverage/default/1.chip_sw_power_idle_load.1400509357
Short name T1052
Test name
Test status
Simulation time 4998806246 ps
CPU time 677.18 seconds
Started Aug 08 08:32:46 PM PDT 24
Finished Aug 08 08:44:03 PM PDT 24
Peak memory 609440 kb
Host smart-f28c35c5-e64d-42c5-8da7-118b011f033d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400509357 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.1400509357
Directory /workspace/1.chip_sw_power_idle_load/latest

Test location /workspace/coverage/default/1.chip_sw_power_sleep_load.78927325
Short name T653
Test name
Test status
Simulation time 10831107200 ps
CPU time 614.4 seconds
Started Aug 08 08:32:36 PM PDT 24
Finished Aug 08 08:42:50 PM PDT 24
Peak memory 610696 kb
Host smart-128dc309-a878-4bdb-b597-38329a768687
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78927325 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.78927325
Directory /workspace/1.chip_sw_power_sleep_load/latest

Test location /workspace/coverage/default/1.chip_sw_power_virus.4007241768
Short name T199
Test name
Test status
Simulation time 5618546858 ps
CPU time 1601.1 seconds
Started Aug 08 08:39:26 PM PDT 24
Finished Aug 08 09:06:07 PM PDT 24
Peak memory 624940 kb
Host smart-5eb74e65-32cb-4f19-910d-b4d69b44fb2b
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_
power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes
t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4007241768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.4007241768
Directory /workspace/1.chip_sw_power_virus/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3817623441
Short name T1273
Test name
Test status
Simulation time 27749244139 ps
CPU time 3022.11 seconds
Started Aug 08 08:31:21 PM PDT 24
Finished Aug 08 09:21:44 PM PDT 24
Peak memory 610928 kb
Host smart-aa4bef68-6704-4a0b-912c-cafe5c118040
User root
Command /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381
7623441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.3817623441
Directory /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2820448123
Short name T909
Test name
Test status
Simulation time 15038037293 ps
CPU time 1582.73 seconds
Started Aug 08 08:24:49 PM PDT 24
Finished Aug 08 08:51:12 PM PDT 24
Peak memory 611320 kb
Host smart-321e8ecd-25b3-4597-a507-6b38663f9da5
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2820448123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2820448123
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3256961220
Short name T1255
Test name
Test status
Simulation time 25833618380 ps
CPU time 1846.49 seconds
Started Aug 08 08:31:47 PM PDT 24
Finished Aug 08 09:02:34 PM PDT 24
Peak memory 611080 kb
Host smart-9eb71523-ec38-4556-a2fb-d7505836f4fa
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3256961220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3256961220
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1190429659
Short name T1115
Test name
Test status
Simulation time 8301997544 ps
CPU time 571.56 seconds
Started Aug 08 08:25:49 PM PDT 24
Finished Aug 08 08:35:21 PM PDT 24
Peak memory 610568 kb
Host smart-dd6d155b-c682-4ce1-a2de-7170eeea2f87
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190429659 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.1190429659
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3892020709
Short name T1138
Test name
Test status
Simulation time 7037411048 ps
CPU time 353.75 seconds
Started Aug 08 08:25:51 PM PDT 24
Finished Aug 08 08:31:45 PM PDT 24
Peak memory 616348 kb
Host smart-27c8be04-7416-4914-8c12-5e32066d69e7
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3892020709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3892020709
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3227988014
Short name T1132
Test name
Test status
Simulation time 8998332517 ps
CPU time 385.98 seconds
Started Aug 08 08:25:24 PM PDT 24
Finished Aug 08 08:31:51 PM PDT 24
Peak memory 610792 kb
Host smart-a9fa8e13-c6bd-49d2-bc6d-1bbfe0ccbf24
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227988014 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.3227988014
Directory /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.791451200
Short name T326
Test name
Test status
Simulation time 3676656104 ps
CPU time 588.14 seconds
Started Aug 08 08:31:54 PM PDT 24
Finished Aug 08 08:41:42 PM PDT 24
Peak memory 609424 kb
Host smart-d9edc173-1210-46a3-8a26-54d0da0400a5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791451200 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.791451200
Directory /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.391045101
Short name T113
Test name
Test status
Simulation time 5490676290 ps
CPU time 486.45 seconds
Started Aug 08 08:25:17 PM PDT 24
Finished Aug 08 08:33:24 PM PDT 24
Peak memory 616228 kb
Host smart-46b1fea7-4290-482a-9274-ceb741bcdf23
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=391045101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.391045101
Directory /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4223410220
Short name T1260
Test name
Test status
Simulation time 11351274390 ps
CPU time 902.84 seconds
Started Aug 08 08:24:47 PM PDT 24
Finished Aug 08 08:39:50 PM PDT 24
Peak memory 611488 kb
Host smart-4e7aa361-9c3c-4bca-b199-6360cbe5a528
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223410220 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4223410220
Directory /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1332227491
Short name T385
Test name
Test status
Simulation time 7321762520 ps
CPU time 477.43 seconds
Started Aug 08 08:32:21 PM PDT 24
Finished Aug 08 08:40:18 PM PDT 24
Peak memory 610404 kb
Host smart-ab19f362-e914-4057-94ee-2d1444d4576b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332227491 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1332227491
Directory /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3934540568
Short name T625
Test name
Test status
Simulation time 6276819626 ps
CPU time 542.99 seconds
Started Aug 08 08:27:56 PM PDT 24
Finished Aug 08 08:37:00 PM PDT 24
Peak memory 610752 kb
Host smart-78f00e05-c953-40d3-bc34-643bd8d26661
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934540568 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.3934540568
Directory /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1623684162
Short name T19
Test name
Test status
Simulation time 22622327192 ps
CPU time 1111.69 seconds
Started Aug 08 08:31:21 PM PDT 24
Finished Aug 08 08:49:53 PM PDT 24
Peak memory 610768 kb
Host smart-92a501f9-729d-416a-92ae-74965a6d13a5
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1623684162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1623684162
Directory /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3413029829
Short name T1000
Test name
Test status
Simulation time 37075722960 ps
CPU time 2953.23 seconds
Started Aug 08 08:28:06 PM PDT 24
Finished Aug 08 09:17:20 PM PDT 24
Peak memory 611448 kb
Host smart-92cedac2-461a-4693-8bd9-65feb402c5cf
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power
_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413029829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit
ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s
leep_power_glitch_reset.3413029829
Directory /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1686355635
Short name T143
Test name
Test status
Simulation time 5704342162 ps
CPU time 455.82 seconds
Started Aug 08 08:32:22 PM PDT 24
Finished Aug 08 08:39:59 PM PDT 24
Peak memory 611028 kb
Host smart-ee62589a-0ada-42ab-bc09-1fdce564fb88
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul
es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1686355635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s
leep_wake_up.1686355635
Directory /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.118330585
Short name T645
Test name
Test status
Simulation time 3455199480 ps
CPU time 220.17 seconds
Started Aug 08 08:26:07 PM PDT 24
Finished Aug 08 08:29:47 PM PDT 24
Peak memory 609572 kb
Host smart-4f59a5fd-2e59-40c3-b417-c86797581a0e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118330585 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.118330585
Directory /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2697140981
Short name T1121
Test name
Test status
Simulation time 5937124160 ps
CPU time 396.83 seconds
Started Aug 08 08:25:23 PM PDT 24
Finished Aug 08 08:32:01 PM PDT 24
Peak memory 616836 kb
Host smart-b7bfee2a-a908-47a7-a6d4-4de3d65ba377
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=2697140981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.2697140981
Directory /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1334317560
Short name T133
Test name
Test status
Simulation time 5793789178 ps
CPU time 375.99 seconds
Started Aug 08 08:31:19 PM PDT 24
Finished Aug 08 08:37:36 PM PDT 24
Peak memory 609956 kb
Host smart-d32c5697-06c8-4a8f-bbe9-15cc90aa198f
User root
Command /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13343175
60 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1334317560
Directory /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1028432829
Short name T1146
Test name
Test status
Simulation time 5445527870 ps
CPU time 490.48 seconds
Started Aug 08 08:32:07 PM PDT 24
Finished Aug 08 08:40:18 PM PDT 24
Peak memory 610472 kb
Host smart-d89db7b0-fd97-4279-b791-1527bb205608
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1028432829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.1028432829
Directory /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.751386431
Short name T877
Test name
Test status
Simulation time 6121133448 ps
CPU time 613.42 seconds
Started Aug 08 08:34:37 PM PDT 24
Finished Aug 08 08:44:51 PM PDT 24
Peak memory 610476 kb
Host smart-d0e73e48-eb74-4d14-9a4b-1e347377454d
User root
Command /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751386431 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.751386431
Directory /workspace/1.chip_sw_pwrmgr_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1303401166
Short name T1014
Test name
Test status
Simulation time 7200278416 ps
CPU time 1108.04 seconds
Started Aug 08 08:27:12 PM PDT 24
Finished Aug 08 08:45:40 PM PDT 24
Peak memory 610892 kb
Host smart-397e5ba5-cf6c-4421-8f32-400f46b10911
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303401166 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.1303401166
Directory /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1266268164
Short name T891
Test name
Test status
Simulation time 3352201184 ps
CPU time 429.39 seconds
Started Aug 08 08:26:39 PM PDT 24
Finished Aug 08 08:33:48 PM PDT 24
Peak memory 609908 kb
Host smart-cda1b1aa-1ee5-4363-8e8c-da9a830c7d1c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266268164 -assert no
postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1266268164
Directory /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.575820394
Short name T20
Test name
Test status
Simulation time 5519070996 ps
CPU time 342.84 seconds
Started Aug 08 08:34:20 PM PDT 24
Finished Aug 08 08:40:03 PM PDT 24
Peak memory 609452 kb
Host smart-e947476c-7638-4dd4-9127-a454cc15ebec
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575820394 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.575820394
Directory /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2042979948
Short name T108
Test name
Test status
Simulation time 5789413328 ps
CPU time 877.22 seconds
Started Aug 08 08:26:16 PM PDT 24
Finished Aug 08 08:40:53 PM PDT 24
Peak memory 610440 kb
Host smart-08841511-1255-47b5-9910-0aca79545401
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204
2979948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.2042979948
Directory /workspace/1.chip_sw_pwrmgr_wdog_reset/latest

Test location /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3122282639
Short name T1329
Test name
Test status
Simulation time 10149613825 ps
CPU time 504.02 seconds
Started Aug 08 08:29:48 PM PDT 24
Finished Aug 08 08:38:13 PM PDT 24
Peak memory 623740 kb
Host smart-e3894918-45fc-4a73-875e-41d855858010
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122282639 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.3122282639
Directory /workspace/1.chip_sw_rom_ctrl_integrity_check/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.4028862258
Short name T240
Test name
Test status
Simulation time 6115770084 ps
CPU time 504.46 seconds
Started Aug 08 08:25:54 PM PDT 24
Finished Aug 08 08:34:20 PM PDT 24
Peak memory 610360 kb
Host smart-2611a438-5487-46ab-b84f-e01a4024b16a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028862258 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.4028862258
Directory /workspace/1.chip_sw_rstmgr_cpu_info/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.896765788
Short name T332
Test name
Test status
Simulation time 6634360948 ps
CPU time 871.42 seconds
Started Aug 08 08:24:05 PM PDT 24
Finished Aug 08 08:38:37 PM PDT 24
Peak memory 641452 kb
Host smart-4a7889e0-8428-4ff1-8bdb-297030379ae7
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
896765788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.896765788
Directory /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.76583474
Short name T1312
Test name
Test status
Simulation time 2923933680 ps
CPU time 222.35 seconds
Started Aug 08 08:33:59 PM PDT 24
Finished Aug 08 08:37:42 PM PDT 24
Peak memory 609656 kb
Host smart-963c4cd7-8b83-401f-8a0f-8cf88b3d9769
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76583474 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_rstmgr_smoketest.76583474
Directory /workspace/1.chip_sw_rstmgr_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.983462445
Short name T1044
Test name
Test status
Simulation time 4732383400 ps
CPU time 408.45 seconds
Started Aug 08 08:24:41 PM PDT 24
Finished Aug 08 08:31:30 PM PDT 24
Peak memory 609024 kb
Host smart-53fe0f62-a07e-4c12-9242-d5290256d26d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983462445 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_rstmgr_sw_req.983462445
Directory /workspace/1.chip_sw_rstmgr_sw_req/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2242255870
Short name T1211
Test name
Test status
Simulation time 3560434382 ps
CPU time 279.32 seconds
Started Aug 08 08:25:29 PM PDT 24
Finished Aug 08 08:30:08 PM PDT 24
Peak memory 609700 kb
Host smart-871699cf-13f1-4b3a-8390-e30845774bcb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242255870 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.2242255870
Directory /workspace/1.chip_sw_rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.891568664
Short name T181
Test name
Test status
Simulation time 2754731120 ps
CPU time 263.88 seconds
Started Aug 08 08:31:27 PM PDT 24
Finished Aug 08 08:35:51 PM PDT 24
Peak memory 608676 kb
Host smart-1067b456-8c20-49b8-852a-9144858cc433
User root
Command /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=891568664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.891568664
Directory /workspace/1.chip_sw_rv_core_ibex_address_translation/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1805525571
Short name T263
Test name
Test status
Simulation time 2323338062 ps
CPU time 157.2 seconds
Started Aug 08 08:33:24 PM PDT 24
Finished Aug 08 08:36:01 PM PDT 24
Peak memory 609740 kb
Host smart-b26995de-f67b-4a7f-bd2d-e659a4480ccc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805525571 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.1805525571
Directory /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.4122772966
Short name T1336
Test name
Test status
Simulation time 2112354168 ps
CPU time 147.66 seconds
Started Aug 08 08:32:03 PM PDT 24
Finished Aug 08 08:34:31 PM PDT 24
Peak memory 642032 kb
Host smart-d6d939e5-e392-4e0b-97dd-8a55d131d94c
User root
Command /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122772966 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.4122772966
Directory /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2504905542
Short name T656
Test name
Test status
Simulation time 5313055570 ps
CPU time 888.85 seconds
Started Aug 08 08:27:03 PM PDT 24
Finished Aug 08 08:41:53 PM PDT 24
Peak memory 608856 kb
Host smart-7e256029-3213-47c9-ac04-d5bc918e6d8a
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25049
05542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.2504905542
Directory /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.4261478284
Short name T997
Test name
Test status
Simulation time 5877453612 ps
CPU time 714.1 seconds
Started Aug 08 08:26:54 PM PDT 24
Finished Aug 08 08:38:49 PM PDT 24
Peak memory 610036 kb
Host smart-a46c2c22-3963-4361-b457-5f25cf49afaa
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4261478284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.4261478284
Directory /workspace/1.chip_sw_rv_core_ibex_rnd/latest

Test location /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3628321352
Short name T628
Test name
Test status
Simulation time 4086005310 ps
CPU time 484.82 seconds
Started Aug 08 08:31:58 PM PDT 24
Finished Aug 08 08:40:03 PM PDT 24
Peak memory 624312 kb
Host smart-6c9ca8e2-06f9-4ea1-829f-11d1511b60a9
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628321352 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.3628321352
Directory /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.623557081
Short name T1109
Test name
Test status
Simulation time 6731397010 ps
CPU time 477.3 seconds
Started Aug 08 08:31:34 PM PDT 24
Finished Aug 08 08:39:32 PM PDT 24
Peak memory 621440 kb
Host smart-db9a9aeb-605a-4e4c-ae0f-e96c6124d7b3
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623557081 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.623557081
Directory /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1152595887
Short name T1143
Test name
Test status
Simulation time 3556017404 ps
CPU time 288.92 seconds
Started Aug 08 08:34:27 PM PDT 24
Finished Aug 08 08:39:16 PM PDT 24
Peak memory 609704 kb
Host smart-459c22c8-03a0-412c-b7af-2988545387e7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152595887 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_rv_plic_smoketest.1152595887
Directory /workspace/1.chip_sw_rv_plic_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_rv_timer_irq.1154002664
Short name T231
Test name
Test status
Simulation time 3076181740 ps
CPU time 266.26 seconds
Started Aug 08 08:27:13 PM PDT 24
Finished Aug 08 08:31:39 PM PDT 24
Peak memory 608396 kb
Host smart-625602f1-7ff5-476a-9a46-bc339d839e8a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154002664 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_rv_timer_irq.1154002664
Directory /workspace/1.chip_sw_rv_timer_irq/latest

Test location /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3282755281
Short name T1104
Test name
Test status
Simulation time 2857076188 ps
CPU time 275.96 seconds
Started Aug 08 08:33:42 PM PDT 24
Finished Aug 08 08:38:18 PM PDT 24
Peak memory 609656 kb
Host smart-dcbb9845-b446-43eb-80b8-31e698b7d6ed
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282755281 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_rv_timer_smoketest.3282755281
Directory /workspace/1.chip_sw_rv_timer_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1611360655
Short name T137
Test name
Test status
Simulation time 8025069712 ps
CPU time 713.97 seconds
Started Aug 08 08:29:38 PM PDT 24
Finished Aug 08 08:41:32 PM PDT 24
Peak memory 610464 kb
Host smart-9e96ffc3-f7d4-4478-866d-2dadb174031d
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16113606
55 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.1611360655
Directory /workspace/1.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.4166912856
Short name T1278
Test name
Test status
Simulation time 2851671428 ps
CPU time 236.31 seconds
Started Aug 08 08:29:53 PM PDT 24
Finished Aug 08 08:33:49 PM PDT 24
Peak memory 609524 kb
Host smart-2e433bba-62b2-4130-aef8-d88bba9c8564
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166912
856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.4166912856
Directory /workspace/1.chip_sw_sensor_ctrl_status/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pin_retention.4187419202
Short name T27
Test name
Test status
Simulation time 3251164502 ps
CPU time 345.59 seconds
Started Aug 08 08:23:45 PM PDT 24
Finished Aug 08 08:29:31 PM PDT 24
Peak memory 608960 kb
Host smart-6713ac36-b2ce-42d1-9dd5-f6c3693aa593
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187419202 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.4187419202
Directory /workspace/1.chip_sw_sleep_pin_retention/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1818509527
Short name T60
Test name
Test status
Simulation time 3254928754 ps
CPU time 216.19 seconds
Started Aug 08 08:25:55 PM PDT 24
Finished Aug 08 08:29:32 PM PDT 24
Peak memory 610196 kb
Host smart-56aa8ed2-9c74-4f3f-9cbc-b038c6f7988e
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818509527
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.1818509527
Directory /workspace/1.chip_sw_sleep_pin_wake/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.3310975192
Short name T982
Test name
Test status
Simulation time 9248196502 ps
CPU time 1302 seconds
Started Aug 08 08:21:38 PM PDT 24
Finished Aug 08 08:43:21 PM PDT 24
Peak memory 609576 kb
Host smart-c5b2a237-0f48-4092-bf56-5a3ac7a86277
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310975192 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.3310975192
Directory /workspace/1.chip_sw_sleep_pwm_pulses/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3462752583
Short name T870
Test name
Test status
Simulation time 6842201366 ps
CPU time 618.88 seconds
Started Aug 08 08:29:23 PM PDT 24
Finished Aug 08 08:39:43 PM PDT 24
Peak memory 610588 kb
Host smart-78af0a40-3af5-41f8-8b02-fb9a2fd34fc4
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462752583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl
eep_sram_ret_contents_no_scramble.3462752583
Directory /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2334627247
Short name T1172
Test name
Test status
Simulation time 7739306616 ps
CPU time 843.04 seconds
Started Aug 08 08:30:38 PM PDT 24
Finished Aug 08 08:44:41 PM PDT 24
Peak memory 610564 kb
Host smart-89540120-4379-4a18-919a-c96d4446f3f8
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334627247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep
_sram_ret_contents_scramble.2334627247
Directory /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3993125855
Short name T201
Test name
Test status
Simulation time 6489095762 ps
CPU time 701.46 seconds
Started Aug 08 08:24:06 PM PDT 24
Finished Aug 08 08:35:48 PM PDT 24
Peak memory 624752 kb
Host smart-dec1ecf3-a798-45a7-a6ea-273bffb82843
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993125855 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.3993125855
Directory /workspace/1.chip_sw_spi_device_pass_through/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2791799333
Short name T45
Test name
Test status
Simulation time 4567133917 ps
CPU time 598.08 seconds
Started Aug 08 08:25:09 PM PDT 24
Finished Aug 08 08:35:07 PM PDT 24
Peak memory 624776 kb
Host smart-10100997-0071-41f3-a421-02b84151c0e1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791799333 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.2791799333
Directory /workspace/1.chip_sw_spi_device_pass_through_collision/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2345168534
Short name T57
Test name
Test status
Simulation time 3620318641 ps
CPU time 275.01 seconds
Started Aug 08 08:24:44 PM PDT 24
Finished Aug 08 08:29:19 PM PDT 24
Peak memory 619024 kb
Host smart-788a0961-7863-4323-8a22-44996b3e0016
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345168534 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.2345168534
Directory /workspace/1.chip_sw_spi_device_pinmux_sleep_retention/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_tpm.812902997
Short name T44
Test name
Test status
Simulation time 3136727908 ps
CPU time 471.95 seconds
Started Aug 08 08:22:23 PM PDT 24
Finished Aug 08 08:30:16 PM PDT 24
Peak memory 618092 kb
Host smart-ea9383d3-18d3-40aa-abd2-94b402522d55
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812902997 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.812902997
Directory /workspace/1.chip_sw_spi_device_tpm/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.4078265226
Short name T187
Test name
Test status
Simulation time 7143590018 ps
CPU time 1043.88 seconds
Started Aug 08 08:29:56 PM PDT 24
Finished Aug 08 08:47:20 PM PDT 24
Peak memory 610624 kb
Host smart-0c1931c8-e418-4615-add8-d02f3cfb1851
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078265226 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.4078265226
Directory /workspace/1.chip_sw_sram_ctrl_execution_main/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2359949682
Short name T512
Test name
Test status
Simulation time 4133892450 ps
CPU time 639.07 seconds
Started Aug 08 08:29:18 PM PDT 24
Finished Aug 08 08:39:57 PM PDT 24
Peak memory 609528 kb
Host smart-5cf247bb-a71f-4e69-9429-83b821f9517a
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359949682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr
l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw
_sram_ctrl_scrambled_access.2359949682
Directory /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3839710771
Short name T1279
Test name
Test status
Simulation time 4122062254 ps
CPU time 512.81 seconds
Started Aug 08 08:31:36 PM PDT 24
Finished Aug 08 08:40:10 PM PDT 24
Peak memory 610776 kb
Host smart-57db2b94-44db-4eb0-8a45-aa0eb8cd9dd4
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s
w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839710771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3839710771
Directory /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.716627698
Short name T252
Test name
Test status
Simulation time 4909040208 ps
CPU time 711.16 seconds
Started Aug 08 08:33:29 PM PDT 24
Finished Aug 08 08:45:21 PM PDT 24
Peak memory 611252 kb
Host smart-5a58d3c9-35fc-48d6-9dde-77e836f804f3
User root
Command /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk
_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716627698 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.716627698
Directory /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1650154929
Short name T1258
Test name
Test status
Simulation time 2800998218 ps
CPU time 269.31 seconds
Started Aug 08 08:34:51 PM PDT 24
Finished Aug 08 08:39:20 PM PDT 24
Peak memory 609712 kb
Host smart-450f14f0-e336-4c50-822a-1662c6d2e1ed
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650154929 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.1650154929
Directory /workspace/1.chip_sw_sram_ctrl_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2839142342
Short name T24
Test name
Test status
Simulation time 20566350979 ps
CPU time 3322.99 seconds
Started Aug 08 08:26:34 PM PDT 24
Finished Aug 08 09:21:58 PM PDT 24
Peak memory 610848 kb
Host smart-8755ad73-04c2-491e-bbe0-3db42902b673
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839142342 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.2839142342
Directory /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1465952168
Short name T1137
Test name
Test status
Simulation time 4702147911 ps
CPU time 602.08 seconds
Started Aug 08 08:27:19 PM PDT 24
Finished Aug 08 08:37:22 PM PDT 24
Peak memory 613476 kb
Host smart-23276f6c-1655-48a6-8077-90945b248060
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465952168 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.1465952168
Directory /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.4061865837
Short name T1263
Test name
Test status
Simulation time 2693711342 ps
CPU time 327.47 seconds
Started Aug 08 08:28:18 PM PDT 24
Finished Aug 08 08:33:48 PM PDT 24
Peak memory 612756 kb
Host smart-f3099c58-6a5d-4b60-9afe-9329e144bc06
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061865837 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.4061865837
Directory /workspace/1.chip_sw_sysrst_ctrl_inputs/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.5229817
Short name T1178
Test name
Test status
Simulation time 3926660676 ps
CPU time 355.29 seconds
Started Aug 08 08:28:03 PM PDT 24
Finished Aug 08 08:33:59 PM PDT 24
Peak memory 609224 kb
Host smart-57e7d542-1833-4bbc-99f2-4ce76c1dd89f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5229817 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.5229817
Directory /workspace/1.chip_sw_sysrst_ctrl_outputs/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1520865940
Short name T212
Test name
Test status
Simulation time 22669905672 ps
CPU time 1892.02 seconds
Started Aug 08 08:27:24 PM PDT 24
Finished Aug 08 08:58:56 PM PDT 24
Peak memory 614008 kb
Host smart-8a848cbc-ca86-422b-b39d-13742bc14840
User root
Command /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15208659
40 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.1520865940
Directory /workspace/1.chip_sw_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1545670321
Short name T40
Test name
Test status
Simulation time 5042901920 ps
CPU time 468.95 seconds
Started Aug 08 08:28:23 PM PDT 24
Finished Aug 08 08:36:12 PM PDT 24
Peak memory 609448 kb
Host smart-f94e22b0-5969-4874-86d0-006b7cef06aa
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545670321 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1545670321
Directory /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.603459859
Short name T215
Test name
Test status
Simulation time 13057900894 ps
CPU time 2544.43 seconds
Started Aug 08 08:21:59 PM PDT 24
Finished Aug 08 09:04:24 PM PDT 24
Peak memory 624632 kb
Host smart-14ac2430-5e57-4944-9b45-d52b2fc9c052
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=603459859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.603459859
Directory /workspace/1.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/1.chip_sw_uart_smoketest.2537753856
Short name T1228
Test name
Test status
Simulation time 3011259836 ps
CPU time 258.44 seconds
Started Aug 08 08:34:09 PM PDT 24
Finished Aug 08 08:38:28 PM PDT 24
Peak memory 614980 kb
Host smart-a65b506b-f119-416c-8192-d7d60902f09c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537753856 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_sw_uart_smoketest.2537753856
Directory /workspace/1.chip_sw_uart_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx.2972475473
Short name T400
Test name
Test status
Simulation time 4048533736 ps
CPU time 452.72 seconds
Started Aug 08 08:22:42 PM PDT 24
Finished Aug 08 08:30:15 PM PDT 24
Peak memory 623900 kb
Host smart-8896fc8f-ac7d-439e-b2eb-e797757e7677
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972475473 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.2972475473
Directory /workspace/1.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2397510230
Short name T1231
Test name
Test status
Simulation time 4099747228 ps
CPU time 857.67 seconds
Started Aug 08 08:22:14 PM PDT 24
Finished Aug 08 08:36:32 PM PDT 24
Peak memory 623504 kb
Host smart-c3ca06f2-50bd-4018-8812-4ac767c888c7
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397510230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx
_alt_clk_freq.2397510230
Directory /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3094392707
Short name T903
Test name
Test status
Simulation time 13122089011 ps
CPU time 1854.95 seconds
Started Aug 08 08:24:24 PM PDT 24
Finished Aug 08 08:55:20 PM PDT 24
Peak memory 618776 kb
Host smart-ef6efb57-3b3e-4acf-abf5-2e71f6518712
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094392707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.3094392707
Directory /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3645265964
Short name T1202
Test name
Test status
Simulation time 78219154592 ps
CPU time 14860.5 seconds
Started Aug 08 08:23:15 PM PDT 24
Finished Aug 09 12:30:57 AM PDT 24
Peak memory 636072 kb
Host smart-95e6bfc0-1896-429a-8880-59afa535ab99
User root
Command /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3645265964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.3645265964
Directory /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2599985961
Short name T873
Test name
Test status
Simulation time 4142901240 ps
CPU time 599.58 seconds
Started Aug 08 08:22:54 PM PDT 24
Finished Aug 08 08:32:54 PM PDT 24
Peak memory 623880 kb
Host smart-2dcf86bb-50a2-441a-8e30-bcee1e494d94
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599985961 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.2599985961
Directory /workspace/1.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2366100202
Short name T1332
Test name
Test status
Simulation time 3553869400 ps
CPU time 480.25 seconds
Started Aug 08 08:21:31 PM PDT 24
Finished Aug 08 08:29:31 PM PDT 24
Peak memory 623904 kb
Host smart-0bb75200-4f89-4e4a-854c-e171d7bcdc25
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366100202 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.2366100202
Directory /workspace/1.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2073275718
Short name T303
Test name
Test status
Simulation time 4990823832 ps
CPU time 730.31 seconds
Started Aug 08 08:23:33 PM PDT 24
Finished Aug 08 08:35:44 PM PDT 24
Peak memory 624136 kb
Host smart-aec0e473-09de-4b2e-bd1e-5e2e903c621f
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073275718 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.2073275718
Directory /workspace/1.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/1.chip_tap_straps_prod.1507393934
Short name T1134
Test name
Test status
Simulation time 14448127518 ps
CPU time 1678.08 seconds
Started Aug 08 08:32:04 PM PDT 24
Finished Aug 08 09:00:03 PM PDT 24
Peak memory 621004 kb
Host smart-74e719fd-f994-4d1a-8c87-850f64a833c0
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1507393934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.1507393934
Directory /workspace/1.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/1.chip_tap_straps_rma.2150458608
Short name T1127
Test name
Test status
Simulation time 5986118772 ps
CPU time 603.58 seconds
Started Aug 08 08:31:15 PM PDT 24
Finished Aug 08 08:41:19 PM PDT 24
Peak memory 632808 kb
Host smart-82775ede-9780-4ca2-90a2-3024f2180aba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150458608 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.2150458608
Directory /workspace/1.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/1.chip_tap_straps_testunlock0.261131103
Short name T76
Test name
Test status
Simulation time 7375804497 ps
CPU time 946.4 seconds
Started Aug 08 08:31:44 PM PDT 24
Finished Aug 08 08:47:31 PM PDT 24
Peak memory 624860 kb
Host smart-6b11395b-0b96-4c9e-aecb-dee219e84bdf
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261131103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.261131103
Directory /workspace/1.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_dev.916774424
Short name T958
Test name
Test status
Simulation time 14948936367 ps
CPU time 4053.33 seconds
Started Aug 08 08:37:45 PM PDT 24
Finished Aug 08 09:45:19 PM PDT 24
Peak memory 610264 kb
Host smart-44693ef3-1040-485d-9dcd-07cf6eae6afe
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916774424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rom_e2e_asm_init_dev.916774424
Directory /workspace/1.rom_e2e_asm_init_dev/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_prod.2641773739
Short name T1237
Test name
Test status
Simulation time 15878526335 ps
CPU time 4219.72 seconds
Started Aug 08 08:36:04 PM PDT 24
Finished Aug 08 09:46:24 PM PDT 24
Peak memory 610236 kb
Host smart-5ee7274e-342e-4f0f-b9c2-347ef415c3a3
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641773739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_
SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rom_e2e_asm_init_prod.2641773739
Directory /workspace/1.rom_e2e_asm_init_prod/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2718624345
Short name T1314
Test name
Test status
Simulation time 15766193118 ps
CPU time 3741.96 seconds
Started Aug 08 08:37:32 PM PDT 24
Finished Aug 08 09:39:55 PM PDT 24
Peak memory 610224 kb
Host smart-f84f68dd-2fd0-44f1-8c34-92019abbb265
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718624345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_e2e_asm_init_prod_end.2718624345
Directory /workspace/1.rom_e2e_asm_init_prod_end/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_rma.1949609444
Short name T1305
Test name
Test status
Simulation time 15016166924 ps
CPU time 3852.93 seconds
Started Aug 08 08:38:17 PM PDT 24
Finished Aug 08 09:42:30 PM PDT 24
Peak memory 610224 kb
Host smart-25361b0f-29e1-428a-ad7f-fb363e6b300b
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949609444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rom_e2e_asm_init_rma.1949609444
Directory /workspace/1.rom_e2e_asm_init_rma/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2037264124
Short name T1286
Test name
Test status
Simulation time 11547640563 ps
CPU time 3187.88 seconds
Started Aug 08 08:40:01 PM PDT 24
Finished Aug 08 09:33:10 PM PDT 24
Peak memory 610576 kb
Host smart-d2c3bef8-cb1a-4996-860f-6799582ee5cd
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037264124 -assert nopostproc +UVM_TESTNAME=chip_base_te
st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.rom_e2e_asm_init_test_unlocked0.2037264124
Directory /workspace/1.rom_e2e_asm_init_test_unlocked0/latest

Test location /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2109275465
Short name T49
Test name
Test status
Simulation time 14745176852 ps
CPU time 3688.87 seconds
Started Aug 08 08:38:09 PM PDT 24
Finished Aug 08 09:39:38 PM PDT 24
Peak memory 610256 kb
Host smart-37dc4a4d-852d-4303-a9d0-29c59b031e1c
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid
_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109275465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip
_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in
it_rom_ext_invalid_meas.2109275465
Directory /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.966203144
Short name T1141
Test name
Test status
Simulation time 15271167108 ps
CPU time 3784.82 seconds
Started Aug 08 08:38:05 PM PDT 24
Finished Aug 08 09:41:10 PM PDT 24
Peak memory 610052 kb
Host smart-290c1648-5d56-4bef-a8b9-8e27120590a9
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:
new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966203144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.966203144
Directory /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2987997323
Short name T939
Test name
Test status
Simulation time 15976085178 ps
CPU time 3262.21 seconds
Started Aug 08 08:37:57 PM PDT 24
Finished Aug 08 09:32:20 PM PDT 24
Peak memory 609912 kb
Host smart-c4cc65e6-f3e8-4e28-b699-1045d106d7a6
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas
:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987997323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext
_no_meas.2987997323
Directory /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.213504867
Short name T990
Test name
Test status
Simulation time 15278813930 ps
CPU time 3562.87 seconds
Started Aug 08 08:37:51 PM PDT 24
Finished Aug 08 09:37:14 PM PDT 24
Peak memory 611348 kb
Host smart-776d0a28-fdbf-4e90-a3f2-909f2f825417
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne
w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213504867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shut
down_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_s
hutdown_exception_c.213504867
Directory /workspace/1.rom_e2e_shutdown_exception_c/latest

Test location /workspace/coverage/default/1.rom_e2e_shutdown_output.1374996385
Short name T1123
Test name
Test status
Simulation time 27493540159 ps
CPU time 3758.4 seconds
Started Aug 08 08:36:48 PM PDT 24
Finished Aug 08 09:39:27 PM PDT 24
Peak memory 611720 kb
Host smart-c199daf3-4df0-4281-bfe7-b6b08f5a9ed5
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f
lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374996385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rom_e2e_shutdown_output.1374996385
Directory /workspace/1.rom_e2e_shutdown_output/latest

Test location /workspace/coverage/default/1.rom_e2e_smoke.4156062394
Short name T934
Test name
Test status
Simulation time 15150533426 ps
CPU time 3694.39 seconds
Started Aug 08 08:37:39 PM PDT 24
Finished Aug 08 09:39:14 PM PDT 24
Peak memory 609940 kb
Host smart-5fc1d84f-03cb-4904-99e2-9935b0f480ca
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img
_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to
p/hw/dv/tools/sim.tcl +ntb_random_seed=4156062394 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.4156062394
Directory /workspace/1.rom_e2e_smoke/latest

Test location /workspace/coverage/default/1.rom_e2e_static_critical.567187279
Short name T1136
Test name
Test status
Simulation time 17447493882 ps
CPU time 4534.47 seconds
Started Aug 08 08:38:29 PM PDT 24
Finished Aug 08 09:54:05 PM PDT 24
Peak memory 610144 kb
Host smart-1f5bf5c1-a101-4ab7-91a2-4d639de268fa
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul
es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567187279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.567187279
Directory /workspace/1.rom_e2e_static_critical/latest

Test location /workspace/coverage/default/1.rom_keymgr_functest.4207384030
Short name T1080
Test name
Test status
Simulation time 4655142488 ps
CPU time 608.99 seconds
Started Aug 08 08:33:48 PM PDT 24
Finished Aug 08 08:43:57 PM PDT 24
Peak memory 610308 kb
Host smart-43879134-0a17-4a93-9c44-14c3b1f0a733
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207384030 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.4207384030
Directory /workspace/1.rom_keymgr_functest/latest

Test location /workspace/coverage/default/1.rom_raw_unlock.4082996772
Short name T659
Test name
Test status
Simulation time 6523940847 ps
CPU time 284.5 seconds
Started Aug 08 08:33:41 PM PDT 24
Finished Aug 08 08:38:26 PM PDT 24
Peak memory 623740 kb
Host smart-694d09dd-19ef-4ff0-95cd-60e4a1f69267
User root
Command /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE
xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4082996772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.4082996772
Directory /workspace/1.rom_raw_unlock/latest

Test location /workspace/coverage/default/1.rom_volatile_raw_unlock.1962491407
Short name T1311
Test name
Test status
Simulation time 2164987162 ps
CPU time 110.69 seconds
Started Aug 08 08:35:52 PM PDT 24
Finished Aug 08 08:37:43 PM PDT 24
Peak memory 616988 kb
Host smart-232c0c59-cb54-413e-960f-fcdd4ca1b2d1
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1
+sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962491407 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.1962491407
Directory /workspace/1.rom_volatile_raw_unlock/latest

Test location /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.765332552
Short name T1116
Test name
Test status
Simulation time 6039166202 ps
CPU time 440.83 seconds
Started Aug 08 08:50:45 PM PDT 24
Finished Aug 08 08:58:06 PM PDT 24
Peak memory 621100 kb
Host smart-39c8d3c0-5006-4c39-a146-a2d3f5e4c55f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765332552 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.765332552
Directory /workspace/10.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1714219190
Short name T946
Test name
Test status
Simulation time 9227919456 ps
CPU time 1765.13 seconds
Started Aug 08 08:48:59 PM PDT 24
Finished Aug 08 09:18:25 PM PDT 24
Peak memory 624372 kb
Host smart-e501596d-6af7-415b-9160-de181e87785d
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1714219190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.1714219190
Directory /workspace/10.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2345155738
Short name T1091
Test name
Test status
Simulation time 3769925320 ps
CPU time 427.6 seconds
Started Aug 08 08:49:49 PM PDT 24
Finished Aug 08 08:56:56 PM PDT 24
Peak memory 618868 kb
Host smart-8da4033e-001c-4aef-899a-98a9d3931cf7
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345155738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2345155738
Directory /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1588743639
Short name T926
Test name
Test status
Simulation time 9756855103 ps
CPU time 832.13 seconds
Started Aug 08 08:48:46 PM PDT 24
Finished Aug 08 09:02:39 PM PDT 24
Peak memory 621136 kb
Host smart-020f2940-ab08-4375-b6fb-97c9a7341dc2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588743639 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.1588743639
Directory /workspace/11.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.517830157
Short name T916
Test name
Test status
Simulation time 4447486420 ps
CPU time 546.1 seconds
Started Aug 08 08:50:31 PM PDT 24
Finished Aug 08 08:59:38 PM PDT 24
Peak memory 624476 kb
Host smart-1f91a8f4-cea8-404b-86aa-530d797c86f9
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=517830157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.517830157
Directory /workspace/11.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.631847409
Short name T950
Test name
Test status
Simulation time 12260897845 ps
CPU time 852.69 seconds
Started Aug 08 08:50:54 PM PDT 24
Finished Aug 08 09:05:08 PM PDT 24
Peak memory 621136 kb
Host smart-9436de1d-38e7-4232-a474-12a7065b4b6c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631847409 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.631847409
Directory /workspace/12.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.4145538668
Short name T1227
Test name
Test status
Simulation time 4041445330 ps
CPU time 508.07 seconds
Started Aug 08 08:48:46 PM PDT 24
Finished Aug 08 08:57:15 PM PDT 24
Peak memory 624420 kb
Host smart-6e56c175-403a-4f55-a8e2-4cab8b6aa8ca
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=4145538668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.4145538668
Directory /workspace/12.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.366851686
Short name T733
Test name
Test status
Simulation time 4188164712 ps
CPU time 379.07 seconds
Started Aug 08 08:50:46 PM PDT 24
Finished Aug 08 08:57:05 PM PDT 24
Peak memory 648760 kb
Host smart-156966e7-ad91-4a23-8f3a-e75124d05bb3
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366851686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_s
w_alert_handler_lpg_sleep_mode_alerts.366851686
Directory /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/13.chip_sw_all_escalation_resets.3279831821
Short name T700
Test name
Test status
Simulation time 5968653346 ps
CPU time 687.76 seconds
Started Aug 08 08:50:05 PM PDT 24
Finished Aug 08 09:01:33 PM PDT 24
Peak memory 619900 kb
Host smart-7811bb96-04fb-4a92-94ef-130af8c7b906
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3279831821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.3279831821
Directory /workspace/13.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1239794256
Short name T1056
Test name
Test status
Simulation time 13872872930 ps
CPU time 1224.83 seconds
Started Aug 08 08:49:37 PM PDT 24
Finished Aug 08 09:10:02 PM PDT 24
Peak memory 624800 kb
Host smart-fe48c582-cfd4-4368-b914-648e9ef01d60
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239794256 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.1239794256
Directory /workspace/13.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3999429506
Short name T1092
Test name
Test status
Simulation time 8212117880 ps
CPU time 1422.58 seconds
Started Aug 08 08:50:17 PM PDT 24
Finished Aug 08 09:14:00 PM PDT 24
Peak memory 624324 kb
Host smart-57c58e4a-6647-4ff3-a57f-44af2b00bf41
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3999429506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.3999429506
Directory /workspace/13.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1681139540
Short name T1102
Test name
Test status
Simulation time 9627519382 ps
CPU time 1079.19 seconds
Started Aug 08 08:50:14 PM PDT 24
Finished Aug 08 09:08:14 PM PDT 24
Peak memory 624744 kb
Host smart-abcef4c7-77a8-454a-9809-564197aad55e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681139540 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.1681139540
Directory /workspace/14.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3552666249
Short name T988
Test name
Test status
Simulation time 4302968916 ps
CPU time 529.81 seconds
Started Aug 08 08:49:51 PM PDT 24
Finished Aug 08 08:58:41 PM PDT 24
Peak memory 624628 kb
Host smart-73a34e96-370a-4265-9e3c-f32d6882fe78
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3552666249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.3552666249
Directory /workspace/14.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2149413540
Short name T1333
Test name
Test status
Simulation time 4786299432 ps
CPU time 675.49 seconds
Started Aug 08 08:50:44 PM PDT 24
Finished Aug 08 09:02:01 PM PDT 24
Peak memory 623256 kb
Host smart-7acf940a-7baf-4b4e-af66-ee9c26386928
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2149413540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.2149413540
Directory /workspace/15.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2417256734
Short name T1214
Test name
Test status
Simulation time 3178213814 ps
CPU time 351.64 seconds
Started Aug 08 08:52:14 PM PDT 24
Finished Aug 08 08:58:06 PM PDT 24
Peak memory 618976 kb
Host smart-bd6c3ebe-00f9-4dfc-b2dd-81a00bf5bee2
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417256734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2417256734
Directory /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1383031014
Short name T1302
Test name
Test status
Simulation time 12733148196 ps
CPU time 2122.95 seconds
Started Aug 08 08:51:09 PM PDT 24
Finished Aug 08 09:26:33 PM PDT 24
Peak memory 622272 kb
Host smart-fbcbcf79-eadf-46e3-a568-f52106d4ac3d
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1383031014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.1383031014
Directory /workspace/16.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1556114521
Short name T1035
Test name
Test status
Simulation time 13125303338 ps
CPU time 2438.48 seconds
Started Aug 08 08:52:12 PM PDT 24
Finished Aug 08 09:32:51 PM PDT 24
Peak memory 624384 kb
Host smart-5939e42c-36d5-487c-b7f1-e10e5dc0d1f1
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1556114521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.1556114521
Directory /workspace/17.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1601589177
Short name T681
Test name
Test status
Simulation time 3762757528 ps
CPU time 317.15 seconds
Started Aug 08 08:51:21 PM PDT 24
Finished Aug 08 08:56:38 PM PDT 24
Peak memory 648756 kb
Host smart-02d41ebd-2d10-4035-9e79-564dac67e7b9
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601589177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1601589177
Directory /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.513478214
Short name T1032
Test name
Test status
Simulation time 12243123812 ps
CPU time 2143.25 seconds
Started Aug 08 08:50:53 PM PDT 24
Finished Aug 08 09:26:37 PM PDT 24
Peak memory 624556 kb
Host smart-5bf283c8-66b4-4006-bac0-7ee3f34934ef
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=513478214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.513478214
Directory /workspace/18.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/19.chip_sw_all_escalation_resets.1531678895
Short name T701
Test name
Test status
Simulation time 5929568760 ps
CPU time 486.1 seconds
Started Aug 08 08:51:37 PM PDT 24
Finished Aug 08 08:59:43 PM PDT 24
Peak memory 619820 kb
Host smart-8d3b4570-0885-4c96-a322-129379cc73a4
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1531678895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.1531678895
Directory /workspace/19.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1875894333
Short name T986
Test name
Test status
Simulation time 4336290120 ps
CPU time 598.82 seconds
Started Aug 08 08:50:27 PM PDT 24
Finished Aug 08 09:00:26 PM PDT 24
Peak memory 623216 kb
Host smart-61599485-e3b9-4996-8836-812416ce7bd7
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1875894333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.1875894333
Directory /workspace/19.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/2.chip_jtag_mem_access.3889709380
Short name T84
Test name
Test status
Simulation time 13805195320 ps
CPU time 1580.77 seconds
Started Aug 08 08:36:07 PM PDT 24
Finished Aug 08 09:02:29 PM PDT 24
Peak memory 607952 kb
Host smart-8cc72ec8-2caf-4cd1-9e6a-8235f78b48e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889709380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_
mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.3
889709380
Directory /workspace/2.chip_jtag_mem_access/latest

Test location /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3425970350
Short name T410
Test name
Test status
Simulation time 3663060072 ps
CPU time 442.72 seconds
Started Aug 08 08:43:55 PM PDT 24
Finished Aug 08 08:51:18 PM PDT 24
Peak memory 619688 kb
Host smart-475d7e31-bab3-4bc9-9006-a32f2bc318bd
User root
Command /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3
425970350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.3425970350
Directory /workspace/2.chip_rv_dm_ndm_reset_req/latest

Test location /workspace/coverage/default/2.chip_sival_flash_info_access.189852476
Short name T1020
Test name
Test status
Simulation time 3385790084 ps
CPU time 292.12 seconds
Started Aug 08 08:35:13 PM PDT 24
Finished Aug 08 08:40:05 PM PDT 24
Peak memory 608728 kb
Host smart-b0a5b83d-6798-47e4-9614-cde999ce14db
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=189852476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.189852476
Directory /workspace/2.chip_sival_flash_info_access/latest

Test location /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3247603381
Short name T334
Test name
Test status
Simulation time 19216667952 ps
CPU time 381.22 seconds
Started Aug 08 08:38:10 PM PDT 24
Finished Aug 08 08:44:31 PM PDT 24
Peak memory 619712 kb
Host smart-1a80655e-4aac-4031-8e28-dd4e712cd055
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3247603381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3247603381
Directory /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_aes_enc.1262843245
Short name T1059
Test name
Test status
Simulation time 3026349630 ps
CPU time 312.78 seconds
Started Aug 08 08:39:57 PM PDT 24
Finished Aug 08 08:45:10 PM PDT 24
Peak memory 609480 kb
Host smart-a98d9e60-04b7-4030-b8ce-8f4bb2697b19
User root
Command /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262843245 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.1262843245
Directory /workspace/2.chip_sw_aes_enc/latest

Test location /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3863135746
Short name T1287
Test name
Test status
Simulation time 3577851095 ps
CPU time 364.96 seconds
Started Aug 08 08:37:53 PM PDT 24
Finished Aug 08 08:43:58 PM PDT 24
Peak memory 609540 kb
Host smart-98845367-9c77-4514-8e02-46040e6b8f45
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863
135746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.3863135746
Directory /workspace/2.chip_sw_aes_enc_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3141885032
Short name T1291
Test name
Test status
Simulation time 2937849217 ps
CPU time 307.84 seconds
Started Aug 08 08:44:06 PM PDT 24
Finished Aug 08 08:49:14 PM PDT 24
Peak memory 609712 kb
Host smart-890ba3f7-4c41-4afd-b4d8-d82ae7e83a32
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3141885032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.3141885032
Directory /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_aes_entropy.187916995
Short name T295
Test name
Test status
Simulation time 2878883800 ps
CPU time 233.8 seconds
Started Aug 08 08:40:30 PM PDT 24
Finished Aug 08 08:44:25 PM PDT 24
Peak memory 609580 kb
Host smart-ebaf8844-0d58-424e-af06-1dcba0fc2dbf
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187916995 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.187916995
Directory /workspace/2.chip_sw_aes_entropy/latest

Test location /workspace/coverage/default/2.chip_sw_aes_idle.637983062
Short name T1004
Test name
Test status
Simulation time 3333780896 ps
CPU time 241.97 seconds
Started Aug 08 08:39:02 PM PDT 24
Finished Aug 08 08:43:04 PM PDT 24
Peak memory 609592 kb
Host smart-2a966b6d-59cc-4aad-8cf3-c08b1497c25b
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637983062 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.637983062
Directory /workspace/2.chip_sw_aes_idle/latest

Test location /workspace/coverage/default/2.chip_sw_aes_masking_off.762364882
Short name T609
Test name
Test status
Simulation time 3749008840 ps
CPU time 374.06 seconds
Started Aug 08 08:38:15 PM PDT 24
Finished Aug 08 08:44:29 PM PDT 24
Peak memory 609372 kb
Host smart-8b679079-e78d-4cb2-a7e7-cae48d558d56
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762364882 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.762364882
Directory /workspace/2.chip_sw_aes_masking_off/latest

Test location /workspace/coverage/default/2.chip_sw_aes_smoketest.4260813121
Short name T1016
Test name
Test status
Simulation time 2483908712 ps
CPU time 276.48 seconds
Started Aug 08 08:47:10 PM PDT 24
Finished Aug 08 08:51:47 PM PDT 24
Peak memory 609640 kb
Host smart-db76cc4d-3818-4442-8101-a2db0ec1e0cc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260813121 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_aes_smoketest.4260813121
Directory /workspace/2.chip_sw_aes_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_entropy.1007612297
Short name T1093
Test name
Test status
Simulation time 2913458331 ps
CPU time 264.11 seconds
Started Aug 08 08:39:43 PM PDT 24
Finished Aug 08 08:44:08 PM PDT 24
Peak memory 609492 kb
Host smart-dc072d31-5dc5-48be-a1c4-d7f0e3fd5ad9
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1007612297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.1007612297
Directory /workspace/2.chip_sw_alert_handler_entropy/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1914026247
Short name T1328
Test name
Test status
Simulation time 4443534188 ps
CPU time 633.56 seconds
Started Aug 08 08:39:28 PM PDT 24
Finished Aug 08 08:50:02 PM PDT 24
Peak memory 619636 kb
Host smart-c3c7590a-1a96-4bba-86ed-792e93461d5d
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=1914026247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.1914026247
Directory /workspace/2.chip_sw_alert_handler_escalation/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3472520611
Short name T1117
Test name
Test status
Simulation time 6721194448 ps
CPU time 1611.05 seconds
Started Aug 08 08:42:26 PM PDT 24
Finished Aug 08 09:09:18 PM PDT 24
Peak memory 609976 kb
Host smart-7c5288e8-da9c-42b4-9688-e54ecce393e3
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3472520611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.3472520611
Directory /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1936993817
Short name T213
Test name
Test status
Simulation time 8223997032 ps
CPU time 1836.7 seconds
Started Aug 08 08:40:07 PM PDT 24
Finished Aug 08 09:10:44 PM PDT 24
Peak memory 609996 kb
Host smart-e7b4dbea-6dd1-4e87-9ec1-d8e2044a3a3f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1936993817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg
le.1936993817
Directory /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.217061778
Short name T1316
Test name
Test status
Simulation time 9516732790 ps
CPU time 1283.59 seconds
Started Aug 08 08:39:32 PM PDT 24
Finished Aug 08 09:00:56 PM PDT 24
Peak memory 610756 kb
Host smart-f1224bce-9fa5-4159-a766-9dbc561b3f1b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler
_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217061778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand
ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.chip_sw_alert_handler_lpg_sleep_mode_pings.217061778
Directory /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.919063567
Short name T1267
Test name
Test status
Simulation time 8369160516 ps
CPU time 1378.99 seconds
Started Aug 08 08:40:15 PM PDT 24
Finished Aug 08 09:03:15 PM PDT 24
Peak memory 609780 kb
Host smart-31af6182-e7ad-4c01-a8b9-9192557237c5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=919063567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.919063567
Directory /workspace/2.chip_sw_alert_handler_ping_ok/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1776782730
Short name T258
Test name
Test status
Simulation time 5213252500 ps
CPU time 588.7 seconds
Started Aug 08 08:39:32 PM PDT 24
Finished Aug 08 08:49:21 PM PDT 24
Peak memory 610060 kb
Host smart-430538a1-e85a-41ec-9a94-10da10524e5f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1776782730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.1776782730
Directory /workspace/2.chip_sw_alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1769686533
Short name T93
Test name
Test status
Simulation time 256249925256 ps
CPU time 13061.2 seconds
Started Aug 08 08:39:52 PM PDT 24
Finished Aug 09 12:17:35 AM PDT 24
Peak memory 610776 kb
Host smart-84682a28-c1ea-42f4-8997-d1e97bee4ff3
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769686533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1769686533
Directory /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location /workspace/coverage/default/2.chip_sw_alert_test.330498597
Short name T67
Test name
Test status
Simulation time 3609938630 ps
CPU time 242.58 seconds
Started Aug 08 08:39:52 PM PDT 24
Finished Aug 08 08:43:54 PM PDT 24
Peak memory 609292 kb
Host smart-9dc349e9-6767-412b-9359-0ddfe097ffcf
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330498597 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.chip_sw_alert_test.330498597
Directory /workspace/2.chip_sw_alert_test/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_irq.1539968576
Short name T1271
Test name
Test status
Simulation time 4290272600 ps
CPU time 502.62 seconds
Started Aug 08 08:38:54 PM PDT 24
Finished Aug 08 08:47:17 PM PDT 24
Peak memory 609248 kb
Host smart-1566b196-3c81-45f9-ae4f-28373463d2c9
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539968576 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.1539968576
Directory /workspace/2.chip_sw_aon_timer_irq/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.4258612198
Short name T1254
Test name
Test status
Simulation time 6997903030 ps
CPU time 441.33 seconds
Started Aug 08 08:37:21 PM PDT 24
Finished Aug 08 08:44:42 PM PDT 24
Peak memory 609412 kb
Host smart-6cf1b4fa-3f33-43f7-b283-40aac5feb55d
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4258612198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.4258612198
Directory /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.668001222
Short name T980
Test name
Test status
Simulation time 3582883880 ps
CPU time 282.89 seconds
Started Aug 08 08:46:07 PM PDT 24
Finished Aug 08 08:50:50 PM PDT 24
Peak memory 608456 kb
Host smart-98f714c6-0f20-4ed0-9602-2dc8b41a729f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668001222 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_aon_timer_smoketest.668001222
Directory /workspace/2.chip_sw_aon_timer_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.765860071
Short name T1148
Test name
Test status
Simulation time 10400446400 ps
CPU time 1025.61 seconds
Started Aug 08 08:37:38 PM PDT 24
Finished Aug 08 08:54:44 PM PDT 24
Peak memory 609624 kb
Host smart-21cca4ee-f885-4fa6-a932-2bc8204cad4d
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
765860071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.765860071
Directory /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.17190291
Short name T954
Test name
Test status
Simulation time 5628432400 ps
CPU time 541.11 seconds
Started Aug 08 08:38:05 PM PDT 24
Finished Aug 08 08:47:06 PM PDT 24
Peak memory 610576 kb
Host smart-2a6da0ad-4bde-4d59-b8b5-efbd7a3e0c31
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=17190291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.17190291
Directory /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location /workspace/coverage/default/2.chip_sw_ast_clk_outputs.250626301
Short name T125
Test name
Test status
Simulation time 8443222536 ps
CPU time 1058.56 seconds
Started Aug 08 08:43:04 PM PDT 24
Finished Aug 08 09:00:43 PM PDT 24
Peak memory 617020 kb
Host smart-337013a4-307e-42ae-925d-16c728eff0fd
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250626301 -assert nopos
tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.250626301
Directory /workspace/2.chip_sw_ast_clk_outputs/latest

Test location /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3532498779
Short name T118
Test name
Test status
Simulation time 24015921144 ps
CPU time 3257.94 seconds
Started Aug 08 08:45:01 PM PDT 24
Finished Aug 08 09:39:20 PM PDT 24
Peak memory 611152 kb
Host smart-bde16c91-3162-45a2-ac72-81a03bcfc955
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532498779
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.3532498779
Directory /workspace/2.chip_sw_ast_clk_rst_inputs/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.395442116
Short name T1288
Test name
Test status
Simulation time 10780910062 ps
CPU time 765.22 seconds
Started Aug 08 08:43:42 PM PDT 24
Finished Aug 08 08:56:28 PM PDT 24
Peak memory 621220 kb
Host smart-031736ad-ba43-4ea2-8a84-08b437d20649
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=395442116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.395442116
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4020191736
Short name T859
Test name
Test status
Simulation time 4096514898 ps
CPU time 515.52 seconds
Started Aug 08 08:42:13 PM PDT 24
Finished Aug 08 08:50:49 PM PDT 24
Peak memory 612052 kb
Host smart-ec19c035-3dd8-44bc-951d-5929c1a25eb2
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020191736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_dev.4020191736
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3035526102
Short name T989
Test name
Test status
Simulation time 3800349370 ps
CPU time 628.54 seconds
Started Aug 08 08:42:59 PM PDT 24
Finished Aug 08 08:53:28 PM PDT 24
Peak memory 612144 kb
Host smart-835b48c7-b375-4123-868f-441f5d4da98b
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035526102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_rma.3035526102
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.510243002
Short name T858
Test name
Test status
Simulation time 3660827512 ps
CPU time 624.89 seconds
Started Aug 08 08:41:57 PM PDT 24
Finished Aug 08 08:52:22 PM PDT 24
Peak memory 612168 kb
Host smart-f147b16c-b9ee-44fa-9943-d481ef1e0126
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510243002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM
_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.510243002
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2368051421
Short name T1310
Test name
Test status
Simulation time 4897444610 ps
CPU time 643.07 seconds
Started Aug 08 08:42:28 PM PDT 24
Finished Aug 08 08:53:12 PM PDT 24
Peak memory 612144 kb
Host smart-cf6e9ce5-ea33-46dc-8f82-c24d8f68dcb1
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368051421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_dev.2368051421
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1457103705
Short name T122
Test name
Test status
Simulation time 5354892902 ps
CPU time 616.26 seconds
Started Aug 08 08:42:33 PM PDT 24
Finished Aug 08 08:52:49 PM PDT 24
Peak memory 612924 kb
Host smart-3ca9d4c5-06e3-44e8-b4c4-28d1883b68a0
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457103705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_rma.1457103705
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3916649323
Short name T1013
Test name
Test status
Simulation time 4002089798 ps
CPU time 783.9 seconds
Started Aug 08 08:43:18 PM PDT 24
Finished Aug 08 08:56:22 PM PDT 24
Peak memory 612180 kb
Host smart-f6f7bcab-a241-4a33-b358-2e44cb42015e
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916649323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3916649323
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_jitter.104153607
Short name T1129
Test name
Test status
Simulation time 2765235383 ps
CPU time 201.25 seconds
Started Aug 08 08:42:37 PM PDT 24
Finished Aug 08 08:45:58 PM PDT 24
Peak memory 609320 kb
Host smart-427f20cc-1168-4d21-8339-d9a16f8894c9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104153607 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_clkmgr_jitter.104153607
Directory /workspace/2.chip_sw_clkmgr_jitter/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3272859153
Short name T1154
Test name
Test status
Simulation time 3654675140 ps
CPU time 336.56 seconds
Started Aug 08 08:42:19 PM PDT 24
Finished Aug 08 08:47:56 PM PDT 24
Peak memory 609536 kb
Host smart-b952a3f5-139e-4a51-a8d7-efbfb39b947a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272859153 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.3272859153
Directory /workspace/2.chip_sw_clkmgr_jitter_frequency/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.4140601694
Short name T885
Test name
Test status
Simulation time 3234103394 ps
CPU time 227.28 seconds
Started Aug 08 08:43:51 PM PDT 24
Finished Aug 08 08:47:39 PM PDT 24
Peak memory 609664 kb
Host smart-1c0ccaf3-75b6-49ef-9a7f-27fcb7a00a99
User root
Command /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140601694 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.4140601694
Directory /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.876555822
Short name T170
Test name
Test status
Simulation time 3475686888 ps
CPU time 361.19 seconds
Started Aug 08 08:42:04 PM PDT 24
Finished Aug 08 08:48:05 PM PDT 24
Peak memory 609340 kb
Host smart-4fcbf763-cc13-44a1-8f25-30552e11a5b4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876555822 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.876555822
Directory /workspace/2.chip_sw_clkmgr_off_aes_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2899623241
Short name T940
Test name
Test status
Simulation time 4436919470 ps
CPU time 382.74 seconds
Started Aug 08 08:42:41 PM PDT 24
Finished Aug 08 08:49:04 PM PDT 24
Peak memory 610388 kb
Host smart-6d6b5e3d-2579-4ec3-91f5-56822f88d87b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899623241 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.2899623241
Directory /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3062807887
Short name T1249
Test name
Test status
Simulation time 4827000528 ps
CPU time 374.44 seconds
Started Aug 08 08:41:58 PM PDT 24
Finished Aug 08 08:48:13 PM PDT 24
Peak memory 610400 kb
Host smart-d50f8c64-7472-45b9-afd1-7980d2c8d4e9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062807887 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.3062807887
Directory /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.728546468
Short name T1325
Test name
Test status
Simulation time 4632394988 ps
CPU time 473.15 seconds
Started Aug 08 08:43:14 PM PDT 24
Finished Aug 08 08:51:08 PM PDT 24
Peak memory 610440 kb
Host smart-9a87f84c-1c93-4982-8466-f60a1a2a64c1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728546468 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.728546468
Directory /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1560111369
Short name T288
Test name
Test status
Simulation time 12268220420 ps
CPU time 1085.52 seconds
Started Aug 08 08:42:20 PM PDT 24
Finished Aug 08 09:00:25 PM PDT 24
Peak memory 610528 kb
Host smart-187c7f8a-acb0-4481-8ab9-0e3534cfbb36
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560111369
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.1560111369
Directory /workspace/2.chip_sw_clkmgr_off_peri/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1480913453
Short name T266
Test name
Test status
Simulation time 3648834080 ps
CPU time 569.16 seconds
Started Aug 08 08:43:02 PM PDT 24
Finished Aug 08 08:52:31 PM PDT 24
Peak memory 609784 kb
Host smart-b2db381d-66d7-4fcc-a8f8-455bdd6ce1fc
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480913453 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.1480913453
Directory /workspace/2.chip_sw_clkmgr_reset_frequency/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1222111054
Short name T379
Test name
Test status
Simulation time 4392074638 ps
CPU time 712.52 seconds
Started Aug 08 08:44:28 PM PDT 24
Finished Aug 08 08:56:21 PM PDT 24
Peak memory 610236 kb
Host smart-a7d63b55-fd69-44bb-b390-502daeec064d
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222111054 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.1222111054
Directory /workspace/2.chip_sw_clkmgr_sleep_frequency/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3425105729
Short name T910
Test name
Test status
Simulation time 2563586592 ps
CPU time 196.78 seconds
Started Aug 08 08:45:38 PM PDT 24
Finished Aug 08 08:48:54 PM PDT 24
Peak memory 609752 kb
Host smart-36366164-d27f-4887-83a1-65d03cff9db8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425105729 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.chip_sw_clkmgr_smoketest.3425105729
Directory /workspace/2.chip_sw_clkmgr_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1566449530
Short name T1061
Test name
Test status
Simulation time 19646293928 ps
CPU time 4739.78 seconds
Started Aug 08 08:39:01 PM PDT 24
Finished Aug 08 09:58:02 PM PDT 24
Peak memory 610336 kb
Host smart-704333bf-a4b7-4cbf-aeb1-4366d7fb0a09
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566449530 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.1566449530
Directory /workspace/2.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3186942963
Short name T117
Test name
Test status
Simulation time 21400592559 ps
CPU time 3716.63 seconds
Started Aug 08 08:44:50 PM PDT 24
Finished Aug 08 09:46:47 PM PDT 24
Peak memory 610028 kb
Host smart-1b3eb83b-cb0c-4115-add8-46c989e0c5c4
User root
Command /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_
cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3186942963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.3186942963
Directory /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1727615454
Short name T189
Test name
Test status
Simulation time 3813792184 ps
CPU time 300.41 seconds
Started Aug 08 08:40:27 PM PDT 24
Finished Aug 08 08:45:27 PM PDT 24
Peak memory 610536 kb
Host smart-c20c306c-51c1-4678-8126-39062d0392c6
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17276
15454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.1727615454
Directory /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_kat_test.2945392807
Short name T1270
Test name
Test status
Simulation time 2749420376 ps
CPU time 320.91 seconds
Started Aug 08 08:39:15 PM PDT 24
Finished Aug 08 08:44:36 PM PDT 24
Peak memory 609644 kb
Host smart-147fb494-da8f-4aee-a82d-93881de4fc02
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945392807 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.2945392807
Directory /workspace/2.chip_sw_csrng_kat_test/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.829025137
Short name T1018
Test name
Test status
Simulation time 5888710999 ps
CPU time 854.13 seconds
Started Aug 08 08:39:59 PM PDT 24
Finished Aug 08 08:54:13 PM PDT 24
Peak memory 610784 kb
Host smart-ee5b7488-8c9b-4244-a471-4a2165aa85a7
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima
ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829025137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l
c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrn
g_lc_hw_debug_en_test.829025137
Directory /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_smoketest.2416386422
Short name T935
Test name
Test status
Simulation time 2426232068 ps
CPU time 258.06 seconds
Started Aug 08 08:45:32 PM PDT 24
Finished Aug 08 08:49:50 PM PDT 24
Peak memory 609292 kb
Host smart-e923a279-aa4f-4d20-8f2c-d5065a0451e4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416386422 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.chip_sw_csrng_smoketest.2416386422
Directory /workspace/2.chip_sw_csrng_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_data_integrity_escalation.1010603933
Short name T250
Test name
Test status
Simulation time 5956023160 ps
CPU time 669.44 seconds
Started Aug 08 08:36:42 PM PDT 24
Finished Aug 08 08:47:52 PM PDT 24
Peak memory 611068 kb
Host smart-7b7df361-86da-4713-8b50-8ac0bb4a5803
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1010603933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.1010603933
Directory /workspace/2.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/2.chip_sw_edn_auto_mode.3670504900
Short name T931
Test name
Test status
Simulation time 4843752620 ps
CPU time 995.13 seconds
Started Aug 08 08:39:17 PM PDT 24
Finished Aug 08 08:55:52 PM PDT 24
Peak memory 610048 kb
Host smart-0815594c-16b2-46d8-a177-2a158dc05c2b
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670504900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_
auto_mode.3670504900
Directory /workspace/2.chip_sw_edn_auto_mode/latest

Test location /workspace/coverage/default/2.chip_sw_edn_boot_mode.2454181580
Short name T610
Test name
Test status
Simulation time 2902281370 ps
CPU time 616.46 seconds
Started Aug 08 08:39:21 PM PDT 24
Finished Aug 08 08:49:38 PM PDT 24
Peak memory 609792 kb
Host smart-8badacff-82cf-42e4-bf83-b8dd5c148a71
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_
build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454181580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_
boot_mode.2454181580
Directory /workspace/2.chip_sw_edn_boot_mode/latest

Test location /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1132830159
Short name T416
Test name
Test status
Simulation time 7103755568 ps
CPU time 1490.26 seconds
Started Aug 08 08:41:05 PM PDT 24
Finished Aug 08 09:05:56 PM PDT 24
Peak memory 610892 kb
Host smart-2bf53c57-51fb-422a-84d9-d2951a2d3c50
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed
n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1132830159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.1132830159
Directory /workspace/2.chip_sw_edn_entropy_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2419460462
Short name T1282
Test name
Test status
Simulation time 6798869102 ps
CPU time 981.94 seconds
Started Aug 08 08:40:27 PM PDT 24
Finished Aug 08 08:56:49 PM PDT 24
Peak memory 609992 kb
Host smart-407cb888-2578-4c88-8733-8c386e3cbf5c
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e
ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419460462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.2419460462
Directory /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest

Test location /workspace/coverage/default/2.chip_sw_edn_kat.164634849
Short name T879
Test name
Test status
Simulation time 3045265820 ps
CPU time 596.01 seconds
Started Aug 08 08:40:13 PM PDT 24
Finished Aug 08 08:50:10 PM PDT 24
Peak memory 615228 kb
Host smart-b4dd0652-e2f9-4a92-a2f9-2a4f2beeaa16
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3
+accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164634849 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_edn_kat.164634849
Directory /workspace/2.chip_sw_edn_kat/latest

Test location /workspace/coverage/default/2.chip_sw_edn_sw_mode.3337391227
Short name T391
Test name
Test status
Simulation time 7216490272 ps
CPU time 1455.87 seconds
Started Aug 08 08:40:12 PM PDT 24
Finished Aug 08 09:04:28 PM PDT 24
Peak memory 609828 kb
Host smart-064649a1-e7b3-43ec-9205-221582995465
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337391227 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.3337391227
Directory /workspace/2.chip_sw_edn_sw_mode/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1627246901
Short name T862
Test name
Test status
Simulation time 3004958528 ps
CPU time 200.71 seconds
Started Aug 08 08:40:54 PM PDT 24
Finished Aug 08 08:44:15 PM PDT 24
Peak memory 609448 kb
Host smart-a083cc1d-bb93-4648-8f2b-8ff18d7fa287
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16
27246901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.1627246901
Directory /workspace/2.chip_sw_entropy_src_ast_rng_req/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2774913571
Short name T313
Test name
Test status
Simulation time 5679350630 ps
CPU time 1285.61 seconds
Started Aug 08 08:40:44 PM PDT 24
Finished Aug 08 09:02:10 PM PDT 24
Peak memory 609332 kb
Host smart-c208b83c-8740-4d2d-acf8-811945d5d6c8
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_
csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2774913571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.2774913571
Directory /workspace/2.chip_sw_entropy_src_csrng/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.500113978
Short name T955
Test name
Test status
Simulation time 3016632656 ps
CPU time 270.38 seconds
Started Aug 08 08:38:42 PM PDT 24
Finished Aug 08 08:43:12 PM PDT 24
Peak memory 609432 kb
Host smart-96a9481e-6d3c-426b-aad1-f4f0325f05f8
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500113978
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.500113978
Directory /workspace/2.chip_sw_entropy_src_kat_test/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.249188
Short name T878
Test name
Test status
Simulation time 3849707696 ps
CPU time 516.77 seconds
Started Aug 08 08:46:48 PM PDT 24
Finished Aug 08 08:55:25 PM PDT 24
Peak memory 608440 kb
Host smart-ece159da-1b9a-4f62-854f-d2fe7503d455
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=249188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.249188
Directory /workspace/2.chip_sw_entropy_src_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_example_concurrency.4211622055
Short name T884
Test name
Test status
Simulation time 2718813736 ps
CPU time 286.73 seconds
Started Aug 08 08:35:10 PM PDT 24
Finished Aug 08 08:39:57 PM PDT 24
Peak memory 609396 kb
Host smart-be064f33-444e-4e98-9509-988d7ba86c86
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211622055 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.chip_sw_example_concurrency.4211622055
Directory /workspace/2.chip_sw_example_concurrency/latest

Test location /workspace/coverage/default/2.chip_sw_example_flash.1818686411
Short name T1163
Test name
Test status
Simulation time 3307248802 ps
CPU time 259.06 seconds
Started Aug 08 08:34:20 PM PDT 24
Finished Aug 08 08:38:39 PM PDT 24
Peak memory 609632 kb
Host smart-58e286e9-7f89-44aa-9b4c-be02babbb27c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818686411 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_example_flash.1818686411
Directory /workspace/2.chip_sw_example_flash/latest

Test location /workspace/coverage/default/2.chip_sw_example_manufacturer.4197115958
Short name T880
Test name
Test status
Simulation time 2828494234 ps
CPU time 185.68 seconds
Started Aug 08 08:37:08 PM PDT 24
Finished Aug 08 08:40:14 PM PDT 24
Peak memory 609536 kb
Host smart-1aad7750-2afe-41f2-9ffc-19e27df87b6b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197115958 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_example_manufacturer.4197115958
Directory /workspace/2.chip_sw_example_manufacturer/latest

Test location /workspace/coverage/default/2.chip_sw_example_rom.3178476551
Short name T1213
Test name
Test status
Simulation time 2514253888 ps
CPU time 114.92 seconds
Started Aug 08 08:36:01 PM PDT 24
Finished Aug 08 08:37:56 PM PDT 24
Peak memory 609228 kb
Host smart-0c00136f-43a1-48c9-95c2-1ac1cb4a930d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178476551 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_example_rom.3178476551
Directory /workspace/2.chip_sw_example_rom/latest

Test location /workspace/coverage/default/2.chip_sw_flash_crash_alert.1877773146
Short name T36
Test name
Test status
Simulation time 4635229320 ps
CPU time 700.6 seconds
Started Aug 08 08:44:09 PM PDT 24
Finished Aug 08 08:55:50 PM PDT 24
Peak memory 610936 kb
Host smart-a51ed945-d2a4-457a-8f9b-217cb3325ee3
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:
new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=1877773146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.1877773146
Directory /workspace/2.chip_sw_flash_crash_alert/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3984809435
Short name T1204
Test name
Test status
Simulation time 5572795860 ps
CPU time 979.81 seconds
Started Aug 08 08:35:44 PM PDT 24
Finished Aug 08 08:52:04 PM PDT 24
Peak memory 610056 kb
Host smart-ee152362-dc91-46a5-af9f-3768b37aa0ad
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984809435 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.chip_sw_flash_ctrl_access.3984809435
Directory /workspace/2.chip_sw_flash_ctrl_access/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1784396811
Short name T1276
Test name
Test status
Simulation time 6473994965 ps
CPU time 1170.36 seconds
Started Aug 08 08:35:19 PM PDT 24
Finished Aug 08 08:54:50 PM PDT 24
Peak memory 610160 kb
Host smart-3d5ff96a-f86f-4c4f-96a6-bfeed994b9c9
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784396811 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.1784396811
Directory /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1641693793
Short name T861
Test name
Test status
Simulation time 7652358265 ps
CPU time 1090.73 seconds
Started Aug 08 08:44:07 PM PDT 24
Finished Aug 08 09:02:18 PM PDT 24
Peak memory 608956 kb
Host smart-b5420e04-f020-4794-9a3e-ef86c7c0cdb0
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641693793 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1641693793
Directory /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3620644770
Short name T1112
Test name
Test status
Simulation time 5691764646 ps
CPU time 1101.22 seconds
Started Aug 08 08:36:32 PM PDT 24
Finished Aug 08 08:54:54 PM PDT 24
Peak memory 609804 kb
Host smart-9a6f6b7e-2c99-4480-a298-7be5d5978f14
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620644770 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.3620644770
Directory /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1111144927
Short name T340
Test name
Test status
Simulation time 2975335624 ps
CPU time 358.53 seconds
Started Aug 08 08:36:38 PM PDT 24
Finished Aug 08 08:42:37 PM PDT 24
Peak memory 609892 kb
Host smart-defdba66-3f24-478b-a539-10b75889f115
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111144927 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.1111144927
Directory /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3037371160
Short name T171
Test name
Test status
Simulation time 4892284674 ps
CPU time 626.65 seconds
Started Aug 08 08:36:23 PM PDT 24
Finished Aug 08 08:46:50 PM PDT 24
Peak memory 609904 kb
Host smart-1cc6a9ca-4f27-4ed3-8e2b-eb467796355d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30
37371160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.3037371160
Directory /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.694985997
Short name T992
Test name
Test status
Simulation time 5518024108 ps
CPU time 1097.76 seconds
Started Aug 08 08:45:18 PM PDT 24
Finished Aug 08 09:03:36 PM PDT 24
Peak memory 609468 kb
Host smart-be2625ec-88f7-4b30-82c3-383fc2035699
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694985997 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.694985997
Directory /workspace/2.chip_sw_flash_ctrl_mem_protection/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1535102073
Short name T328
Test name
Test status
Simulation time 3652601840 ps
CPU time 696.92 seconds
Started Aug 08 08:37:30 PM PDT 24
Finished Aug 08 08:49:07 PM PDT 24
Peak memory 609776 kb
Host smart-7a50bf6a-4b68-4f2c-8d84-e0225aa2831e
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535102073
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.1535102073
Directory /workspace/2.chip_sw_flash_ctrl_ops/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.131072731
Short name T1239
Test name
Test status
Simulation time 3755008054 ps
CPU time 549.6 seconds
Started Aug 08 08:35:49 PM PDT 24
Finished Aug 08 08:44:58 PM PDT 24
Peak memory 609916 kb
Host smart-01bc8bf5-f301-46e3-b826-f4066c3d8d2d
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=131072731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.131072731
Directory /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2941258324
Short name T1229
Test name
Test status
Simulation time 4487341164 ps
CPU time 923.33 seconds
Started Aug 08 08:44:50 PM PDT 24
Finished Aug 08 09:00:14 PM PDT 24
Peak memory 610172 kb
Host smart-d2948aea-9f64-4f6c-a095-f6a12a454027
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_
rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2941258324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2941258324
Directory /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.3017491389
Short name T853
Test name
Test status
Simulation time 3427380792 ps
CPU time 388.94 seconds
Started Aug 08 08:44:56 PM PDT 24
Finished Aug 08 08:51:26 PM PDT 24
Peak memory 609784 kb
Host smart-3f90a597-2f1e-48e5-a902-06da10fd75ea
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017491
389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.3017491389
Directory /workspace/2.chip_sw_flash_ctrl_write_clear/latest

Test location /workspace/coverage/default/2.chip_sw_flash_init.2647388473
Short name T280
Test name
Test status
Simulation time 18358650779 ps
CPU time 1918.28 seconds
Started Aug 08 08:35:54 PM PDT 24
Finished Aug 08 09:07:53 PM PDT 24
Peak memory 613392 kb
Host smart-e533d19b-0eb7-485b-b221-4db9b878eed5
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647388473 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.2647388473
Directory /workspace/2.chip_sw_flash_init/latest

Test location /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.948654668
Short name T276
Test name
Test status
Simulation time 19925273725 ps
CPU time 1667.68 seconds
Started Aug 08 08:44:00 PM PDT 24
Finished Aug 08 09:11:48 PM PDT 24
Peak memory 614488 kb
Host smart-0799eb10-c400-443f-8608-d88db5f4fed5
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=948654668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.948654668
Directory /workspace/2.chip_sw_flash_init_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3293761658
Short name T1189
Test name
Test status
Simulation time 2360434510 ps
CPU time 258.02 seconds
Started Aug 08 08:49:38 PM PDT 24
Finished Aug 08 08:53:56 PM PDT 24
Peak memory 609676 kb
Host smart-74e8008b-78f7-4766-9c1c-8d23114c851c
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket
est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3293761658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.3293761658
Directory /workspace/2.chip_sw_flash_scrambling_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_gpio_smoketest.2104290327
Short name T257
Test name
Test status
Simulation time 2868968673 ps
CPU time 250.59 seconds
Started Aug 08 08:45:34 PM PDT 24
Finished Aug 08 08:49:44 PM PDT 24
Peak memory 609756 kb
Host smart-f711b648-fae4-45d2-bcc2-b1a31f57acf1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104290327 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_sw_gpio_smoketest.2104290327
Directory /workspace/2.chip_sw_gpio_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc.127468862
Short name T1135
Test name
Test status
Simulation time 3369229564 ps
CPU time 298.86 seconds
Started Aug 08 08:40:28 PM PDT 24
Finished Aug 08 08:45:27 PM PDT 24
Peak memory 609712 kb
Host smart-0c54a329-3450-43d6-9793-9c8d4f4ab9c3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127468862 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_hmac_enc.127468862
Directory /workspace/2.chip_sw_hmac_enc/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc_idle.4251466483
Short name T1224
Test name
Test status
Simulation time 2818431486 ps
CPU time 320.32 seconds
Started Aug 08 08:40:53 PM PDT 24
Finished Aug 08 08:46:14 PM PDT 24
Peak memory 609296 kb
Host smart-090a5648-2cc4-4e18-9935-d00fdea4787b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251466483 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_hmac_enc_idle.4251466483
Directory /workspace/2.chip_sw_hmac_enc_idle/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3056743618
Short name T864
Test name
Test status
Simulation time 2718354160 ps
CPU time 343.61 seconds
Started Aug 08 08:41:01 PM PDT 24
Finished Aug 08 08:46:45 PM PDT 24
Peak memory 609632 kb
Host smart-6a24ea17-ba4e-4955-ae8d-fc6a41edbb7e
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056743618 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.3056743618
Directory /workspace/2.chip_sw_hmac_enc_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3181278351
Short name T894
Test name
Test status
Simulation time 2744082434 ps
CPU time 250.64 seconds
Started Aug 08 08:45:15 PM PDT 24
Finished Aug 08 08:49:25 PM PDT 24
Peak memory 609784 kb
Host smart-17fc2768-bfeb-4786-ae4d-11736090ba91
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181278351 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.3181278351
Directory /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_multistream.2434888127
Short name T357
Test name
Test status
Simulation time 7948293096 ps
CPU time 1671.15 seconds
Started Aug 08 08:39:44 PM PDT 24
Finished Aug 08 09:07:35 PM PDT 24
Peak memory 610032 kb
Host smart-9d5388ef-d6b7-4263-bb48-9afe683fde06
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434888127 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.chip_sw_hmac_multistream.2434888127
Directory /workspace/2.chip_sw_hmac_multistream/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_oneshot.813281409
Short name T991
Test name
Test status
Simulation time 3280642166 ps
CPU time 293.02 seconds
Started Aug 08 08:39:51 PM PDT 24
Finished Aug 08 08:44:44 PM PDT 24
Peak memory 609452 kb
Host smart-5fffb396-32dd-4149-b698-b9d0740117b9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813281409 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_hmac_oneshot.813281409
Directory /workspace/2.chip_sw_hmac_oneshot/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_smoketest.4226977958
Short name T1094
Test name
Test status
Simulation time 3542282912 ps
CPU time 372.48 seconds
Started Aug 08 08:46:36 PM PDT 24
Finished Aug 08 08:52:49 PM PDT 24
Peak memory 609300 kb
Host smart-0433dfd5-b136-4bc0-8a2d-697d394749fc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226977958 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_hmac_smoketest.4226977958
Directory /workspace/2.chip_sw_hmac_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2955072808
Short name T1344
Test name
Test status
Simulation time 4440715970 ps
CPU time 626.47 seconds
Started Aug 08 08:35:15 PM PDT 24
Finished Aug 08 08:45:42 PM PDT 24
Peak memory 609672 kb
Host smart-defe1a3b-cb56-4066-9e62-def1b7c43c94
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955072808 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.2955072808
Directory /workspace/2.chip_sw_i2c_device_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.4176993651
Short name T949
Test name
Test status
Simulation time 4629789660 ps
CPU time 650.84 seconds
Started Aug 08 08:36:09 PM PDT 24
Finished Aug 08 08:47:00 PM PDT 24
Peak memory 609972 kb
Host smart-5c9ae7f8-4c31-4178-a92f-48e1b2b20510
User root
Command /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176993651 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.4176993651
Directory /workspace/2.chip_sw_i2c_host_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.4258721583
Short name T318
Test name
Test status
Simulation time 4179465208 ps
CPU time 955.91 seconds
Started Aug 08 08:36:11 PM PDT 24
Finished Aug 08 08:52:08 PM PDT 24
Peak memory 609696 kb
Host smart-c9deaffc-7308-4faf-9b58-3a5d3dca39a9
User root
Command /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258721583 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.4258721583
Directory /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest

Test location /workspace/coverage/default/2.chip_sw_inject_scramble_seed.4108494910
Short name T208
Test name
Test status
Simulation time 64073086743 ps
CPU time 10831.8 seconds
Started Aug 08 08:36:29 PM PDT 24
Finished Aug 08 11:37:02 PM PDT 24
Peak memory 624708 kb
Host smart-0e00152a-b4f6-437f-9001-792e4eff5573
User root
Command /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4108494910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.4108494910
Directory /workspace/2.chip_sw_inject_scramble_seed/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1167604909
Short name T1241
Test name
Test status
Simulation time 8824566678 ps
CPU time 1602.17 seconds
Started Aug 08 08:40:26 PM PDT 24
Finished Aug 08 09:07:09 PM PDT 24
Peak memory 617584 kb
Host smart-66f7f48f-fbf9-4f44-be3d-bbc4be0527e3
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167
604909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.1167604909
Directory /workspace/2.chip_sw_keymgr_key_derivation/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3357464018
Short name T358
Test name
Test status
Simulation time 8373508052 ps
CPU time 1672.1 seconds
Started Aug 08 08:40:08 PM PDT 24
Finished Aug 08 09:08:00 PM PDT 24
Peak memory 616556 kb
Host smart-1bd06edb-6ada-4fa3-ae31-e4712b62b580
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3357464018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.3357464018
Directory /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.382779362
Short name T114
Test name
Test status
Simulation time 9837926388 ps
CPU time 1327.21 seconds
Started Aug 08 08:45:14 PM PDT 24
Finished Aug 08 09:07:22 PM PDT 24
Peak memory 617860 kb
Host smart-51f78f6f-4be8-4929-80d5-b6617158aae0
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=382779362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en_
reduced_freq.382779362
Directory /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1931360791
Short name T404
Test name
Test status
Simulation time 7709760452 ps
CPU time 1688.9 seconds
Started Aug 08 08:40:45 PM PDT 24
Finished Aug 08 09:08:54 PM PDT 24
Peak memory 616828 kb
Host smart-ca0363ae-f939-490c-a334-43a60d3e3f2e
User root
Command /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1931360791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.1931360791
Directory /workspace/2.chip_sw_keymgr_key_derivation_prod/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.4051611723
Short name T271
Test name
Test status
Simulation time 9483834130 ps
CPU time 1958.37 seconds
Started Aug 08 08:41:08 PM PDT 24
Finished Aug 08 09:13:47 PM PDT 24
Peak memory 611128 kb
Host smart-8448db9c-1062-4143-9d4b-2e1ce85b0fad
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405161
1723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.4051611723
Directory /workspace/2.chip_sw_keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2275166911
Short name T912
Test name
Test status
Simulation time 12339468316 ps
CPU time 2426.19 seconds
Started Aug 08 08:40:37 PM PDT 24
Finished Aug 08 09:21:03 PM PDT 24
Peak memory 611252 kb
Host smart-111baeeb-8c8b-43c3-9ac4-696f5ba0f41d
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22751
66911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.2275166911
Directory /workspace/2.chip_sw_keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_app_rom.3870469106
Short name T382
Test name
Test status
Simulation time 2835796720 ps
CPU time 212.26 seconds
Started Aug 08 08:40:07 PM PDT 24
Finished Aug 08 08:43:40 PM PDT 24
Peak memory 609564 kb
Host smart-b518c071-4fc5-4fa5-a649-4eb6ac5bb36a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870469106 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_kmac_app_rom.3870469106
Directory /workspace/2.chip_sw_kmac_app_rom/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_entropy.3539765378
Short name T953
Test name
Test status
Simulation time 2941811336 ps
CPU time 321.93 seconds
Started Aug 08 08:35:21 PM PDT 24
Finished Aug 08 08:40:43 PM PDT 24
Peak memory 609300 kb
Host smart-1f2cb5c5-60f4-4280-b3e8-110a23d57094
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539765378 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_kmac_entropy.3539765378
Directory /workspace/2.chip_sw_kmac_entropy/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_idle.1778774697
Short name T1209
Test name
Test status
Simulation time 3127155304 ps
CPU time 351.15 seconds
Started Aug 08 08:41:46 PM PDT 24
Finished Aug 08 08:47:37 PM PDT 24
Peak memory 609516 kb
Host smart-13539b59-e855-46d8-9168-1c9d54303073
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778774697 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_kmac_idle.1778774697
Directory /workspace/2.chip_sw_kmac_idle/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2480543740
Short name T1075
Test name
Test status
Simulation time 2994446616 ps
CPU time 312.28 seconds
Started Aug 08 08:40:56 PM PDT 24
Finished Aug 08 08:46:09 PM PDT 24
Peak memory 609664 kb
Host smart-e5498b76-8fe9-4eae-99e6-a78bd08bb56e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480543740 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.chip_sw_kmac_mode_cshake.2480543740
Directory /workspace/2.chip_sw_kmac_mode_cshake/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2410762774
Short name T1119
Test name
Test status
Simulation time 3541905760 ps
CPU time 365.23 seconds
Started Aug 08 08:40:35 PM PDT 24
Finished Aug 08 08:46:41 PM PDT 24
Peak memory 609296 kb
Host smart-e9e6e20f-75c6-4261-ae31-a4584abe215f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410762774 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_kmac_mode_kmac.2410762774
Directory /workspace/2.chip_sw_kmac_mode_kmac/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3508972326
Short name T1217
Test name
Test status
Simulation time 3038863340 ps
CPU time 323.34 seconds
Started Aug 08 08:41:12 PM PDT 24
Finished Aug 08 08:46:36 PM PDT 24
Peak memory 609392 kb
Host smart-c8438cac-9962-45c3-b30c-6b49ce634dbb
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508972326 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.3508972326
Directory /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3981393921
Short name T922
Test name
Test status
Simulation time 3058260192 ps
CPU time 383.15 seconds
Started Aug 08 08:45:15 PM PDT 24
Finished Aug 08 08:51:39 PM PDT 24
Peak memory 609828 kb
Host smart-6c57147e-ba9b-4fdf-baa4-a94b867ff495
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39813939
21 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3981393921
Directory /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_smoketest.676350799
Short name T1215
Test name
Test status
Simulation time 3046829720 ps
CPU time 295.36 seconds
Started Aug 08 08:46:19 PM PDT 24
Finished Aug 08 08:51:15 PM PDT 24
Peak memory 609656 kb
Host smart-8fd530d0-d9e6-44cf-8dde-1be5c0e8b853
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676350799 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_kmac_smoketest.676350799
Directory /workspace/2.chip_sw_kmac_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1252122954
Short name T1122
Test name
Test status
Simulation time 3672944800 ps
CPU time 287.87 seconds
Started Aug 08 08:35:45 PM PDT 24
Finished Aug 08 08:40:33 PM PDT 24
Peak memory 609376 kb
Host smart-58e30fd0-3ff1-4de9-bf9a-e173b70634f6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252122954 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.1252122954
Directory /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.4180706968
Short name T167
Test name
Test status
Simulation time 5813380986 ps
CPU time 646.22 seconds
Started Aug 08 08:42:25 PM PDT 24
Finished Aug 08 08:53:12 PM PDT 24
Peak memory 610808 kb
Host smart-1a92fe25-147c-4977-a79d-982b7d893352
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4180706968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.4180706968
Directory /workspace/2.chip_sw_lc_ctrl_program_error/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2833238970
Short name T1008
Test name
Test status
Simulation time 10196345222 ps
CPU time 830.65 seconds
Started Aug 08 08:36:20 PM PDT 24
Finished Aug 08 08:50:11 PM PDT 24
Peak memory 624680 kb
Host smart-1554d504-6aa8-493c-b219-6b8e77431bb6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833238970 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.2833238970
Directory /workspace/2.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3106499802
Short name T631
Test name
Test status
Simulation time 2022822392 ps
CPU time 104.35 seconds
Started Aug 08 08:39:50 PM PDT 24
Finished Aug 08 08:41:35 PM PDT 24
Peak memory 617664 kb
Host smart-59f8c9b9-e434-4657-8aa4-4093b9a5a3a0
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes
t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3106499802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.3106499802
Directory /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1289497559
Short name T633
Test name
Test status
Simulation time 2275705368 ps
CPU time 101.96 seconds
Started Aug 08 08:36:50 PM PDT 24
Finished Aug 08 08:38:33 PM PDT 24
Peak memory 616996 kb
Host smart-89daa795-388c-41b6-a5cd-dba0cba91f90
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s
im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289497559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1289497559
Directory /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.791253037
Short name T277
Test name
Test status
Simulation time 51324668312 ps
CPU time 5087.68 seconds
Started Aug 08 08:38:18 PM PDT 24
Finished Aug 08 10:03:07 PM PDT 24
Peak memory 620360 kb
Host smart-75e05f7c-ab45-40c4-8be2-d1f4e899e85f
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d
evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791253037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip
_sw_lc_walkthrough_prod.791253037
Directory /workspace/2.chip_sw_lc_walkthrough_prod/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.587836921
Short name T283
Test name
Test status
Simulation time 47857071064 ps
CPU time 4982.18 seconds
Started Aug 08 08:37:30 PM PDT 24
Finished Aug 08 10:00:33 PM PDT 24
Peak memory 619596 kb
Host smart-d7c4e8a6-6907-4b9b-b2c0-01741ce41b45
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587836921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch
ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_
sw_lc_walkthrough_rma.587836921
Directory /workspace/2.chip_sw_lc_walkthrough_rma/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1951460905
Short name T175
Test name
Test status
Simulation time 24583245812 ps
CPU time 1964.99 seconds
Started Aug 08 08:36:30 PM PDT 24
Finished Aug 08 09:09:16 PM PDT 24
Peak memory 621232 kb
Host smart-cbb152d8-4333-4794-989e-abe0b0bca6ff
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks
_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1951460905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun
locks.1951460905
Directory /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1933755099
Short name T1048
Test name
Test status
Simulation time 17298010710 ps
CPU time 3211.31 seconds
Started Aug 08 08:41:21 PM PDT 24
Finished Aug 08 09:34:53 PM PDT 24
Peak memory 610020 kb
Host smart-1a7f47ad-1c8c-42c9-a52a-6a6dca542d80
User root
Command /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_
rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1933755099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.1933755099
Directory /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1094672385
Short name T974
Test name
Test status
Simulation time 19161932583 ps
CPU time 3617.86 seconds
Started Aug 08 08:38:38 PM PDT 24
Finished Aug 08 09:38:56 PM PDT 24
Peak memory 610328 kb
Host smart-bb9b8467-8f29-4185-bf04-35e931ee748e
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne
w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1094672385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1094672385
Directory /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2562112402
Short name T95
Test name
Test status
Simulation time 24515579786 ps
CPU time 3629.07 seconds
Started Aug 08 08:45:01 PM PDT 24
Finished Aug 08 09:45:30 PM PDT 24
Peak memory 610020 kb
Host smart-5fe334e3-1743-47d3-8dc3-2e0bbc62e941
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e
cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562112402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu
ced_freq.2562112402
Directory /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3662011162
Short name T251
Test name
Test status
Simulation time 4025435406 ps
CPU time 534.21 seconds
Started Aug 08 08:38:44 PM PDT 24
Finished Aug 08 08:47:38 PM PDT 24
Peak memory 609736 kb
Host smart-e7e8a2db-1dfe-41d3-baa0-f6cb4cd6e5c1
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn
_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662011162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.3662011162
Directory /workspace/2.chip_sw_otbn_mem_scramble/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_randomness.366554329
Short name T1071
Test name
Test status
Simulation time 6494326750 ps
CPU time 964.7 seconds
Started Aug 08 08:38:27 PM PDT 24
Finished Aug 08 08:54:32 PM PDT 24
Peak memory 610296 kb
Host smart-6ed17e30-e059-4e87-b055-5986eaee18a4
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=366554329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.366554329
Directory /workspace/2.chip_sw_otbn_randomness/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_smoketest.3296402327
Short name T962
Test name
Test status
Simulation time 7250924596 ps
CPU time 1441.61 seconds
Started Aug 08 08:46:45 PM PDT 24
Finished Aug 08 09:10:47 PM PDT 24
Peak memory 610168 kb
Host smart-0ef24ea2-479b-469b-bc8e-2fa13e941509
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296402327 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_otbn_smoketest.3296402327
Directory /workspace/2.chip_sw_otbn_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1036659119
Short name T405
Test name
Test status
Simulation time 3307142574 ps
CPU time 317.1 seconds
Started Aug 08 08:38:08 PM PDT 24
Finished Aug 08 08:43:27 PM PDT 24
Peak memory 608960 kb
Host smart-85521cb5-0e22-4f67-93fd-abe5bd9d9735
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036659119 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.1036659119
Directory /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.100340995
Short name T270
Test name
Test status
Simulation time 6912199404 ps
CPU time 1507.87 seconds
Started Aug 08 08:36:29 PM PDT 24
Finished Aug 08 09:01:37 PM PDT 24
Peak memory 610460 kb
Host smart-ef2b2cf3-cf18-45cd-a680-04c40a9fe2ae
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=100340995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.100340995
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3273871660
Short name T165
Test name
Test status
Simulation time 7703048936 ps
CPU time 1392.13 seconds
Started Aug 08 08:36:33 PM PDT 24
Finished Aug 08 08:59:46 PM PDT 24
Peak memory 610356 kb
Host smart-9e5b12f8-c624-46d1-ab4c-4b0661285b78
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3273871660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.3273871660
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3887648589
Short name T1055
Test name
Test status
Simulation time 8378270710 ps
CPU time 1131.84 seconds
Started Aug 08 08:39:48 PM PDT 24
Finished Aug 08 08:58:40 PM PDT 24
Peak memory 610712 kb
Host smart-bec2c8e5-c3e4-42ac-8583-9488240c6261
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3887648589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.3887648589
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1175686147
Short name T957
Test name
Test status
Simulation time 4540713966 ps
CPU time 727.53 seconds
Started Aug 08 08:36:25 PM PDT 24
Finished Aug 08 08:48:33 PM PDT 24
Peak memory 609908 kb
Host smart-3355554e-d734-4bb0-bc52-1c92e463ad8c
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=1175686147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1175686147
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.2684427551
Short name T1170
Test name
Test status
Simulation time 2952399428 ps
CPU time 265.42 seconds
Started Aug 08 08:46:02 PM PDT 24
Finished Aug 08 08:50:28 PM PDT 24
Peak memory 609696 kb
Host smart-409ee04d-9a7a-476e-b203-20c36aa1a439
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684427551 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_otp_ctrl_smoketest.2684427551
Directory /workspace/2.chip_sw_otp_ctrl_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_pattgen_ios.3110651934
Short name T218
Test name
Test status
Simulation time 3245178304 ps
CPU time 198.15 seconds
Started Aug 08 08:33:53 PM PDT 24
Finished Aug 08 08:37:12 PM PDT 24
Peak memory 612384 kb
Host smart-cec5eb64-9feb-4dd2-a2a3-f1030cb1a77d
User root
Command /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110651934 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.3110651934
Directory /workspace/2.chip_sw_pattgen_ios/latest

Test location /workspace/coverage/default/2.chip_sw_plic_sw_irq.3233737061
Short name T646
Test name
Test status
Simulation time 3251988964 ps
CPU time 309.96 seconds
Started Aug 08 08:41:19 PM PDT 24
Finished Aug 08 08:46:29 PM PDT 24
Peak memory 609356 kb
Host smart-7550879a-1c79-40a8-9d68-286f1a5260b1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233737061 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.chip_sw_plic_sw_irq.3233737061
Directory /workspace/2.chip_sw_plic_sw_irq/latest

Test location /workspace/coverage/default/2.chip_sw_power_idle_load.3195671263
Short name T637
Test name
Test status
Simulation time 4048456480 ps
CPU time 789.84 seconds
Started Aug 08 08:45:09 PM PDT 24
Finished Aug 08 08:58:19 PM PDT 24
Peak memory 609404 kb
Host smart-0ed75628-8c29-44a4-ac37-d5110eb9c213
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195671263 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.3195671263
Directory /workspace/2.chip_sw_power_idle_load/latest

Test location /workspace/coverage/default/2.chip_sw_power_sleep_load.763402185
Short name T5
Test name
Test status
Simulation time 4440567790 ps
CPU time 329.78 seconds
Started Aug 08 08:44:29 PM PDT 24
Finished Aug 08 08:49:59 PM PDT 24
Peak memory 609516 kb
Host smart-b738ca5e-3b1e-41a1-8ec9-2ead7c193c41
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763402185 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.763402185
Directory /workspace/2.chip_sw_power_sleep_load/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1499465361
Short name T1261
Test name
Test status
Simulation time 13627055746 ps
CPU time 1682.91 seconds
Started Aug 08 08:37:55 PM PDT 24
Finished Aug 08 09:05:58 PM PDT 24
Peak memory 611452 kb
Host smart-ffda7d25-c98e-4954-9580-7ab8b91c5074
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499
465361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.1499465361
Directory /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2823911029
Short name T1160
Test name
Test status
Simulation time 22372885594 ps
CPU time 1861.79 seconds
Started Aug 08 08:41:21 PM PDT 24
Finished Aug 08 09:12:24 PM PDT 24
Peak memory 610616 kb
Host smart-27bf7499-4e34-4e37-a8b6-70e570fbf270
User root
Command /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282
3911029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.2823911029
Directory /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1624450982
Short name T403
Test name
Test status
Simulation time 17598858984 ps
CPU time 1486.58 seconds
Started Aug 08 08:37:46 PM PDT 24
Finished Aug 08 09:02:33 PM PDT 24
Peak memory 611552 kb
Host smart-ea6d36f9-833a-4e63-8cab-3b156df7c7ac
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1624450982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1624450982
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.265955641
Short name T1280
Test name
Test status
Simulation time 7810659362 ps
CPU time 743.48 seconds
Started Aug 08 08:37:25 PM PDT 24
Finished Aug 08 08:49:49 PM PDT 24
Peak memory 610872 kb
Host smart-b5023e76-3857-4ea1-87ed-6f943037f0b2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265955641 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.265955641
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2273813253
Short name T1113
Test name
Test status
Simulation time 6050914164 ps
CPU time 621.79 seconds
Started Aug 08 08:36:47 PM PDT 24
Finished Aug 08 08:47:09 PM PDT 24
Peak memory 616432 kb
Host smart-49875cc4-3c26-49b9-8d1b-f51d84aea766
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2273813253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2273813253
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3390058132
Short name T144
Test name
Test status
Simulation time 8302489224 ps
CPU time 448.46 seconds
Started Aug 08 08:36:22 PM PDT 24
Finished Aug 08 08:43:51 PM PDT 24
Peak memory 610820 kb
Host smart-a358ddb7-02ba-49d4-a846-6ce973848e2a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390058132 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.3390058132
Directory /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.3429705643
Short name T325
Test name
Test status
Simulation time 3736983320 ps
CPU time 447.51 seconds
Started Aug 08 08:43:19 PM PDT 24
Finished Aug 08 08:50:47 PM PDT 24
Peak memory 609424 kb
Host smart-e9dfc2f6-c8c8-40ea-882d-ff79929101d1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429705643 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.3429705643
Directory /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.10664887
Short name T941
Test name
Test status
Simulation time 3042540596 ps
CPU time 311.5 seconds
Started Aug 08 08:37:42 PM PDT 24
Finished Aug 08 08:42:54 PM PDT 24
Peak memory 617256 kb
Host smart-02b292a4-b7a7-4001-b0ec-db6dc445fb05
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=10664887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.10664887
Directory /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.833874515
Short name T1165
Test name
Test status
Simulation time 9938183292 ps
CPU time 1368 seconds
Started Aug 08 08:39:15 PM PDT 24
Finished Aug 08 09:02:03 PM PDT 24
Peak memory 611412 kb
Host smart-b88618b1-6225-478f-9be0-03484d1d3210
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833874515 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.833874515
Directory /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.730626461
Short name T109
Test name
Test status
Simulation time 7718075884 ps
CPU time 509.64 seconds
Started Aug 08 08:43:04 PM PDT 24
Finished Aug 08 08:51:34 PM PDT 24
Peak memory 610652 kb
Host smart-1e8c9422-b0dd-4eb0-afd2-ca1d21cdce47
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730626461 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.730626461
Directory /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3765540987
Short name T876
Test name
Test status
Simulation time 5879600693 ps
CPU time 709.92 seconds
Started Aug 08 08:37:02 PM PDT 24
Finished Aug 08 08:48:52 PM PDT 24
Peak memory 609596 kb
Host smart-95487dc4-4460-4273-8d89-837d4d26f5a2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765540987 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.3765540987
Directory /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2495765910
Short name T1186
Test name
Test status
Simulation time 23947782906 ps
CPU time 2028.9 seconds
Started Aug 08 08:37:40 PM PDT 24
Finished Aug 08 09:11:29 PM PDT 24
Peak memory 611548 kb
Host smart-cdaec6c1-69bc-4ecb-9eb2-8f7b59024a74
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2495765910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2495765910
Directory /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1468127713
Short name T62
Test name
Test status
Simulation time 23333424600 ps
CPU time 1185.35 seconds
Started Aug 08 08:43:05 PM PDT 24
Finished Aug 08 09:02:50 PM PDT 24
Peak memory 610948 kb
Host smart-85d3acd9-9521-494a-a052-fee59fcb4e4f
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1468127713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1468127713
Directory /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.345269809
Short name T341
Test name
Test status
Simulation time 38736295490 ps
CPU time 2850.89 seconds
Started Aug 08 08:37:03 PM PDT 24
Finished Aug 08 09:24:34 PM PDT 24
Peak memory 612056 kb
Host smart-9bd8ae96-620b-45cc-9450-7f166027d756
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power
_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345269809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sl
eep_power_glitch_reset.345269809
Directory /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3933904269
Short name T345
Test name
Test status
Simulation time 6367007104 ps
CPU time 673.96 seconds
Started Aug 08 08:42:58 PM PDT 24
Finished Aug 08 08:54:12 PM PDT 24
Peak memory 609732 kb
Host smart-6a200ead-703e-40e1-93a3-a4b2b00d81c1
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul
es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3933904269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s
leep_wake_up.3933904269
Directory /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3339192944
Short name T96
Test name
Test status
Simulation time 2822906460 ps
CPU time 241.82 seconds
Started Aug 08 08:39:55 PM PDT 24
Finished Aug 08 08:43:57 PM PDT 24
Peak memory 609384 kb
Host smart-ca4e9e65-ca72-4a8d-843a-bf96bf1d695c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339192944 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.3339192944
Directory /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1215229638
Short name T1315
Test name
Test status
Simulation time 5492128225 ps
CPU time 457.8 seconds
Started Aug 08 08:37:24 PM PDT 24
Finished Aug 08 08:45:02 PM PDT 24
Peak memory 617828 kb
Host smart-60092e24-56ac-4646-bbfb-59152a960a93
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=1215229638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.1215229638
Directory /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2443797067
Short name T138
Test name
Test status
Simulation time 5426832822 ps
CPU time 409.15 seconds
Started Aug 08 08:41:09 PM PDT 24
Finished Aug 08 08:47:59 PM PDT 24
Peak memory 608604 kb
Host smart-56f34cb1-44af-4177-9d20-f95e120b6f11
User root
Command /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24437970
67 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2443797067
Directory /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1251657759
Short name T129
Test name
Test status
Simulation time 6175268952 ps
CPU time 465.95 seconds
Started Aug 08 08:43:15 PM PDT 24
Finished Aug 08 08:51:01 PM PDT 24
Peak memory 610752 kb
Host smart-1cd8553d-8eba-4fa0-a56b-fd11d56dc658
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1251657759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.1251657759
Directory /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3628306198
Short name T959
Test name
Test status
Simulation time 5426137672 ps
CPU time 453.55 seconds
Started Aug 08 08:47:37 PM PDT 24
Finished Aug 08 08:55:11 PM PDT 24
Peak memory 610432 kb
Host smart-709269bf-9c75-49ea-bf2c-35028db739e0
User root
Command /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628306198 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.3628306198
Directory /workspace/2.chip_sw_pwrmgr_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.292207232
Short name T1086
Test name
Test status
Simulation time 6166916568 ps
CPU time 1385.84 seconds
Started Aug 08 08:38:01 PM PDT 24
Finished Aug 08 09:01:07 PM PDT 24
Peak memory 610512 kb
Host smart-2bda3a28-3a4a-4841-9239-d3842c48cc20
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292207232 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.292207232
Directory /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.266502151
Short name T1190
Test name
Test status
Simulation time 5521479232 ps
CPU time 505.39 seconds
Started Aug 08 08:39:46 PM PDT 24
Finished Aug 08 08:48:12 PM PDT 24
Peak memory 610424 kb
Host smart-b5d6073b-c77e-4712-af22-f540c0b43005
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266502151 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.266502151
Directory /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.429042958
Short name T1200
Test name
Test status
Simulation time 4885249956 ps
CPU time 301.23 seconds
Started Aug 08 08:48:32 PM PDT 24
Finished Aug 08 08:53:33 PM PDT 24
Peak memory 610184 kb
Host smart-b0436a67-436b-4ab0-8526-adb299033678
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429042958 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.429042958
Directory /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1026984032
Short name T857
Test name
Test status
Simulation time 5230904534 ps
CPU time 580.61 seconds
Started Aug 08 08:37:49 PM PDT 24
Finished Aug 08 08:47:30 PM PDT 24
Peak memory 610452 kb
Host smart-bc27163b-1219-472f-bf18-a9dfa02423ba
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102
6984032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.1026984032
Directory /workspace/2.chip_sw_pwrmgr_wdog_reset/latest

Test location /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1152244771
Short name T7
Test name
Test status
Simulation time 9689486817 ps
CPU time 722.57 seconds
Started Aug 08 08:41:21 PM PDT 24
Finished Aug 08 08:53:24 PM PDT 24
Peak memory 624732 kb
Host smart-0362cea5-c987-4f13-adb1-dac592d16fc2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152244771 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.1152244771
Directory /workspace/2.chip_sw_rom_ctrl_integrity_check/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1575197803
Short name T312
Test name
Test status
Simulation time 12325803826 ps
CPU time 1623.94 seconds
Started Aug 08 08:37:45 PM PDT 24
Finished Aug 08 09:04:49 PM PDT 24
Peak memory 611044 kb
Host smart-873c56b5-d63d-43ba-8169-7d21cda0e6bb
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=1575197803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.1575197803
Directory /workspace/2.chip_sw_rstmgr_alert_info/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.334116578
Short name T241
Test name
Test status
Simulation time 5234364440 ps
CPU time 553.66 seconds
Started Aug 08 08:37:50 PM PDT 24
Finished Aug 08 08:47:04 PM PDT 24
Peak memory 609416 kb
Host smart-9bcc53ed-e30e-43d7-a9b3-5c2294b8ecec
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334116578 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_rstmgr_cpu_info.334116578
Directory /workspace/2.chip_sw_rstmgr_cpu_info/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3906431146
Short name T651
Test name
Test status
Simulation time 4487037058 ps
CPU time 599.22 seconds
Started Aug 08 08:35:32 PM PDT 24
Finished Aug 08 08:45:31 PM PDT 24
Peak memory 641484 kb
Host smart-9eaff406-642f-4523-9dfc-880bda217eaa
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3906431146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.3906431146
Directory /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.4513391
Short name T930
Test name
Test status
Simulation time 2289752744 ps
CPU time 246.97 seconds
Started Aug 08 08:46:10 PM PDT 24
Finished Aug 08 08:50:17 PM PDT 24
Peak memory 609232 kb
Host smart-3bc2537e-ab44-4f24-88e1-abc10470756c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4513391 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_rstmgr_smoketest.4513391
Directory /workspace/2.chip_sw_rstmgr_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1382138337
Short name T952
Test name
Test status
Simulation time 4580352460 ps
CPU time 601.33 seconds
Started Aug 08 08:37:09 PM PDT 24
Finished Aug 08 08:47:11 PM PDT 24
Peak memory 609036 kb
Host smart-af09c757-23a6-4641-8846-ec2d4ccf3765
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382138337 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_rstmgr_sw_req.1382138337
Directory /workspace/2.chip_sw_rstmgr_sw_req/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.702136315
Short name T1347
Test name
Test status
Simulation time 2465599192 ps
CPU time 214.2 seconds
Started Aug 08 08:39:48 PM PDT 24
Finished Aug 08 08:43:23 PM PDT 24
Peak memory 609740 kb
Host smart-760df930-2867-49a9-b195-9ca3262e6006
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702136315 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.702136315
Directory /workspace/2.chip_sw_rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1527744898
Short name T262
Test name
Test status
Simulation time 2800355568 ps
CPU time 256.99 seconds
Started Aug 08 08:43:26 PM PDT 24
Finished Aug 08 08:47:43 PM PDT 24
Peak memory 608676 kb
Host smart-8d3be955-cbb9-4a95-8c13-d6f8bb003c6a
User root
Command /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1527744898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.1527744898
Directory /workspace/2.chip_sw_rv_core_ibex_address_translation/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2128620944
Short name T182
Test name
Test status
Simulation time 3065586768 ps
CPU time 339.93 seconds
Started Aug 08 08:45:16 PM PDT 24
Finished Aug 08 08:50:56 PM PDT 24
Peak memory 610056 kb
Host smart-4455d354-c608-483b-8e3a-0ee8b7c20bfd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128620944 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.2128620944
Directory /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3014060054
Short name T657
Test name
Test status
Simulation time 5091642170 ps
CPU time 644.08 seconds
Started Aug 08 08:38:23 PM PDT 24
Finished Aug 08 08:49:07 PM PDT 24
Peak memory 610168 kb
Host smart-0c4ab45b-e936-45ea-9a2a-87d7410d72e7
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30140
60054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.3014060054
Directory /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.843020151
Short name T376
Test name
Test status
Simulation time 5736718490 ps
CPU time 893.86 seconds
Started Aug 08 08:37:45 PM PDT 24
Finished Aug 08 08:52:39 PM PDT 24
Peak memory 610016 kb
Host smart-8d76dee4-c1eb-4e4b-aaed-2d0d1114c48d
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=843020151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.843020151
Directory /workspace/2.chip_sw_rv_core_ibex_rnd/latest

Test location /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.848768848
Short name T866
Test name
Test status
Simulation time 6924130804 ps
CPU time 499.18 seconds
Started Aug 08 08:43:40 PM PDT 24
Finished Aug 08 08:51:59 PM PDT 24
Peak memory 620448 kb
Host smart-a365c260-d796-4ec2-93f0-cf0c81f0f104
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848768848 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.848768848
Directory /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3855252290
Short name T297
Test name
Test status
Simulation time 3688560456 ps
CPU time 484.54 seconds
Started Aug 08 08:43:53 PM PDT 24
Finished Aug 08 08:51:57 PM PDT 24
Peak memory 621272 kb
Host smart-c74d8d4a-c942-41d0-a2bb-c3c2fdac335c
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385525
2290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3855252290
Directory /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3230999629
Short name T1089
Test name
Test status
Simulation time 2343035900 ps
CPU time 295.75 seconds
Started Aug 08 08:46:48 PM PDT 24
Finished Aug 08 08:51:44 PM PDT 24
Peak memory 609636 kb
Host smart-7bfc744b-6714-4ecd-9136-12a5ce00e2ad
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230999629 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_rv_plic_smoketest.3230999629
Directory /workspace/2.chip_sw_rv_plic_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_rv_timer_irq.1214805097
Short name T956
Test name
Test status
Simulation time 2506470260 ps
CPU time 207.32 seconds
Started Aug 08 08:38:09 PM PDT 24
Finished Aug 08 08:41:36 PM PDT 24
Peak memory 609316 kb
Host smart-ee7da79d-eb46-4fe2-9289-4972579d43d1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214805097 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_rv_timer_irq.1214805097
Directory /workspace/2.chip_sw_rv_timer_irq/latest

Test location /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.948023182
Short name T1193
Test name
Test status
Simulation time 3263157128 ps
CPU time 286.62 seconds
Started Aug 08 08:47:23 PM PDT 24
Finished Aug 08 08:52:10 PM PDT 24
Peak memory 609628 kb
Host smart-b4fcde43-8d9e-46ec-bbd6-f61fd18a610b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948023182 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_rv_timer_smoketest.948023182
Directory /workspace/2.chip_sw_rv_timer_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3959711637
Short name T1264
Test name
Test status
Simulation time 3092826047 ps
CPU time 184.4 seconds
Started Aug 08 08:41:18 PM PDT 24
Finished Aug 08 08:44:23 PM PDT 24
Peak memory 609504 kb
Host smart-ed287f23-de2a-4764-86cc-463c41e82f93
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959711
637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.3959711637
Directory /workspace/2.chip_sw_sensor_ctrl_status/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pin_wake.2578523589
Short name T64
Test name
Test status
Simulation time 5028217426 ps
CPU time 465.62 seconds
Started Aug 08 08:37:14 PM PDT 24
Finished Aug 08 08:45:00 PM PDT 24
Peak memory 610664 kb
Host smart-b6419b2b-3d64-4573-a086-94cb122d9e87
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578523589
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.2578523589
Directory /workspace/2.chip_sw_sleep_pin_wake/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3685059649
Short name T1155
Test name
Test status
Simulation time 8224255350 ps
CPU time 1330.53 seconds
Started Aug 08 08:35:16 PM PDT 24
Finished Aug 08 08:57:27 PM PDT 24
Peak memory 609524 kb
Host smart-b12de384-2b18-4f9b-97a0-69b871508752
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685059649 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.3685059649
Directory /workspace/2.chip_sw_sleep_pwm_pulses/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1359856338
Short name T394
Test name
Test status
Simulation time 9051103760 ps
CPU time 692.49 seconds
Started Aug 08 08:41:18 PM PDT 24
Finished Aug 08 08:52:51 PM PDT 24
Peak memory 610656 kb
Host smart-6adeb34e-f3b7-485f-83e4-0a818a108e35
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359856338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl
eep_sram_ret_contents_no_scramble.1359856338
Directory /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2927103571
Short name T1210
Test name
Test status
Simulation time 7267335542 ps
CPU time 790.32 seconds
Started Aug 08 08:40:53 PM PDT 24
Finished Aug 08 08:54:03 PM PDT 24
Peak memory 610440 kb
Host smart-2037ae11-cbca-4301-a81a-6dddd46bb914
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927103571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep
_sram_ret_contents_scramble.2927103571
Directory /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3172040063
Short name T204
Test name
Test status
Simulation time 7459754399 ps
CPU time 600.02 seconds
Started Aug 08 08:34:14 PM PDT 24
Finished Aug 08 08:44:14 PM PDT 24
Peak memory 624816 kb
Host smart-84046d05-c7ef-49c6-af43-6182f569f2b1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172040063 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.3172040063
Directory /workspace/2.chip_sw_spi_device_pass_through/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3533788675
Short name T13
Test name
Test status
Simulation time 4851327416 ps
CPU time 572.12 seconds
Started Aug 08 08:35:22 PM PDT 24
Finished Aug 08 08:44:54 PM PDT 24
Peak memory 624800 kb
Host smart-4769af56-0978-421c-8a22-d16dc5a67b05
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533788675 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.3533788675
Directory /workspace/2.chip_sw_spi_device_pass_through_collision/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.1855226450
Short name T56
Test name
Test status
Simulation time 2873582327 ps
CPU time 234.15 seconds
Started Aug 08 08:35:14 PM PDT 24
Finished Aug 08 08:39:08 PM PDT 24
Peak memory 618748 kb
Host smart-34012150-9153-40ef-96f8-113e0d14ac0a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855226450 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.1855226450
Directory /workspace/2.chip_sw_spi_device_pinmux_sleep_retention/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_tpm.1759461053
Short name T43
Test name
Test status
Simulation time 3466202410 ps
CPU time 465.66 seconds
Started Aug 08 08:35:24 PM PDT 24
Finished Aug 08 08:43:10 PM PDT 24
Peak memory 618496 kb
Host smart-9901c776-8e81-4243-b974-99c53b1e9cf6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759461053 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.1759461053
Directory /workspace/2.chip_sw_spi_device_tpm/latest

Test location /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1339122429
Short name T14
Test name
Test status
Simulation time 3465623400 ps
CPU time 245 seconds
Started Aug 08 08:35:56 PM PDT 24
Finished Aug 08 08:40:01 PM PDT 24
Peak memory 608924 kb
Host smart-c6cef6a5-ecef-4820-8f5d-ab0c8e4d1c2c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339122429 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.1339122429
Directory /workspace/2.chip_sw_spi_host_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2219728763
Short name T186
Test name
Test status
Simulation time 8427861193 ps
CPU time 918.2 seconds
Started Aug 08 08:42:49 PM PDT 24
Finished Aug 08 08:58:08 PM PDT 24
Peak memory 609632 kb
Host smart-50280a17-cf92-44c6-8328-2b242b4d28d7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219728763 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.2219728763
Directory /workspace/2.chip_sw_sram_ctrl_execution_main/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.4230112634
Short name T395
Test name
Test status
Simulation time 4494082488 ps
CPU time 694.09 seconds
Started Aug 08 08:41:02 PM PDT 24
Finished Aug 08 08:52:36 PM PDT 24
Peak memory 609864 kb
Host smart-c33854b7-7f3e-413d-9299-0fb48c8c7a76
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230112634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr
l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw
_sram_ctrl_scrambled_access.4230112634
Directory /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.4006210733
Short name T513
Test name
Test status
Simulation time 5278091955 ps
CPU time 530.18 seconds
Started Aug 08 08:40:43 PM PDT 24
Finished Aug 08 08:49:34 PM PDT 24
Peak memory 611088 kb
Host smart-e897fe03-1ccf-4b6a-b046-9826d5cc9db3
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s
w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006210733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.4006210733
Directory /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1240370848
Short name T407
Test name
Test status
Simulation time 3146510584 ps
CPU time 235.32 seconds
Started Aug 08 08:46:19 PM PDT 24
Finished Aug 08 08:50:15 PM PDT 24
Peak memory 609340 kb
Host smart-1bd9c349-a4ae-4932-9e24-1c5772b7c5fb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240370848 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.1240370848
Directory /workspace/2.chip_sw_sram_ctrl_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.29919823
Short name T219
Test name
Test status
Simulation time 20536444065 ps
CPU time 2928.31 seconds
Started Aug 08 08:37:27 PM PDT 24
Finished Aug 08 09:26:16 PM PDT 24
Peak memory 610868 kb
Host smart-dbbb3851-3755-4f89-8d27-cd204761d3fd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29919823 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.29919823
Directory /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2517599404
Short name T1142
Test name
Test status
Simulation time 5326318755 ps
CPU time 862.04 seconds
Started Aug 08 08:39:23 PM PDT 24
Finished Aug 08 08:53:47 PM PDT 24
Peak memory 613732 kb
Host smart-d7e3fcd8-650d-4f6c-85a6-db32b7452c3a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517599404 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.2517599404
Directory /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2000483261
Short name T209
Test name
Test status
Simulation time 3102109063 ps
CPU time 323.26 seconds
Started Aug 08 08:39:50 PM PDT 24
Finished Aug 08 08:45:14 PM PDT 24
Peak memory 613096 kb
Host smart-0d5f40e5-d09f-4f71-aad2-c392ddf454ed
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000483261 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.2000483261
Directory /workspace/2.chip_sw_sysrst_ctrl_inputs/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2078430160
Short name T1240
Test name
Test status
Simulation time 3504958004 ps
CPU time 364.4 seconds
Started Aug 08 08:37:44 PM PDT 24
Finished Aug 08 08:43:48 PM PDT 24
Peak memory 609396 kb
Host smart-9ecef82d-a41a-4044-b3da-bcfa0dcce154
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078430160 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.2078430160
Directory /workspace/2.chip_sw_sysrst_ctrl_outputs/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.763827112
Short name T1139
Test name
Test status
Simulation time 24589671856 ps
CPU time 1892.58 seconds
Started Aug 08 08:40:10 PM PDT 24
Finished Aug 08 09:11:43 PM PDT 24
Peak memory 614976 kb
Host smart-b32513ac-d431-4f77-b180-c411c4607f88
User root
Command /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76382711
2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.763827112
Directory /workspace/2.chip_sw_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.620719352
Short name T39
Test name
Test status
Simulation time 5440543732 ps
CPU time 433.04 seconds
Started Aug 08 08:37:01 PM PDT 24
Finished Aug 08 08:44:14 PM PDT 24
Peak memory 610748 kb
Host smart-beb22025-32cc-4aa4-9419-284e6c9274ce
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620719352 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.620719352
Directory /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.4045154450
Short name T1313
Test name
Test status
Simulation time 8741586194 ps
CPU time 1740.59 seconds
Started Aug 08 08:35:02 PM PDT 24
Finished Aug 08 09:04:03 PM PDT 24
Peak memory 624564 kb
Host smart-7b631334-a9a5-49f3-8aac-babd08d97e07
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=4045154450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.4045154450
Directory /workspace/2.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/2.chip_sw_uart_smoketest.3477775150
Short name T978
Test name
Test status
Simulation time 3160523804 ps
CPU time 302.31 seconds
Started Aug 08 08:45:58 PM PDT 24
Finished Aug 08 08:51:00 PM PDT 24
Peak memory 615088 kb
Host smart-46c26a59-8ede-4f35-98e3-c1090e7a89b9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477775150 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_sw_uart_smoketest.3477775150
Directory /workspace/2.chip_sw_uart_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx.2975128566
Short name T1088
Test name
Test status
Simulation time 4225258740 ps
CPU time 528.1 seconds
Started Aug 08 08:34:02 PM PDT 24
Finished Aug 08 08:42:50 PM PDT 24
Peak memory 623580 kb
Host smart-bba29c54-eef4-4a34-86ee-816bb24eb656
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975128566 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.2975128566
Directory /workspace/2.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3778036487
Short name T1195
Test name
Test status
Simulation time 8263912399 ps
CPU time 1491.9 seconds
Started Aug 08 08:36:39 PM PDT 24
Finished Aug 08 09:01:31 PM PDT 24
Peak memory 624496 kb
Host smart-76ac9603-e528-411d-964e-017dabb174a9
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778036487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx
_alt_clk_freq.3778036487
Directory /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3281806436
Short name T918
Test name
Test status
Simulation time 8370474018 ps
CPU time 1165.05 seconds
Started Aug 08 08:35:31 PM PDT 24
Finished Aug 08 08:54:56 PM PDT 24
Peak memory 624520 kb
Host smart-2a922e96-6ae0-4ccb-8795-508448c56fe0
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281806436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.3281806436
Directory /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.102550671
Short name T1050
Test name
Test status
Simulation time 77636362983 ps
CPU time 13186.4 seconds
Started Aug 08 08:35:59 PM PDT 24
Finished Aug 09 12:15:47 AM PDT 24
Peak memory 635064 kb
Host smart-55d825bf-0ebc-49b5-9297-c73280e09236
User root
Command /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=102550671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.102550671
Directory /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.4183680713
Short name T214
Test name
Test status
Simulation time 4530933800 ps
CPU time 595.27 seconds
Started Aug 08 08:36:36 PM PDT 24
Finished Aug 08 08:46:32 PM PDT 24
Peak memory 623900 kb
Host smart-eee2d9f0-9f27-4acd-ad4f-f315bff55e85
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183680713 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.4183680713
Directory /workspace/2.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2982813927
Short name T1096
Test name
Test status
Simulation time 3942160072 ps
CPU time 722.8 seconds
Started Aug 08 08:35:14 PM PDT 24
Finished Aug 08 08:47:18 PM PDT 24
Peak memory 623828 kb
Host smart-f4125074-6b4c-47aa-bf53-3f0da49692ce
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982813927 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.2982813927
Directory /workspace/2.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.15962544
Short name T1168
Test name
Test status
Simulation time 4265052564 ps
CPU time 704.08 seconds
Started Aug 08 08:36:46 PM PDT 24
Finished Aug 08 08:48:30 PM PDT 24
Peak memory 623856 kb
Host smart-c6eea7c1-afc0-41ad-bc80-9ed4c88f2b00
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15962544 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.15962544
Directory /workspace/2.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/2.chip_tap_straps_dev.3805489114
Short name T629
Test name
Test status
Simulation time 6626638990 ps
CPU time 605.56 seconds
Started Aug 08 08:43:28 PM PDT 24
Finished Aug 08 08:53:34 PM PDT 24
Peak memory 624676 kb
Host smart-5fe99e54-a363-4c09-bb7d-35f13f4dd18a
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3805489114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.3805489114
Directory /workspace/2.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/2.chip_tap_straps_prod.1590909041
Short name T867
Test name
Test status
Simulation time 3210090753 ps
CPU time 189.46 seconds
Started Aug 08 08:43:28 PM PDT 24
Finished Aug 08 08:46:38 PM PDT 24
Peak memory 620932 kb
Host smart-18af7914-f749-4061-92fb-08132a908163
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1590909041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.1590909041
Directory /workspace/2.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/2.chip_tap_straps_rma.205001399
Short name T1245
Test name
Test status
Simulation time 2666691345 ps
CPU time 178.02 seconds
Started Aug 08 08:43:01 PM PDT 24
Finished Aug 08 08:45:59 PM PDT 24
Peak memory 624484 kb
Host smart-fd34baf0-5098-4c2d-bca4-ceac014ef98d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205001399 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.205001399
Directory /workspace/2.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_dev.4155639892
Short name T942
Test name
Test status
Simulation time 16174026746 ps
CPU time 3219.57 seconds
Started Aug 08 08:49:54 PM PDT 24
Finished Aug 08 09:43:34 PM PDT 24
Peak memory 610168 kb
Host smart-ac1cc915-84b1-4a14-854e-4ada291c21cb
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155639892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rom_e2e_asm_init_dev.4155639892
Directory /workspace/2.rom_e2e_asm_init_dev/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_prod.2165581849
Short name T938
Test name
Test status
Simulation time 15584131250 ps
CPU time 3247.95 seconds
Started Aug 08 08:51:05 PM PDT 24
Finished Aug 08 09:45:14 PM PDT 24
Peak memory 610048 kb
Host smart-9543d158-3eeb-4985-a1cb-369348cbe349
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165581849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_
SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rom_e2e_asm_init_prod.2165581849
Directory /workspace/2.rom_e2e_asm_init_prod/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3475715066
Short name T889
Test name
Test status
Simulation time 15611215487 ps
CPU time 3899.59 seconds
Started Aug 08 08:51:47 PM PDT 24
Finished Aug 08 09:56:47 PM PDT 24
Peak memory 610228 kb
Host smart-f62fb943-dec6-4adc-965c-25960e5c0276
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475715066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_e2e_asm_init_prod_end.3475715066
Directory /workspace/2.rom_e2e_asm_init_prod_end/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_rma.380334252
Short name T373
Test name
Test status
Simulation time 14662508393 ps
CPU time 3812.47 seconds
Started Aug 08 08:49:29 PM PDT 24
Finished Aug 08 09:53:02 PM PDT 24
Peak memory 610264 kb
Host smart-39549ff0-fdcb-4299-8c74-b82dd30fabc3
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380334252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rom_e2e_asm_init_rma.380334252
Directory /workspace/2.rom_e2e_asm_init_rma/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2812659609
Short name T1045
Test name
Test status
Simulation time 11340826650 ps
CPU time 2830.03 seconds
Started Aug 08 08:50:34 PM PDT 24
Finished Aug 08 09:37:44 PM PDT 24
Peak memory 610504 kb
Host smart-5b250848-810f-4242-bb92-6071a012fe3d
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812659609 -assert nopostproc +UVM_TESTNAME=chip_base_te
st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.rom_e2e_asm_init_test_unlocked0.2812659609
Directory /workspace/2.rom_e2e_asm_init_test_unlocked0/latest

Test location /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.4036423354
Short name T976
Test name
Test status
Simulation time 14667335504 ps
CPU time 3801.58 seconds
Started Aug 08 08:51:14 PM PDT 24
Finished Aug 08 09:54:37 PM PDT 24
Peak memory 609864 kb
Host smart-a8b8899b-5493-4f0f-bc4f-d44b4dace80c
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid
_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036423354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip
_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in
it_rom_ext_invalid_meas.4036423354
Directory /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2038395272
Short name T911
Test name
Test status
Simulation time 15858374500 ps
CPU time 3472.82 seconds
Started Aug 08 08:50:31 PM PDT 24
Finished Aug 08 09:48:24 PM PDT 24
Peak memory 610028 kb
Host smart-20b97196-afe3-45e9-b9d9-9e087b0c017b
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:
new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038395272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.2038395272
Directory /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.4169276974
Short name T887
Test name
Test status
Simulation time 15059009960 ps
CPU time 4261.66 seconds
Started Aug 08 08:52:08 PM PDT 24
Finished Aug 08 10:03:10 PM PDT 24
Peak memory 609908 kb
Host smart-4ea2eebd-fbf2-4734-af84-66e729ea8e87
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas
:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169276974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext
_no_meas.4169276974
Directory /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location /workspace/coverage/default/2.rom_e2e_self_hash.3531797476
Short name T1005
Test name
Test status
Simulation time 26075457734 ps
CPU time 5549.98 seconds
Started Aug 08 08:49:22 PM PDT 24
Finished Aug 08 10:21:53 PM PDT 24
Peak memory 609916 kb
Host smart-55751509-7497-428c-b9be-6b3a4520b45f
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r
ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531797476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.3531797476
Directory /workspace/2.rom_e2e_self_hash/latest

Test location /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1876313153
Short name T902
Test name
Test status
Simulation time 14657511563 ps
CPU time 2813.54 seconds
Started Aug 08 08:52:48 PM PDT 24
Finished Aug 08 09:39:42 PM PDT 24
Peak memory 611148 kb
Host smart-c521c823-d986-4afd-bb33-5719486eed0b
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne
w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876313153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu
tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_
shutdown_exception_c.1876313153
Directory /workspace/2.rom_e2e_shutdown_exception_c/latest

Test location /workspace/coverage/default/2.rom_e2e_shutdown_output.1816246919
Short name T1074
Test name
Test status
Simulation time 27567684679 ps
CPU time 3253.31 seconds
Started Aug 08 08:51:47 PM PDT 24
Finished Aug 08 09:46:01 PM PDT 24
Peak memory 611412 kb
Host smart-a7936e5b-9e2e-4853-8fe3-4e5104c52aa9
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f
lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816246919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rom_e2e_shutdown_output.1816246919
Directory /workspace/2.rom_e2e_shutdown_output/latest

Test location /workspace/coverage/default/2.rom_e2e_smoke.2706925055
Short name T1153
Test name
Test status
Simulation time 15134786424 ps
CPU time 3358.6 seconds
Started Aug 08 08:53:10 PM PDT 24
Finished Aug 08 09:49:09 PM PDT 24
Peak memory 609968 kb
Host smart-8a7a3b16-1518-46f8-ad69-1caddf419125
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img
_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to
p/hw/dv/tools/sim.tcl +ntb_random_seed=2706925055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.2706925055
Directory /workspace/2.rom_e2e_smoke/latest

Test location /workspace/coverage/default/2.rom_e2e_static_critical.1326120169
Short name T1073
Test name
Test status
Simulation time 16828434316 ps
CPU time 4583.38 seconds
Started Aug 08 08:50:53 PM PDT 24
Finished Aug 08 10:07:18 PM PDT 24
Peak memory 610052 kb
Host smart-64baf65d-9fbf-4fd3-8090-7d4564959e9f
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul
es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326120169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.1326120169
Directory /workspace/2.rom_e2e_static_critical/latest

Test location /workspace/coverage/default/2.rom_keymgr_functest.1605222093
Short name T1047
Test name
Test status
Simulation time 5413755080 ps
CPU time 381.2 seconds
Started Aug 08 08:46:10 PM PDT 24
Finished Aug 08 08:52:31 PM PDT 24
Peak memory 610584 kb
Host smart-bd70360b-60c0-44e7-859e-2761c0d5c646
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605222093 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.1605222093
Directory /workspace/2.rom_keymgr_functest/latest

Test location /workspace/coverage/default/2.rom_raw_unlock.1083213454
Short name T83
Test name
Test status
Simulation time 5984636596 ps
CPU time 237.09 seconds
Started Aug 08 08:47:03 PM PDT 24
Finished Aug 08 08:51:01 PM PDT 24
Peak memory 621788 kb
Host smart-5ebcb8ad-1786-4d37-9672-6b85dc2939b7
User root
Command /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE
xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1083213454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.1083213454
Directory /workspace/2.rom_raw_unlock/latest

Test location /workspace/coverage/default/2.rom_volatile_raw_unlock.2228756016
Short name T1339
Test name
Test status
Simulation time 2575119791 ps
CPU time 119.94 seconds
Started Aug 08 08:47:38 PM PDT 24
Finished Aug 08 08:49:38 PM PDT 24
Peak memory 617616 kb
Host smart-1c6f5ea7-3910-4c4b-b197-821bdc267e66
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1
+sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228756016 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.2228756016
Directory /workspace/2.rom_volatile_raw_unlock/latest

Test location /workspace/coverage/default/20.chip_sw_all_escalation_resets.3077214113
Short name T634
Test name
Test status
Simulation time 5341759992 ps
CPU time 501.29 seconds
Started Aug 08 08:52:43 PM PDT 24
Finished Aug 08 09:01:05 PM PDT 24
Peak memory 610996 kb
Host smart-7aed9166-8a2c-47fd-a9e1-d2e200791f83
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3077214113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.3077214113
Directory /workspace/20.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/22.chip_sw_all_escalation_resets.3935730697
Short name T1253
Test name
Test status
Simulation time 5570443208 ps
CPU time 690.44 seconds
Started Aug 08 08:52:09 PM PDT 24
Finished Aug 08 09:03:40 PM PDT 24
Peak memory 649880 kb
Host smart-7d25b6f8-edf8-420f-b360-ed63c1093192
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3935730697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.3935730697
Directory /workspace/22.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2368787799
Short name T1321
Test name
Test status
Simulation time 3211604446 ps
CPU time 445.91 seconds
Started Aug 08 08:51:53 PM PDT 24
Finished Aug 08 08:59:19 PM PDT 24
Peak memory 649060 kb
Host smart-d7af0dac-7953-4ef6-8cc4-9f0e0992594f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368787799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2368787799
Directory /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3526590425
Short name T750
Test name
Test status
Simulation time 3300688038 ps
CPU time 431.92 seconds
Started Aug 08 08:53:33 PM PDT 24
Finished Aug 08 09:00:46 PM PDT 24
Peak memory 648620 kb
Host smart-3856fe9c-25b6-4809-9648-1fd1870e4b40
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526590425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3526590425
Directory /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/26.chip_sw_all_escalation_resets.2221381367
Short name T686
Test name
Test status
Simulation time 4821436000 ps
CPU time 607.94 seconds
Started Aug 08 08:51:46 PM PDT 24
Finished Aug 08 09:01:55 PM PDT 24
Peak memory 650032 kb
Host smart-e6412ce7-2510-4c37-8e1f-fe8521146a7e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2221381367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.2221381367
Directory /workspace/26.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.717763446
Short name T91
Test name
Test status
Simulation time 4164600658 ps
CPU time 524.56 seconds
Started Aug 08 08:51:50 PM PDT 24
Finished Aug 08 09:00:35 PM PDT 24
Peak memory 648924 kb
Host smart-aa45f46b-8f4e-4bf8-8de4-1f68dc537957
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717763446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_s
w_alert_handler_lpg_sleep_mode_alerts.717763446
Directory /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/28.chip_sw_all_escalation_resets.4209666949
Short name T1252
Test name
Test status
Simulation time 5058486176 ps
CPU time 750.39 seconds
Started Aug 08 08:54:08 PM PDT 24
Finished Aug 08 09:06:39 PM PDT 24
Peak memory 649892 kb
Host smart-b93b3728-2aee-4b7f-80a1-4744ede75550
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4209666949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.4209666949
Directory /workspace/28.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/29.chip_sw_all_escalation_resets.3090805490
Short name T706
Test name
Test status
Simulation time 5023760088 ps
CPU time 561.56 seconds
Started Aug 08 08:53:09 PM PDT 24
Finished Aug 08 09:02:31 PM PDT 24
Peak memory 649568 kb
Host smart-b6107551-0fbf-41b2-b91a-60eeefeb88dd
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3090805490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.3090805490
Directory /workspace/29.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/3.chip_sw_all_escalation_resets.3332681449
Short name T764
Test name
Test status
Simulation time 4862548200 ps
CPU time 612.14 seconds
Started Aug 08 08:46:41 PM PDT 24
Finished Aug 08 08:56:54 PM PDT 24
Peak memory 649784 kb
Host smart-dee3e432-c0e2-48a1-9a68-a838640b89be
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3332681449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.3332681449
Directory /workspace/3.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4070237555
Short name T1225
Test name
Test status
Simulation time 8042511914 ps
CPU time 474.4 seconds
Started Aug 08 08:48:16 PM PDT 24
Finished Aug 08 08:56:11 PM PDT 24
Peak memory 609220 kb
Host smart-c4f10aac-a761-4a94-82c7-fdc6028cc2d9
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4070237555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4070237555
Directory /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/3.chip_sw_data_integrity_escalation.707490123
Short name T249
Test name
Test status
Simulation time 5099187810 ps
CPU time 772.67 seconds
Started Aug 08 08:46:57 PM PDT 24
Finished Aug 08 08:59:50 PM PDT 24
Peak memory 611020 kb
Host smart-5ec499d0-e57d-4fb1-94e7-1e465f607f2e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=707490123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.707490123
Directory /workspace/3.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.4252642304
Short name T1103
Test name
Test status
Simulation time 9086786386 ps
CPU time 924.2 seconds
Started Aug 08 08:46:45 PM PDT 24
Finished Aug 08 09:02:10 PM PDT 24
Peak memory 621136 kb
Host smart-07035a34-ee42-4660-b030-b5e825866a89
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252642304 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.4252642304
Directory /workspace/3.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.625122889
Short name T131
Test name
Test status
Simulation time 4983044418 ps
CPU time 533.97 seconds
Started Aug 08 08:50:26 PM PDT 24
Finished Aug 08 08:59:20 PM PDT 24
Peak memory 608636 kb
Host smart-c3ea62d8-c390-48ab-972f-4e0849c022b3
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62512288
9 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.625122889
Directory /workspace/3.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3120645705
Short name T1001
Test name
Test status
Simulation time 3539573210 ps
CPU time 518.95 seconds
Started Aug 08 08:47:37 PM PDT 24
Finished Aug 08 08:56:16 PM PDT 24
Peak memory 623368 kb
Host smart-25313865-5b4c-4c64-99fa-2049adfba822
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3120645705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.3120645705
Directory /workspace/3.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx.1451690935
Short name T314
Test name
Test status
Simulation time 4184444200 ps
CPU time 475.37 seconds
Started Aug 08 08:49:14 PM PDT 24
Finished Aug 08 08:57:10 PM PDT 24
Peak memory 622156 kb
Host smart-a9afa5bf-cd31-4699-9d37-9901533209a8
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451690935 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.1451690935
Directory /workspace/3.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1172085181
Short name T1319
Test name
Test status
Simulation time 3929942246 ps
CPU time 658.01 seconds
Started Aug 08 08:46:30 PM PDT 24
Finished Aug 08 08:57:29 PM PDT 24
Peak memory 623528 kb
Host smart-8516a3f4-91a7-4995-9476-b479d6f24317
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172085181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx
_alt_clk_freq.1172085181
Directory /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3594930149
Short name T287
Test name
Test status
Simulation time 8578647069 ps
CPU time 1139.14 seconds
Started Aug 08 08:46:55 PM PDT 24
Finished Aug 08 09:05:55 PM PDT 24
Peak memory 619684 kb
Host smart-3ae1b348-3399-4418-a660-ade7175203be
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594930149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.3594930149
Directory /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1726382433
Short name T1179
Test name
Test status
Simulation time 4654289606 ps
CPU time 567.27 seconds
Started Aug 08 08:46:58 PM PDT 24
Finished Aug 08 08:56:26 PM PDT 24
Peak memory 624528 kb
Host smart-ebce370f-6d33-4f9d-9f1c-6b22630d7ab3
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726382433 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.1726382433
Directory /workspace/3.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1645334449
Short name T1320
Test name
Test status
Simulation time 4213427048 ps
CPU time 610.25 seconds
Started Aug 08 08:47:25 PM PDT 24
Finished Aug 08 08:57:36 PM PDT 24
Peak memory 623564 kb
Host smart-bee489ea-07e7-4382-94fd-387272398d33
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645334449 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.1645334449
Directory /workspace/3.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2991612793
Short name T1244
Test name
Test status
Simulation time 4496426820 ps
CPU time 470.37 seconds
Started Aug 08 08:48:35 PM PDT 24
Finished Aug 08 08:56:26 PM PDT 24
Peak memory 622204 kb
Host smart-3cdbcbc1-1982-412a-967a-32554b5ade0f
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991612793 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.2991612793
Directory /workspace/3.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/3.chip_tap_straps_dev.1366248593
Short name T1334
Test name
Test status
Simulation time 17636803572 ps
CPU time 1957.2 seconds
Started Aug 08 08:46:51 PM PDT 24
Finished Aug 08 09:19:29 PM PDT 24
Peak memory 620956 kb
Host smart-0abd610f-c610-475a-9b61-ed6e16c31fa5
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1366248593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.1366248593
Directory /workspace/3.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/3.chip_tap_straps_prod.1108767658
Short name T261
Test name
Test status
Simulation time 2563875307 ps
CPU time 152.12 seconds
Started Aug 08 08:47:01 PM PDT 24
Finished Aug 08 08:49:34 PM PDT 24
Peak memory 623364 kb
Host smart-fdb4ba71-492d-483f-bb0b-e4c426be484c
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1108767658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.1108767658
Directory /workspace/3.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/3.chip_tap_straps_rma.1714690466
Short name T1066
Test name
Test status
Simulation time 3059579844 ps
CPU time 178.37 seconds
Started Aug 08 08:46:03 PM PDT 24
Finished Aug 08 08:49:02 PM PDT 24
Peak memory 623596 kb
Host smart-e2439b34-414c-4fac-9503-e976e10cc959
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714690466 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.1714690466
Directory /workspace/3.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/3.chip_tap_straps_testunlock0.1796612768
Short name T73
Test name
Test status
Simulation time 7115453682 ps
CPU time 761.32 seconds
Started Aug 08 08:46:50 PM PDT 24
Finished Aug 08 08:59:31 PM PDT 24
Peak memory 624500 kb
Host smart-17960046-0d2d-4728-9c18-faa0d1df0deb
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796612768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.1796612768
Directory /workspace/3.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2190416445
Short name T732
Test name
Test status
Simulation time 4688159956 ps
CPU time 405.68 seconds
Started Aug 08 08:52:03 PM PDT 24
Finished Aug 08 08:58:49 PM PDT 24
Peak memory 649288 kb
Host smart-5d4d504b-0881-43e4-915b-51f3aa2f3f38
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190416445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2190416445
Directory /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/30.chip_sw_all_escalation_resets.2061440633
Short name T763
Test name
Test status
Simulation time 5478593270 ps
CPU time 706.98 seconds
Started Aug 08 08:54:17 PM PDT 24
Finished Aug 08 09:06:04 PM PDT 24
Peak memory 649456 kb
Host smart-9429b819-ca37-4e3f-91d0-dd597c492f5e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2061440633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.2061440633
Directory /workspace/30.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2105629130
Short name T687
Test name
Test status
Simulation time 3956734264 ps
CPU time 392.83 seconds
Started Aug 08 08:53:16 PM PDT 24
Finished Aug 08 08:59:49 PM PDT 24
Peak memory 648848 kb
Host smart-c7a23586-b88c-4d27-990e-14cbc9dbbdba
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105629130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2105629130
Directory /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/31.chip_sw_all_escalation_resets.607858336
Short name T753
Test name
Test status
Simulation time 5617503648 ps
CPU time 522.71 seconds
Started Aug 08 08:53:39 PM PDT 24
Finished Aug 08 09:02:22 PM PDT 24
Peak memory 649888 kb
Host smart-19d8e192-b88f-4e38-abd9-b56ab82a100f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
607858336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.607858336
Directory /workspace/31.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2570746397
Short name T749
Test name
Test status
Simulation time 3474097228 ps
CPU time 389.11 seconds
Started Aug 08 08:53:43 PM PDT 24
Finished Aug 08 09:00:12 PM PDT 24
Peak memory 648632 kb
Host smart-4061b69e-3031-46b3-8469-53550ae93280
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570746397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2570746397
Directory /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/32.chip_sw_all_escalation_resets.1341919215
Short name T735
Test name
Test status
Simulation time 4810824492 ps
CPU time 561.3 seconds
Started Aug 08 08:51:50 PM PDT 24
Finished Aug 08 09:01:11 PM PDT 24
Peak memory 649972 kb
Host smart-d8b25aaf-fa32-463c-9c9a-f1920e71512e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1341919215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.1341919215
Directory /workspace/32.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/33.chip_sw_all_escalation_resets.690322650
Short name T758
Test name
Test status
Simulation time 5084349700 ps
CPU time 594.95 seconds
Started Aug 08 08:52:32 PM PDT 24
Finished Aug 08 09:02:27 PM PDT 24
Peak memory 649876 kb
Host smart-2dae6056-8e5d-49e4-a4ea-e66994864c93
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
690322650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.690322650
Directory /workspace/33.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3909747231
Short name T286
Test name
Test status
Simulation time 3830918600 ps
CPU time 464.61 seconds
Started Aug 08 08:52:40 PM PDT 24
Finished Aug 08 09:00:25 PM PDT 24
Peak memory 648700 kb
Host smart-b242854e-3515-480c-8d73-c1a4ab561484
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909747231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3909747231
Directory /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1386694262
Short name T1133
Test name
Test status
Simulation time 4598422552 ps
CPU time 449.91 seconds
Started Aug 08 08:52:45 PM PDT 24
Finished Aug 08 09:00:15 PM PDT 24
Peak memory 648612 kb
Host smart-2495e0d4-3c24-4e43-9aee-36cdd56835ca
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386694262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1386694262
Directory /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/35.chip_sw_all_escalation_resets.51467974
Short name T705
Test name
Test status
Simulation time 5182144692 ps
CPU time 611.78 seconds
Started Aug 08 08:53:12 PM PDT 24
Finished Aug 08 09:03:24 PM PDT 24
Peak memory 649496 kb
Host smart-4f382630-f9e3-405d-a7da-d9778dc18be0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
51467974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.51467974
Directory /workspace/35.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/36.chip_sw_all_escalation_resets.2893769353
Short name T730
Test name
Test status
Simulation time 4597728146 ps
CPU time 502.43 seconds
Started Aug 08 08:52:39 PM PDT 24
Finished Aug 08 09:01:01 PM PDT 24
Peak memory 649904 kb
Host smart-39fca1e9-be8e-4b8a-8442-d7ef5d575e2e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2893769353 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.2893769353
Directory /workspace/36.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1980559149
Short name T756
Test name
Test status
Simulation time 4159221948 ps
CPU time 469 seconds
Started Aug 08 08:53:22 PM PDT 24
Finished Aug 08 09:01:11 PM PDT 24
Peak memory 648576 kb
Host smart-f43c47bf-5fa7-4238-a2c8-1822c1c45878
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980559149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1980559149
Directory /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.984181828
Short name T614
Test name
Test status
Simulation time 3731370136 ps
CPU time 424.99 seconds
Started Aug 08 08:52:45 PM PDT 24
Finished Aug 08 08:59:51 PM PDT 24
Peak memory 649004 kb
Host smart-3b5cfd34-1b38-4f6f-8e9a-363bc0b06861
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984181828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_s
w_alert_handler_lpg_sleep_mode_alerts.984181828
Directory /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/38.chip_sw_all_escalation_resets.4232626080
Short name T694
Test name
Test status
Simulation time 4221033404 ps
CPU time 514.85 seconds
Started Aug 08 08:52:05 PM PDT 24
Finished Aug 08 09:00:40 PM PDT 24
Peak memory 649540 kb
Host smart-192caac4-fa6e-4fa4-8f0d-706c09ef13bc
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4232626080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.4232626080
Directory /workspace/38.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3844121425
Short name T734
Test name
Test status
Simulation time 3983516376 ps
CPU time 386.59 seconds
Started Aug 08 08:52:25 PM PDT 24
Finished Aug 08 08:58:52 PM PDT 24
Peak memory 648768 kb
Host smart-e9c13b23-3bf5-4a6f-b961-e5272b5f68bb
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844121425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3844121425
Directory /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/39.chip_sw_all_escalation_resets.1298925667
Short name T406
Test name
Test status
Simulation time 5824376344 ps
CPU time 693.17 seconds
Started Aug 08 08:53:34 PM PDT 24
Finished Aug 08 09:05:07 PM PDT 24
Peak memory 649876 kb
Host smart-03a9628f-4cd6-4fad-9875-625cb7a905dc
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1298925667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.1298925667
Directory /workspace/39.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.53708607
Short name T102
Test name
Test status
Simulation time 4398628616 ps
CPU time 394.12 seconds
Started Aug 08 08:48:31 PM PDT 24
Finished Aug 08 08:55:05 PM PDT 24
Peak memory 649496 kb
Host smart-5582062a-25a1-4927-9114-ff384be2caf5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53708607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_
escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_
alert_handler_lpg_sleep_mode_alerts.53708607
Directory /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/4.chip_sw_all_escalation_resets.1358962098
Short name T680
Test name
Test status
Simulation time 4802199184 ps
CPU time 596.84 seconds
Started Aug 08 08:47:31 PM PDT 24
Finished Aug 08 08:57:28 PM PDT 24
Peak memory 649864 kb
Host smart-1504a4d0-ab68-40c5-a526-3c41d2789824
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1358962098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.1358962098
Directory /workspace/4.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.4119411648
Short name T863
Test name
Test status
Simulation time 7507334836 ps
CPU time 375.77 seconds
Started Aug 08 08:49:05 PM PDT 24
Finished Aug 08 08:55:21 PM PDT 24
Peak memory 609176 kb
Host smart-51f96ecd-2ae6-44a3-9f25-0eb818317935
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4119411648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.4119411648
Directory /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2511988613
Short name T924
Test name
Test status
Simulation time 18938805104 ps
CPU time 4653.91 seconds
Started Aug 08 08:48:35 PM PDT 24
Finished Aug 08 10:06:09 PM PDT 24
Peak memory 610336 kb
Host smart-0a6ac98a-5553-45ad-ac83-2a9d36765305
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511988613 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.2511988613
Directory /workspace/4.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/4.chip_sw_data_integrity_escalation.3429690980
Short name T247
Test name
Test status
Simulation time 4895317778 ps
CPU time 471.32 seconds
Started Aug 08 08:50:37 PM PDT 24
Finished Aug 08 08:58:29 PM PDT 24
Peak memory 609428 kb
Host smart-df20cc40-10ea-41e1-bf4b-8fc6b0c58cdf
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3429690980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.3429690980
Directory /workspace/4.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3146544345
Short name T1038
Test name
Test status
Simulation time 6040090053 ps
CPU time 522.65 seconds
Started Aug 08 08:47:13 PM PDT 24
Finished Aug 08 08:55:56 PM PDT 24
Peak memory 622440 kb
Host smart-b4e2c9a4-5104-4e42-9c71-b5f3cb178e41
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146544345 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.3146544345
Directory /workspace/4.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3817519866
Short name T140
Test name
Test status
Simulation time 5780723000 ps
CPU time 622.61 seconds
Started Aug 08 08:48:07 PM PDT 24
Finished Aug 08 08:58:30 PM PDT 24
Peak memory 610256 kb
Host smart-4b6e9d19-d8db-46e4-a3d3-06d689c3346e
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38175198
66 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.3817519866
Directory /workspace/4.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3938242157
Short name T1028
Test name
Test status
Simulation time 4546227096 ps
CPU time 661.55 seconds
Started Aug 08 08:49:02 PM PDT 24
Finished Aug 08 09:00:04 PM PDT 24
Peak memory 624548 kb
Host smart-dd8ccc21-cae2-4292-aec5-a179e904fb66
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3938242157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.3938242157
Directory /workspace/4.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx.2197808739
Short name T1078
Test name
Test status
Simulation time 4296909192 ps
CPU time 477.69 seconds
Started Aug 08 08:47:37 PM PDT 24
Finished Aug 08 08:55:35 PM PDT 24
Peak memory 624124 kb
Host smart-3182811c-ce88-412d-b8d1-c4197c08e07a
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197808739 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.2197808739
Directory /workspace/4.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1568664234
Short name T983
Test name
Test status
Simulation time 3684858451 ps
CPU time 609.54 seconds
Started Aug 08 08:47:58 PM PDT 24
Finished Aug 08 08:58:08 PM PDT 24
Peak memory 618772 kb
Host smart-efe6d361-7e27-453d-b0ac-e79d79f599e3
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568664234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx
_alt_clk_freq.1568664234
Directory /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3500430447
Short name T1275
Test name
Test status
Simulation time 4259957431 ps
CPU time 628.18 seconds
Started Aug 08 08:48:58 PM PDT 24
Finished Aug 08 08:59:27 PM PDT 24
Peak memory 623572 kb
Host smart-f6982b26-768a-45d5-8e6e-fac983868c32
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500430447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.3500430447
Directory /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1587757224
Short name T1171
Test name
Test status
Simulation time 4408361918 ps
CPU time 604.19 seconds
Started Aug 08 08:48:24 PM PDT 24
Finished Aug 08 08:58:28 PM PDT 24
Peak memory 623884 kb
Host smart-6df1028b-fa69-46ea-b455-71fb5ec72619
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587757224 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.1587757224
Directory /workspace/4.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1040452552
Short name T315
Test name
Test status
Simulation time 3856613950 ps
CPU time 636.08 seconds
Started Aug 08 08:47:25 PM PDT 24
Finished Aug 08 08:58:01 PM PDT 24
Peak memory 623716 kb
Host smart-dc3f4c00-857d-4a9a-aa74-91dd61117d97
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040452552 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.1040452552
Directory /workspace/4.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.463447196
Short name T304
Test name
Test status
Simulation time 3993357278 ps
CPU time 591.56 seconds
Started Aug 08 08:47:53 PM PDT 24
Finished Aug 08 08:57:45 PM PDT 24
Peak memory 623864 kb
Host smart-ebd9d994-0fa0-4b5a-98c3-dbbbbcba6337
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463447196 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.463447196
Directory /workspace/4.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/4.chip_tap_straps_dev.467201168
Short name T1208
Test name
Test status
Simulation time 4268763040 ps
CPU time 344.85 seconds
Started Aug 08 08:48:16 PM PDT 24
Finished Aug 08 08:54:01 PM PDT 24
Peak memory 621948 kb
Host smart-1991c5da-16fb-4269-9830-32517ac01d8f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=467201168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.467201168
Directory /workspace/4.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/4.chip_tap_straps_prod.3414099091
Short name T874
Test name
Test status
Simulation time 14452100677 ps
CPU time 1321.63 seconds
Started Aug 08 08:48:00 PM PDT 24
Finished Aug 08 09:10:02 PM PDT 24
Peak memory 624496 kb
Host smart-cb8440fa-dea4-4087-bfdd-85f05749239c
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3414099091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.3414099091
Directory /workspace/4.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/4.chip_tap_straps_rma.4285707391
Short name T1174
Test name
Test status
Simulation time 7060825686 ps
CPU time 523.11 seconds
Started Aug 08 08:46:52 PM PDT 24
Finished Aug 08 08:55:36 PM PDT 24
Peak memory 632804 kb
Host smart-c3aa2380-ef5c-4282-b098-6419aeb9b790
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285707391 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.4285707391
Directory /workspace/4.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/4.chip_tap_straps_testunlock0.2977075021
Short name T1322
Test name
Test status
Simulation time 7620431734 ps
CPU time 661.36 seconds
Started Aug 08 08:47:36 PM PDT 24
Finished Aug 08 08:58:37 PM PDT 24
Peak memory 624836 kb
Host smart-28461b96-2ed9-4e38-ae7c-d2f731af7aaa
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977075021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.2977075021
Directory /workspace/4.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/40.chip_sw_all_escalation_resets.1504717382
Short name T693
Test name
Test status
Simulation time 6241172210 ps
CPU time 661.2 seconds
Started Aug 08 08:54:08 PM PDT 24
Finished Aug 08 09:05:10 PM PDT 24
Peak memory 649960 kb
Host smart-8408c7fa-cd81-474a-9112-4c9e3cef11cb
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1504717382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.1504717382
Directory /workspace/40.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3965148425
Short name T736
Test name
Test status
Simulation time 3961582744 ps
CPU time 382.46 seconds
Started Aug 08 08:54:58 PM PDT 24
Finished Aug 08 09:01:21 PM PDT 24
Peak memory 648456 kb
Host smart-79763bf0-f3a0-4650-a58a-871a7fb910ed
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965148425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3965148425
Directory /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1390852149
Short name T294
Test name
Test status
Simulation time 3248817800 ps
CPU time 407.29 seconds
Started Aug 08 08:53:27 PM PDT 24
Finished Aug 08 09:00:14 PM PDT 24
Peak memory 648840 kb
Host smart-cea7fbc8-0579-4763-b089-eee7a1629ccb
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390852149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1390852149
Directory /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/43.chip_sw_all_escalation_resets.3498438479
Short name T238
Test name
Test status
Simulation time 5344664408 ps
CPU time 598.85 seconds
Started Aug 08 08:53:29 PM PDT 24
Finished Aug 08 09:03:28 PM PDT 24
Peak memory 611088 kb
Host smart-906ded5a-c83b-41c9-a1c9-5e1da69628ce
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3498438479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.3498438479
Directory /workspace/43.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2296688920
Short name T100
Test name
Test status
Simulation time 4291832920 ps
CPU time 389.93 seconds
Started Aug 08 08:53:23 PM PDT 24
Finished Aug 08 08:59:54 PM PDT 24
Peak memory 649212 kb
Host smart-cee663fd-0a8f-4951-802d-1c93bb69bf75
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296688920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2296688920
Directory /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/44.chip_sw_all_escalation_resets.858302148
Short name T222
Test name
Test status
Simulation time 5805886952 ps
CPU time 728.89 seconds
Started Aug 08 08:53:24 PM PDT 24
Finished Aug 08 09:05:33 PM PDT 24
Peak memory 650104 kb
Host smart-9bc83289-db81-4a14-b33a-f6846cc7ff46
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
858302148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.858302148
Directory /workspace/44.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/45.chip_sw_all_escalation_resets.3619597362
Short name T754
Test name
Test status
Simulation time 5632668360 ps
CPU time 559.95 seconds
Started Aug 08 08:52:55 PM PDT 24
Finished Aug 08 09:02:15 PM PDT 24
Peak memory 649772 kb
Host smart-0caa8fc1-7c65-4a32-9b25-8d8149d8797d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3619597362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.3619597362
Directory /workspace/45.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.861819183
Short name T741
Test name
Test status
Simulation time 4191209544 ps
CPU time 344.76 seconds
Started Aug 08 08:54:25 PM PDT 24
Finished Aug 08 09:00:10 PM PDT 24
Peak memory 648600 kb
Host smart-dea97fac-a84b-4b52-b280-9cc3003c1603
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861819183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_s
w_alert_handler_lpg_sleep_mode_alerts.861819183
Directory /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.4032492823
Short name T347
Test name
Test status
Simulation time 4048604584 ps
CPU time 564.24 seconds
Started Aug 08 08:54:19 PM PDT 24
Finished Aug 08 09:03:44 PM PDT 24
Peak memory 648712 kb
Host smart-5f9f1581-139a-4e89-877b-b623c61e385d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032492823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4032492823
Directory /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2183852606
Short name T397
Test name
Test status
Simulation time 4086064676 ps
CPU time 425.68 seconds
Started Aug 08 08:54:08 PM PDT 24
Finished Aug 08 09:01:14 PM PDT 24
Peak memory 648680 kb
Host smart-c6cc840f-5ecc-4caa-94a2-9edfa429f9dd
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183852606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2183852606
Directory /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/48.chip_sw_all_escalation_resets.2963319554
Short name T292
Test name
Test status
Simulation time 4130795600 ps
CPU time 479.94 seconds
Started Aug 08 08:53:28 PM PDT 24
Finished Aug 08 09:01:28 PM PDT 24
Peak memory 649756 kb
Host smart-b30054f3-5c11-4018-903a-0312f480729c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2963319554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.2963319554
Directory /workspace/48.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/49.chip_sw_all_escalation_resets.975357971
Short name T715
Test name
Test status
Simulation time 4961410156 ps
CPU time 607.15 seconds
Started Aug 08 08:54:34 PM PDT 24
Finished Aug 08 09:04:42 PM PDT 24
Peak memory 649564 kb
Host smart-56263acb-7cad-40f8-b658-6566a94d3d4b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
975357971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.975357971
Directory /workspace/49.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3051974834
Short name T768
Test name
Test status
Simulation time 3419137200 ps
CPU time 475.56 seconds
Started Aug 08 08:48:05 PM PDT 24
Finished Aug 08 08:56:01 PM PDT 24
Peak memory 648380 kb
Host smart-41bd1ed5-572d-4531-9450-a2fe14c8926f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051974834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s
w_alert_handler_lpg_sleep_mode_alerts.3051974834
Directory /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/5.chip_sw_all_escalation_resets.117929435
Short name T970
Test name
Test status
Simulation time 4459835728 ps
CPU time 498.48 seconds
Started Aug 08 08:48:59 PM PDT 24
Finished Aug 08 08:57:18 PM PDT 24
Peak memory 649912 kb
Host smart-87ab8ff1-84ff-41a8-bac8-bda2e97725f9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
117929435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.117929435
Directory /workspace/5.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2184520568
Short name T1212
Test name
Test status
Simulation time 23575979348 ps
CPU time 4965.8 seconds
Started Aug 08 08:48:46 PM PDT 24
Finished Aug 08 10:11:33 PM PDT 24
Peak memory 610424 kb
Host smart-8d076750-0491-4f04-8e12-232d3a74df83
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184520568 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.2184520568
Directory /workspace/5.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/5.chip_sw_data_integrity_escalation.234693746
Short name T994
Test name
Test status
Simulation time 5656730168 ps
CPU time 817.26 seconds
Started Aug 08 08:48:02 PM PDT 24
Finished Aug 08 09:01:40 PM PDT 24
Peak memory 611072 kb
Host smart-331d9816-f251-47ae-82c7-408d69516dbb
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=234693746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.234693746
Directory /workspace/5.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1039394367
Short name T1030
Test name
Test status
Simulation time 12865914809 ps
CPU time 997 seconds
Started Aug 08 08:49:09 PM PDT 24
Finished Aug 08 09:05:46 PM PDT 24
Peak memory 622452 kb
Host smart-14c5fce7-30f8-4473-abd6-ba6a5c6a5d61
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039394367 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.1039394367
Directory /workspace/5.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2198549894
Short name T1306
Test name
Test status
Simulation time 4648613800 ps
CPU time 630.35 seconds
Started Aug 08 08:49:09 PM PDT 24
Finished Aug 08 08:59:40 PM PDT 24
Peak memory 623344 kb
Host smart-e0116ee7-ff6f-4dcf-b5c8-79817a166a75
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2198549894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.2198549894
Directory /workspace/5.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3289395000
Short name T757
Test name
Test status
Simulation time 3716870288 ps
CPU time 460.45 seconds
Started Aug 08 08:54:05 PM PDT 24
Finished Aug 08 09:01:46 PM PDT 24
Peak memory 648476 kb
Host smart-a3cd9717-95f9-4503-bf60-b38eca9381d8
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289395000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3289395000
Directory /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/50.chip_sw_all_escalation_resets.1782619592
Short name T702
Test name
Test status
Simulation time 5520080426 ps
CPU time 634.27 seconds
Started Aug 08 08:53:17 PM PDT 24
Finished Aug 08 09:03:51 PM PDT 24
Peak memory 619852 kb
Host smart-a3e60046-f905-4cf1-ba33-c3850e02cd77
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1782619592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.1782619592
Directory /workspace/50.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3675972949
Short name T1308
Test name
Test status
Simulation time 3927785046 ps
CPU time 337.91 seconds
Started Aug 08 08:54:03 PM PDT 24
Finished Aug 08 08:59:41 PM PDT 24
Peak memory 648956 kb
Host smart-3fb2b053-db9b-4c9b-a104-1e41d224b460
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675972949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3675972949
Directory /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/51.chip_sw_all_escalation_resets.830733869
Short name T655
Test name
Test status
Simulation time 4315297800 ps
CPU time 587.8 seconds
Started Aug 08 08:54:42 PM PDT 24
Finished Aug 08 09:04:30 PM PDT 24
Peak memory 649788 kb
Host smart-b0207697-7e0a-47b5-bfe3-61cbc90f87e2
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
830733869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.830733869
Directory /workspace/51.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1465088766
Short name T684
Test name
Test status
Simulation time 3836772920 ps
CPU time 464.59 seconds
Started Aug 08 08:53:55 PM PDT 24
Finished Aug 08 09:01:40 PM PDT 24
Peak memory 648740 kb
Host smart-df3ed0f3-9d88-4fe8-87f3-3d164a72b42c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465088766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1465088766
Directory /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3027099658
Short name T1331
Test name
Test status
Simulation time 3158632100 ps
CPU time 492.83 seconds
Started Aug 08 08:53:57 PM PDT 24
Finished Aug 08 09:02:10 PM PDT 24
Peak memory 648708 kb
Host smart-65fbad3d-ae7c-4e86-b523-c88f3412e2b5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027099658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3027099658
Directory /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.297290908
Short name T101
Test name
Test status
Simulation time 3353078568 ps
CPU time 394.08 seconds
Started Aug 08 08:55:51 PM PDT 24
Finished Aug 08 09:02:25 PM PDT 24
Peak memory 649216 kb
Host smart-b9b39f0d-87b2-4222-9039-f65a8d360669
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297290908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_s
w_alert_handler_lpg_sleep_mode_alerts.297290908
Directory /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.4039229074
Short name T713
Test name
Test status
Simulation time 3604166824 ps
CPU time 510.71 seconds
Started Aug 08 08:55:37 PM PDT 24
Finished Aug 08 09:04:08 PM PDT 24
Peak memory 648588 kb
Host smart-dae3f702-cb30-43a0-a5ed-6bf01ccd2e7d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039229074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4039229074
Directory /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2733018194
Short name T226
Test name
Test status
Simulation time 4077000750 ps
CPU time 467.28 seconds
Started Aug 08 08:55:47 PM PDT 24
Finished Aug 08 09:03:35 PM PDT 24
Peak memory 648680 kb
Host smart-ee2a7240-3591-4b3d-a167-edce71743aee
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733018194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2733018194
Directory /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.407928169
Short name T699
Test name
Test status
Simulation time 3024770260 ps
CPU time 398.38 seconds
Started Aug 08 08:55:50 PM PDT 24
Finished Aug 08 09:02:28 PM PDT 24
Peak memory 648700 kb
Host smart-a8a50e2b-948c-4ac8-b01e-61c2defe5d3b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407928169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_s
w_alert_handler_lpg_sleep_mode_alerts.407928169
Directory /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/58.chip_sw_all_escalation_resets.3670874373
Short name T698
Test name
Test status
Simulation time 4295586500 ps
CPU time 464.31 seconds
Started Aug 08 08:55:09 PM PDT 24
Finished Aug 08 09:02:54 PM PDT 24
Peak memory 649844 kb
Host smart-054bc088-a189-44a0-99a5-943aa9713ca8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3670874373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.3670874373
Directory /workspace/58.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/59.chip_sw_all_escalation_resets.3304048892
Short name T1098
Test name
Test status
Simulation time 4863911080 ps
CPU time 484.44 seconds
Started Aug 08 08:54:11 PM PDT 24
Finished Aug 08 09:02:16 PM PDT 24
Peak memory 650260 kb
Host smart-61952065-15f6-401e-bc0d-19790977fd56
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3304048892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.3304048892
Directory /workspace/59.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.817827802
Short name T747
Test name
Test status
Simulation time 4095764496 ps
CPU time 417.89 seconds
Started Aug 08 08:48:16 PM PDT 24
Finished Aug 08 08:55:14 PM PDT 24
Peak memory 648680 kb
Host smart-7e42022e-d3aa-413a-a334-a6c9b2e8fd42
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817827802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw
_alert_handler_lpg_sleep_mode_alerts.817827802
Directory /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/6.chip_sw_all_escalation_resets.2187779017
Short name T738
Test name
Test status
Simulation time 5264214914 ps
CPU time 628.72 seconds
Started Aug 08 08:47:48 PM PDT 24
Finished Aug 08 08:58:17 PM PDT 24
Peak memory 649908 kb
Host smart-8f67dbe2-7358-401d-80cb-230b23f82d30
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2187779017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.2187779017
Directory /workspace/6.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1471666413
Short name T923
Test name
Test status
Simulation time 19099869150 ps
CPU time 4001.03 seconds
Started Aug 08 08:49:15 PM PDT 24
Finished Aug 08 09:55:57 PM PDT 24
Peak memory 609412 kb
Host smart-3897e5c4-617b-433a-887b-7650718e2200
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471666413 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.1471666413
Directory /workspace/6.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.317649807
Short name T1272
Test name
Test status
Simulation time 6825956868 ps
CPU time 578.91 seconds
Started Aug 08 08:48:12 PM PDT 24
Finished Aug 08 08:57:51 PM PDT 24
Peak memory 622496 kb
Host smart-3e290c67-59de-4746-9cd1-3b0d552ce7f8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317649807 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.317649807
Directory /workspace/6.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2138305365
Short name T1303
Test name
Test status
Simulation time 3813814712 ps
CPU time 540.7 seconds
Started Aug 08 08:48:53 PM PDT 24
Finished Aug 08 08:57:55 PM PDT 24
Peak memory 624516 kb
Host smart-cad0ec0c-23f9-42a7-bb9e-ddd732dea7c3
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2138305365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.2138305365
Directory /workspace/6.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.378539888
Short name T742
Test name
Test status
Simulation time 4205346292 ps
CPU time 371.1 seconds
Started Aug 08 08:55:48 PM PDT 24
Finished Aug 08 09:01:59 PM PDT 24
Peak memory 648724 kb
Host smart-ae66e156-30d0-42ab-a6d1-2fd34c257d43
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378539888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_s
w_alert_handler_lpg_sleep_mode_alerts.378539888
Directory /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.716382738
Short name T667
Test name
Test status
Simulation time 4514706360 ps
CPU time 314.05 seconds
Started Aug 08 08:55:42 PM PDT 24
Finished Aug 08 09:00:56 PM PDT 24
Peak memory 648916 kb
Host smart-ae23d950-e672-417e-953a-80f1c7660734
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716382738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_s
w_alert_handler_lpg_sleep_mode_alerts.716382738
Directory /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2406326352
Short name T652
Test name
Test status
Simulation time 4097624568 ps
CPU time 371.19 seconds
Started Aug 08 08:56:13 PM PDT 24
Finished Aug 08 09:02:24 PM PDT 24
Peak memory 648724 kb
Host smart-f9eda711-16d7-4b00-80a6-1aa502cd9683
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406326352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2406326352
Directory /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/62.chip_sw_all_escalation_resets.752266004
Short name T692
Test name
Test status
Simulation time 5525324860 ps
CPU time 635.75 seconds
Started Aug 08 08:55:55 PM PDT 24
Finished Aug 08 09:06:31 PM PDT 24
Peak memory 649900 kb
Host smart-098d8d8a-0143-475b-8e44-36b94286bf75
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
752266004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.752266004
Directory /workspace/62.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/64.chip_sw_all_escalation_resets.2358613841
Short name T762
Test name
Test status
Simulation time 5775832568 ps
CPU time 488.33 seconds
Started Aug 08 08:55:25 PM PDT 24
Finished Aug 08 09:03:33 PM PDT 24
Peak memory 649700 kb
Host smart-5d225658-c92a-4b78-914a-299df9af6c37
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2358613841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.2358613841
Directory /workspace/64.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.756446988
Short name T740
Test name
Test status
Simulation time 3641526800 ps
CPU time 371.32 seconds
Started Aug 08 08:55:30 PM PDT 24
Finished Aug 08 09:01:42 PM PDT 24
Peak memory 648660 kb
Host smart-c0f96ed3-624f-44d7-8b47-efe1926ab689
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756446988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_s
w_alert_handler_lpg_sleep_mode_alerts.756446988
Directory /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/65.chip_sw_all_escalation_resets.1353579185
Short name T239
Test name
Test status
Simulation time 4524751296 ps
CPU time 591.19 seconds
Started Aug 08 08:56:08 PM PDT 24
Finished Aug 08 09:06:00 PM PDT 24
Peak memory 650100 kb
Host smart-6c9a8b9f-64af-4cad-be59-003c11a3eb2b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1353579185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.1353579185
Directory /workspace/65.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/66.chip_sw_all_escalation_resets.790978623
Short name T384
Test name
Test status
Simulation time 5839068008 ps
CPU time 515.36 seconds
Started Aug 08 08:55:52 PM PDT 24
Finished Aug 08 09:04:28 PM PDT 24
Peak memory 650236 kb
Host smart-ac047255-1255-401b-bdb0-36910e4debb9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
790978623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.790978623
Directory /workspace/66.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2166527369
Short name T675
Test name
Test status
Simulation time 4128534616 ps
CPU time 401.13 seconds
Started Aug 08 08:56:46 PM PDT 24
Finished Aug 08 09:03:27 PM PDT 24
Peak memory 648896 kb
Host smart-af6bd207-c1b4-4ec8-923e-c75b573c5231
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166527369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2166527369
Directory /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/67.chip_sw_all_escalation_resets.4002525009
Short name T254
Test name
Test status
Simulation time 5640804684 ps
CPU time 585.32 seconds
Started Aug 08 08:55:38 PM PDT 24
Finished Aug 08 09:05:24 PM PDT 24
Peak memory 649832 kb
Host smart-2e0be66b-90f5-48b8-b4e4-c98ea9d457a4
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4002525009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.4002525009
Directory /workspace/67.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/68.chip_sw_all_escalation_resets.3701325958
Short name T745
Test name
Test status
Simulation time 4854873360 ps
CPU time 560.7 seconds
Started Aug 08 08:56:02 PM PDT 24
Finished Aug 08 09:05:23 PM PDT 24
Peak memory 649936 kb
Host smart-f9472f88-16c4-4011-83c1-10438e8c615f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3701325958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.3701325958
Directory /workspace/68.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4084929547
Short name T661
Test name
Test status
Simulation time 3814913940 ps
CPU time 423.23 seconds
Started Aug 08 08:56:15 PM PDT 24
Finished Aug 08 09:03:19 PM PDT 24
Peak memory 648688 kb
Host smart-72141d5e-3505-427f-bde7-4fa37016831c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084929547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4084929547
Directory /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/69.chip_sw_all_escalation_resets.3031922223
Short name T1162
Test name
Test status
Simulation time 5817910108 ps
CPU time 664.36 seconds
Started Aug 08 08:56:26 PM PDT 24
Finished Aug 08 09:07:31 PM PDT 24
Peak memory 616788 kb
Host smart-79317f27-2921-4342-8c60-7217fd682a3b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3031922223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.3031922223
Directory /workspace/69.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3497219242
Short name T374
Test name
Test status
Simulation time 3380761552 ps
CPU time 296.07 seconds
Started Aug 08 08:49:25 PM PDT 24
Finished Aug 08 08:54:21 PM PDT 24
Peak memory 648916 kb
Host smart-ce97b99c-c77d-466f-8cff-a4d4d9583f9c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497219242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s
w_alert_handler_lpg_sleep_mode_alerts.3497219242
Directory /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/7.chip_sw_all_escalation_resets.449349079
Short name T378
Test name
Test status
Simulation time 4875433944 ps
CPU time 441.51 seconds
Started Aug 08 08:50:10 PM PDT 24
Finished Aug 08 08:57:32 PM PDT 24
Peak memory 650128 kb
Host smart-386992b9-115b-4fc4-9502-933f3ee1ca40
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
449349079 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.449349079
Directory /workspace/7.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.941391246
Short name T1125
Test name
Test status
Simulation time 17221194600 ps
CPU time 4045.25 seconds
Started Aug 08 08:48:42 PM PDT 24
Finished Aug 08 09:56:08 PM PDT 24
Peak memory 610276 kb
Host smart-2b3fe1e0-a261-48b2-a50b-15ed384f12cd
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941391246 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.941391246
Directory /workspace/7.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.4175115789
Short name T1326
Test name
Test status
Simulation time 11035494465 ps
CPU time 748.65 seconds
Started Aug 08 08:48:51 PM PDT 24
Finished Aug 08 09:01:20 PM PDT 24
Peak memory 621180 kb
Host smart-769eaba0-1de6-4055-a27f-5d2b21a12942
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175115789 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.4175115789
Directory /workspace/7.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.4045323605
Short name T965
Test name
Test status
Simulation time 3361571728 ps
CPU time 448.68 seconds
Started Aug 08 08:49:08 PM PDT 24
Finished Aug 08 08:56:37 PM PDT 24
Peak memory 624536 kb
Host smart-e6376788-fe02-465c-b1da-c483212cc2b4
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=4045323605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.4045323605
Directory /workspace/7.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1308658701
Short name T1324
Test name
Test status
Simulation time 3332235620 ps
CPU time 352.02 seconds
Started Aug 08 08:55:06 PM PDT 24
Finished Aug 08 09:00:58 PM PDT 24
Peak memory 648608 kb
Host smart-e6174dc6-a15c-44ab-8220-a5839afd92ab
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308658701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1308658701
Directory /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/70.chip_sw_all_escalation_resets.4224085960
Short name T228
Test name
Test status
Simulation time 4162098400 ps
CPU time 518.4 seconds
Started Aug 08 08:58:01 PM PDT 24
Finished Aug 08 09:06:40 PM PDT 24
Peak memory 649260 kb
Host smart-32cca330-c0e1-4283-bf74-579056fc9639
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4224085960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.4224085960
Directory /workspace/70.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/71.chip_sw_all_escalation_resets.2107411834
Short name T746
Test name
Test status
Simulation time 5766868100 ps
CPU time 546.22 seconds
Started Aug 08 08:55:21 PM PDT 24
Finished Aug 08 09:04:28 PM PDT 24
Peak memory 649880 kb
Host smart-f96ad8bc-42ce-45a2-90d1-25d3f5b9860e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2107411834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.2107411834
Directory /workspace/71.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1400108250
Short name T760
Test name
Test status
Simulation time 3677585424 ps
CPU time 330.32 seconds
Started Aug 08 08:56:25 PM PDT 24
Finished Aug 08 09:01:56 PM PDT 24
Peak memory 648488 kb
Host smart-b33effad-d35a-4693-8e7f-a419da0ddda4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400108250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1400108250
Directory /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3682497061
Short name T708
Test name
Test status
Simulation time 3967083980 ps
CPU time 409.38 seconds
Started Aug 08 08:55:56 PM PDT 24
Finished Aug 08 09:02:45 PM PDT 24
Peak memory 648576 kb
Host smart-c3721a99-45f6-4827-a0ea-4c851bf8b9cb
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682497061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3682497061
Directory /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/74.chip_sw_all_escalation_resets.2874064494
Short name T255
Test name
Test status
Simulation time 5550088536 ps
CPU time 509.13 seconds
Started Aug 08 08:58:22 PM PDT 24
Finished Aug 08 09:06:51 PM PDT 24
Peak memory 649624 kb
Host smart-538b5540-e179-493f-b071-c0652b922d69
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2874064494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.2874064494
Directory /workspace/74.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.5444066
Short name T253
Test name
Test status
Simulation time 3756549620 ps
CPU time 427.84 seconds
Started Aug 08 08:57:08 PM PDT 24
Finished Aug 08 09:04:16 PM PDT 24
Peak memory 648392 kb
Host smart-3bbe1c6a-3404-4ce0-853c-dc46e10b8b53
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5444066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_e
scalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_
alert_handler_lpg_sleep_mode_alerts.5444066
Directory /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/75.chip_sw_all_escalation_resets.508918
Short name T293
Test name
Test status
Simulation time 4384661188 ps
CPU time 555.39 seconds
Started Aug 08 08:55:28 PM PDT 24
Finished Aug 08 09:04:43 PM PDT 24
Peak memory 650060 kb
Host smart-8a69bd84-b1b8-4c52-a148-bde473e5e9dc
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
508918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.508918
Directory /workspace/75.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.36063770
Short name T1256
Test name
Test status
Simulation time 4091455254 ps
CPU time 313.35 seconds
Started Aug 08 08:56:26 PM PDT 24
Finished Aug 08 09:01:40 PM PDT 24
Peak memory 648808 kb
Host smart-a261b77e-1c51-4af3-bd79-8c3f89aa9544
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36063770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_
escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw
_alert_handler_lpg_sleep_mode_alerts.36063770
Directory /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/76.chip_sw_all_escalation_resets.4253539610
Short name T291
Test name
Test status
Simulation time 4676468940 ps
CPU time 622.1 seconds
Started Aug 08 08:56:59 PM PDT 24
Finished Aug 08 09:07:22 PM PDT 24
Peak memory 649716 kb
Host smart-d222d5bf-41e2-45db-b1e4-ddd09a0a0683
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4253539610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.4253539610
Directory /workspace/76.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1906782957
Short name T723
Test name
Test status
Simulation time 3264061010 ps
CPU time 418.55 seconds
Started Aug 08 08:56:23 PM PDT 24
Finished Aug 08 09:03:22 PM PDT 24
Peak memory 648828 kb
Host smart-585c4ca0-c45b-445a-bd71-aaa221c8b147
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906782957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1906782957
Directory /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/77.chip_sw_all_escalation_resets.623743273
Short name T689
Test name
Test status
Simulation time 5637539920 ps
CPU time 641.58 seconds
Started Aug 08 08:57:09 PM PDT 24
Finished Aug 08 09:07:51 PM PDT 24
Peak memory 649504 kb
Host smart-50b28423-26d1-4118-99f1-5bbe713317aa
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
623743273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.623743273
Directory /workspace/77.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/78.chip_sw_all_escalation_resets.3053489225
Short name T221
Test name
Test status
Simulation time 6496766520 ps
CPU time 532.19 seconds
Started Aug 08 08:55:26 PM PDT 24
Finished Aug 08 09:04:18 PM PDT 24
Peak memory 649964 kb
Host smart-87f26b2c-8473-45a9-8dee-dc950c5eba7c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3053489225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.3053489225
Directory /workspace/78.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3874842978
Short name T1323
Test name
Test status
Simulation time 3560965478 ps
CPU time 353.64 seconds
Started Aug 08 08:57:37 PM PDT 24
Finished Aug 08 09:03:31 PM PDT 24
Peak memory 648808 kb
Host smart-00cb25b6-94bc-4964-b949-7e2c8b959633
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874842978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3874842978
Directory /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.997835923
Short name T1265
Test name
Test status
Simulation time 4139107266 ps
CPU time 429.67 seconds
Started Aug 08 08:50:55 PM PDT 24
Finished Aug 08 08:58:05 PM PDT 24
Peak memory 648756 kb
Host smart-73de5d0c-8cad-4c72-bca9-65e49f52e386
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997835923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw
_alert_handler_lpg_sleep_mode_alerts.997835923
Directory /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.4285945130
Short name T933
Test name
Test status
Simulation time 14877611912 ps
CPU time 3187.73 seconds
Started Aug 08 08:49:10 PM PDT 24
Finished Aug 08 09:42:18 PM PDT 24
Peak memory 610400 kb
Host smart-e28c77ac-90a9-48b4-aa00-3864852c9838
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285945130 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.4285945130
Directory /workspace/8.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.4059131038
Short name T860
Test name
Test status
Simulation time 11088106221 ps
CPU time 893.29 seconds
Started Aug 08 08:49:27 PM PDT 24
Finished Aug 08 09:04:20 PM PDT 24
Peak memory 624488 kb
Host smart-228f8dd3-939d-4786-a1af-1b92507851e8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059131038 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.4059131038
Directory /workspace/8.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2841770750
Short name T1106
Test name
Test status
Simulation time 12919137900 ps
CPU time 2586.74 seconds
Started Aug 08 08:48:33 PM PDT 24
Finished Aug 08 09:31:40 PM PDT 24
Peak memory 624528 kb
Host smart-7fb8353c-5365-4ebc-afb5-5a419374bf01
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2841770750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.2841770750
Directory /workspace/8.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.844158137
Short name T727
Test name
Test status
Simulation time 3757234696 ps
CPU time 334.87 seconds
Started Aug 08 08:59:26 PM PDT 24
Finished Aug 08 09:05:01 PM PDT 24
Peak memory 648512 kb
Host smart-be5cb8bb-7a67-4e7d-a97f-1318bd4d99bd
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844158137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_s
w_alert_handler_lpg_sleep_mode_alerts.844158137
Directory /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/80.chip_sw_all_escalation_resets.2514504417
Short name T1337
Test name
Test status
Simulation time 6401649660 ps
CPU time 659.45 seconds
Started Aug 08 08:58:09 PM PDT 24
Finished Aug 08 09:09:09 PM PDT 24
Peak memory 649560 kb
Host smart-0485f9e5-fb21-458a-ae56-d7fc4f94c310
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2514504417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.2514504417
Directory /workspace/80.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3553814356
Short name T104
Test name
Test status
Simulation time 3484373480 ps
CPU time 317.59 seconds
Started Aug 08 08:56:53 PM PDT 24
Finished Aug 08 09:02:10 PM PDT 24
Peak memory 648356 kb
Host smart-5a504f06-c13c-46a0-8bf7-cfe845211b7d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553814356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3553814356
Directory /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/81.chip_sw_all_escalation_resets.3928425117
Short name T399
Test name
Test status
Simulation time 5349283536 ps
CPU time 614.79 seconds
Started Aug 08 08:57:52 PM PDT 24
Finished Aug 08 09:08:07 PM PDT 24
Peak memory 649848 kb
Host smart-9cd970df-d1ef-4dc7-bf6e-ee0fd21c6512
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3928425117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.3928425117
Directory /workspace/81.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.858656540
Short name T707
Test name
Test status
Simulation time 3653853064 ps
CPU time 378.95 seconds
Started Aug 08 08:57:17 PM PDT 24
Finished Aug 08 09:03:36 PM PDT 24
Peak memory 648372 kb
Host smart-78ebbfd4-3335-45ab-87b2-21df45707204
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858656540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_s
w_alert_handler_lpg_sleep_mode_alerts.858656540
Directory /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/82.chip_sw_all_escalation_resets.2502094992
Short name T267
Test name
Test status
Simulation time 4358426692 ps
CPU time 620.19 seconds
Started Aug 08 08:56:51 PM PDT 24
Finished Aug 08 09:07:12 PM PDT 24
Peak memory 650144 kb
Host smart-822964ec-b775-480f-a771-3ab99d03cbc3
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2502094992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.2502094992
Directory /workspace/82.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4072582765
Short name T761
Test name
Test status
Simulation time 3341709072 ps
CPU time 410.04 seconds
Started Aug 08 08:58:07 PM PDT 24
Finished Aug 08 09:04:57 PM PDT 24
Peak memory 648756 kb
Host smart-7396a0bc-de54-4060-a20c-2a4292a95da4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072582765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4072582765
Directory /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/84.chip_sw_all_escalation_resets.2988143920
Short name T346
Test name
Test status
Simulation time 5812237668 ps
CPU time 668.22 seconds
Started Aug 08 08:57:38 PM PDT 24
Finished Aug 08 09:08:46 PM PDT 24
Peak memory 649736 kb
Host smart-efaaf426-225b-4a6b-abdc-f7d65a93a9a0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2988143920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.2988143920
Directory /workspace/84.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1473170800
Short name T99
Test name
Test status
Simulation time 3691716992 ps
CPU time 394.63 seconds
Started Aug 08 08:57:52 PM PDT 24
Finished Aug 08 09:04:27 PM PDT 24
Peak memory 648868 kb
Host smart-82ced3a1-b4c9-429b-bf6d-794e49b771a7
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473170800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1473170800
Directory /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/85.chip_sw_all_escalation_resets.2024493092
Short name T673
Test name
Test status
Simulation time 4381923700 ps
CPU time 552.07 seconds
Started Aug 08 08:57:32 PM PDT 24
Finished Aug 08 09:06:45 PM PDT 24
Peak memory 650168 kb
Host smart-97b88447-04c6-4711-9cd2-2dc8a5892f36
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2024493092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.2024493092
Directory /workspace/85.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/86.chip_sw_all_escalation_resets.329813370
Short name T350
Test name
Test status
Simulation time 5299924958 ps
CPU time 474.37 seconds
Started Aug 08 08:57:33 PM PDT 24
Finished Aug 08 09:05:27 PM PDT 24
Peak memory 649840 kb
Host smart-6ac14e26-3986-40bd-966d-8975465d16b1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
329813370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.329813370
Directory /workspace/86.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3854409923
Short name T765
Test name
Test status
Simulation time 3255305080 ps
CPU time 336.43 seconds
Started Aug 08 08:58:06 PM PDT 24
Finished Aug 08 09:03:43 PM PDT 24
Peak memory 648532 kb
Host smart-aebad19b-4e18-45e4-a1a2-7a24306cab17
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854409923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3854409923
Directory /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/87.chip_sw_all_escalation_resets.3919547089
Short name T1175
Test name
Test status
Simulation time 6450134936 ps
CPU time 645.32 seconds
Started Aug 08 08:57:20 PM PDT 24
Finished Aug 08 09:08:05 PM PDT 24
Peak memory 649948 kb
Host smart-54a94f41-cc22-42e2-a51c-0bdeed1cddec
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3919547089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.3919547089
Directory /workspace/87.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2052196559
Short name T1232
Test name
Test status
Simulation time 3056108856 ps
CPU time 356 seconds
Started Aug 08 08:58:42 PM PDT 24
Finished Aug 08 09:04:38 PM PDT 24
Peak memory 648716 kb
Host smart-0ba2ba8d-aea5-424e-adee-c0b0a21fc76f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052196559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2052196559
Directory /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2290124782
Short name T1169
Test name
Test status
Simulation time 3480913400 ps
CPU time 299.04 seconds
Started Aug 08 08:57:57 PM PDT 24
Finished Aug 08 09:02:56 PM PDT 24
Peak memory 648648 kb
Host smart-7528eb20-0972-496a-bf14-62cf08bd17d3
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290124782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2290124782
Directory /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/89.chip_sw_all_escalation_resets.3093285425
Short name T299
Test name
Test status
Simulation time 4643998580 ps
CPU time 471.78 seconds
Started Aug 08 08:57:57 PM PDT 24
Finished Aug 08 09:05:49 PM PDT 24
Peak memory 650048 kb
Host smart-363bf510-bcc0-45d2-b30c-1979aa81bc9b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3093285425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.3093285425
Directory /workspace/89.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/9.chip_sw_all_escalation_resets.1787369104
Short name T380
Test name
Test status
Simulation time 6369702840 ps
CPU time 920.35 seconds
Started Aug 08 08:49:30 PM PDT 24
Finished Aug 08 09:04:51 PM PDT 24
Peak memory 649848 kb
Host smart-95aa034f-6ddd-49cf-896c-a663ce368df3
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1787369104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.1787369104
Directory /workspace/9.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3268483442
Short name T1081
Test name
Test status
Simulation time 17886160180 ps
CPU time 4197.24 seconds
Started Aug 08 08:50:05 PM PDT 24
Finished Aug 08 10:00:03 PM PDT 24
Peak memory 610352 kb
Host smart-bca09482-61e7-4b11-8046-2119162bd6c8
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r
egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268483442 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.3268483442
Directory /workspace/9.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.522179904
Short name T1111
Test name
Test status
Simulation time 10440892442 ps
CPU time 800.99 seconds
Started Aug 08 08:48:44 PM PDT 24
Finished Aug 08 09:02:06 PM PDT 24
Peak memory 624652 kb
Host smart-3edcc688-f6aa-424b-af2b-2782f516d841
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522179904 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.522179904
Directory /workspace/9.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3798116976
Short name T985
Test name
Test status
Simulation time 4586264440 ps
CPU time 562.32 seconds
Started Aug 08 08:48:18 PM PDT 24
Finished Aug 08 08:57:40 PM PDT 24
Peak memory 624600 kb
Host smart-5110c701-52c0-4708-bc87-2bb4af283316
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3798116976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.3798116976
Directory /workspace/9.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/90.chip_sw_all_escalation_resets.997637024
Short name T696
Test name
Test status
Simulation time 5204090564 ps
CPU time 701.14 seconds
Started Aug 08 08:58:03 PM PDT 24
Finished Aug 08 09:09:44 PM PDT 24
Peak memory 649836 kb
Host smart-ca0355c0-bc07-46e9-b434-a7fe20f449d7
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
997637024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.997637024
Directory /workspace/90.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/92.chip_sw_all_escalation_resets.3115311300
Short name T353
Test name
Test status
Simulation time 5443375292 ps
CPU time 531.15 seconds
Started Aug 08 08:57:40 PM PDT 24
Finished Aug 08 09:06:32 PM PDT 24
Peak memory 649844 kb
Host smart-af105c34-dab0-429e-8698-aeee8a7554ac
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3115311300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.3115311300
Directory /workspace/92.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/93.chip_sw_all_escalation_resets.2647049354
Short name T666
Test name
Test status
Simulation time 6219931930 ps
CPU time 495.16 seconds
Started Aug 08 08:57:41 PM PDT 24
Finished Aug 08 09:05:56 PM PDT 24
Peak memory 649496 kb
Host smart-2e17980b-78df-477f-87c8-fbcc5c3e33e9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2647049354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.2647049354
Directory /workspace/93.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/95.chip_sw_all_escalation_resets.1237878098
Short name T725
Test name
Test status
Simulation time 6086146138 ps
CPU time 575.78 seconds
Started Aug 08 08:59:17 PM PDT 24
Finished Aug 08 09:08:53 PM PDT 24
Peak memory 649944 kb
Host smart-23cd3e5c-fafe-4f16-b4f6-b591870b64db
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1237878098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.1237878098
Directory /workspace/95.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/96.chip_sw_all_escalation_resets.2859837896
Short name T351
Test name
Test status
Simulation time 4523093420 ps
CPU time 457.84 seconds
Started Aug 08 08:57:47 PM PDT 24
Finished Aug 08 09:05:25 PM PDT 24
Peak memory 649572 kb
Host smart-f0b60ef5-3d32-483d-84f4-7e8eeb8c3408
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2859837896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.2859837896
Directory /workspace/96.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/97.chip_sw_all_escalation_resets.75673444
Short name T1219
Test name
Test status
Simulation time 4631252600 ps
CPU time 649.22 seconds
Started Aug 08 08:59:25 PM PDT 24
Finished Aug 08 09:10:14 PM PDT 24
Peak memory 649888 kb
Host smart-caa3f62e-5056-468c-ba6f-9047b2b42fc8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
75673444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.75673444
Directory /workspace/97.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/99.chip_sw_all_escalation_resets.3578826838
Short name T752
Test name
Test status
Simulation time 5348568968 ps
CPU time 556.99 seconds
Started Aug 08 08:58:08 PM PDT 24
Finished Aug 08 09:07:25 PM PDT 24
Peak memory 649844 kb
Host smart-ecf68dad-c024-43fe-a411-f1456f3fabac
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3578826838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.3578826838
Directory /workspace/99.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1793758878
Short name T190
Test name
Test status
Simulation time 4356613992 ps
CPU time 280.43 seconds
Started Aug 08 07:49:50 PM PDT 24
Finished Aug 08 07:54:30 PM PDT 24
Peak memory 657380 kb
Host smart-d069d819-ac2e-4e73-a70a-07e7c4e5b059
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793758878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 1.chip_padctrl_attributes.1793758878
Directory /workspace/1.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1851739404
Short name T32
Test name
Test status
Simulation time 5019645988 ps
CPU time 235.74 seconds
Started Aug 08 07:49:55 PM PDT 24
Finished Aug 08 07:53:51 PM PDT 24
Peak memory 652556 kb
Host smart-045f6637-dc88-4b4d-980e-ed3317c6c408
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851739404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 2.chip_padctrl_attributes.1851739404
Directory /workspace/2.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.4180290392
Short name T194
Test name
Test status
Simulation time 4023199880 ps
CPU time 155.54 seconds
Started Aug 08 07:49:53 PM PDT 24
Finished Aug 08 07:52:28 PM PDT 24
Peak memory 640952 kb
Host smart-63a254bf-463b-4c08-a4e2-68c57cb0b5cd
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180290392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 3.chip_padctrl_attributes.4180290392
Directory /workspace/3.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3408872537
Short name T192
Test name
Test status
Simulation time 5657131496 ps
CPU time 364.4 seconds
Started Aug 08 07:49:49 PM PDT 24
Finished Aug 08 07:55:54 PM PDT 24
Peak memory 655436 kb
Host smart-6d878573-7b77-4b54-bf7e-b65aa84f067f
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408872537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 4.chip_padctrl_attributes.3408872537
Directory /workspace/4.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.4238819953
Short name T196
Test name
Test status
Simulation time 4665639096 ps
CPU time 260.49 seconds
Started Aug 08 07:49:53 PM PDT 24
Finished Aug 08 07:54:14 PM PDT 24
Peak memory 641012 kb
Host smart-0c1e7f19-c269-4685-95c6-294f5b15fc8a
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238819953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 5.chip_padctrl_attributes.4238819953
Directory /workspace/5.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3216452664
Short name T191
Test name
Test status
Simulation time 3958640540 ps
CPU time 207.64 seconds
Started Aug 08 07:49:53 PM PDT 24
Finished Aug 08 07:53:21 PM PDT 24
Peak memory 640960 kb
Host smart-66e6f8bd-de69-4c03-9806-4a357799d60a
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216452664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 6.chip_padctrl_attributes.3216452664
Directory /workspace/6.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3249991543
Short name T197
Test name
Test status
Simulation time 4341118359 ps
CPU time 270.65 seconds
Started Aug 08 07:49:50 PM PDT 24
Finished Aug 08 07:54:21 PM PDT 24
Peak memory 640904 kb
Host smart-7f786eae-4684-4005-b96d-5ec602a765b5
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249991543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 7.chip_padctrl_attributes.3249991543
Directory /workspace/7.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.219820730
Short name T33
Test name
Test status
Simulation time 4376198491 ps
CPU time 205.76 seconds
Started Aug 08 07:49:50 PM PDT 24
Finished Aug 08 07:53:16 PM PDT 24
Peak memory 657340 kb
Host smart-d134f6bd-d072-4d9f-aaf8-8b077eee99a5
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219820730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n
ull -cm_name 8.chip_padctrl_attributes.219820730
Directory /workspace/8.chip_padctrl_attributes/latest
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