Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.22	99.72	97.17			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.22	99.72	97.17			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.22	99.72	97.17			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.22	99.72	97.17			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.22	99.72	97.17			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.22	99.72	97.17			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.68	96.99	84.51			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.22	99.72	97.17			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T60,T366,T152

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T366,T152
1	1	Covered	T60,T366,T152

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T60,T366,T152

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T60,T366,T152
1	1	Covered	T60,T366,T152

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T60,T366,T152
0	0	1	Covered	T60,T366,T152
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T60,T366,T152
0	0	1	Covered	T60,T366,T152
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152985238	91788	0	0
DstReqKnown_A	1876721	1651694	0	0
SrcAckBusyChk_A	152985238	237	0	0
SrcBusyKnown_A	152985238	152165392	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	91788	0	0
T14	19368	0	0	0
T60	443985	281	0	0
T129	68453	0	0	0
T152	0	7025	0	0
T153	0	343	0	0
T154	0	743	0	0
T168	101111	0	0	0
T226	26349	0	0	0
T307	51742	0	0	0
T363	0	3097	0	0
T366	0	611	0	0
T378	0	631	0	0
T384	0	287	0	0
T385	0	882	0	0
T386	58759	0	0	0
T387	132994	0	0	0
T388	43522	0	0	0
T389	224322	0	0	0
T390	0	293	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1876721	1651694	0	0
T1	546	374	0	0
T2	631	457	0	0
T3	663	492	0	0
T4	761	586	0	0
T5	730	558	0	0
T15	558	386	0	0
T34	454	279	0	0
T48	2946	2773	0	0
T54	486	314	0	0
T90	734	560	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	237	0	0
T14	19368	0	0	0
T60	443985	1	0	0
T129	68453	0	0	0
T152	0	18	0	0
T153	0	1	0	0
T154	0	2	0	0
T168	101111	0	0	0
T226	26349	0	0	0
T307	51742	0	0	0
T363	0	8	0	0
T366	0	2	0	0
T378	0	2	0	0
T384	0	1	0	0
T385	0	2	0	0
T386	58759	0	0	0
T387	132994	0	0	0
T388	43522	0	0	0
T389	224322	0	0	0
T390	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	152165392	0	0
T1	36935	36460	0	0
T2	37550	37229	0	0
T3	56765	56181	0	0
T4	54526	53829	0	0
T5	59342	58859	0	0
T15	46804	45940	0	0
T34	29313	28317	0	0
T48	323925	323530	0	0
T54	28974	28520	0	0
T90	59555	59057	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T60,T366,T152

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T366,T152
1	1	Covered	T60,T366,T152

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T60,T366,T152

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T60,T366,T152
1	1	Covered	T60,T366,T152

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T60,T366,T152
0	0	1	Covered	T60,T366,T152
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T60,T366,T152
0	0	1	Covered	T60,T366,T152
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152985238	107541	0	0
DstReqKnown_A	1876721	1651694	0	0
SrcAckBusyChk_A	152985238	275	0	0
SrcBusyKnown_A	152985238	152165392	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	107541	0	0
T14	19368	0	0	0
T60	443985	257	0	0
T129	68453	0	0	0
T152	0	5489	0	0
T153	0	317	0	0
T154	0	719	0	0
T168	101111	0	0	0
T226	26349	0	0	0
T307	51742	0	0	0
T363	0	5386	0	0
T366	0	612	0	0
T378	0	673	0	0
T384	0	290	0	0
T385	0	821	0	0
T386	58759	0	0	0
T387	132994	0	0	0
T388	43522	0	0	0
T389	224322	0	0	0
T390	0	285	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1876721	1651694	0	0
T1	546	374	0	0
T2	631	457	0	0
T3	663	492	0	0
T4	761	586	0	0
T5	730	558	0	0
T15	558	386	0	0
T34	454	279	0	0
T48	2946	2773	0	0
T54	486	314	0	0
T90	734	560	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	275	0	0
T14	19368	0	0	0
T60	443985	1	0	0
T129	68453	0	0	0
T152	0	14	0	0
T153	0	1	0	0
T154	0	2	0	0
T168	101111	0	0	0
T226	26349	0	0	0
T307	51742	0	0	0
T363	0	14	0	0
T366	0	2	0	0
T378	0	2	0	0
T384	0	1	0	0
T385	0	2	0	0
T386	58759	0	0	0
T387	132994	0	0	0
T388	43522	0	0	0
T389	224322	0	0	0
T390	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	152165392	0	0
T1	36935	36460	0	0
T2	37550	37229	0	0
T3	56765	56181	0	0
T4	54526	53829	0	0
T5	59342	58859	0	0
T15	46804	45940	0	0
T34	29313	28317	0	0
T48	323925	323530	0	0
T54	28974	28520	0	0
T90	59555	59057	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T60,T366,T152

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T366,T152
1	1	Covered	T60,T366,T152

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T60,T366,T152

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T60,T366,T152
1	1	Covered	T60,T366,T152

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T60,T366,T152
0	0	1	Covered	T60,T366,T152
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T60,T366,T152
0	0	1	Covered	T60,T366,T152
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152985238	92904	0	0
DstReqKnown_A	1876721	1651694	0	0
SrcAckBusyChk_A	152985238	239	0	0
SrcBusyKnown_A	152985238	152165392	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	92904	0	0
T14	19368	0	0	0
T60	443985	274	0	0
T129	68453	0	0	0
T152	0	4585	0	0
T153	0	288	0	0
T154	0	782	0	0
T168	101111	0	0	0
T226	26349	0	0	0
T307	51742	0	0	0
T363	0	1840	0	0
T366	0	633	0	0
T378	0	795	0	0
T384	0	270	0	0
T385	0	853	0	0
T386	58759	0	0	0
T387	132994	0	0	0
T388	43522	0	0	0
T389	224322	0	0	0
T390	0	277	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1876721	1651694	0	0
T1	546	374	0	0
T2	631	457	0	0
T3	663	492	0	0
T4	761	586	0	0
T5	730	558	0	0
T15	558	386	0	0
T34	454	279	0	0
T48	2946	2773	0	0
T54	486	314	0	0
T90	734	560	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	239	0	0
T14	19368	0	0	0
T60	443985	1	0	0
T129	68453	0	0	0
T152	0	12	0	0
T153	0	1	0	0
T154	0	2	0	0
T168	101111	0	0	0
T226	26349	0	0	0
T307	51742	0	0	0
T363	0	5	0	0
T366	0	2	0	0
T378	0	2	0	0
T384	0	1	0	0
T385	0	2	0	0
T386	58759	0	0	0
T387	132994	0	0	0
T388	43522	0	0	0
T389	224322	0	0	0
T390	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	152165392	0	0
T1	36935	36460	0	0
T2	37550	37229	0	0
T3	56765	56181	0	0
T4	54526	53829	0	0
T5	59342	58859	0	0
T15	46804	45940	0	0
T34	29313	28317	0	0
T48	323925	323530	0	0
T54	28974	28520	0	0
T90	59555	59057	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T60,T366,T152

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T366,T152
1	1	Covered	T60,T366,T152

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T60,T366,T152

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T60,T366,T152
1	1	Covered	T60,T366,T152

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T60,T366,T152
0	0	1	Covered	T60,T366,T152
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T60,T366,T152
0	0	1	Covered	T60,T366,T152
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152985238	107818	0	0
DstReqKnown_A	1876721	1651694	0	0
SrcAckBusyChk_A	152985238	277	0	0
SrcBusyKnown_A	152985238	152165392	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	107818	0	0
T14	19368	0	0	0
T60	443985	292	0	0
T129	68453	0	0	0
T152	0	5132	0	0
T153	0	280	0	0
T154	0	703	0	0
T168	101111	0	0	0
T226	26349	0	0	0
T307	51742	0	0	0
T363	0	5587	0	0
T366	0	594	0	0
T378	0	718	0	0
T384	0	298	0	0
T385	0	842	0	0
T386	58759	0	0	0
T387	132994	0	0	0
T388	43522	0	0	0
T389	224322	0	0	0
T390	0	290	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1876721	1651694	0	0
T1	546	374	0	0
T2	631	457	0	0
T3	663	492	0	0
T4	761	586	0	0
T5	730	558	0	0
T15	558	386	0	0
T34	454	279	0	0
T48	2946	2773	0	0
T54	486	314	0	0
T90	734	560	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	277	0	0
T14	19368	0	0	0
T60	443985	1	0	0
T129	68453	0	0	0
T152	0	13	0	0
T153	0	1	0	0
T154	0	2	0	0
T168	101111	0	0	0
T226	26349	0	0	0
T307	51742	0	0	0
T363	0	15	0	0
T366	0	2	0	0
T378	0	2	0	0
T384	0	1	0	0
T385	0	2	0	0
T386	58759	0	0	0
T387	132994	0	0	0
T388	43522	0	0	0
T389	224322	0	0	0
T390	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	152165392	0	0
T1	36935	36460	0	0
T2	37550	37229	0	0
T3	56765	56181	0	0
T4	54526	53829	0	0
T5	59342	58859	0	0
T15	46804	45940	0	0
T34	29313	28317	0	0
T48	323925	323530	0	0
T54	28974	28520	0	0
T90	59555	59057	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T60,T366,T152

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T366,T152
1	1	Covered	T60,T366,T152

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T60,T366,T152

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T60,T366,T152
1	1	Covered	T60,T366,T152

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T60,T366,T152
0	0	1	Covered	T60,T366,T152
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T60,T366,T152
0	0	1	Covered	T60,T366,T152
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152985238	85262	0	0
DstReqKnown_A	1876721	1651694	0	0
SrcAckBusyChk_A	152985238	219	0	0
SrcBusyKnown_A	152985238	152165392	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	85262	0	0
T14	19368	0	0	0
T60	443985	331	0	0
T129	68453	0	0	0
T152	0	1950	0	0
T153	0	361	0	0
T154	0	724	0	0
T168	101111	0	0	0
T226	26349	0	0	0
T307	51742	0	0	0
T363	0	2649	0	0
T366	0	596	0	0
T378	0	792	0	0
T384	0	319	0	0
T385	0	918	0	0
T386	58759	0	0	0
T387	132994	0	0	0
T388	43522	0	0	0
T389	224322	0	0	0
T390	0	298	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1876721	1651694	0	0
T1	546	374	0	0
T2	631	457	0	0
T3	663	492	0	0
T4	761	586	0	0
T5	730	558	0	0
T15	558	386	0	0
T34	454	279	0	0
T48	2946	2773	0	0
T54	486	314	0	0
T90	734	560	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	219	0	0
T14	19368	0	0	0
T60	443985	1	0	0
T129	68453	0	0	0
T152	0	5	0	0
T153	0	1	0	0
T154	0	2	0	0
T168	101111	0	0	0
T226	26349	0	0	0
T307	51742	0	0	0
T363	0	7	0	0
T366	0	2	0	0
T378	0	2	0	0
T384	0	1	0	0
T385	0	2	0	0
T386	58759	0	0	0
T387	132994	0	0	0
T388	43522	0	0	0
T389	224322	0	0	0
T390	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	152165392	0	0
T1	36935	36460	0	0
T2	37550	37229	0	0
T3	56765	56181	0	0
T4	54526	53829	0	0
T5	59342	58859	0	0
T15	46804	45940	0	0
T34	29313	28317	0	0
T48	323925	323530	0	0
T54	28974	28520	0	0
T90	59555	59057	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T60,T366,T152

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T366,T152
1	1	Covered	T60,T366,T152

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T60,T366,T152

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T60,T366,T152
1	1	Covered	T60,T366,T152

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T60,T366,T152
0	0	1	Covered	T60,T366,T152
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T60,T366,T152
0	0	1	Covered	T60,T366,T152
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152985238	87462	0	0
DstReqKnown_A	1876721	1651694	0	0
SrcAckBusyChk_A	152985238	225	0	0
SrcBusyKnown_A	152985238	152165392	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	87462	0	0
T14	19368	0	0	0
T60	443985	346	0	0
T129	68453	0	0	0
T152	0	3149	0	0
T153	0	273	0	0
T154	0	762	0	0
T168	101111	0	0	0
T226	26349	0	0	0
T307	51742	0	0	0
T363	0	1451	0	0
T366	0	620	0	0
T378	0	776	0	0
T384	0	244	0	0
T385	0	810	0	0
T386	58759	0	0	0
T387	132994	0	0	0
T388	43522	0	0	0
T389	224322	0	0	0
T390	0	296	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1876721	1651694	0	0
T1	546	374	0	0
T2	631	457	0	0
T3	663	492	0	0
T4	761	586	0	0
T5	730	558	0	0
T15	558	386	0	0
T34	454	279	0	0
T48	2946	2773	0	0
T54	486	314	0	0
T90	734	560	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	225	0	0
T14	19368	0	0	0
T60	443985	1	0	0
T129	68453	0	0	0
T152	0	8	0	0
T153	0	1	0	0
T154	0	2	0	0
T168	101111	0	0	0
T226	26349	0	0	0
T307	51742	0	0	0
T363	0	4	0	0
T366	0	2	0	0
T378	0	2	0	0
T384	0	1	0	0
T385	0	2	0	0
T386	58759	0	0	0
T387	132994	0	0	0
T388	43522	0	0	0
T389	224322	0	0	0
T390	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	152165392	0	0
T1	36935	36460	0	0
T2	37550	37229	0	0
T3	56765	56181	0	0
T4	54526	53829	0	0
T5	59342	58859	0	0
T15	46804	45940	0	0
T34	29313	28317	0	0
T48	323925	323530	0	0
T54	28974	28520	0	0
T90	59555	59057	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T57,T20,T60

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T57,T20,T60
1	1	Covered	T57,T20,T60

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T57,T20,T63
1	0	Covered	T57,T20,T60

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T57,T20,T60
1	1	Covered	T57,T20,T60

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T57,T20,T63

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T57,T20,T60
0	0	1	Covered	T57,T20,T60
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T57,T20,T60
0	0	1	Covered	T57,T20,T60
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152985238	122719	0	0
DstReqKnown_A	1876721	1651694	0	0
SrcAckBusyChk_A	152985238	278	0	0
SrcBusyKnown_A	152985238	152165392	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	122719	0	0
T20	0	676	0	0
T21	0	1366	0	0
T28	0	1143	0	0
T57	36343	941	0	0
T58	0	1643	0	0
T60	0	246	0	0
T61	0	946	0	0
T62	0	943	0	0
T75	295397	0	0	0
T78	0	765	0	0
T104	0	649	0	0
T105	88141	0	0	0
T106	240960	0	0	0
T107	53910	0	0	0
T108	23414	0	0	0
T109	22655	0	0	0
T110	56971	0	0	0
T111	55690	0	0	0
T112	23773	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1876721	1651694	0	0
T1	546	374	0	0
T2	631	457	0	0
T3	663	492	0	0
T4	761	586	0	0
T5	730	558	0	0
T15	558	386	0	0
T34	454	279	0	0
T48	2946	2773	0	0
T54	486	314	0	0
T90	734	560	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	278	0	0
T20	0	2	0	0
T21	0	4	0	0
T28	0	2	0	0
T57	36343	3	0	0
T58	0	4	0	0
T60	0	1	0	0
T61	0	3	0	0
T62	0	3	0	0
T75	295397	0	0	0
T78	0	2	0	0
T104	0	2	0	0
T105	88141	0	0	0
T106	240960	0	0	0
T107	53910	0	0	0
T108	23414	0	0	0
T109	22655	0	0	0
T110	56971	0	0	0
T111	55690	0	0	0
T112	23773	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152985238	152165392	0	0
T1	36935	36460	0	0
T2	37550	37229	0	0
T3	56765	56181	0	0
T4	54526	53829	0	0
T5	59342	58859	0	0
T15	46804	45940	0	0
T34	29313	28317	0	0
T48	323925	323530	0	0
T54	28974	28520	0	0
T90	59555	59057	0	0